1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/etherdevice.h> 17 #include <linux/crc32.h> 18 #include <linux/firmware.h> 19 #include <linux/utsname.h> 20 #include <linux/time.h> 21 #include "bnxt_hsi.h" 22 #include "bnxt.h" 23 #include "bnxt_xdp.h" 24 #include "bnxt_ethtool.h" 25 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 26 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 27 #include "bnxt_coredump.h" 28 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 29 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 30 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 32 static u32 bnxt_get_msglevel(struct net_device *dev) 33 { 34 struct bnxt *bp = netdev_priv(dev); 35 36 return bp->msg_enable; 37 } 38 39 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 40 { 41 struct bnxt *bp = netdev_priv(dev); 42 43 bp->msg_enable = value; 44 } 45 46 static int bnxt_get_coalesce(struct net_device *dev, 47 struct ethtool_coalesce *coal) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 struct bnxt_coal *hw_coal; 51 u16 mult; 52 53 memset(coal, 0, sizeof(*coal)); 54 55 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 56 57 hw_coal = &bp->rx_coal; 58 mult = hw_coal->bufs_per_record; 59 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 60 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 61 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 62 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 63 64 hw_coal = &bp->tx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 71 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 72 73 return 0; 74 } 75 76 static int bnxt_set_coalesce(struct net_device *dev, 77 struct ethtool_coalesce *coal) 78 { 79 struct bnxt *bp = netdev_priv(dev); 80 bool update_stats = false; 81 struct bnxt_coal *hw_coal; 82 int rc = 0; 83 u16 mult; 84 85 if (coal->use_adaptive_rx_coalesce) { 86 bp->flags |= BNXT_FLAG_DIM; 87 } else { 88 if (bp->flags & BNXT_FLAG_DIM) { 89 bp->flags &= ~(BNXT_FLAG_DIM); 90 goto reset_coalesce; 91 } 92 } 93 94 hw_coal = &bp->rx_coal; 95 mult = hw_coal->bufs_per_record; 96 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 97 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 98 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 99 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 100 101 hw_coal = &bp->tx_coal; 102 mult = hw_coal->bufs_per_record; 103 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 104 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 105 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 106 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 107 108 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 109 u32 stats_ticks = coal->stats_block_coalesce_usecs; 110 111 /* Allow 0, which means disable. */ 112 if (stats_ticks) 113 stats_ticks = clamp_t(u32, stats_ticks, 114 BNXT_MIN_STATS_COAL_TICKS, 115 BNXT_MAX_STATS_COAL_TICKS); 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 117 bp->stats_coal_ticks = stats_ticks; 118 if (bp->stats_coal_ticks) 119 bp->current_interval = 120 bp->stats_coal_ticks * HZ / 1000000; 121 else 122 bp->current_interval = BNXT_TIMER_INTERVAL; 123 update_stats = true; 124 } 125 126 reset_coalesce: 127 if (netif_running(dev)) { 128 if (update_stats) { 129 rc = bnxt_close_nic(bp, true, false); 130 if (!rc) 131 rc = bnxt_open_nic(bp, true, false); 132 } else { 133 rc = bnxt_hwrm_set_coal(bp); 134 } 135 } 136 137 return rc; 138 } 139 140 static const char * const bnxt_ring_rx_stats_str[] = { 141 "rx_ucast_packets", 142 "rx_mcast_packets", 143 "rx_bcast_packets", 144 "rx_discards", 145 "rx_drops", 146 "rx_ucast_bytes", 147 "rx_mcast_bytes", 148 "rx_bcast_bytes", 149 }; 150 151 static const char * const bnxt_ring_tx_stats_str[] = { 152 "tx_ucast_packets", 153 "tx_mcast_packets", 154 "tx_bcast_packets", 155 "tx_discards", 156 "tx_drops", 157 "tx_ucast_bytes", 158 "tx_mcast_bytes", 159 "tx_bcast_bytes", 160 }; 161 162 static const char * const bnxt_ring_tpa_stats_str[] = { 163 "tpa_packets", 164 "tpa_bytes", 165 "tpa_events", 166 "tpa_aborts", 167 }; 168 169 static const char * const bnxt_ring_tpa2_stats_str[] = { 170 "rx_tpa_eligible_pkt", 171 "rx_tpa_eligible_bytes", 172 "rx_tpa_pkt", 173 "rx_tpa_bytes", 174 "rx_tpa_errors", 175 }; 176 177 static const char * const bnxt_rx_sw_stats_str[] = { 178 "rx_l4_csum_errors", 179 "rx_buf_errors", 180 }; 181 182 static const char * const bnxt_cmn_sw_stats_str[] = { 183 "missed_irqs", 184 }; 185 186 #define BNXT_RX_STATS_ENTRY(counter) \ 187 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 188 189 #define BNXT_TX_STATS_ENTRY(counter) \ 190 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 191 192 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 193 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 194 195 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 196 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 197 198 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 199 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 200 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 201 202 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 203 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 204 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 205 206 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 207 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 208 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 209 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 210 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 211 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 212 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 213 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 214 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 215 216 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 217 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 218 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 219 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 220 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 221 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 222 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 223 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 224 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 225 226 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 227 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 228 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 229 230 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 231 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 232 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 233 234 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 235 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 236 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 237 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 238 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 239 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 240 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 241 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 242 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 243 244 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 245 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 246 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 247 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 248 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 249 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 250 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 251 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 252 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 253 254 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 255 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 256 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 257 258 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 259 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 260 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 261 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 267 268 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 269 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 270 __stringify(counter##_pri##n) } 271 272 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 273 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 274 __stringify(counter##_pri##n) } 275 276 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 277 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 278 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 279 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 280 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 281 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 282 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 283 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 284 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 285 286 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 287 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 288 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 289 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 290 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 291 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 292 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 293 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 294 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 295 296 #define BNXT_PCIE_STATS_ENTRY(counter) \ 297 { BNXT_PCIE_STATS_OFFSET(counter), __stringify(counter) } 298 299 enum { 300 RX_TOTAL_DISCARDS, 301 TX_TOTAL_DISCARDS, 302 }; 303 304 static struct { 305 u64 counter; 306 char string[ETH_GSTRING_LEN]; 307 } bnxt_sw_func_stats[] = { 308 {0, "rx_total_discard_pkts"}, 309 {0, "tx_total_discard_pkts"}, 310 }; 311 312 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 313 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 314 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 315 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 316 317 static const struct { 318 long offset; 319 char string[ETH_GSTRING_LEN]; 320 } bnxt_port_stats_arr[] = { 321 BNXT_RX_STATS_ENTRY(rx_64b_frames), 322 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 323 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 324 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 325 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 326 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 327 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 328 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 329 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 330 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 331 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 332 BNXT_RX_STATS_ENTRY(rx_total_frames), 333 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 334 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 335 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 336 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 337 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 338 BNXT_RX_STATS_ENTRY(rx_pause_frames), 339 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 340 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 341 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 342 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 343 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 344 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 345 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 346 BNXT_RX_STATS_ENTRY(rx_good_frames), 347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 354 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 355 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 357 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 358 BNXT_RX_STATS_ENTRY(rx_bytes), 359 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 360 BNXT_RX_STATS_ENTRY(rx_runt_frames), 361 BNXT_RX_STATS_ENTRY(rx_stat_discard), 362 BNXT_RX_STATS_ENTRY(rx_stat_err), 363 364 BNXT_TX_STATS_ENTRY(tx_64b_frames), 365 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 366 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 367 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 368 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 369 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 370 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 371 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 372 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 373 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 374 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 375 BNXT_TX_STATS_ENTRY(tx_good_frames), 376 BNXT_TX_STATS_ENTRY(tx_total_frames), 377 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 378 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 379 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 380 BNXT_TX_STATS_ENTRY(tx_pause_frames), 381 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 382 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 383 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 384 BNXT_TX_STATS_ENTRY(tx_err), 385 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 393 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 395 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 396 BNXT_TX_STATS_ENTRY(tx_total_collisions), 397 BNXT_TX_STATS_ENTRY(tx_bytes), 398 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 399 BNXT_TX_STATS_ENTRY(tx_stat_discard), 400 BNXT_TX_STATS_ENTRY(tx_stat_error), 401 }; 402 403 static const struct { 404 long offset; 405 char string[ETH_GSTRING_LEN]; 406 } bnxt_port_stats_ext_arr[] = { 407 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 408 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 409 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 410 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 411 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 412 BNXT_RX_STATS_EXT_COS_ENTRIES, 413 BNXT_RX_STATS_EXT_PFC_ENTRIES, 414 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 415 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 416 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 417 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 418 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 419 }; 420 421 static const struct { 422 long offset; 423 char string[ETH_GSTRING_LEN]; 424 } bnxt_tx_port_stats_ext_arr[] = { 425 BNXT_TX_STATS_EXT_COS_ENTRIES, 426 BNXT_TX_STATS_EXT_PFC_ENTRIES, 427 }; 428 429 static const struct { 430 long base_off; 431 char string[ETH_GSTRING_LEN]; 432 } bnxt_rx_bytes_pri_arr[] = { 433 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 434 }; 435 436 static const struct { 437 long base_off; 438 char string[ETH_GSTRING_LEN]; 439 } bnxt_rx_pkts_pri_arr[] = { 440 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 441 }; 442 443 static const struct { 444 long base_off; 445 char string[ETH_GSTRING_LEN]; 446 } bnxt_tx_bytes_pri_arr[] = { 447 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 448 }; 449 450 static const struct { 451 long base_off; 452 char string[ETH_GSTRING_LEN]; 453 } bnxt_tx_pkts_pri_arr[] = { 454 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 455 }; 456 457 static const struct { 458 long offset; 459 char string[ETH_GSTRING_LEN]; 460 } bnxt_pcie_stats_arr[] = { 461 BNXT_PCIE_STATS_ENTRY(pcie_pl_signal_integrity), 462 BNXT_PCIE_STATS_ENTRY(pcie_dl_signal_integrity), 463 BNXT_PCIE_STATS_ENTRY(pcie_tl_signal_integrity), 464 BNXT_PCIE_STATS_ENTRY(pcie_link_integrity), 465 BNXT_PCIE_STATS_ENTRY(pcie_tx_traffic_rate), 466 BNXT_PCIE_STATS_ENTRY(pcie_rx_traffic_rate), 467 BNXT_PCIE_STATS_ENTRY(pcie_tx_dllp_statistics), 468 BNXT_PCIE_STATS_ENTRY(pcie_rx_dllp_statistics), 469 BNXT_PCIE_STATS_ENTRY(pcie_equalization_time), 470 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[0]), 471 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[2]), 472 BNXT_PCIE_STATS_ENTRY(pcie_recovery_histogram), 473 }; 474 475 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 476 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 477 #define BNXT_NUM_STATS_PRI \ 478 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 479 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 480 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 481 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 482 #define BNXT_NUM_PCIE_STATS ARRAY_SIZE(bnxt_pcie_stats_arr) 483 484 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 485 { 486 if (BNXT_SUPPORTS_TPA(bp)) { 487 if (bp->max_tpa_v2) 488 return ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 489 return ARRAY_SIZE(bnxt_ring_tpa_stats_str); 490 } 491 return 0; 492 } 493 494 static int bnxt_get_num_ring_stats(struct bnxt *bp) 495 { 496 int rx, tx, cmn; 497 bool sh = false; 498 499 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 500 sh = true; 501 502 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 503 bnxt_get_num_tpa_ring_stats(bp); 504 tx = NUM_RING_TX_HW_STATS; 505 cmn = NUM_RING_CMN_SW_STATS; 506 if (sh) 507 return (rx + tx + cmn) * bp->cp_nr_rings; 508 else 509 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 510 cmn * bp->cp_nr_rings; 511 } 512 513 static int bnxt_get_num_stats(struct bnxt *bp) 514 { 515 int num_stats = bnxt_get_num_ring_stats(bp); 516 517 num_stats += BNXT_NUM_SW_FUNC_STATS; 518 519 if (bp->flags & BNXT_FLAG_PORT_STATS) 520 num_stats += BNXT_NUM_PORT_STATS; 521 522 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 523 num_stats += bp->fw_rx_stats_ext_size + 524 bp->fw_tx_stats_ext_size; 525 if (bp->pri2cos_valid) 526 num_stats += BNXT_NUM_STATS_PRI; 527 } 528 529 if (bp->flags & BNXT_FLAG_PCIE_STATS) 530 num_stats += BNXT_NUM_PCIE_STATS; 531 532 return num_stats; 533 } 534 535 static int bnxt_get_sset_count(struct net_device *dev, int sset) 536 { 537 struct bnxt *bp = netdev_priv(dev); 538 539 switch (sset) { 540 case ETH_SS_STATS: 541 return bnxt_get_num_stats(bp); 542 case ETH_SS_TEST: 543 if (!bp->num_tests) 544 return -EOPNOTSUPP; 545 return bp->num_tests; 546 default: 547 return -EOPNOTSUPP; 548 } 549 } 550 551 static bool is_rx_ring(struct bnxt *bp, int ring_num) 552 { 553 return ring_num < bp->rx_nr_rings; 554 } 555 556 static bool is_tx_ring(struct bnxt *bp, int ring_num) 557 { 558 int tx_base = 0; 559 560 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 561 tx_base = bp->rx_nr_rings; 562 563 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 564 return true; 565 return false; 566 } 567 568 static void bnxt_get_ethtool_stats(struct net_device *dev, 569 struct ethtool_stats *stats, u64 *buf) 570 { 571 u32 i, j = 0; 572 struct bnxt *bp = netdev_priv(dev); 573 u32 tpa_stats; 574 575 if (!bp->bnapi) { 576 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 577 goto skip_ring_stats; 578 } 579 580 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 581 bnxt_sw_func_stats[i].counter = 0; 582 583 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 584 for (i = 0; i < bp->cp_nr_rings; i++) { 585 struct bnxt_napi *bnapi = bp->bnapi[i]; 586 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 587 __le64 *hw_stats = (__le64 *)cpr->hw_stats; 588 u64 *sw; 589 int k; 590 591 if (is_rx_ring(bp, i)) { 592 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 593 buf[j] = le64_to_cpu(hw_stats[k]); 594 } 595 if (is_tx_ring(bp, i)) { 596 k = NUM_RING_RX_HW_STATS; 597 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 598 j++, k++) 599 buf[j] = le64_to_cpu(hw_stats[k]); 600 } 601 if (!tpa_stats || !is_rx_ring(bp, i)) 602 goto skip_tpa_ring_stats; 603 604 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 605 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 606 tpa_stats; j++, k++) 607 buf[j] = le64_to_cpu(hw_stats[k]); 608 609 skip_tpa_ring_stats: 610 sw = (u64 *)&cpr->sw_stats.rx; 611 if (is_rx_ring(bp, i)) { 612 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 613 buf[j] = sw[k]; 614 } 615 616 sw = (u64 *)&cpr->sw_stats.cmn; 617 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 618 buf[j] = sw[k]; 619 620 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 621 le64_to_cpu(cpr->hw_stats->rx_discard_pkts); 622 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 623 le64_to_cpu(cpr->hw_stats->tx_discard_pkts); 624 } 625 626 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 627 buf[j] = bnxt_sw_func_stats[i].counter; 628 629 skip_ring_stats: 630 if (bp->flags & BNXT_FLAG_PORT_STATS) { 631 __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats; 632 633 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) { 634 buf[j] = le64_to_cpu(*(port_stats + 635 bnxt_port_stats_arr[i].offset)); 636 } 637 } 638 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 639 __le64 *rx_port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext; 640 __le64 *tx_port_stats_ext = (__le64 *)bp->hw_tx_port_stats_ext; 641 642 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 643 buf[j] = le64_to_cpu(*(rx_port_stats_ext + 644 bnxt_port_stats_ext_arr[i].offset)); 645 } 646 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 647 buf[j] = le64_to_cpu(*(tx_port_stats_ext + 648 bnxt_tx_port_stats_ext_arr[i].offset)); 649 } 650 if (bp->pri2cos_valid) { 651 for (i = 0; i < 8; i++, j++) { 652 long n = bnxt_rx_bytes_pri_arr[i].base_off + 653 bp->pri2cos_idx[i]; 654 655 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 656 } 657 for (i = 0; i < 8; i++, j++) { 658 long n = bnxt_rx_pkts_pri_arr[i].base_off + 659 bp->pri2cos_idx[i]; 660 661 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 662 } 663 for (i = 0; i < 8; i++, j++) { 664 long n = bnxt_tx_bytes_pri_arr[i].base_off + 665 bp->pri2cos_idx[i]; 666 667 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 668 } 669 for (i = 0; i < 8; i++, j++) { 670 long n = bnxt_tx_pkts_pri_arr[i].base_off + 671 bp->pri2cos_idx[i]; 672 673 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 674 } 675 } 676 } 677 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 678 __le64 *pcie_stats = (__le64 *)bp->hw_pcie_stats; 679 680 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++, j++) { 681 buf[j] = le64_to_cpu(*(pcie_stats + 682 bnxt_pcie_stats_arr[i].offset)); 683 } 684 } 685 } 686 687 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 688 { 689 struct bnxt *bp = netdev_priv(dev); 690 static const char * const *str; 691 u32 i, j, num_str; 692 693 switch (stringset) { 694 case ETH_SS_STATS: 695 for (i = 0; i < bp->cp_nr_rings; i++) { 696 if (is_rx_ring(bp, i)) { 697 num_str = NUM_RING_RX_HW_STATS; 698 for (j = 0; j < num_str; j++) { 699 sprintf(buf, "[%d]: %s", i, 700 bnxt_ring_rx_stats_str[j]); 701 buf += ETH_GSTRING_LEN; 702 } 703 } 704 if (is_tx_ring(bp, i)) { 705 num_str = NUM_RING_TX_HW_STATS; 706 for (j = 0; j < num_str; j++) { 707 sprintf(buf, "[%d]: %s", i, 708 bnxt_ring_tx_stats_str[j]); 709 buf += ETH_GSTRING_LEN; 710 } 711 } 712 num_str = bnxt_get_num_tpa_ring_stats(bp); 713 if (!num_str || !is_rx_ring(bp, i)) 714 goto skip_tpa_stats; 715 716 if (bp->max_tpa_v2) 717 str = bnxt_ring_tpa2_stats_str; 718 else 719 str = bnxt_ring_tpa_stats_str; 720 721 for (j = 0; j < num_str; j++) { 722 sprintf(buf, "[%d]: %s", i, str[j]); 723 buf += ETH_GSTRING_LEN; 724 } 725 skip_tpa_stats: 726 if (is_rx_ring(bp, i)) { 727 num_str = NUM_RING_RX_SW_STATS; 728 for (j = 0; j < num_str; j++) { 729 sprintf(buf, "[%d]: %s", i, 730 bnxt_rx_sw_stats_str[j]); 731 buf += ETH_GSTRING_LEN; 732 } 733 } 734 num_str = NUM_RING_CMN_SW_STATS; 735 for (j = 0; j < num_str; j++) { 736 sprintf(buf, "[%d]: %s", i, 737 bnxt_cmn_sw_stats_str[j]); 738 buf += ETH_GSTRING_LEN; 739 } 740 } 741 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 742 strcpy(buf, bnxt_sw_func_stats[i].string); 743 buf += ETH_GSTRING_LEN; 744 } 745 746 if (bp->flags & BNXT_FLAG_PORT_STATS) { 747 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 748 strcpy(buf, bnxt_port_stats_arr[i].string); 749 buf += ETH_GSTRING_LEN; 750 } 751 } 752 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 753 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 754 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 755 buf += ETH_GSTRING_LEN; 756 } 757 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 758 strcpy(buf, 759 bnxt_tx_port_stats_ext_arr[i].string); 760 buf += ETH_GSTRING_LEN; 761 } 762 if (bp->pri2cos_valid) { 763 for (i = 0; i < 8; i++) { 764 strcpy(buf, 765 bnxt_rx_bytes_pri_arr[i].string); 766 buf += ETH_GSTRING_LEN; 767 } 768 for (i = 0; i < 8; i++) { 769 strcpy(buf, 770 bnxt_rx_pkts_pri_arr[i].string); 771 buf += ETH_GSTRING_LEN; 772 } 773 for (i = 0; i < 8; i++) { 774 strcpy(buf, 775 bnxt_tx_bytes_pri_arr[i].string); 776 buf += ETH_GSTRING_LEN; 777 } 778 for (i = 0; i < 8; i++) { 779 strcpy(buf, 780 bnxt_tx_pkts_pri_arr[i].string); 781 buf += ETH_GSTRING_LEN; 782 } 783 } 784 } 785 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 786 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++) { 787 strcpy(buf, bnxt_pcie_stats_arr[i].string); 788 buf += ETH_GSTRING_LEN; 789 } 790 } 791 break; 792 case ETH_SS_TEST: 793 if (bp->num_tests) 794 memcpy(buf, bp->test_info->string, 795 bp->num_tests * ETH_GSTRING_LEN); 796 break; 797 default: 798 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 799 stringset); 800 break; 801 } 802 } 803 804 static void bnxt_get_ringparam(struct net_device *dev, 805 struct ethtool_ringparam *ering) 806 { 807 struct bnxt *bp = netdev_priv(dev); 808 809 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 810 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 811 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 812 813 ering->rx_pending = bp->rx_ring_size; 814 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 815 ering->tx_pending = bp->tx_ring_size; 816 } 817 818 static int bnxt_set_ringparam(struct net_device *dev, 819 struct ethtool_ringparam *ering) 820 { 821 struct bnxt *bp = netdev_priv(dev); 822 823 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 824 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 825 (ering->tx_pending <= MAX_SKB_FRAGS)) 826 return -EINVAL; 827 828 if (netif_running(dev)) 829 bnxt_close_nic(bp, false, false); 830 831 bp->rx_ring_size = ering->rx_pending; 832 bp->tx_ring_size = ering->tx_pending; 833 bnxt_set_ring_params(bp); 834 835 if (netif_running(dev)) 836 return bnxt_open_nic(bp, false, false); 837 838 return 0; 839 } 840 841 static void bnxt_get_channels(struct net_device *dev, 842 struct ethtool_channels *channel) 843 { 844 struct bnxt *bp = netdev_priv(dev); 845 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 846 int max_rx_rings, max_tx_rings, tcs; 847 int max_tx_sch_inputs; 848 849 /* Get the most up-to-date max_tx_sch_inputs. */ 850 if (BNXT_NEW_RM(bp)) 851 bnxt_hwrm_func_resc_qcaps(bp, false); 852 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 853 854 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 855 if (max_tx_sch_inputs) 856 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 857 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 858 859 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 860 max_rx_rings = 0; 861 max_tx_rings = 0; 862 } 863 if (max_tx_sch_inputs) 864 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 865 866 tcs = netdev_get_num_tc(dev); 867 if (tcs > 1) 868 max_tx_rings /= tcs; 869 870 channel->max_rx = max_rx_rings; 871 channel->max_tx = max_tx_rings; 872 channel->max_other = 0; 873 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 874 channel->combined_count = bp->rx_nr_rings; 875 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 876 channel->combined_count--; 877 } else { 878 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 879 channel->rx_count = bp->rx_nr_rings; 880 channel->tx_count = bp->tx_nr_rings_per_tc; 881 } 882 } 883 } 884 885 static int bnxt_set_channels(struct net_device *dev, 886 struct ethtool_channels *channel) 887 { 888 struct bnxt *bp = netdev_priv(dev); 889 int req_tx_rings, req_rx_rings, tcs; 890 bool sh = false; 891 int tx_xdp = 0; 892 int rc = 0; 893 894 if (channel->other_count) 895 return -EINVAL; 896 897 if (!channel->combined_count && 898 (!channel->rx_count || !channel->tx_count)) 899 return -EINVAL; 900 901 if (channel->combined_count && 902 (channel->rx_count || channel->tx_count)) 903 return -EINVAL; 904 905 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 906 channel->tx_count)) 907 return -EINVAL; 908 909 if (channel->combined_count) 910 sh = true; 911 912 tcs = netdev_get_num_tc(dev); 913 914 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 915 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 916 if (bp->tx_nr_rings_xdp) { 917 if (!sh) { 918 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 919 return -EINVAL; 920 } 921 tx_xdp = req_rx_rings; 922 } 923 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 924 if (rc) { 925 netdev_warn(dev, "Unable to allocate the requested rings\n"); 926 return rc; 927 } 928 929 if (netif_running(dev)) { 930 if (BNXT_PF(bp)) { 931 /* TODO CHIMP_FW: Send message to all VF's 932 * before PF unload 933 */ 934 } 935 rc = bnxt_close_nic(bp, true, false); 936 if (rc) { 937 netdev_err(bp->dev, "Set channel failure rc :%x\n", 938 rc); 939 return rc; 940 } 941 } 942 943 if (sh) { 944 bp->flags |= BNXT_FLAG_SHARED_RINGS; 945 bp->rx_nr_rings = channel->combined_count; 946 bp->tx_nr_rings_per_tc = channel->combined_count; 947 } else { 948 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 949 bp->rx_nr_rings = channel->rx_count; 950 bp->tx_nr_rings_per_tc = channel->tx_count; 951 } 952 bp->tx_nr_rings_xdp = tx_xdp; 953 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 954 if (tcs > 1) 955 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 956 957 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 958 bp->tx_nr_rings + bp->rx_nr_rings; 959 960 /* After changing number of rx channels, update NTUPLE feature. */ 961 netdev_update_features(dev); 962 if (netif_running(dev)) { 963 rc = bnxt_open_nic(bp, true, false); 964 if ((!rc) && BNXT_PF(bp)) { 965 /* TODO CHIMP_FW: Send message to all VF's 966 * to renable 967 */ 968 } 969 } else { 970 rc = bnxt_reserve_rings(bp, true); 971 } 972 973 return rc; 974 } 975 976 #ifdef CONFIG_RFS_ACCEL 977 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 978 u32 *rule_locs) 979 { 980 int i, j = 0; 981 982 cmd->data = bp->ntp_fltr_count; 983 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 984 struct hlist_head *head; 985 struct bnxt_ntuple_filter *fltr; 986 987 head = &bp->ntp_fltr_hash_tbl[i]; 988 rcu_read_lock(); 989 hlist_for_each_entry_rcu(fltr, head, hash) { 990 if (j == cmd->rule_cnt) 991 break; 992 rule_locs[j++] = fltr->sw_id; 993 } 994 rcu_read_unlock(); 995 if (j == cmd->rule_cnt) 996 break; 997 } 998 cmd->rule_cnt = j; 999 return 0; 1000 } 1001 1002 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1003 { 1004 struct ethtool_rx_flow_spec *fs = 1005 (struct ethtool_rx_flow_spec *)&cmd->fs; 1006 struct bnxt_ntuple_filter *fltr; 1007 struct flow_keys *fkeys; 1008 int i, rc = -EINVAL; 1009 1010 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1011 return rc; 1012 1013 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1014 struct hlist_head *head; 1015 1016 head = &bp->ntp_fltr_hash_tbl[i]; 1017 rcu_read_lock(); 1018 hlist_for_each_entry_rcu(fltr, head, hash) { 1019 if (fltr->sw_id == fs->location) 1020 goto fltr_found; 1021 } 1022 rcu_read_unlock(); 1023 } 1024 return rc; 1025 1026 fltr_found: 1027 fkeys = &fltr->fkeys; 1028 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1029 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1030 fs->flow_type = TCP_V4_FLOW; 1031 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1032 fs->flow_type = UDP_V4_FLOW; 1033 else 1034 goto fltr_err; 1035 1036 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1037 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1038 1039 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1040 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1041 1042 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1043 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1044 1045 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1046 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1047 } else { 1048 int i; 1049 1050 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1051 fs->flow_type = TCP_V6_FLOW; 1052 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1053 fs->flow_type = UDP_V6_FLOW; 1054 else 1055 goto fltr_err; 1056 1057 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1058 fkeys->addrs.v6addrs.src; 1059 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1060 fkeys->addrs.v6addrs.dst; 1061 for (i = 0; i < 4; i++) { 1062 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1063 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1064 } 1065 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1066 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1067 1068 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1069 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1070 } 1071 1072 fs->ring_cookie = fltr->rxq; 1073 rc = 0; 1074 1075 fltr_err: 1076 rcu_read_unlock(); 1077 1078 return rc; 1079 } 1080 #endif 1081 1082 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1083 { 1084 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1085 return RXH_IP_SRC | RXH_IP_DST; 1086 return 0; 1087 } 1088 1089 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1090 { 1091 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1092 return RXH_IP_SRC | RXH_IP_DST; 1093 return 0; 1094 } 1095 1096 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1097 { 1098 cmd->data = 0; 1099 switch (cmd->flow_type) { 1100 case TCP_V4_FLOW: 1101 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1102 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1103 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1104 cmd->data |= get_ethtool_ipv4_rss(bp); 1105 break; 1106 case UDP_V4_FLOW: 1107 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1108 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1109 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1110 /* fall through */ 1111 case SCTP_V4_FLOW: 1112 case AH_ESP_V4_FLOW: 1113 case AH_V4_FLOW: 1114 case ESP_V4_FLOW: 1115 case IPV4_FLOW: 1116 cmd->data |= get_ethtool_ipv4_rss(bp); 1117 break; 1118 1119 case TCP_V6_FLOW: 1120 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1121 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1122 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1123 cmd->data |= get_ethtool_ipv6_rss(bp); 1124 break; 1125 case UDP_V6_FLOW: 1126 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1127 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1128 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1129 /* fall through */ 1130 case SCTP_V6_FLOW: 1131 case AH_ESP_V6_FLOW: 1132 case AH_V6_FLOW: 1133 case ESP_V6_FLOW: 1134 case IPV6_FLOW: 1135 cmd->data |= get_ethtool_ipv6_rss(bp); 1136 break; 1137 } 1138 return 0; 1139 } 1140 1141 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1142 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1143 1144 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1145 { 1146 u32 rss_hash_cfg = bp->rss_hash_cfg; 1147 int tuple, rc = 0; 1148 1149 if (cmd->data == RXH_4TUPLE) 1150 tuple = 4; 1151 else if (cmd->data == RXH_2TUPLE) 1152 tuple = 2; 1153 else if (!cmd->data) 1154 tuple = 0; 1155 else 1156 return -EINVAL; 1157 1158 if (cmd->flow_type == TCP_V4_FLOW) { 1159 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1160 if (tuple == 4) 1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1162 } else if (cmd->flow_type == UDP_V4_FLOW) { 1163 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1164 return -EINVAL; 1165 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1166 if (tuple == 4) 1167 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1168 } else if (cmd->flow_type == TCP_V6_FLOW) { 1169 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1170 if (tuple == 4) 1171 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1172 } else if (cmd->flow_type == UDP_V6_FLOW) { 1173 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1174 return -EINVAL; 1175 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1176 if (tuple == 4) 1177 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1178 } else if (tuple == 4) { 1179 return -EINVAL; 1180 } 1181 1182 switch (cmd->flow_type) { 1183 case TCP_V4_FLOW: 1184 case UDP_V4_FLOW: 1185 case SCTP_V4_FLOW: 1186 case AH_ESP_V4_FLOW: 1187 case AH_V4_FLOW: 1188 case ESP_V4_FLOW: 1189 case IPV4_FLOW: 1190 if (tuple == 2) 1191 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1192 else if (!tuple) 1193 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1194 break; 1195 1196 case TCP_V6_FLOW: 1197 case UDP_V6_FLOW: 1198 case SCTP_V6_FLOW: 1199 case AH_ESP_V6_FLOW: 1200 case AH_V6_FLOW: 1201 case ESP_V6_FLOW: 1202 case IPV6_FLOW: 1203 if (tuple == 2) 1204 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1205 else if (!tuple) 1206 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1207 break; 1208 } 1209 1210 if (bp->rss_hash_cfg == rss_hash_cfg) 1211 return 0; 1212 1213 bp->rss_hash_cfg = rss_hash_cfg; 1214 if (netif_running(bp->dev)) { 1215 bnxt_close_nic(bp, false, false); 1216 rc = bnxt_open_nic(bp, false, false); 1217 } 1218 return rc; 1219 } 1220 1221 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1222 u32 *rule_locs) 1223 { 1224 struct bnxt *bp = netdev_priv(dev); 1225 int rc = 0; 1226 1227 switch (cmd->cmd) { 1228 #ifdef CONFIG_RFS_ACCEL 1229 case ETHTOOL_GRXRINGS: 1230 cmd->data = bp->rx_nr_rings; 1231 break; 1232 1233 case ETHTOOL_GRXCLSRLCNT: 1234 cmd->rule_cnt = bp->ntp_fltr_count; 1235 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1236 break; 1237 1238 case ETHTOOL_GRXCLSRLALL: 1239 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1240 break; 1241 1242 case ETHTOOL_GRXCLSRULE: 1243 rc = bnxt_grxclsrule(bp, cmd); 1244 break; 1245 #endif 1246 1247 case ETHTOOL_GRXFH: 1248 rc = bnxt_grxfh(bp, cmd); 1249 break; 1250 1251 default: 1252 rc = -EOPNOTSUPP; 1253 break; 1254 } 1255 1256 return rc; 1257 } 1258 1259 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1260 { 1261 struct bnxt *bp = netdev_priv(dev); 1262 int rc; 1263 1264 switch (cmd->cmd) { 1265 case ETHTOOL_SRXFH: 1266 rc = bnxt_srxfh(bp, cmd); 1267 break; 1268 1269 default: 1270 rc = -EOPNOTSUPP; 1271 break; 1272 } 1273 return rc; 1274 } 1275 1276 static u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1277 { 1278 return HW_HASH_INDEX_SIZE; 1279 } 1280 1281 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1282 { 1283 return HW_HASH_KEY_SIZE; 1284 } 1285 1286 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1287 u8 *hfunc) 1288 { 1289 struct bnxt *bp = netdev_priv(dev); 1290 struct bnxt_vnic_info *vnic; 1291 int i = 0; 1292 1293 if (hfunc) 1294 *hfunc = ETH_RSS_HASH_TOP; 1295 1296 if (!bp->vnic_info) 1297 return 0; 1298 1299 vnic = &bp->vnic_info[0]; 1300 if (indir && vnic->rss_table) { 1301 for (i = 0; i < HW_HASH_INDEX_SIZE; i++) 1302 indir[i] = le16_to_cpu(vnic->rss_table[i]); 1303 } 1304 1305 if (key && vnic->rss_hash_key) 1306 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1307 1308 return 0; 1309 } 1310 1311 static void bnxt_get_drvinfo(struct net_device *dev, 1312 struct ethtool_drvinfo *info) 1313 { 1314 struct bnxt *bp = netdev_priv(dev); 1315 1316 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1317 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1318 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1319 info->n_stats = bnxt_get_num_stats(bp); 1320 info->testinfo_len = bp->num_tests; 1321 /* TODO CHIMP_FW: eeprom dump details */ 1322 info->eedump_len = 0; 1323 /* TODO CHIMP FW: reg dump details */ 1324 info->regdump_len = 0; 1325 } 1326 1327 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1328 { 1329 struct bnxt *bp = netdev_priv(dev); 1330 1331 wol->supported = 0; 1332 wol->wolopts = 0; 1333 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1334 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1335 wol->supported = WAKE_MAGIC; 1336 if (bp->wol) 1337 wol->wolopts = WAKE_MAGIC; 1338 } 1339 } 1340 1341 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1342 { 1343 struct bnxt *bp = netdev_priv(dev); 1344 1345 if (wol->wolopts & ~WAKE_MAGIC) 1346 return -EINVAL; 1347 1348 if (wol->wolopts & WAKE_MAGIC) { 1349 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1350 return -EINVAL; 1351 if (!bp->wol) { 1352 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1353 return -EBUSY; 1354 bp->wol = 1; 1355 } 1356 } else { 1357 if (bp->wol) { 1358 if (bnxt_hwrm_free_wol_fltr(bp)) 1359 return -EBUSY; 1360 bp->wol = 0; 1361 } 1362 } 1363 return 0; 1364 } 1365 1366 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1367 { 1368 u32 speed_mask = 0; 1369 1370 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1371 /* set the advertised speeds */ 1372 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1373 speed_mask |= ADVERTISED_100baseT_Full; 1374 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1375 speed_mask |= ADVERTISED_1000baseT_Full; 1376 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1377 speed_mask |= ADVERTISED_2500baseX_Full; 1378 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1379 speed_mask |= ADVERTISED_10000baseT_Full; 1380 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1381 speed_mask |= ADVERTISED_40000baseCR4_Full; 1382 1383 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1384 speed_mask |= ADVERTISED_Pause; 1385 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1386 speed_mask |= ADVERTISED_Asym_Pause; 1387 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1388 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1389 1390 return speed_mask; 1391 } 1392 1393 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1394 { \ 1395 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1396 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1397 100baseT_Full); \ 1398 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1399 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1400 1000baseT_Full); \ 1401 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1402 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1403 10000baseT_Full); \ 1404 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1405 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1406 25000baseCR_Full); \ 1407 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1408 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1409 40000baseCR4_Full);\ 1410 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1411 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1412 50000baseCR2_Full);\ 1413 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1414 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1415 100000baseCR4_Full);\ 1416 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1417 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1418 Pause); \ 1419 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1420 ethtool_link_ksettings_add_link_mode( \ 1421 lk_ksettings, name, Asym_Pause);\ 1422 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1423 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1424 Asym_Pause); \ 1425 } \ 1426 } 1427 1428 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1429 { \ 1430 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1431 100baseT_Full) || \ 1432 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1433 100baseT_Half)) \ 1434 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1435 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1436 1000baseT_Full) || \ 1437 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1438 1000baseT_Half)) \ 1439 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1440 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1441 10000baseT_Full)) \ 1442 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1443 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1444 25000baseCR_Full)) \ 1445 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1446 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1447 40000baseCR4_Full)) \ 1448 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1449 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1450 50000baseCR2_Full)) \ 1451 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1452 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1453 100000baseCR4_Full)) \ 1454 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1455 } 1456 1457 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1458 struct ethtool_link_ksettings *lk_ksettings) 1459 { 1460 u16 fw_speeds = link_info->advertising; 1461 u8 fw_pause = 0; 1462 1463 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1464 fw_pause = link_info->auto_pause_setting; 1465 1466 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1467 } 1468 1469 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1470 struct ethtool_link_ksettings *lk_ksettings) 1471 { 1472 u16 fw_speeds = link_info->lp_auto_link_speeds; 1473 u8 fw_pause = 0; 1474 1475 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1476 fw_pause = link_info->lp_pause; 1477 1478 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1479 lp_advertising); 1480 } 1481 1482 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1483 struct ethtool_link_ksettings *lk_ksettings) 1484 { 1485 u16 fw_speeds = link_info->support_speeds; 1486 1487 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1488 1489 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1490 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1491 Asym_Pause); 1492 1493 if (link_info->support_auto_speeds) 1494 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1495 Autoneg); 1496 } 1497 1498 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1499 { 1500 switch (fw_link_speed) { 1501 case BNXT_LINK_SPEED_100MB: 1502 return SPEED_100; 1503 case BNXT_LINK_SPEED_1GB: 1504 return SPEED_1000; 1505 case BNXT_LINK_SPEED_2_5GB: 1506 return SPEED_2500; 1507 case BNXT_LINK_SPEED_10GB: 1508 return SPEED_10000; 1509 case BNXT_LINK_SPEED_20GB: 1510 return SPEED_20000; 1511 case BNXT_LINK_SPEED_25GB: 1512 return SPEED_25000; 1513 case BNXT_LINK_SPEED_40GB: 1514 return SPEED_40000; 1515 case BNXT_LINK_SPEED_50GB: 1516 return SPEED_50000; 1517 case BNXT_LINK_SPEED_100GB: 1518 return SPEED_100000; 1519 default: 1520 return SPEED_UNKNOWN; 1521 } 1522 } 1523 1524 static int bnxt_get_link_ksettings(struct net_device *dev, 1525 struct ethtool_link_ksettings *lk_ksettings) 1526 { 1527 struct bnxt *bp = netdev_priv(dev); 1528 struct bnxt_link_info *link_info = &bp->link_info; 1529 struct ethtool_link_settings *base = &lk_ksettings->base; 1530 u32 ethtool_speed; 1531 1532 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1533 mutex_lock(&bp->link_lock); 1534 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1535 1536 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1537 if (link_info->autoneg) { 1538 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1539 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1540 advertising, Autoneg); 1541 base->autoneg = AUTONEG_ENABLE; 1542 base->duplex = DUPLEX_UNKNOWN; 1543 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1544 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1545 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1546 base->duplex = DUPLEX_FULL; 1547 else 1548 base->duplex = DUPLEX_HALF; 1549 } 1550 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1551 } else { 1552 base->autoneg = AUTONEG_DISABLE; 1553 ethtool_speed = 1554 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1555 base->duplex = DUPLEX_HALF; 1556 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1557 base->duplex = DUPLEX_FULL; 1558 } 1559 base->speed = ethtool_speed; 1560 1561 base->port = PORT_NONE; 1562 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1563 base->port = PORT_TP; 1564 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1565 TP); 1566 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1567 TP); 1568 } else { 1569 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1570 FIBRE); 1571 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1572 FIBRE); 1573 1574 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1575 base->port = PORT_DA; 1576 else if (link_info->media_type == 1577 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1578 base->port = PORT_FIBRE; 1579 } 1580 base->phy_address = link_info->phy_addr; 1581 mutex_unlock(&bp->link_lock); 1582 1583 return 0; 1584 } 1585 1586 static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed) 1587 { 1588 struct bnxt *bp = netdev_priv(dev); 1589 struct bnxt_link_info *link_info = &bp->link_info; 1590 u16 support_spds = link_info->support_speeds; 1591 u32 fw_speed = 0; 1592 1593 switch (ethtool_speed) { 1594 case SPEED_100: 1595 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1596 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB; 1597 break; 1598 case SPEED_1000: 1599 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1600 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB; 1601 break; 1602 case SPEED_2500: 1603 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1604 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB; 1605 break; 1606 case SPEED_10000: 1607 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1608 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB; 1609 break; 1610 case SPEED_20000: 1611 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1612 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB; 1613 break; 1614 case SPEED_25000: 1615 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1616 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB; 1617 break; 1618 case SPEED_40000: 1619 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1620 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB; 1621 break; 1622 case SPEED_50000: 1623 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) 1624 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB; 1625 break; 1626 case SPEED_100000: 1627 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) 1628 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB; 1629 break; 1630 default: 1631 netdev_err(dev, "unsupported speed!\n"); 1632 break; 1633 } 1634 return fw_speed; 1635 } 1636 1637 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1638 { 1639 u16 fw_speed_mask = 0; 1640 1641 /* only support autoneg at speed 100, 1000, and 10000 */ 1642 if (advertising & (ADVERTISED_100baseT_Full | 1643 ADVERTISED_100baseT_Half)) { 1644 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1645 } 1646 if (advertising & (ADVERTISED_1000baseT_Full | 1647 ADVERTISED_1000baseT_Half)) { 1648 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1649 } 1650 if (advertising & ADVERTISED_10000baseT_Full) 1651 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1652 1653 if (advertising & ADVERTISED_40000baseCR4_Full) 1654 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1655 1656 return fw_speed_mask; 1657 } 1658 1659 static int bnxt_set_link_ksettings(struct net_device *dev, 1660 const struct ethtool_link_ksettings *lk_ksettings) 1661 { 1662 struct bnxt *bp = netdev_priv(dev); 1663 struct bnxt_link_info *link_info = &bp->link_info; 1664 const struct ethtool_link_settings *base = &lk_ksettings->base; 1665 bool set_pause = false; 1666 u16 fw_advertising = 0; 1667 u32 speed; 1668 int rc = 0; 1669 1670 if (!BNXT_PHY_CFG_ABLE(bp)) 1671 return -EOPNOTSUPP; 1672 1673 mutex_lock(&bp->link_lock); 1674 if (base->autoneg == AUTONEG_ENABLE) { 1675 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings, 1676 advertising); 1677 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1678 if (!fw_advertising) 1679 link_info->advertising = link_info->support_auto_speeds; 1680 else 1681 link_info->advertising = fw_advertising; 1682 /* any change to autoneg will cause link change, therefore the 1683 * driver should put back the original pause setting in autoneg 1684 */ 1685 set_pause = true; 1686 } else { 1687 u16 fw_speed; 1688 u8 phy_type = link_info->phy_type; 1689 1690 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1691 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1692 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1693 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1694 rc = -EINVAL; 1695 goto set_setting_exit; 1696 } 1697 if (base->duplex == DUPLEX_HALF) { 1698 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1699 rc = -EINVAL; 1700 goto set_setting_exit; 1701 } 1702 speed = base->speed; 1703 fw_speed = bnxt_get_fw_speed(dev, speed); 1704 if (!fw_speed) { 1705 rc = -EINVAL; 1706 goto set_setting_exit; 1707 } 1708 link_info->req_link_speed = fw_speed; 1709 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1710 link_info->autoneg = 0; 1711 link_info->advertising = 0; 1712 } 1713 1714 if (netif_running(dev)) 1715 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1716 1717 set_setting_exit: 1718 mutex_unlock(&bp->link_lock); 1719 return rc; 1720 } 1721 1722 static void bnxt_get_pauseparam(struct net_device *dev, 1723 struct ethtool_pauseparam *epause) 1724 { 1725 struct bnxt *bp = netdev_priv(dev); 1726 struct bnxt_link_info *link_info = &bp->link_info; 1727 1728 if (BNXT_VF(bp)) 1729 return; 1730 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 1731 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 1732 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 1733 } 1734 1735 static int bnxt_set_pauseparam(struct net_device *dev, 1736 struct ethtool_pauseparam *epause) 1737 { 1738 int rc = 0; 1739 struct bnxt *bp = netdev_priv(dev); 1740 struct bnxt_link_info *link_info = &bp->link_info; 1741 1742 if (!BNXT_PHY_CFG_ABLE(bp)) 1743 return -EOPNOTSUPP; 1744 1745 if (epause->autoneg) { 1746 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 1747 return -EINVAL; 1748 1749 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 1750 if (bp->hwrm_spec_code >= 0x10201) 1751 link_info->req_flow_ctrl = 1752 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 1753 } else { 1754 /* when transition from auto pause to force pause, 1755 * force a link change 1756 */ 1757 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1758 link_info->force_link_chng = true; 1759 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 1760 link_info->req_flow_ctrl = 0; 1761 } 1762 if (epause->rx_pause) 1763 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 1764 1765 if (epause->tx_pause) 1766 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 1767 1768 if (netif_running(dev)) 1769 rc = bnxt_hwrm_set_pause(bp); 1770 return rc; 1771 } 1772 1773 static u32 bnxt_get_link(struct net_device *dev) 1774 { 1775 struct bnxt *bp = netdev_priv(dev); 1776 1777 /* TODO: handle MF, VF, driver close case */ 1778 return bp->link_info.link_up; 1779 } 1780 1781 static void bnxt_print_admin_err(struct bnxt *bp) 1782 { 1783 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 1784 } 1785 1786 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 1787 u16 ext, u16 *index, u32 *item_length, 1788 u32 *data_length); 1789 1790 static int bnxt_flash_nvram(struct net_device *dev, 1791 u16 dir_type, 1792 u16 dir_ordinal, 1793 u16 dir_ext, 1794 u16 dir_attr, 1795 const u8 *data, 1796 size_t data_len) 1797 { 1798 struct bnxt *bp = netdev_priv(dev); 1799 int rc; 1800 struct hwrm_nvm_write_input req = {0}; 1801 dma_addr_t dma_handle; 1802 u8 *kmem; 1803 1804 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 1805 1806 req.dir_type = cpu_to_le16(dir_type); 1807 req.dir_ordinal = cpu_to_le16(dir_ordinal); 1808 req.dir_ext = cpu_to_le16(dir_ext); 1809 req.dir_attr = cpu_to_le16(dir_attr); 1810 req.dir_data_length = cpu_to_le32(data_len); 1811 1812 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 1813 GFP_KERNEL); 1814 if (!kmem) { 1815 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 1816 (unsigned)data_len); 1817 return -ENOMEM; 1818 } 1819 memcpy(kmem, data, data_len); 1820 req.host_src_addr = cpu_to_le64(dma_handle); 1821 1822 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 1823 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 1824 1825 if (rc == -EACCES) 1826 bnxt_print_admin_err(bp); 1827 return rc; 1828 } 1829 1830 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 1831 u8 self_reset, u8 flags) 1832 { 1833 struct hwrm_fw_reset_input req = {0}; 1834 struct bnxt *bp = netdev_priv(dev); 1835 int rc; 1836 1837 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 1838 1839 req.embedded_proc_type = proc_type; 1840 req.selfrst_status = self_reset; 1841 req.flags = flags; 1842 1843 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 1844 rc = hwrm_send_message_silent(bp, &req, sizeof(req), 1845 HWRM_CMD_TIMEOUT); 1846 } else { 1847 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1848 if (rc == -EACCES) 1849 bnxt_print_admin_err(bp); 1850 } 1851 return rc; 1852 } 1853 1854 static int bnxt_firmware_reset(struct net_device *dev, 1855 enum bnxt_nvm_directory_type dir_type) 1856 { 1857 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 1858 u8 proc_type, flags = 0; 1859 1860 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 1861 /* (e.g. when firmware isn't already running) */ 1862 switch (dir_type) { 1863 case BNX_DIR_TYPE_CHIMP_PATCH: 1864 case BNX_DIR_TYPE_BOOTCODE: 1865 case BNX_DIR_TYPE_BOOTCODE_2: 1866 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 1867 /* Self-reset ChiMP upon next PCIe reset: */ 1868 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1869 break; 1870 case BNX_DIR_TYPE_APE_FW: 1871 case BNX_DIR_TYPE_APE_PATCH: 1872 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 1873 /* Self-reset APE upon next PCIe reset: */ 1874 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1875 break; 1876 case BNX_DIR_TYPE_KONG_FW: 1877 case BNX_DIR_TYPE_KONG_PATCH: 1878 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 1879 break; 1880 case BNX_DIR_TYPE_BONO_FW: 1881 case BNX_DIR_TYPE_BONO_PATCH: 1882 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 1883 break; 1884 default: 1885 return -EINVAL; 1886 } 1887 1888 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 1889 } 1890 1891 static int bnxt_firmware_reset_chip(struct net_device *dev) 1892 { 1893 struct bnxt *bp = netdev_priv(dev); 1894 u8 flags = 0; 1895 1896 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 1897 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 1898 1899 return bnxt_hwrm_firmware_reset(dev, 1900 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 1901 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 1902 flags); 1903 } 1904 1905 static int bnxt_firmware_reset_ap(struct net_device *dev) 1906 { 1907 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 1908 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 1909 0); 1910 } 1911 1912 static int bnxt_flash_firmware(struct net_device *dev, 1913 u16 dir_type, 1914 const u8 *fw_data, 1915 size_t fw_size) 1916 { 1917 int rc = 0; 1918 u16 code_type; 1919 u32 stored_crc; 1920 u32 calculated_crc; 1921 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 1922 1923 switch (dir_type) { 1924 case BNX_DIR_TYPE_BOOTCODE: 1925 case BNX_DIR_TYPE_BOOTCODE_2: 1926 code_type = CODE_BOOT; 1927 break; 1928 case BNX_DIR_TYPE_CHIMP_PATCH: 1929 code_type = CODE_CHIMP_PATCH; 1930 break; 1931 case BNX_DIR_TYPE_APE_FW: 1932 code_type = CODE_MCTP_PASSTHRU; 1933 break; 1934 case BNX_DIR_TYPE_APE_PATCH: 1935 code_type = CODE_APE_PATCH; 1936 break; 1937 case BNX_DIR_TYPE_KONG_FW: 1938 code_type = CODE_KONG_FW; 1939 break; 1940 case BNX_DIR_TYPE_KONG_PATCH: 1941 code_type = CODE_KONG_PATCH; 1942 break; 1943 case BNX_DIR_TYPE_BONO_FW: 1944 code_type = CODE_BONO_FW; 1945 break; 1946 case BNX_DIR_TYPE_BONO_PATCH: 1947 code_type = CODE_BONO_PATCH; 1948 break; 1949 default: 1950 netdev_err(dev, "Unsupported directory entry type: %u\n", 1951 dir_type); 1952 return -EINVAL; 1953 } 1954 if (fw_size < sizeof(struct bnxt_fw_header)) { 1955 netdev_err(dev, "Invalid firmware file size: %u\n", 1956 (unsigned int)fw_size); 1957 return -EINVAL; 1958 } 1959 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 1960 netdev_err(dev, "Invalid firmware signature: %08X\n", 1961 le32_to_cpu(header->signature)); 1962 return -EINVAL; 1963 } 1964 if (header->code_type != code_type) { 1965 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 1966 code_type, header->code_type); 1967 return -EINVAL; 1968 } 1969 if (header->device != DEVICE_CUMULUS_FAMILY) { 1970 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 1971 DEVICE_CUMULUS_FAMILY, header->device); 1972 return -EINVAL; 1973 } 1974 /* Confirm the CRC32 checksum of the file: */ 1975 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 1976 sizeof(stored_crc))); 1977 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 1978 if (calculated_crc != stored_crc) { 1979 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 1980 (unsigned long)stored_crc, 1981 (unsigned long)calculated_crc); 1982 return -EINVAL; 1983 } 1984 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1985 0, 0, fw_data, fw_size); 1986 if (rc == 0) /* Firmware update successful */ 1987 rc = bnxt_firmware_reset(dev, dir_type); 1988 1989 return rc; 1990 } 1991 1992 static int bnxt_flash_microcode(struct net_device *dev, 1993 u16 dir_type, 1994 const u8 *fw_data, 1995 size_t fw_size) 1996 { 1997 struct bnxt_ucode_trailer *trailer; 1998 u32 calculated_crc; 1999 u32 stored_crc; 2000 int rc = 0; 2001 2002 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2003 netdev_err(dev, "Invalid microcode file size: %u\n", 2004 (unsigned int)fw_size); 2005 return -EINVAL; 2006 } 2007 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2008 sizeof(*trailer))); 2009 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2010 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2011 le32_to_cpu(trailer->sig)); 2012 return -EINVAL; 2013 } 2014 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2015 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2016 dir_type, le16_to_cpu(trailer->dir_type)); 2017 return -EINVAL; 2018 } 2019 if (le16_to_cpu(trailer->trailer_length) < 2020 sizeof(struct bnxt_ucode_trailer)) { 2021 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2022 le16_to_cpu(trailer->trailer_length)); 2023 return -EINVAL; 2024 } 2025 2026 /* Confirm the CRC32 checksum of the file: */ 2027 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2028 sizeof(stored_crc))); 2029 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2030 if (calculated_crc != stored_crc) { 2031 netdev_err(dev, 2032 "CRC32 (%08lX) does not match calculated: %08lX\n", 2033 (unsigned long)stored_crc, 2034 (unsigned long)calculated_crc); 2035 return -EINVAL; 2036 } 2037 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2038 0, 0, fw_data, fw_size); 2039 2040 return rc; 2041 } 2042 2043 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2044 { 2045 switch (dir_type) { 2046 case BNX_DIR_TYPE_CHIMP_PATCH: 2047 case BNX_DIR_TYPE_BOOTCODE: 2048 case BNX_DIR_TYPE_BOOTCODE_2: 2049 case BNX_DIR_TYPE_APE_FW: 2050 case BNX_DIR_TYPE_APE_PATCH: 2051 case BNX_DIR_TYPE_KONG_FW: 2052 case BNX_DIR_TYPE_KONG_PATCH: 2053 case BNX_DIR_TYPE_BONO_FW: 2054 case BNX_DIR_TYPE_BONO_PATCH: 2055 return true; 2056 } 2057 2058 return false; 2059 } 2060 2061 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2062 { 2063 switch (dir_type) { 2064 case BNX_DIR_TYPE_AVS: 2065 case BNX_DIR_TYPE_EXP_ROM_MBA: 2066 case BNX_DIR_TYPE_PCIE: 2067 case BNX_DIR_TYPE_TSCF_UCODE: 2068 case BNX_DIR_TYPE_EXT_PHY: 2069 case BNX_DIR_TYPE_CCM: 2070 case BNX_DIR_TYPE_ISCSI_BOOT: 2071 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2072 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2073 return true; 2074 } 2075 2076 return false; 2077 } 2078 2079 static bool bnxt_dir_type_is_executable(u16 dir_type) 2080 { 2081 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2082 bnxt_dir_type_is_other_exec_format(dir_type); 2083 } 2084 2085 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2086 u16 dir_type, 2087 const char *filename) 2088 { 2089 const struct firmware *fw; 2090 int rc; 2091 2092 rc = request_firmware(&fw, filename, &dev->dev); 2093 if (rc != 0) { 2094 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2095 rc, filename); 2096 return rc; 2097 } 2098 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2099 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2100 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2101 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2102 else 2103 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2104 0, 0, fw->data, fw->size); 2105 release_firmware(fw); 2106 return rc; 2107 } 2108 2109 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2110 u32 install_type) 2111 { 2112 struct bnxt *bp = netdev_priv(dev); 2113 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2114 struct hwrm_nvm_install_update_input install = {0}; 2115 const struct firmware *fw; 2116 u32 item_len; 2117 int rc = 0; 2118 u16 index; 2119 2120 bnxt_hwrm_fw_set_time(bp); 2121 2122 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2123 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2124 &index, &item_len, NULL); 2125 if (rc) { 2126 netdev_err(dev, "PKG update area not created in nvram\n"); 2127 return rc; 2128 } 2129 2130 rc = request_firmware(&fw, filename, &dev->dev); 2131 if (rc != 0) { 2132 netdev_err(dev, "PKG error %d requesting file: %s\n", 2133 rc, filename); 2134 return rc; 2135 } 2136 2137 if (fw->size > item_len) { 2138 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2139 (unsigned long)fw->size); 2140 rc = -EFBIG; 2141 } else { 2142 dma_addr_t dma_handle; 2143 u8 *kmem; 2144 struct hwrm_nvm_modify_input modify = {0}; 2145 2146 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2147 2148 modify.dir_idx = cpu_to_le16(index); 2149 modify.len = cpu_to_le32(fw->size); 2150 2151 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2152 &dma_handle, GFP_KERNEL); 2153 if (!kmem) { 2154 netdev_err(dev, 2155 "dma_alloc_coherent failure, length = %u\n", 2156 (unsigned int)fw->size); 2157 rc = -ENOMEM; 2158 } else { 2159 memcpy(kmem, fw->data, fw->size); 2160 modify.host_src_addr = cpu_to_le64(dma_handle); 2161 2162 rc = hwrm_send_message(bp, &modify, sizeof(modify), 2163 FLASH_PACKAGE_TIMEOUT); 2164 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2165 dma_handle); 2166 } 2167 } 2168 release_firmware(fw); 2169 if (rc) 2170 goto err_exit; 2171 2172 if ((install_type & 0xffff) == 0) 2173 install_type >>= 16; 2174 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2175 install.install_type = cpu_to_le32(install_type); 2176 2177 mutex_lock(&bp->hwrm_cmd_lock); 2178 rc = _hwrm_send_message(bp, &install, sizeof(install), 2179 INSTALL_PACKAGE_TIMEOUT); 2180 if (rc) { 2181 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2182 2183 if (resp->error_code && error_code == 2184 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2185 install.flags |= cpu_to_le16( 2186 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2187 rc = _hwrm_send_message(bp, &install, sizeof(install), 2188 INSTALL_PACKAGE_TIMEOUT); 2189 } 2190 if (rc) 2191 goto flash_pkg_exit; 2192 } 2193 2194 if (resp->result) { 2195 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2196 (s8)resp->result, (int)resp->problem_item); 2197 rc = -ENOPKG; 2198 } 2199 flash_pkg_exit: 2200 mutex_unlock(&bp->hwrm_cmd_lock); 2201 err_exit: 2202 if (rc == -EACCES) 2203 bnxt_print_admin_err(bp); 2204 return rc; 2205 } 2206 2207 static int bnxt_flash_device(struct net_device *dev, 2208 struct ethtool_flash *flash) 2209 { 2210 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2211 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2212 return -EINVAL; 2213 } 2214 2215 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2216 flash->region > 0xffff) 2217 return bnxt_flash_package_from_file(dev, flash->data, 2218 flash->region); 2219 2220 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2221 } 2222 2223 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2224 { 2225 struct bnxt *bp = netdev_priv(dev); 2226 int rc; 2227 struct hwrm_nvm_get_dir_info_input req = {0}; 2228 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2229 2230 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2231 2232 mutex_lock(&bp->hwrm_cmd_lock); 2233 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2234 if (!rc) { 2235 *entries = le32_to_cpu(output->entries); 2236 *length = le32_to_cpu(output->entry_length); 2237 } 2238 mutex_unlock(&bp->hwrm_cmd_lock); 2239 return rc; 2240 } 2241 2242 static int bnxt_get_eeprom_len(struct net_device *dev) 2243 { 2244 struct bnxt *bp = netdev_priv(dev); 2245 2246 if (BNXT_VF(bp)) 2247 return 0; 2248 2249 /* The -1 return value allows the entire 32-bit range of offsets to be 2250 * passed via the ethtool command-line utility. 2251 */ 2252 return -1; 2253 } 2254 2255 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2256 { 2257 struct bnxt *bp = netdev_priv(dev); 2258 int rc; 2259 u32 dir_entries; 2260 u32 entry_length; 2261 u8 *buf; 2262 size_t buflen; 2263 dma_addr_t dma_handle; 2264 struct hwrm_nvm_get_dir_entries_input req = {0}; 2265 2266 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2267 if (rc != 0) 2268 return rc; 2269 2270 /* Insert 2 bytes of directory info (count and size of entries) */ 2271 if (len < 2) 2272 return -EINVAL; 2273 2274 *data++ = dir_entries; 2275 *data++ = entry_length; 2276 len -= 2; 2277 memset(data, 0xff, len); 2278 2279 buflen = dir_entries * entry_length; 2280 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2281 GFP_KERNEL); 2282 if (!buf) { 2283 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2284 (unsigned)buflen); 2285 return -ENOMEM; 2286 } 2287 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2288 req.host_dest_addr = cpu_to_le64(dma_handle); 2289 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2290 if (rc == 0) 2291 memcpy(data, buf, len > buflen ? buflen : len); 2292 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2293 return rc; 2294 } 2295 2296 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2297 u32 length, u8 *data) 2298 { 2299 struct bnxt *bp = netdev_priv(dev); 2300 int rc; 2301 u8 *buf; 2302 dma_addr_t dma_handle; 2303 struct hwrm_nvm_read_input req = {0}; 2304 2305 if (!length) 2306 return -EINVAL; 2307 2308 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2309 GFP_KERNEL); 2310 if (!buf) { 2311 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2312 (unsigned)length); 2313 return -ENOMEM; 2314 } 2315 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2316 req.host_dest_addr = cpu_to_le64(dma_handle); 2317 req.dir_idx = cpu_to_le16(index); 2318 req.offset = cpu_to_le32(offset); 2319 req.len = cpu_to_le32(length); 2320 2321 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2322 if (rc == 0) 2323 memcpy(data, buf, length); 2324 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2325 return rc; 2326 } 2327 2328 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2329 u16 ext, u16 *index, u32 *item_length, 2330 u32 *data_length) 2331 { 2332 struct bnxt *bp = netdev_priv(dev); 2333 int rc; 2334 struct hwrm_nvm_find_dir_entry_input req = {0}; 2335 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2336 2337 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2338 req.enables = 0; 2339 req.dir_idx = 0; 2340 req.dir_type = cpu_to_le16(type); 2341 req.dir_ordinal = cpu_to_le16(ordinal); 2342 req.dir_ext = cpu_to_le16(ext); 2343 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2344 mutex_lock(&bp->hwrm_cmd_lock); 2345 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2346 if (rc == 0) { 2347 if (index) 2348 *index = le16_to_cpu(output->dir_idx); 2349 if (item_length) 2350 *item_length = le32_to_cpu(output->dir_item_length); 2351 if (data_length) 2352 *data_length = le32_to_cpu(output->dir_data_length); 2353 } 2354 mutex_unlock(&bp->hwrm_cmd_lock); 2355 return rc; 2356 } 2357 2358 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2359 { 2360 char *retval = NULL; 2361 char *p; 2362 char *value; 2363 int field = 0; 2364 2365 if (datalen < 1) 2366 return NULL; 2367 /* null-terminate the log data (removing last '\n'): */ 2368 data[datalen - 1] = 0; 2369 for (p = data; *p != 0; p++) { 2370 field = 0; 2371 retval = NULL; 2372 while (*p != 0 && *p != '\n') { 2373 value = p; 2374 while (*p != 0 && *p != '\t' && *p != '\n') 2375 p++; 2376 if (field == desired_field) 2377 retval = value; 2378 if (*p != '\t') 2379 break; 2380 *p = 0; 2381 field++; 2382 p++; 2383 } 2384 if (*p == 0) 2385 break; 2386 *p = 0; 2387 } 2388 return retval; 2389 } 2390 2391 static void bnxt_get_pkgver(struct net_device *dev) 2392 { 2393 struct bnxt *bp = netdev_priv(dev); 2394 u16 index = 0; 2395 char *pkgver; 2396 u32 pkglen; 2397 u8 *pkgbuf; 2398 int len; 2399 2400 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2401 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2402 &index, NULL, &pkglen) != 0) 2403 return; 2404 2405 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2406 if (!pkgbuf) { 2407 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2408 pkglen); 2409 return; 2410 } 2411 2412 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2413 goto err; 2414 2415 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2416 pkglen); 2417 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2418 len = strlen(bp->fw_ver_str); 2419 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2420 "/pkg %s", pkgver); 2421 } 2422 err: 2423 kfree(pkgbuf); 2424 } 2425 2426 static int bnxt_get_eeprom(struct net_device *dev, 2427 struct ethtool_eeprom *eeprom, 2428 u8 *data) 2429 { 2430 u32 index; 2431 u32 offset; 2432 2433 if (eeprom->offset == 0) /* special offset value to get directory */ 2434 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2435 2436 index = eeprom->offset >> 24; 2437 offset = eeprom->offset & 0xffffff; 2438 2439 if (index == 0) { 2440 netdev_err(dev, "unsupported index value: %d\n", index); 2441 return -EINVAL; 2442 } 2443 2444 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2445 } 2446 2447 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2448 { 2449 struct bnxt *bp = netdev_priv(dev); 2450 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2451 2452 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2453 req.dir_idx = cpu_to_le16(index); 2454 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2455 } 2456 2457 static int bnxt_set_eeprom(struct net_device *dev, 2458 struct ethtool_eeprom *eeprom, 2459 u8 *data) 2460 { 2461 struct bnxt *bp = netdev_priv(dev); 2462 u8 index, dir_op; 2463 u16 type, ext, ordinal, attr; 2464 2465 if (!BNXT_PF(bp)) { 2466 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2467 return -EINVAL; 2468 } 2469 2470 type = eeprom->magic >> 16; 2471 2472 if (type == 0xffff) { /* special value for directory operations */ 2473 index = eeprom->magic & 0xff; 2474 dir_op = eeprom->magic >> 8; 2475 if (index == 0) 2476 return -EINVAL; 2477 switch (dir_op) { 2478 case 0x0e: /* erase */ 2479 if (eeprom->offset != ~eeprom->magic) 2480 return -EINVAL; 2481 return bnxt_erase_nvram_directory(dev, index - 1); 2482 default: 2483 return -EINVAL; 2484 } 2485 } 2486 2487 /* Create or re-write an NVM item: */ 2488 if (bnxt_dir_type_is_executable(type)) 2489 return -EOPNOTSUPP; 2490 ext = eeprom->magic & 0xffff; 2491 ordinal = eeprom->offset >> 16; 2492 attr = eeprom->offset & 0xffff; 2493 2494 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2495 eeprom->len); 2496 } 2497 2498 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2499 { 2500 struct bnxt *bp = netdev_priv(dev); 2501 struct ethtool_eee *eee = &bp->eee; 2502 struct bnxt_link_info *link_info = &bp->link_info; 2503 u32 advertising = 2504 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2505 int rc = 0; 2506 2507 if (!BNXT_PHY_CFG_ABLE(bp)) 2508 return -EOPNOTSUPP; 2509 2510 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2511 return -EOPNOTSUPP; 2512 2513 if (!edata->eee_enabled) 2514 goto eee_ok; 2515 2516 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2517 netdev_warn(dev, "EEE requires autoneg\n"); 2518 return -EINVAL; 2519 } 2520 if (edata->tx_lpi_enabled) { 2521 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2522 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2523 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2524 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2525 return -EINVAL; 2526 } else if (!bp->lpi_tmr_hi) { 2527 edata->tx_lpi_timer = eee->tx_lpi_timer; 2528 } 2529 } 2530 if (!edata->advertised) { 2531 edata->advertised = advertising & eee->supported; 2532 } else if (edata->advertised & ~advertising) { 2533 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2534 edata->advertised, advertising); 2535 return -EINVAL; 2536 } 2537 2538 eee->advertised = edata->advertised; 2539 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2540 eee->tx_lpi_timer = edata->tx_lpi_timer; 2541 eee_ok: 2542 eee->eee_enabled = edata->eee_enabled; 2543 2544 if (netif_running(dev)) 2545 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2546 2547 return rc; 2548 } 2549 2550 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2551 { 2552 struct bnxt *bp = netdev_priv(dev); 2553 2554 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2555 return -EOPNOTSUPP; 2556 2557 *edata = bp->eee; 2558 if (!bp->eee.eee_enabled) { 2559 /* Preserve tx_lpi_timer so that the last value will be used 2560 * by default when it is re-enabled. 2561 */ 2562 edata->advertised = 0; 2563 edata->tx_lpi_enabled = 0; 2564 } 2565 2566 if (!bp->eee.eee_active) 2567 edata->lp_advertised = 0; 2568 2569 return 0; 2570 } 2571 2572 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2573 u16 page_number, u16 start_addr, 2574 u16 data_length, u8 *buf) 2575 { 2576 struct hwrm_port_phy_i2c_read_input req = {0}; 2577 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2578 int rc, byte_offset = 0; 2579 2580 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2581 req.i2c_slave_addr = i2c_addr; 2582 req.page_number = cpu_to_le16(page_number); 2583 req.port_id = cpu_to_le16(bp->pf.port_id); 2584 do { 2585 u16 xfer_size; 2586 2587 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2588 data_length -= xfer_size; 2589 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2590 req.data_length = xfer_size; 2591 req.enables = cpu_to_le32(start_addr + byte_offset ? 2592 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2593 mutex_lock(&bp->hwrm_cmd_lock); 2594 rc = _hwrm_send_message(bp, &req, sizeof(req), 2595 HWRM_CMD_TIMEOUT); 2596 if (!rc) 2597 memcpy(buf + byte_offset, output->data, xfer_size); 2598 mutex_unlock(&bp->hwrm_cmd_lock); 2599 byte_offset += xfer_size; 2600 } while (!rc && data_length > 0); 2601 2602 return rc; 2603 } 2604 2605 static int bnxt_get_module_info(struct net_device *dev, 2606 struct ethtool_modinfo *modinfo) 2607 { 2608 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2609 struct bnxt *bp = netdev_priv(dev); 2610 int rc; 2611 2612 /* No point in going further if phy status indicates 2613 * module is not inserted or if it is powered down or 2614 * if it is of type 10GBase-T 2615 */ 2616 if (bp->link_info.module_status > 2617 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2618 return -EOPNOTSUPP; 2619 2620 /* This feature is not supported in older firmware versions */ 2621 if (bp->hwrm_spec_code < 0x10202) 2622 return -EOPNOTSUPP; 2623 2624 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2625 SFF_DIAG_SUPPORT_OFFSET + 1, 2626 data); 2627 if (!rc) { 2628 u8 module_id = data[0]; 2629 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2630 2631 switch (module_id) { 2632 case SFF_MODULE_ID_SFP: 2633 modinfo->type = ETH_MODULE_SFF_8472; 2634 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2635 if (!diag_supported) 2636 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2637 break; 2638 case SFF_MODULE_ID_QSFP: 2639 case SFF_MODULE_ID_QSFP_PLUS: 2640 modinfo->type = ETH_MODULE_SFF_8436; 2641 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2642 break; 2643 case SFF_MODULE_ID_QSFP28: 2644 modinfo->type = ETH_MODULE_SFF_8636; 2645 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2646 break; 2647 default: 2648 rc = -EOPNOTSUPP; 2649 break; 2650 } 2651 } 2652 return rc; 2653 } 2654 2655 static int bnxt_get_module_eeprom(struct net_device *dev, 2656 struct ethtool_eeprom *eeprom, 2657 u8 *data) 2658 { 2659 struct bnxt *bp = netdev_priv(dev); 2660 u16 start = eeprom->offset, length = eeprom->len; 2661 int rc = 0; 2662 2663 memset(data, 0, eeprom->len); 2664 2665 /* Read A0 portion of the EEPROM */ 2666 if (start < ETH_MODULE_SFF_8436_LEN) { 2667 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 2668 length = ETH_MODULE_SFF_8436_LEN - start; 2669 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 2670 start, length, data); 2671 if (rc) 2672 return rc; 2673 start += length; 2674 data += length; 2675 length = eeprom->len - length; 2676 } 2677 2678 /* Read A2 portion of the EEPROM */ 2679 if (length) { 2680 start -= ETH_MODULE_SFF_8436_LEN; 2681 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, 2682 start, length, data); 2683 } 2684 return rc; 2685 } 2686 2687 static int bnxt_nway_reset(struct net_device *dev) 2688 { 2689 int rc = 0; 2690 2691 struct bnxt *bp = netdev_priv(dev); 2692 struct bnxt_link_info *link_info = &bp->link_info; 2693 2694 if (!BNXT_PHY_CFG_ABLE(bp)) 2695 return -EOPNOTSUPP; 2696 2697 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 2698 return -EINVAL; 2699 2700 if (netif_running(dev)) 2701 rc = bnxt_hwrm_set_link_setting(bp, true, false); 2702 2703 return rc; 2704 } 2705 2706 static int bnxt_set_phys_id(struct net_device *dev, 2707 enum ethtool_phys_id_state state) 2708 { 2709 struct hwrm_port_led_cfg_input req = {0}; 2710 struct bnxt *bp = netdev_priv(dev); 2711 struct bnxt_pf_info *pf = &bp->pf; 2712 struct bnxt_led_cfg *led_cfg; 2713 u8 led_state; 2714 __le16 duration; 2715 int i; 2716 2717 if (!bp->num_leds || BNXT_VF(bp)) 2718 return -EOPNOTSUPP; 2719 2720 if (state == ETHTOOL_ID_ACTIVE) { 2721 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 2722 duration = cpu_to_le16(500); 2723 } else if (state == ETHTOOL_ID_INACTIVE) { 2724 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 2725 duration = cpu_to_le16(0); 2726 } else { 2727 return -EINVAL; 2728 } 2729 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 2730 req.port_id = cpu_to_le16(pf->port_id); 2731 req.num_leds = bp->num_leds; 2732 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 2733 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 2734 req.enables |= BNXT_LED_DFLT_ENABLES(i); 2735 led_cfg->led_id = bp->leds[i].led_id; 2736 led_cfg->led_state = led_state; 2737 led_cfg->led_blink_on = duration; 2738 led_cfg->led_blink_off = duration; 2739 led_cfg->led_group_id = bp->leds[i].led_group_id; 2740 } 2741 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2742 } 2743 2744 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 2745 { 2746 struct hwrm_selftest_irq_input req = {0}; 2747 2748 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 2749 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2750 } 2751 2752 static int bnxt_test_irq(struct bnxt *bp) 2753 { 2754 int i; 2755 2756 for (i = 0; i < bp->cp_nr_rings; i++) { 2757 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 2758 int rc; 2759 2760 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 2761 if (rc) 2762 return rc; 2763 } 2764 return 0; 2765 } 2766 2767 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 2768 { 2769 struct hwrm_port_mac_cfg_input req = {0}; 2770 2771 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 2772 2773 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 2774 if (enable) 2775 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 2776 else 2777 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 2778 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2779 } 2780 2781 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 2782 { 2783 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 2784 struct hwrm_port_phy_qcaps_input req = {0}; 2785 int rc; 2786 2787 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 2788 mutex_lock(&bp->hwrm_cmd_lock); 2789 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2790 if (!rc) 2791 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 2792 2793 mutex_unlock(&bp->hwrm_cmd_lock); 2794 return rc; 2795 } 2796 2797 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 2798 struct hwrm_port_phy_cfg_input *req) 2799 { 2800 struct bnxt_link_info *link_info = &bp->link_info; 2801 u16 fw_advertising; 2802 u16 fw_speed; 2803 int rc; 2804 2805 if (!link_info->autoneg || 2806 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK)) 2807 return 0; 2808 2809 rc = bnxt_query_force_speeds(bp, &fw_advertising); 2810 if (rc) 2811 return rc; 2812 2813 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2814 if (bp->link_info.link_up) 2815 fw_speed = bp->link_info.link_speed; 2816 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 2817 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2818 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 2819 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2820 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 2821 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2822 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 2823 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2824 2825 req->force_link_speed = cpu_to_le16(fw_speed); 2826 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 2827 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2828 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 2829 req->flags = 0; 2830 req->force_link_speed = cpu_to_le16(0); 2831 return rc; 2832 } 2833 2834 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 2835 { 2836 struct hwrm_port_phy_cfg_input req = {0}; 2837 2838 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 2839 2840 if (enable) { 2841 bnxt_disable_an_for_lpbk(bp, &req); 2842 if (ext) 2843 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 2844 else 2845 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 2846 } else { 2847 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 2848 } 2849 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 2850 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2851 } 2852 2853 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2854 u32 raw_cons, int pkt_size) 2855 { 2856 struct bnxt_napi *bnapi = cpr->bnapi; 2857 struct bnxt_rx_ring_info *rxr; 2858 struct bnxt_sw_rx_bd *rx_buf; 2859 struct rx_cmp *rxcmp; 2860 u16 cp_cons, cons; 2861 u8 *data; 2862 u32 len; 2863 int i; 2864 2865 rxr = bnapi->rx_ring; 2866 cp_cons = RING_CMP(raw_cons); 2867 rxcmp = (struct rx_cmp *) 2868 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2869 cons = rxcmp->rx_cmp_opaque; 2870 rx_buf = &rxr->rx_buf_ring[cons]; 2871 data = rx_buf->data_ptr; 2872 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 2873 if (len != pkt_size) 2874 return -EIO; 2875 i = ETH_ALEN; 2876 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 2877 return -EIO; 2878 i += ETH_ALEN; 2879 for ( ; i < pkt_size; i++) { 2880 if (data[i] != (u8)(i & 0xff)) 2881 return -EIO; 2882 } 2883 return 0; 2884 } 2885 2886 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2887 int pkt_size) 2888 { 2889 struct tx_cmp *txcmp; 2890 int rc = -EIO; 2891 u32 raw_cons; 2892 u32 cons; 2893 int i; 2894 2895 raw_cons = cpr->cp_raw_cons; 2896 for (i = 0; i < 200; i++) { 2897 cons = RING_CMP(raw_cons); 2898 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2899 2900 if (!TX_CMP_VALID(txcmp, raw_cons)) { 2901 udelay(5); 2902 continue; 2903 } 2904 2905 /* The valid test of the entry must be done first before 2906 * reading any further. 2907 */ 2908 dma_rmb(); 2909 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 2910 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 2911 raw_cons = NEXT_RAW_CMP(raw_cons); 2912 raw_cons = NEXT_RAW_CMP(raw_cons); 2913 break; 2914 } 2915 raw_cons = NEXT_RAW_CMP(raw_cons); 2916 } 2917 cpr->cp_raw_cons = raw_cons; 2918 return rc; 2919 } 2920 2921 static int bnxt_run_loopback(struct bnxt *bp) 2922 { 2923 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 2924 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 2925 struct bnxt_cp_ring_info *cpr; 2926 int pkt_size, i = 0; 2927 struct sk_buff *skb; 2928 dma_addr_t map; 2929 u8 *data; 2930 int rc; 2931 2932 cpr = &rxr->bnapi->cp_ring; 2933 if (bp->flags & BNXT_FLAG_CHIP_P5) 2934 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 2935 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 2936 skb = netdev_alloc_skb(bp->dev, pkt_size); 2937 if (!skb) 2938 return -ENOMEM; 2939 data = skb_put(skb, pkt_size); 2940 eth_broadcast_addr(data); 2941 i += ETH_ALEN; 2942 ether_addr_copy(&data[i], bp->dev->dev_addr); 2943 i += ETH_ALEN; 2944 for ( ; i < pkt_size; i++) 2945 data[i] = (u8)(i & 0xff); 2946 2947 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 2948 PCI_DMA_TODEVICE); 2949 if (dma_mapping_error(&bp->pdev->dev, map)) { 2950 dev_kfree_skb(skb); 2951 return -EIO; 2952 } 2953 bnxt_xmit_bd(bp, txr, map, pkt_size); 2954 2955 /* Sync BD data before updating doorbell */ 2956 wmb(); 2957 2958 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 2959 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 2960 2961 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 2962 dev_kfree_skb(skb); 2963 return rc; 2964 } 2965 2966 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 2967 { 2968 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 2969 struct hwrm_selftest_exec_input req = {0}; 2970 int rc; 2971 2972 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 2973 mutex_lock(&bp->hwrm_cmd_lock); 2974 resp->test_success = 0; 2975 req.flags = test_mask; 2976 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 2977 *test_results = resp->test_success; 2978 mutex_unlock(&bp->hwrm_cmd_lock); 2979 return rc; 2980 } 2981 2982 #define BNXT_DRV_TESTS 4 2983 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 2984 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 2985 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 2986 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 2987 2988 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 2989 u64 *buf) 2990 { 2991 struct bnxt *bp = netdev_priv(dev); 2992 bool do_ext_lpbk = false; 2993 bool offline = false; 2994 u8 test_results = 0; 2995 u8 test_mask = 0; 2996 int rc = 0, i; 2997 2998 if (!bp->num_tests || !BNXT_SINGLE_PF(bp)) 2999 return; 3000 memset(buf, 0, sizeof(u64) * bp->num_tests); 3001 if (!netif_running(dev)) { 3002 etest->flags |= ETH_TEST_FL_FAILED; 3003 return; 3004 } 3005 3006 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3007 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 3008 do_ext_lpbk = true; 3009 3010 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3011 if (bp->pf.active_vfs) { 3012 etest->flags |= ETH_TEST_FL_FAILED; 3013 netdev_warn(dev, "Offline tests cannot be run with active VFs\n"); 3014 return; 3015 } 3016 offline = true; 3017 } 3018 3019 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3020 u8 bit_val = 1 << i; 3021 3022 if (!(bp->test_info->offline_mask & bit_val)) 3023 test_mask |= bit_val; 3024 else if (offline) 3025 test_mask |= bit_val; 3026 } 3027 if (!offline) { 3028 bnxt_run_fw_tests(bp, test_mask, &test_results); 3029 } else { 3030 rc = bnxt_close_nic(bp, false, false); 3031 if (rc) 3032 return; 3033 bnxt_run_fw_tests(bp, test_mask, &test_results); 3034 3035 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3036 bnxt_hwrm_mac_loopback(bp, true); 3037 msleep(250); 3038 rc = bnxt_half_open_nic(bp); 3039 if (rc) { 3040 bnxt_hwrm_mac_loopback(bp, false); 3041 etest->flags |= ETH_TEST_FL_FAILED; 3042 return; 3043 } 3044 if (bnxt_run_loopback(bp)) 3045 etest->flags |= ETH_TEST_FL_FAILED; 3046 else 3047 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3048 3049 bnxt_hwrm_mac_loopback(bp, false); 3050 bnxt_hwrm_phy_loopback(bp, true, false); 3051 msleep(1000); 3052 if (bnxt_run_loopback(bp)) { 3053 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3054 etest->flags |= ETH_TEST_FL_FAILED; 3055 } 3056 if (do_ext_lpbk) { 3057 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3058 bnxt_hwrm_phy_loopback(bp, true, true); 3059 msleep(1000); 3060 if (bnxt_run_loopback(bp)) { 3061 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3062 etest->flags |= ETH_TEST_FL_FAILED; 3063 } 3064 } 3065 bnxt_hwrm_phy_loopback(bp, false, false); 3066 bnxt_half_close_nic(bp); 3067 rc = bnxt_open_nic(bp, false, true); 3068 } 3069 if (rc || bnxt_test_irq(bp)) { 3070 buf[BNXT_IRQ_TEST_IDX] = 1; 3071 etest->flags |= ETH_TEST_FL_FAILED; 3072 } 3073 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3074 u8 bit_val = 1 << i; 3075 3076 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3077 buf[i] = 1; 3078 etest->flags |= ETH_TEST_FL_FAILED; 3079 } 3080 } 3081 } 3082 3083 static int bnxt_reset(struct net_device *dev, u32 *flags) 3084 { 3085 struct bnxt *bp = netdev_priv(dev); 3086 bool reload = false; 3087 u32 req = *flags; 3088 3089 if (!req) 3090 return -EINVAL; 3091 3092 if (!BNXT_PF(bp)) { 3093 netdev_err(dev, "Reset is not supported from a VF\n"); 3094 return -EOPNOTSUPP; 3095 } 3096 3097 if (pci_vfs_assigned(bp->pdev) && 3098 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3099 netdev_err(dev, 3100 "Reset not allowed when VFs are assigned to VMs\n"); 3101 return -EBUSY; 3102 } 3103 3104 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3105 /* This feature is not supported in older firmware versions */ 3106 if (bp->hwrm_spec_code >= 0x10803) { 3107 if (!bnxt_firmware_reset_chip(dev)) { 3108 netdev_info(dev, "Firmware reset request successful.\n"); 3109 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3110 reload = true; 3111 *flags &= ~BNXT_FW_RESET_CHIP; 3112 } 3113 } else if (req == BNXT_FW_RESET_CHIP) { 3114 return -EOPNOTSUPP; /* only request, fail hard */ 3115 } 3116 } 3117 3118 if (req & BNXT_FW_RESET_AP) { 3119 /* This feature is not supported in older firmware versions */ 3120 if (bp->hwrm_spec_code >= 0x10803) { 3121 if (!bnxt_firmware_reset_ap(dev)) { 3122 netdev_info(dev, "Reset application processor successful.\n"); 3123 reload = true; 3124 *flags &= ~BNXT_FW_RESET_AP; 3125 } 3126 } else if (req == BNXT_FW_RESET_AP) { 3127 return -EOPNOTSUPP; /* only request, fail hard */ 3128 } 3129 } 3130 3131 if (reload) 3132 netdev_info(dev, "Reload driver to complete reset\n"); 3133 3134 return 0; 3135 } 3136 3137 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3138 struct bnxt_hwrm_dbg_dma_info *info) 3139 { 3140 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3141 struct hwrm_dbg_cmn_input *cmn_req = msg; 3142 __le16 *seq_ptr = msg + info->seq_off; 3143 u16 seq = 0, len, segs_off; 3144 void *resp = cmn_resp; 3145 dma_addr_t dma_handle; 3146 int rc, off = 0; 3147 void *dma_buf; 3148 3149 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3150 GFP_KERNEL); 3151 if (!dma_buf) 3152 return -ENOMEM; 3153 3154 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3155 total_segments); 3156 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3157 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3158 mutex_lock(&bp->hwrm_cmd_lock); 3159 while (1) { 3160 *seq_ptr = cpu_to_le16(seq); 3161 rc = _hwrm_send_message(bp, msg, msg_len, 3162 HWRM_COREDUMP_TIMEOUT); 3163 if (rc) 3164 break; 3165 3166 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3167 if (!seq && 3168 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3169 info->segs = le16_to_cpu(*((__le16 *)(resp + 3170 segs_off))); 3171 if (!info->segs) { 3172 rc = -EIO; 3173 break; 3174 } 3175 3176 info->dest_buf_size = info->segs * 3177 sizeof(struct coredump_segment_record); 3178 info->dest_buf = kmalloc(info->dest_buf_size, 3179 GFP_KERNEL); 3180 if (!info->dest_buf) { 3181 rc = -ENOMEM; 3182 break; 3183 } 3184 } 3185 3186 if (info->dest_buf) { 3187 if ((info->seg_start + off + len) <= 3188 BNXT_COREDUMP_BUF_LEN(info->buf_len)) { 3189 memcpy(info->dest_buf + off, dma_buf, len); 3190 } else { 3191 rc = -ENOBUFS; 3192 break; 3193 } 3194 } 3195 3196 if (cmn_req->req_type == 3197 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3198 info->dest_buf_size += len; 3199 3200 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3201 break; 3202 3203 seq++; 3204 off += len; 3205 } 3206 mutex_unlock(&bp->hwrm_cmd_lock); 3207 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3208 return rc; 3209 } 3210 3211 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3212 struct bnxt_coredump *coredump) 3213 { 3214 struct hwrm_dbg_coredump_list_input req = {0}; 3215 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3216 int rc; 3217 3218 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3219 3220 info.dma_len = COREDUMP_LIST_BUF_LEN; 3221 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3222 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3223 data_len); 3224 3225 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3226 if (!rc) { 3227 coredump->data = info.dest_buf; 3228 coredump->data_size = info.dest_buf_size; 3229 coredump->total_segs = info.segs; 3230 } 3231 return rc; 3232 } 3233 3234 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3235 u16 segment_id) 3236 { 3237 struct hwrm_dbg_coredump_initiate_input req = {0}; 3238 3239 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3240 req.component_id = cpu_to_le16(component_id); 3241 req.segment_id = cpu_to_le16(segment_id); 3242 3243 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3244 } 3245 3246 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3247 u16 segment_id, u32 *seg_len, 3248 void *buf, u32 buf_len, u32 offset) 3249 { 3250 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3251 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3252 int rc; 3253 3254 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3255 req.component_id = cpu_to_le16(component_id); 3256 req.segment_id = cpu_to_le16(segment_id); 3257 3258 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3259 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3260 seq_no); 3261 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3262 data_len); 3263 if (buf) { 3264 info.dest_buf = buf + offset; 3265 info.buf_len = buf_len; 3266 info.seg_start = offset; 3267 } 3268 3269 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3270 if (!rc) 3271 *seg_len = info.dest_buf_size; 3272 3273 return rc; 3274 } 3275 3276 static void 3277 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3278 struct bnxt_coredump_segment_hdr *seg_hdr, 3279 struct coredump_segment_record *seg_rec, u32 seg_len, 3280 int status, u32 duration, u32 instance) 3281 { 3282 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3283 memcpy(seg_hdr->signature, "sEgM", 4); 3284 if (seg_rec) { 3285 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3286 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3287 seg_hdr->low_version = seg_rec->version_low; 3288 seg_hdr->high_version = seg_rec->version_hi; 3289 } else { 3290 /* For hwrm_ver_get response Component id = 2 3291 * and Segment id = 0 3292 */ 3293 seg_hdr->component_id = cpu_to_le32(2); 3294 seg_hdr->segment_id = 0; 3295 } 3296 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3297 seg_hdr->length = cpu_to_le32(seg_len); 3298 seg_hdr->status = cpu_to_le32(status); 3299 seg_hdr->duration = cpu_to_le32(duration); 3300 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3301 seg_hdr->instance = cpu_to_le32(instance); 3302 } 3303 3304 static void 3305 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3306 time64_t start, s16 start_utc, u16 total_segs, 3307 int status) 3308 { 3309 time64_t end = ktime_get_real_seconds(); 3310 u32 os_ver_major = 0, os_ver_minor = 0; 3311 struct tm tm; 3312 3313 time64_to_tm(start, 0, &tm); 3314 memset(record, 0, sizeof(*record)); 3315 memcpy(record->signature, "cOrE", 4); 3316 record->flags = 0; 3317 record->low_version = 0; 3318 record->high_version = 1; 3319 record->asic_state = 0; 3320 strlcpy(record->system_name, utsname()->nodename, 3321 sizeof(record->system_name)); 3322 record->year = cpu_to_le16(tm.tm_year + 1900); 3323 record->month = cpu_to_le16(tm.tm_mon + 1); 3324 record->day = cpu_to_le16(tm.tm_mday); 3325 record->hour = cpu_to_le16(tm.tm_hour); 3326 record->minute = cpu_to_le16(tm.tm_min); 3327 record->second = cpu_to_le16(tm.tm_sec); 3328 record->utc_bias = cpu_to_le16(start_utc); 3329 strcpy(record->commandline, "ethtool -w"); 3330 record->total_segments = cpu_to_le32(total_segs); 3331 3332 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3333 record->os_ver_major = cpu_to_le32(os_ver_major); 3334 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3335 3336 strlcpy(record->os_name, utsname()->sysname, 32); 3337 time64_to_tm(end, 0, &tm); 3338 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3339 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3340 record->end_day = cpu_to_le16(tm.tm_mday); 3341 record->end_hour = cpu_to_le16(tm.tm_hour); 3342 record->end_minute = cpu_to_le16(tm.tm_min); 3343 record->end_second = cpu_to_le16(tm.tm_sec); 3344 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3345 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3346 bp->ver_resp.chip_rev << 8 | 3347 bp->ver_resp.chip_metal); 3348 record->asic_id2 = 0; 3349 record->coredump_status = cpu_to_le32(status); 3350 record->ioctl_low_version = 0; 3351 record->ioctl_high_version = 0; 3352 } 3353 3354 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3355 { 3356 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3357 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0; 3358 struct coredump_segment_record *seg_record = NULL; 3359 struct bnxt_coredump_segment_hdr seg_hdr; 3360 struct bnxt_coredump coredump = {NULL}; 3361 time64_t start_time; 3362 u16 start_utc; 3363 int rc = 0, i; 3364 3365 if (buf) 3366 buf_len = *dump_len; 3367 3368 start_time = ktime_get_real_seconds(); 3369 start_utc = sys_tz.tz_minuteswest * 60; 3370 seg_hdr_len = sizeof(seg_hdr); 3371 3372 /* First segment should be hwrm_ver_get response */ 3373 *dump_len = seg_hdr_len + ver_get_resp_len; 3374 if (buf) { 3375 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3376 0, 0, 0); 3377 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3378 offset += seg_hdr_len; 3379 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3380 offset += ver_get_resp_len; 3381 } 3382 3383 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3384 if (rc) { 3385 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3386 goto err; 3387 } 3388 3389 *dump_len += seg_hdr_len * coredump.total_segs; 3390 3391 seg_record = (struct coredump_segment_record *)coredump.data; 3392 seg_record_len = sizeof(*seg_record); 3393 3394 for (i = 0; i < coredump.total_segs; i++) { 3395 u16 comp_id = le16_to_cpu(seg_record->component_id); 3396 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3397 u32 duration = 0, seg_len = 0; 3398 unsigned long start, end; 3399 3400 if (buf && ((offset + seg_hdr_len) > 3401 BNXT_COREDUMP_BUF_LEN(buf_len))) { 3402 rc = -ENOBUFS; 3403 goto err; 3404 } 3405 3406 start = jiffies; 3407 3408 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3409 if (rc) { 3410 netdev_err(bp->dev, 3411 "Failed to initiate coredump for seg = %d\n", 3412 seg_record->segment_id); 3413 goto next_seg; 3414 } 3415 3416 /* Write segment data into the buffer */ 3417 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3418 &seg_len, buf, buf_len, 3419 offset + seg_hdr_len); 3420 if (rc && rc == -ENOBUFS) 3421 goto err; 3422 else if (rc) 3423 netdev_err(bp->dev, 3424 "Failed to retrieve coredump for seg = %d\n", 3425 seg_record->segment_id); 3426 3427 next_seg: 3428 end = jiffies; 3429 duration = jiffies_to_msecs(end - start); 3430 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3431 rc, duration, 0); 3432 3433 if (buf) { 3434 /* Write segment header into the buffer */ 3435 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3436 offset += seg_hdr_len + seg_len; 3437 } 3438 3439 *dump_len += seg_len; 3440 seg_record = 3441 (struct coredump_segment_record *)((u8 *)seg_record + 3442 seg_record_len); 3443 } 3444 3445 err: 3446 if (buf) 3447 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3448 start_utc, coredump.total_segs + 1, 3449 rc); 3450 kfree(coredump.data); 3451 *dump_len += sizeof(struct bnxt_coredump_record); 3452 if (rc == -ENOBUFS) 3453 netdev_err(bp->dev, "Firmware returned large coredump buffer\n"); 3454 return rc; 3455 } 3456 3457 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3458 { 3459 struct bnxt *bp = netdev_priv(dev); 3460 3461 if (dump->flag > BNXT_DUMP_CRASH) { 3462 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3463 return -EINVAL; 3464 } 3465 3466 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3467 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3468 return -EOPNOTSUPP; 3469 } 3470 3471 bp->dump_flag = dump->flag; 3472 return 0; 3473 } 3474 3475 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3476 { 3477 struct bnxt *bp = netdev_priv(dev); 3478 3479 if (bp->hwrm_spec_code < 0x10801) 3480 return -EOPNOTSUPP; 3481 3482 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3483 bp->ver_resp.hwrm_fw_min_8b << 16 | 3484 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3485 bp->ver_resp.hwrm_fw_rsvd_8b; 3486 3487 dump->flag = bp->dump_flag; 3488 if (bp->dump_flag == BNXT_DUMP_CRASH) 3489 dump->len = BNXT_CRASH_DUMP_LEN; 3490 else 3491 bnxt_get_coredump(bp, NULL, &dump->len); 3492 return 0; 3493 } 3494 3495 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3496 void *buf) 3497 { 3498 struct bnxt *bp = netdev_priv(dev); 3499 3500 if (bp->hwrm_spec_code < 0x10801) 3501 return -EOPNOTSUPP; 3502 3503 memset(buf, 0, dump->len); 3504 3505 dump->flag = bp->dump_flag; 3506 if (dump->flag == BNXT_DUMP_CRASH) { 3507 #ifdef CONFIG_TEE_BNXT_FW 3508 return tee_bnxt_copy_coredump(buf, 0, dump->len); 3509 #endif 3510 } else { 3511 return bnxt_get_coredump(bp, buf, &dump->len); 3512 } 3513 3514 return 0; 3515 } 3516 3517 void bnxt_ethtool_init(struct bnxt *bp) 3518 { 3519 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3520 struct hwrm_selftest_qlist_input req = {0}; 3521 struct bnxt_test_info *test_info; 3522 struct net_device *dev = bp->dev; 3523 int i, rc; 3524 3525 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3526 bnxt_get_pkgver(dev); 3527 3528 bp->num_tests = 0; 3529 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp)) 3530 return; 3531 3532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3533 mutex_lock(&bp->hwrm_cmd_lock); 3534 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3535 if (rc) 3536 goto ethtool_init_exit; 3537 3538 test_info = bp->test_info; 3539 if (!test_info) 3540 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3541 if (!test_info) 3542 goto ethtool_init_exit; 3543 3544 bp->test_info = test_info; 3545 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3546 if (bp->num_tests > BNXT_MAX_TEST) 3547 bp->num_tests = BNXT_MAX_TEST; 3548 3549 test_info->offline_mask = resp->offline_tests; 3550 test_info->timeout = le16_to_cpu(resp->test_timeout); 3551 if (!test_info->timeout) 3552 test_info->timeout = HWRM_CMD_TIMEOUT; 3553 for (i = 0; i < bp->num_tests; i++) { 3554 char *str = test_info->string[i]; 3555 char *fw_str = resp->test0_name + i * 32; 3556 3557 if (i == BNXT_MACLPBK_TEST_IDX) { 3558 strcpy(str, "Mac loopback test (offline)"); 3559 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3560 strcpy(str, "Phy loopback test (offline)"); 3561 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3562 strcpy(str, "Ext loopback test (offline)"); 3563 } else if (i == BNXT_IRQ_TEST_IDX) { 3564 strcpy(str, "Interrupt_test (offline)"); 3565 } else { 3566 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3567 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3568 if (test_info->offline_mask & (1 << i)) 3569 strncat(str, " (offline)", 3570 ETH_GSTRING_LEN - strlen(str)); 3571 else 3572 strncat(str, " (online)", 3573 ETH_GSTRING_LEN - strlen(str)); 3574 } 3575 } 3576 3577 ethtool_init_exit: 3578 mutex_unlock(&bp->hwrm_cmd_lock); 3579 } 3580 3581 void bnxt_ethtool_free(struct bnxt *bp) 3582 { 3583 kfree(bp->test_info); 3584 bp->test_info = NULL; 3585 } 3586 3587 const struct ethtool_ops bnxt_ethtool_ops = { 3588 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3589 ETHTOOL_COALESCE_MAX_FRAMES | 3590 ETHTOOL_COALESCE_USECS_IRQ | 3591 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3592 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3593 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3594 .get_link_ksettings = bnxt_get_link_ksettings, 3595 .set_link_ksettings = bnxt_set_link_ksettings, 3596 .get_pauseparam = bnxt_get_pauseparam, 3597 .set_pauseparam = bnxt_set_pauseparam, 3598 .get_drvinfo = bnxt_get_drvinfo, 3599 .get_wol = bnxt_get_wol, 3600 .set_wol = bnxt_set_wol, 3601 .get_coalesce = bnxt_get_coalesce, 3602 .set_coalesce = bnxt_set_coalesce, 3603 .get_msglevel = bnxt_get_msglevel, 3604 .set_msglevel = bnxt_set_msglevel, 3605 .get_sset_count = bnxt_get_sset_count, 3606 .get_strings = bnxt_get_strings, 3607 .get_ethtool_stats = bnxt_get_ethtool_stats, 3608 .set_ringparam = bnxt_set_ringparam, 3609 .get_ringparam = bnxt_get_ringparam, 3610 .get_channels = bnxt_get_channels, 3611 .set_channels = bnxt_set_channels, 3612 .get_rxnfc = bnxt_get_rxnfc, 3613 .set_rxnfc = bnxt_set_rxnfc, 3614 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3615 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3616 .get_rxfh = bnxt_get_rxfh, 3617 .flash_device = bnxt_flash_device, 3618 .get_eeprom_len = bnxt_get_eeprom_len, 3619 .get_eeprom = bnxt_get_eeprom, 3620 .set_eeprom = bnxt_set_eeprom, 3621 .get_link = bnxt_get_link, 3622 .get_eee = bnxt_get_eee, 3623 .set_eee = bnxt_set_eee, 3624 .get_module_info = bnxt_get_module_info, 3625 .get_module_eeprom = bnxt_get_module_eeprom, 3626 .nway_reset = bnxt_nway_reset, 3627 .set_phys_id = bnxt_set_phys_id, 3628 .self_test = bnxt_self_test, 3629 .reset = bnxt_reset, 3630 .set_dump = bnxt_set_dump, 3631 .get_dump_flag = bnxt_get_dump_flag, 3632 .get_dump_data = bnxt_get_dump_data, 3633 }; 3634