1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/linkmode.h> 15 #include <linux/interrupt.h> 16 #include <linux/pci.h> 17 #include <linux/etherdevice.h> 18 #include <linux/crc32.h> 19 #include <linux/firmware.h> 20 #include <linux/utsname.h> 21 #include <linux/time.h> 22 #include <linux/ptp_clock_kernel.h> 23 #include <linux/net_tstamp.h> 24 #include <linux/timecounter.h> 25 #include "bnxt_hsi.h" 26 #include "bnxt.h" 27 #include "bnxt_hwrm.h" 28 #include "bnxt_xdp.h" 29 #include "bnxt_ptp.h" 30 #include "bnxt_ethtool.h" 31 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 32 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 33 #include "bnxt_coredump.h" 34 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 35 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 36 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 37 38 static u32 bnxt_get_msglevel(struct net_device *dev) 39 { 40 struct bnxt *bp = netdev_priv(dev); 41 42 return bp->msg_enable; 43 } 44 45 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 46 { 47 struct bnxt *bp = netdev_priv(dev); 48 49 bp->msg_enable = value; 50 } 51 52 static int bnxt_get_coalesce(struct net_device *dev, 53 struct ethtool_coalesce *coal, 54 struct kernel_ethtool_coalesce *kernel_coal, 55 struct netlink_ext_ack *extack) 56 { 57 struct bnxt *bp = netdev_priv(dev); 58 struct bnxt_coal *hw_coal; 59 u16 mult; 60 61 memset(coal, 0, sizeof(*coal)); 62 63 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 64 65 hw_coal = &bp->rx_coal; 66 mult = hw_coal->bufs_per_record; 67 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 68 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 69 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 70 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 71 72 hw_coal = &bp->tx_coal; 73 mult = hw_coal->bufs_per_record; 74 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 75 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 76 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 77 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 78 79 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 80 81 return 0; 82 } 83 84 static int bnxt_set_coalesce(struct net_device *dev, 85 struct ethtool_coalesce *coal, 86 struct kernel_ethtool_coalesce *kernel_coal, 87 struct netlink_ext_ack *extack) 88 { 89 struct bnxt *bp = netdev_priv(dev); 90 bool update_stats = false; 91 struct bnxt_coal *hw_coal; 92 int rc = 0; 93 u16 mult; 94 95 if (coal->use_adaptive_rx_coalesce) { 96 bp->flags |= BNXT_FLAG_DIM; 97 } else { 98 if (bp->flags & BNXT_FLAG_DIM) { 99 bp->flags &= ~(BNXT_FLAG_DIM); 100 goto reset_coalesce; 101 } 102 } 103 104 hw_coal = &bp->rx_coal; 105 mult = hw_coal->bufs_per_record; 106 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 107 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 108 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 109 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 110 111 hw_coal = &bp->tx_coal; 112 mult = hw_coal->bufs_per_record; 113 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 114 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 115 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 116 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 117 118 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 119 u32 stats_ticks = coal->stats_block_coalesce_usecs; 120 121 /* Allow 0, which means disable. */ 122 if (stats_ticks) 123 stats_ticks = clamp_t(u32, stats_ticks, 124 BNXT_MIN_STATS_COAL_TICKS, 125 BNXT_MAX_STATS_COAL_TICKS); 126 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 127 bp->stats_coal_ticks = stats_ticks; 128 if (bp->stats_coal_ticks) 129 bp->current_interval = 130 bp->stats_coal_ticks * HZ / 1000000; 131 else 132 bp->current_interval = BNXT_TIMER_INTERVAL; 133 update_stats = true; 134 } 135 136 reset_coalesce: 137 if (netif_running(dev)) { 138 if (update_stats) { 139 rc = bnxt_close_nic(bp, true, false); 140 if (!rc) 141 rc = bnxt_open_nic(bp, true, false); 142 } else { 143 rc = bnxt_hwrm_set_coal(bp); 144 } 145 } 146 147 return rc; 148 } 149 150 static const char * const bnxt_ring_rx_stats_str[] = { 151 "rx_ucast_packets", 152 "rx_mcast_packets", 153 "rx_bcast_packets", 154 "rx_discards", 155 "rx_errors", 156 "rx_ucast_bytes", 157 "rx_mcast_bytes", 158 "rx_bcast_bytes", 159 }; 160 161 static const char * const bnxt_ring_tx_stats_str[] = { 162 "tx_ucast_packets", 163 "tx_mcast_packets", 164 "tx_bcast_packets", 165 "tx_errors", 166 "tx_discards", 167 "tx_ucast_bytes", 168 "tx_mcast_bytes", 169 "tx_bcast_bytes", 170 }; 171 172 static const char * const bnxt_ring_tpa_stats_str[] = { 173 "tpa_packets", 174 "tpa_bytes", 175 "tpa_events", 176 "tpa_aborts", 177 }; 178 179 static const char * const bnxt_ring_tpa2_stats_str[] = { 180 "rx_tpa_eligible_pkt", 181 "rx_tpa_eligible_bytes", 182 "rx_tpa_pkt", 183 "rx_tpa_bytes", 184 "rx_tpa_errors", 185 "rx_tpa_events", 186 }; 187 188 static const char * const bnxt_rx_sw_stats_str[] = { 189 "rx_l4_csum_errors", 190 "rx_resets", 191 "rx_buf_errors", 192 }; 193 194 static const char * const bnxt_cmn_sw_stats_str[] = { 195 "missed_irqs", 196 }; 197 198 #define BNXT_RX_STATS_ENTRY(counter) \ 199 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 200 201 #define BNXT_TX_STATS_ENTRY(counter) \ 202 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 203 204 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 205 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 206 207 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 208 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 209 210 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 211 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 212 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 213 214 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 215 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 216 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 217 218 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 219 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 220 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 221 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 222 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 223 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 224 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 225 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 226 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 227 228 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 229 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 230 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 231 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 232 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 233 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 234 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 235 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 236 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 237 238 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 240 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 241 242 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 244 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 245 246 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 247 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 255 256 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 257 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 265 266 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 269 270 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 271 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 272 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 273 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 274 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 275 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 276 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 277 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 278 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 279 280 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 281 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 282 __stringify(counter##_pri##n) } 283 284 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 285 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 286 __stringify(counter##_pri##n) } 287 288 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 289 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 290 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 291 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 292 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 293 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 294 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 295 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 296 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 297 298 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 299 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 300 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 301 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 302 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 303 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 304 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 305 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 306 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 307 308 enum { 309 RX_TOTAL_DISCARDS, 310 TX_TOTAL_DISCARDS, 311 RX_NETPOLL_DISCARDS, 312 }; 313 314 static struct { 315 u64 counter; 316 char string[ETH_GSTRING_LEN]; 317 } bnxt_sw_func_stats[] = { 318 {0, "rx_total_discard_pkts"}, 319 {0, "tx_total_discard_pkts"}, 320 {0, "rx_total_netpoll_discards"}, 321 }; 322 323 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 324 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 325 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 326 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 327 328 static const struct { 329 long offset; 330 char string[ETH_GSTRING_LEN]; 331 } bnxt_port_stats_arr[] = { 332 BNXT_RX_STATS_ENTRY(rx_64b_frames), 333 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 334 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 335 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 336 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 337 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 338 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 339 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 340 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 341 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 342 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 343 BNXT_RX_STATS_ENTRY(rx_total_frames), 344 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 345 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 346 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 347 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 348 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 349 BNXT_RX_STATS_ENTRY(rx_pause_frames), 350 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 351 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 352 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 353 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 354 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 355 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 356 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 357 BNXT_RX_STATS_ENTRY(rx_good_frames), 358 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 359 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 360 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 361 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 362 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 363 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 364 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 365 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 366 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 367 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 368 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 369 BNXT_RX_STATS_ENTRY(rx_bytes), 370 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 371 BNXT_RX_STATS_ENTRY(rx_runt_frames), 372 BNXT_RX_STATS_ENTRY(rx_stat_discard), 373 BNXT_RX_STATS_ENTRY(rx_stat_err), 374 375 BNXT_TX_STATS_ENTRY(tx_64b_frames), 376 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 377 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 378 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 379 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 380 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 381 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 382 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 383 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 384 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 385 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 386 BNXT_TX_STATS_ENTRY(tx_good_frames), 387 BNXT_TX_STATS_ENTRY(tx_total_frames), 388 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 389 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 390 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 391 BNXT_TX_STATS_ENTRY(tx_pause_frames), 392 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 393 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 394 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 395 BNXT_TX_STATS_ENTRY(tx_err), 396 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 397 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 398 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 399 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 400 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 401 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 402 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 403 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 404 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 405 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 406 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 407 BNXT_TX_STATS_ENTRY(tx_total_collisions), 408 BNXT_TX_STATS_ENTRY(tx_bytes), 409 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 410 BNXT_TX_STATS_ENTRY(tx_stat_discard), 411 BNXT_TX_STATS_ENTRY(tx_stat_error), 412 }; 413 414 static const struct { 415 long offset; 416 char string[ETH_GSTRING_LEN]; 417 } bnxt_port_stats_ext_arr[] = { 418 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 419 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 420 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 421 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 422 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 423 BNXT_RX_STATS_EXT_COS_ENTRIES, 424 BNXT_RX_STATS_EXT_PFC_ENTRIES, 425 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 426 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 427 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 428 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 429 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 430 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 431 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 432 }; 433 434 static const struct { 435 long offset; 436 char string[ETH_GSTRING_LEN]; 437 } bnxt_tx_port_stats_ext_arr[] = { 438 BNXT_TX_STATS_EXT_COS_ENTRIES, 439 BNXT_TX_STATS_EXT_PFC_ENTRIES, 440 }; 441 442 static const struct { 443 long base_off; 444 char string[ETH_GSTRING_LEN]; 445 } bnxt_rx_bytes_pri_arr[] = { 446 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 447 }; 448 449 static const struct { 450 long base_off; 451 char string[ETH_GSTRING_LEN]; 452 } bnxt_rx_pkts_pri_arr[] = { 453 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 454 }; 455 456 static const struct { 457 long base_off; 458 char string[ETH_GSTRING_LEN]; 459 } bnxt_tx_bytes_pri_arr[] = { 460 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 461 }; 462 463 static const struct { 464 long base_off; 465 char string[ETH_GSTRING_LEN]; 466 } bnxt_tx_pkts_pri_arr[] = { 467 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 468 }; 469 470 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 471 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 472 #define BNXT_NUM_STATS_PRI \ 473 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 474 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 475 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 476 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 477 478 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 479 { 480 if (BNXT_SUPPORTS_TPA(bp)) { 481 if (bp->max_tpa_v2) { 482 if (BNXT_CHIP_P5_THOR(bp)) 483 return BNXT_NUM_TPA_RING_STATS_P5; 484 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 485 } 486 return BNXT_NUM_TPA_RING_STATS; 487 } 488 return 0; 489 } 490 491 static int bnxt_get_num_ring_stats(struct bnxt *bp) 492 { 493 int rx, tx, cmn; 494 495 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 496 bnxt_get_num_tpa_ring_stats(bp); 497 tx = NUM_RING_TX_HW_STATS; 498 cmn = NUM_RING_CMN_SW_STATS; 499 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 500 cmn * bp->cp_nr_rings; 501 } 502 503 static int bnxt_get_num_stats(struct bnxt *bp) 504 { 505 int num_stats = bnxt_get_num_ring_stats(bp); 506 507 num_stats += BNXT_NUM_SW_FUNC_STATS; 508 509 if (bp->flags & BNXT_FLAG_PORT_STATS) 510 num_stats += BNXT_NUM_PORT_STATS; 511 512 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 513 num_stats += bp->fw_rx_stats_ext_size + 514 bp->fw_tx_stats_ext_size; 515 if (bp->pri2cos_valid) 516 num_stats += BNXT_NUM_STATS_PRI; 517 } 518 519 return num_stats; 520 } 521 522 static int bnxt_get_sset_count(struct net_device *dev, int sset) 523 { 524 struct bnxt *bp = netdev_priv(dev); 525 526 switch (sset) { 527 case ETH_SS_STATS: 528 return bnxt_get_num_stats(bp); 529 case ETH_SS_TEST: 530 if (!bp->num_tests) 531 return -EOPNOTSUPP; 532 return bp->num_tests; 533 default: 534 return -EOPNOTSUPP; 535 } 536 } 537 538 static bool is_rx_ring(struct bnxt *bp, int ring_num) 539 { 540 return ring_num < bp->rx_nr_rings; 541 } 542 543 static bool is_tx_ring(struct bnxt *bp, int ring_num) 544 { 545 int tx_base = 0; 546 547 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 548 tx_base = bp->rx_nr_rings; 549 550 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 551 return true; 552 return false; 553 } 554 555 static void bnxt_get_ethtool_stats(struct net_device *dev, 556 struct ethtool_stats *stats, u64 *buf) 557 { 558 u32 i, j = 0; 559 struct bnxt *bp = netdev_priv(dev); 560 u32 tpa_stats; 561 562 if (!bp->bnapi) { 563 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 564 goto skip_ring_stats; 565 } 566 567 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 568 bnxt_sw_func_stats[i].counter = 0; 569 570 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 571 for (i = 0; i < bp->cp_nr_rings; i++) { 572 struct bnxt_napi *bnapi = bp->bnapi[i]; 573 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 574 u64 *sw_stats = cpr->stats.sw_stats; 575 u64 *sw; 576 int k; 577 578 if (is_rx_ring(bp, i)) { 579 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 580 buf[j] = sw_stats[k]; 581 } 582 if (is_tx_ring(bp, i)) { 583 k = NUM_RING_RX_HW_STATS; 584 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 585 j++, k++) 586 buf[j] = sw_stats[k]; 587 } 588 if (!tpa_stats || !is_rx_ring(bp, i)) 589 goto skip_tpa_ring_stats; 590 591 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 592 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 593 tpa_stats; j++, k++) 594 buf[j] = sw_stats[k]; 595 596 skip_tpa_ring_stats: 597 sw = (u64 *)&cpr->sw_stats.rx; 598 if (is_rx_ring(bp, i)) { 599 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 600 buf[j] = sw[k]; 601 } 602 603 sw = (u64 *)&cpr->sw_stats.cmn; 604 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 605 buf[j] = sw[k]; 606 607 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 608 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts); 609 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 610 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts); 611 bnxt_sw_func_stats[RX_NETPOLL_DISCARDS].counter += 612 cpr->sw_stats.rx.rx_netpoll_discards; 613 } 614 615 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 616 buf[j] = bnxt_sw_func_stats[i].counter; 617 618 skip_ring_stats: 619 if (bp->flags & BNXT_FLAG_PORT_STATS) { 620 u64 *port_stats = bp->port_stats.sw_stats; 621 622 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 623 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 624 } 625 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 626 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 627 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 628 629 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 630 buf[j] = *(rx_port_stats_ext + 631 bnxt_port_stats_ext_arr[i].offset); 632 } 633 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 634 buf[j] = *(tx_port_stats_ext + 635 bnxt_tx_port_stats_ext_arr[i].offset); 636 } 637 if (bp->pri2cos_valid) { 638 for (i = 0; i < 8; i++, j++) { 639 long n = bnxt_rx_bytes_pri_arr[i].base_off + 640 bp->pri2cos_idx[i]; 641 642 buf[j] = *(rx_port_stats_ext + n); 643 } 644 for (i = 0; i < 8; i++, j++) { 645 long n = bnxt_rx_pkts_pri_arr[i].base_off + 646 bp->pri2cos_idx[i]; 647 648 buf[j] = *(rx_port_stats_ext + n); 649 } 650 for (i = 0; i < 8; i++, j++) { 651 long n = bnxt_tx_bytes_pri_arr[i].base_off + 652 bp->pri2cos_idx[i]; 653 654 buf[j] = *(tx_port_stats_ext + n); 655 } 656 for (i = 0; i < 8; i++, j++) { 657 long n = bnxt_tx_pkts_pri_arr[i].base_off + 658 bp->pri2cos_idx[i]; 659 660 buf[j] = *(tx_port_stats_ext + n); 661 } 662 } 663 } 664 } 665 666 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 667 { 668 struct bnxt *bp = netdev_priv(dev); 669 static const char * const *str; 670 u32 i, j, num_str; 671 672 switch (stringset) { 673 case ETH_SS_STATS: 674 for (i = 0; i < bp->cp_nr_rings; i++) { 675 if (is_rx_ring(bp, i)) { 676 num_str = NUM_RING_RX_HW_STATS; 677 for (j = 0; j < num_str; j++) { 678 sprintf(buf, "[%d]: %s", i, 679 bnxt_ring_rx_stats_str[j]); 680 buf += ETH_GSTRING_LEN; 681 } 682 } 683 if (is_tx_ring(bp, i)) { 684 num_str = NUM_RING_TX_HW_STATS; 685 for (j = 0; j < num_str; j++) { 686 sprintf(buf, "[%d]: %s", i, 687 bnxt_ring_tx_stats_str[j]); 688 buf += ETH_GSTRING_LEN; 689 } 690 } 691 num_str = bnxt_get_num_tpa_ring_stats(bp); 692 if (!num_str || !is_rx_ring(bp, i)) 693 goto skip_tpa_stats; 694 695 if (bp->max_tpa_v2) 696 str = bnxt_ring_tpa2_stats_str; 697 else 698 str = bnxt_ring_tpa_stats_str; 699 700 for (j = 0; j < num_str; j++) { 701 sprintf(buf, "[%d]: %s", i, str[j]); 702 buf += ETH_GSTRING_LEN; 703 } 704 skip_tpa_stats: 705 if (is_rx_ring(bp, i)) { 706 num_str = NUM_RING_RX_SW_STATS; 707 for (j = 0; j < num_str; j++) { 708 sprintf(buf, "[%d]: %s", i, 709 bnxt_rx_sw_stats_str[j]); 710 buf += ETH_GSTRING_LEN; 711 } 712 } 713 num_str = NUM_RING_CMN_SW_STATS; 714 for (j = 0; j < num_str; j++) { 715 sprintf(buf, "[%d]: %s", i, 716 bnxt_cmn_sw_stats_str[j]); 717 buf += ETH_GSTRING_LEN; 718 } 719 } 720 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 721 strcpy(buf, bnxt_sw_func_stats[i].string); 722 buf += ETH_GSTRING_LEN; 723 } 724 725 if (bp->flags & BNXT_FLAG_PORT_STATS) { 726 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 727 strcpy(buf, bnxt_port_stats_arr[i].string); 728 buf += ETH_GSTRING_LEN; 729 } 730 } 731 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 732 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 733 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 734 buf += ETH_GSTRING_LEN; 735 } 736 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 737 strcpy(buf, 738 bnxt_tx_port_stats_ext_arr[i].string); 739 buf += ETH_GSTRING_LEN; 740 } 741 if (bp->pri2cos_valid) { 742 for (i = 0; i < 8; i++) { 743 strcpy(buf, 744 bnxt_rx_bytes_pri_arr[i].string); 745 buf += ETH_GSTRING_LEN; 746 } 747 for (i = 0; i < 8; i++) { 748 strcpy(buf, 749 bnxt_rx_pkts_pri_arr[i].string); 750 buf += ETH_GSTRING_LEN; 751 } 752 for (i = 0; i < 8; i++) { 753 strcpy(buf, 754 bnxt_tx_bytes_pri_arr[i].string); 755 buf += ETH_GSTRING_LEN; 756 } 757 for (i = 0; i < 8; i++) { 758 strcpy(buf, 759 bnxt_tx_pkts_pri_arr[i].string); 760 buf += ETH_GSTRING_LEN; 761 } 762 } 763 } 764 break; 765 case ETH_SS_TEST: 766 if (bp->num_tests) 767 memcpy(buf, bp->test_info->string, 768 bp->num_tests * ETH_GSTRING_LEN); 769 break; 770 default: 771 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 772 stringset); 773 break; 774 } 775 } 776 777 static void bnxt_get_ringparam(struct net_device *dev, 778 struct ethtool_ringparam *ering, 779 struct kernel_ethtool_ringparam *kernel_ering, 780 struct netlink_ext_ack *extack) 781 { 782 struct bnxt *bp = netdev_priv(dev); 783 784 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 785 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 786 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 787 } else { 788 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 789 ering->rx_jumbo_max_pending = 0; 790 } 791 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 792 793 ering->rx_pending = bp->rx_ring_size; 794 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 795 ering->tx_pending = bp->tx_ring_size; 796 } 797 798 static int bnxt_set_ringparam(struct net_device *dev, 799 struct ethtool_ringparam *ering, 800 struct kernel_ethtool_ringparam *kernel_ering, 801 struct netlink_ext_ack *extack) 802 { 803 struct bnxt *bp = netdev_priv(dev); 804 805 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 806 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 807 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 808 return -EINVAL; 809 810 if (netif_running(dev)) 811 bnxt_close_nic(bp, false, false); 812 813 bp->rx_ring_size = ering->rx_pending; 814 bp->tx_ring_size = ering->tx_pending; 815 bnxt_set_ring_params(bp); 816 817 if (netif_running(dev)) 818 return bnxt_open_nic(bp, false, false); 819 820 return 0; 821 } 822 823 static void bnxt_get_channels(struct net_device *dev, 824 struct ethtool_channels *channel) 825 { 826 struct bnxt *bp = netdev_priv(dev); 827 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 828 int max_rx_rings, max_tx_rings, tcs; 829 int max_tx_sch_inputs, tx_grps; 830 831 /* Get the most up-to-date max_tx_sch_inputs. */ 832 if (netif_running(dev) && BNXT_NEW_RM(bp)) 833 bnxt_hwrm_func_resc_qcaps(bp, false); 834 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 835 836 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 837 if (max_tx_sch_inputs) 838 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 839 840 tcs = netdev_get_num_tc(dev); 841 tx_grps = max(tcs, 1); 842 if (bp->tx_nr_rings_xdp) 843 tx_grps++; 844 max_tx_rings /= tx_grps; 845 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 846 847 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 848 max_rx_rings = 0; 849 max_tx_rings = 0; 850 } 851 if (max_tx_sch_inputs) 852 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 853 854 if (tcs > 1) 855 max_tx_rings /= tcs; 856 857 channel->max_rx = max_rx_rings; 858 channel->max_tx = max_tx_rings; 859 channel->max_other = 0; 860 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 861 channel->combined_count = bp->rx_nr_rings; 862 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 863 channel->combined_count--; 864 } else { 865 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 866 channel->rx_count = bp->rx_nr_rings; 867 channel->tx_count = bp->tx_nr_rings_per_tc; 868 } 869 } 870 } 871 872 static int bnxt_set_channels(struct net_device *dev, 873 struct ethtool_channels *channel) 874 { 875 struct bnxt *bp = netdev_priv(dev); 876 int req_tx_rings, req_rx_rings, tcs; 877 bool sh = false; 878 int tx_xdp = 0; 879 int rc = 0; 880 881 if (channel->other_count) 882 return -EINVAL; 883 884 if (!channel->combined_count && 885 (!channel->rx_count || !channel->tx_count)) 886 return -EINVAL; 887 888 if (channel->combined_count && 889 (channel->rx_count || channel->tx_count)) 890 return -EINVAL; 891 892 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 893 channel->tx_count)) 894 return -EINVAL; 895 896 if (channel->combined_count) 897 sh = true; 898 899 tcs = netdev_get_num_tc(dev); 900 901 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 902 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 903 if (bp->tx_nr_rings_xdp) { 904 if (!sh) { 905 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 906 return -EINVAL; 907 } 908 tx_xdp = req_rx_rings; 909 } 910 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 911 if (rc) { 912 netdev_warn(dev, "Unable to allocate the requested rings\n"); 913 return rc; 914 } 915 916 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 917 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 918 netif_is_rxfh_configured(dev)) { 919 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 920 return -EINVAL; 921 } 922 923 if (netif_running(dev)) { 924 if (BNXT_PF(bp)) { 925 /* TODO CHIMP_FW: Send message to all VF's 926 * before PF unload 927 */ 928 } 929 rc = bnxt_close_nic(bp, true, false); 930 if (rc) { 931 netdev_err(bp->dev, "Set channel failure rc :%x\n", 932 rc); 933 return rc; 934 } 935 } 936 937 if (sh) { 938 bp->flags |= BNXT_FLAG_SHARED_RINGS; 939 bp->rx_nr_rings = channel->combined_count; 940 bp->tx_nr_rings_per_tc = channel->combined_count; 941 } else { 942 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 943 bp->rx_nr_rings = channel->rx_count; 944 bp->tx_nr_rings_per_tc = channel->tx_count; 945 } 946 bp->tx_nr_rings_xdp = tx_xdp; 947 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 948 if (tcs > 1) 949 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 950 951 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 952 bp->tx_nr_rings + bp->rx_nr_rings; 953 954 /* After changing number of rx channels, update NTUPLE feature. */ 955 netdev_update_features(dev); 956 if (netif_running(dev)) { 957 rc = bnxt_open_nic(bp, true, false); 958 if ((!rc) && BNXT_PF(bp)) { 959 /* TODO CHIMP_FW: Send message to all VF's 960 * to renable 961 */ 962 } 963 } else { 964 rc = bnxt_reserve_rings(bp, true); 965 } 966 967 return rc; 968 } 969 970 #ifdef CONFIG_RFS_ACCEL 971 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 972 u32 *rule_locs) 973 { 974 int i, j = 0; 975 976 cmd->data = bp->ntp_fltr_count; 977 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 978 struct hlist_head *head; 979 struct bnxt_ntuple_filter *fltr; 980 981 head = &bp->ntp_fltr_hash_tbl[i]; 982 rcu_read_lock(); 983 hlist_for_each_entry_rcu(fltr, head, hash) { 984 if (j == cmd->rule_cnt) 985 break; 986 rule_locs[j++] = fltr->sw_id; 987 } 988 rcu_read_unlock(); 989 if (j == cmd->rule_cnt) 990 break; 991 } 992 cmd->rule_cnt = j; 993 return 0; 994 } 995 996 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 997 { 998 struct ethtool_rx_flow_spec *fs = 999 (struct ethtool_rx_flow_spec *)&cmd->fs; 1000 struct bnxt_ntuple_filter *fltr; 1001 struct flow_keys *fkeys; 1002 int i, rc = -EINVAL; 1003 1004 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1005 return rc; 1006 1007 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1008 struct hlist_head *head; 1009 1010 head = &bp->ntp_fltr_hash_tbl[i]; 1011 rcu_read_lock(); 1012 hlist_for_each_entry_rcu(fltr, head, hash) { 1013 if (fltr->sw_id == fs->location) 1014 goto fltr_found; 1015 } 1016 rcu_read_unlock(); 1017 } 1018 return rc; 1019 1020 fltr_found: 1021 fkeys = &fltr->fkeys; 1022 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1023 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1024 fs->flow_type = TCP_V4_FLOW; 1025 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1026 fs->flow_type = UDP_V4_FLOW; 1027 else 1028 goto fltr_err; 1029 1030 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1031 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1032 1033 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1034 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1035 1036 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1037 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1038 1039 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1040 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1041 } else { 1042 int i; 1043 1044 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1045 fs->flow_type = TCP_V6_FLOW; 1046 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1047 fs->flow_type = UDP_V6_FLOW; 1048 else 1049 goto fltr_err; 1050 1051 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1052 fkeys->addrs.v6addrs.src; 1053 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1054 fkeys->addrs.v6addrs.dst; 1055 for (i = 0; i < 4; i++) { 1056 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1057 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1058 } 1059 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1060 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1061 1062 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1063 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1064 } 1065 1066 fs->ring_cookie = fltr->rxq; 1067 rc = 0; 1068 1069 fltr_err: 1070 rcu_read_unlock(); 1071 1072 return rc; 1073 } 1074 #endif 1075 1076 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1077 { 1078 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1079 return RXH_IP_SRC | RXH_IP_DST; 1080 return 0; 1081 } 1082 1083 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1084 { 1085 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1086 return RXH_IP_SRC | RXH_IP_DST; 1087 return 0; 1088 } 1089 1090 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1091 { 1092 cmd->data = 0; 1093 switch (cmd->flow_type) { 1094 case TCP_V4_FLOW: 1095 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1096 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1097 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1098 cmd->data |= get_ethtool_ipv4_rss(bp); 1099 break; 1100 case UDP_V4_FLOW: 1101 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1102 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1103 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1104 fallthrough; 1105 case SCTP_V4_FLOW: 1106 case AH_ESP_V4_FLOW: 1107 case AH_V4_FLOW: 1108 case ESP_V4_FLOW: 1109 case IPV4_FLOW: 1110 cmd->data |= get_ethtool_ipv4_rss(bp); 1111 break; 1112 1113 case TCP_V6_FLOW: 1114 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1115 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1116 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1117 cmd->data |= get_ethtool_ipv6_rss(bp); 1118 break; 1119 case UDP_V6_FLOW: 1120 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1121 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1122 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1123 fallthrough; 1124 case SCTP_V6_FLOW: 1125 case AH_ESP_V6_FLOW: 1126 case AH_V6_FLOW: 1127 case ESP_V6_FLOW: 1128 case IPV6_FLOW: 1129 cmd->data |= get_ethtool_ipv6_rss(bp); 1130 break; 1131 } 1132 return 0; 1133 } 1134 1135 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1136 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1137 1138 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1139 { 1140 u32 rss_hash_cfg = bp->rss_hash_cfg; 1141 int tuple, rc = 0; 1142 1143 if (cmd->data == RXH_4TUPLE) 1144 tuple = 4; 1145 else if (cmd->data == RXH_2TUPLE) 1146 tuple = 2; 1147 else if (!cmd->data) 1148 tuple = 0; 1149 else 1150 return -EINVAL; 1151 1152 if (cmd->flow_type == TCP_V4_FLOW) { 1153 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1154 if (tuple == 4) 1155 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1156 } else if (cmd->flow_type == UDP_V4_FLOW) { 1157 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1158 return -EINVAL; 1159 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1160 if (tuple == 4) 1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1162 } else if (cmd->flow_type == TCP_V6_FLOW) { 1163 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1164 if (tuple == 4) 1165 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1166 } else if (cmd->flow_type == UDP_V6_FLOW) { 1167 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1168 return -EINVAL; 1169 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1170 if (tuple == 4) 1171 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1172 } else if (tuple == 4) { 1173 return -EINVAL; 1174 } 1175 1176 switch (cmd->flow_type) { 1177 case TCP_V4_FLOW: 1178 case UDP_V4_FLOW: 1179 case SCTP_V4_FLOW: 1180 case AH_ESP_V4_FLOW: 1181 case AH_V4_FLOW: 1182 case ESP_V4_FLOW: 1183 case IPV4_FLOW: 1184 if (tuple == 2) 1185 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1186 else if (!tuple) 1187 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1188 break; 1189 1190 case TCP_V6_FLOW: 1191 case UDP_V6_FLOW: 1192 case SCTP_V6_FLOW: 1193 case AH_ESP_V6_FLOW: 1194 case AH_V6_FLOW: 1195 case ESP_V6_FLOW: 1196 case IPV6_FLOW: 1197 if (tuple == 2) 1198 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1199 else if (!tuple) 1200 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1201 break; 1202 } 1203 1204 if (bp->rss_hash_cfg == rss_hash_cfg) 1205 return 0; 1206 1207 bp->rss_hash_cfg = rss_hash_cfg; 1208 if (netif_running(bp->dev)) { 1209 bnxt_close_nic(bp, false, false); 1210 rc = bnxt_open_nic(bp, false, false); 1211 } 1212 return rc; 1213 } 1214 1215 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1216 u32 *rule_locs) 1217 { 1218 struct bnxt *bp = netdev_priv(dev); 1219 int rc = 0; 1220 1221 switch (cmd->cmd) { 1222 #ifdef CONFIG_RFS_ACCEL 1223 case ETHTOOL_GRXRINGS: 1224 cmd->data = bp->rx_nr_rings; 1225 break; 1226 1227 case ETHTOOL_GRXCLSRLCNT: 1228 cmd->rule_cnt = bp->ntp_fltr_count; 1229 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1230 break; 1231 1232 case ETHTOOL_GRXCLSRLALL: 1233 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1234 break; 1235 1236 case ETHTOOL_GRXCLSRULE: 1237 rc = bnxt_grxclsrule(bp, cmd); 1238 break; 1239 #endif 1240 1241 case ETHTOOL_GRXFH: 1242 rc = bnxt_grxfh(bp, cmd); 1243 break; 1244 1245 default: 1246 rc = -EOPNOTSUPP; 1247 break; 1248 } 1249 1250 return rc; 1251 } 1252 1253 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1254 { 1255 struct bnxt *bp = netdev_priv(dev); 1256 int rc; 1257 1258 switch (cmd->cmd) { 1259 case ETHTOOL_SRXFH: 1260 rc = bnxt_srxfh(bp, cmd); 1261 break; 1262 1263 default: 1264 rc = -EOPNOTSUPP; 1265 break; 1266 } 1267 return rc; 1268 } 1269 1270 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1271 { 1272 struct bnxt *bp = netdev_priv(dev); 1273 1274 if (bp->flags & BNXT_FLAG_CHIP_P5) 1275 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1276 return HW_HASH_INDEX_SIZE; 1277 } 1278 1279 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1280 { 1281 return HW_HASH_KEY_SIZE; 1282 } 1283 1284 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1285 u8 *hfunc) 1286 { 1287 struct bnxt *bp = netdev_priv(dev); 1288 struct bnxt_vnic_info *vnic; 1289 u32 i, tbl_size; 1290 1291 if (hfunc) 1292 *hfunc = ETH_RSS_HASH_TOP; 1293 1294 if (!bp->vnic_info) 1295 return 0; 1296 1297 vnic = &bp->vnic_info[0]; 1298 if (indir && bp->rss_indir_tbl) { 1299 tbl_size = bnxt_get_rxfh_indir_size(dev); 1300 for (i = 0; i < tbl_size; i++) 1301 indir[i] = bp->rss_indir_tbl[i]; 1302 } 1303 1304 if (key && vnic->rss_hash_key) 1305 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1306 1307 return 0; 1308 } 1309 1310 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1311 const u8 *key, const u8 hfunc) 1312 { 1313 struct bnxt *bp = netdev_priv(dev); 1314 int rc = 0; 1315 1316 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1317 return -EOPNOTSUPP; 1318 1319 if (key) 1320 return -EOPNOTSUPP; 1321 1322 if (indir) { 1323 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1324 1325 for (i = 0; i < tbl_size; i++) 1326 bp->rss_indir_tbl[i] = indir[i]; 1327 pad = bp->rss_indir_tbl_entries - tbl_size; 1328 if (pad) 1329 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1330 } 1331 1332 if (netif_running(bp->dev)) { 1333 bnxt_close_nic(bp, false, false); 1334 rc = bnxt_open_nic(bp, false, false); 1335 } 1336 return rc; 1337 } 1338 1339 static void bnxt_get_drvinfo(struct net_device *dev, 1340 struct ethtool_drvinfo *info) 1341 { 1342 struct bnxt *bp = netdev_priv(dev); 1343 1344 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1345 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1346 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1347 info->n_stats = bnxt_get_num_stats(bp); 1348 info->testinfo_len = bp->num_tests; 1349 /* TODO CHIMP_FW: eeprom dump details */ 1350 info->eedump_len = 0; 1351 /* TODO CHIMP FW: reg dump details */ 1352 info->regdump_len = 0; 1353 } 1354 1355 static int bnxt_get_regs_len(struct net_device *dev) 1356 { 1357 struct bnxt *bp = netdev_priv(dev); 1358 int reg_len; 1359 1360 if (!BNXT_PF(bp)) 1361 return -EOPNOTSUPP; 1362 1363 reg_len = BNXT_PXP_REG_LEN; 1364 1365 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1366 reg_len += sizeof(struct pcie_ctx_hw_stats); 1367 1368 return reg_len; 1369 } 1370 1371 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1372 void *_p) 1373 { 1374 struct pcie_ctx_hw_stats *hw_pcie_stats; 1375 struct hwrm_pcie_qstats_input *req; 1376 struct bnxt *bp = netdev_priv(dev); 1377 dma_addr_t hw_pcie_stats_addr; 1378 int rc; 1379 1380 regs->version = 0; 1381 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1382 1383 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1384 return; 1385 1386 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1387 return; 1388 1389 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1390 &hw_pcie_stats_addr); 1391 if (!hw_pcie_stats) { 1392 hwrm_req_drop(bp, req); 1393 return; 1394 } 1395 1396 regs->version = 1; 1397 hwrm_req_hold(bp, req); /* hold on to slice */ 1398 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1399 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1400 rc = hwrm_req_send(bp, req); 1401 if (!rc) { 1402 __le64 *src = (__le64 *)hw_pcie_stats; 1403 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1404 int i; 1405 1406 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1407 dst[i] = le64_to_cpu(src[i]); 1408 } 1409 hwrm_req_drop(bp, req); 1410 } 1411 1412 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1413 { 1414 struct bnxt *bp = netdev_priv(dev); 1415 1416 wol->supported = 0; 1417 wol->wolopts = 0; 1418 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1419 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1420 wol->supported = WAKE_MAGIC; 1421 if (bp->wol) 1422 wol->wolopts = WAKE_MAGIC; 1423 } 1424 } 1425 1426 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1427 { 1428 struct bnxt *bp = netdev_priv(dev); 1429 1430 if (wol->wolopts & ~WAKE_MAGIC) 1431 return -EINVAL; 1432 1433 if (wol->wolopts & WAKE_MAGIC) { 1434 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1435 return -EINVAL; 1436 if (!bp->wol) { 1437 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1438 return -EBUSY; 1439 bp->wol = 1; 1440 } 1441 } else { 1442 if (bp->wol) { 1443 if (bnxt_hwrm_free_wol_fltr(bp)) 1444 return -EBUSY; 1445 bp->wol = 0; 1446 } 1447 } 1448 return 0; 1449 } 1450 1451 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1452 { 1453 u32 speed_mask = 0; 1454 1455 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1456 /* set the advertised speeds */ 1457 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1458 speed_mask |= ADVERTISED_100baseT_Full; 1459 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1460 speed_mask |= ADVERTISED_1000baseT_Full; 1461 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1462 speed_mask |= ADVERTISED_2500baseX_Full; 1463 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1464 speed_mask |= ADVERTISED_10000baseT_Full; 1465 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1466 speed_mask |= ADVERTISED_40000baseCR4_Full; 1467 1468 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1469 speed_mask |= ADVERTISED_Pause; 1470 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1471 speed_mask |= ADVERTISED_Asym_Pause; 1472 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1473 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1474 1475 return speed_mask; 1476 } 1477 1478 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1479 { \ 1480 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1481 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1482 100baseT_Full); \ 1483 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1484 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1485 1000baseT_Full); \ 1486 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1487 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1488 10000baseT_Full); \ 1489 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1490 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1491 25000baseCR_Full); \ 1492 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1493 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1494 40000baseCR4_Full);\ 1495 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1496 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1497 50000baseCR2_Full);\ 1498 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1499 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1500 100000baseCR4_Full);\ 1501 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1502 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1503 Pause); \ 1504 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1505 ethtool_link_ksettings_add_link_mode( \ 1506 lk_ksettings, name, Asym_Pause);\ 1507 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1508 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1509 Asym_Pause); \ 1510 } \ 1511 } 1512 1513 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1514 { \ 1515 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1516 100baseT_Full) || \ 1517 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1518 100baseT_Half)) \ 1519 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1520 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1521 1000baseT_Full) || \ 1522 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1523 1000baseT_Half)) \ 1524 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1525 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1526 10000baseT_Full)) \ 1527 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1528 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1529 25000baseCR_Full)) \ 1530 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1531 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1532 40000baseCR4_Full)) \ 1533 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1534 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1535 50000baseCR2_Full)) \ 1536 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1537 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1538 100000baseCR4_Full)) \ 1539 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1540 } 1541 1542 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1543 { \ 1544 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \ 1545 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1546 50000baseCR_Full); \ 1547 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \ 1548 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1549 100000baseCR2_Full);\ 1550 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \ 1551 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1552 200000baseCR4_Full);\ 1553 } 1554 1555 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1556 { \ 1557 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1558 50000baseCR_Full)) \ 1559 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \ 1560 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1561 100000baseCR2_Full)) \ 1562 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \ 1563 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1564 200000baseCR4_Full)) \ 1565 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \ 1566 } 1567 1568 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1569 struct ethtool_link_ksettings *lk_ksettings) 1570 { 1571 u16 fec_cfg = link_info->fec_cfg; 1572 1573 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1574 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1575 lk_ksettings->link_modes.advertising); 1576 return; 1577 } 1578 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1579 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1580 lk_ksettings->link_modes.advertising); 1581 if (fec_cfg & BNXT_FEC_ENC_RS) 1582 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1583 lk_ksettings->link_modes.advertising); 1584 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1585 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1586 lk_ksettings->link_modes.advertising); 1587 } 1588 1589 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1590 struct ethtool_link_ksettings *lk_ksettings) 1591 { 1592 u16 fw_speeds = link_info->advertising; 1593 u8 fw_pause = 0; 1594 1595 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1596 fw_pause = link_info->auto_pause_setting; 1597 1598 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1599 fw_speeds = link_info->advertising_pam4; 1600 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising); 1601 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 1602 } 1603 1604 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1605 struct ethtool_link_ksettings *lk_ksettings) 1606 { 1607 u16 fw_speeds = link_info->lp_auto_link_speeds; 1608 u8 fw_pause = 0; 1609 1610 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1611 fw_pause = link_info->lp_pause; 1612 1613 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1614 lp_advertising); 1615 fw_speeds = link_info->lp_auto_pam4_link_speeds; 1616 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising); 1617 } 1618 1619 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1620 struct ethtool_link_ksettings *lk_ksettings) 1621 { 1622 u16 fec_cfg = link_info->fec_cfg; 1623 1624 if (fec_cfg & BNXT_FEC_NONE) { 1625 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1626 lk_ksettings->link_modes.supported); 1627 return; 1628 } 1629 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1630 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1631 lk_ksettings->link_modes.supported); 1632 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1633 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1634 lk_ksettings->link_modes.supported); 1635 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1636 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1637 lk_ksettings->link_modes.supported); 1638 } 1639 1640 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1641 struct ethtool_link_ksettings *lk_ksettings) 1642 { 1643 u16 fw_speeds = link_info->support_speeds; 1644 1645 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1646 fw_speeds = link_info->support_pam4_speeds; 1647 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported); 1648 1649 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1650 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1651 Asym_Pause); 1652 1653 if (link_info->support_auto_speeds || 1654 link_info->support_pam4_auto_speeds) 1655 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1656 Autoneg); 1657 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 1658 } 1659 1660 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1661 { 1662 switch (fw_link_speed) { 1663 case BNXT_LINK_SPEED_100MB: 1664 return SPEED_100; 1665 case BNXT_LINK_SPEED_1GB: 1666 return SPEED_1000; 1667 case BNXT_LINK_SPEED_2_5GB: 1668 return SPEED_2500; 1669 case BNXT_LINK_SPEED_10GB: 1670 return SPEED_10000; 1671 case BNXT_LINK_SPEED_20GB: 1672 return SPEED_20000; 1673 case BNXT_LINK_SPEED_25GB: 1674 return SPEED_25000; 1675 case BNXT_LINK_SPEED_40GB: 1676 return SPEED_40000; 1677 case BNXT_LINK_SPEED_50GB: 1678 return SPEED_50000; 1679 case BNXT_LINK_SPEED_100GB: 1680 return SPEED_100000; 1681 default: 1682 return SPEED_UNKNOWN; 1683 } 1684 } 1685 1686 static int bnxt_get_link_ksettings(struct net_device *dev, 1687 struct ethtool_link_ksettings *lk_ksettings) 1688 { 1689 struct bnxt *bp = netdev_priv(dev); 1690 struct bnxt_link_info *link_info = &bp->link_info; 1691 struct ethtool_link_settings *base = &lk_ksettings->base; 1692 u32 ethtool_speed; 1693 1694 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1695 mutex_lock(&bp->link_lock); 1696 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1697 1698 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1699 if (link_info->autoneg) { 1700 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1701 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1702 advertising, Autoneg); 1703 base->autoneg = AUTONEG_ENABLE; 1704 base->duplex = DUPLEX_UNKNOWN; 1705 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1706 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1707 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1708 base->duplex = DUPLEX_FULL; 1709 else 1710 base->duplex = DUPLEX_HALF; 1711 } 1712 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1713 } else { 1714 base->autoneg = AUTONEG_DISABLE; 1715 ethtool_speed = 1716 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1717 base->duplex = DUPLEX_HALF; 1718 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1719 base->duplex = DUPLEX_FULL; 1720 } 1721 base->speed = ethtool_speed; 1722 1723 base->port = PORT_NONE; 1724 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1725 base->port = PORT_TP; 1726 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1727 TP); 1728 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1729 TP); 1730 } else { 1731 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1732 FIBRE); 1733 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1734 FIBRE); 1735 1736 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1737 base->port = PORT_DA; 1738 else if (link_info->media_type == 1739 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1740 base->port = PORT_FIBRE; 1741 } 1742 base->phy_address = link_info->phy_addr; 1743 mutex_unlock(&bp->link_lock); 1744 1745 return 0; 1746 } 1747 1748 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed) 1749 { 1750 struct bnxt *bp = netdev_priv(dev); 1751 struct bnxt_link_info *link_info = &bp->link_info; 1752 u16 support_pam4_spds = link_info->support_pam4_speeds; 1753 u16 support_spds = link_info->support_speeds; 1754 u8 sig_mode = BNXT_SIG_MODE_NRZ; 1755 u16 fw_speed = 0; 1756 1757 switch (ethtool_speed) { 1758 case SPEED_100: 1759 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1760 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 1761 break; 1762 case SPEED_1000: 1763 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1764 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 1765 break; 1766 case SPEED_2500: 1767 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1768 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 1769 break; 1770 case SPEED_10000: 1771 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1772 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 1773 break; 1774 case SPEED_20000: 1775 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1776 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 1777 break; 1778 case SPEED_25000: 1779 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1780 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 1781 break; 1782 case SPEED_40000: 1783 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1784 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 1785 break; 1786 case SPEED_50000: 1787 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) { 1788 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 1789 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 1790 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 1791 sig_mode = BNXT_SIG_MODE_PAM4; 1792 } 1793 break; 1794 case SPEED_100000: 1795 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) { 1796 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 1797 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 1798 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 1799 sig_mode = BNXT_SIG_MODE_PAM4; 1800 } 1801 break; 1802 case SPEED_200000: 1803 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 1804 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 1805 sig_mode = BNXT_SIG_MODE_PAM4; 1806 } 1807 break; 1808 } 1809 1810 if (!fw_speed) { 1811 netdev_err(dev, "unsupported speed!\n"); 1812 return -EINVAL; 1813 } 1814 1815 if (link_info->req_link_speed == fw_speed && 1816 link_info->req_signal_mode == sig_mode && 1817 link_info->autoneg == 0) 1818 return -EALREADY; 1819 1820 link_info->req_link_speed = fw_speed; 1821 link_info->req_signal_mode = sig_mode; 1822 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1823 link_info->autoneg = 0; 1824 link_info->advertising = 0; 1825 link_info->advertising_pam4 = 0; 1826 1827 return 0; 1828 } 1829 1830 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1831 { 1832 u16 fw_speed_mask = 0; 1833 1834 /* only support autoneg at speed 100, 1000, and 10000 */ 1835 if (advertising & (ADVERTISED_100baseT_Full | 1836 ADVERTISED_100baseT_Half)) { 1837 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1838 } 1839 if (advertising & (ADVERTISED_1000baseT_Full | 1840 ADVERTISED_1000baseT_Half)) { 1841 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1842 } 1843 if (advertising & ADVERTISED_10000baseT_Full) 1844 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1845 1846 if (advertising & ADVERTISED_40000baseCR4_Full) 1847 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1848 1849 return fw_speed_mask; 1850 } 1851 1852 static int bnxt_set_link_ksettings(struct net_device *dev, 1853 const struct ethtool_link_ksettings *lk_ksettings) 1854 { 1855 struct bnxt *bp = netdev_priv(dev); 1856 struct bnxt_link_info *link_info = &bp->link_info; 1857 const struct ethtool_link_settings *base = &lk_ksettings->base; 1858 bool set_pause = false; 1859 u32 speed; 1860 int rc = 0; 1861 1862 if (!BNXT_PHY_CFG_ABLE(bp)) 1863 return -EOPNOTSUPP; 1864 1865 mutex_lock(&bp->link_lock); 1866 if (base->autoneg == AUTONEG_ENABLE) { 1867 link_info->advertising = 0; 1868 link_info->advertising_pam4 = 0; 1869 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings, 1870 advertising); 1871 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4, 1872 lk_ksettings, advertising); 1873 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1874 if (!link_info->advertising && !link_info->advertising_pam4) { 1875 link_info->advertising = link_info->support_auto_speeds; 1876 link_info->advertising_pam4 = 1877 link_info->support_pam4_auto_speeds; 1878 } 1879 /* any change to autoneg will cause link change, therefore the 1880 * driver should put back the original pause setting in autoneg 1881 */ 1882 set_pause = true; 1883 } else { 1884 u8 phy_type = link_info->phy_type; 1885 1886 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1887 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1888 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1889 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1890 rc = -EINVAL; 1891 goto set_setting_exit; 1892 } 1893 if (base->duplex == DUPLEX_HALF) { 1894 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1895 rc = -EINVAL; 1896 goto set_setting_exit; 1897 } 1898 speed = base->speed; 1899 rc = bnxt_force_link_speed(dev, speed); 1900 if (rc) { 1901 if (rc == -EALREADY) 1902 rc = 0; 1903 goto set_setting_exit; 1904 } 1905 } 1906 1907 if (netif_running(dev)) 1908 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1909 1910 set_setting_exit: 1911 mutex_unlock(&bp->link_lock); 1912 return rc; 1913 } 1914 1915 static int bnxt_get_fecparam(struct net_device *dev, 1916 struct ethtool_fecparam *fec) 1917 { 1918 struct bnxt *bp = netdev_priv(dev); 1919 struct bnxt_link_info *link_info; 1920 u8 active_fec; 1921 u16 fec_cfg; 1922 1923 link_info = &bp->link_info; 1924 fec_cfg = link_info->fec_cfg; 1925 active_fec = link_info->active_fec_sig_mode & 1926 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 1927 if (fec_cfg & BNXT_FEC_NONE) { 1928 fec->fec = ETHTOOL_FEC_NONE; 1929 fec->active_fec = ETHTOOL_FEC_NONE; 1930 return 0; 1931 } 1932 if (fec_cfg & BNXT_FEC_AUTONEG) 1933 fec->fec |= ETHTOOL_FEC_AUTO; 1934 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1935 fec->fec |= ETHTOOL_FEC_BASER; 1936 if (fec_cfg & BNXT_FEC_ENC_RS) 1937 fec->fec |= ETHTOOL_FEC_RS; 1938 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1939 fec->fec |= ETHTOOL_FEC_LLRS; 1940 1941 switch (active_fec) { 1942 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 1943 fec->active_fec |= ETHTOOL_FEC_BASER; 1944 break; 1945 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 1946 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 1947 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 1948 fec->active_fec |= ETHTOOL_FEC_RS; 1949 break; 1950 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 1951 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 1952 fec->active_fec |= ETHTOOL_FEC_LLRS; 1953 break; 1954 } 1955 return 0; 1956 } 1957 1958 static void bnxt_get_fec_stats(struct net_device *dev, 1959 struct ethtool_fec_stats *fec_stats) 1960 { 1961 struct bnxt *bp = netdev_priv(dev); 1962 u64 *rx; 1963 1964 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 1965 return; 1966 1967 rx = bp->rx_port_stats_ext.sw_stats; 1968 fec_stats->corrected_bits.total = 1969 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 1970 } 1971 1972 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 1973 u32 fec) 1974 { 1975 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 1976 1977 if (fec & ETHTOOL_FEC_BASER) 1978 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 1979 else if (fec & ETHTOOL_FEC_RS) 1980 fw_fec |= BNXT_FEC_RS_ON(link_info); 1981 else if (fec & ETHTOOL_FEC_LLRS) 1982 fw_fec |= BNXT_FEC_LLRS_ON; 1983 return fw_fec; 1984 } 1985 1986 static int bnxt_set_fecparam(struct net_device *dev, 1987 struct ethtool_fecparam *fecparam) 1988 { 1989 struct hwrm_port_phy_cfg_input *req; 1990 struct bnxt *bp = netdev_priv(dev); 1991 struct bnxt_link_info *link_info; 1992 u32 new_cfg, fec = fecparam->fec; 1993 u16 fec_cfg; 1994 int rc; 1995 1996 link_info = &bp->link_info; 1997 fec_cfg = link_info->fec_cfg; 1998 if (fec_cfg & BNXT_FEC_NONE) 1999 return -EOPNOTSUPP; 2000 2001 if (fec & ETHTOOL_FEC_OFF) { 2002 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 2003 BNXT_FEC_ALL_OFF(link_info); 2004 goto apply_fec; 2005 } 2006 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2007 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2008 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2009 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2010 return -EINVAL; 2011 2012 if (fec & ETHTOOL_FEC_AUTO) { 2013 if (!link_info->autoneg) 2014 return -EINVAL; 2015 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2016 } else { 2017 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2018 } 2019 2020 apply_fec: 2021 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2022 if (rc) 2023 return rc; 2024 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2025 rc = hwrm_req_send(bp, req); 2026 /* update current settings */ 2027 if (!rc) { 2028 mutex_lock(&bp->link_lock); 2029 bnxt_update_link(bp, false); 2030 mutex_unlock(&bp->link_lock); 2031 } 2032 return rc; 2033 } 2034 2035 static void bnxt_get_pauseparam(struct net_device *dev, 2036 struct ethtool_pauseparam *epause) 2037 { 2038 struct bnxt *bp = netdev_priv(dev); 2039 struct bnxt_link_info *link_info = &bp->link_info; 2040 2041 if (BNXT_VF(bp)) 2042 return; 2043 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2044 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2045 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2046 } 2047 2048 static void bnxt_get_pause_stats(struct net_device *dev, 2049 struct ethtool_pause_stats *epstat) 2050 { 2051 struct bnxt *bp = netdev_priv(dev); 2052 u64 *rx, *tx; 2053 2054 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2055 return; 2056 2057 rx = bp->port_stats.sw_stats; 2058 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2059 2060 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2061 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2062 } 2063 2064 static int bnxt_set_pauseparam(struct net_device *dev, 2065 struct ethtool_pauseparam *epause) 2066 { 2067 int rc = 0; 2068 struct bnxt *bp = netdev_priv(dev); 2069 struct bnxt_link_info *link_info = &bp->link_info; 2070 2071 if (!BNXT_PHY_CFG_ABLE(bp)) 2072 return -EOPNOTSUPP; 2073 2074 mutex_lock(&bp->link_lock); 2075 if (epause->autoneg) { 2076 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2077 rc = -EINVAL; 2078 goto pause_exit; 2079 } 2080 2081 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2082 if (bp->hwrm_spec_code >= 0x10201) 2083 link_info->req_flow_ctrl = 2084 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 2085 } else { 2086 /* when transition from auto pause to force pause, 2087 * force a link change 2088 */ 2089 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2090 link_info->force_link_chng = true; 2091 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2092 link_info->req_flow_ctrl = 0; 2093 } 2094 if (epause->rx_pause) 2095 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2096 2097 if (epause->tx_pause) 2098 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2099 2100 if (netif_running(dev)) 2101 rc = bnxt_hwrm_set_pause(bp); 2102 2103 pause_exit: 2104 mutex_unlock(&bp->link_lock); 2105 return rc; 2106 } 2107 2108 static u32 bnxt_get_link(struct net_device *dev) 2109 { 2110 struct bnxt *bp = netdev_priv(dev); 2111 2112 /* TODO: handle MF, VF, driver close case */ 2113 return bp->link_info.link_up; 2114 } 2115 2116 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2117 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2118 { 2119 struct hwrm_nvm_get_dev_info_output *resp; 2120 struct hwrm_nvm_get_dev_info_input *req; 2121 int rc; 2122 2123 if (BNXT_VF(bp)) 2124 return -EOPNOTSUPP; 2125 2126 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2127 if (rc) 2128 return rc; 2129 2130 resp = hwrm_req_hold(bp, req); 2131 rc = hwrm_req_send(bp, req); 2132 if (!rc) 2133 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2134 hwrm_req_drop(bp, req); 2135 return rc; 2136 } 2137 2138 static void bnxt_print_admin_err(struct bnxt *bp) 2139 { 2140 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2141 } 2142 2143 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2144 u16 ext, u16 *index, u32 *item_length, 2145 u32 *data_length); 2146 2147 static int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2148 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2149 u32 dir_item_len, const u8 *data, 2150 size_t data_len) 2151 { 2152 struct bnxt *bp = netdev_priv(dev); 2153 struct hwrm_nvm_write_input *req; 2154 int rc; 2155 2156 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2157 if (rc) 2158 return rc; 2159 2160 if (data_len && data) { 2161 dma_addr_t dma_handle; 2162 u8 *kmem; 2163 2164 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2165 if (!kmem) { 2166 hwrm_req_drop(bp, req); 2167 return -ENOMEM; 2168 } 2169 2170 req->dir_data_length = cpu_to_le32(data_len); 2171 2172 memcpy(kmem, data, data_len); 2173 req->host_src_addr = cpu_to_le64(dma_handle); 2174 } 2175 2176 hwrm_req_timeout(bp, req, FLASH_NVRAM_TIMEOUT); 2177 req->dir_type = cpu_to_le16(dir_type); 2178 req->dir_ordinal = cpu_to_le16(dir_ordinal); 2179 req->dir_ext = cpu_to_le16(dir_ext); 2180 req->dir_attr = cpu_to_le16(dir_attr); 2181 req->dir_item_length = cpu_to_le32(dir_item_len); 2182 rc = hwrm_req_send(bp, req); 2183 2184 if (rc == -EACCES) 2185 bnxt_print_admin_err(bp); 2186 return rc; 2187 } 2188 2189 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2190 u8 self_reset, u8 flags) 2191 { 2192 struct bnxt *bp = netdev_priv(dev); 2193 struct hwrm_fw_reset_input *req; 2194 int rc; 2195 2196 if (!bnxt_hwrm_reset_permitted(bp)) { 2197 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 2198 return -EPERM; 2199 } 2200 2201 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 2202 if (rc) 2203 return rc; 2204 2205 req->embedded_proc_type = proc_type; 2206 req->selfrst_status = self_reset; 2207 req->flags = flags; 2208 2209 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2210 rc = hwrm_req_send_silent(bp, req); 2211 } else { 2212 rc = hwrm_req_send(bp, req); 2213 if (rc == -EACCES) 2214 bnxt_print_admin_err(bp); 2215 } 2216 return rc; 2217 } 2218 2219 static int bnxt_firmware_reset(struct net_device *dev, 2220 enum bnxt_nvm_directory_type dir_type) 2221 { 2222 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2223 u8 proc_type, flags = 0; 2224 2225 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2226 /* (e.g. when firmware isn't already running) */ 2227 switch (dir_type) { 2228 case BNX_DIR_TYPE_CHIMP_PATCH: 2229 case BNX_DIR_TYPE_BOOTCODE: 2230 case BNX_DIR_TYPE_BOOTCODE_2: 2231 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2232 /* Self-reset ChiMP upon next PCIe reset: */ 2233 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2234 break; 2235 case BNX_DIR_TYPE_APE_FW: 2236 case BNX_DIR_TYPE_APE_PATCH: 2237 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2238 /* Self-reset APE upon next PCIe reset: */ 2239 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2240 break; 2241 case BNX_DIR_TYPE_KONG_FW: 2242 case BNX_DIR_TYPE_KONG_PATCH: 2243 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2244 break; 2245 case BNX_DIR_TYPE_BONO_FW: 2246 case BNX_DIR_TYPE_BONO_PATCH: 2247 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2248 break; 2249 default: 2250 return -EINVAL; 2251 } 2252 2253 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2254 } 2255 2256 static int bnxt_firmware_reset_chip(struct net_device *dev) 2257 { 2258 struct bnxt *bp = netdev_priv(dev); 2259 u8 flags = 0; 2260 2261 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2262 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2263 2264 return bnxt_hwrm_firmware_reset(dev, 2265 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2266 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2267 flags); 2268 } 2269 2270 static int bnxt_firmware_reset_ap(struct net_device *dev) 2271 { 2272 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2273 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2274 0); 2275 } 2276 2277 static int bnxt_flash_firmware(struct net_device *dev, 2278 u16 dir_type, 2279 const u8 *fw_data, 2280 size_t fw_size) 2281 { 2282 int rc = 0; 2283 u16 code_type; 2284 u32 stored_crc; 2285 u32 calculated_crc; 2286 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2287 2288 switch (dir_type) { 2289 case BNX_DIR_TYPE_BOOTCODE: 2290 case BNX_DIR_TYPE_BOOTCODE_2: 2291 code_type = CODE_BOOT; 2292 break; 2293 case BNX_DIR_TYPE_CHIMP_PATCH: 2294 code_type = CODE_CHIMP_PATCH; 2295 break; 2296 case BNX_DIR_TYPE_APE_FW: 2297 code_type = CODE_MCTP_PASSTHRU; 2298 break; 2299 case BNX_DIR_TYPE_APE_PATCH: 2300 code_type = CODE_APE_PATCH; 2301 break; 2302 case BNX_DIR_TYPE_KONG_FW: 2303 code_type = CODE_KONG_FW; 2304 break; 2305 case BNX_DIR_TYPE_KONG_PATCH: 2306 code_type = CODE_KONG_PATCH; 2307 break; 2308 case BNX_DIR_TYPE_BONO_FW: 2309 code_type = CODE_BONO_FW; 2310 break; 2311 case BNX_DIR_TYPE_BONO_PATCH: 2312 code_type = CODE_BONO_PATCH; 2313 break; 2314 default: 2315 netdev_err(dev, "Unsupported directory entry type: %u\n", 2316 dir_type); 2317 return -EINVAL; 2318 } 2319 if (fw_size < sizeof(struct bnxt_fw_header)) { 2320 netdev_err(dev, "Invalid firmware file size: %u\n", 2321 (unsigned int)fw_size); 2322 return -EINVAL; 2323 } 2324 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2325 netdev_err(dev, "Invalid firmware signature: %08X\n", 2326 le32_to_cpu(header->signature)); 2327 return -EINVAL; 2328 } 2329 if (header->code_type != code_type) { 2330 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2331 code_type, header->code_type); 2332 return -EINVAL; 2333 } 2334 if (header->device != DEVICE_CUMULUS_FAMILY) { 2335 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2336 DEVICE_CUMULUS_FAMILY, header->device); 2337 return -EINVAL; 2338 } 2339 /* Confirm the CRC32 checksum of the file: */ 2340 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2341 sizeof(stored_crc))); 2342 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2343 if (calculated_crc != stored_crc) { 2344 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2345 (unsigned long)stored_crc, 2346 (unsigned long)calculated_crc); 2347 return -EINVAL; 2348 } 2349 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2350 0, 0, 0, fw_data, fw_size); 2351 if (rc == 0) /* Firmware update successful */ 2352 rc = bnxt_firmware_reset(dev, dir_type); 2353 2354 return rc; 2355 } 2356 2357 static int bnxt_flash_microcode(struct net_device *dev, 2358 u16 dir_type, 2359 const u8 *fw_data, 2360 size_t fw_size) 2361 { 2362 struct bnxt_ucode_trailer *trailer; 2363 u32 calculated_crc; 2364 u32 stored_crc; 2365 int rc = 0; 2366 2367 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2368 netdev_err(dev, "Invalid microcode file size: %u\n", 2369 (unsigned int)fw_size); 2370 return -EINVAL; 2371 } 2372 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2373 sizeof(*trailer))); 2374 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2375 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2376 le32_to_cpu(trailer->sig)); 2377 return -EINVAL; 2378 } 2379 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2380 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2381 dir_type, le16_to_cpu(trailer->dir_type)); 2382 return -EINVAL; 2383 } 2384 if (le16_to_cpu(trailer->trailer_length) < 2385 sizeof(struct bnxt_ucode_trailer)) { 2386 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2387 le16_to_cpu(trailer->trailer_length)); 2388 return -EINVAL; 2389 } 2390 2391 /* Confirm the CRC32 checksum of the file: */ 2392 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2393 sizeof(stored_crc))); 2394 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2395 if (calculated_crc != stored_crc) { 2396 netdev_err(dev, 2397 "CRC32 (%08lX) does not match calculated: %08lX\n", 2398 (unsigned long)stored_crc, 2399 (unsigned long)calculated_crc); 2400 return -EINVAL; 2401 } 2402 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2403 0, 0, 0, fw_data, fw_size); 2404 2405 return rc; 2406 } 2407 2408 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2409 { 2410 switch (dir_type) { 2411 case BNX_DIR_TYPE_CHIMP_PATCH: 2412 case BNX_DIR_TYPE_BOOTCODE: 2413 case BNX_DIR_TYPE_BOOTCODE_2: 2414 case BNX_DIR_TYPE_APE_FW: 2415 case BNX_DIR_TYPE_APE_PATCH: 2416 case BNX_DIR_TYPE_KONG_FW: 2417 case BNX_DIR_TYPE_KONG_PATCH: 2418 case BNX_DIR_TYPE_BONO_FW: 2419 case BNX_DIR_TYPE_BONO_PATCH: 2420 return true; 2421 } 2422 2423 return false; 2424 } 2425 2426 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2427 { 2428 switch (dir_type) { 2429 case BNX_DIR_TYPE_AVS: 2430 case BNX_DIR_TYPE_EXP_ROM_MBA: 2431 case BNX_DIR_TYPE_PCIE: 2432 case BNX_DIR_TYPE_TSCF_UCODE: 2433 case BNX_DIR_TYPE_EXT_PHY: 2434 case BNX_DIR_TYPE_CCM: 2435 case BNX_DIR_TYPE_ISCSI_BOOT: 2436 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2437 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2438 return true; 2439 } 2440 2441 return false; 2442 } 2443 2444 static bool bnxt_dir_type_is_executable(u16 dir_type) 2445 { 2446 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2447 bnxt_dir_type_is_other_exec_format(dir_type); 2448 } 2449 2450 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2451 u16 dir_type, 2452 const char *filename) 2453 { 2454 const struct firmware *fw; 2455 int rc; 2456 2457 rc = request_firmware(&fw, filename, &dev->dev); 2458 if (rc != 0) { 2459 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2460 rc, filename); 2461 return rc; 2462 } 2463 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2464 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2465 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2466 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2467 else 2468 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2469 0, 0, 0, fw->data, fw->size); 2470 release_firmware(fw); 2471 return rc; 2472 } 2473 2474 #define BNXT_PKG_DMA_SIZE 0x40000 2475 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2476 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2477 2478 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2479 u32 install_type) 2480 { 2481 struct hwrm_nvm_install_update_input *install; 2482 struct hwrm_nvm_install_update_output *resp; 2483 struct hwrm_nvm_modify_input *modify; 2484 struct bnxt *bp = netdev_priv(dev); 2485 bool defrag_attempted = false; 2486 dma_addr_t dma_handle; 2487 u8 *kmem = NULL; 2488 u32 modify_len; 2489 u32 item_len; 2490 u16 index; 2491 int rc; 2492 2493 bnxt_hwrm_fw_set_time(bp); 2494 2495 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 2496 if (rc) 2497 return rc; 2498 2499 /* Try allocating a large DMA buffer first. Older fw will 2500 * cause excessive NVRAM erases when using small blocks. 2501 */ 2502 modify_len = roundup_pow_of_two(fw->size); 2503 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 2504 while (1) { 2505 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 2506 if (!kmem && modify_len > PAGE_SIZE) 2507 modify_len /= 2; 2508 else 2509 break; 2510 } 2511 if (!kmem) { 2512 hwrm_req_drop(bp, modify); 2513 return -ENOMEM; 2514 } 2515 2516 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 2517 if (rc) { 2518 hwrm_req_drop(bp, modify); 2519 return rc; 2520 } 2521 2522 hwrm_req_timeout(bp, modify, FLASH_PACKAGE_TIMEOUT); 2523 hwrm_req_timeout(bp, install, INSTALL_PACKAGE_TIMEOUT); 2524 2525 hwrm_req_hold(bp, modify); 2526 modify->host_src_addr = cpu_to_le64(dma_handle); 2527 2528 resp = hwrm_req_hold(bp, install); 2529 if ((install_type & 0xffff) == 0) 2530 install_type >>= 16; 2531 install->install_type = cpu_to_le32(install_type); 2532 2533 do { 2534 u32 copied = 0, len = modify_len; 2535 2536 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2537 BNX_DIR_ORDINAL_FIRST, 2538 BNX_DIR_EXT_NONE, 2539 &index, &item_len, NULL); 2540 if (rc) { 2541 netdev_err(dev, "PKG update area not created in nvram\n"); 2542 break; 2543 } 2544 if (fw->size > item_len) { 2545 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2546 (unsigned long)fw->size); 2547 rc = -EFBIG; 2548 break; 2549 } 2550 2551 modify->dir_idx = cpu_to_le16(index); 2552 2553 if (fw->size > modify_len) 2554 modify->flags = BNXT_NVM_MORE_FLAG; 2555 while (copied < fw->size) { 2556 u32 balance = fw->size - copied; 2557 2558 if (balance <= modify_len) { 2559 len = balance; 2560 if (copied) 2561 modify->flags |= BNXT_NVM_LAST_FLAG; 2562 } 2563 memcpy(kmem, fw->data + copied, len); 2564 modify->len = cpu_to_le32(len); 2565 modify->offset = cpu_to_le32(copied); 2566 rc = hwrm_req_send(bp, modify); 2567 if (rc) 2568 goto pkg_abort; 2569 copied += len; 2570 } 2571 2572 rc = hwrm_req_send_silent(bp, install); 2573 2574 if (defrag_attempted) { 2575 /* We have tried to defragment already in the previous 2576 * iteration. Return with the result for INSTALL_UPDATE 2577 */ 2578 break; 2579 } 2580 2581 if (rc && ((struct hwrm_err_output *)resp)->cmd_err == 2582 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2583 install->flags = 2584 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2585 2586 rc = hwrm_req_send_silent(bp, install); 2587 2588 if (rc && ((struct hwrm_err_output *)resp)->cmd_err == 2589 NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 2590 /* FW has cleared NVM area, driver will create 2591 * UPDATE directory and try the flash again 2592 */ 2593 defrag_attempted = true; 2594 install->flags = 0; 2595 rc = bnxt_flash_nvram(bp->dev, 2596 BNX_DIR_TYPE_UPDATE, 2597 BNX_DIR_ORDINAL_FIRST, 2598 0, 0, item_len, NULL, 0); 2599 } else if (rc) { 2600 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x\n", rc); 2601 } 2602 } else if (rc) { 2603 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x\n", rc); 2604 } 2605 } while (defrag_attempted && !rc); 2606 2607 pkg_abort: 2608 hwrm_req_drop(bp, modify); 2609 hwrm_req_drop(bp, install); 2610 2611 if (resp->result) { 2612 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2613 (s8)resp->result, (int)resp->problem_item); 2614 rc = -ENOPKG; 2615 } 2616 if (rc == -EACCES) 2617 bnxt_print_admin_err(bp); 2618 return rc; 2619 } 2620 2621 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2622 u32 install_type) 2623 { 2624 const struct firmware *fw; 2625 int rc; 2626 2627 rc = request_firmware(&fw, filename, &dev->dev); 2628 if (rc != 0) { 2629 netdev_err(dev, "PKG error %d requesting file: %s\n", 2630 rc, filename); 2631 return rc; 2632 } 2633 2634 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type); 2635 2636 release_firmware(fw); 2637 2638 return rc; 2639 } 2640 2641 static int bnxt_flash_device(struct net_device *dev, 2642 struct ethtool_flash *flash) 2643 { 2644 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2645 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2646 return -EINVAL; 2647 } 2648 2649 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2650 flash->region > 0xffff) 2651 return bnxt_flash_package_from_file(dev, flash->data, 2652 flash->region); 2653 2654 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2655 } 2656 2657 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2658 { 2659 struct hwrm_nvm_get_dir_info_output *output; 2660 struct hwrm_nvm_get_dir_info_input *req; 2661 struct bnxt *bp = netdev_priv(dev); 2662 int rc; 2663 2664 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 2665 if (rc) 2666 return rc; 2667 2668 output = hwrm_req_hold(bp, req); 2669 rc = hwrm_req_send(bp, req); 2670 if (!rc) { 2671 *entries = le32_to_cpu(output->entries); 2672 *length = le32_to_cpu(output->entry_length); 2673 } 2674 hwrm_req_drop(bp, req); 2675 return rc; 2676 } 2677 2678 static int bnxt_get_eeprom_len(struct net_device *dev) 2679 { 2680 struct bnxt *bp = netdev_priv(dev); 2681 2682 if (BNXT_VF(bp)) 2683 return 0; 2684 2685 /* The -1 return value allows the entire 32-bit range of offsets to be 2686 * passed via the ethtool command-line utility. 2687 */ 2688 return -1; 2689 } 2690 2691 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2692 { 2693 struct bnxt *bp = netdev_priv(dev); 2694 int rc; 2695 u32 dir_entries; 2696 u32 entry_length; 2697 u8 *buf; 2698 size_t buflen; 2699 dma_addr_t dma_handle; 2700 struct hwrm_nvm_get_dir_entries_input *req; 2701 2702 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2703 if (rc != 0) 2704 return rc; 2705 2706 if (!dir_entries || !entry_length) 2707 return -EIO; 2708 2709 /* Insert 2 bytes of directory info (count and size of entries) */ 2710 if (len < 2) 2711 return -EINVAL; 2712 2713 *data++ = dir_entries; 2714 *data++ = entry_length; 2715 len -= 2; 2716 memset(data, 0xff, len); 2717 2718 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 2719 if (rc) 2720 return rc; 2721 2722 buflen = dir_entries * entry_length; 2723 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 2724 if (!buf) { 2725 hwrm_req_drop(bp, req); 2726 return -ENOMEM; 2727 } 2728 req->host_dest_addr = cpu_to_le64(dma_handle); 2729 2730 hwrm_req_hold(bp, req); /* hold the slice */ 2731 rc = hwrm_req_send(bp, req); 2732 if (rc == 0) 2733 memcpy(data, buf, len > buflen ? buflen : len); 2734 hwrm_req_drop(bp, req); 2735 return rc; 2736 } 2737 2738 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2739 u32 length, u8 *data) 2740 { 2741 struct bnxt *bp = netdev_priv(dev); 2742 int rc; 2743 u8 *buf; 2744 dma_addr_t dma_handle; 2745 struct hwrm_nvm_read_input *req; 2746 2747 if (!length) 2748 return -EINVAL; 2749 2750 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 2751 if (rc) 2752 return rc; 2753 2754 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 2755 if (!buf) { 2756 hwrm_req_drop(bp, req); 2757 return -ENOMEM; 2758 } 2759 2760 req->host_dest_addr = cpu_to_le64(dma_handle); 2761 req->dir_idx = cpu_to_le16(index); 2762 req->offset = cpu_to_le32(offset); 2763 req->len = cpu_to_le32(length); 2764 2765 hwrm_req_hold(bp, req); /* hold the slice */ 2766 rc = hwrm_req_send(bp, req); 2767 if (rc == 0) 2768 memcpy(data, buf, length); 2769 hwrm_req_drop(bp, req); 2770 return rc; 2771 } 2772 2773 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2774 u16 ext, u16 *index, u32 *item_length, 2775 u32 *data_length) 2776 { 2777 struct hwrm_nvm_find_dir_entry_output *output; 2778 struct hwrm_nvm_find_dir_entry_input *req; 2779 struct bnxt *bp = netdev_priv(dev); 2780 int rc; 2781 2782 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 2783 if (rc) 2784 return rc; 2785 2786 req->enables = 0; 2787 req->dir_idx = 0; 2788 req->dir_type = cpu_to_le16(type); 2789 req->dir_ordinal = cpu_to_le16(ordinal); 2790 req->dir_ext = cpu_to_le16(ext); 2791 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2792 output = hwrm_req_hold(bp, req); 2793 rc = hwrm_req_send_silent(bp, req); 2794 if (rc == 0) { 2795 if (index) 2796 *index = le16_to_cpu(output->dir_idx); 2797 if (item_length) 2798 *item_length = le32_to_cpu(output->dir_item_length); 2799 if (data_length) 2800 *data_length = le32_to_cpu(output->dir_data_length); 2801 } 2802 hwrm_req_drop(bp, req); 2803 return rc; 2804 } 2805 2806 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2807 { 2808 char *retval = NULL; 2809 char *p; 2810 char *value; 2811 int field = 0; 2812 2813 if (datalen < 1) 2814 return NULL; 2815 /* null-terminate the log data (removing last '\n'): */ 2816 data[datalen - 1] = 0; 2817 for (p = data; *p != 0; p++) { 2818 field = 0; 2819 retval = NULL; 2820 while (*p != 0 && *p != '\n') { 2821 value = p; 2822 while (*p != 0 && *p != '\t' && *p != '\n') 2823 p++; 2824 if (field == desired_field) 2825 retval = value; 2826 if (*p != '\t') 2827 break; 2828 *p = 0; 2829 field++; 2830 p++; 2831 } 2832 if (*p == 0) 2833 break; 2834 *p = 0; 2835 } 2836 return retval; 2837 } 2838 2839 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 2840 { 2841 struct bnxt *bp = netdev_priv(dev); 2842 u16 index = 0; 2843 char *pkgver; 2844 u32 pkglen; 2845 u8 *pkgbuf; 2846 int rc; 2847 2848 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2849 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2850 &index, NULL, &pkglen); 2851 if (rc) 2852 return rc; 2853 2854 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2855 if (!pkgbuf) { 2856 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2857 pkglen); 2858 return -ENOMEM; 2859 } 2860 2861 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 2862 if (rc) 2863 goto err; 2864 2865 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2866 pkglen); 2867 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 2868 strscpy(ver, pkgver, size); 2869 else 2870 rc = -ENOENT; 2871 2872 err: 2873 kfree(pkgbuf); 2874 2875 return rc; 2876 } 2877 2878 static void bnxt_get_pkgver(struct net_device *dev) 2879 { 2880 struct bnxt *bp = netdev_priv(dev); 2881 char buf[FW_VER_STR_LEN]; 2882 int len; 2883 2884 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 2885 len = strlen(bp->fw_ver_str); 2886 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2887 "/pkg %s", buf); 2888 } 2889 } 2890 2891 static int bnxt_get_eeprom(struct net_device *dev, 2892 struct ethtool_eeprom *eeprom, 2893 u8 *data) 2894 { 2895 u32 index; 2896 u32 offset; 2897 2898 if (eeprom->offset == 0) /* special offset value to get directory */ 2899 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2900 2901 index = eeprom->offset >> 24; 2902 offset = eeprom->offset & 0xffffff; 2903 2904 if (index == 0) { 2905 netdev_err(dev, "unsupported index value: %d\n", index); 2906 return -EINVAL; 2907 } 2908 2909 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2910 } 2911 2912 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2913 { 2914 struct hwrm_nvm_erase_dir_entry_input *req; 2915 struct bnxt *bp = netdev_priv(dev); 2916 int rc; 2917 2918 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 2919 if (rc) 2920 return rc; 2921 2922 req->dir_idx = cpu_to_le16(index); 2923 return hwrm_req_send(bp, req); 2924 } 2925 2926 static int bnxt_set_eeprom(struct net_device *dev, 2927 struct ethtool_eeprom *eeprom, 2928 u8 *data) 2929 { 2930 struct bnxt *bp = netdev_priv(dev); 2931 u8 index, dir_op; 2932 u16 type, ext, ordinal, attr; 2933 2934 if (!BNXT_PF(bp)) { 2935 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2936 return -EINVAL; 2937 } 2938 2939 type = eeprom->magic >> 16; 2940 2941 if (type == 0xffff) { /* special value for directory operations */ 2942 index = eeprom->magic & 0xff; 2943 dir_op = eeprom->magic >> 8; 2944 if (index == 0) 2945 return -EINVAL; 2946 switch (dir_op) { 2947 case 0x0e: /* erase */ 2948 if (eeprom->offset != ~eeprom->magic) 2949 return -EINVAL; 2950 return bnxt_erase_nvram_directory(dev, index - 1); 2951 default: 2952 return -EINVAL; 2953 } 2954 } 2955 2956 /* Create or re-write an NVM item: */ 2957 if (bnxt_dir_type_is_executable(type)) 2958 return -EOPNOTSUPP; 2959 ext = eeprom->magic & 0xffff; 2960 ordinal = eeprom->offset >> 16; 2961 attr = eeprom->offset & 0xffff; 2962 2963 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 2964 eeprom->len); 2965 } 2966 2967 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2968 { 2969 struct bnxt *bp = netdev_priv(dev); 2970 struct ethtool_eee *eee = &bp->eee; 2971 struct bnxt_link_info *link_info = &bp->link_info; 2972 u32 advertising; 2973 int rc = 0; 2974 2975 if (!BNXT_PHY_CFG_ABLE(bp)) 2976 return -EOPNOTSUPP; 2977 2978 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 2979 return -EOPNOTSUPP; 2980 2981 mutex_lock(&bp->link_lock); 2982 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2983 if (!edata->eee_enabled) 2984 goto eee_ok; 2985 2986 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2987 netdev_warn(dev, "EEE requires autoneg\n"); 2988 rc = -EINVAL; 2989 goto eee_exit; 2990 } 2991 if (edata->tx_lpi_enabled) { 2992 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2993 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2994 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2995 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2996 rc = -EINVAL; 2997 goto eee_exit; 2998 } else if (!bp->lpi_tmr_hi) { 2999 edata->tx_lpi_timer = eee->tx_lpi_timer; 3000 } 3001 } 3002 if (!edata->advertised) { 3003 edata->advertised = advertising & eee->supported; 3004 } else if (edata->advertised & ~advertising) { 3005 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3006 edata->advertised, advertising); 3007 rc = -EINVAL; 3008 goto eee_exit; 3009 } 3010 3011 eee->advertised = edata->advertised; 3012 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3013 eee->tx_lpi_timer = edata->tx_lpi_timer; 3014 eee_ok: 3015 eee->eee_enabled = edata->eee_enabled; 3016 3017 if (netif_running(dev)) 3018 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3019 3020 eee_exit: 3021 mutex_unlock(&bp->link_lock); 3022 return rc; 3023 } 3024 3025 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3026 { 3027 struct bnxt *bp = netdev_priv(dev); 3028 3029 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3030 return -EOPNOTSUPP; 3031 3032 *edata = bp->eee; 3033 if (!bp->eee.eee_enabled) { 3034 /* Preserve tx_lpi_timer so that the last value will be used 3035 * by default when it is re-enabled. 3036 */ 3037 edata->advertised = 0; 3038 edata->tx_lpi_enabled = 0; 3039 } 3040 3041 if (!bp->eee.eee_active) 3042 edata->lp_advertised = 0; 3043 3044 return 0; 3045 } 3046 3047 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3048 u16 page_number, u16 start_addr, 3049 u16 data_length, u8 *buf) 3050 { 3051 struct hwrm_port_phy_i2c_read_output *output; 3052 struct hwrm_port_phy_i2c_read_input *req; 3053 int rc, byte_offset = 0; 3054 3055 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3056 if (rc) 3057 return rc; 3058 3059 output = hwrm_req_hold(bp, req); 3060 req->i2c_slave_addr = i2c_addr; 3061 req->page_number = cpu_to_le16(page_number); 3062 req->port_id = cpu_to_le16(bp->pf.port_id); 3063 do { 3064 u16 xfer_size; 3065 3066 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3067 data_length -= xfer_size; 3068 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3069 req->data_length = xfer_size; 3070 req->enables = cpu_to_le32(start_addr + byte_offset ? 3071 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 3072 rc = hwrm_req_send(bp, req); 3073 if (!rc) 3074 memcpy(buf + byte_offset, output->data, xfer_size); 3075 byte_offset += xfer_size; 3076 } while (!rc && data_length > 0); 3077 hwrm_req_drop(bp, req); 3078 3079 return rc; 3080 } 3081 3082 static int bnxt_get_module_info(struct net_device *dev, 3083 struct ethtool_modinfo *modinfo) 3084 { 3085 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 3086 struct bnxt *bp = netdev_priv(dev); 3087 int rc; 3088 3089 /* No point in going further if phy status indicates 3090 * module is not inserted or if it is powered down or 3091 * if it is of type 10GBase-T 3092 */ 3093 if (bp->link_info.module_status > 3094 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3095 return -EOPNOTSUPP; 3096 3097 /* This feature is not supported in older firmware versions */ 3098 if (bp->hwrm_spec_code < 0x10202) 3099 return -EOPNOTSUPP; 3100 3101 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3102 SFF_DIAG_SUPPORT_OFFSET + 1, 3103 data); 3104 if (!rc) { 3105 u8 module_id = data[0]; 3106 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 3107 3108 switch (module_id) { 3109 case SFF_MODULE_ID_SFP: 3110 modinfo->type = ETH_MODULE_SFF_8472; 3111 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3112 if (!diag_supported) 3113 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3114 break; 3115 case SFF_MODULE_ID_QSFP: 3116 case SFF_MODULE_ID_QSFP_PLUS: 3117 modinfo->type = ETH_MODULE_SFF_8436; 3118 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3119 break; 3120 case SFF_MODULE_ID_QSFP28: 3121 modinfo->type = ETH_MODULE_SFF_8636; 3122 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 3123 break; 3124 default: 3125 rc = -EOPNOTSUPP; 3126 break; 3127 } 3128 } 3129 return rc; 3130 } 3131 3132 static int bnxt_get_module_eeprom(struct net_device *dev, 3133 struct ethtool_eeprom *eeprom, 3134 u8 *data) 3135 { 3136 struct bnxt *bp = netdev_priv(dev); 3137 u16 start = eeprom->offset, length = eeprom->len; 3138 int rc = 0; 3139 3140 memset(data, 0, eeprom->len); 3141 3142 /* Read A0 portion of the EEPROM */ 3143 if (start < ETH_MODULE_SFF_8436_LEN) { 3144 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3145 length = ETH_MODULE_SFF_8436_LEN - start; 3146 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3147 start, length, data); 3148 if (rc) 3149 return rc; 3150 start += length; 3151 data += length; 3152 length = eeprom->len - length; 3153 } 3154 3155 /* Read A2 portion of the EEPROM */ 3156 if (length) { 3157 start -= ETH_MODULE_SFF_8436_LEN; 3158 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 3159 start, length, data); 3160 } 3161 return rc; 3162 } 3163 3164 static int bnxt_nway_reset(struct net_device *dev) 3165 { 3166 int rc = 0; 3167 3168 struct bnxt *bp = netdev_priv(dev); 3169 struct bnxt_link_info *link_info = &bp->link_info; 3170 3171 if (!BNXT_PHY_CFG_ABLE(bp)) 3172 return -EOPNOTSUPP; 3173 3174 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3175 return -EINVAL; 3176 3177 if (netif_running(dev)) 3178 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3179 3180 return rc; 3181 } 3182 3183 static int bnxt_set_phys_id(struct net_device *dev, 3184 enum ethtool_phys_id_state state) 3185 { 3186 struct hwrm_port_led_cfg_input *req; 3187 struct bnxt *bp = netdev_priv(dev); 3188 struct bnxt_pf_info *pf = &bp->pf; 3189 struct bnxt_led_cfg *led_cfg; 3190 u8 led_state; 3191 __le16 duration; 3192 int rc, i; 3193 3194 if (!bp->num_leds || BNXT_VF(bp)) 3195 return -EOPNOTSUPP; 3196 3197 if (state == ETHTOOL_ID_ACTIVE) { 3198 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3199 duration = cpu_to_le16(500); 3200 } else if (state == ETHTOOL_ID_INACTIVE) { 3201 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3202 duration = cpu_to_le16(0); 3203 } else { 3204 return -EINVAL; 3205 } 3206 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 3207 if (rc) 3208 return rc; 3209 3210 req->port_id = cpu_to_le16(pf->port_id); 3211 req->num_leds = bp->num_leds; 3212 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 3213 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3214 req->enables |= BNXT_LED_DFLT_ENABLES(i); 3215 led_cfg->led_id = bp->leds[i].led_id; 3216 led_cfg->led_state = led_state; 3217 led_cfg->led_blink_on = duration; 3218 led_cfg->led_blink_off = duration; 3219 led_cfg->led_group_id = bp->leds[i].led_group_id; 3220 } 3221 return hwrm_req_send(bp, req); 3222 } 3223 3224 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3225 { 3226 struct hwrm_selftest_irq_input *req; 3227 int rc; 3228 3229 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 3230 if (rc) 3231 return rc; 3232 3233 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3234 return hwrm_req_send(bp, req); 3235 } 3236 3237 static int bnxt_test_irq(struct bnxt *bp) 3238 { 3239 int i; 3240 3241 for (i = 0; i < bp->cp_nr_rings; i++) { 3242 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3243 int rc; 3244 3245 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3246 if (rc) 3247 return rc; 3248 } 3249 return 0; 3250 } 3251 3252 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3253 { 3254 struct hwrm_port_mac_cfg_input *req; 3255 int rc; 3256 3257 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 3258 if (rc) 3259 return rc; 3260 3261 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3262 if (enable) 3263 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3264 else 3265 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3266 return hwrm_req_send(bp, req); 3267 } 3268 3269 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3270 { 3271 struct hwrm_port_phy_qcaps_output *resp; 3272 struct hwrm_port_phy_qcaps_input *req; 3273 int rc; 3274 3275 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 3276 if (rc) 3277 return rc; 3278 3279 resp = hwrm_req_hold(bp, req); 3280 rc = hwrm_req_send(bp, req); 3281 if (!rc) 3282 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3283 3284 hwrm_req_drop(bp, req); 3285 return rc; 3286 } 3287 3288 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3289 struct hwrm_port_phy_cfg_input *req) 3290 { 3291 struct bnxt_link_info *link_info = &bp->link_info; 3292 u16 fw_advertising; 3293 u16 fw_speed; 3294 int rc; 3295 3296 if (!link_info->autoneg || 3297 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 3298 return 0; 3299 3300 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3301 if (rc) 3302 return rc; 3303 3304 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3305 if (bp->link_info.link_up) 3306 fw_speed = bp->link_info.link_speed; 3307 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3308 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3309 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3310 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3311 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3312 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3313 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3314 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3315 3316 req->force_link_speed = cpu_to_le16(fw_speed); 3317 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3318 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3319 rc = hwrm_req_send(bp, req); 3320 req->flags = 0; 3321 req->force_link_speed = cpu_to_le16(0); 3322 return rc; 3323 } 3324 3325 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3326 { 3327 struct hwrm_port_phy_cfg_input *req; 3328 int rc; 3329 3330 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3331 if (rc) 3332 return rc; 3333 3334 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 3335 hwrm_req_hold(bp, req); 3336 3337 if (enable) { 3338 bnxt_disable_an_for_lpbk(bp, req); 3339 if (ext) 3340 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3341 else 3342 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3343 } else { 3344 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3345 } 3346 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3347 rc = hwrm_req_send(bp, req); 3348 hwrm_req_drop(bp, req); 3349 return rc; 3350 } 3351 3352 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3353 u32 raw_cons, int pkt_size) 3354 { 3355 struct bnxt_napi *bnapi = cpr->bnapi; 3356 struct bnxt_rx_ring_info *rxr; 3357 struct bnxt_sw_rx_bd *rx_buf; 3358 struct rx_cmp *rxcmp; 3359 u16 cp_cons, cons; 3360 u8 *data; 3361 u32 len; 3362 int i; 3363 3364 rxr = bnapi->rx_ring; 3365 cp_cons = RING_CMP(raw_cons); 3366 rxcmp = (struct rx_cmp *) 3367 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3368 cons = rxcmp->rx_cmp_opaque; 3369 rx_buf = &rxr->rx_buf_ring[cons]; 3370 data = rx_buf->data_ptr; 3371 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3372 if (len != pkt_size) 3373 return -EIO; 3374 i = ETH_ALEN; 3375 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3376 return -EIO; 3377 i += ETH_ALEN; 3378 for ( ; i < pkt_size; i++) { 3379 if (data[i] != (u8)(i & 0xff)) 3380 return -EIO; 3381 } 3382 return 0; 3383 } 3384 3385 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3386 int pkt_size) 3387 { 3388 struct tx_cmp *txcmp; 3389 int rc = -EIO; 3390 u32 raw_cons; 3391 u32 cons; 3392 int i; 3393 3394 raw_cons = cpr->cp_raw_cons; 3395 for (i = 0; i < 200; i++) { 3396 cons = RING_CMP(raw_cons); 3397 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3398 3399 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3400 udelay(5); 3401 continue; 3402 } 3403 3404 /* The valid test of the entry must be done first before 3405 * reading any further. 3406 */ 3407 dma_rmb(); 3408 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3409 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3410 raw_cons = NEXT_RAW_CMP(raw_cons); 3411 raw_cons = NEXT_RAW_CMP(raw_cons); 3412 break; 3413 } 3414 raw_cons = NEXT_RAW_CMP(raw_cons); 3415 } 3416 cpr->cp_raw_cons = raw_cons; 3417 return rc; 3418 } 3419 3420 static int bnxt_run_loopback(struct bnxt *bp) 3421 { 3422 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3423 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3424 struct bnxt_cp_ring_info *cpr; 3425 int pkt_size, i = 0; 3426 struct sk_buff *skb; 3427 dma_addr_t map; 3428 u8 *data; 3429 int rc; 3430 3431 cpr = &rxr->bnapi->cp_ring; 3432 if (bp->flags & BNXT_FLAG_CHIP_P5) 3433 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3434 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3435 skb = netdev_alloc_skb(bp->dev, pkt_size); 3436 if (!skb) 3437 return -ENOMEM; 3438 data = skb_put(skb, pkt_size); 3439 eth_broadcast_addr(data); 3440 i += ETH_ALEN; 3441 ether_addr_copy(&data[i], bp->dev->dev_addr); 3442 i += ETH_ALEN; 3443 for ( ; i < pkt_size; i++) 3444 data[i] = (u8)(i & 0xff); 3445 3446 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3447 DMA_TO_DEVICE); 3448 if (dma_mapping_error(&bp->pdev->dev, map)) { 3449 dev_kfree_skb(skb); 3450 return -EIO; 3451 } 3452 bnxt_xmit_bd(bp, txr, map, pkt_size); 3453 3454 /* Sync BD data before updating doorbell */ 3455 wmb(); 3456 3457 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3458 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3459 3460 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 3461 dev_kfree_skb(skb); 3462 return rc; 3463 } 3464 3465 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3466 { 3467 struct hwrm_selftest_exec_output *resp; 3468 struct hwrm_selftest_exec_input *req; 3469 int rc; 3470 3471 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 3472 if (rc) 3473 return rc; 3474 3475 hwrm_req_timeout(bp, req, bp->test_info->timeout); 3476 req->flags = test_mask; 3477 3478 resp = hwrm_req_hold(bp, req); 3479 rc = hwrm_req_send(bp, req); 3480 *test_results = resp->test_success; 3481 hwrm_req_drop(bp, req); 3482 return rc; 3483 } 3484 3485 #define BNXT_DRV_TESTS 4 3486 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3487 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3488 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3489 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3490 3491 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3492 u64 *buf) 3493 { 3494 struct bnxt *bp = netdev_priv(dev); 3495 bool do_ext_lpbk = false; 3496 bool offline = false; 3497 u8 test_results = 0; 3498 u8 test_mask = 0; 3499 int rc = 0, i; 3500 3501 if (!bp->num_tests || !BNXT_PF(bp)) 3502 return; 3503 memset(buf, 0, sizeof(u64) * bp->num_tests); 3504 if (!netif_running(dev)) { 3505 etest->flags |= ETH_TEST_FL_FAILED; 3506 return; 3507 } 3508 3509 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3510 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 3511 do_ext_lpbk = true; 3512 3513 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3514 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 3515 etest->flags |= ETH_TEST_FL_FAILED; 3516 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 3517 return; 3518 } 3519 offline = true; 3520 } 3521 3522 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3523 u8 bit_val = 1 << i; 3524 3525 if (!(bp->test_info->offline_mask & bit_val)) 3526 test_mask |= bit_val; 3527 else if (offline) 3528 test_mask |= bit_val; 3529 } 3530 if (!offline) { 3531 bnxt_run_fw_tests(bp, test_mask, &test_results); 3532 } else { 3533 rc = bnxt_close_nic(bp, false, false); 3534 if (rc) 3535 return; 3536 bnxt_run_fw_tests(bp, test_mask, &test_results); 3537 3538 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3539 bnxt_hwrm_mac_loopback(bp, true); 3540 msleep(250); 3541 rc = bnxt_half_open_nic(bp); 3542 if (rc) { 3543 bnxt_hwrm_mac_loopback(bp, false); 3544 etest->flags |= ETH_TEST_FL_FAILED; 3545 return; 3546 } 3547 if (bnxt_run_loopback(bp)) 3548 etest->flags |= ETH_TEST_FL_FAILED; 3549 else 3550 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3551 3552 bnxt_hwrm_mac_loopback(bp, false); 3553 bnxt_hwrm_phy_loopback(bp, true, false); 3554 msleep(1000); 3555 if (bnxt_run_loopback(bp)) { 3556 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3557 etest->flags |= ETH_TEST_FL_FAILED; 3558 } 3559 if (do_ext_lpbk) { 3560 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3561 bnxt_hwrm_phy_loopback(bp, true, true); 3562 msleep(1000); 3563 if (bnxt_run_loopback(bp)) { 3564 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3565 etest->flags |= ETH_TEST_FL_FAILED; 3566 } 3567 } 3568 bnxt_hwrm_phy_loopback(bp, false, false); 3569 bnxt_half_close_nic(bp); 3570 rc = bnxt_open_nic(bp, false, true); 3571 } 3572 if (rc || bnxt_test_irq(bp)) { 3573 buf[BNXT_IRQ_TEST_IDX] = 1; 3574 etest->flags |= ETH_TEST_FL_FAILED; 3575 } 3576 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3577 u8 bit_val = 1 << i; 3578 3579 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3580 buf[i] = 1; 3581 etest->flags |= ETH_TEST_FL_FAILED; 3582 } 3583 } 3584 } 3585 3586 static int bnxt_reset(struct net_device *dev, u32 *flags) 3587 { 3588 struct bnxt *bp = netdev_priv(dev); 3589 bool reload = false; 3590 u32 req = *flags; 3591 3592 if (!req) 3593 return -EINVAL; 3594 3595 if (!BNXT_PF(bp)) { 3596 netdev_err(dev, "Reset is not supported from a VF\n"); 3597 return -EOPNOTSUPP; 3598 } 3599 3600 if (pci_vfs_assigned(bp->pdev) && 3601 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3602 netdev_err(dev, 3603 "Reset not allowed when VFs are assigned to VMs\n"); 3604 return -EBUSY; 3605 } 3606 3607 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3608 /* This feature is not supported in older firmware versions */ 3609 if (bp->hwrm_spec_code >= 0x10803) { 3610 if (!bnxt_firmware_reset_chip(dev)) { 3611 netdev_info(dev, "Firmware reset request successful.\n"); 3612 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3613 reload = true; 3614 *flags &= ~BNXT_FW_RESET_CHIP; 3615 } 3616 } else if (req == BNXT_FW_RESET_CHIP) { 3617 return -EOPNOTSUPP; /* only request, fail hard */ 3618 } 3619 } 3620 3621 if (req & BNXT_FW_RESET_AP) { 3622 /* This feature is not supported in older firmware versions */ 3623 if (bp->hwrm_spec_code >= 0x10803) { 3624 if (!bnxt_firmware_reset_ap(dev)) { 3625 netdev_info(dev, "Reset application processor successful.\n"); 3626 reload = true; 3627 *flags &= ~BNXT_FW_RESET_AP; 3628 } 3629 } else if (req == BNXT_FW_RESET_AP) { 3630 return -EOPNOTSUPP; /* only request, fail hard */ 3631 } 3632 } 3633 3634 if (reload) 3635 netdev_info(dev, "Reload driver to complete reset\n"); 3636 3637 return 0; 3638 } 3639 3640 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3641 { 3642 struct bnxt *bp = netdev_priv(dev); 3643 3644 if (dump->flag > BNXT_DUMP_CRASH) { 3645 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3646 return -EINVAL; 3647 } 3648 3649 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3650 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3651 return -EOPNOTSUPP; 3652 } 3653 3654 bp->dump_flag = dump->flag; 3655 return 0; 3656 } 3657 3658 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3659 { 3660 struct bnxt *bp = netdev_priv(dev); 3661 3662 if (bp->hwrm_spec_code < 0x10801) 3663 return -EOPNOTSUPP; 3664 3665 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3666 bp->ver_resp.hwrm_fw_min_8b << 16 | 3667 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3668 bp->ver_resp.hwrm_fw_rsvd_8b; 3669 3670 dump->flag = bp->dump_flag; 3671 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 3672 return 0; 3673 } 3674 3675 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3676 void *buf) 3677 { 3678 struct bnxt *bp = netdev_priv(dev); 3679 3680 if (bp->hwrm_spec_code < 0x10801) 3681 return -EOPNOTSUPP; 3682 3683 memset(buf, 0, dump->len); 3684 3685 dump->flag = bp->dump_flag; 3686 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 3687 } 3688 3689 static int bnxt_get_ts_info(struct net_device *dev, 3690 struct ethtool_ts_info *info) 3691 { 3692 struct bnxt *bp = netdev_priv(dev); 3693 struct bnxt_ptp_cfg *ptp; 3694 3695 ptp = bp->ptp_cfg; 3696 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3697 SOF_TIMESTAMPING_RX_SOFTWARE | 3698 SOF_TIMESTAMPING_SOFTWARE; 3699 3700 info->phc_index = -1; 3701 if (!ptp) 3702 return 0; 3703 3704 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 3705 SOF_TIMESTAMPING_RX_HARDWARE | 3706 SOF_TIMESTAMPING_RAW_HARDWARE; 3707 if (ptp->ptp_clock) 3708 info->phc_index = ptp_clock_index(ptp->ptp_clock); 3709 3710 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 3711 3712 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3713 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 3714 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 3715 return 0; 3716 } 3717 3718 void bnxt_ethtool_init(struct bnxt *bp) 3719 { 3720 struct hwrm_selftest_qlist_output *resp; 3721 struct hwrm_selftest_qlist_input *req; 3722 struct bnxt_test_info *test_info; 3723 struct net_device *dev = bp->dev; 3724 int i, rc; 3725 3726 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3727 bnxt_get_pkgver(dev); 3728 3729 bp->num_tests = 0; 3730 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 3731 return; 3732 3733 test_info = bp->test_info; 3734 if (!test_info) { 3735 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3736 if (!test_info) 3737 return; 3738 bp->test_info = test_info; 3739 } 3740 3741 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 3742 return; 3743 3744 resp = hwrm_req_hold(bp, req); 3745 rc = hwrm_req_send_silent(bp, req); 3746 if (rc) 3747 goto ethtool_init_exit; 3748 3749 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3750 if (bp->num_tests > BNXT_MAX_TEST) 3751 bp->num_tests = BNXT_MAX_TEST; 3752 3753 test_info->offline_mask = resp->offline_tests; 3754 test_info->timeout = le16_to_cpu(resp->test_timeout); 3755 if (!test_info->timeout) 3756 test_info->timeout = HWRM_CMD_TIMEOUT; 3757 for (i = 0; i < bp->num_tests; i++) { 3758 char *str = test_info->string[i]; 3759 char *fw_str = resp->test0_name + i * 32; 3760 3761 if (i == BNXT_MACLPBK_TEST_IDX) { 3762 strcpy(str, "Mac loopback test (offline)"); 3763 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3764 strcpy(str, "Phy loopback test (offline)"); 3765 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3766 strcpy(str, "Ext loopback test (offline)"); 3767 } else if (i == BNXT_IRQ_TEST_IDX) { 3768 strcpy(str, "Interrupt_test (offline)"); 3769 } else { 3770 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3771 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3772 if (test_info->offline_mask & (1 << i)) 3773 strncat(str, " (offline)", 3774 ETH_GSTRING_LEN - strlen(str)); 3775 else 3776 strncat(str, " (online)", 3777 ETH_GSTRING_LEN - strlen(str)); 3778 } 3779 } 3780 3781 ethtool_init_exit: 3782 hwrm_req_drop(bp, req); 3783 } 3784 3785 static void bnxt_get_eth_phy_stats(struct net_device *dev, 3786 struct ethtool_eth_phy_stats *phy_stats) 3787 { 3788 struct bnxt *bp = netdev_priv(dev); 3789 u64 *rx; 3790 3791 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3792 return; 3793 3794 rx = bp->rx_port_stats_ext.sw_stats; 3795 phy_stats->SymbolErrorDuringCarrier = 3796 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 3797 } 3798 3799 static void bnxt_get_eth_mac_stats(struct net_device *dev, 3800 struct ethtool_eth_mac_stats *mac_stats) 3801 { 3802 struct bnxt *bp = netdev_priv(dev); 3803 u64 *rx, *tx; 3804 3805 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3806 return; 3807 3808 rx = bp->port_stats.sw_stats; 3809 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3810 3811 mac_stats->FramesReceivedOK = 3812 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 3813 mac_stats->FramesTransmittedOK = 3814 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 3815 mac_stats->FrameCheckSequenceErrors = 3816 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 3817 mac_stats->AlignmentErrors = 3818 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 3819 mac_stats->OutOfRangeLengthField = 3820 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 3821 } 3822 3823 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 3824 struct ethtool_eth_ctrl_stats *ctrl_stats) 3825 { 3826 struct bnxt *bp = netdev_priv(dev); 3827 u64 *rx; 3828 3829 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3830 return; 3831 3832 rx = bp->port_stats.sw_stats; 3833 ctrl_stats->MACControlFramesReceived = 3834 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 3835 } 3836 3837 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 3838 { 0, 64 }, 3839 { 65, 127 }, 3840 { 128, 255 }, 3841 { 256, 511 }, 3842 { 512, 1023 }, 3843 { 1024, 1518 }, 3844 { 1519, 2047 }, 3845 { 2048, 4095 }, 3846 { 4096, 9216 }, 3847 { 9217, 16383 }, 3848 {} 3849 }; 3850 3851 static void bnxt_get_rmon_stats(struct net_device *dev, 3852 struct ethtool_rmon_stats *rmon_stats, 3853 const struct ethtool_rmon_hist_range **ranges) 3854 { 3855 struct bnxt *bp = netdev_priv(dev); 3856 u64 *rx, *tx; 3857 3858 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3859 return; 3860 3861 rx = bp->port_stats.sw_stats; 3862 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3863 3864 rmon_stats->jabbers = 3865 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 3866 rmon_stats->oversize_pkts = 3867 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 3868 rmon_stats->undersize_pkts = 3869 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 3870 3871 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 3872 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 3873 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 3874 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 3875 rmon_stats->hist[4] = 3876 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 3877 rmon_stats->hist[5] = 3878 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 3879 rmon_stats->hist[6] = 3880 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 3881 rmon_stats->hist[7] = 3882 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 3883 rmon_stats->hist[8] = 3884 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 3885 rmon_stats->hist[9] = 3886 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 3887 3888 rmon_stats->hist_tx[0] = 3889 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 3890 rmon_stats->hist_tx[1] = 3891 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 3892 rmon_stats->hist_tx[2] = 3893 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 3894 rmon_stats->hist_tx[3] = 3895 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 3896 rmon_stats->hist_tx[4] = 3897 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 3898 rmon_stats->hist_tx[5] = 3899 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 3900 rmon_stats->hist_tx[6] = 3901 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 3902 rmon_stats->hist_tx[7] = 3903 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 3904 rmon_stats->hist_tx[8] = 3905 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 3906 rmon_stats->hist_tx[9] = 3907 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 3908 3909 *ranges = bnxt_rmon_ranges; 3910 } 3911 3912 void bnxt_ethtool_free(struct bnxt *bp) 3913 { 3914 kfree(bp->test_info); 3915 bp->test_info = NULL; 3916 } 3917 3918 const struct ethtool_ops bnxt_ethtool_ops = { 3919 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3920 ETHTOOL_COALESCE_MAX_FRAMES | 3921 ETHTOOL_COALESCE_USECS_IRQ | 3922 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3923 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3924 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3925 .get_link_ksettings = bnxt_get_link_ksettings, 3926 .set_link_ksettings = bnxt_set_link_ksettings, 3927 .get_fec_stats = bnxt_get_fec_stats, 3928 .get_fecparam = bnxt_get_fecparam, 3929 .set_fecparam = bnxt_set_fecparam, 3930 .get_pause_stats = bnxt_get_pause_stats, 3931 .get_pauseparam = bnxt_get_pauseparam, 3932 .set_pauseparam = bnxt_set_pauseparam, 3933 .get_drvinfo = bnxt_get_drvinfo, 3934 .get_regs_len = bnxt_get_regs_len, 3935 .get_regs = bnxt_get_regs, 3936 .get_wol = bnxt_get_wol, 3937 .set_wol = bnxt_set_wol, 3938 .get_coalesce = bnxt_get_coalesce, 3939 .set_coalesce = bnxt_set_coalesce, 3940 .get_msglevel = bnxt_get_msglevel, 3941 .set_msglevel = bnxt_set_msglevel, 3942 .get_sset_count = bnxt_get_sset_count, 3943 .get_strings = bnxt_get_strings, 3944 .get_ethtool_stats = bnxt_get_ethtool_stats, 3945 .set_ringparam = bnxt_set_ringparam, 3946 .get_ringparam = bnxt_get_ringparam, 3947 .get_channels = bnxt_get_channels, 3948 .set_channels = bnxt_set_channels, 3949 .get_rxnfc = bnxt_get_rxnfc, 3950 .set_rxnfc = bnxt_set_rxnfc, 3951 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3952 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3953 .get_rxfh = bnxt_get_rxfh, 3954 .set_rxfh = bnxt_set_rxfh, 3955 .flash_device = bnxt_flash_device, 3956 .get_eeprom_len = bnxt_get_eeprom_len, 3957 .get_eeprom = bnxt_get_eeprom, 3958 .set_eeprom = bnxt_set_eeprom, 3959 .get_link = bnxt_get_link, 3960 .get_eee = bnxt_get_eee, 3961 .set_eee = bnxt_set_eee, 3962 .get_module_info = bnxt_get_module_info, 3963 .get_module_eeprom = bnxt_get_module_eeprom, 3964 .nway_reset = bnxt_nway_reset, 3965 .set_phys_id = bnxt_set_phys_id, 3966 .self_test = bnxt_self_test, 3967 .get_ts_info = bnxt_get_ts_info, 3968 .reset = bnxt_reset, 3969 .set_dump = bnxt_set_dump, 3970 .get_dump_flag = bnxt_get_dump_flag, 3971 .get_dump_data = bnxt_get_dump_data, 3972 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 3973 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 3974 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 3975 .get_rmon_stats = bnxt_get_rmon_stats, 3976 }; 3977