1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/etherdevice.h> 17 #include <linux/crc32.h> 18 #include <linux/firmware.h> 19 #include <linux/utsname.h> 20 #include <linux/time.h> 21 #include "bnxt_hsi.h" 22 #include "bnxt.h" 23 #include "bnxt_xdp.h" 24 #include "bnxt_ethtool.h" 25 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 26 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 27 #include "bnxt_coredump.h" 28 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 29 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 30 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 32 static u32 bnxt_get_msglevel(struct net_device *dev) 33 { 34 struct bnxt *bp = netdev_priv(dev); 35 36 return bp->msg_enable; 37 } 38 39 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 40 { 41 struct bnxt *bp = netdev_priv(dev); 42 43 bp->msg_enable = value; 44 } 45 46 static int bnxt_get_coalesce(struct net_device *dev, 47 struct ethtool_coalesce *coal) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 struct bnxt_coal *hw_coal; 51 u16 mult; 52 53 memset(coal, 0, sizeof(*coal)); 54 55 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 56 57 hw_coal = &bp->rx_coal; 58 mult = hw_coal->bufs_per_record; 59 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 60 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 61 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 62 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 63 64 hw_coal = &bp->tx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 71 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 72 73 return 0; 74 } 75 76 static int bnxt_set_coalesce(struct net_device *dev, 77 struct ethtool_coalesce *coal) 78 { 79 struct bnxt *bp = netdev_priv(dev); 80 bool update_stats = false; 81 struct bnxt_coal *hw_coal; 82 int rc = 0; 83 u16 mult; 84 85 if (coal->use_adaptive_rx_coalesce) { 86 bp->flags |= BNXT_FLAG_DIM; 87 } else { 88 if (bp->flags & BNXT_FLAG_DIM) { 89 bp->flags &= ~(BNXT_FLAG_DIM); 90 goto reset_coalesce; 91 } 92 } 93 94 hw_coal = &bp->rx_coal; 95 mult = hw_coal->bufs_per_record; 96 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 97 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 98 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 99 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 100 101 hw_coal = &bp->tx_coal; 102 mult = hw_coal->bufs_per_record; 103 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 104 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 105 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 106 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 107 108 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 109 u32 stats_ticks = coal->stats_block_coalesce_usecs; 110 111 /* Allow 0, which means disable. */ 112 if (stats_ticks) 113 stats_ticks = clamp_t(u32, stats_ticks, 114 BNXT_MIN_STATS_COAL_TICKS, 115 BNXT_MAX_STATS_COAL_TICKS); 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 117 bp->stats_coal_ticks = stats_ticks; 118 if (bp->stats_coal_ticks) 119 bp->current_interval = 120 bp->stats_coal_ticks * HZ / 1000000; 121 else 122 bp->current_interval = BNXT_TIMER_INTERVAL; 123 update_stats = true; 124 } 125 126 reset_coalesce: 127 if (netif_running(dev)) { 128 if (update_stats) { 129 rc = bnxt_close_nic(bp, true, false); 130 if (!rc) 131 rc = bnxt_open_nic(bp, true, false); 132 } else { 133 rc = bnxt_hwrm_set_coal(bp); 134 } 135 } 136 137 return rc; 138 } 139 140 static const char * const bnxt_ring_rx_stats_str[] = { 141 "rx_ucast_packets", 142 "rx_mcast_packets", 143 "rx_bcast_packets", 144 "rx_discards", 145 "rx_errors", 146 "rx_ucast_bytes", 147 "rx_mcast_bytes", 148 "rx_bcast_bytes", 149 }; 150 151 static const char * const bnxt_ring_tx_stats_str[] = { 152 "tx_ucast_packets", 153 "tx_mcast_packets", 154 "tx_bcast_packets", 155 "tx_errors", 156 "tx_discards", 157 "tx_ucast_bytes", 158 "tx_mcast_bytes", 159 "tx_bcast_bytes", 160 }; 161 162 static const char * const bnxt_ring_tpa_stats_str[] = { 163 "tpa_packets", 164 "tpa_bytes", 165 "tpa_events", 166 "tpa_aborts", 167 }; 168 169 static const char * const bnxt_ring_tpa2_stats_str[] = { 170 "rx_tpa_eligible_pkt", 171 "rx_tpa_eligible_bytes", 172 "rx_tpa_pkt", 173 "rx_tpa_bytes", 174 "rx_tpa_errors", 175 }; 176 177 static const char * const bnxt_rx_sw_stats_str[] = { 178 "rx_l4_csum_errors", 179 "rx_buf_errors", 180 }; 181 182 static const char * const bnxt_cmn_sw_stats_str[] = { 183 "missed_irqs", 184 }; 185 186 #define BNXT_RX_STATS_ENTRY(counter) \ 187 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 188 189 #define BNXT_TX_STATS_ENTRY(counter) \ 190 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 191 192 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 193 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 194 195 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 196 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 197 198 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 199 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 200 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 201 202 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 203 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 204 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 205 206 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 207 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 208 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 209 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 210 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 211 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 212 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 213 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 214 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 215 216 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 217 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 218 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 219 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 220 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 221 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 222 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 223 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 224 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 225 226 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 227 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 228 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 229 230 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 231 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 232 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 233 234 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 235 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 236 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 237 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 238 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 239 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 240 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 241 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 242 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 243 244 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 245 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 246 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 247 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 248 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 249 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 250 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 251 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 252 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 253 254 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 255 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 256 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 257 258 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 259 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 260 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 261 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 267 268 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 269 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 270 __stringify(counter##_pri##n) } 271 272 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 273 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 274 __stringify(counter##_pri##n) } 275 276 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 277 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 278 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 279 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 280 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 281 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 282 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 283 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 284 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 285 286 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 287 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 288 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 289 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 290 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 291 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 292 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 293 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 294 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 295 296 enum { 297 RX_TOTAL_DISCARDS, 298 TX_TOTAL_DISCARDS, 299 }; 300 301 static struct { 302 u64 counter; 303 char string[ETH_GSTRING_LEN]; 304 } bnxt_sw_func_stats[] = { 305 {0, "rx_total_discard_pkts"}, 306 {0, "tx_total_discard_pkts"}, 307 }; 308 309 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 310 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 311 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 312 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 313 314 static const struct { 315 long offset; 316 char string[ETH_GSTRING_LEN]; 317 } bnxt_port_stats_arr[] = { 318 BNXT_RX_STATS_ENTRY(rx_64b_frames), 319 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 320 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 321 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 322 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 323 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 324 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 325 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 326 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 327 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 328 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 329 BNXT_RX_STATS_ENTRY(rx_total_frames), 330 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 331 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 332 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 333 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 334 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 335 BNXT_RX_STATS_ENTRY(rx_pause_frames), 336 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 337 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 338 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 339 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 340 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 341 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 342 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 343 BNXT_RX_STATS_ENTRY(rx_good_frames), 344 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 345 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 346 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 352 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 353 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 354 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 355 BNXT_RX_STATS_ENTRY(rx_bytes), 356 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 357 BNXT_RX_STATS_ENTRY(rx_runt_frames), 358 BNXT_RX_STATS_ENTRY(rx_stat_discard), 359 BNXT_RX_STATS_ENTRY(rx_stat_err), 360 361 BNXT_TX_STATS_ENTRY(tx_64b_frames), 362 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 363 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 364 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 365 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 366 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 367 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 368 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 369 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 370 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 371 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 372 BNXT_TX_STATS_ENTRY(tx_good_frames), 373 BNXT_TX_STATS_ENTRY(tx_total_frames), 374 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 375 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 376 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 377 BNXT_TX_STATS_ENTRY(tx_pause_frames), 378 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 379 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 380 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 381 BNXT_TX_STATS_ENTRY(tx_err), 382 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 383 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 384 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 385 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 391 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 392 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 393 BNXT_TX_STATS_ENTRY(tx_total_collisions), 394 BNXT_TX_STATS_ENTRY(tx_bytes), 395 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 396 BNXT_TX_STATS_ENTRY(tx_stat_discard), 397 BNXT_TX_STATS_ENTRY(tx_stat_error), 398 }; 399 400 static const struct { 401 long offset; 402 char string[ETH_GSTRING_LEN]; 403 } bnxt_port_stats_ext_arr[] = { 404 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 405 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 406 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 407 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 408 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 409 BNXT_RX_STATS_EXT_COS_ENTRIES, 410 BNXT_RX_STATS_EXT_PFC_ENTRIES, 411 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 412 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 413 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 414 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 415 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 416 }; 417 418 static const struct { 419 long offset; 420 char string[ETH_GSTRING_LEN]; 421 } bnxt_tx_port_stats_ext_arr[] = { 422 BNXT_TX_STATS_EXT_COS_ENTRIES, 423 BNXT_TX_STATS_EXT_PFC_ENTRIES, 424 }; 425 426 static const struct { 427 long base_off; 428 char string[ETH_GSTRING_LEN]; 429 } bnxt_rx_bytes_pri_arr[] = { 430 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 431 }; 432 433 static const struct { 434 long base_off; 435 char string[ETH_GSTRING_LEN]; 436 } bnxt_rx_pkts_pri_arr[] = { 437 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 438 }; 439 440 static const struct { 441 long base_off; 442 char string[ETH_GSTRING_LEN]; 443 } bnxt_tx_bytes_pri_arr[] = { 444 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 445 }; 446 447 static const struct { 448 long base_off; 449 char string[ETH_GSTRING_LEN]; 450 } bnxt_tx_pkts_pri_arr[] = { 451 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 452 }; 453 454 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 455 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 456 #define BNXT_NUM_STATS_PRI \ 457 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 458 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 459 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 460 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 461 462 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 463 { 464 if (BNXT_SUPPORTS_TPA(bp)) { 465 if (bp->max_tpa_v2) 466 return ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 467 return ARRAY_SIZE(bnxt_ring_tpa_stats_str); 468 } 469 return 0; 470 } 471 472 static int bnxt_get_num_ring_stats(struct bnxt *bp) 473 { 474 int rx, tx, cmn; 475 476 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 477 bnxt_get_num_tpa_ring_stats(bp); 478 tx = NUM_RING_TX_HW_STATS; 479 cmn = NUM_RING_CMN_SW_STATS; 480 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 481 cmn * bp->cp_nr_rings; 482 } 483 484 static int bnxt_get_num_stats(struct bnxt *bp) 485 { 486 int num_stats = bnxt_get_num_ring_stats(bp); 487 488 num_stats += BNXT_NUM_SW_FUNC_STATS; 489 490 if (bp->flags & BNXT_FLAG_PORT_STATS) 491 num_stats += BNXT_NUM_PORT_STATS; 492 493 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 494 num_stats += bp->fw_rx_stats_ext_size + 495 bp->fw_tx_stats_ext_size; 496 if (bp->pri2cos_valid) 497 num_stats += BNXT_NUM_STATS_PRI; 498 } 499 500 return num_stats; 501 } 502 503 static int bnxt_get_sset_count(struct net_device *dev, int sset) 504 { 505 struct bnxt *bp = netdev_priv(dev); 506 507 switch (sset) { 508 case ETH_SS_STATS: 509 return bnxt_get_num_stats(bp); 510 case ETH_SS_TEST: 511 if (!bp->num_tests) 512 return -EOPNOTSUPP; 513 return bp->num_tests; 514 default: 515 return -EOPNOTSUPP; 516 } 517 } 518 519 static bool is_rx_ring(struct bnxt *bp, int ring_num) 520 { 521 return ring_num < bp->rx_nr_rings; 522 } 523 524 static bool is_tx_ring(struct bnxt *bp, int ring_num) 525 { 526 int tx_base = 0; 527 528 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 529 tx_base = bp->rx_nr_rings; 530 531 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 532 return true; 533 return false; 534 } 535 536 static void bnxt_get_ethtool_stats(struct net_device *dev, 537 struct ethtool_stats *stats, u64 *buf) 538 { 539 u32 i, j = 0; 540 struct bnxt *bp = netdev_priv(dev); 541 u32 tpa_stats; 542 543 if (!bp->bnapi) { 544 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 545 goto skip_ring_stats; 546 } 547 548 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 549 bnxt_sw_func_stats[i].counter = 0; 550 551 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 552 for (i = 0; i < bp->cp_nr_rings; i++) { 553 struct bnxt_napi *bnapi = bp->bnapi[i]; 554 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 555 u64 *sw_stats = cpr->stats.sw_stats; 556 u64 *sw; 557 int k; 558 559 if (is_rx_ring(bp, i)) { 560 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 561 buf[j] = sw_stats[k]; 562 } 563 if (is_tx_ring(bp, i)) { 564 k = NUM_RING_RX_HW_STATS; 565 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 566 j++, k++) 567 buf[j] = sw_stats[k]; 568 } 569 if (!tpa_stats || !is_rx_ring(bp, i)) 570 goto skip_tpa_ring_stats; 571 572 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 573 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 574 tpa_stats; j++, k++) 575 buf[j] = sw_stats[k]; 576 577 skip_tpa_ring_stats: 578 sw = (u64 *)&cpr->sw_stats.rx; 579 if (is_rx_ring(bp, i)) { 580 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 581 buf[j] = sw[k]; 582 } 583 584 sw = (u64 *)&cpr->sw_stats.cmn; 585 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 586 buf[j] = sw[k]; 587 588 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 589 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts); 590 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 591 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts); 592 } 593 594 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 595 buf[j] = bnxt_sw_func_stats[i].counter; 596 597 skip_ring_stats: 598 if (bp->flags & BNXT_FLAG_PORT_STATS) { 599 u64 *port_stats = bp->port_stats.sw_stats; 600 601 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 602 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 603 } 604 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 605 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 606 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 607 608 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 609 buf[j] = *(rx_port_stats_ext + 610 bnxt_port_stats_ext_arr[i].offset); 611 } 612 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 613 buf[j] = *(tx_port_stats_ext + 614 bnxt_tx_port_stats_ext_arr[i].offset); 615 } 616 if (bp->pri2cos_valid) { 617 for (i = 0; i < 8; i++, j++) { 618 long n = bnxt_rx_bytes_pri_arr[i].base_off + 619 bp->pri2cos_idx[i]; 620 621 buf[j] = *(rx_port_stats_ext + n); 622 } 623 for (i = 0; i < 8; i++, j++) { 624 long n = bnxt_rx_pkts_pri_arr[i].base_off + 625 bp->pri2cos_idx[i]; 626 627 buf[j] = *(rx_port_stats_ext + n); 628 } 629 for (i = 0; i < 8; i++, j++) { 630 long n = bnxt_tx_bytes_pri_arr[i].base_off + 631 bp->pri2cos_idx[i]; 632 633 buf[j] = *(tx_port_stats_ext + n); 634 } 635 for (i = 0; i < 8; i++, j++) { 636 long n = bnxt_tx_pkts_pri_arr[i].base_off + 637 bp->pri2cos_idx[i]; 638 639 buf[j] = *(tx_port_stats_ext + n); 640 } 641 } 642 } 643 } 644 645 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 646 { 647 struct bnxt *bp = netdev_priv(dev); 648 static const char * const *str; 649 u32 i, j, num_str; 650 651 switch (stringset) { 652 case ETH_SS_STATS: 653 for (i = 0; i < bp->cp_nr_rings; i++) { 654 if (is_rx_ring(bp, i)) { 655 num_str = NUM_RING_RX_HW_STATS; 656 for (j = 0; j < num_str; j++) { 657 sprintf(buf, "[%d]: %s", i, 658 bnxt_ring_rx_stats_str[j]); 659 buf += ETH_GSTRING_LEN; 660 } 661 } 662 if (is_tx_ring(bp, i)) { 663 num_str = NUM_RING_TX_HW_STATS; 664 for (j = 0; j < num_str; j++) { 665 sprintf(buf, "[%d]: %s", i, 666 bnxt_ring_tx_stats_str[j]); 667 buf += ETH_GSTRING_LEN; 668 } 669 } 670 num_str = bnxt_get_num_tpa_ring_stats(bp); 671 if (!num_str || !is_rx_ring(bp, i)) 672 goto skip_tpa_stats; 673 674 if (bp->max_tpa_v2) 675 str = bnxt_ring_tpa2_stats_str; 676 else 677 str = bnxt_ring_tpa_stats_str; 678 679 for (j = 0; j < num_str; j++) { 680 sprintf(buf, "[%d]: %s", i, str[j]); 681 buf += ETH_GSTRING_LEN; 682 } 683 skip_tpa_stats: 684 if (is_rx_ring(bp, i)) { 685 num_str = NUM_RING_RX_SW_STATS; 686 for (j = 0; j < num_str; j++) { 687 sprintf(buf, "[%d]: %s", i, 688 bnxt_rx_sw_stats_str[j]); 689 buf += ETH_GSTRING_LEN; 690 } 691 } 692 num_str = NUM_RING_CMN_SW_STATS; 693 for (j = 0; j < num_str; j++) { 694 sprintf(buf, "[%d]: %s", i, 695 bnxt_cmn_sw_stats_str[j]); 696 buf += ETH_GSTRING_LEN; 697 } 698 } 699 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 700 strcpy(buf, bnxt_sw_func_stats[i].string); 701 buf += ETH_GSTRING_LEN; 702 } 703 704 if (bp->flags & BNXT_FLAG_PORT_STATS) { 705 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 706 strcpy(buf, bnxt_port_stats_arr[i].string); 707 buf += ETH_GSTRING_LEN; 708 } 709 } 710 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 711 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 712 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 713 buf += ETH_GSTRING_LEN; 714 } 715 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 716 strcpy(buf, 717 bnxt_tx_port_stats_ext_arr[i].string); 718 buf += ETH_GSTRING_LEN; 719 } 720 if (bp->pri2cos_valid) { 721 for (i = 0; i < 8; i++) { 722 strcpy(buf, 723 bnxt_rx_bytes_pri_arr[i].string); 724 buf += ETH_GSTRING_LEN; 725 } 726 for (i = 0; i < 8; i++) { 727 strcpy(buf, 728 bnxt_rx_pkts_pri_arr[i].string); 729 buf += ETH_GSTRING_LEN; 730 } 731 for (i = 0; i < 8; i++) { 732 strcpy(buf, 733 bnxt_tx_bytes_pri_arr[i].string); 734 buf += ETH_GSTRING_LEN; 735 } 736 for (i = 0; i < 8; i++) { 737 strcpy(buf, 738 bnxt_tx_pkts_pri_arr[i].string); 739 buf += ETH_GSTRING_LEN; 740 } 741 } 742 } 743 break; 744 case ETH_SS_TEST: 745 if (bp->num_tests) 746 memcpy(buf, bp->test_info->string, 747 bp->num_tests * ETH_GSTRING_LEN); 748 break; 749 default: 750 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 751 stringset); 752 break; 753 } 754 } 755 756 static void bnxt_get_ringparam(struct net_device *dev, 757 struct ethtool_ringparam *ering) 758 { 759 struct bnxt *bp = netdev_priv(dev); 760 761 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 762 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 763 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 764 765 ering->rx_pending = bp->rx_ring_size; 766 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 767 ering->tx_pending = bp->tx_ring_size; 768 } 769 770 static int bnxt_set_ringparam(struct net_device *dev, 771 struct ethtool_ringparam *ering) 772 { 773 struct bnxt *bp = netdev_priv(dev); 774 775 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 776 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 777 (ering->tx_pending <= MAX_SKB_FRAGS)) 778 return -EINVAL; 779 780 if (netif_running(dev)) 781 bnxt_close_nic(bp, false, false); 782 783 bp->rx_ring_size = ering->rx_pending; 784 bp->tx_ring_size = ering->tx_pending; 785 bnxt_set_ring_params(bp); 786 787 if (netif_running(dev)) 788 return bnxt_open_nic(bp, false, false); 789 790 return 0; 791 } 792 793 static void bnxt_get_channels(struct net_device *dev, 794 struct ethtool_channels *channel) 795 { 796 struct bnxt *bp = netdev_priv(dev); 797 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 798 int max_rx_rings, max_tx_rings, tcs; 799 int max_tx_sch_inputs; 800 801 /* Get the most up-to-date max_tx_sch_inputs. */ 802 if (netif_running(dev) && BNXT_NEW_RM(bp)) 803 bnxt_hwrm_func_resc_qcaps(bp, false); 804 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 805 806 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 807 if (max_tx_sch_inputs) 808 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 809 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 810 811 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 812 max_rx_rings = 0; 813 max_tx_rings = 0; 814 } 815 if (max_tx_sch_inputs) 816 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 817 818 tcs = netdev_get_num_tc(dev); 819 if (tcs > 1) 820 max_tx_rings /= tcs; 821 822 channel->max_rx = max_rx_rings; 823 channel->max_tx = max_tx_rings; 824 channel->max_other = 0; 825 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 826 channel->combined_count = bp->rx_nr_rings; 827 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 828 channel->combined_count--; 829 } else { 830 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 831 channel->rx_count = bp->rx_nr_rings; 832 channel->tx_count = bp->tx_nr_rings_per_tc; 833 } 834 } 835 } 836 837 static int bnxt_set_channels(struct net_device *dev, 838 struct ethtool_channels *channel) 839 { 840 struct bnxt *bp = netdev_priv(dev); 841 int req_tx_rings, req_rx_rings, tcs; 842 bool sh = false; 843 int tx_xdp = 0; 844 int rc = 0; 845 846 if (channel->other_count) 847 return -EINVAL; 848 849 if (!channel->combined_count && 850 (!channel->rx_count || !channel->tx_count)) 851 return -EINVAL; 852 853 if (channel->combined_count && 854 (channel->rx_count || channel->tx_count)) 855 return -EINVAL; 856 857 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 858 channel->tx_count)) 859 return -EINVAL; 860 861 if (channel->combined_count) 862 sh = true; 863 864 tcs = netdev_get_num_tc(dev); 865 866 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 867 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 868 if (bp->tx_nr_rings_xdp) { 869 if (!sh) { 870 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 871 return -EINVAL; 872 } 873 tx_xdp = req_rx_rings; 874 } 875 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 876 if (rc) { 877 netdev_warn(dev, "Unable to allocate the requested rings\n"); 878 return rc; 879 } 880 881 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 882 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 883 (dev->priv_flags & IFF_RXFH_CONFIGURED)) { 884 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 885 return -EINVAL; 886 } 887 888 if (netif_running(dev)) { 889 if (BNXT_PF(bp)) { 890 /* TODO CHIMP_FW: Send message to all VF's 891 * before PF unload 892 */ 893 } 894 rc = bnxt_close_nic(bp, true, false); 895 if (rc) { 896 netdev_err(bp->dev, "Set channel failure rc :%x\n", 897 rc); 898 return rc; 899 } 900 } 901 902 if (sh) { 903 bp->flags |= BNXT_FLAG_SHARED_RINGS; 904 bp->rx_nr_rings = channel->combined_count; 905 bp->tx_nr_rings_per_tc = channel->combined_count; 906 } else { 907 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 908 bp->rx_nr_rings = channel->rx_count; 909 bp->tx_nr_rings_per_tc = channel->tx_count; 910 } 911 bp->tx_nr_rings_xdp = tx_xdp; 912 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 913 if (tcs > 1) 914 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 915 916 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 917 bp->tx_nr_rings + bp->rx_nr_rings; 918 919 /* After changing number of rx channels, update NTUPLE feature. */ 920 netdev_update_features(dev); 921 if (netif_running(dev)) { 922 rc = bnxt_open_nic(bp, true, false); 923 if ((!rc) && BNXT_PF(bp)) { 924 /* TODO CHIMP_FW: Send message to all VF's 925 * to renable 926 */ 927 } 928 } else { 929 rc = bnxt_reserve_rings(bp, true); 930 } 931 932 return rc; 933 } 934 935 #ifdef CONFIG_RFS_ACCEL 936 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 937 u32 *rule_locs) 938 { 939 int i, j = 0; 940 941 cmd->data = bp->ntp_fltr_count; 942 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 943 struct hlist_head *head; 944 struct bnxt_ntuple_filter *fltr; 945 946 head = &bp->ntp_fltr_hash_tbl[i]; 947 rcu_read_lock(); 948 hlist_for_each_entry_rcu(fltr, head, hash) { 949 if (j == cmd->rule_cnt) 950 break; 951 rule_locs[j++] = fltr->sw_id; 952 } 953 rcu_read_unlock(); 954 if (j == cmd->rule_cnt) 955 break; 956 } 957 cmd->rule_cnt = j; 958 return 0; 959 } 960 961 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 962 { 963 struct ethtool_rx_flow_spec *fs = 964 (struct ethtool_rx_flow_spec *)&cmd->fs; 965 struct bnxt_ntuple_filter *fltr; 966 struct flow_keys *fkeys; 967 int i, rc = -EINVAL; 968 969 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 970 return rc; 971 972 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 973 struct hlist_head *head; 974 975 head = &bp->ntp_fltr_hash_tbl[i]; 976 rcu_read_lock(); 977 hlist_for_each_entry_rcu(fltr, head, hash) { 978 if (fltr->sw_id == fs->location) 979 goto fltr_found; 980 } 981 rcu_read_unlock(); 982 } 983 return rc; 984 985 fltr_found: 986 fkeys = &fltr->fkeys; 987 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 988 if (fkeys->basic.ip_proto == IPPROTO_TCP) 989 fs->flow_type = TCP_V4_FLOW; 990 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 991 fs->flow_type = UDP_V4_FLOW; 992 else 993 goto fltr_err; 994 995 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 996 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 997 998 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 999 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1000 1001 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1002 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1003 1004 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1005 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1006 } else { 1007 int i; 1008 1009 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1010 fs->flow_type = TCP_V6_FLOW; 1011 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1012 fs->flow_type = UDP_V6_FLOW; 1013 else 1014 goto fltr_err; 1015 1016 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1017 fkeys->addrs.v6addrs.src; 1018 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1019 fkeys->addrs.v6addrs.dst; 1020 for (i = 0; i < 4; i++) { 1021 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1022 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1023 } 1024 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1025 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1026 1027 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1028 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1029 } 1030 1031 fs->ring_cookie = fltr->rxq; 1032 rc = 0; 1033 1034 fltr_err: 1035 rcu_read_unlock(); 1036 1037 return rc; 1038 } 1039 #endif 1040 1041 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1042 { 1043 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1044 return RXH_IP_SRC | RXH_IP_DST; 1045 return 0; 1046 } 1047 1048 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1049 { 1050 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1051 return RXH_IP_SRC | RXH_IP_DST; 1052 return 0; 1053 } 1054 1055 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1056 { 1057 cmd->data = 0; 1058 switch (cmd->flow_type) { 1059 case TCP_V4_FLOW: 1060 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1061 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1062 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1063 cmd->data |= get_ethtool_ipv4_rss(bp); 1064 break; 1065 case UDP_V4_FLOW: 1066 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1067 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1068 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1069 fallthrough; 1070 case SCTP_V4_FLOW: 1071 case AH_ESP_V4_FLOW: 1072 case AH_V4_FLOW: 1073 case ESP_V4_FLOW: 1074 case IPV4_FLOW: 1075 cmd->data |= get_ethtool_ipv4_rss(bp); 1076 break; 1077 1078 case TCP_V6_FLOW: 1079 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1080 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1081 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1082 cmd->data |= get_ethtool_ipv6_rss(bp); 1083 break; 1084 case UDP_V6_FLOW: 1085 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1086 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1087 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1088 fallthrough; 1089 case SCTP_V6_FLOW: 1090 case AH_ESP_V6_FLOW: 1091 case AH_V6_FLOW: 1092 case ESP_V6_FLOW: 1093 case IPV6_FLOW: 1094 cmd->data |= get_ethtool_ipv6_rss(bp); 1095 break; 1096 } 1097 return 0; 1098 } 1099 1100 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1101 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1102 1103 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1104 { 1105 u32 rss_hash_cfg = bp->rss_hash_cfg; 1106 int tuple, rc = 0; 1107 1108 if (cmd->data == RXH_4TUPLE) 1109 tuple = 4; 1110 else if (cmd->data == RXH_2TUPLE) 1111 tuple = 2; 1112 else if (!cmd->data) 1113 tuple = 0; 1114 else 1115 return -EINVAL; 1116 1117 if (cmd->flow_type == TCP_V4_FLOW) { 1118 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1119 if (tuple == 4) 1120 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1121 } else if (cmd->flow_type == UDP_V4_FLOW) { 1122 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1123 return -EINVAL; 1124 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1125 if (tuple == 4) 1126 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1127 } else if (cmd->flow_type == TCP_V6_FLOW) { 1128 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1129 if (tuple == 4) 1130 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1131 } else if (cmd->flow_type == UDP_V6_FLOW) { 1132 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1133 return -EINVAL; 1134 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1135 if (tuple == 4) 1136 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1137 } else if (tuple == 4) { 1138 return -EINVAL; 1139 } 1140 1141 switch (cmd->flow_type) { 1142 case TCP_V4_FLOW: 1143 case UDP_V4_FLOW: 1144 case SCTP_V4_FLOW: 1145 case AH_ESP_V4_FLOW: 1146 case AH_V4_FLOW: 1147 case ESP_V4_FLOW: 1148 case IPV4_FLOW: 1149 if (tuple == 2) 1150 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1151 else if (!tuple) 1152 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1153 break; 1154 1155 case TCP_V6_FLOW: 1156 case UDP_V6_FLOW: 1157 case SCTP_V6_FLOW: 1158 case AH_ESP_V6_FLOW: 1159 case AH_V6_FLOW: 1160 case ESP_V6_FLOW: 1161 case IPV6_FLOW: 1162 if (tuple == 2) 1163 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1164 else if (!tuple) 1165 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1166 break; 1167 } 1168 1169 if (bp->rss_hash_cfg == rss_hash_cfg) 1170 return 0; 1171 1172 bp->rss_hash_cfg = rss_hash_cfg; 1173 if (netif_running(bp->dev)) { 1174 bnxt_close_nic(bp, false, false); 1175 rc = bnxt_open_nic(bp, false, false); 1176 } 1177 return rc; 1178 } 1179 1180 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1181 u32 *rule_locs) 1182 { 1183 struct bnxt *bp = netdev_priv(dev); 1184 int rc = 0; 1185 1186 switch (cmd->cmd) { 1187 #ifdef CONFIG_RFS_ACCEL 1188 case ETHTOOL_GRXRINGS: 1189 cmd->data = bp->rx_nr_rings; 1190 break; 1191 1192 case ETHTOOL_GRXCLSRLCNT: 1193 cmd->rule_cnt = bp->ntp_fltr_count; 1194 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1195 break; 1196 1197 case ETHTOOL_GRXCLSRLALL: 1198 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1199 break; 1200 1201 case ETHTOOL_GRXCLSRULE: 1202 rc = bnxt_grxclsrule(bp, cmd); 1203 break; 1204 #endif 1205 1206 case ETHTOOL_GRXFH: 1207 rc = bnxt_grxfh(bp, cmd); 1208 break; 1209 1210 default: 1211 rc = -EOPNOTSUPP; 1212 break; 1213 } 1214 1215 return rc; 1216 } 1217 1218 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1219 { 1220 struct bnxt *bp = netdev_priv(dev); 1221 int rc; 1222 1223 switch (cmd->cmd) { 1224 case ETHTOOL_SRXFH: 1225 rc = bnxt_srxfh(bp, cmd); 1226 break; 1227 1228 default: 1229 rc = -EOPNOTSUPP; 1230 break; 1231 } 1232 return rc; 1233 } 1234 1235 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1236 { 1237 struct bnxt *bp = netdev_priv(dev); 1238 1239 if (bp->flags & BNXT_FLAG_CHIP_P5) 1240 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1241 return HW_HASH_INDEX_SIZE; 1242 } 1243 1244 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1245 { 1246 return HW_HASH_KEY_SIZE; 1247 } 1248 1249 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1250 u8 *hfunc) 1251 { 1252 struct bnxt *bp = netdev_priv(dev); 1253 struct bnxt_vnic_info *vnic; 1254 u32 i, tbl_size; 1255 1256 if (hfunc) 1257 *hfunc = ETH_RSS_HASH_TOP; 1258 1259 if (!bp->vnic_info) 1260 return 0; 1261 1262 vnic = &bp->vnic_info[0]; 1263 if (indir && bp->rss_indir_tbl) { 1264 tbl_size = bnxt_get_rxfh_indir_size(dev); 1265 for (i = 0; i < tbl_size; i++) 1266 indir[i] = bp->rss_indir_tbl[i]; 1267 } 1268 1269 if (key && vnic->rss_hash_key) 1270 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1271 1272 return 0; 1273 } 1274 1275 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1276 const u8 *key, const u8 hfunc) 1277 { 1278 struct bnxt *bp = netdev_priv(dev); 1279 int rc = 0; 1280 1281 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1282 return -EOPNOTSUPP; 1283 1284 if (key) 1285 return -EOPNOTSUPP; 1286 1287 if (indir) { 1288 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1289 1290 for (i = 0; i < tbl_size; i++) 1291 bp->rss_indir_tbl[i] = indir[i]; 1292 pad = bp->rss_indir_tbl_entries - tbl_size; 1293 if (pad) 1294 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1295 } 1296 1297 if (netif_running(bp->dev)) { 1298 bnxt_close_nic(bp, false, false); 1299 rc = bnxt_open_nic(bp, false, false); 1300 } 1301 return rc; 1302 } 1303 1304 static void bnxt_get_drvinfo(struct net_device *dev, 1305 struct ethtool_drvinfo *info) 1306 { 1307 struct bnxt *bp = netdev_priv(dev); 1308 1309 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1310 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1311 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1312 info->n_stats = bnxt_get_num_stats(bp); 1313 info->testinfo_len = bp->num_tests; 1314 /* TODO CHIMP_FW: eeprom dump details */ 1315 info->eedump_len = 0; 1316 /* TODO CHIMP FW: reg dump details */ 1317 info->regdump_len = 0; 1318 } 1319 1320 static int bnxt_get_regs_len(struct net_device *dev) 1321 { 1322 struct bnxt *bp = netdev_priv(dev); 1323 int reg_len; 1324 1325 if (!BNXT_PF(bp)) 1326 return -EOPNOTSUPP; 1327 1328 reg_len = BNXT_PXP_REG_LEN; 1329 1330 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1331 reg_len += sizeof(struct pcie_ctx_hw_stats); 1332 1333 return reg_len; 1334 } 1335 1336 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1337 void *_p) 1338 { 1339 struct pcie_ctx_hw_stats *hw_pcie_stats; 1340 struct hwrm_pcie_qstats_input req = {0}; 1341 struct bnxt *bp = netdev_priv(dev); 1342 dma_addr_t hw_pcie_stats_addr; 1343 int rc; 1344 1345 regs->version = 0; 1346 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1347 1348 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1349 return; 1350 1351 hw_pcie_stats = dma_alloc_coherent(&bp->pdev->dev, 1352 sizeof(*hw_pcie_stats), 1353 &hw_pcie_stats_addr, GFP_KERNEL); 1354 if (!hw_pcie_stats) 1355 return; 1356 1357 regs->version = 1; 1358 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 1359 req.pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1360 req.pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1361 mutex_lock(&bp->hwrm_cmd_lock); 1362 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1363 if (!rc) { 1364 __le64 *src = (__le64 *)hw_pcie_stats; 1365 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1366 int i; 1367 1368 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1369 dst[i] = le64_to_cpu(src[i]); 1370 } 1371 mutex_unlock(&bp->hwrm_cmd_lock); 1372 dma_free_coherent(&bp->pdev->dev, sizeof(*hw_pcie_stats), hw_pcie_stats, 1373 hw_pcie_stats_addr); 1374 } 1375 1376 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1377 { 1378 struct bnxt *bp = netdev_priv(dev); 1379 1380 wol->supported = 0; 1381 wol->wolopts = 0; 1382 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1383 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1384 wol->supported = WAKE_MAGIC; 1385 if (bp->wol) 1386 wol->wolopts = WAKE_MAGIC; 1387 } 1388 } 1389 1390 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1391 { 1392 struct bnxt *bp = netdev_priv(dev); 1393 1394 if (wol->wolopts & ~WAKE_MAGIC) 1395 return -EINVAL; 1396 1397 if (wol->wolopts & WAKE_MAGIC) { 1398 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1399 return -EINVAL; 1400 if (!bp->wol) { 1401 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1402 return -EBUSY; 1403 bp->wol = 1; 1404 } 1405 } else { 1406 if (bp->wol) { 1407 if (bnxt_hwrm_free_wol_fltr(bp)) 1408 return -EBUSY; 1409 bp->wol = 0; 1410 } 1411 } 1412 return 0; 1413 } 1414 1415 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1416 { 1417 u32 speed_mask = 0; 1418 1419 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1420 /* set the advertised speeds */ 1421 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1422 speed_mask |= ADVERTISED_100baseT_Full; 1423 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1424 speed_mask |= ADVERTISED_1000baseT_Full; 1425 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1426 speed_mask |= ADVERTISED_2500baseX_Full; 1427 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1428 speed_mask |= ADVERTISED_10000baseT_Full; 1429 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1430 speed_mask |= ADVERTISED_40000baseCR4_Full; 1431 1432 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1433 speed_mask |= ADVERTISED_Pause; 1434 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1435 speed_mask |= ADVERTISED_Asym_Pause; 1436 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1437 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1438 1439 return speed_mask; 1440 } 1441 1442 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1443 { \ 1444 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1445 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1446 100baseT_Full); \ 1447 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1448 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1449 1000baseT_Full); \ 1450 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1451 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1452 10000baseT_Full); \ 1453 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1454 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1455 25000baseCR_Full); \ 1456 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1457 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1458 40000baseCR4_Full);\ 1459 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1460 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1461 50000baseCR2_Full);\ 1462 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1463 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1464 100000baseCR4_Full);\ 1465 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1466 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1467 Pause); \ 1468 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1469 ethtool_link_ksettings_add_link_mode( \ 1470 lk_ksettings, name, Asym_Pause);\ 1471 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1472 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1473 Asym_Pause); \ 1474 } \ 1475 } 1476 1477 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1478 { \ 1479 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1480 100baseT_Full) || \ 1481 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1482 100baseT_Half)) \ 1483 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1484 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1485 1000baseT_Full) || \ 1486 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1487 1000baseT_Half)) \ 1488 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1489 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1490 10000baseT_Full)) \ 1491 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1492 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1493 25000baseCR_Full)) \ 1494 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1495 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1496 40000baseCR4_Full)) \ 1497 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1498 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1499 50000baseCR2_Full)) \ 1500 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1501 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1502 100000baseCR4_Full)) \ 1503 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1504 } 1505 1506 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1507 struct ethtool_link_ksettings *lk_ksettings) 1508 { 1509 u16 fw_speeds = link_info->advertising; 1510 u8 fw_pause = 0; 1511 1512 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1513 fw_pause = link_info->auto_pause_setting; 1514 1515 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1516 } 1517 1518 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1519 struct ethtool_link_ksettings *lk_ksettings) 1520 { 1521 u16 fw_speeds = link_info->lp_auto_link_speeds; 1522 u8 fw_pause = 0; 1523 1524 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1525 fw_pause = link_info->lp_pause; 1526 1527 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1528 lp_advertising); 1529 } 1530 1531 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1532 struct ethtool_link_ksettings *lk_ksettings) 1533 { 1534 u16 fw_speeds = link_info->support_speeds; 1535 1536 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1537 1538 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1539 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1540 Asym_Pause); 1541 1542 if (link_info->support_auto_speeds) 1543 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1544 Autoneg); 1545 } 1546 1547 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1548 { 1549 switch (fw_link_speed) { 1550 case BNXT_LINK_SPEED_100MB: 1551 return SPEED_100; 1552 case BNXT_LINK_SPEED_1GB: 1553 return SPEED_1000; 1554 case BNXT_LINK_SPEED_2_5GB: 1555 return SPEED_2500; 1556 case BNXT_LINK_SPEED_10GB: 1557 return SPEED_10000; 1558 case BNXT_LINK_SPEED_20GB: 1559 return SPEED_20000; 1560 case BNXT_LINK_SPEED_25GB: 1561 return SPEED_25000; 1562 case BNXT_LINK_SPEED_40GB: 1563 return SPEED_40000; 1564 case BNXT_LINK_SPEED_50GB: 1565 return SPEED_50000; 1566 case BNXT_LINK_SPEED_100GB: 1567 return SPEED_100000; 1568 default: 1569 return SPEED_UNKNOWN; 1570 } 1571 } 1572 1573 static int bnxt_get_link_ksettings(struct net_device *dev, 1574 struct ethtool_link_ksettings *lk_ksettings) 1575 { 1576 struct bnxt *bp = netdev_priv(dev); 1577 struct bnxt_link_info *link_info = &bp->link_info; 1578 struct ethtool_link_settings *base = &lk_ksettings->base; 1579 u32 ethtool_speed; 1580 1581 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1582 mutex_lock(&bp->link_lock); 1583 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1584 1585 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1586 if (link_info->autoneg) { 1587 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1588 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1589 advertising, Autoneg); 1590 base->autoneg = AUTONEG_ENABLE; 1591 base->duplex = DUPLEX_UNKNOWN; 1592 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1593 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1594 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1595 base->duplex = DUPLEX_FULL; 1596 else 1597 base->duplex = DUPLEX_HALF; 1598 } 1599 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1600 } else { 1601 base->autoneg = AUTONEG_DISABLE; 1602 ethtool_speed = 1603 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1604 base->duplex = DUPLEX_HALF; 1605 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1606 base->duplex = DUPLEX_FULL; 1607 } 1608 base->speed = ethtool_speed; 1609 1610 base->port = PORT_NONE; 1611 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1612 base->port = PORT_TP; 1613 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1614 TP); 1615 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1616 TP); 1617 } else { 1618 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1619 FIBRE); 1620 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1621 FIBRE); 1622 1623 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1624 base->port = PORT_DA; 1625 else if (link_info->media_type == 1626 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1627 base->port = PORT_FIBRE; 1628 } 1629 base->phy_address = link_info->phy_addr; 1630 mutex_unlock(&bp->link_lock); 1631 1632 return 0; 1633 } 1634 1635 static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed) 1636 { 1637 struct bnxt *bp = netdev_priv(dev); 1638 struct bnxt_link_info *link_info = &bp->link_info; 1639 u16 support_spds = link_info->support_speeds; 1640 u32 fw_speed = 0; 1641 1642 switch (ethtool_speed) { 1643 case SPEED_100: 1644 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1645 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB; 1646 break; 1647 case SPEED_1000: 1648 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1649 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB; 1650 break; 1651 case SPEED_2500: 1652 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1653 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB; 1654 break; 1655 case SPEED_10000: 1656 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1657 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB; 1658 break; 1659 case SPEED_20000: 1660 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1661 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB; 1662 break; 1663 case SPEED_25000: 1664 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1665 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB; 1666 break; 1667 case SPEED_40000: 1668 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1669 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB; 1670 break; 1671 case SPEED_50000: 1672 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) 1673 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB; 1674 break; 1675 case SPEED_100000: 1676 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) 1677 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB; 1678 break; 1679 default: 1680 netdev_err(dev, "unsupported speed!\n"); 1681 break; 1682 } 1683 return fw_speed; 1684 } 1685 1686 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1687 { 1688 u16 fw_speed_mask = 0; 1689 1690 /* only support autoneg at speed 100, 1000, and 10000 */ 1691 if (advertising & (ADVERTISED_100baseT_Full | 1692 ADVERTISED_100baseT_Half)) { 1693 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1694 } 1695 if (advertising & (ADVERTISED_1000baseT_Full | 1696 ADVERTISED_1000baseT_Half)) { 1697 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1698 } 1699 if (advertising & ADVERTISED_10000baseT_Full) 1700 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1701 1702 if (advertising & ADVERTISED_40000baseCR4_Full) 1703 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1704 1705 return fw_speed_mask; 1706 } 1707 1708 static int bnxt_set_link_ksettings(struct net_device *dev, 1709 const struct ethtool_link_ksettings *lk_ksettings) 1710 { 1711 struct bnxt *bp = netdev_priv(dev); 1712 struct bnxt_link_info *link_info = &bp->link_info; 1713 const struct ethtool_link_settings *base = &lk_ksettings->base; 1714 bool set_pause = false; 1715 u16 fw_advertising = 0; 1716 u32 speed; 1717 int rc = 0; 1718 1719 if (!BNXT_PHY_CFG_ABLE(bp)) 1720 return -EOPNOTSUPP; 1721 1722 mutex_lock(&bp->link_lock); 1723 if (base->autoneg == AUTONEG_ENABLE) { 1724 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings, 1725 advertising); 1726 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1727 if (!fw_advertising) 1728 link_info->advertising = link_info->support_auto_speeds; 1729 else 1730 link_info->advertising = fw_advertising; 1731 /* any change to autoneg will cause link change, therefore the 1732 * driver should put back the original pause setting in autoneg 1733 */ 1734 set_pause = true; 1735 } else { 1736 u16 fw_speed; 1737 u8 phy_type = link_info->phy_type; 1738 1739 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1740 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1741 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1742 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1743 rc = -EINVAL; 1744 goto set_setting_exit; 1745 } 1746 if (base->duplex == DUPLEX_HALF) { 1747 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1748 rc = -EINVAL; 1749 goto set_setting_exit; 1750 } 1751 speed = base->speed; 1752 fw_speed = bnxt_get_fw_speed(dev, speed); 1753 if (!fw_speed) { 1754 rc = -EINVAL; 1755 goto set_setting_exit; 1756 } 1757 link_info->req_link_speed = fw_speed; 1758 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1759 link_info->autoneg = 0; 1760 link_info->advertising = 0; 1761 } 1762 1763 if (netif_running(dev)) 1764 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1765 1766 set_setting_exit: 1767 mutex_unlock(&bp->link_lock); 1768 return rc; 1769 } 1770 1771 static void bnxt_get_pauseparam(struct net_device *dev, 1772 struct ethtool_pauseparam *epause) 1773 { 1774 struct bnxt *bp = netdev_priv(dev); 1775 struct bnxt_link_info *link_info = &bp->link_info; 1776 1777 if (BNXT_VF(bp)) 1778 return; 1779 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 1780 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 1781 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 1782 } 1783 1784 static int bnxt_set_pauseparam(struct net_device *dev, 1785 struct ethtool_pauseparam *epause) 1786 { 1787 int rc = 0; 1788 struct bnxt *bp = netdev_priv(dev); 1789 struct bnxt_link_info *link_info = &bp->link_info; 1790 1791 if (!BNXT_PHY_CFG_ABLE(bp)) 1792 return -EOPNOTSUPP; 1793 1794 mutex_lock(&bp->link_lock); 1795 if (epause->autoneg) { 1796 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 1797 rc = -EINVAL; 1798 goto pause_exit; 1799 } 1800 1801 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 1802 if (bp->hwrm_spec_code >= 0x10201) 1803 link_info->req_flow_ctrl = 1804 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 1805 } else { 1806 /* when transition from auto pause to force pause, 1807 * force a link change 1808 */ 1809 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1810 link_info->force_link_chng = true; 1811 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 1812 link_info->req_flow_ctrl = 0; 1813 } 1814 if (epause->rx_pause) 1815 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 1816 1817 if (epause->tx_pause) 1818 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 1819 1820 if (netif_running(dev)) 1821 rc = bnxt_hwrm_set_pause(bp); 1822 1823 pause_exit: 1824 mutex_unlock(&bp->link_lock); 1825 return rc; 1826 } 1827 1828 static u32 bnxt_get_link(struct net_device *dev) 1829 { 1830 struct bnxt *bp = netdev_priv(dev); 1831 1832 /* TODO: handle MF, VF, driver close case */ 1833 return bp->link_info.link_up; 1834 } 1835 1836 static void bnxt_print_admin_err(struct bnxt *bp) 1837 { 1838 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 1839 } 1840 1841 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 1842 u16 ext, u16 *index, u32 *item_length, 1843 u32 *data_length); 1844 1845 static int bnxt_flash_nvram(struct net_device *dev, 1846 u16 dir_type, 1847 u16 dir_ordinal, 1848 u16 dir_ext, 1849 u16 dir_attr, 1850 const u8 *data, 1851 size_t data_len) 1852 { 1853 struct bnxt *bp = netdev_priv(dev); 1854 int rc; 1855 struct hwrm_nvm_write_input req = {0}; 1856 dma_addr_t dma_handle; 1857 u8 *kmem; 1858 1859 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 1860 1861 req.dir_type = cpu_to_le16(dir_type); 1862 req.dir_ordinal = cpu_to_le16(dir_ordinal); 1863 req.dir_ext = cpu_to_le16(dir_ext); 1864 req.dir_attr = cpu_to_le16(dir_attr); 1865 req.dir_data_length = cpu_to_le32(data_len); 1866 1867 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 1868 GFP_KERNEL); 1869 if (!kmem) { 1870 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 1871 (unsigned)data_len); 1872 return -ENOMEM; 1873 } 1874 memcpy(kmem, data, data_len); 1875 req.host_src_addr = cpu_to_le64(dma_handle); 1876 1877 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 1878 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 1879 1880 if (rc == -EACCES) 1881 bnxt_print_admin_err(bp); 1882 return rc; 1883 } 1884 1885 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 1886 u8 self_reset, u8 flags) 1887 { 1888 struct hwrm_fw_reset_input req = {0}; 1889 struct bnxt *bp = netdev_priv(dev); 1890 int rc; 1891 1892 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 1893 1894 req.embedded_proc_type = proc_type; 1895 req.selfrst_status = self_reset; 1896 req.flags = flags; 1897 1898 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 1899 rc = hwrm_send_message_silent(bp, &req, sizeof(req), 1900 HWRM_CMD_TIMEOUT); 1901 } else { 1902 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1903 if (rc == -EACCES) 1904 bnxt_print_admin_err(bp); 1905 } 1906 return rc; 1907 } 1908 1909 static int bnxt_firmware_reset(struct net_device *dev, 1910 enum bnxt_nvm_directory_type dir_type) 1911 { 1912 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 1913 u8 proc_type, flags = 0; 1914 1915 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 1916 /* (e.g. when firmware isn't already running) */ 1917 switch (dir_type) { 1918 case BNX_DIR_TYPE_CHIMP_PATCH: 1919 case BNX_DIR_TYPE_BOOTCODE: 1920 case BNX_DIR_TYPE_BOOTCODE_2: 1921 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 1922 /* Self-reset ChiMP upon next PCIe reset: */ 1923 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1924 break; 1925 case BNX_DIR_TYPE_APE_FW: 1926 case BNX_DIR_TYPE_APE_PATCH: 1927 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 1928 /* Self-reset APE upon next PCIe reset: */ 1929 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1930 break; 1931 case BNX_DIR_TYPE_KONG_FW: 1932 case BNX_DIR_TYPE_KONG_PATCH: 1933 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 1934 break; 1935 case BNX_DIR_TYPE_BONO_FW: 1936 case BNX_DIR_TYPE_BONO_PATCH: 1937 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 1938 break; 1939 default: 1940 return -EINVAL; 1941 } 1942 1943 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 1944 } 1945 1946 static int bnxt_firmware_reset_chip(struct net_device *dev) 1947 { 1948 struct bnxt *bp = netdev_priv(dev); 1949 u8 flags = 0; 1950 1951 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 1952 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 1953 1954 return bnxt_hwrm_firmware_reset(dev, 1955 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 1956 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 1957 flags); 1958 } 1959 1960 static int bnxt_firmware_reset_ap(struct net_device *dev) 1961 { 1962 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 1963 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 1964 0); 1965 } 1966 1967 static int bnxt_flash_firmware(struct net_device *dev, 1968 u16 dir_type, 1969 const u8 *fw_data, 1970 size_t fw_size) 1971 { 1972 int rc = 0; 1973 u16 code_type; 1974 u32 stored_crc; 1975 u32 calculated_crc; 1976 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 1977 1978 switch (dir_type) { 1979 case BNX_DIR_TYPE_BOOTCODE: 1980 case BNX_DIR_TYPE_BOOTCODE_2: 1981 code_type = CODE_BOOT; 1982 break; 1983 case BNX_DIR_TYPE_CHIMP_PATCH: 1984 code_type = CODE_CHIMP_PATCH; 1985 break; 1986 case BNX_DIR_TYPE_APE_FW: 1987 code_type = CODE_MCTP_PASSTHRU; 1988 break; 1989 case BNX_DIR_TYPE_APE_PATCH: 1990 code_type = CODE_APE_PATCH; 1991 break; 1992 case BNX_DIR_TYPE_KONG_FW: 1993 code_type = CODE_KONG_FW; 1994 break; 1995 case BNX_DIR_TYPE_KONG_PATCH: 1996 code_type = CODE_KONG_PATCH; 1997 break; 1998 case BNX_DIR_TYPE_BONO_FW: 1999 code_type = CODE_BONO_FW; 2000 break; 2001 case BNX_DIR_TYPE_BONO_PATCH: 2002 code_type = CODE_BONO_PATCH; 2003 break; 2004 default: 2005 netdev_err(dev, "Unsupported directory entry type: %u\n", 2006 dir_type); 2007 return -EINVAL; 2008 } 2009 if (fw_size < sizeof(struct bnxt_fw_header)) { 2010 netdev_err(dev, "Invalid firmware file size: %u\n", 2011 (unsigned int)fw_size); 2012 return -EINVAL; 2013 } 2014 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2015 netdev_err(dev, "Invalid firmware signature: %08X\n", 2016 le32_to_cpu(header->signature)); 2017 return -EINVAL; 2018 } 2019 if (header->code_type != code_type) { 2020 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2021 code_type, header->code_type); 2022 return -EINVAL; 2023 } 2024 if (header->device != DEVICE_CUMULUS_FAMILY) { 2025 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2026 DEVICE_CUMULUS_FAMILY, header->device); 2027 return -EINVAL; 2028 } 2029 /* Confirm the CRC32 checksum of the file: */ 2030 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2031 sizeof(stored_crc))); 2032 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2033 if (calculated_crc != stored_crc) { 2034 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2035 (unsigned long)stored_crc, 2036 (unsigned long)calculated_crc); 2037 return -EINVAL; 2038 } 2039 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2040 0, 0, fw_data, fw_size); 2041 if (rc == 0) /* Firmware update successful */ 2042 rc = bnxt_firmware_reset(dev, dir_type); 2043 2044 return rc; 2045 } 2046 2047 static int bnxt_flash_microcode(struct net_device *dev, 2048 u16 dir_type, 2049 const u8 *fw_data, 2050 size_t fw_size) 2051 { 2052 struct bnxt_ucode_trailer *trailer; 2053 u32 calculated_crc; 2054 u32 stored_crc; 2055 int rc = 0; 2056 2057 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2058 netdev_err(dev, "Invalid microcode file size: %u\n", 2059 (unsigned int)fw_size); 2060 return -EINVAL; 2061 } 2062 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2063 sizeof(*trailer))); 2064 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2065 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2066 le32_to_cpu(trailer->sig)); 2067 return -EINVAL; 2068 } 2069 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2070 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2071 dir_type, le16_to_cpu(trailer->dir_type)); 2072 return -EINVAL; 2073 } 2074 if (le16_to_cpu(trailer->trailer_length) < 2075 sizeof(struct bnxt_ucode_trailer)) { 2076 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2077 le16_to_cpu(trailer->trailer_length)); 2078 return -EINVAL; 2079 } 2080 2081 /* Confirm the CRC32 checksum of the file: */ 2082 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2083 sizeof(stored_crc))); 2084 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2085 if (calculated_crc != stored_crc) { 2086 netdev_err(dev, 2087 "CRC32 (%08lX) does not match calculated: %08lX\n", 2088 (unsigned long)stored_crc, 2089 (unsigned long)calculated_crc); 2090 return -EINVAL; 2091 } 2092 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2093 0, 0, fw_data, fw_size); 2094 2095 return rc; 2096 } 2097 2098 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2099 { 2100 switch (dir_type) { 2101 case BNX_DIR_TYPE_CHIMP_PATCH: 2102 case BNX_DIR_TYPE_BOOTCODE: 2103 case BNX_DIR_TYPE_BOOTCODE_2: 2104 case BNX_DIR_TYPE_APE_FW: 2105 case BNX_DIR_TYPE_APE_PATCH: 2106 case BNX_DIR_TYPE_KONG_FW: 2107 case BNX_DIR_TYPE_KONG_PATCH: 2108 case BNX_DIR_TYPE_BONO_FW: 2109 case BNX_DIR_TYPE_BONO_PATCH: 2110 return true; 2111 } 2112 2113 return false; 2114 } 2115 2116 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2117 { 2118 switch (dir_type) { 2119 case BNX_DIR_TYPE_AVS: 2120 case BNX_DIR_TYPE_EXP_ROM_MBA: 2121 case BNX_DIR_TYPE_PCIE: 2122 case BNX_DIR_TYPE_TSCF_UCODE: 2123 case BNX_DIR_TYPE_EXT_PHY: 2124 case BNX_DIR_TYPE_CCM: 2125 case BNX_DIR_TYPE_ISCSI_BOOT: 2126 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2127 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2128 return true; 2129 } 2130 2131 return false; 2132 } 2133 2134 static bool bnxt_dir_type_is_executable(u16 dir_type) 2135 { 2136 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2137 bnxt_dir_type_is_other_exec_format(dir_type); 2138 } 2139 2140 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2141 u16 dir_type, 2142 const char *filename) 2143 { 2144 const struct firmware *fw; 2145 int rc; 2146 2147 rc = request_firmware(&fw, filename, &dev->dev); 2148 if (rc != 0) { 2149 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2150 rc, filename); 2151 return rc; 2152 } 2153 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2154 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2155 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2156 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2157 else 2158 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2159 0, 0, fw->data, fw->size); 2160 release_firmware(fw); 2161 return rc; 2162 } 2163 2164 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2165 u32 install_type) 2166 { 2167 struct bnxt *bp = netdev_priv(dev); 2168 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2169 struct hwrm_nvm_install_update_input install = {0}; 2170 const struct firmware *fw; 2171 u32 item_len; 2172 int rc = 0; 2173 u16 index; 2174 2175 bnxt_hwrm_fw_set_time(bp); 2176 2177 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2178 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2179 &index, &item_len, NULL); 2180 if (rc) { 2181 netdev_err(dev, "PKG update area not created in nvram\n"); 2182 return rc; 2183 } 2184 2185 rc = request_firmware(&fw, filename, &dev->dev); 2186 if (rc != 0) { 2187 netdev_err(dev, "PKG error %d requesting file: %s\n", 2188 rc, filename); 2189 return rc; 2190 } 2191 2192 if (fw->size > item_len) { 2193 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2194 (unsigned long)fw->size); 2195 rc = -EFBIG; 2196 } else { 2197 dma_addr_t dma_handle; 2198 u8 *kmem; 2199 struct hwrm_nvm_modify_input modify = {0}; 2200 2201 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2202 2203 modify.dir_idx = cpu_to_le16(index); 2204 modify.len = cpu_to_le32(fw->size); 2205 2206 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2207 &dma_handle, GFP_KERNEL); 2208 if (!kmem) { 2209 netdev_err(dev, 2210 "dma_alloc_coherent failure, length = %u\n", 2211 (unsigned int)fw->size); 2212 rc = -ENOMEM; 2213 } else { 2214 memcpy(kmem, fw->data, fw->size); 2215 modify.host_src_addr = cpu_to_le64(dma_handle); 2216 2217 rc = hwrm_send_message(bp, &modify, sizeof(modify), 2218 FLASH_PACKAGE_TIMEOUT); 2219 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2220 dma_handle); 2221 } 2222 } 2223 release_firmware(fw); 2224 if (rc) 2225 goto err_exit; 2226 2227 if ((install_type & 0xffff) == 0) 2228 install_type >>= 16; 2229 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2230 install.install_type = cpu_to_le32(install_type); 2231 2232 mutex_lock(&bp->hwrm_cmd_lock); 2233 rc = _hwrm_send_message(bp, &install, sizeof(install), 2234 INSTALL_PACKAGE_TIMEOUT); 2235 if (rc) { 2236 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2237 2238 if (resp->error_code && error_code == 2239 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2240 install.flags |= cpu_to_le16( 2241 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2242 rc = _hwrm_send_message(bp, &install, sizeof(install), 2243 INSTALL_PACKAGE_TIMEOUT); 2244 } 2245 if (rc) 2246 goto flash_pkg_exit; 2247 } 2248 2249 if (resp->result) { 2250 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2251 (s8)resp->result, (int)resp->problem_item); 2252 rc = -ENOPKG; 2253 } 2254 flash_pkg_exit: 2255 mutex_unlock(&bp->hwrm_cmd_lock); 2256 err_exit: 2257 if (rc == -EACCES) 2258 bnxt_print_admin_err(bp); 2259 return rc; 2260 } 2261 2262 static int bnxt_flash_device(struct net_device *dev, 2263 struct ethtool_flash *flash) 2264 { 2265 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2266 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2267 return -EINVAL; 2268 } 2269 2270 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2271 flash->region > 0xffff) 2272 return bnxt_flash_package_from_file(dev, flash->data, 2273 flash->region); 2274 2275 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2276 } 2277 2278 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2279 { 2280 struct bnxt *bp = netdev_priv(dev); 2281 int rc; 2282 struct hwrm_nvm_get_dir_info_input req = {0}; 2283 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2284 2285 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2286 2287 mutex_lock(&bp->hwrm_cmd_lock); 2288 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2289 if (!rc) { 2290 *entries = le32_to_cpu(output->entries); 2291 *length = le32_to_cpu(output->entry_length); 2292 } 2293 mutex_unlock(&bp->hwrm_cmd_lock); 2294 return rc; 2295 } 2296 2297 static int bnxt_get_eeprom_len(struct net_device *dev) 2298 { 2299 struct bnxt *bp = netdev_priv(dev); 2300 2301 if (BNXT_VF(bp)) 2302 return 0; 2303 2304 /* The -1 return value allows the entire 32-bit range of offsets to be 2305 * passed via the ethtool command-line utility. 2306 */ 2307 return -1; 2308 } 2309 2310 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2311 { 2312 struct bnxt *bp = netdev_priv(dev); 2313 int rc; 2314 u32 dir_entries; 2315 u32 entry_length; 2316 u8 *buf; 2317 size_t buflen; 2318 dma_addr_t dma_handle; 2319 struct hwrm_nvm_get_dir_entries_input req = {0}; 2320 2321 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2322 if (rc != 0) 2323 return rc; 2324 2325 if (!dir_entries || !entry_length) 2326 return -EIO; 2327 2328 /* Insert 2 bytes of directory info (count and size of entries) */ 2329 if (len < 2) 2330 return -EINVAL; 2331 2332 *data++ = dir_entries; 2333 *data++ = entry_length; 2334 len -= 2; 2335 memset(data, 0xff, len); 2336 2337 buflen = dir_entries * entry_length; 2338 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2339 GFP_KERNEL); 2340 if (!buf) { 2341 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2342 (unsigned)buflen); 2343 return -ENOMEM; 2344 } 2345 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2346 req.host_dest_addr = cpu_to_le64(dma_handle); 2347 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2348 if (rc == 0) 2349 memcpy(data, buf, len > buflen ? buflen : len); 2350 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2351 return rc; 2352 } 2353 2354 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2355 u32 length, u8 *data) 2356 { 2357 struct bnxt *bp = netdev_priv(dev); 2358 int rc; 2359 u8 *buf; 2360 dma_addr_t dma_handle; 2361 struct hwrm_nvm_read_input req = {0}; 2362 2363 if (!length) 2364 return -EINVAL; 2365 2366 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2367 GFP_KERNEL); 2368 if (!buf) { 2369 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2370 (unsigned)length); 2371 return -ENOMEM; 2372 } 2373 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2374 req.host_dest_addr = cpu_to_le64(dma_handle); 2375 req.dir_idx = cpu_to_le16(index); 2376 req.offset = cpu_to_le32(offset); 2377 req.len = cpu_to_le32(length); 2378 2379 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2380 if (rc == 0) 2381 memcpy(data, buf, length); 2382 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2383 return rc; 2384 } 2385 2386 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2387 u16 ext, u16 *index, u32 *item_length, 2388 u32 *data_length) 2389 { 2390 struct bnxt *bp = netdev_priv(dev); 2391 int rc; 2392 struct hwrm_nvm_find_dir_entry_input req = {0}; 2393 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2394 2395 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2396 req.enables = 0; 2397 req.dir_idx = 0; 2398 req.dir_type = cpu_to_le16(type); 2399 req.dir_ordinal = cpu_to_le16(ordinal); 2400 req.dir_ext = cpu_to_le16(ext); 2401 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2402 mutex_lock(&bp->hwrm_cmd_lock); 2403 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2404 if (rc == 0) { 2405 if (index) 2406 *index = le16_to_cpu(output->dir_idx); 2407 if (item_length) 2408 *item_length = le32_to_cpu(output->dir_item_length); 2409 if (data_length) 2410 *data_length = le32_to_cpu(output->dir_data_length); 2411 } 2412 mutex_unlock(&bp->hwrm_cmd_lock); 2413 return rc; 2414 } 2415 2416 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2417 { 2418 char *retval = NULL; 2419 char *p; 2420 char *value; 2421 int field = 0; 2422 2423 if (datalen < 1) 2424 return NULL; 2425 /* null-terminate the log data (removing last '\n'): */ 2426 data[datalen - 1] = 0; 2427 for (p = data; *p != 0; p++) { 2428 field = 0; 2429 retval = NULL; 2430 while (*p != 0 && *p != '\n') { 2431 value = p; 2432 while (*p != 0 && *p != '\t' && *p != '\n') 2433 p++; 2434 if (field == desired_field) 2435 retval = value; 2436 if (*p != '\t') 2437 break; 2438 *p = 0; 2439 field++; 2440 p++; 2441 } 2442 if (*p == 0) 2443 break; 2444 *p = 0; 2445 } 2446 return retval; 2447 } 2448 2449 static void bnxt_get_pkgver(struct net_device *dev) 2450 { 2451 struct bnxt *bp = netdev_priv(dev); 2452 u16 index = 0; 2453 char *pkgver; 2454 u32 pkglen; 2455 u8 *pkgbuf; 2456 int len; 2457 2458 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2459 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2460 &index, NULL, &pkglen) != 0) 2461 return; 2462 2463 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2464 if (!pkgbuf) { 2465 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2466 pkglen); 2467 return; 2468 } 2469 2470 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2471 goto err; 2472 2473 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2474 pkglen); 2475 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2476 len = strlen(bp->fw_ver_str); 2477 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2478 "/pkg %s", pkgver); 2479 } 2480 err: 2481 kfree(pkgbuf); 2482 } 2483 2484 static int bnxt_get_eeprom(struct net_device *dev, 2485 struct ethtool_eeprom *eeprom, 2486 u8 *data) 2487 { 2488 u32 index; 2489 u32 offset; 2490 2491 if (eeprom->offset == 0) /* special offset value to get directory */ 2492 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2493 2494 index = eeprom->offset >> 24; 2495 offset = eeprom->offset & 0xffffff; 2496 2497 if (index == 0) { 2498 netdev_err(dev, "unsupported index value: %d\n", index); 2499 return -EINVAL; 2500 } 2501 2502 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2503 } 2504 2505 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2506 { 2507 struct bnxt *bp = netdev_priv(dev); 2508 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2509 2510 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2511 req.dir_idx = cpu_to_le16(index); 2512 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2513 } 2514 2515 static int bnxt_set_eeprom(struct net_device *dev, 2516 struct ethtool_eeprom *eeprom, 2517 u8 *data) 2518 { 2519 struct bnxt *bp = netdev_priv(dev); 2520 u8 index, dir_op; 2521 u16 type, ext, ordinal, attr; 2522 2523 if (!BNXT_PF(bp)) { 2524 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2525 return -EINVAL; 2526 } 2527 2528 type = eeprom->magic >> 16; 2529 2530 if (type == 0xffff) { /* special value for directory operations */ 2531 index = eeprom->magic & 0xff; 2532 dir_op = eeprom->magic >> 8; 2533 if (index == 0) 2534 return -EINVAL; 2535 switch (dir_op) { 2536 case 0x0e: /* erase */ 2537 if (eeprom->offset != ~eeprom->magic) 2538 return -EINVAL; 2539 return bnxt_erase_nvram_directory(dev, index - 1); 2540 default: 2541 return -EINVAL; 2542 } 2543 } 2544 2545 /* Create or re-write an NVM item: */ 2546 if (bnxt_dir_type_is_executable(type)) 2547 return -EOPNOTSUPP; 2548 ext = eeprom->magic & 0xffff; 2549 ordinal = eeprom->offset >> 16; 2550 attr = eeprom->offset & 0xffff; 2551 2552 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2553 eeprom->len); 2554 } 2555 2556 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2557 { 2558 struct bnxt *bp = netdev_priv(dev); 2559 struct ethtool_eee *eee = &bp->eee; 2560 struct bnxt_link_info *link_info = &bp->link_info; 2561 u32 advertising; 2562 int rc = 0; 2563 2564 if (!BNXT_PHY_CFG_ABLE(bp)) 2565 return -EOPNOTSUPP; 2566 2567 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2568 return -EOPNOTSUPP; 2569 2570 mutex_lock(&bp->link_lock); 2571 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2572 if (!edata->eee_enabled) 2573 goto eee_ok; 2574 2575 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2576 netdev_warn(dev, "EEE requires autoneg\n"); 2577 rc = -EINVAL; 2578 goto eee_exit; 2579 } 2580 if (edata->tx_lpi_enabled) { 2581 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2582 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2583 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2584 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2585 rc = -EINVAL; 2586 goto eee_exit; 2587 } else if (!bp->lpi_tmr_hi) { 2588 edata->tx_lpi_timer = eee->tx_lpi_timer; 2589 } 2590 } 2591 if (!edata->advertised) { 2592 edata->advertised = advertising & eee->supported; 2593 } else if (edata->advertised & ~advertising) { 2594 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2595 edata->advertised, advertising); 2596 rc = -EINVAL; 2597 goto eee_exit; 2598 } 2599 2600 eee->advertised = edata->advertised; 2601 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2602 eee->tx_lpi_timer = edata->tx_lpi_timer; 2603 eee_ok: 2604 eee->eee_enabled = edata->eee_enabled; 2605 2606 if (netif_running(dev)) 2607 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2608 2609 eee_exit: 2610 mutex_unlock(&bp->link_lock); 2611 return rc; 2612 } 2613 2614 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2615 { 2616 struct bnxt *bp = netdev_priv(dev); 2617 2618 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2619 return -EOPNOTSUPP; 2620 2621 *edata = bp->eee; 2622 if (!bp->eee.eee_enabled) { 2623 /* Preserve tx_lpi_timer so that the last value will be used 2624 * by default when it is re-enabled. 2625 */ 2626 edata->advertised = 0; 2627 edata->tx_lpi_enabled = 0; 2628 } 2629 2630 if (!bp->eee.eee_active) 2631 edata->lp_advertised = 0; 2632 2633 return 0; 2634 } 2635 2636 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2637 u16 page_number, u16 start_addr, 2638 u16 data_length, u8 *buf) 2639 { 2640 struct hwrm_port_phy_i2c_read_input req = {0}; 2641 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2642 int rc, byte_offset = 0; 2643 2644 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2645 req.i2c_slave_addr = i2c_addr; 2646 req.page_number = cpu_to_le16(page_number); 2647 req.port_id = cpu_to_le16(bp->pf.port_id); 2648 do { 2649 u16 xfer_size; 2650 2651 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2652 data_length -= xfer_size; 2653 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2654 req.data_length = xfer_size; 2655 req.enables = cpu_to_le32(start_addr + byte_offset ? 2656 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2657 mutex_lock(&bp->hwrm_cmd_lock); 2658 rc = _hwrm_send_message(bp, &req, sizeof(req), 2659 HWRM_CMD_TIMEOUT); 2660 if (!rc) 2661 memcpy(buf + byte_offset, output->data, xfer_size); 2662 mutex_unlock(&bp->hwrm_cmd_lock); 2663 byte_offset += xfer_size; 2664 } while (!rc && data_length > 0); 2665 2666 return rc; 2667 } 2668 2669 static int bnxt_get_module_info(struct net_device *dev, 2670 struct ethtool_modinfo *modinfo) 2671 { 2672 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2673 struct bnxt *bp = netdev_priv(dev); 2674 int rc; 2675 2676 /* No point in going further if phy status indicates 2677 * module is not inserted or if it is powered down or 2678 * if it is of type 10GBase-T 2679 */ 2680 if (bp->link_info.module_status > 2681 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2682 return -EOPNOTSUPP; 2683 2684 /* This feature is not supported in older firmware versions */ 2685 if (bp->hwrm_spec_code < 0x10202) 2686 return -EOPNOTSUPP; 2687 2688 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2689 SFF_DIAG_SUPPORT_OFFSET + 1, 2690 data); 2691 if (!rc) { 2692 u8 module_id = data[0]; 2693 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2694 2695 switch (module_id) { 2696 case SFF_MODULE_ID_SFP: 2697 modinfo->type = ETH_MODULE_SFF_8472; 2698 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2699 if (!diag_supported) 2700 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2701 break; 2702 case SFF_MODULE_ID_QSFP: 2703 case SFF_MODULE_ID_QSFP_PLUS: 2704 modinfo->type = ETH_MODULE_SFF_8436; 2705 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2706 break; 2707 case SFF_MODULE_ID_QSFP28: 2708 modinfo->type = ETH_MODULE_SFF_8636; 2709 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2710 break; 2711 default: 2712 rc = -EOPNOTSUPP; 2713 break; 2714 } 2715 } 2716 return rc; 2717 } 2718 2719 static int bnxt_get_module_eeprom(struct net_device *dev, 2720 struct ethtool_eeprom *eeprom, 2721 u8 *data) 2722 { 2723 struct bnxt *bp = netdev_priv(dev); 2724 u16 start = eeprom->offset, length = eeprom->len; 2725 int rc = 0; 2726 2727 memset(data, 0, eeprom->len); 2728 2729 /* Read A0 portion of the EEPROM */ 2730 if (start < ETH_MODULE_SFF_8436_LEN) { 2731 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 2732 length = ETH_MODULE_SFF_8436_LEN - start; 2733 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 2734 start, length, data); 2735 if (rc) 2736 return rc; 2737 start += length; 2738 data += length; 2739 length = eeprom->len - length; 2740 } 2741 2742 /* Read A2 portion of the EEPROM */ 2743 if (length) { 2744 start -= ETH_MODULE_SFF_8436_LEN; 2745 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, 2746 start, length, data); 2747 } 2748 return rc; 2749 } 2750 2751 static int bnxt_nway_reset(struct net_device *dev) 2752 { 2753 int rc = 0; 2754 2755 struct bnxt *bp = netdev_priv(dev); 2756 struct bnxt_link_info *link_info = &bp->link_info; 2757 2758 if (!BNXT_PHY_CFG_ABLE(bp)) 2759 return -EOPNOTSUPP; 2760 2761 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 2762 return -EINVAL; 2763 2764 if (netif_running(dev)) 2765 rc = bnxt_hwrm_set_link_setting(bp, true, false); 2766 2767 return rc; 2768 } 2769 2770 static int bnxt_set_phys_id(struct net_device *dev, 2771 enum ethtool_phys_id_state state) 2772 { 2773 struct hwrm_port_led_cfg_input req = {0}; 2774 struct bnxt *bp = netdev_priv(dev); 2775 struct bnxt_pf_info *pf = &bp->pf; 2776 struct bnxt_led_cfg *led_cfg; 2777 u8 led_state; 2778 __le16 duration; 2779 int i; 2780 2781 if (!bp->num_leds || BNXT_VF(bp)) 2782 return -EOPNOTSUPP; 2783 2784 if (state == ETHTOOL_ID_ACTIVE) { 2785 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 2786 duration = cpu_to_le16(500); 2787 } else if (state == ETHTOOL_ID_INACTIVE) { 2788 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 2789 duration = cpu_to_le16(0); 2790 } else { 2791 return -EINVAL; 2792 } 2793 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 2794 req.port_id = cpu_to_le16(pf->port_id); 2795 req.num_leds = bp->num_leds; 2796 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 2797 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 2798 req.enables |= BNXT_LED_DFLT_ENABLES(i); 2799 led_cfg->led_id = bp->leds[i].led_id; 2800 led_cfg->led_state = led_state; 2801 led_cfg->led_blink_on = duration; 2802 led_cfg->led_blink_off = duration; 2803 led_cfg->led_group_id = bp->leds[i].led_group_id; 2804 } 2805 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2806 } 2807 2808 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 2809 { 2810 struct hwrm_selftest_irq_input req = {0}; 2811 2812 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 2813 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2814 } 2815 2816 static int bnxt_test_irq(struct bnxt *bp) 2817 { 2818 int i; 2819 2820 for (i = 0; i < bp->cp_nr_rings; i++) { 2821 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 2822 int rc; 2823 2824 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 2825 if (rc) 2826 return rc; 2827 } 2828 return 0; 2829 } 2830 2831 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 2832 { 2833 struct hwrm_port_mac_cfg_input req = {0}; 2834 2835 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 2836 2837 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 2838 if (enable) 2839 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 2840 else 2841 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 2842 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2843 } 2844 2845 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 2846 { 2847 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 2848 struct hwrm_port_phy_qcaps_input req = {0}; 2849 int rc; 2850 2851 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 2852 mutex_lock(&bp->hwrm_cmd_lock); 2853 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2854 if (!rc) 2855 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 2856 2857 mutex_unlock(&bp->hwrm_cmd_lock); 2858 return rc; 2859 } 2860 2861 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 2862 struct hwrm_port_phy_cfg_input *req) 2863 { 2864 struct bnxt_link_info *link_info = &bp->link_info; 2865 u16 fw_advertising; 2866 u16 fw_speed; 2867 int rc; 2868 2869 if (!link_info->autoneg || 2870 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK)) 2871 return 0; 2872 2873 rc = bnxt_query_force_speeds(bp, &fw_advertising); 2874 if (rc) 2875 return rc; 2876 2877 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2878 if (bp->link_info.link_up) 2879 fw_speed = bp->link_info.link_speed; 2880 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 2881 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2882 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 2883 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2884 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 2885 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2886 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 2887 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2888 2889 req->force_link_speed = cpu_to_le16(fw_speed); 2890 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 2891 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2892 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 2893 req->flags = 0; 2894 req->force_link_speed = cpu_to_le16(0); 2895 return rc; 2896 } 2897 2898 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 2899 { 2900 struct hwrm_port_phy_cfg_input req = {0}; 2901 2902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 2903 2904 if (enable) { 2905 bnxt_disable_an_for_lpbk(bp, &req); 2906 if (ext) 2907 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 2908 else 2909 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 2910 } else { 2911 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 2912 } 2913 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 2914 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2915 } 2916 2917 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2918 u32 raw_cons, int pkt_size) 2919 { 2920 struct bnxt_napi *bnapi = cpr->bnapi; 2921 struct bnxt_rx_ring_info *rxr; 2922 struct bnxt_sw_rx_bd *rx_buf; 2923 struct rx_cmp *rxcmp; 2924 u16 cp_cons, cons; 2925 u8 *data; 2926 u32 len; 2927 int i; 2928 2929 rxr = bnapi->rx_ring; 2930 cp_cons = RING_CMP(raw_cons); 2931 rxcmp = (struct rx_cmp *) 2932 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2933 cons = rxcmp->rx_cmp_opaque; 2934 rx_buf = &rxr->rx_buf_ring[cons]; 2935 data = rx_buf->data_ptr; 2936 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 2937 if (len != pkt_size) 2938 return -EIO; 2939 i = ETH_ALEN; 2940 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 2941 return -EIO; 2942 i += ETH_ALEN; 2943 for ( ; i < pkt_size; i++) { 2944 if (data[i] != (u8)(i & 0xff)) 2945 return -EIO; 2946 } 2947 return 0; 2948 } 2949 2950 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2951 int pkt_size) 2952 { 2953 struct tx_cmp *txcmp; 2954 int rc = -EIO; 2955 u32 raw_cons; 2956 u32 cons; 2957 int i; 2958 2959 raw_cons = cpr->cp_raw_cons; 2960 for (i = 0; i < 200; i++) { 2961 cons = RING_CMP(raw_cons); 2962 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2963 2964 if (!TX_CMP_VALID(txcmp, raw_cons)) { 2965 udelay(5); 2966 continue; 2967 } 2968 2969 /* The valid test of the entry must be done first before 2970 * reading any further. 2971 */ 2972 dma_rmb(); 2973 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 2974 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 2975 raw_cons = NEXT_RAW_CMP(raw_cons); 2976 raw_cons = NEXT_RAW_CMP(raw_cons); 2977 break; 2978 } 2979 raw_cons = NEXT_RAW_CMP(raw_cons); 2980 } 2981 cpr->cp_raw_cons = raw_cons; 2982 return rc; 2983 } 2984 2985 static int bnxt_run_loopback(struct bnxt *bp) 2986 { 2987 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 2988 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 2989 struct bnxt_cp_ring_info *cpr; 2990 int pkt_size, i = 0; 2991 struct sk_buff *skb; 2992 dma_addr_t map; 2993 u8 *data; 2994 int rc; 2995 2996 cpr = &rxr->bnapi->cp_ring; 2997 if (bp->flags & BNXT_FLAG_CHIP_P5) 2998 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 2999 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3000 skb = netdev_alloc_skb(bp->dev, pkt_size); 3001 if (!skb) 3002 return -ENOMEM; 3003 data = skb_put(skb, pkt_size); 3004 eth_broadcast_addr(data); 3005 i += ETH_ALEN; 3006 ether_addr_copy(&data[i], bp->dev->dev_addr); 3007 i += ETH_ALEN; 3008 for ( ; i < pkt_size; i++) 3009 data[i] = (u8)(i & 0xff); 3010 3011 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3012 PCI_DMA_TODEVICE); 3013 if (dma_mapping_error(&bp->pdev->dev, map)) { 3014 dev_kfree_skb(skb); 3015 return -EIO; 3016 } 3017 bnxt_xmit_bd(bp, txr, map, pkt_size); 3018 3019 /* Sync BD data before updating doorbell */ 3020 wmb(); 3021 3022 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3023 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3024 3025 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 3026 dev_kfree_skb(skb); 3027 return rc; 3028 } 3029 3030 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3031 { 3032 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 3033 struct hwrm_selftest_exec_input req = {0}; 3034 int rc; 3035 3036 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 3037 mutex_lock(&bp->hwrm_cmd_lock); 3038 resp->test_success = 0; 3039 req.flags = test_mask; 3040 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 3041 *test_results = resp->test_success; 3042 mutex_unlock(&bp->hwrm_cmd_lock); 3043 return rc; 3044 } 3045 3046 #define BNXT_DRV_TESTS 4 3047 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3048 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3049 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3050 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3051 3052 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3053 u64 *buf) 3054 { 3055 struct bnxt *bp = netdev_priv(dev); 3056 bool do_ext_lpbk = false; 3057 bool offline = false; 3058 u8 test_results = 0; 3059 u8 test_mask = 0; 3060 int rc = 0, i; 3061 3062 if (!bp->num_tests || !BNXT_SINGLE_PF(bp)) 3063 return; 3064 memset(buf, 0, sizeof(u64) * bp->num_tests); 3065 if (!netif_running(dev)) { 3066 etest->flags |= ETH_TEST_FL_FAILED; 3067 return; 3068 } 3069 3070 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3071 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 3072 do_ext_lpbk = true; 3073 3074 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3075 if (bp->pf.active_vfs) { 3076 etest->flags |= ETH_TEST_FL_FAILED; 3077 netdev_warn(dev, "Offline tests cannot be run with active VFs\n"); 3078 return; 3079 } 3080 offline = true; 3081 } 3082 3083 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3084 u8 bit_val = 1 << i; 3085 3086 if (!(bp->test_info->offline_mask & bit_val)) 3087 test_mask |= bit_val; 3088 else if (offline) 3089 test_mask |= bit_val; 3090 } 3091 if (!offline) { 3092 bnxt_run_fw_tests(bp, test_mask, &test_results); 3093 } else { 3094 rc = bnxt_close_nic(bp, false, false); 3095 if (rc) 3096 return; 3097 bnxt_run_fw_tests(bp, test_mask, &test_results); 3098 3099 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3100 bnxt_hwrm_mac_loopback(bp, true); 3101 msleep(250); 3102 rc = bnxt_half_open_nic(bp); 3103 if (rc) { 3104 bnxt_hwrm_mac_loopback(bp, false); 3105 etest->flags |= ETH_TEST_FL_FAILED; 3106 return; 3107 } 3108 if (bnxt_run_loopback(bp)) 3109 etest->flags |= ETH_TEST_FL_FAILED; 3110 else 3111 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3112 3113 bnxt_hwrm_mac_loopback(bp, false); 3114 bnxt_hwrm_phy_loopback(bp, true, false); 3115 msleep(1000); 3116 if (bnxt_run_loopback(bp)) { 3117 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3118 etest->flags |= ETH_TEST_FL_FAILED; 3119 } 3120 if (do_ext_lpbk) { 3121 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3122 bnxt_hwrm_phy_loopback(bp, true, true); 3123 msleep(1000); 3124 if (bnxt_run_loopback(bp)) { 3125 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3126 etest->flags |= ETH_TEST_FL_FAILED; 3127 } 3128 } 3129 bnxt_hwrm_phy_loopback(bp, false, false); 3130 bnxt_half_close_nic(bp); 3131 rc = bnxt_open_nic(bp, false, true); 3132 } 3133 if (rc || bnxt_test_irq(bp)) { 3134 buf[BNXT_IRQ_TEST_IDX] = 1; 3135 etest->flags |= ETH_TEST_FL_FAILED; 3136 } 3137 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3138 u8 bit_val = 1 << i; 3139 3140 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3141 buf[i] = 1; 3142 etest->flags |= ETH_TEST_FL_FAILED; 3143 } 3144 } 3145 } 3146 3147 static int bnxt_reset(struct net_device *dev, u32 *flags) 3148 { 3149 struct bnxt *bp = netdev_priv(dev); 3150 bool reload = false; 3151 u32 req = *flags; 3152 3153 if (!req) 3154 return -EINVAL; 3155 3156 if (!BNXT_PF(bp)) { 3157 netdev_err(dev, "Reset is not supported from a VF\n"); 3158 return -EOPNOTSUPP; 3159 } 3160 3161 if (pci_vfs_assigned(bp->pdev) && 3162 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3163 netdev_err(dev, 3164 "Reset not allowed when VFs are assigned to VMs\n"); 3165 return -EBUSY; 3166 } 3167 3168 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3169 /* This feature is not supported in older firmware versions */ 3170 if (bp->hwrm_spec_code >= 0x10803) { 3171 if (!bnxt_firmware_reset_chip(dev)) { 3172 netdev_info(dev, "Firmware reset request successful.\n"); 3173 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3174 reload = true; 3175 *flags &= ~BNXT_FW_RESET_CHIP; 3176 } 3177 } else if (req == BNXT_FW_RESET_CHIP) { 3178 return -EOPNOTSUPP; /* only request, fail hard */ 3179 } 3180 } 3181 3182 if (req & BNXT_FW_RESET_AP) { 3183 /* This feature is not supported in older firmware versions */ 3184 if (bp->hwrm_spec_code >= 0x10803) { 3185 if (!bnxt_firmware_reset_ap(dev)) { 3186 netdev_info(dev, "Reset application processor successful.\n"); 3187 reload = true; 3188 *flags &= ~BNXT_FW_RESET_AP; 3189 } 3190 } else if (req == BNXT_FW_RESET_AP) { 3191 return -EOPNOTSUPP; /* only request, fail hard */ 3192 } 3193 } 3194 3195 if (reload) 3196 netdev_info(dev, "Reload driver to complete reset\n"); 3197 3198 return 0; 3199 } 3200 3201 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3202 struct bnxt_hwrm_dbg_dma_info *info) 3203 { 3204 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3205 struct hwrm_dbg_cmn_input *cmn_req = msg; 3206 __le16 *seq_ptr = msg + info->seq_off; 3207 u16 seq = 0, len, segs_off; 3208 void *resp = cmn_resp; 3209 dma_addr_t dma_handle; 3210 int rc, off = 0; 3211 void *dma_buf; 3212 3213 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3214 GFP_KERNEL); 3215 if (!dma_buf) 3216 return -ENOMEM; 3217 3218 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3219 total_segments); 3220 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3221 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3222 mutex_lock(&bp->hwrm_cmd_lock); 3223 while (1) { 3224 *seq_ptr = cpu_to_le16(seq); 3225 rc = _hwrm_send_message(bp, msg, msg_len, 3226 HWRM_COREDUMP_TIMEOUT); 3227 if (rc) 3228 break; 3229 3230 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3231 if (!seq && 3232 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3233 info->segs = le16_to_cpu(*((__le16 *)(resp + 3234 segs_off))); 3235 if (!info->segs) { 3236 rc = -EIO; 3237 break; 3238 } 3239 3240 info->dest_buf_size = info->segs * 3241 sizeof(struct coredump_segment_record); 3242 info->dest_buf = kmalloc(info->dest_buf_size, 3243 GFP_KERNEL); 3244 if (!info->dest_buf) { 3245 rc = -ENOMEM; 3246 break; 3247 } 3248 } 3249 3250 if (info->dest_buf) { 3251 if ((info->seg_start + off + len) <= 3252 BNXT_COREDUMP_BUF_LEN(info->buf_len)) { 3253 memcpy(info->dest_buf + off, dma_buf, len); 3254 } else { 3255 rc = -ENOBUFS; 3256 break; 3257 } 3258 } 3259 3260 if (cmn_req->req_type == 3261 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3262 info->dest_buf_size += len; 3263 3264 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3265 break; 3266 3267 seq++; 3268 off += len; 3269 } 3270 mutex_unlock(&bp->hwrm_cmd_lock); 3271 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3272 return rc; 3273 } 3274 3275 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3276 struct bnxt_coredump *coredump) 3277 { 3278 struct hwrm_dbg_coredump_list_input req = {0}; 3279 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3280 int rc; 3281 3282 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3283 3284 info.dma_len = COREDUMP_LIST_BUF_LEN; 3285 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3286 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3287 data_len); 3288 3289 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3290 if (!rc) { 3291 coredump->data = info.dest_buf; 3292 coredump->data_size = info.dest_buf_size; 3293 coredump->total_segs = info.segs; 3294 } 3295 return rc; 3296 } 3297 3298 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3299 u16 segment_id) 3300 { 3301 struct hwrm_dbg_coredump_initiate_input req = {0}; 3302 3303 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3304 req.component_id = cpu_to_le16(component_id); 3305 req.segment_id = cpu_to_le16(segment_id); 3306 3307 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3308 } 3309 3310 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3311 u16 segment_id, u32 *seg_len, 3312 void *buf, u32 buf_len, u32 offset) 3313 { 3314 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3315 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3316 int rc; 3317 3318 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3319 req.component_id = cpu_to_le16(component_id); 3320 req.segment_id = cpu_to_le16(segment_id); 3321 3322 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3323 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3324 seq_no); 3325 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3326 data_len); 3327 if (buf) { 3328 info.dest_buf = buf + offset; 3329 info.buf_len = buf_len; 3330 info.seg_start = offset; 3331 } 3332 3333 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3334 if (!rc) 3335 *seg_len = info.dest_buf_size; 3336 3337 return rc; 3338 } 3339 3340 static void 3341 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3342 struct bnxt_coredump_segment_hdr *seg_hdr, 3343 struct coredump_segment_record *seg_rec, u32 seg_len, 3344 int status, u32 duration, u32 instance) 3345 { 3346 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3347 memcpy(seg_hdr->signature, "sEgM", 4); 3348 if (seg_rec) { 3349 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3350 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3351 seg_hdr->low_version = seg_rec->version_low; 3352 seg_hdr->high_version = seg_rec->version_hi; 3353 } else { 3354 /* For hwrm_ver_get response Component id = 2 3355 * and Segment id = 0 3356 */ 3357 seg_hdr->component_id = cpu_to_le32(2); 3358 seg_hdr->segment_id = 0; 3359 } 3360 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3361 seg_hdr->length = cpu_to_le32(seg_len); 3362 seg_hdr->status = cpu_to_le32(status); 3363 seg_hdr->duration = cpu_to_le32(duration); 3364 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3365 seg_hdr->instance = cpu_to_le32(instance); 3366 } 3367 3368 static void 3369 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3370 time64_t start, s16 start_utc, u16 total_segs, 3371 int status) 3372 { 3373 time64_t end = ktime_get_real_seconds(); 3374 u32 os_ver_major = 0, os_ver_minor = 0; 3375 struct tm tm; 3376 3377 time64_to_tm(start, 0, &tm); 3378 memset(record, 0, sizeof(*record)); 3379 memcpy(record->signature, "cOrE", 4); 3380 record->flags = 0; 3381 record->low_version = 0; 3382 record->high_version = 1; 3383 record->asic_state = 0; 3384 strlcpy(record->system_name, utsname()->nodename, 3385 sizeof(record->system_name)); 3386 record->year = cpu_to_le16(tm.tm_year + 1900); 3387 record->month = cpu_to_le16(tm.tm_mon + 1); 3388 record->day = cpu_to_le16(tm.tm_mday); 3389 record->hour = cpu_to_le16(tm.tm_hour); 3390 record->minute = cpu_to_le16(tm.tm_min); 3391 record->second = cpu_to_le16(tm.tm_sec); 3392 record->utc_bias = cpu_to_le16(start_utc); 3393 strcpy(record->commandline, "ethtool -w"); 3394 record->total_segments = cpu_to_le32(total_segs); 3395 3396 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3397 record->os_ver_major = cpu_to_le32(os_ver_major); 3398 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3399 3400 strlcpy(record->os_name, utsname()->sysname, 32); 3401 time64_to_tm(end, 0, &tm); 3402 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3403 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3404 record->end_day = cpu_to_le16(tm.tm_mday); 3405 record->end_hour = cpu_to_le16(tm.tm_hour); 3406 record->end_minute = cpu_to_le16(tm.tm_min); 3407 record->end_second = cpu_to_le16(tm.tm_sec); 3408 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3409 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3410 bp->ver_resp.chip_rev << 8 | 3411 bp->ver_resp.chip_metal); 3412 record->asic_id2 = 0; 3413 record->coredump_status = cpu_to_le32(status); 3414 record->ioctl_low_version = 0; 3415 record->ioctl_high_version = 0; 3416 } 3417 3418 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3419 { 3420 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3421 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0; 3422 struct coredump_segment_record *seg_record = NULL; 3423 struct bnxt_coredump_segment_hdr seg_hdr; 3424 struct bnxt_coredump coredump = {NULL}; 3425 time64_t start_time; 3426 u16 start_utc; 3427 int rc = 0, i; 3428 3429 if (buf) 3430 buf_len = *dump_len; 3431 3432 start_time = ktime_get_real_seconds(); 3433 start_utc = sys_tz.tz_minuteswest * 60; 3434 seg_hdr_len = sizeof(seg_hdr); 3435 3436 /* First segment should be hwrm_ver_get response */ 3437 *dump_len = seg_hdr_len + ver_get_resp_len; 3438 if (buf) { 3439 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3440 0, 0, 0); 3441 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3442 offset += seg_hdr_len; 3443 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3444 offset += ver_get_resp_len; 3445 } 3446 3447 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3448 if (rc) { 3449 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3450 goto err; 3451 } 3452 3453 *dump_len += seg_hdr_len * coredump.total_segs; 3454 3455 seg_record = (struct coredump_segment_record *)coredump.data; 3456 seg_record_len = sizeof(*seg_record); 3457 3458 for (i = 0; i < coredump.total_segs; i++) { 3459 u16 comp_id = le16_to_cpu(seg_record->component_id); 3460 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3461 u32 duration = 0, seg_len = 0; 3462 unsigned long start, end; 3463 3464 if (buf && ((offset + seg_hdr_len) > 3465 BNXT_COREDUMP_BUF_LEN(buf_len))) { 3466 rc = -ENOBUFS; 3467 goto err; 3468 } 3469 3470 start = jiffies; 3471 3472 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3473 if (rc) { 3474 netdev_err(bp->dev, 3475 "Failed to initiate coredump for seg = %d\n", 3476 seg_record->segment_id); 3477 goto next_seg; 3478 } 3479 3480 /* Write segment data into the buffer */ 3481 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3482 &seg_len, buf, buf_len, 3483 offset + seg_hdr_len); 3484 if (rc && rc == -ENOBUFS) 3485 goto err; 3486 else if (rc) 3487 netdev_err(bp->dev, 3488 "Failed to retrieve coredump for seg = %d\n", 3489 seg_record->segment_id); 3490 3491 next_seg: 3492 end = jiffies; 3493 duration = jiffies_to_msecs(end - start); 3494 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3495 rc, duration, 0); 3496 3497 if (buf) { 3498 /* Write segment header into the buffer */ 3499 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3500 offset += seg_hdr_len + seg_len; 3501 } 3502 3503 *dump_len += seg_len; 3504 seg_record = 3505 (struct coredump_segment_record *)((u8 *)seg_record + 3506 seg_record_len); 3507 } 3508 3509 err: 3510 if (buf) 3511 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3512 start_utc, coredump.total_segs + 1, 3513 rc); 3514 kfree(coredump.data); 3515 *dump_len += sizeof(struct bnxt_coredump_record); 3516 if (rc == -ENOBUFS) 3517 netdev_err(bp->dev, "Firmware returned large coredump buffer\n"); 3518 return rc; 3519 } 3520 3521 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3522 { 3523 struct bnxt *bp = netdev_priv(dev); 3524 3525 if (dump->flag > BNXT_DUMP_CRASH) { 3526 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3527 return -EINVAL; 3528 } 3529 3530 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3531 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3532 return -EOPNOTSUPP; 3533 } 3534 3535 bp->dump_flag = dump->flag; 3536 return 0; 3537 } 3538 3539 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3540 { 3541 struct bnxt *bp = netdev_priv(dev); 3542 3543 if (bp->hwrm_spec_code < 0x10801) 3544 return -EOPNOTSUPP; 3545 3546 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3547 bp->ver_resp.hwrm_fw_min_8b << 16 | 3548 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3549 bp->ver_resp.hwrm_fw_rsvd_8b; 3550 3551 dump->flag = bp->dump_flag; 3552 if (bp->dump_flag == BNXT_DUMP_CRASH) 3553 dump->len = BNXT_CRASH_DUMP_LEN; 3554 else 3555 bnxt_get_coredump(bp, NULL, &dump->len); 3556 return 0; 3557 } 3558 3559 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3560 void *buf) 3561 { 3562 struct bnxt *bp = netdev_priv(dev); 3563 3564 if (bp->hwrm_spec_code < 0x10801) 3565 return -EOPNOTSUPP; 3566 3567 memset(buf, 0, dump->len); 3568 3569 dump->flag = bp->dump_flag; 3570 if (dump->flag == BNXT_DUMP_CRASH) { 3571 #ifdef CONFIG_TEE_BNXT_FW 3572 return tee_bnxt_copy_coredump(buf, 0, dump->len); 3573 #endif 3574 } else { 3575 return bnxt_get_coredump(bp, buf, &dump->len); 3576 } 3577 3578 return 0; 3579 } 3580 3581 void bnxt_ethtool_init(struct bnxt *bp) 3582 { 3583 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3584 struct hwrm_selftest_qlist_input req = {0}; 3585 struct bnxt_test_info *test_info; 3586 struct net_device *dev = bp->dev; 3587 int i, rc; 3588 3589 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3590 bnxt_get_pkgver(dev); 3591 3592 bp->num_tests = 0; 3593 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp)) 3594 return; 3595 3596 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3597 mutex_lock(&bp->hwrm_cmd_lock); 3598 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3599 if (rc) 3600 goto ethtool_init_exit; 3601 3602 test_info = bp->test_info; 3603 if (!test_info) 3604 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3605 if (!test_info) 3606 goto ethtool_init_exit; 3607 3608 bp->test_info = test_info; 3609 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3610 if (bp->num_tests > BNXT_MAX_TEST) 3611 bp->num_tests = BNXT_MAX_TEST; 3612 3613 test_info->offline_mask = resp->offline_tests; 3614 test_info->timeout = le16_to_cpu(resp->test_timeout); 3615 if (!test_info->timeout) 3616 test_info->timeout = HWRM_CMD_TIMEOUT; 3617 for (i = 0; i < bp->num_tests; i++) { 3618 char *str = test_info->string[i]; 3619 char *fw_str = resp->test0_name + i * 32; 3620 3621 if (i == BNXT_MACLPBK_TEST_IDX) { 3622 strcpy(str, "Mac loopback test (offline)"); 3623 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3624 strcpy(str, "Phy loopback test (offline)"); 3625 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3626 strcpy(str, "Ext loopback test (offline)"); 3627 } else if (i == BNXT_IRQ_TEST_IDX) { 3628 strcpy(str, "Interrupt_test (offline)"); 3629 } else { 3630 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3631 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3632 if (test_info->offline_mask & (1 << i)) 3633 strncat(str, " (offline)", 3634 ETH_GSTRING_LEN - strlen(str)); 3635 else 3636 strncat(str, " (online)", 3637 ETH_GSTRING_LEN - strlen(str)); 3638 } 3639 } 3640 3641 ethtool_init_exit: 3642 mutex_unlock(&bp->hwrm_cmd_lock); 3643 } 3644 3645 void bnxt_ethtool_free(struct bnxt *bp) 3646 { 3647 kfree(bp->test_info); 3648 bp->test_info = NULL; 3649 } 3650 3651 const struct ethtool_ops bnxt_ethtool_ops = { 3652 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3653 ETHTOOL_COALESCE_MAX_FRAMES | 3654 ETHTOOL_COALESCE_USECS_IRQ | 3655 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3656 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3657 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3658 .get_link_ksettings = bnxt_get_link_ksettings, 3659 .set_link_ksettings = bnxt_set_link_ksettings, 3660 .get_pauseparam = bnxt_get_pauseparam, 3661 .set_pauseparam = bnxt_set_pauseparam, 3662 .get_drvinfo = bnxt_get_drvinfo, 3663 .get_regs_len = bnxt_get_regs_len, 3664 .get_regs = bnxt_get_regs, 3665 .get_wol = bnxt_get_wol, 3666 .set_wol = bnxt_set_wol, 3667 .get_coalesce = bnxt_get_coalesce, 3668 .set_coalesce = bnxt_set_coalesce, 3669 .get_msglevel = bnxt_get_msglevel, 3670 .set_msglevel = bnxt_set_msglevel, 3671 .get_sset_count = bnxt_get_sset_count, 3672 .get_strings = bnxt_get_strings, 3673 .get_ethtool_stats = bnxt_get_ethtool_stats, 3674 .set_ringparam = bnxt_set_ringparam, 3675 .get_ringparam = bnxt_get_ringparam, 3676 .get_channels = bnxt_get_channels, 3677 .set_channels = bnxt_set_channels, 3678 .get_rxnfc = bnxt_get_rxnfc, 3679 .set_rxnfc = bnxt_set_rxnfc, 3680 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3681 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3682 .get_rxfh = bnxt_get_rxfh, 3683 .set_rxfh = bnxt_set_rxfh, 3684 .flash_device = bnxt_flash_device, 3685 .get_eeprom_len = bnxt_get_eeprom_len, 3686 .get_eeprom = bnxt_get_eeprom, 3687 .set_eeprom = bnxt_set_eeprom, 3688 .get_link = bnxt_get_link, 3689 .get_eee = bnxt_get_eee, 3690 .set_eee = bnxt_set_eee, 3691 .get_module_info = bnxt_get_module_info, 3692 .get_module_eeprom = bnxt_get_module_eeprom, 3693 .nway_reset = bnxt_nway_reset, 3694 .set_phys_id = bnxt_set_phys_id, 3695 .self_test = bnxt_self_test, 3696 .reset = bnxt_reset, 3697 .set_dump = bnxt_set_dump, 3698 .get_dump_flag = bnxt_get_dump_flag, 3699 .get_dump_data = bnxt_get_dump_data, 3700 }; 3701