1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/etherdevice.h> 17 #include <linux/crc32.h> 18 #include <linux/firmware.h> 19 #include <linux/utsname.h> 20 #include <linux/time.h> 21 #include "bnxt_hsi.h" 22 #include "bnxt.h" 23 #include "bnxt_xdp.h" 24 #include "bnxt_ethtool.h" 25 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 26 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 27 #include "bnxt_coredump.h" 28 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 29 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 30 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 32 static u32 bnxt_get_msglevel(struct net_device *dev) 33 { 34 struct bnxt *bp = netdev_priv(dev); 35 36 return bp->msg_enable; 37 } 38 39 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 40 { 41 struct bnxt *bp = netdev_priv(dev); 42 43 bp->msg_enable = value; 44 } 45 46 static int bnxt_get_coalesce(struct net_device *dev, 47 struct ethtool_coalesce *coal) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 struct bnxt_coal *hw_coal; 51 u16 mult; 52 53 memset(coal, 0, sizeof(*coal)); 54 55 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 56 57 hw_coal = &bp->rx_coal; 58 mult = hw_coal->bufs_per_record; 59 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 60 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 61 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 62 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 63 64 hw_coal = &bp->tx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 71 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 72 73 return 0; 74 } 75 76 static int bnxt_set_coalesce(struct net_device *dev, 77 struct ethtool_coalesce *coal) 78 { 79 struct bnxt *bp = netdev_priv(dev); 80 bool update_stats = false; 81 struct bnxt_coal *hw_coal; 82 int rc = 0; 83 u16 mult; 84 85 if (coal->use_adaptive_rx_coalesce) { 86 bp->flags |= BNXT_FLAG_DIM; 87 } else { 88 if (bp->flags & BNXT_FLAG_DIM) { 89 bp->flags &= ~(BNXT_FLAG_DIM); 90 goto reset_coalesce; 91 } 92 } 93 94 hw_coal = &bp->rx_coal; 95 mult = hw_coal->bufs_per_record; 96 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 97 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 98 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 99 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 100 101 hw_coal = &bp->tx_coal; 102 mult = hw_coal->bufs_per_record; 103 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 104 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 105 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 106 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 107 108 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 109 u32 stats_ticks = coal->stats_block_coalesce_usecs; 110 111 /* Allow 0, which means disable. */ 112 if (stats_ticks) 113 stats_ticks = clamp_t(u32, stats_ticks, 114 BNXT_MIN_STATS_COAL_TICKS, 115 BNXT_MAX_STATS_COAL_TICKS); 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 117 bp->stats_coal_ticks = stats_ticks; 118 if (bp->stats_coal_ticks) 119 bp->current_interval = 120 bp->stats_coal_ticks * HZ / 1000000; 121 else 122 bp->current_interval = BNXT_TIMER_INTERVAL; 123 update_stats = true; 124 } 125 126 reset_coalesce: 127 if (netif_running(dev)) { 128 if (update_stats) { 129 rc = bnxt_close_nic(bp, true, false); 130 if (!rc) 131 rc = bnxt_open_nic(bp, true, false); 132 } else { 133 rc = bnxt_hwrm_set_coal(bp); 134 } 135 } 136 137 return rc; 138 } 139 140 static const char * const bnxt_ring_rx_stats_str[] = { 141 "rx_ucast_packets", 142 "rx_mcast_packets", 143 "rx_bcast_packets", 144 "rx_discards", 145 "rx_drops", 146 "rx_ucast_bytes", 147 "rx_mcast_bytes", 148 "rx_bcast_bytes", 149 }; 150 151 static const char * const bnxt_ring_tx_stats_str[] = { 152 "tx_ucast_packets", 153 "tx_mcast_packets", 154 "tx_bcast_packets", 155 "tx_discards", 156 "tx_drops", 157 "tx_ucast_bytes", 158 "tx_mcast_bytes", 159 "tx_bcast_bytes", 160 }; 161 162 static const char * const bnxt_ring_tpa_stats_str[] = { 163 "tpa_packets", 164 "tpa_bytes", 165 "tpa_events", 166 "tpa_aborts", 167 }; 168 169 static const char * const bnxt_ring_tpa2_stats_str[] = { 170 "rx_tpa_eligible_pkt", 171 "rx_tpa_eligible_bytes", 172 "rx_tpa_pkt", 173 "rx_tpa_bytes", 174 "rx_tpa_errors", 175 }; 176 177 static const char * const bnxt_rx_sw_stats_str[] = { 178 "rx_l4_csum_errors", 179 "rx_buf_errors", 180 }; 181 182 static const char * const bnxt_cmn_sw_stats_str[] = { 183 "missed_irqs", 184 }; 185 186 #define BNXT_RX_STATS_ENTRY(counter) \ 187 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 188 189 #define BNXT_TX_STATS_ENTRY(counter) \ 190 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 191 192 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 193 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 194 195 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 196 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 197 198 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 199 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 200 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 201 202 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 203 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 204 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 205 206 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 207 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 208 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 209 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 210 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 211 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 212 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 213 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 214 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 215 216 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 217 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 218 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 219 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 220 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 221 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 222 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 223 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 224 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 225 226 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 227 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 228 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 229 230 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 231 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 232 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 233 234 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 235 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 236 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 237 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 238 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 239 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 240 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 241 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 242 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 243 244 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 245 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 246 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 247 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 248 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 249 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 250 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 251 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 252 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 253 254 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 255 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 256 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 257 258 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 259 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 260 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 261 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 267 268 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 269 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 270 __stringify(counter##_pri##n) } 271 272 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 273 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 274 __stringify(counter##_pri##n) } 275 276 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 277 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 278 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 279 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 280 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 281 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 282 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 283 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 284 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 285 286 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 287 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 288 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 289 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 290 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 291 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 292 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 293 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 294 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 295 296 #define BNXT_PCIE_STATS_ENTRY(counter) \ 297 { BNXT_PCIE_STATS_OFFSET(counter), __stringify(counter) } 298 299 enum { 300 RX_TOTAL_DISCARDS, 301 TX_TOTAL_DISCARDS, 302 }; 303 304 static struct { 305 u64 counter; 306 char string[ETH_GSTRING_LEN]; 307 } bnxt_sw_func_stats[] = { 308 {0, "rx_total_discard_pkts"}, 309 {0, "tx_total_discard_pkts"}, 310 }; 311 312 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 313 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 314 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 315 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 316 317 static const struct { 318 long offset; 319 char string[ETH_GSTRING_LEN]; 320 } bnxt_port_stats_arr[] = { 321 BNXT_RX_STATS_ENTRY(rx_64b_frames), 322 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 323 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 324 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 325 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 326 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 327 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 328 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 329 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 330 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 331 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 332 BNXT_RX_STATS_ENTRY(rx_total_frames), 333 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 334 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 335 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 336 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 337 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 338 BNXT_RX_STATS_ENTRY(rx_pause_frames), 339 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 340 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 341 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 342 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 343 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 344 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 345 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 346 BNXT_RX_STATS_ENTRY(rx_good_frames), 347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 354 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 355 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 357 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 358 BNXT_RX_STATS_ENTRY(rx_bytes), 359 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 360 BNXT_RX_STATS_ENTRY(rx_runt_frames), 361 BNXT_RX_STATS_ENTRY(rx_stat_discard), 362 BNXT_RX_STATS_ENTRY(rx_stat_err), 363 364 BNXT_TX_STATS_ENTRY(tx_64b_frames), 365 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 366 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 367 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 368 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 369 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 370 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 371 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 372 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 373 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 374 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 375 BNXT_TX_STATS_ENTRY(tx_good_frames), 376 BNXT_TX_STATS_ENTRY(tx_total_frames), 377 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 378 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 379 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 380 BNXT_TX_STATS_ENTRY(tx_pause_frames), 381 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 382 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 383 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 384 BNXT_TX_STATS_ENTRY(tx_err), 385 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 393 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 395 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 396 BNXT_TX_STATS_ENTRY(tx_total_collisions), 397 BNXT_TX_STATS_ENTRY(tx_bytes), 398 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 399 BNXT_TX_STATS_ENTRY(tx_stat_discard), 400 BNXT_TX_STATS_ENTRY(tx_stat_error), 401 }; 402 403 static const struct { 404 long offset; 405 char string[ETH_GSTRING_LEN]; 406 } bnxt_port_stats_ext_arr[] = { 407 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 408 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 409 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 410 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 411 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 412 BNXT_RX_STATS_EXT_COS_ENTRIES, 413 BNXT_RX_STATS_EXT_PFC_ENTRIES, 414 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 415 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 416 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 417 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 418 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 419 }; 420 421 static const struct { 422 long offset; 423 char string[ETH_GSTRING_LEN]; 424 } bnxt_tx_port_stats_ext_arr[] = { 425 BNXT_TX_STATS_EXT_COS_ENTRIES, 426 BNXT_TX_STATS_EXT_PFC_ENTRIES, 427 }; 428 429 static const struct { 430 long base_off; 431 char string[ETH_GSTRING_LEN]; 432 } bnxt_rx_bytes_pri_arr[] = { 433 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 434 }; 435 436 static const struct { 437 long base_off; 438 char string[ETH_GSTRING_LEN]; 439 } bnxt_rx_pkts_pri_arr[] = { 440 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 441 }; 442 443 static const struct { 444 long base_off; 445 char string[ETH_GSTRING_LEN]; 446 } bnxt_tx_bytes_pri_arr[] = { 447 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 448 }; 449 450 static const struct { 451 long base_off; 452 char string[ETH_GSTRING_LEN]; 453 } bnxt_tx_pkts_pri_arr[] = { 454 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 455 }; 456 457 static const struct { 458 long offset; 459 char string[ETH_GSTRING_LEN]; 460 } bnxt_pcie_stats_arr[] = { 461 BNXT_PCIE_STATS_ENTRY(pcie_pl_signal_integrity), 462 BNXT_PCIE_STATS_ENTRY(pcie_dl_signal_integrity), 463 BNXT_PCIE_STATS_ENTRY(pcie_tl_signal_integrity), 464 BNXT_PCIE_STATS_ENTRY(pcie_link_integrity), 465 BNXT_PCIE_STATS_ENTRY(pcie_tx_traffic_rate), 466 BNXT_PCIE_STATS_ENTRY(pcie_rx_traffic_rate), 467 BNXT_PCIE_STATS_ENTRY(pcie_tx_dllp_statistics), 468 BNXT_PCIE_STATS_ENTRY(pcie_rx_dllp_statistics), 469 BNXT_PCIE_STATS_ENTRY(pcie_equalization_time), 470 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[0]), 471 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[2]), 472 BNXT_PCIE_STATS_ENTRY(pcie_recovery_histogram), 473 }; 474 475 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 476 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 477 #define BNXT_NUM_STATS_PRI \ 478 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 479 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 480 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 481 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 482 #define BNXT_NUM_PCIE_STATS ARRAY_SIZE(bnxt_pcie_stats_arr) 483 484 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 485 { 486 if (BNXT_SUPPORTS_TPA(bp)) { 487 if (bp->max_tpa_v2) 488 return ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 489 return ARRAY_SIZE(bnxt_ring_tpa_stats_str); 490 } 491 return 0; 492 } 493 494 static int bnxt_get_num_ring_stats(struct bnxt *bp) 495 { 496 int rx, tx, cmn; 497 bool sh = false; 498 499 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 500 sh = true; 501 502 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 503 bnxt_get_num_tpa_ring_stats(bp); 504 tx = NUM_RING_TX_HW_STATS; 505 cmn = NUM_RING_CMN_SW_STATS; 506 if (sh) 507 return (rx + tx + cmn) * bp->cp_nr_rings; 508 else 509 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 510 cmn * bp->cp_nr_rings; 511 } 512 513 static int bnxt_get_num_stats(struct bnxt *bp) 514 { 515 int num_stats = bnxt_get_num_ring_stats(bp); 516 517 num_stats += BNXT_NUM_SW_FUNC_STATS; 518 519 if (bp->flags & BNXT_FLAG_PORT_STATS) 520 num_stats += BNXT_NUM_PORT_STATS; 521 522 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 523 num_stats += bp->fw_rx_stats_ext_size + 524 bp->fw_tx_stats_ext_size; 525 if (bp->pri2cos_valid) 526 num_stats += BNXT_NUM_STATS_PRI; 527 } 528 529 if (bp->flags & BNXT_FLAG_PCIE_STATS) 530 num_stats += BNXT_NUM_PCIE_STATS; 531 532 return num_stats; 533 } 534 535 static int bnxt_get_sset_count(struct net_device *dev, int sset) 536 { 537 struct bnxt *bp = netdev_priv(dev); 538 539 switch (sset) { 540 case ETH_SS_STATS: 541 return bnxt_get_num_stats(bp); 542 case ETH_SS_TEST: 543 if (!bp->num_tests) 544 return -EOPNOTSUPP; 545 return bp->num_tests; 546 default: 547 return -EOPNOTSUPP; 548 } 549 } 550 551 static bool is_rx_ring(struct bnxt *bp, int ring_num) 552 { 553 return ring_num < bp->rx_nr_rings; 554 } 555 556 static bool is_tx_ring(struct bnxt *bp, int ring_num) 557 { 558 int tx_base = 0; 559 560 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 561 tx_base = bp->rx_nr_rings; 562 563 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 564 return true; 565 return false; 566 } 567 568 static void bnxt_get_ethtool_stats(struct net_device *dev, 569 struct ethtool_stats *stats, u64 *buf) 570 { 571 u32 i, j = 0; 572 struct bnxt *bp = netdev_priv(dev); 573 u32 tpa_stats; 574 575 if (!bp->bnapi) { 576 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 577 goto skip_ring_stats; 578 } 579 580 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 581 bnxt_sw_func_stats[i].counter = 0; 582 583 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 584 for (i = 0; i < bp->cp_nr_rings; i++) { 585 struct bnxt_napi *bnapi = bp->bnapi[i]; 586 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 587 __le64 *hw_stats = (__le64 *)cpr->hw_stats; 588 u64 *sw; 589 int k; 590 591 if (is_rx_ring(bp, i)) { 592 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 593 buf[j] = le64_to_cpu(hw_stats[k]); 594 } 595 if (is_tx_ring(bp, i)) { 596 k = NUM_RING_RX_HW_STATS; 597 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 598 j++, k++) 599 buf[j] = le64_to_cpu(hw_stats[k]); 600 } 601 if (!tpa_stats || !is_rx_ring(bp, i)) 602 goto skip_tpa_ring_stats; 603 604 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 605 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 606 tpa_stats; j++, k++) 607 buf[j] = le64_to_cpu(hw_stats[k]); 608 609 skip_tpa_ring_stats: 610 sw = (u64 *)&cpr->sw_stats.rx; 611 if (is_rx_ring(bp, i)) { 612 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 613 buf[j] = sw[k]; 614 } 615 616 sw = (u64 *)&cpr->sw_stats.cmn; 617 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 618 buf[j] = sw[k]; 619 620 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 621 le64_to_cpu(cpr->hw_stats->rx_discard_pkts); 622 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 623 le64_to_cpu(cpr->hw_stats->tx_discard_pkts); 624 } 625 626 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 627 buf[j] = bnxt_sw_func_stats[i].counter; 628 629 skip_ring_stats: 630 if (bp->flags & BNXT_FLAG_PORT_STATS) { 631 __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats; 632 633 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) { 634 buf[j] = le64_to_cpu(*(port_stats + 635 bnxt_port_stats_arr[i].offset)); 636 } 637 } 638 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 639 __le64 *rx_port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext; 640 __le64 *tx_port_stats_ext = (__le64 *)bp->hw_tx_port_stats_ext; 641 642 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 643 buf[j] = le64_to_cpu(*(rx_port_stats_ext + 644 bnxt_port_stats_ext_arr[i].offset)); 645 } 646 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 647 buf[j] = le64_to_cpu(*(tx_port_stats_ext + 648 bnxt_tx_port_stats_ext_arr[i].offset)); 649 } 650 if (bp->pri2cos_valid) { 651 for (i = 0; i < 8; i++, j++) { 652 long n = bnxt_rx_bytes_pri_arr[i].base_off + 653 bp->pri2cos_idx[i]; 654 655 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 656 } 657 for (i = 0; i < 8; i++, j++) { 658 long n = bnxt_rx_pkts_pri_arr[i].base_off + 659 bp->pri2cos_idx[i]; 660 661 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 662 } 663 for (i = 0; i < 8; i++, j++) { 664 long n = bnxt_tx_bytes_pri_arr[i].base_off + 665 bp->pri2cos_idx[i]; 666 667 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 668 } 669 for (i = 0; i < 8; i++, j++) { 670 long n = bnxt_tx_pkts_pri_arr[i].base_off + 671 bp->pri2cos_idx[i]; 672 673 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 674 } 675 } 676 } 677 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 678 __le64 *pcie_stats = (__le64 *)bp->hw_pcie_stats; 679 680 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++, j++) { 681 buf[j] = le64_to_cpu(*(pcie_stats + 682 bnxt_pcie_stats_arr[i].offset)); 683 } 684 } 685 } 686 687 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 688 { 689 struct bnxt *bp = netdev_priv(dev); 690 static const char * const *str; 691 u32 i, j, num_str; 692 693 switch (stringset) { 694 case ETH_SS_STATS: 695 for (i = 0; i < bp->cp_nr_rings; i++) { 696 if (is_rx_ring(bp, i)) { 697 num_str = NUM_RING_RX_HW_STATS; 698 for (j = 0; j < num_str; j++) { 699 sprintf(buf, "[%d]: %s", i, 700 bnxt_ring_rx_stats_str[j]); 701 buf += ETH_GSTRING_LEN; 702 } 703 } 704 if (is_tx_ring(bp, i)) { 705 num_str = NUM_RING_TX_HW_STATS; 706 for (j = 0; j < num_str; j++) { 707 sprintf(buf, "[%d]: %s", i, 708 bnxt_ring_tx_stats_str[j]); 709 buf += ETH_GSTRING_LEN; 710 } 711 } 712 num_str = bnxt_get_num_tpa_ring_stats(bp); 713 if (!num_str || !is_rx_ring(bp, i)) 714 goto skip_tpa_stats; 715 716 if (bp->max_tpa_v2) 717 str = bnxt_ring_tpa2_stats_str; 718 else 719 str = bnxt_ring_tpa_stats_str; 720 721 for (j = 0; j < num_str; j++) { 722 sprintf(buf, "[%d]: %s", i, str[j]); 723 buf += ETH_GSTRING_LEN; 724 } 725 skip_tpa_stats: 726 if (is_rx_ring(bp, i)) { 727 num_str = NUM_RING_RX_SW_STATS; 728 for (j = 0; j < num_str; j++) { 729 sprintf(buf, "[%d]: %s", i, 730 bnxt_rx_sw_stats_str[j]); 731 buf += ETH_GSTRING_LEN; 732 } 733 } 734 num_str = NUM_RING_CMN_SW_STATS; 735 for (j = 0; j < num_str; j++) { 736 sprintf(buf, "[%d]: %s", i, 737 bnxt_cmn_sw_stats_str[j]); 738 buf += ETH_GSTRING_LEN; 739 } 740 } 741 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 742 strcpy(buf, bnxt_sw_func_stats[i].string); 743 buf += ETH_GSTRING_LEN; 744 } 745 746 if (bp->flags & BNXT_FLAG_PORT_STATS) { 747 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 748 strcpy(buf, bnxt_port_stats_arr[i].string); 749 buf += ETH_GSTRING_LEN; 750 } 751 } 752 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 753 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 754 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 755 buf += ETH_GSTRING_LEN; 756 } 757 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 758 strcpy(buf, 759 bnxt_tx_port_stats_ext_arr[i].string); 760 buf += ETH_GSTRING_LEN; 761 } 762 if (bp->pri2cos_valid) { 763 for (i = 0; i < 8; i++) { 764 strcpy(buf, 765 bnxt_rx_bytes_pri_arr[i].string); 766 buf += ETH_GSTRING_LEN; 767 } 768 for (i = 0; i < 8; i++) { 769 strcpy(buf, 770 bnxt_rx_pkts_pri_arr[i].string); 771 buf += ETH_GSTRING_LEN; 772 } 773 for (i = 0; i < 8; i++) { 774 strcpy(buf, 775 bnxt_tx_bytes_pri_arr[i].string); 776 buf += ETH_GSTRING_LEN; 777 } 778 for (i = 0; i < 8; i++) { 779 strcpy(buf, 780 bnxt_tx_pkts_pri_arr[i].string); 781 buf += ETH_GSTRING_LEN; 782 } 783 } 784 } 785 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 786 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++) { 787 strcpy(buf, bnxt_pcie_stats_arr[i].string); 788 buf += ETH_GSTRING_LEN; 789 } 790 } 791 break; 792 case ETH_SS_TEST: 793 if (bp->num_tests) 794 memcpy(buf, bp->test_info->string, 795 bp->num_tests * ETH_GSTRING_LEN); 796 break; 797 default: 798 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 799 stringset); 800 break; 801 } 802 } 803 804 static void bnxt_get_ringparam(struct net_device *dev, 805 struct ethtool_ringparam *ering) 806 { 807 struct bnxt *bp = netdev_priv(dev); 808 809 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 810 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 811 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 812 813 ering->rx_pending = bp->rx_ring_size; 814 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 815 ering->tx_pending = bp->tx_ring_size; 816 } 817 818 static int bnxt_set_ringparam(struct net_device *dev, 819 struct ethtool_ringparam *ering) 820 { 821 struct bnxt *bp = netdev_priv(dev); 822 823 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 824 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 825 (ering->tx_pending <= MAX_SKB_FRAGS)) 826 return -EINVAL; 827 828 if (netif_running(dev)) 829 bnxt_close_nic(bp, false, false); 830 831 bp->rx_ring_size = ering->rx_pending; 832 bp->tx_ring_size = ering->tx_pending; 833 bnxt_set_ring_params(bp); 834 835 if (netif_running(dev)) 836 return bnxt_open_nic(bp, false, false); 837 838 return 0; 839 } 840 841 static void bnxt_get_channels(struct net_device *dev, 842 struct ethtool_channels *channel) 843 { 844 struct bnxt *bp = netdev_priv(dev); 845 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 846 int max_rx_rings, max_tx_rings, tcs; 847 int max_tx_sch_inputs; 848 849 /* Get the most up-to-date max_tx_sch_inputs. */ 850 if (BNXT_NEW_RM(bp)) 851 bnxt_hwrm_func_resc_qcaps(bp, false); 852 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 853 854 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 855 if (max_tx_sch_inputs) 856 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 857 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 858 859 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 860 max_rx_rings = 0; 861 max_tx_rings = 0; 862 } 863 if (max_tx_sch_inputs) 864 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 865 866 tcs = netdev_get_num_tc(dev); 867 if (tcs > 1) 868 max_tx_rings /= tcs; 869 870 channel->max_rx = max_rx_rings; 871 channel->max_tx = max_tx_rings; 872 channel->max_other = 0; 873 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 874 channel->combined_count = bp->rx_nr_rings; 875 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 876 channel->combined_count--; 877 } else { 878 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 879 channel->rx_count = bp->rx_nr_rings; 880 channel->tx_count = bp->tx_nr_rings_per_tc; 881 } 882 } 883 } 884 885 static int bnxt_set_channels(struct net_device *dev, 886 struct ethtool_channels *channel) 887 { 888 struct bnxt *bp = netdev_priv(dev); 889 int req_tx_rings, req_rx_rings, tcs; 890 bool sh = false; 891 int tx_xdp = 0; 892 int rc = 0; 893 894 if (channel->other_count) 895 return -EINVAL; 896 897 if (!channel->combined_count && 898 (!channel->rx_count || !channel->tx_count)) 899 return -EINVAL; 900 901 if (channel->combined_count && 902 (channel->rx_count || channel->tx_count)) 903 return -EINVAL; 904 905 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 906 channel->tx_count)) 907 return -EINVAL; 908 909 if (channel->combined_count) 910 sh = true; 911 912 tcs = netdev_get_num_tc(dev); 913 914 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 915 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 916 if (bp->tx_nr_rings_xdp) { 917 if (!sh) { 918 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 919 return -EINVAL; 920 } 921 tx_xdp = req_rx_rings; 922 } 923 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 924 if (rc) { 925 netdev_warn(dev, "Unable to allocate the requested rings\n"); 926 return rc; 927 } 928 929 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 930 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 931 (dev->priv_flags & IFF_RXFH_CONFIGURED)) { 932 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 933 return -EINVAL; 934 } 935 936 if (netif_running(dev)) { 937 if (BNXT_PF(bp)) { 938 /* TODO CHIMP_FW: Send message to all VF's 939 * before PF unload 940 */ 941 } 942 rc = bnxt_close_nic(bp, true, false); 943 if (rc) { 944 netdev_err(bp->dev, "Set channel failure rc :%x\n", 945 rc); 946 return rc; 947 } 948 } 949 950 if (sh) { 951 bp->flags |= BNXT_FLAG_SHARED_RINGS; 952 bp->rx_nr_rings = channel->combined_count; 953 bp->tx_nr_rings_per_tc = channel->combined_count; 954 } else { 955 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 956 bp->rx_nr_rings = channel->rx_count; 957 bp->tx_nr_rings_per_tc = channel->tx_count; 958 } 959 bp->tx_nr_rings_xdp = tx_xdp; 960 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 961 if (tcs > 1) 962 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 963 964 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 965 bp->tx_nr_rings + bp->rx_nr_rings; 966 967 /* After changing number of rx channels, update NTUPLE feature. */ 968 netdev_update_features(dev); 969 if (netif_running(dev)) { 970 rc = bnxt_open_nic(bp, true, false); 971 if ((!rc) && BNXT_PF(bp)) { 972 /* TODO CHIMP_FW: Send message to all VF's 973 * to renable 974 */ 975 } 976 } else { 977 rc = bnxt_reserve_rings(bp, true); 978 } 979 980 return rc; 981 } 982 983 #ifdef CONFIG_RFS_ACCEL 984 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 985 u32 *rule_locs) 986 { 987 int i, j = 0; 988 989 cmd->data = bp->ntp_fltr_count; 990 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 991 struct hlist_head *head; 992 struct bnxt_ntuple_filter *fltr; 993 994 head = &bp->ntp_fltr_hash_tbl[i]; 995 rcu_read_lock(); 996 hlist_for_each_entry_rcu(fltr, head, hash) { 997 if (j == cmd->rule_cnt) 998 break; 999 rule_locs[j++] = fltr->sw_id; 1000 } 1001 rcu_read_unlock(); 1002 if (j == cmd->rule_cnt) 1003 break; 1004 } 1005 cmd->rule_cnt = j; 1006 return 0; 1007 } 1008 1009 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1010 { 1011 struct ethtool_rx_flow_spec *fs = 1012 (struct ethtool_rx_flow_spec *)&cmd->fs; 1013 struct bnxt_ntuple_filter *fltr; 1014 struct flow_keys *fkeys; 1015 int i, rc = -EINVAL; 1016 1017 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1018 return rc; 1019 1020 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1021 struct hlist_head *head; 1022 1023 head = &bp->ntp_fltr_hash_tbl[i]; 1024 rcu_read_lock(); 1025 hlist_for_each_entry_rcu(fltr, head, hash) { 1026 if (fltr->sw_id == fs->location) 1027 goto fltr_found; 1028 } 1029 rcu_read_unlock(); 1030 } 1031 return rc; 1032 1033 fltr_found: 1034 fkeys = &fltr->fkeys; 1035 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1036 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1037 fs->flow_type = TCP_V4_FLOW; 1038 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1039 fs->flow_type = UDP_V4_FLOW; 1040 else 1041 goto fltr_err; 1042 1043 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1044 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1045 1046 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1047 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1048 1049 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1050 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1051 1052 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1053 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1054 } else { 1055 int i; 1056 1057 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1058 fs->flow_type = TCP_V6_FLOW; 1059 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1060 fs->flow_type = UDP_V6_FLOW; 1061 else 1062 goto fltr_err; 1063 1064 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1065 fkeys->addrs.v6addrs.src; 1066 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1067 fkeys->addrs.v6addrs.dst; 1068 for (i = 0; i < 4; i++) { 1069 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1070 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1071 } 1072 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1073 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1074 1075 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1076 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1077 } 1078 1079 fs->ring_cookie = fltr->rxq; 1080 rc = 0; 1081 1082 fltr_err: 1083 rcu_read_unlock(); 1084 1085 return rc; 1086 } 1087 #endif 1088 1089 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1090 { 1091 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1092 return RXH_IP_SRC | RXH_IP_DST; 1093 return 0; 1094 } 1095 1096 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1097 { 1098 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1099 return RXH_IP_SRC | RXH_IP_DST; 1100 return 0; 1101 } 1102 1103 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1104 { 1105 cmd->data = 0; 1106 switch (cmd->flow_type) { 1107 case TCP_V4_FLOW: 1108 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1109 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1110 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1111 cmd->data |= get_ethtool_ipv4_rss(bp); 1112 break; 1113 case UDP_V4_FLOW: 1114 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1115 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1116 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1117 /* fall through */ 1118 case SCTP_V4_FLOW: 1119 case AH_ESP_V4_FLOW: 1120 case AH_V4_FLOW: 1121 case ESP_V4_FLOW: 1122 case IPV4_FLOW: 1123 cmd->data |= get_ethtool_ipv4_rss(bp); 1124 break; 1125 1126 case TCP_V6_FLOW: 1127 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1128 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1129 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1130 cmd->data |= get_ethtool_ipv6_rss(bp); 1131 break; 1132 case UDP_V6_FLOW: 1133 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1134 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1135 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1136 /* fall through */ 1137 case SCTP_V6_FLOW: 1138 case AH_ESP_V6_FLOW: 1139 case AH_V6_FLOW: 1140 case ESP_V6_FLOW: 1141 case IPV6_FLOW: 1142 cmd->data |= get_ethtool_ipv6_rss(bp); 1143 break; 1144 } 1145 return 0; 1146 } 1147 1148 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1149 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1150 1151 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1152 { 1153 u32 rss_hash_cfg = bp->rss_hash_cfg; 1154 int tuple, rc = 0; 1155 1156 if (cmd->data == RXH_4TUPLE) 1157 tuple = 4; 1158 else if (cmd->data == RXH_2TUPLE) 1159 tuple = 2; 1160 else if (!cmd->data) 1161 tuple = 0; 1162 else 1163 return -EINVAL; 1164 1165 if (cmd->flow_type == TCP_V4_FLOW) { 1166 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1167 if (tuple == 4) 1168 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1169 } else if (cmd->flow_type == UDP_V4_FLOW) { 1170 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1171 return -EINVAL; 1172 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1173 if (tuple == 4) 1174 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1175 } else if (cmd->flow_type == TCP_V6_FLOW) { 1176 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1177 if (tuple == 4) 1178 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1179 } else if (cmd->flow_type == UDP_V6_FLOW) { 1180 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1181 return -EINVAL; 1182 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1183 if (tuple == 4) 1184 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1185 } else if (tuple == 4) { 1186 return -EINVAL; 1187 } 1188 1189 switch (cmd->flow_type) { 1190 case TCP_V4_FLOW: 1191 case UDP_V4_FLOW: 1192 case SCTP_V4_FLOW: 1193 case AH_ESP_V4_FLOW: 1194 case AH_V4_FLOW: 1195 case ESP_V4_FLOW: 1196 case IPV4_FLOW: 1197 if (tuple == 2) 1198 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1199 else if (!tuple) 1200 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1201 break; 1202 1203 case TCP_V6_FLOW: 1204 case UDP_V6_FLOW: 1205 case SCTP_V6_FLOW: 1206 case AH_ESP_V6_FLOW: 1207 case AH_V6_FLOW: 1208 case ESP_V6_FLOW: 1209 case IPV6_FLOW: 1210 if (tuple == 2) 1211 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1212 else if (!tuple) 1213 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1214 break; 1215 } 1216 1217 if (bp->rss_hash_cfg == rss_hash_cfg) 1218 return 0; 1219 1220 bp->rss_hash_cfg = rss_hash_cfg; 1221 if (netif_running(bp->dev)) { 1222 bnxt_close_nic(bp, false, false); 1223 rc = bnxt_open_nic(bp, false, false); 1224 } 1225 return rc; 1226 } 1227 1228 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1229 u32 *rule_locs) 1230 { 1231 struct bnxt *bp = netdev_priv(dev); 1232 int rc = 0; 1233 1234 switch (cmd->cmd) { 1235 #ifdef CONFIG_RFS_ACCEL 1236 case ETHTOOL_GRXRINGS: 1237 cmd->data = bp->rx_nr_rings; 1238 break; 1239 1240 case ETHTOOL_GRXCLSRLCNT: 1241 cmd->rule_cnt = bp->ntp_fltr_count; 1242 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1243 break; 1244 1245 case ETHTOOL_GRXCLSRLALL: 1246 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1247 break; 1248 1249 case ETHTOOL_GRXCLSRULE: 1250 rc = bnxt_grxclsrule(bp, cmd); 1251 break; 1252 #endif 1253 1254 case ETHTOOL_GRXFH: 1255 rc = bnxt_grxfh(bp, cmd); 1256 break; 1257 1258 default: 1259 rc = -EOPNOTSUPP; 1260 break; 1261 } 1262 1263 return rc; 1264 } 1265 1266 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1267 { 1268 struct bnxt *bp = netdev_priv(dev); 1269 int rc; 1270 1271 switch (cmd->cmd) { 1272 case ETHTOOL_SRXFH: 1273 rc = bnxt_srxfh(bp, cmd); 1274 break; 1275 1276 default: 1277 rc = -EOPNOTSUPP; 1278 break; 1279 } 1280 return rc; 1281 } 1282 1283 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1284 { 1285 struct bnxt *bp = netdev_priv(dev); 1286 1287 if (bp->flags & BNXT_FLAG_CHIP_P5) 1288 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1289 return HW_HASH_INDEX_SIZE; 1290 } 1291 1292 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1293 { 1294 return HW_HASH_KEY_SIZE; 1295 } 1296 1297 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1298 u8 *hfunc) 1299 { 1300 struct bnxt *bp = netdev_priv(dev); 1301 struct bnxt_vnic_info *vnic; 1302 u32 i, tbl_size; 1303 1304 if (hfunc) 1305 *hfunc = ETH_RSS_HASH_TOP; 1306 1307 if (!bp->vnic_info) 1308 return 0; 1309 1310 vnic = &bp->vnic_info[0]; 1311 if (indir && bp->rss_indir_tbl) { 1312 tbl_size = bnxt_get_rxfh_indir_size(dev); 1313 for (i = 0; i < tbl_size; i++) 1314 indir[i] = bp->rss_indir_tbl[i]; 1315 } 1316 1317 if (key && vnic->rss_hash_key) 1318 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1319 1320 return 0; 1321 } 1322 1323 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1324 const u8 *key, const u8 hfunc) 1325 { 1326 struct bnxt *bp = netdev_priv(dev); 1327 int rc = 0; 1328 1329 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1330 return -EOPNOTSUPP; 1331 1332 if (key) 1333 return -EOPNOTSUPP; 1334 1335 if (indir) { 1336 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1337 1338 for (i = 0; i < tbl_size; i++) 1339 bp->rss_indir_tbl[i] = indir[i]; 1340 pad = bp->rss_indir_tbl_entries - tbl_size; 1341 if (pad) 1342 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1343 } 1344 1345 if (netif_running(bp->dev)) { 1346 bnxt_close_nic(bp, false, false); 1347 rc = bnxt_open_nic(bp, false, false); 1348 } 1349 return rc; 1350 } 1351 1352 static void bnxt_get_drvinfo(struct net_device *dev, 1353 struct ethtool_drvinfo *info) 1354 { 1355 struct bnxt *bp = netdev_priv(dev); 1356 1357 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1358 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1359 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1360 info->n_stats = bnxt_get_num_stats(bp); 1361 info->testinfo_len = bp->num_tests; 1362 /* TODO CHIMP_FW: eeprom dump details */ 1363 info->eedump_len = 0; 1364 /* TODO CHIMP FW: reg dump details */ 1365 info->regdump_len = 0; 1366 } 1367 1368 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1369 { 1370 struct bnxt *bp = netdev_priv(dev); 1371 1372 wol->supported = 0; 1373 wol->wolopts = 0; 1374 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1375 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1376 wol->supported = WAKE_MAGIC; 1377 if (bp->wol) 1378 wol->wolopts = WAKE_MAGIC; 1379 } 1380 } 1381 1382 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1383 { 1384 struct bnxt *bp = netdev_priv(dev); 1385 1386 if (wol->wolopts & ~WAKE_MAGIC) 1387 return -EINVAL; 1388 1389 if (wol->wolopts & WAKE_MAGIC) { 1390 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1391 return -EINVAL; 1392 if (!bp->wol) { 1393 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1394 return -EBUSY; 1395 bp->wol = 1; 1396 } 1397 } else { 1398 if (bp->wol) { 1399 if (bnxt_hwrm_free_wol_fltr(bp)) 1400 return -EBUSY; 1401 bp->wol = 0; 1402 } 1403 } 1404 return 0; 1405 } 1406 1407 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1408 { 1409 u32 speed_mask = 0; 1410 1411 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1412 /* set the advertised speeds */ 1413 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1414 speed_mask |= ADVERTISED_100baseT_Full; 1415 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1416 speed_mask |= ADVERTISED_1000baseT_Full; 1417 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1418 speed_mask |= ADVERTISED_2500baseX_Full; 1419 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1420 speed_mask |= ADVERTISED_10000baseT_Full; 1421 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1422 speed_mask |= ADVERTISED_40000baseCR4_Full; 1423 1424 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1425 speed_mask |= ADVERTISED_Pause; 1426 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1427 speed_mask |= ADVERTISED_Asym_Pause; 1428 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1429 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1430 1431 return speed_mask; 1432 } 1433 1434 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1435 { \ 1436 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1437 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1438 100baseT_Full); \ 1439 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1440 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1441 1000baseT_Full); \ 1442 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1443 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1444 10000baseT_Full); \ 1445 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1446 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1447 25000baseCR_Full); \ 1448 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1449 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1450 40000baseCR4_Full);\ 1451 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1452 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1453 50000baseCR2_Full);\ 1454 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1455 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1456 100000baseCR4_Full);\ 1457 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1458 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1459 Pause); \ 1460 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1461 ethtool_link_ksettings_add_link_mode( \ 1462 lk_ksettings, name, Asym_Pause);\ 1463 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1464 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1465 Asym_Pause); \ 1466 } \ 1467 } 1468 1469 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1470 { \ 1471 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1472 100baseT_Full) || \ 1473 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1474 100baseT_Half)) \ 1475 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1476 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1477 1000baseT_Full) || \ 1478 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1479 1000baseT_Half)) \ 1480 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1481 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1482 10000baseT_Full)) \ 1483 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1484 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1485 25000baseCR_Full)) \ 1486 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1487 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1488 40000baseCR4_Full)) \ 1489 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1490 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1491 50000baseCR2_Full)) \ 1492 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1493 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1494 100000baseCR4_Full)) \ 1495 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1496 } 1497 1498 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1499 struct ethtool_link_ksettings *lk_ksettings) 1500 { 1501 u16 fw_speeds = link_info->advertising; 1502 u8 fw_pause = 0; 1503 1504 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1505 fw_pause = link_info->auto_pause_setting; 1506 1507 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1508 } 1509 1510 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1511 struct ethtool_link_ksettings *lk_ksettings) 1512 { 1513 u16 fw_speeds = link_info->lp_auto_link_speeds; 1514 u8 fw_pause = 0; 1515 1516 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1517 fw_pause = link_info->lp_pause; 1518 1519 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1520 lp_advertising); 1521 } 1522 1523 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1524 struct ethtool_link_ksettings *lk_ksettings) 1525 { 1526 u16 fw_speeds = link_info->support_speeds; 1527 1528 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1529 1530 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1531 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1532 Asym_Pause); 1533 1534 if (link_info->support_auto_speeds) 1535 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1536 Autoneg); 1537 } 1538 1539 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1540 { 1541 switch (fw_link_speed) { 1542 case BNXT_LINK_SPEED_100MB: 1543 return SPEED_100; 1544 case BNXT_LINK_SPEED_1GB: 1545 return SPEED_1000; 1546 case BNXT_LINK_SPEED_2_5GB: 1547 return SPEED_2500; 1548 case BNXT_LINK_SPEED_10GB: 1549 return SPEED_10000; 1550 case BNXT_LINK_SPEED_20GB: 1551 return SPEED_20000; 1552 case BNXT_LINK_SPEED_25GB: 1553 return SPEED_25000; 1554 case BNXT_LINK_SPEED_40GB: 1555 return SPEED_40000; 1556 case BNXT_LINK_SPEED_50GB: 1557 return SPEED_50000; 1558 case BNXT_LINK_SPEED_100GB: 1559 return SPEED_100000; 1560 default: 1561 return SPEED_UNKNOWN; 1562 } 1563 } 1564 1565 static int bnxt_get_link_ksettings(struct net_device *dev, 1566 struct ethtool_link_ksettings *lk_ksettings) 1567 { 1568 struct bnxt *bp = netdev_priv(dev); 1569 struct bnxt_link_info *link_info = &bp->link_info; 1570 struct ethtool_link_settings *base = &lk_ksettings->base; 1571 u32 ethtool_speed; 1572 1573 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1574 mutex_lock(&bp->link_lock); 1575 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1576 1577 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1578 if (link_info->autoneg) { 1579 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1580 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1581 advertising, Autoneg); 1582 base->autoneg = AUTONEG_ENABLE; 1583 base->duplex = DUPLEX_UNKNOWN; 1584 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1585 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1586 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1587 base->duplex = DUPLEX_FULL; 1588 else 1589 base->duplex = DUPLEX_HALF; 1590 } 1591 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1592 } else { 1593 base->autoneg = AUTONEG_DISABLE; 1594 ethtool_speed = 1595 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1596 base->duplex = DUPLEX_HALF; 1597 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1598 base->duplex = DUPLEX_FULL; 1599 } 1600 base->speed = ethtool_speed; 1601 1602 base->port = PORT_NONE; 1603 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1604 base->port = PORT_TP; 1605 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1606 TP); 1607 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1608 TP); 1609 } else { 1610 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1611 FIBRE); 1612 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1613 FIBRE); 1614 1615 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1616 base->port = PORT_DA; 1617 else if (link_info->media_type == 1618 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1619 base->port = PORT_FIBRE; 1620 } 1621 base->phy_address = link_info->phy_addr; 1622 mutex_unlock(&bp->link_lock); 1623 1624 return 0; 1625 } 1626 1627 static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed) 1628 { 1629 struct bnxt *bp = netdev_priv(dev); 1630 struct bnxt_link_info *link_info = &bp->link_info; 1631 u16 support_spds = link_info->support_speeds; 1632 u32 fw_speed = 0; 1633 1634 switch (ethtool_speed) { 1635 case SPEED_100: 1636 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1637 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB; 1638 break; 1639 case SPEED_1000: 1640 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1641 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB; 1642 break; 1643 case SPEED_2500: 1644 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1645 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB; 1646 break; 1647 case SPEED_10000: 1648 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1649 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB; 1650 break; 1651 case SPEED_20000: 1652 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1653 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB; 1654 break; 1655 case SPEED_25000: 1656 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1657 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB; 1658 break; 1659 case SPEED_40000: 1660 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1661 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB; 1662 break; 1663 case SPEED_50000: 1664 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) 1665 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB; 1666 break; 1667 case SPEED_100000: 1668 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) 1669 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB; 1670 break; 1671 default: 1672 netdev_err(dev, "unsupported speed!\n"); 1673 break; 1674 } 1675 return fw_speed; 1676 } 1677 1678 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1679 { 1680 u16 fw_speed_mask = 0; 1681 1682 /* only support autoneg at speed 100, 1000, and 10000 */ 1683 if (advertising & (ADVERTISED_100baseT_Full | 1684 ADVERTISED_100baseT_Half)) { 1685 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1686 } 1687 if (advertising & (ADVERTISED_1000baseT_Full | 1688 ADVERTISED_1000baseT_Half)) { 1689 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1690 } 1691 if (advertising & ADVERTISED_10000baseT_Full) 1692 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1693 1694 if (advertising & ADVERTISED_40000baseCR4_Full) 1695 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1696 1697 return fw_speed_mask; 1698 } 1699 1700 static int bnxt_set_link_ksettings(struct net_device *dev, 1701 const struct ethtool_link_ksettings *lk_ksettings) 1702 { 1703 struct bnxt *bp = netdev_priv(dev); 1704 struct bnxt_link_info *link_info = &bp->link_info; 1705 const struct ethtool_link_settings *base = &lk_ksettings->base; 1706 bool set_pause = false; 1707 u16 fw_advertising = 0; 1708 u32 speed; 1709 int rc = 0; 1710 1711 if (!BNXT_PHY_CFG_ABLE(bp)) 1712 return -EOPNOTSUPP; 1713 1714 mutex_lock(&bp->link_lock); 1715 if (base->autoneg == AUTONEG_ENABLE) { 1716 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings, 1717 advertising); 1718 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1719 if (!fw_advertising) 1720 link_info->advertising = link_info->support_auto_speeds; 1721 else 1722 link_info->advertising = fw_advertising; 1723 /* any change to autoneg will cause link change, therefore the 1724 * driver should put back the original pause setting in autoneg 1725 */ 1726 set_pause = true; 1727 } else { 1728 u16 fw_speed; 1729 u8 phy_type = link_info->phy_type; 1730 1731 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1732 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1733 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1734 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1735 rc = -EINVAL; 1736 goto set_setting_exit; 1737 } 1738 if (base->duplex == DUPLEX_HALF) { 1739 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1740 rc = -EINVAL; 1741 goto set_setting_exit; 1742 } 1743 speed = base->speed; 1744 fw_speed = bnxt_get_fw_speed(dev, speed); 1745 if (!fw_speed) { 1746 rc = -EINVAL; 1747 goto set_setting_exit; 1748 } 1749 link_info->req_link_speed = fw_speed; 1750 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1751 link_info->autoneg = 0; 1752 link_info->advertising = 0; 1753 } 1754 1755 if (netif_running(dev)) 1756 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1757 1758 set_setting_exit: 1759 mutex_unlock(&bp->link_lock); 1760 return rc; 1761 } 1762 1763 static void bnxt_get_pauseparam(struct net_device *dev, 1764 struct ethtool_pauseparam *epause) 1765 { 1766 struct bnxt *bp = netdev_priv(dev); 1767 struct bnxt_link_info *link_info = &bp->link_info; 1768 1769 if (BNXT_VF(bp)) 1770 return; 1771 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 1772 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 1773 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 1774 } 1775 1776 static int bnxt_set_pauseparam(struct net_device *dev, 1777 struct ethtool_pauseparam *epause) 1778 { 1779 int rc = 0; 1780 struct bnxt *bp = netdev_priv(dev); 1781 struct bnxt_link_info *link_info = &bp->link_info; 1782 1783 if (!BNXT_PHY_CFG_ABLE(bp)) 1784 return -EOPNOTSUPP; 1785 1786 if (epause->autoneg) { 1787 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 1788 return -EINVAL; 1789 1790 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 1791 if (bp->hwrm_spec_code >= 0x10201) 1792 link_info->req_flow_ctrl = 1793 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 1794 } else { 1795 /* when transition from auto pause to force pause, 1796 * force a link change 1797 */ 1798 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1799 link_info->force_link_chng = true; 1800 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 1801 link_info->req_flow_ctrl = 0; 1802 } 1803 if (epause->rx_pause) 1804 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 1805 1806 if (epause->tx_pause) 1807 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 1808 1809 if (netif_running(dev)) 1810 rc = bnxt_hwrm_set_pause(bp); 1811 return rc; 1812 } 1813 1814 static u32 bnxt_get_link(struct net_device *dev) 1815 { 1816 struct bnxt *bp = netdev_priv(dev); 1817 1818 /* TODO: handle MF, VF, driver close case */ 1819 return bp->link_info.link_up; 1820 } 1821 1822 static void bnxt_print_admin_err(struct bnxt *bp) 1823 { 1824 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 1825 } 1826 1827 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 1828 u16 ext, u16 *index, u32 *item_length, 1829 u32 *data_length); 1830 1831 static int bnxt_flash_nvram(struct net_device *dev, 1832 u16 dir_type, 1833 u16 dir_ordinal, 1834 u16 dir_ext, 1835 u16 dir_attr, 1836 const u8 *data, 1837 size_t data_len) 1838 { 1839 struct bnxt *bp = netdev_priv(dev); 1840 int rc; 1841 struct hwrm_nvm_write_input req = {0}; 1842 dma_addr_t dma_handle; 1843 u8 *kmem; 1844 1845 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 1846 1847 req.dir_type = cpu_to_le16(dir_type); 1848 req.dir_ordinal = cpu_to_le16(dir_ordinal); 1849 req.dir_ext = cpu_to_le16(dir_ext); 1850 req.dir_attr = cpu_to_le16(dir_attr); 1851 req.dir_data_length = cpu_to_le32(data_len); 1852 1853 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 1854 GFP_KERNEL); 1855 if (!kmem) { 1856 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 1857 (unsigned)data_len); 1858 return -ENOMEM; 1859 } 1860 memcpy(kmem, data, data_len); 1861 req.host_src_addr = cpu_to_le64(dma_handle); 1862 1863 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 1864 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 1865 1866 if (rc == -EACCES) 1867 bnxt_print_admin_err(bp); 1868 return rc; 1869 } 1870 1871 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 1872 u8 self_reset, u8 flags) 1873 { 1874 struct hwrm_fw_reset_input req = {0}; 1875 struct bnxt *bp = netdev_priv(dev); 1876 int rc; 1877 1878 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 1879 1880 req.embedded_proc_type = proc_type; 1881 req.selfrst_status = self_reset; 1882 req.flags = flags; 1883 1884 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 1885 rc = hwrm_send_message_silent(bp, &req, sizeof(req), 1886 HWRM_CMD_TIMEOUT); 1887 } else { 1888 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1889 if (rc == -EACCES) 1890 bnxt_print_admin_err(bp); 1891 } 1892 return rc; 1893 } 1894 1895 static int bnxt_firmware_reset(struct net_device *dev, 1896 enum bnxt_nvm_directory_type dir_type) 1897 { 1898 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 1899 u8 proc_type, flags = 0; 1900 1901 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 1902 /* (e.g. when firmware isn't already running) */ 1903 switch (dir_type) { 1904 case BNX_DIR_TYPE_CHIMP_PATCH: 1905 case BNX_DIR_TYPE_BOOTCODE: 1906 case BNX_DIR_TYPE_BOOTCODE_2: 1907 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 1908 /* Self-reset ChiMP upon next PCIe reset: */ 1909 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1910 break; 1911 case BNX_DIR_TYPE_APE_FW: 1912 case BNX_DIR_TYPE_APE_PATCH: 1913 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 1914 /* Self-reset APE upon next PCIe reset: */ 1915 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1916 break; 1917 case BNX_DIR_TYPE_KONG_FW: 1918 case BNX_DIR_TYPE_KONG_PATCH: 1919 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 1920 break; 1921 case BNX_DIR_TYPE_BONO_FW: 1922 case BNX_DIR_TYPE_BONO_PATCH: 1923 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 1924 break; 1925 default: 1926 return -EINVAL; 1927 } 1928 1929 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 1930 } 1931 1932 static int bnxt_firmware_reset_chip(struct net_device *dev) 1933 { 1934 struct bnxt *bp = netdev_priv(dev); 1935 u8 flags = 0; 1936 1937 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 1938 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 1939 1940 return bnxt_hwrm_firmware_reset(dev, 1941 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 1942 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 1943 flags); 1944 } 1945 1946 static int bnxt_firmware_reset_ap(struct net_device *dev) 1947 { 1948 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 1949 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 1950 0); 1951 } 1952 1953 static int bnxt_flash_firmware(struct net_device *dev, 1954 u16 dir_type, 1955 const u8 *fw_data, 1956 size_t fw_size) 1957 { 1958 int rc = 0; 1959 u16 code_type; 1960 u32 stored_crc; 1961 u32 calculated_crc; 1962 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 1963 1964 switch (dir_type) { 1965 case BNX_DIR_TYPE_BOOTCODE: 1966 case BNX_DIR_TYPE_BOOTCODE_2: 1967 code_type = CODE_BOOT; 1968 break; 1969 case BNX_DIR_TYPE_CHIMP_PATCH: 1970 code_type = CODE_CHIMP_PATCH; 1971 break; 1972 case BNX_DIR_TYPE_APE_FW: 1973 code_type = CODE_MCTP_PASSTHRU; 1974 break; 1975 case BNX_DIR_TYPE_APE_PATCH: 1976 code_type = CODE_APE_PATCH; 1977 break; 1978 case BNX_DIR_TYPE_KONG_FW: 1979 code_type = CODE_KONG_FW; 1980 break; 1981 case BNX_DIR_TYPE_KONG_PATCH: 1982 code_type = CODE_KONG_PATCH; 1983 break; 1984 case BNX_DIR_TYPE_BONO_FW: 1985 code_type = CODE_BONO_FW; 1986 break; 1987 case BNX_DIR_TYPE_BONO_PATCH: 1988 code_type = CODE_BONO_PATCH; 1989 break; 1990 default: 1991 netdev_err(dev, "Unsupported directory entry type: %u\n", 1992 dir_type); 1993 return -EINVAL; 1994 } 1995 if (fw_size < sizeof(struct bnxt_fw_header)) { 1996 netdev_err(dev, "Invalid firmware file size: %u\n", 1997 (unsigned int)fw_size); 1998 return -EINVAL; 1999 } 2000 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2001 netdev_err(dev, "Invalid firmware signature: %08X\n", 2002 le32_to_cpu(header->signature)); 2003 return -EINVAL; 2004 } 2005 if (header->code_type != code_type) { 2006 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2007 code_type, header->code_type); 2008 return -EINVAL; 2009 } 2010 if (header->device != DEVICE_CUMULUS_FAMILY) { 2011 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2012 DEVICE_CUMULUS_FAMILY, header->device); 2013 return -EINVAL; 2014 } 2015 /* Confirm the CRC32 checksum of the file: */ 2016 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2017 sizeof(stored_crc))); 2018 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2019 if (calculated_crc != stored_crc) { 2020 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2021 (unsigned long)stored_crc, 2022 (unsigned long)calculated_crc); 2023 return -EINVAL; 2024 } 2025 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2026 0, 0, fw_data, fw_size); 2027 if (rc == 0) /* Firmware update successful */ 2028 rc = bnxt_firmware_reset(dev, dir_type); 2029 2030 return rc; 2031 } 2032 2033 static int bnxt_flash_microcode(struct net_device *dev, 2034 u16 dir_type, 2035 const u8 *fw_data, 2036 size_t fw_size) 2037 { 2038 struct bnxt_ucode_trailer *trailer; 2039 u32 calculated_crc; 2040 u32 stored_crc; 2041 int rc = 0; 2042 2043 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2044 netdev_err(dev, "Invalid microcode file size: %u\n", 2045 (unsigned int)fw_size); 2046 return -EINVAL; 2047 } 2048 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2049 sizeof(*trailer))); 2050 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2051 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2052 le32_to_cpu(trailer->sig)); 2053 return -EINVAL; 2054 } 2055 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2056 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2057 dir_type, le16_to_cpu(trailer->dir_type)); 2058 return -EINVAL; 2059 } 2060 if (le16_to_cpu(trailer->trailer_length) < 2061 sizeof(struct bnxt_ucode_trailer)) { 2062 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2063 le16_to_cpu(trailer->trailer_length)); 2064 return -EINVAL; 2065 } 2066 2067 /* Confirm the CRC32 checksum of the file: */ 2068 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2069 sizeof(stored_crc))); 2070 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2071 if (calculated_crc != stored_crc) { 2072 netdev_err(dev, 2073 "CRC32 (%08lX) does not match calculated: %08lX\n", 2074 (unsigned long)stored_crc, 2075 (unsigned long)calculated_crc); 2076 return -EINVAL; 2077 } 2078 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2079 0, 0, fw_data, fw_size); 2080 2081 return rc; 2082 } 2083 2084 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2085 { 2086 switch (dir_type) { 2087 case BNX_DIR_TYPE_CHIMP_PATCH: 2088 case BNX_DIR_TYPE_BOOTCODE: 2089 case BNX_DIR_TYPE_BOOTCODE_2: 2090 case BNX_DIR_TYPE_APE_FW: 2091 case BNX_DIR_TYPE_APE_PATCH: 2092 case BNX_DIR_TYPE_KONG_FW: 2093 case BNX_DIR_TYPE_KONG_PATCH: 2094 case BNX_DIR_TYPE_BONO_FW: 2095 case BNX_DIR_TYPE_BONO_PATCH: 2096 return true; 2097 } 2098 2099 return false; 2100 } 2101 2102 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2103 { 2104 switch (dir_type) { 2105 case BNX_DIR_TYPE_AVS: 2106 case BNX_DIR_TYPE_EXP_ROM_MBA: 2107 case BNX_DIR_TYPE_PCIE: 2108 case BNX_DIR_TYPE_TSCF_UCODE: 2109 case BNX_DIR_TYPE_EXT_PHY: 2110 case BNX_DIR_TYPE_CCM: 2111 case BNX_DIR_TYPE_ISCSI_BOOT: 2112 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2113 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2114 return true; 2115 } 2116 2117 return false; 2118 } 2119 2120 static bool bnxt_dir_type_is_executable(u16 dir_type) 2121 { 2122 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2123 bnxt_dir_type_is_other_exec_format(dir_type); 2124 } 2125 2126 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2127 u16 dir_type, 2128 const char *filename) 2129 { 2130 const struct firmware *fw; 2131 int rc; 2132 2133 rc = request_firmware(&fw, filename, &dev->dev); 2134 if (rc != 0) { 2135 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2136 rc, filename); 2137 return rc; 2138 } 2139 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2140 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2141 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2142 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2143 else 2144 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2145 0, 0, fw->data, fw->size); 2146 release_firmware(fw); 2147 return rc; 2148 } 2149 2150 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2151 u32 install_type) 2152 { 2153 struct bnxt *bp = netdev_priv(dev); 2154 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2155 struct hwrm_nvm_install_update_input install = {0}; 2156 const struct firmware *fw; 2157 u32 item_len; 2158 int rc = 0; 2159 u16 index; 2160 2161 bnxt_hwrm_fw_set_time(bp); 2162 2163 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2164 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2165 &index, &item_len, NULL); 2166 if (rc) { 2167 netdev_err(dev, "PKG update area not created in nvram\n"); 2168 return rc; 2169 } 2170 2171 rc = request_firmware(&fw, filename, &dev->dev); 2172 if (rc != 0) { 2173 netdev_err(dev, "PKG error %d requesting file: %s\n", 2174 rc, filename); 2175 return rc; 2176 } 2177 2178 if (fw->size > item_len) { 2179 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2180 (unsigned long)fw->size); 2181 rc = -EFBIG; 2182 } else { 2183 dma_addr_t dma_handle; 2184 u8 *kmem; 2185 struct hwrm_nvm_modify_input modify = {0}; 2186 2187 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2188 2189 modify.dir_idx = cpu_to_le16(index); 2190 modify.len = cpu_to_le32(fw->size); 2191 2192 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2193 &dma_handle, GFP_KERNEL); 2194 if (!kmem) { 2195 netdev_err(dev, 2196 "dma_alloc_coherent failure, length = %u\n", 2197 (unsigned int)fw->size); 2198 rc = -ENOMEM; 2199 } else { 2200 memcpy(kmem, fw->data, fw->size); 2201 modify.host_src_addr = cpu_to_le64(dma_handle); 2202 2203 rc = hwrm_send_message(bp, &modify, sizeof(modify), 2204 FLASH_PACKAGE_TIMEOUT); 2205 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2206 dma_handle); 2207 } 2208 } 2209 release_firmware(fw); 2210 if (rc) 2211 goto err_exit; 2212 2213 if ((install_type & 0xffff) == 0) 2214 install_type >>= 16; 2215 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2216 install.install_type = cpu_to_le32(install_type); 2217 2218 mutex_lock(&bp->hwrm_cmd_lock); 2219 rc = _hwrm_send_message(bp, &install, sizeof(install), 2220 INSTALL_PACKAGE_TIMEOUT); 2221 if (rc) { 2222 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2223 2224 if (resp->error_code && error_code == 2225 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2226 install.flags |= cpu_to_le16( 2227 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2228 rc = _hwrm_send_message(bp, &install, sizeof(install), 2229 INSTALL_PACKAGE_TIMEOUT); 2230 } 2231 if (rc) 2232 goto flash_pkg_exit; 2233 } 2234 2235 if (resp->result) { 2236 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2237 (s8)resp->result, (int)resp->problem_item); 2238 rc = -ENOPKG; 2239 } 2240 flash_pkg_exit: 2241 mutex_unlock(&bp->hwrm_cmd_lock); 2242 err_exit: 2243 if (rc == -EACCES) 2244 bnxt_print_admin_err(bp); 2245 return rc; 2246 } 2247 2248 static int bnxt_flash_device(struct net_device *dev, 2249 struct ethtool_flash *flash) 2250 { 2251 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2252 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2253 return -EINVAL; 2254 } 2255 2256 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2257 flash->region > 0xffff) 2258 return bnxt_flash_package_from_file(dev, flash->data, 2259 flash->region); 2260 2261 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2262 } 2263 2264 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2265 { 2266 struct bnxt *bp = netdev_priv(dev); 2267 int rc; 2268 struct hwrm_nvm_get_dir_info_input req = {0}; 2269 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2270 2271 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2272 2273 mutex_lock(&bp->hwrm_cmd_lock); 2274 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2275 if (!rc) { 2276 *entries = le32_to_cpu(output->entries); 2277 *length = le32_to_cpu(output->entry_length); 2278 } 2279 mutex_unlock(&bp->hwrm_cmd_lock); 2280 return rc; 2281 } 2282 2283 static int bnxt_get_eeprom_len(struct net_device *dev) 2284 { 2285 struct bnxt *bp = netdev_priv(dev); 2286 2287 if (BNXT_VF(bp)) 2288 return 0; 2289 2290 /* The -1 return value allows the entire 32-bit range of offsets to be 2291 * passed via the ethtool command-line utility. 2292 */ 2293 return -1; 2294 } 2295 2296 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2297 { 2298 struct bnxt *bp = netdev_priv(dev); 2299 int rc; 2300 u32 dir_entries; 2301 u32 entry_length; 2302 u8 *buf; 2303 size_t buflen; 2304 dma_addr_t dma_handle; 2305 struct hwrm_nvm_get_dir_entries_input req = {0}; 2306 2307 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2308 if (rc != 0) 2309 return rc; 2310 2311 /* Insert 2 bytes of directory info (count and size of entries) */ 2312 if (len < 2) 2313 return -EINVAL; 2314 2315 *data++ = dir_entries; 2316 *data++ = entry_length; 2317 len -= 2; 2318 memset(data, 0xff, len); 2319 2320 buflen = dir_entries * entry_length; 2321 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2322 GFP_KERNEL); 2323 if (!buf) { 2324 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2325 (unsigned)buflen); 2326 return -ENOMEM; 2327 } 2328 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2329 req.host_dest_addr = cpu_to_le64(dma_handle); 2330 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2331 if (rc == 0) 2332 memcpy(data, buf, len > buflen ? buflen : len); 2333 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2334 return rc; 2335 } 2336 2337 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2338 u32 length, u8 *data) 2339 { 2340 struct bnxt *bp = netdev_priv(dev); 2341 int rc; 2342 u8 *buf; 2343 dma_addr_t dma_handle; 2344 struct hwrm_nvm_read_input req = {0}; 2345 2346 if (!length) 2347 return -EINVAL; 2348 2349 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2350 GFP_KERNEL); 2351 if (!buf) { 2352 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2353 (unsigned)length); 2354 return -ENOMEM; 2355 } 2356 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2357 req.host_dest_addr = cpu_to_le64(dma_handle); 2358 req.dir_idx = cpu_to_le16(index); 2359 req.offset = cpu_to_le32(offset); 2360 req.len = cpu_to_le32(length); 2361 2362 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2363 if (rc == 0) 2364 memcpy(data, buf, length); 2365 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2366 return rc; 2367 } 2368 2369 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2370 u16 ext, u16 *index, u32 *item_length, 2371 u32 *data_length) 2372 { 2373 struct bnxt *bp = netdev_priv(dev); 2374 int rc; 2375 struct hwrm_nvm_find_dir_entry_input req = {0}; 2376 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2377 2378 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2379 req.enables = 0; 2380 req.dir_idx = 0; 2381 req.dir_type = cpu_to_le16(type); 2382 req.dir_ordinal = cpu_to_le16(ordinal); 2383 req.dir_ext = cpu_to_le16(ext); 2384 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2385 mutex_lock(&bp->hwrm_cmd_lock); 2386 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2387 if (rc == 0) { 2388 if (index) 2389 *index = le16_to_cpu(output->dir_idx); 2390 if (item_length) 2391 *item_length = le32_to_cpu(output->dir_item_length); 2392 if (data_length) 2393 *data_length = le32_to_cpu(output->dir_data_length); 2394 } 2395 mutex_unlock(&bp->hwrm_cmd_lock); 2396 return rc; 2397 } 2398 2399 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2400 { 2401 char *retval = NULL; 2402 char *p; 2403 char *value; 2404 int field = 0; 2405 2406 if (datalen < 1) 2407 return NULL; 2408 /* null-terminate the log data (removing last '\n'): */ 2409 data[datalen - 1] = 0; 2410 for (p = data; *p != 0; p++) { 2411 field = 0; 2412 retval = NULL; 2413 while (*p != 0 && *p != '\n') { 2414 value = p; 2415 while (*p != 0 && *p != '\t' && *p != '\n') 2416 p++; 2417 if (field == desired_field) 2418 retval = value; 2419 if (*p != '\t') 2420 break; 2421 *p = 0; 2422 field++; 2423 p++; 2424 } 2425 if (*p == 0) 2426 break; 2427 *p = 0; 2428 } 2429 return retval; 2430 } 2431 2432 static void bnxt_get_pkgver(struct net_device *dev) 2433 { 2434 struct bnxt *bp = netdev_priv(dev); 2435 u16 index = 0; 2436 char *pkgver; 2437 u32 pkglen; 2438 u8 *pkgbuf; 2439 int len; 2440 2441 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2442 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2443 &index, NULL, &pkglen) != 0) 2444 return; 2445 2446 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2447 if (!pkgbuf) { 2448 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2449 pkglen); 2450 return; 2451 } 2452 2453 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2454 goto err; 2455 2456 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2457 pkglen); 2458 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2459 len = strlen(bp->fw_ver_str); 2460 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2461 "/pkg %s", pkgver); 2462 } 2463 err: 2464 kfree(pkgbuf); 2465 } 2466 2467 static int bnxt_get_eeprom(struct net_device *dev, 2468 struct ethtool_eeprom *eeprom, 2469 u8 *data) 2470 { 2471 u32 index; 2472 u32 offset; 2473 2474 if (eeprom->offset == 0) /* special offset value to get directory */ 2475 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2476 2477 index = eeprom->offset >> 24; 2478 offset = eeprom->offset & 0xffffff; 2479 2480 if (index == 0) { 2481 netdev_err(dev, "unsupported index value: %d\n", index); 2482 return -EINVAL; 2483 } 2484 2485 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2486 } 2487 2488 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2489 { 2490 struct bnxt *bp = netdev_priv(dev); 2491 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2492 2493 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2494 req.dir_idx = cpu_to_le16(index); 2495 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2496 } 2497 2498 static int bnxt_set_eeprom(struct net_device *dev, 2499 struct ethtool_eeprom *eeprom, 2500 u8 *data) 2501 { 2502 struct bnxt *bp = netdev_priv(dev); 2503 u8 index, dir_op; 2504 u16 type, ext, ordinal, attr; 2505 2506 if (!BNXT_PF(bp)) { 2507 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2508 return -EINVAL; 2509 } 2510 2511 type = eeprom->magic >> 16; 2512 2513 if (type == 0xffff) { /* special value for directory operations */ 2514 index = eeprom->magic & 0xff; 2515 dir_op = eeprom->magic >> 8; 2516 if (index == 0) 2517 return -EINVAL; 2518 switch (dir_op) { 2519 case 0x0e: /* erase */ 2520 if (eeprom->offset != ~eeprom->magic) 2521 return -EINVAL; 2522 return bnxt_erase_nvram_directory(dev, index - 1); 2523 default: 2524 return -EINVAL; 2525 } 2526 } 2527 2528 /* Create or re-write an NVM item: */ 2529 if (bnxt_dir_type_is_executable(type)) 2530 return -EOPNOTSUPP; 2531 ext = eeprom->magic & 0xffff; 2532 ordinal = eeprom->offset >> 16; 2533 attr = eeprom->offset & 0xffff; 2534 2535 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2536 eeprom->len); 2537 } 2538 2539 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2540 { 2541 struct bnxt *bp = netdev_priv(dev); 2542 struct ethtool_eee *eee = &bp->eee; 2543 struct bnxt_link_info *link_info = &bp->link_info; 2544 u32 advertising = 2545 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2546 int rc = 0; 2547 2548 if (!BNXT_PHY_CFG_ABLE(bp)) 2549 return -EOPNOTSUPP; 2550 2551 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2552 return -EOPNOTSUPP; 2553 2554 if (!edata->eee_enabled) 2555 goto eee_ok; 2556 2557 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2558 netdev_warn(dev, "EEE requires autoneg\n"); 2559 return -EINVAL; 2560 } 2561 if (edata->tx_lpi_enabled) { 2562 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2563 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2564 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2565 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2566 return -EINVAL; 2567 } else if (!bp->lpi_tmr_hi) { 2568 edata->tx_lpi_timer = eee->tx_lpi_timer; 2569 } 2570 } 2571 if (!edata->advertised) { 2572 edata->advertised = advertising & eee->supported; 2573 } else if (edata->advertised & ~advertising) { 2574 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2575 edata->advertised, advertising); 2576 return -EINVAL; 2577 } 2578 2579 eee->advertised = edata->advertised; 2580 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2581 eee->tx_lpi_timer = edata->tx_lpi_timer; 2582 eee_ok: 2583 eee->eee_enabled = edata->eee_enabled; 2584 2585 if (netif_running(dev)) 2586 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2587 2588 return rc; 2589 } 2590 2591 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2592 { 2593 struct bnxt *bp = netdev_priv(dev); 2594 2595 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2596 return -EOPNOTSUPP; 2597 2598 *edata = bp->eee; 2599 if (!bp->eee.eee_enabled) { 2600 /* Preserve tx_lpi_timer so that the last value will be used 2601 * by default when it is re-enabled. 2602 */ 2603 edata->advertised = 0; 2604 edata->tx_lpi_enabled = 0; 2605 } 2606 2607 if (!bp->eee.eee_active) 2608 edata->lp_advertised = 0; 2609 2610 return 0; 2611 } 2612 2613 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2614 u16 page_number, u16 start_addr, 2615 u16 data_length, u8 *buf) 2616 { 2617 struct hwrm_port_phy_i2c_read_input req = {0}; 2618 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2619 int rc, byte_offset = 0; 2620 2621 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2622 req.i2c_slave_addr = i2c_addr; 2623 req.page_number = cpu_to_le16(page_number); 2624 req.port_id = cpu_to_le16(bp->pf.port_id); 2625 do { 2626 u16 xfer_size; 2627 2628 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2629 data_length -= xfer_size; 2630 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2631 req.data_length = xfer_size; 2632 req.enables = cpu_to_le32(start_addr + byte_offset ? 2633 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2634 mutex_lock(&bp->hwrm_cmd_lock); 2635 rc = _hwrm_send_message(bp, &req, sizeof(req), 2636 HWRM_CMD_TIMEOUT); 2637 if (!rc) 2638 memcpy(buf + byte_offset, output->data, xfer_size); 2639 mutex_unlock(&bp->hwrm_cmd_lock); 2640 byte_offset += xfer_size; 2641 } while (!rc && data_length > 0); 2642 2643 return rc; 2644 } 2645 2646 static int bnxt_get_module_info(struct net_device *dev, 2647 struct ethtool_modinfo *modinfo) 2648 { 2649 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2650 struct bnxt *bp = netdev_priv(dev); 2651 int rc; 2652 2653 /* No point in going further if phy status indicates 2654 * module is not inserted or if it is powered down or 2655 * if it is of type 10GBase-T 2656 */ 2657 if (bp->link_info.module_status > 2658 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2659 return -EOPNOTSUPP; 2660 2661 /* This feature is not supported in older firmware versions */ 2662 if (bp->hwrm_spec_code < 0x10202) 2663 return -EOPNOTSUPP; 2664 2665 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2666 SFF_DIAG_SUPPORT_OFFSET + 1, 2667 data); 2668 if (!rc) { 2669 u8 module_id = data[0]; 2670 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2671 2672 switch (module_id) { 2673 case SFF_MODULE_ID_SFP: 2674 modinfo->type = ETH_MODULE_SFF_8472; 2675 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2676 if (!diag_supported) 2677 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2678 break; 2679 case SFF_MODULE_ID_QSFP: 2680 case SFF_MODULE_ID_QSFP_PLUS: 2681 modinfo->type = ETH_MODULE_SFF_8436; 2682 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2683 break; 2684 case SFF_MODULE_ID_QSFP28: 2685 modinfo->type = ETH_MODULE_SFF_8636; 2686 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2687 break; 2688 default: 2689 rc = -EOPNOTSUPP; 2690 break; 2691 } 2692 } 2693 return rc; 2694 } 2695 2696 static int bnxt_get_module_eeprom(struct net_device *dev, 2697 struct ethtool_eeprom *eeprom, 2698 u8 *data) 2699 { 2700 struct bnxt *bp = netdev_priv(dev); 2701 u16 start = eeprom->offset, length = eeprom->len; 2702 int rc = 0; 2703 2704 memset(data, 0, eeprom->len); 2705 2706 /* Read A0 portion of the EEPROM */ 2707 if (start < ETH_MODULE_SFF_8436_LEN) { 2708 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 2709 length = ETH_MODULE_SFF_8436_LEN - start; 2710 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 2711 start, length, data); 2712 if (rc) 2713 return rc; 2714 start += length; 2715 data += length; 2716 length = eeprom->len - length; 2717 } 2718 2719 /* Read A2 portion of the EEPROM */ 2720 if (length) { 2721 start -= ETH_MODULE_SFF_8436_LEN; 2722 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, 2723 start, length, data); 2724 } 2725 return rc; 2726 } 2727 2728 static int bnxt_nway_reset(struct net_device *dev) 2729 { 2730 int rc = 0; 2731 2732 struct bnxt *bp = netdev_priv(dev); 2733 struct bnxt_link_info *link_info = &bp->link_info; 2734 2735 if (!BNXT_PHY_CFG_ABLE(bp)) 2736 return -EOPNOTSUPP; 2737 2738 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 2739 return -EINVAL; 2740 2741 if (netif_running(dev)) 2742 rc = bnxt_hwrm_set_link_setting(bp, true, false); 2743 2744 return rc; 2745 } 2746 2747 static int bnxt_set_phys_id(struct net_device *dev, 2748 enum ethtool_phys_id_state state) 2749 { 2750 struct hwrm_port_led_cfg_input req = {0}; 2751 struct bnxt *bp = netdev_priv(dev); 2752 struct bnxt_pf_info *pf = &bp->pf; 2753 struct bnxt_led_cfg *led_cfg; 2754 u8 led_state; 2755 __le16 duration; 2756 int i; 2757 2758 if (!bp->num_leds || BNXT_VF(bp)) 2759 return -EOPNOTSUPP; 2760 2761 if (state == ETHTOOL_ID_ACTIVE) { 2762 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 2763 duration = cpu_to_le16(500); 2764 } else if (state == ETHTOOL_ID_INACTIVE) { 2765 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 2766 duration = cpu_to_le16(0); 2767 } else { 2768 return -EINVAL; 2769 } 2770 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 2771 req.port_id = cpu_to_le16(pf->port_id); 2772 req.num_leds = bp->num_leds; 2773 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 2774 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 2775 req.enables |= BNXT_LED_DFLT_ENABLES(i); 2776 led_cfg->led_id = bp->leds[i].led_id; 2777 led_cfg->led_state = led_state; 2778 led_cfg->led_blink_on = duration; 2779 led_cfg->led_blink_off = duration; 2780 led_cfg->led_group_id = bp->leds[i].led_group_id; 2781 } 2782 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2783 } 2784 2785 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 2786 { 2787 struct hwrm_selftest_irq_input req = {0}; 2788 2789 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 2790 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2791 } 2792 2793 static int bnxt_test_irq(struct bnxt *bp) 2794 { 2795 int i; 2796 2797 for (i = 0; i < bp->cp_nr_rings; i++) { 2798 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 2799 int rc; 2800 2801 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 2802 if (rc) 2803 return rc; 2804 } 2805 return 0; 2806 } 2807 2808 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 2809 { 2810 struct hwrm_port_mac_cfg_input req = {0}; 2811 2812 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 2813 2814 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 2815 if (enable) 2816 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 2817 else 2818 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 2819 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2820 } 2821 2822 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 2823 { 2824 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 2825 struct hwrm_port_phy_qcaps_input req = {0}; 2826 int rc; 2827 2828 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 2829 mutex_lock(&bp->hwrm_cmd_lock); 2830 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2831 if (!rc) 2832 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 2833 2834 mutex_unlock(&bp->hwrm_cmd_lock); 2835 return rc; 2836 } 2837 2838 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 2839 struct hwrm_port_phy_cfg_input *req) 2840 { 2841 struct bnxt_link_info *link_info = &bp->link_info; 2842 u16 fw_advertising; 2843 u16 fw_speed; 2844 int rc; 2845 2846 if (!link_info->autoneg || 2847 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK)) 2848 return 0; 2849 2850 rc = bnxt_query_force_speeds(bp, &fw_advertising); 2851 if (rc) 2852 return rc; 2853 2854 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2855 if (bp->link_info.link_up) 2856 fw_speed = bp->link_info.link_speed; 2857 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 2858 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2859 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 2860 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2861 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 2862 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2863 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 2864 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2865 2866 req->force_link_speed = cpu_to_le16(fw_speed); 2867 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 2868 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2869 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 2870 req->flags = 0; 2871 req->force_link_speed = cpu_to_le16(0); 2872 return rc; 2873 } 2874 2875 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 2876 { 2877 struct hwrm_port_phy_cfg_input req = {0}; 2878 2879 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 2880 2881 if (enable) { 2882 bnxt_disable_an_for_lpbk(bp, &req); 2883 if (ext) 2884 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 2885 else 2886 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 2887 } else { 2888 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 2889 } 2890 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 2891 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2892 } 2893 2894 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2895 u32 raw_cons, int pkt_size) 2896 { 2897 struct bnxt_napi *bnapi = cpr->bnapi; 2898 struct bnxt_rx_ring_info *rxr; 2899 struct bnxt_sw_rx_bd *rx_buf; 2900 struct rx_cmp *rxcmp; 2901 u16 cp_cons, cons; 2902 u8 *data; 2903 u32 len; 2904 int i; 2905 2906 rxr = bnapi->rx_ring; 2907 cp_cons = RING_CMP(raw_cons); 2908 rxcmp = (struct rx_cmp *) 2909 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2910 cons = rxcmp->rx_cmp_opaque; 2911 rx_buf = &rxr->rx_buf_ring[cons]; 2912 data = rx_buf->data_ptr; 2913 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 2914 if (len != pkt_size) 2915 return -EIO; 2916 i = ETH_ALEN; 2917 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 2918 return -EIO; 2919 i += ETH_ALEN; 2920 for ( ; i < pkt_size; i++) { 2921 if (data[i] != (u8)(i & 0xff)) 2922 return -EIO; 2923 } 2924 return 0; 2925 } 2926 2927 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2928 int pkt_size) 2929 { 2930 struct tx_cmp *txcmp; 2931 int rc = -EIO; 2932 u32 raw_cons; 2933 u32 cons; 2934 int i; 2935 2936 raw_cons = cpr->cp_raw_cons; 2937 for (i = 0; i < 200; i++) { 2938 cons = RING_CMP(raw_cons); 2939 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2940 2941 if (!TX_CMP_VALID(txcmp, raw_cons)) { 2942 udelay(5); 2943 continue; 2944 } 2945 2946 /* The valid test of the entry must be done first before 2947 * reading any further. 2948 */ 2949 dma_rmb(); 2950 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 2951 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 2952 raw_cons = NEXT_RAW_CMP(raw_cons); 2953 raw_cons = NEXT_RAW_CMP(raw_cons); 2954 break; 2955 } 2956 raw_cons = NEXT_RAW_CMP(raw_cons); 2957 } 2958 cpr->cp_raw_cons = raw_cons; 2959 return rc; 2960 } 2961 2962 static int bnxt_run_loopback(struct bnxt *bp) 2963 { 2964 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 2965 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 2966 struct bnxt_cp_ring_info *cpr; 2967 int pkt_size, i = 0; 2968 struct sk_buff *skb; 2969 dma_addr_t map; 2970 u8 *data; 2971 int rc; 2972 2973 cpr = &rxr->bnapi->cp_ring; 2974 if (bp->flags & BNXT_FLAG_CHIP_P5) 2975 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 2976 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 2977 skb = netdev_alloc_skb(bp->dev, pkt_size); 2978 if (!skb) 2979 return -ENOMEM; 2980 data = skb_put(skb, pkt_size); 2981 eth_broadcast_addr(data); 2982 i += ETH_ALEN; 2983 ether_addr_copy(&data[i], bp->dev->dev_addr); 2984 i += ETH_ALEN; 2985 for ( ; i < pkt_size; i++) 2986 data[i] = (u8)(i & 0xff); 2987 2988 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 2989 PCI_DMA_TODEVICE); 2990 if (dma_mapping_error(&bp->pdev->dev, map)) { 2991 dev_kfree_skb(skb); 2992 return -EIO; 2993 } 2994 bnxt_xmit_bd(bp, txr, map, pkt_size); 2995 2996 /* Sync BD data before updating doorbell */ 2997 wmb(); 2998 2999 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3000 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3001 3002 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 3003 dev_kfree_skb(skb); 3004 return rc; 3005 } 3006 3007 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3008 { 3009 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 3010 struct hwrm_selftest_exec_input req = {0}; 3011 int rc; 3012 3013 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 3014 mutex_lock(&bp->hwrm_cmd_lock); 3015 resp->test_success = 0; 3016 req.flags = test_mask; 3017 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 3018 *test_results = resp->test_success; 3019 mutex_unlock(&bp->hwrm_cmd_lock); 3020 return rc; 3021 } 3022 3023 #define BNXT_DRV_TESTS 4 3024 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3025 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3026 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3027 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3028 3029 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3030 u64 *buf) 3031 { 3032 struct bnxt *bp = netdev_priv(dev); 3033 bool do_ext_lpbk = false; 3034 bool offline = false; 3035 u8 test_results = 0; 3036 u8 test_mask = 0; 3037 int rc = 0, i; 3038 3039 if (!bp->num_tests || !BNXT_SINGLE_PF(bp)) 3040 return; 3041 memset(buf, 0, sizeof(u64) * bp->num_tests); 3042 if (!netif_running(dev)) { 3043 etest->flags |= ETH_TEST_FL_FAILED; 3044 return; 3045 } 3046 3047 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3048 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 3049 do_ext_lpbk = true; 3050 3051 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3052 if (bp->pf.active_vfs) { 3053 etest->flags |= ETH_TEST_FL_FAILED; 3054 netdev_warn(dev, "Offline tests cannot be run with active VFs\n"); 3055 return; 3056 } 3057 offline = true; 3058 } 3059 3060 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3061 u8 bit_val = 1 << i; 3062 3063 if (!(bp->test_info->offline_mask & bit_val)) 3064 test_mask |= bit_val; 3065 else if (offline) 3066 test_mask |= bit_val; 3067 } 3068 if (!offline) { 3069 bnxt_run_fw_tests(bp, test_mask, &test_results); 3070 } else { 3071 rc = bnxt_close_nic(bp, false, false); 3072 if (rc) 3073 return; 3074 bnxt_run_fw_tests(bp, test_mask, &test_results); 3075 3076 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3077 bnxt_hwrm_mac_loopback(bp, true); 3078 msleep(250); 3079 rc = bnxt_half_open_nic(bp); 3080 if (rc) { 3081 bnxt_hwrm_mac_loopback(bp, false); 3082 etest->flags |= ETH_TEST_FL_FAILED; 3083 return; 3084 } 3085 if (bnxt_run_loopback(bp)) 3086 etest->flags |= ETH_TEST_FL_FAILED; 3087 else 3088 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3089 3090 bnxt_hwrm_mac_loopback(bp, false); 3091 bnxt_hwrm_phy_loopback(bp, true, false); 3092 msleep(1000); 3093 if (bnxt_run_loopback(bp)) { 3094 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3095 etest->flags |= ETH_TEST_FL_FAILED; 3096 } 3097 if (do_ext_lpbk) { 3098 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3099 bnxt_hwrm_phy_loopback(bp, true, true); 3100 msleep(1000); 3101 if (bnxt_run_loopback(bp)) { 3102 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3103 etest->flags |= ETH_TEST_FL_FAILED; 3104 } 3105 } 3106 bnxt_hwrm_phy_loopback(bp, false, false); 3107 bnxt_half_close_nic(bp); 3108 rc = bnxt_open_nic(bp, false, true); 3109 } 3110 if (rc || bnxt_test_irq(bp)) { 3111 buf[BNXT_IRQ_TEST_IDX] = 1; 3112 etest->flags |= ETH_TEST_FL_FAILED; 3113 } 3114 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3115 u8 bit_val = 1 << i; 3116 3117 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3118 buf[i] = 1; 3119 etest->flags |= ETH_TEST_FL_FAILED; 3120 } 3121 } 3122 } 3123 3124 static int bnxt_reset(struct net_device *dev, u32 *flags) 3125 { 3126 struct bnxt *bp = netdev_priv(dev); 3127 bool reload = false; 3128 u32 req = *flags; 3129 3130 if (!req) 3131 return -EINVAL; 3132 3133 if (!BNXT_PF(bp)) { 3134 netdev_err(dev, "Reset is not supported from a VF\n"); 3135 return -EOPNOTSUPP; 3136 } 3137 3138 if (pci_vfs_assigned(bp->pdev) && 3139 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3140 netdev_err(dev, 3141 "Reset not allowed when VFs are assigned to VMs\n"); 3142 return -EBUSY; 3143 } 3144 3145 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3146 /* This feature is not supported in older firmware versions */ 3147 if (bp->hwrm_spec_code >= 0x10803) { 3148 if (!bnxt_firmware_reset_chip(dev)) { 3149 netdev_info(dev, "Firmware reset request successful.\n"); 3150 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3151 reload = true; 3152 *flags &= ~BNXT_FW_RESET_CHIP; 3153 } 3154 } else if (req == BNXT_FW_RESET_CHIP) { 3155 return -EOPNOTSUPP; /* only request, fail hard */ 3156 } 3157 } 3158 3159 if (req & BNXT_FW_RESET_AP) { 3160 /* This feature is not supported in older firmware versions */ 3161 if (bp->hwrm_spec_code >= 0x10803) { 3162 if (!bnxt_firmware_reset_ap(dev)) { 3163 netdev_info(dev, "Reset application processor successful.\n"); 3164 reload = true; 3165 *flags &= ~BNXT_FW_RESET_AP; 3166 } 3167 } else if (req == BNXT_FW_RESET_AP) { 3168 return -EOPNOTSUPP; /* only request, fail hard */ 3169 } 3170 } 3171 3172 if (reload) 3173 netdev_info(dev, "Reload driver to complete reset\n"); 3174 3175 return 0; 3176 } 3177 3178 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3179 struct bnxt_hwrm_dbg_dma_info *info) 3180 { 3181 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3182 struct hwrm_dbg_cmn_input *cmn_req = msg; 3183 __le16 *seq_ptr = msg + info->seq_off; 3184 u16 seq = 0, len, segs_off; 3185 void *resp = cmn_resp; 3186 dma_addr_t dma_handle; 3187 int rc, off = 0; 3188 void *dma_buf; 3189 3190 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3191 GFP_KERNEL); 3192 if (!dma_buf) 3193 return -ENOMEM; 3194 3195 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3196 total_segments); 3197 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3198 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3199 mutex_lock(&bp->hwrm_cmd_lock); 3200 while (1) { 3201 *seq_ptr = cpu_to_le16(seq); 3202 rc = _hwrm_send_message(bp, msg, msg_len, 3203 HWRM_COREDUMP_TIMEOUT); 3204 if (rc) 3205 break; 3206 3207 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3208 if (!seq && 3209 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3210 info->segs = le16_to_cpu(*((__le16 *)(resp + 3211 segs_off))); 3212 if (!info->segs) { 3213 rc = -EIO; 3214 break; 3215 } 3216 3217 info->dest_buf_size = info->segs * 3218 sizeof(struct coredump_segment_record); 3219 info->dest_buf = kmalloc(info->dest_buf_size, 3220 GFP_KERNEL); 3221 if (!info->dest_buf) { 3222 rc = -ENOMEM; 3223 break; 3224 } 3225 } 3226 3227 if (info->dest_buf) { 3228 if ((info->seg_start + off + len) <= 3229 BNXT_COREDUMP_BUF_LEN(info->buf_len)) { 3230 memcpy(info->dest_buf + off, dma_buf, len); 3231 } else { 3232 rc = -ENOBUFS; 3233 break; 3234 } 3235 } 3236 3237 if (cmn_req->req_type == 3238 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3239 info->dest_buf_size += len; 3240 3241 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3242 break; 3243 3244 seq++; 3245 off += len; 3246 } 3247 mutex_unlock(&bp->hwrm_cmd_lock); 3248 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3249 return rc; 3250 } 3251 3252 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3253 struct bnxt_coredump *coredump) 3254 { 3255 struct hwrm_dbg_coredump_list_input req = {0}; 3256 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3257 int rc; 3258 3259 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3260 3261 info.dma_len = COREDUMP_LIST_BUF_LEN; 3262 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3263 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3264 data_len); 3265 3266 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3267 if (!rc) { 3268 coredump->data = info.dest_buf; 3269 coredump->data_size = info.dest_buf_size; 3270 coredump->total_segs = info.segs; 3271 } 3272 return rc; 3273 } 3274 3275 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3276 u16 segment_id) 3277 { 3278 struct hwrm_dbg_coredump_initiate_input req = {0}; 3279 3280 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3281 req.component_id = cpu_to_le16(component_id); 3282 req.segment_id = cpu_to_le16(segment_id); 3283 3284 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3285 } 3286 3287 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3288 u16 segment_id, u32 *seg_len, 3289 void *buf, u32 buf_len, u32 offset) 3290 { 3291 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3292 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3293 int rc; 3294 3295 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3296 req.component_id = cpu_to_le16(component_id); 3297 req.segment_id = cpu_to_le16(segment_id); 3298 3299 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3300 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3301 seq_no); 3302 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3303 data_len); 3304 if (buf) { 3305 info.dest_buf = buf + offset; 3306 info.buf_len = buf_len; 3307 info.seg_start = offset; 3308 } 3309 3310 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3311 if (!rc) 3312 *seg_len = info.dest_buf_size; 3313 3314 return rc; 3315 } 3316 3317 static void 3318 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3319 struct bnxt_coredump_segment_hdr *seg_hdr, 3320 struct coredump_segment_record *seg_rec, u32 seg_len, 3321 int status, u32 duration, u32 instance) 3322 { 3323 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3324 memcpy(seg_hdr->signature, "sEgM", 4); 3325 if (seg_rec) { 3326 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3327 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3328 seg_hdr->low_version = seg_rec->version_low; 3329 seg_hdr->high_version = seg_rec->version_hi; 3330 } else { 3331 /* For hwrm_ver_get response Component id = 2 3332 * and Segment id = 0 3333 */ 3334 seg_hdr->component_id = cpu_to_le32(2); 3335 seg_hdr->segment_id = 0; 3336 } 3337 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3338 seg_hdr->length = cpu_to_le32(seg_len); 3339 seg_hdr->status = cpu_to_le32(status); 3340 seg_hdr->duration = cpu_to_le32(duration); 3341 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3342 seg_hdr->instance = cpu_to_le32(instance); 3343 } 3344 3345 static void 3346 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3347 time64_t start, s16 start_utc, u16 total_segs, 3348 int status) 3349 { 3350 time64_t end = ktime_get_real_seconds(); 3351 u32 os_ver_major = 0, os_ver_minor = 0; 3352 struct tm tm; 3353 3354 time64_to_tm(start, 0, &tm); 3355 memset(record, 0, sizeof(*record)); 3356 memcpy(record->signature, "cOrE", 4); 3357 record->flags = 0; 3358 record->low_version = 0; 3359 record->high_version = 1; 3360 record->asic_state = 0; 3361 strlcpy(record->system_name, utsname()->nodename, 3362 sizeof(record->system_name)); 3363 record->year = cpu_to_le16(tm.tm_year + 1900); 3364 record->month = cpu_to_le16(tm.tm_mon + 1); 3365 record->day = cpu_to_le16(tm.tm_mday); 3366 record->hour = cpu_to_le16(tm.tm_hour); 3367 record->minute = cpu_to_le16(tm.tm_min); 3368 record->second = cpu_to_le16(tm.tm_sec); 3369 record->utc_bias = cpu_to_le16(start_utc); 3370 strcpy(record->commandline, "ethtool -w"); 3371 record->total_segments = cpu_to_le32(total_segs); 3372 3373 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3374 record->os_ver_major = cpu_to_le32(os_ver_major); 3375 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3376 3377 strlcpy(record->os_name, utsname()->sysname, 32); 3378 time64_to_tm(end, 0, &tm); 3379 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3380 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3381 record->end_day = cpu_to_le16(tm.tm_mday); 3382 record->end_hour = cpu_to_le16(tm.tm_hour); 3383 record->end_minute = cpu_to_le16(tm.tm_min); 3384 record->end_second = cpu_to_le16(tm.tm_sec); 3385 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3386 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3387 bp->ver_resp.chip_rev << 8 | 3388 bp->ver_resp.chip_metal); 3389 record->asic_id2 = 0; 3390 record->coredump_status = cpu_to_le32(status); 3391 record->ioctl_low_version = 0; 3392 record->ioctl_high_version = 0; 3393 } 3394 3395 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3396 { 3397 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3398 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0; 3399 struct coredump_segment_record *seg_record = NULL; 3400 struct bnxt_coredump_segment_hdr seg_hdr; 3401 struct bnxt_coredump coredump = {NULL}; 3402 time64_t start_time; 3403 u16 start_utc; 3404 int rc = 0, i; 3405 3406 if (buf) 3407 buf_len = *dump_len; 3408 3409 start_time = ktime_get_real_seconds(); 3410 start_utc = sys_tz.tz_minuteswest * 60; 3411 seg_hdr_len = sizeof(seg_hdr); 3412 3413 /* First segment should be hwrm_ver_get response */ 3414 *dump_len = seg_hdr_len + ver_get_resp_len; 3415 if (buf) { 3416 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3417 0, 0, 0); 3418 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3419 offset += seg_hdr_len; 3420 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3421 offset += ver_get_resp_len; 3422 } 3423 3424 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3425 if (rc) { 3426 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3427 goto err; 3428 } 3429 3430 *dump_len += seg_hdr_len * coredump.total_segs; 3431 3432 seg_record = (struct coredump_segment_record *)coredump.data; 3433 seg_record_len = sizeof(*seg_record); 3434 3435 for (i = 0; i < coredump.total_segs; i++) { 3436 u16 comp_id = le16_to_cpu(seg_record->component_id); 3437 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3438 u32 duration = 0, seg_len = 0; 3439 unsigned long start, end; 3440 3441 if (buf && ((offset + seg_hdr_len) > 3442 BNXT_COREDUMP_BUF_LEN(buf_len))) { 3443 rc = -ENOBUFS; 3444 goto err; 3445 } 3446 3447 start = jiffies; 3448 3449 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3450 if (rc) { 3451 netdev_err(bp->dev, 3452 "Failed to initiate coredump for seg = %d\n", 3453 seg_record->segment_id); 3454 goto next_seg; 3455 } 3456 3457 /* Write segment data into the buffer */ 3458 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3459 &seg_len, buf, buf_len, 3460 offset + seg_hdr_len); 3461 if (rc && rc == -ENOBUFS) 3462 goto err; 3463 else if (rc) 3464 netdev_err(bp->dev, 3465 "Failed to retrieve coredump for seg = %d\n", 3466 seg_record->segment_id); 3467 3468 next_seg: 3469 end = jiffies; 3470 duration = jiffies_to_msecs(end - start); 3471 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3472 rc, duration, 0); 3473 3474 if (buf) { 3475 /* Write segment header into the buffer */ 3476 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3477 offset += seg_hdr_len + seg_len; 3478 } 3479 3480 *dump_len += seg_len; 3481 seg_record = 3482 (struct coredump_segment_record *)((u8 *)seg_record + 3483 seg_record_len); 3484 } 3485 3486 err: 3487 if (buf) 3488 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3489 start_utc, coredump.total_segs + 1, 3490 rc); 3491 kfree(coredump.data); 3492 *dump_len += sizeof(struct bnxt_coredump_record); 3493 if (rc == -ENOBUFS) 3494 netdev_err(bp->dev, "Firmware returned large coredump buffer\n"); 3495 return rc; 3496 } 3497 3498 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3499 { 3500 struct bnxt *bp = netdev_priv(dev); 3501 3502 if (dump->flag > BNXT_DUMP_CRASH) { 3503 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3504 return -EINVAL; 3505 } 3506 3507 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3508 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3509 return -EOPNOTSUPP; 3510 } 3511 3512 bp->dump_flag = dump->flag; 3513 return 0; 3514 } 3515 3516 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3517 { 3518 struct bnxt *bp = netdev_priv(dev); 3519 3520 if (bp->hwrm_spec_code < 0x10801) 3521 return -EOPNOTSUPP; 3522 3523 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3524 bp->ver_resp.hwrm_fw_min_8b << 16 | 3525 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3526 bp->ver_resp.hwrm_fw_rsvd_8b; 3527 3528 dump->flag = bp->dump_flag; 3529 if (bp->dump_flag == BNXT_DUMP_CRASH) 3530 dump->len = BNXT_CRASH_DUMP_LEN; 3531 else 3532 bnxt_get_coredump(bp, NULL, &dump->len); 3533 return 0; 3534 } 3535 3536 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3537 void *buf) 3538 { 3539 struct bnxt *bp = netdev_priv(dev); 3540 3541 if (bp->hwrm_spec_code < 0x10801) 3542 return -EOPNOTSUPP; 3543 3544 memset(buf, 0, dump->len); 3545 3546 dump->flag = bp->dump_flag; 3547 if (dump->flag == BNXT_DUMP_CRASH) { 3548 #ifdef CONFIG_TEE_BNXT_FW 3549 return tee_bnxt_copy_coredump(buf, 0, dump->len); 3550 #endif 3551 } else { 3552 return bnxt_get_coredump(bp, buf, &dump->len); 3553 } 3554 3555 return 0; 3556 } 3557 3558 void bnxt_ethtool_init(struct bnxt *bp) 3559 { 3560 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3561 struct hwrm_selftest_qlist_input req = {0}; 3562 struct bnxt_test_info *test_info; 3563 struct net_device *dev = bp->dev; 3564 int i, rc; 3565 3566 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3567 bnxt_get_pkgver(dev); 3568 3569 bp->num_tests = 0; 3570 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp)) 3571 return; 3572 3573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3574 mutex_lock(&bp->hwrm_cmd_lock); 3575 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3576 if (rc) 3577 goto ethtool_init_exit; 3578 3579 test_info = bp->test_info; 3580 if (!test_info) 3581 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3582 if (!test_info) 3583 goto ethtool_init_exit; 3584 3585 bp->test_info = test_info; 3586 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3587 if (bp->num_tests > BNXT_MAX_TEST) 3588 bp->num_tests = BNXT_MAX_TEST; 3589 3590 test_info->offline_mask = resp->offline_tests; 3591 test_info->timeout = le16_to_cpu(resp->test_timeout); 3592 if (!test_info->timeout) 3593 test_info->timeout = HWRM_CMD_TIMEOUT; 3594 for (i = 0; i < bp->num_tests; i++) { 3595 char *str = test_info->string[i]; 3596 char *fw_str = resp->test0_name + i * 32; 3597 3598 if (i == BNXT_MACLPBK_TEST_IDX) { 3599 strcpy(str, "Mac loopback test (offline)"); 3600 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3601 strcpy(str, "Phy loopback test (offline)"); 3602 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3603 strcpy(str, "Ext loopback test (offline)"); 3604 } else if (i == BNXT_IRQ_TEST_IDX) { 3605 strcpy(str, "Interrupt_test (offline)"); 3606 } else { 3607 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3608 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3609 if (test_info->offline_mask & (1 << i)) 3610 strncat(str, " (offline)", 3611 ETH_GSTRING_LEN - strlen(str)); 3612 else 3613 strncat(str, " (online)", 3614 ETH_GSTRING_LEN - strlen(str)); 3615 } 3616 } 3617 3618 ethtool_init_exit: 3619 mutex_unlock(&bp->hwrm_cmd_lock); 3620 } 3621 3622 void bnxt_ethtool_free(struct bnxt *bp) 3623 { 3624 kfree(bp->test_info); 3625 bp->test_info = NULL; 3626 } 3627 3628 const struct ethtool_ops bnxt_ethtool_ops = { 3629 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3630 ETHTOOL_COALESCE_MAX_FRAMES | 3631 ETHTOOL_COALESCE_USECS_IRQ | 3632 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3633 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3634 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3635 .get_link_ksettings = bnxt_get_link_ksettings, 3636 .set_link_ksettings = bnxt_set_link_ksettings, 3637 .get_pauseparam = bnxt_get_pauseparam, 3638 .set_pauseparam = bnxt_set_pauseparam, 3639 .get_drvinfo = bnxt_get_drvinfo, 3640 .get_wol = bnxt_get_wol, 3641 .set_wol = bnxt_set_wol, 3642 .get_coalesce = bnxt_get_coalesce, 3643 .set_coalesce = bnxt_set_coalesce, 3644 .get_msglevel = bnxt_get_msglevel, 3645 .set_msglevel = bnxt_set_msglevel, 3646 .get_sset_count = bnxt_get_sset_count, 3647 .get_strings = bnxt_get_strings, 3648 .get_ethtool_stats = bnxt_get_ethtool_stats, 3649 .set_ringparam = bnxt_set_ringparam, 3650 .get_ringparam = bnxt_get_ringparam, 3651 .get_channels = bnxt_get_channels, 3652 .set_channels = bnxt_set_channels, 3653 .get_rxnfc = bnxt_get_rxnfc, 3654 .set_rxnfc = bnxt_set_rxnfc, 3655 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3656 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3657 .get_rxfh = bnxt_get_rxfh, 3658 .set_rxfh = bnxt_set_rxfh, 3659 .flash_device = bnxt_flash_device, 3660 .get_eeprom_len = bnxt_get_eeprom_len, 3661 .get_eeprom = bnxt_get_eeprom, 3662 .set_eeprom = bnxt_set_eeprom, 3663 .get_link = bnxt_get_link, 3664 .get_eee = bnxt_get_eee, 3665 .set_eee = bnxt_set_eee, 3666 .get_module_info = bnxt_get_module_info, 3667 .get_module_eeprom = bnxt_get_module_eeprom, 3668 .nway_reset = bnxt_nway_reset, 3669 .set_phys_id = bnxt_set_phys_id, 3670 .self_test = bnxt_self_test, 3671 .reset = bnxt_reset, 3672 .set_dump = bnxt_set_dump, 3673 .get_dump_flag = bnxt_get_dump_flag, 3674 .get_dump_data = bnxt_get_dump_data, 3675 }; 3676