1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/ethtool_netlink.h> 15 #include <linux/linkmode.h> 16 #include <linux/interrupt.h> 17 #include <linux/pci.h> 18 #include <linux/etherdevice.h> 19 #include <linux/crc32.h> 20 #include <linux/firmware.h> 21 #include <linux/utsname.h> 22 #include <linux/time.h> 23 #include <linux/ptp_clock_kernel.h> 24 #include <linux/net_tstamp.h> 25 #include <linux/timecounter.h> 26 #include "bnxt_hsi.h" 27 #include "bnxt.h" 28 #include "bnxt_hwrm.h" 29 #include "bnxt_ulp.h" 30 #include "bnxt_xdp.h" 31 #include "bnxt_ptp.h" 32 #include "bnxt_ethtool.h" 33 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 34 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 35 #include "bnxt_coredump.h" 36 37 static u32 bnxt_get_msglevel(struct net_device *dev) 38 { 39 struct bnxt *bp = netdev_priv(dev); 40 41 return bp->msg_enable; 42 } 43 44 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 45 { 46 struct bnxt *bp = netdev_priv(dev); 47 48 bp->msg_enable = value; 49 } 50 51 static int bnxt_get_coalesce(struct net_device *dev, 52 struct ethtool_coalesce *coal, 53 struct kernel_ethtool_coalesce *kernel_coal, 54 struct netlink_ext_ack *extack) 55 { 56 struct bnxt *bp = netdev_priv(dev); 57 struct bnxt_coal *hw_coal; 58 u16 mult; 59 60 memset(coal, 0, sizeof(*coal)); 61 62 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 63 64 hw_coal = &bp->rx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 if (hw_coal->flags & 71 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 72 kernel_coal->use_cqe_mode_rx = true; 73 74 hw_coal = &bp->tx_coal; 75 mult = hw_coal->bufs_per_record; 76 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 77 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 78 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 79 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 80 if (hw_coal->flags & 81 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 82 kernel_coal->use_cqe_mode_tx = true; 83 84 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 85 86 return 0; 87 } 88 89 static int bnxt_set_coalesce(struct net_device *dev, 90 struct ethtool_coalesce *coal, 91 struct kernel_ethtool_coalesce *kernel_coal, 92 struct netlink_ext_ack *extack) 93 { 94 struct bnxt *bp = netdev_priv(dev); 95 bool update_stats = false; 96 struct bnxt_coal *hw_coal; 97 int rc = 0; 98 u16 mult; 99 100 if (coal->use_adaptive_rx_coalesce) { 101 bp->flags |= BNXT_FLAG_DIM; 102 } else { 103 if (bp->flags & BNXT_FLAG_DIM) { 104 bp->flags &= ~(BNXT_FLAG_DIM); 105 goto reset_coalesce; 106 } 107 } 108 109 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 110 !(bp->coal_cap.cmpl_params & 111 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 112 return -EOPNOTSUPP; 113 114 hw_coal = &bp->rx_coal; 115 mult = hw_coal->bufs_per_record; 116 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 117 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 118 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 119 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 120 hw_coal->flags &= 121 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 122 if (kernel_coal->use_cqe_mode_rx) 123 hw_coal->flags |= 124 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 125 126 hw_coal = &bp->tx_coal; 127 mult = hw_coal->bufs_per_record; 128 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 129 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 130 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 131 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 132 hw_coal->flags &= 133 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 if (kernel_coal->use_cqe_mode_tx) 135 hw_coal->flags |= 136 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 137 138 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 139 u32 stats_ticks = coal->stats_block_coalesce_usecs; 140 141 /* Allow 0, which means disable. */ 142 if (stats_ticks) 143 stats_ticks = clamp_t(u32, stats_ticks, 144 BNXT_MIN_STATS_COAL_TICKS, 145 BNXT_MAX_STATS_COAL_TICKS); 146 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 147 bp->stats_coal_ticks = stats_ticks; 148 if (bp->stats_coal_ticks) 149 bp->current_interval = 150 bp->stats_coal_ticks * HZ / 1000000; 151 else 152 bp->current_interval = BNXT_TIMER_INTERVAL; 153 update_stats = true; 154 } 155 156 reset_coalesce: 157 if (netif_running(dev)) { 158 if (update_stats) { 159 rc = bnxt_close_nic(bp, true, false); 160 if (!rc) 161 rc = bnxt_open_nic(bp, true, false); 162 } else { 163 rc = bnxt_hwrm_set_coal(bp); 164 } 165 } 166 167 return rc; 168 } 169 170 static const char * const bnxt_ring_rx_stats_str[] = { 171 "rx_ucast_packets", 172 "rx_mcast_packets", 173 "rx_bcast_packets", 174 "rx_discards", 175 "rx_errors", 176 "rx_ucast_bytes", 177 "rx_mcast_bytes", 178 "rx_bcast_bytes", 179 }; 180 181 static const char * const bnxt_ring_tx_stats_str[] = { 182 "tx_ucast_packets", 183 "tx_mcast_packets", 184 "tx_bcast_packets", 185 "tx_errors", 186 "tx_discards", 187 "tx_ucast_bytes", 188 "tx_mcast_bytes", 189 "tx_bcast_bytes", 190 }; 191 192 static const char * const bnxt_ring_tpa_stats_str[] = { 193 "tpa_packets", 194 "tpa_bytes", 195 "tpa_events", 196 "tpa_aborts", 197 }; 198 199 static const char * const bnxt_ring_tpa2_stats_str[] = { 200 "rx_tpa_eligible_pkt", 201 "rx_tpa_eligible_bytes", 202 "rx_tpa_pkt", 203 "rx_tpa_bytes", 204 "rx_tpa_errors", 205 "rx_tpa_events", 206 }; 207 208 static const char * const bnxt_rx_sw_stats_str[] = { 209 "rx_l4_csum_errors", 210 "rx_resets", 211 "rx_buf_errors", 212 }; 213 214 static const char * const bnxt_cmn_sw_stats_str[] = { 215 "missed_irqs", 216 }; 217 218 #define BNXT_RX_STATS_ENTRY(counter) \ 219 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 220 221 #define BNXT_TX_STATS_ENTRY(counter) \ 222 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 223 224 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 225 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 226 227 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 228 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 229 230 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 231 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 232 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 233 234 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 235 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 236 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 237 238 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 239 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 240 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 241 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 242 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 243 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 244 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 245 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 246 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 247 248 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 249 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 250 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 251 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 252 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 253 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 254 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 255 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 256 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 257 258 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 259 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 260 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 261 262 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 263 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 264 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 265 266 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 267 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 268 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 269 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 270 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 271 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 272 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 273 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 274 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 275 276 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 277 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 278 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 279 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 280 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 281 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 282 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 283 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 284 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 285 286 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 287 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 288 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 289 290 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 291 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 292 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 293 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 294 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 295 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 296 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 297 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 298 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 299 300 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 301 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 302 __stringify(counter##_pri##n) } 303 304 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 305 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 306 __stringify(counter##_pri##n) } 307 308 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 309 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 310 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 311 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 312 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 313 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 314 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 315 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 316 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 317 318 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 319 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 320 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 321 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 322 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 323 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 324 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 325 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 326 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 327 328 enum { 329 RX_TOTAL_DISCARDS, 330 TX_TOTAL_DISCARDS, 331 RX_NETPOLL_DISCARDS, 332 }; 333 334 static struct { 335 u64 counter; 336 char string[ETH_GSTRING_LEN]; 337 } bnxt_sw_func_stats[] = { 338 {0, "rx_total_discard_pkts"}, 339 {0, "tx_total_discard_pkts"}, 340 {0, "rx_total_netpoll_discards"}, 341 }; 342 343 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 344 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 345 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 346 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 347 348 static const struct { 349 long offset; 350 char string[ETH_GSTRING_LEN]; 351 } bnxt_port_stats_arr[] = { 352 BNXT_RX_STATS_ENTRY(rx_64b_frames), 353 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 354 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 355 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 356 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 357 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 358 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 359 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 360 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 361 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 362 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 363 BNXT_RX_STATS_ENTRY(rx_total_frames), 364 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 365 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 366 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 367 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 368 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 369 BNXT_RX_STATS_ENTRY(rx_pause_frames), 370 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 371 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 372 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 373 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 374 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 375 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 376 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 377 BNXT_RX_STATS_ENTRY(rx_good_frames), 378 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 379 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 380 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 381 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 382 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 383 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 384 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 385 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 386 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 387 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 388 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 389 BNXT_RX_STATS_ENTRY(rx_bytes), 390 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 391 BNXT_RX_STATS_ENTRY(rx_runt_frames), 392 BNXT_RX_STATS_ENTRY(rx_stat_discard), 393 BNXT_RX_STATS_ENTRY(rx_stat_err), 394 395 BNXT_TX_STATS_ENTRY(tx_64b_frames), 396 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 397 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 398 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 399 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 400 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 401 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 402 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 403 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 404 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 405 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 406 BNXT_TX_STATS_ENTRY(tx_good_frames), 407 BNXT_TX_STATS_ENTRY(tx_total_frames), 408 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 409 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 410 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 411 BNXT_TX_STATS_ENTRY(tx_pause_frames), 412 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 413 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 414 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 415 BNXT_TX_STATS_ENTRY(tx_err), 416 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 417 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 418 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 419 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 420 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 421 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 422 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 423 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 424 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 425 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 426 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 427 BNXT_TX_STATS_ENTRY(tx_total_collisions), 428 BNXT_TX_STATS_ENTRY(tx_bytes), 429 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 430 BNXT_TX_STATS_ENTRY(tx_stat_discard), 431 BNXT_TX_STATS_ENTRY(tx_stat_error), 432 }; 433 434 static const struct { 435 long offset; 436 char string[ETH_GSTRING_LEN]; 437 } bnxt_port_stats_ext_arr[] = { 438 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 439 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 440 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 441 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 442 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 443 BNXT_RX_STATS_EXT_COS_ENTRIES, 444 BNXT_RX_STATS_EXT_PFC_ENTRIES, 445 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 446 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 447 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 448 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 449 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 450 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 451 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 452 }; 453 454 static const struct { 455 long offset; 456 char string[ETH_GSTRING_LEN]; 457 } bnxt_tx_port_stats_ext_arr[] = { 458 BNXT_TX_STATS_EXT_COS_ENTRIES, 459 BNXT_TX_STATS_EXT_PFC_ENTRIES, 460 }; 461 462 static const struct { 463 long base_off; 464 char string[ETH_GSTRING_LEN]; 465 } bnxt_rx_bytes_pri_arr[] = { 466 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 467 }; 468 469 static const struct { 470 long base_off; 471 char string[ETH_GSTRING_LEN]; 472 } bnxt_rx_pkts_pri_arr[] = { 473 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 474 }; 475 476 static const struct { 477 long base_off; 478 char string[ETH_GSTRING_LEN]; 479 } bnxt_tx_bytes_pri_arr[] = { 480 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 481 }; 482 483 static const struct { 484 long base_off; 485 char string[ETH_GSTRING_LEN]; 486 } bnxt_tx_pkts_pri_arr[] = { 487 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 488 }; 489 490 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 491 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 492 #define BNXT_NUM_STATS_PRI \ 493 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 494 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 495 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 496 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 497 498 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 499 { 500 if (BNXT_SUPPORTS_TPA(bp)) { 501 if (bp->max_tpa_v2) { 502 if (BNXT_CHIP_P5_THOR(bp)) 503 return BNXT_NUM_TPA_RING_STATS_P5; 504 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 505 } 506 return BNXT_NUM_TPA_RING_STATS; 507 } 508 return 0; 509 } 510 511 static int bnxt_get_num_ring_stats(struct bnxt *bp) 512 { 513 int rx, tx, cmn; 514 515 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 516 bnxt_get_num_tpa_ring_stats(bp); 517 tx = NUM_RING_TX_HW_STATS; 518 cmn = NUM_RING_CMN_SW_STATS; 519 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 520 cmn * bp->cp_nr_rings; 521 } 522 523 static int bnxt_get_num_stats(struct bnxt *bp) 524 { 525 int num_stats = bnxt_get_num_ring_stats(bp); 526 527 num_stats += BNXT_NUM_SW_FUNC_STATS; 528 529 if (bp->flags & BNXT_FLAG_PORT_STATS) 530 num_stats += BNXT_NUM_PORT_STATS; 531 532 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 533 num_stats += bp->fw_rx_stats_ext_size + 534 bp->fw_tx_stats_ext_size; 535 if (bp->pri2cos_valid) 536 num_stats += BNXT_NUM_STATS_PRI; 537 } 538 539 return num_stats; 540 } 541 542 static int bnxt_get_sset_count(struct net_device *dev, int sset) 543 { 544 struct bnxt *bp = netdev_priv(dev); 545 546 switch (sset) { 547 case ETH_SS_STATS: 548 return bnxt_get_num_stats(bp); 549 case ETH_SS_TEST: 550 if (!bp->num_tests) 551 return -EOPNOTSUPP; 552 return bp->num_tests; 553 default: 554 return -EOPNOTSUPP; 555 } 556 } 557 558 static bool is_rx_ring(struct bnxt *bp, int ring_num) 559 { 560 return ring_num < bp->rx_nr_rings; 561 } 562 563 static bool is_tx_ring(struct bnxt *bp, int ring_num) 564 { 565 int tx_base = 0; 566 567 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 568 tx_base = bp->rx_nr_rings; 569 570 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 571 return true; 572 return false; 573 } 574 575 static void bnxt_get_ethtool_stats(struct net_device *dev, 576 struct ethtool_stats *stats, u64 *buf) 577 { 578 u32 i, j = 0; 579 struct bnxt *bp = netdev_priv(dev); 580 u32 tpa_stats; 581 582 if (!bp->bnapi) { 583 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 584 goto skip_ring_stats; 585 } 586 587 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 588 bnxt_sw_func_stats[i].counter = 0; 589 590 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 591 for (i = 0; i < bp->cp_nr_rings; i++) { 592 struct bnxt_napi *bnapi = bp->bnapi[i]; 593 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 594 u64 *sw_stats = cpr->stats.sw_stats; 595 u64 *sw; 596 int k; 597 598 if (is_rx_ring(bp, i)) { 599 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 600 buf[j] = sw_stats[k]; 601 } 602 if (is_tx_ring(bp, i)) { 603 k = NUM_RING_RX_HW_STATS; 604 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 605 j++, k++) 606 buf[j] = sw_stats[k]; 607 } 608 if (!tpa_stats || !is_rx_ring(bp, i)) 609 goto skip_tpa_ring_stats; 610 611 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 612 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 613 tpa_stats; j++, k++) 614 buf[j] = sw_stats[k]; 615 616 skip_tpa_ring_stats: 617 sw = (u64 *)&cpr->sw_stats.rx; 618 if (is_rx_ring(bp, i)) { 619 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 620 buf[j] = sw[k]; 621 } 622 623 sw = (u64 *)&cpr->sw_stats.cmn; 624 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 625 buf[j] = sw[k]; 626 627 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 628 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts); 629 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 630 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts); 631 bnxt_sw_func_stats[RX_NETPOLL_DISCARDS].counter += 632 cpr->sw_stats.rx.rx_netpoll_discards; 633 } 634 635 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 636 buf[j] = bnxt_sw_func_stats[i].counter; 637 638 skip_ring_stats: 639 if (bp->flags & BNXT_FLAG_PORT_STATS) { 640 u64 *port_stats = bp->port_stats.sw_stats; 641 642 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 643 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 644 } 645 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 646 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 647 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 648 649 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 650 buf[j] = *(rx_port_stats_ext + 651 bnxt_port_stats_ext_arr[i].offset); 652 } 653 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 654 buf[j] = *(tx_port_stats_ext + 655 bnxt_tx_port_stats_ext_arr[i].offset); 656 } 657 if (bp->pri2cos_valid) { 658 for (i = 0; i < 8; i++, j++) { 659 long n = bnxt_rx_bytes_pri_arr[i].base_off + 660 bp->pri2cos_idx[i]; 661 662 buf[j] = *(rx_port_stats_ext + n); 663 } 664 for (i = 0; i < 8; i++, j++) { 665 long n = bnxt_rx_pkts_pri_arr[i].base_off + 666 bp->pri2cos_idx[i]; 667 668 buf[j] = *(rx_port_stats_ext + n); 669 } 670 for (i = 0; i < 8; i++, j++) { 671 long n = bnxt_tx_bytes_pri_arr[i].base_off + 672 bp->pri2cos_idx[i]; 673 674 buf[j] = *(tx_port_stats_ext + n); 675 } 676 for (i = 0; i < 8; i++, j++) { 677 long n = bnxt_tx_pkts_pri_arr[i].base_off + 678 bp->pri2cos_idx[i]; 679 680 buf[j] = *(tx_port_stats_ext + n); 681 } 682 } 683 } 684 } 685 686 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 687 { 688 struct bnxt *bp = netdev_priv(dev); 689 static const char * const *str; 690 u32 i, j, num_str; 691 692 switch (stringset) { 693 case ETH_SS_STATS: 694 for (i = 0; i < bp->cp_nr_rings; i++) { 695 if (is_rx_ring(bp, i)) { 696 num_str = NUM_RING_RX_HW_STATS; 697 for (j = 0; j < num_str; j++) { 698 sprintf(buf, "[%d]: %s", i, 699 bnxt_ring_rx_stats_str[j]); 700 buf += ETH_GSTRING_LEN; 701 } 702 } 703 if (is_tx_ring(bp, i)) { 704 num_str = NUM_RING_TX_HW_STATS; 705 for (j = 0; j < num_str; j++) { 706 sprintf(buf, "[%d]: %s", i, 707 bnxt_ring_tx_stats_str[j]); 708 buf += ETH_GSTRING_LEN; 709 } 710 } 711 num_str = bnxt_get_num_tpa_ring_stats(bp); 712 if (!num_str || !is_rx_ring(bp, i)) 713 goto skip_tpa_stats; 714 715 if (bp->max_tpa_v2) 716 str = bnxt_ring_tpa2_stats_str; 717 else 718 str = bnxt_ring_tpa_stats_str; 719 720 for (j = 0; j < num_str; j++) { 721 sprintf(buf, "[%d]: %s", i, str[j]); 722 buf += ETH_GSTRING_LEN; 723 } 724 skip_tpa_stats: 725 if (is_rx_ring(bp, i)) { 726 num_str = NUM_RING_RX_SW_STATS; 727 for (j = 0; j < num_str; j++) { 728 sprintf(buf, "[%d]: %s", i, 729 bnxt_rx_sw_stats_str[j]); 730 buf += ETH_GSTRING_LEN; 731 } 732 } 733 num_str = NUM_RING_CMN_SW_STATS; 734 for (j = 0; j < num_str; j++) { 735 sprintf(buf, "[%d]: %s", i, 736 bnxt_cmn_sw_stats_str[j]); 737 buf += ETH_GSTRING_LEN; 738 } 739 } 740 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 741 strcpy(buf, bnxt_sw_func_stats[i].string); 742 buf += ETH_GSTRING_LEN; 743 } 744 745 if (bp->flags & BNXT_FLAG_PORT_STATS) { 746 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 747 strcpy(buf, bnxt_port_stats_arr[i].string); 748 buf += ETH_GSTRING_LEN; 749 } 750 } 751 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 752 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 753 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 754 buf += ETH_GSTRING_LEN; 755 } 756 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 757 strcpy(buf, 758 bnxt_tx_port_stats_ext_arr[i].string); 759 buf += ETH_GSTRING_LEN; 760 } 761 if (bp->pri2cos_valid) { 762 for (i = 0; i < 8; i++) { 763 strcpy(buf, 764 bnxt_rx_bytes_pri_arr[i].string); 765 buf += ETH_GSTRING_LEN; 766 } 767 for (i = 0; i < 8; i++) { 768 strcpy(buf, 769 bnxt_rx_pkts_pri_arr[i].string); 770 buf += ETH_GSTRING_LEN; 771 } 772 for (i = 0; i < 8; i++) { 773 strcpy(buf, 774 bnxt_tx_bytes_pri_arr[i].string); 775 buf += ETH_GSTRING_LEN; 776 } 777 for (i = 0; i < 8; i++) { 778 strcpy(buf, 779 bnxt_tx_pkts_pri_arr[i].string); 780 buf += ETH_GSTRING_LEN; 781 } 782 } 783 } 784 break; 785 case ETH_SS_TEST: 786 if (bp->num_tests) 787 memcpy(buf, bp->test_info->string, 788 bp->num_tests * ETH_GSTRING_LEN); 789 break; 790 default: 791 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 792 stringset); 793 break; 794 } 795 } 796 797 static void bnxt_get_ringparam(struct net_device *dev, 798 struct ethtool_ringparam *ering, 799 struct kernel_ethtool_ringparam *kernel_ering, 800 struct netlink_ext_ack *extack) 801 { 802 struct bnxt *bp = netdev_priv(dev); 803 804 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 805 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 806 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 807 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 808 } else { 809 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 810 ering->rx_jumbo_max_pending = 0; 811 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 812 } 813 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 814 815 ering->rx_pending = bp->rx_ring_size; 816 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 817 ering->tx_pending = bp->tx_ring_size; 818 } 819 820 static int bnxt_set_ringparam(struct net_device *dev, 821 struct ethtool_ringparam *ering, 822 struct kernel_ethtool_ringparam *kernel_ering, 823 struct netlink_ext_ack *extack) 824 { 825 struct bnxt *bp = netdev_priv(dev); 826 827 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 828 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 829 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 830 return -EINVAL; 831 832 if (netif_running(dev)) 833 bnxt_close_nic(bp, false, false); 834 835 bp->rx_ring_size = ering->rx_pending; 836 bp->tx_ring_size = ering->tx_pending; 837 bnxt_set_ring_params(bp); 838 839 if (netif_running(dev)) 840 return bnxt_open_nic(bp, false, false); 841 842 return 0; 843 } 844 845 static void bnxt_get_channels(struct net_device *dev, 846 struct ethtool_channels *channel) 847 { 848 struct bnxt *bp = netdev_priv(dev); 849 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 850 int max_rx_rings, max_tx_rings, tcs; 851 int max_tx_sch_inputs, tx_grps; 852 853 /* Get the most up-to-date max_tx_sch_inputs. */ 854 if (netif_running(dev) && BNXT_NEW_RM(bp)) 855 bnxt_hwrm_func_resc_qcaps(bp, false); 856 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 857 858 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 859 if (max_tx_sch_inputs) 860 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 861 862 tcs = netdev_get_num_tc(dev); 863 tx_grps = max(tcs, 1); 864 if (bp->tx_nr_rings_xdp) 865 tx_grps++; 866 max_tx_rings /= tx_grps; 867 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 868 869 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 870 max_rx_rings = 0; 871 max_tx_rings = 0; 872 } 873 if (max_tx_sch_inputs) 874 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 875 876 if (tcs > 1) 877 max_tx_rings /= tcs; 878 879 channel->max_rx = max_rx_rings; 880 channel->max_tx = max_tx_rings; 881 channel->max_other = 0; 882 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 883 channel->combined_count = bp->rx_nr_rings; 884 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 885 channel->combined_count--; 886 } else { 887 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 888 channel->rx_count = bp->rx_nr_rings; 889 channel->tx_count = bp->tx_nr_rings_per_tc; 890 } 891 } 892 } 893 894 static int bnxt_set_channels(struct net_device *dev, 895 struct ethtool_channels *channel) 896 { 897 struct bnxt *bp = netdev_priv(dev); 898 int req_tx_rings, req_rx_rings, tcs; 899 bool sh = false; 900 int tx_xdp = 0; 901 int rc = 0; 902 903 if (channel->other_count) 904 return -EINVAL; 905 906 if (!channel->combined_count && 907 (!channel->rx_count || !channel->tx_count)) 908 return -EINVAL; 909 910 if (channel->combined_count && 911 (channel->rx_count || channel->tx_count)) 912 return -EINVAL; 913 914 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 915 channel->tx_count)) 916 return -EINVAL; 917 918 if (channel->combined_count) 919 sh = true; 920 921 tcs = netdev_get_num_tc(dev); 922 923 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 924 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 925 if (bp->tx_nr_rings_xdp) { 926 if (!sh) { 927 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 928 return -EINVAL; 929 } 930 tx_xdp = req_rx_rings; 931 } 932 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 933 if (rc) { 934 netdev_warn(dev, "Unable to allocate the requested rings\n"); 935 return rc; 936 } 937 938 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 939 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 940 netif_is_rxfh_configured(dev)) { 941 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 942 return -EINVAL; 943 } 944 945 if (netif_running(dev)) { 946 if (BNXT_PF(bp)) { 947 /* TODO CHIMP_FW: Send message to all VF's 948 * before PF unload 949 */ 950 } 951 rc = bnxt_close_nic(bp, true, false); 952 if (rc) { 953 netdev_err(bp->dev, "Set channel failure rc :%x\n", 954 rc); 955 return rc; 956 } 957 } 958 959 if (sh) { 960 bp->flags |= BNXT_FLAG_SHARED_RINGS; 961 bp->rx_nr_rings = channel->combined_count; 962 bp->tx_nr_rings_per_tc = channel->combined_count; 963 } else { 964 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 965 bp->rx_nr_rings = channel->rx_count; 966 bp->tx_nr_rings_per_tc = channel->tx_count; 967 } 968 bp->tx_nr_rings_xdp = tx_xdp; 969 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 970 if (tcs > 1) 971 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 972 973 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 974 bp->tx_nr_rings + bp->rx_nr_rings; 975 976 /* After changing number of rx channels, update NTUPLE feature. */ 977 netdev_update_features(dev); 978 if (netif_running(dev)) { 979 rc = bnxt_open_nic(bp, true, false); 980 if ((!rc) && BNXT_PF(bp)) { 981 /* TODO CHIMP_FW: Send message to all VF's 982 * to renable 983 */ 984 } 985 } else { 986 rc = bnxt_reserve_rings(bp, true); 987 } 988 989 return rc; 990 } 991 992 #ifdef CONFIG_RFS_ACCEL 993 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 994 u32 *rule_locs) 995 { 996 int i, j = 0; 997 998 cmd->data = bp->ntp_fltr_count; 999 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1000 struct hlist_head *head; 1001 struct bnxt_ntuple_filter *fltr; 1002 1003 head = &bp->ntp_fltr_hash_tbl[i]; 1004 rcu_read_lock(); 1005 hlist_for_each_entry_rcu(fltr, head, hash) { 1006 if (j == cmd->rule_cnt) 1007 break; 1008 rule_locs[j++] = fltr->sw_id; 1009 } 1010 rcu_read_unlock(); 1011 if (j == cmd->rule_cnt) 1012 break; 1013 } 1014 cmd->rule_cnt = j; 1015 return 0; 1016 } 1017 1018 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1019 { 1020 struct ethtool_rx_flow_spec *fs = 1021 (struct ethtool_rx_flow_spec *)&cmd->fs; 1022 struct bnxt_ntuple_filter *fltr; 1023 struct flow_keys *fkeys; 1024 int i, rc = -EINVAL; 1025 1026 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1027 return rc; 1028 1029 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1030 struct hlist_head *head; 1031 1032 head = &bp->ntp_fltr_hash_tbl[i]; 1033 rcu_read_lock(); 1034 hlist_for_each_entry_rcu(fltr, head, hash) { 1035 if (fltr->sw_id == fs->location) 1036 goto fltr_found; 1037 } 1038 rcu_read_unlock(); 1039 } 1040 return rc; 1041 1042 fltr_found: 1043 fkeys = &fltr->fkeys; 1044 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1045 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1046 fs->flow_type = TCP_V4_FLOW; 1047 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1048 fs->flow_type = UDP_V4_FLOW; 1049 else 1050 goto fltr_err; 1051 1052 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1053 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1054 1055 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1056 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1057 1058 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1059 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1060 1061 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1062 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1063 } else { 1064 int i; 1065 1066 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1067 fs->flow_type = TCP_V6_FLOW; 1068 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1069 fs->flow_type = UDP_V6_FLOW; 1070 else 1071 goto fltr_err; 1072 1073 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1074 fkeys->addrs.v6addrs.src; 1075 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1076 fkeys->addrs.v6addrs.dst; 1077 for (i = 0; i < 4; i++) { 1078 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1079 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1080 } 1081 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1082 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1083 1084 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1085 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1086 } 1087 1088 fs->ring_cookie = fltr->rxq; 1089 rc = 0; 1090 1091 fltr_err: 1092 rcu_read_unlock(); 1093 1094 return rc; 1095 } 1096 #endif 1097 1098 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1099 { 1100 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1101 return RXH_IP_SRC | RXH_IP_DST; 1102 return 0; 1103 } 1104 1105 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1106 { 1107 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1108 return RXH_IP_SRC | RXH_IP_DST; 1109 return 0; 1110 } 1111 1112 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1113 { 1114 cmd->data = 0; 1115 switch (cmd->flow_type) { 1116 case TCP_V4_FLOW: 1117 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1118 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1119 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1120 cmd->data |= get_ethtool_ipv4_rss(bp); 1121 break; 1122 case UDP_V4_FLOW: 1123 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1124 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1125 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1126 fallthrough; 1127 case SCTP_V4_FLOW: 1128 case AH_ESP_V4_FLOW: 1129 case AH_V4_FLOW: 1130 case ESP_V4_FLOW: 1131 case IPV4_FLOW: 1132 cmd->data |= get_ethtool_ipv4_rss(bp); 1133 break; 1134 1135 case TCP_V6_FLOW: 1136 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1137 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1138 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1139 cmd->data |= get_ethtool_ipv6_rss(bp); 1140 break; 1141 case UDP_V6_FLOW: 1142 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1143 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1144 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1145 fallthrough; 1146 case SCTP_V6_FLOW: 1147 case AH_ESP_V6_FLOW: 1148 case AH_V6_FLOW: 1149 case ESP_V6_FLOW: 1150 case IPV6_FLOW: 1151 cmd->data |= get_ethtool_ipv6_rss(bp); 1152 break; 1153 } 1154 return 0; 1155 } 1156 1157 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1158 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1159 1160 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1161 { 1162 u32 rss_hash_cfg = bp->rss_hash_cfg; 1163 int tuple, rc = 0; 1164 1165 if (cmd->data == RXH_4TUPLE) 1166 tuple = 4; 1167 else if (cmd->data == RXH_2TUPLE) 1168 tuple = 2; 1169 else if (!cmd->data) 1170 tuple = 0; 1171 else 1172 return -EINVAL; 1173 1174 if (cmd->flow_type == TCP_V4_FLOW) { 1175 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1176 if (tuple == 4) 1177 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1178 } else if (cmd->flow_type == UDP_V4_FLOW) { 1179 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1180 return -EINVAL; 1181 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1182 if (tuple == 4) 1183 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1184 } else if (cmd->flow_type == TCP_V6_FLOW) { 1185 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1186 if (tuple == 4) 1187 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1188 } else if (cmd->flow_type == UDP_V6_FLOW) { 1189 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1190 return -EINVAL; 1191 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1192 if (tuple == 4) 1193 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1194 } else if (tuple == 4) { 1195 return -EINVAL; 1196 } 1197 1198 switch (cmd->flow_type) { 1199 case TCP_V4_FLOW: 1200 case UDP_V4_FLOW: 1201 case SCTP_V4_FLOW: 1202 case AH_ESP_V4_FLOW: 1203 case AH_V4_FLOW: 1204 case ESP_V4_FLOW: 1205 case IPV4_FLOW: 1206 if (tuple == 2) 1207 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1208 else if (!tuple) 1209 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1210 break; 1211 1212 case TCP_V6_FLOW: 1213 case UDP_V6_FLOW: 1214 case SCTP_V6_FLOW: 1215 case AH_ESP_V6_FLOW: 1216 case AH_V6_FLOW: 1217 case ESP_V6_FLOW: 1218 case IPV6_FLOW: 1219 if (tuple == 2) 1220 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1221 else if (!tuple) 1222 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1223 break; 1224 } 1225 1226 if (bp->rss_hash_cfg == rss_hash_cfg) 1227 return 0; 1228 1229 bp->rss_hash_cfg = rss_hash_cfg; 1230 if (netif_running(bp->dev)) { 1231 bnxt_close_nic(bp, false, false); 1232 rc = bnxt_open_nic(bp, false, false); 1233 } 1234 return rc; 1235 } 1236 1237 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1238 u32 *rule_locs) 1239 { 1240 struct bnxt *bp = netdev_priv(dev); 1241 int rc = 0; 1242 1243 switch (cmd->cmd) { 1244 #ifdef CONFIG_RFS_ACCEL 1245 case ETHTOOL_GRXRINGS: 1246 cmd->data = bp->rx_nr_rings; 1247 break; 1248 1249 case ETHTOOL_GRXCLSRLCNT: 1250 cmd->rule_cnt = bp->ntp_fltr_count; 1251 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1252 break; 1253 1254 case ETHTOOL_GRXCLSRLALL: 1255 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1256 break; 1257 1258 case ETHTOOL_GRXCLSRULE: 1259 rc = bnxt_grxclsrule(bp, cmd); 1260 break; 1261 #endif 1262 1263 case ETHTOOL_GRXFH: 1264 rc = bnxt_grxfh(bp, cmd); 1265 break; 1266 1267 default: 1268 rc = -EOPNOTSUPP; 1269 break; 1270 } 1271 1272 return rc; 1273 } 1274 1275 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1276 { 1277 struct bnxt *bp = netdev_priv(dev); 1278 int rc; 1279 1280 switch (cmd->cmd) { 1281 case ETHTOOL_SRXFH: 1282 rc = bnxt_srxfh(bp, cmd); 1283 break; 1284 1285 default: 1286 rc = -EOPNOTSUPP; 1287 break; 1288 } 1289 return rc; 1290 } 1291 1292 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1293 { 1294 struct bnxt *bp = netdev_priv(dev); 1295 1296 if (bp->flags & BNXT_FLAG_CHIP_P5) 1297 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1298 return HW_HASH_INDEX_SIZE; 1299 } 1300 1301 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1302 { 1303 return HW_HASH_KEY_SIZE; 1304 } 1305 1306 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1307 u8 *hfunc) 1308 { 1309 struct bnxt *bp = netdev_priv(dev); 1310 struct bnxt_vnic_info *vnic; 1311 u32 i, tbl_size; 1312 1313 if (hfunc) 1314 *hfunc = ETH_RSS_HASH_TOP; 1315 1316 if (!bp->vnic_info) 1317 return 0; 1318 1319 vnic = &bp->vnic_info[0]; 1320 if (indir && bp->rss_indir_tbl) { 1321 tbl_size = bnxt_get_rxfh_indir_size(dev); 1322 for (i = 0; i < tbl_size; i++) 1323 indir[i] = bp->rss_indir_tbl[i]; 1324 } 1325 1326 if (key && vnic->rss_hash_key) 1327 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1328 1329 return 0; 1330 } 1331 1332 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1333 const u8 *key, const u8 hfunc) 1334 { 1335 struct bnxt *bp = netdev_priv(dev); 1336 int rc = 0; 1337 1338 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1339 return -EOPNOTSUPP; 1340 1341 if (key) 1342 return -EOPNOTSUPP; 1343 1344 if (indir) { 1345 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1346 1347 for (i = 0; i < tbl_size; i++) 1348 bp->rss_indir_tbl[i] = indir[i]; 1349 pad = bp->rss_indir_tbl_entries - tbl_size; 1350 if (pad) 1351 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1352 } 1353 1354 if (netif_running(bp->dev)) { 1355 bnxt_close_nic(bp, false, false); 1356 rc = bnxt_open_nic(bp, false, false); 1357 } 1358 return rc; 1359 } 1360 1361 static void bnxt_get_drvinfo(struct net_device *dev, 1362 struct ethtool_drvinfo *info) 1363 { 1364 struct bnxt *bp = netdev_priv(dev); 1365 1366 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1367 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1368 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1369 info->n_stats = bnxt_get_num_stats(bp); 1370 info->testinfo_len = bp->num_tests; 1371 /* TODO CHIMP_FW: eeprom dump details */ 1372 info->eedump_len = 0; 1373 /* TODO CHIMP FW: reg dump details */ 1374 info->regdump_len = 0; 1375 } 1376 1377 static int bnxt_get_regs_len(struct net_device *dev) 1378 { 1379 struct bnxt *bp = netdev_priv(dev); 1380 int reg_len; 1381 1382 if (!BNXT_PF(bp)) 1383 return -EOPNOTSUPP; 1384 1385 reg_len = BNXT_PXP_REG_LEN; 1386 1387 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1388 reg_len += sizeof(struct pcie_ctx_hw_stats); 1389 1390 return reg_len; 1391 } 1392 1393 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1394 void *_p) 1395 { 1396 struct pcie_ctx_hw_stats *hw_pcie_stats; 1397 struct hwrm_pcie_qstats_input *req; 1398 struct bnxt *bp = netdev_priv(dev); 1399 dma_addr_t hw_pcie_stats_addr; 1400 int rc; 1401 1402 regs->version = 0; 1403 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1404 1405 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1406 return; 1407 1408 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1409 return; 1410 1411 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1412 &hw_pcie_stats_addr); 1413 if (!hw_pcie_stats) { 1414 hwrm_req_drop(bp, req); 1415 return; 1416 } 1417 1418 regs->version = 1; 1419 hwrm_req_hold(bp, req); /* hold on to slice */ 1420 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1421 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1422 rc = hwrm_req_send(bp, req); 1423 if (!rc) { 1424 __le64 *src = (__le64 *)hw_pcie_stats; 1425 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1426 int i; 1427 1428 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1429 dst[i] = le64_to_cpu(src[i]); 1430 } 1431 hwrm_req_drop(bp, req); 1432 } 1433 1434 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1435 { 1436 struct bnxt *bp = netdev_priv(dev); 1437 1438 wol->supported = 0; 1439 wol->wolopts = 0; 1440 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1441 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1442 wol->supported = WAKE_MAGIC; 1443 if (bp->wol) 1444 wol->wolopts = WAKE_MAGIC; 1445 } 1446 } 1447 1448 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1449 { 1450 struct bnxt *bp = netdev_priv(dev); 1451 1452 if (wol->wolopts & ~WAKE_MAGIC) 1453 return -EINVAL; 1454 1455 if (wol->wolopts & WAKE_MAGIC) { 1456 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1457 return -EINVAL; 1458 if (!bp->wol) { 1459 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1460 return -EBUSY; 1461 bp->wol = 1; 1462 } 1463 } else { 1464 if (bp->wol) { 1465 if (bnxt_hwrm_free_wol_fltr(bp)) 1466 return -EBUSY; 1467 bp->wol = 0; 1468 } 1469 } 1470 return 0; 1471 } 1472 1473 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1474 { 1475 u32 speed_mask = 0; 1476 1477 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1478 /* set the advertised speeds */ 1479 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1480 speed_mask |= ADVERTISED_100baseT_Full; 1481 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1482 speed_mask |= ADVERTISED_1000baseT_Full; 1483 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1484 speed_mask |= ADVERTISED_2500baseX_Full; 1485 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1486 speed_mask |= ADVERTISED_10000baseT_Full; 1487 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1488 speed_mask |= ADVERTISED_40000baseCR4_Full; 1489 1490 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1491 speed_mask |= ADVERTISED_Pause; 1492 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1493 speed_mask |= ADVERTISED_Asym_Pause; 1494 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1495 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1496 1497 return speed_mask; 1498 } 1499 1500 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1501 { \ 1502 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1503 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1504 100baseT_Full); \ 1505 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1506 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1507 1000baseT_Full); \ 1508 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1509 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1510 10000baseT_Full); \ 1511 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1512 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1513 25000baseCR_Full); \ 1514 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1515 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1516 40000baseCR4_Full);\ 1517 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1518 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1519 50000baseCR2_Full);\ 1520 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1521 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1522 100000baseCR4_Full);\ 1523 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1524 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1525 Pause); \ 1526 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1527 ethtool_link_ksettings_add_link_mode( \ 1528 lk_ksettings, name, Asym_Pause);\ 1529 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1530 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1531 Asym_Pause); \ 1532 } \ 1533 } 1534 1535 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1536 { \ 1537 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1538 100baseT_Full) || \ 1539 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1540 100baseT_Half)) \ 1541 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1542 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1543 1000baseT_Full) || \ 1544 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1545 1000baseT_Half)) \ 1546 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1547 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1548 10000baseT_Full)) \ 1549 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1550 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1551 25000baseCR_Full)) \ 1552 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1553 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1554 40000baseCR4_Full)) \ 1555 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1556 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1557 50000baseCR2_Full)) \ 1558 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1559 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1560 100000baseCR4_Full)) \ 1561 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1562 } 1563 1564 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1565 { \ 1566 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \ 1567 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1568 50000baseCR_Full); \ 1569 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \ 1570 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1571 100000baseCR2_Full);\ 1572 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \ 1573 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1574 200000baseCR4_Full);\ 1575 } 1576 1577 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1578 { \ 1579 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1580 50000baseCR_Full)) \ 1581 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \ 1582 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1583 100000baseCR2_Full)) \ 1584 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \ 1585 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1586 200000baseCR4_Full)) \ 1587 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \ 1588 } 1589 1590 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1591 struct ethtool_link_ksettings *lk_ksettings) 1592 { 1593 u16 fec_cfg = link_info->fec_cfg; 1594 1595 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1596 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1597 lk_ksettings->link_modes.advertising); 1598 return; 1599 } 1600 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1601 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1602 lk_ksettings->link_modes.advertising); 1603 if (fec_cfg & BNXT_FEC_ENC_RS) 1604 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1605 lk_ksettings->link_modes.advertising); 1606 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1607 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1608 lk_ksettings->link_modes.advertising); 1609 } 1610 1611 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1612 struct ethtool_link_ksettings *lk_ksettings) 1613 { 1614 u16 fw_speeds = link_info->advertising; 1615 u8 fw_pause = 0; 1616 1617 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1618 fw_pause = link_info->auto_pause_setting; 1619 1620 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1621 fw_speeds = link_info->advertising_pam4; 1622 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising); 1623 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 1624 } 1625 1626 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1627 struct ethtool_link_ksettings *lk_ksettings) 1628 { 1629 u16 fw_speeds = link_info->lp_auto_link_speeds; 1630 u8 fw_pause = 0; 1631 1632 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1633 fw_pause = link_info->lp_pause; 1634 1635 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1636 lp_advertising); 1637 fw_speeds = link_info->lp_auto_pam4_link_speeds; 1638 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising); 1639 } 1640 1641 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1642 struct ethtool_link_ksettings *lk_ksettings) 1643 { 1644 u16 fec_cfg = link_info->fec_cfg; 1645 1646 if (fec_cfg & BNXT_FEC_NONE) { 1647 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1648 lk_ksettings->link_modes.supported); 1649 return; 1650 } 1651 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1652 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1653 lk_ksettings->link_modes.supported); 1654 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1655 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1656 lk_ksettings->link_modes.supported); 1657 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1658 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1659 lk_ksettings->link_modes.supported); 1660 } 1661 1662 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1663 struct ethtool_link_ksettings *lk_ksettings) 1664 { 1665 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 1666 u16 fw_speeds = link_info->support_speeds; 1667 1668 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1669 fw_speeds = link_info->support_pam4_speeds; 1670 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported); 1671 1672 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 1673 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1674 Pause); 1675 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1676 Asym_Pause); 1677 } 1678 1679 if (link_info->support_auto_speeds || 1680 link_info->support_pam4_auto_speeds) 1681 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1682 Autoneg); 1683 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 1684 } 1685 1686 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1687 { 1688 switch (fw_link_speed) { 1689 case BNXT_LINK_SPEED_100MB: 1690 return SPEED_100; 1691 case BNXT_LINK_SPEED_1GB: 1692 return SPEED_1000; 1693 case BNXT_LINK_SPEED_2_5GB: 1694 return SPEED_2500; 1695 case BNXT_LINK_SPEED_10GB: 1696 return SPEED_10000; 1697 case BNXT_LINK_SPEED_20GB: 1698 return SPEED_20000; 1699 case BNXT_LINK_SPEED_25GB: 1700 return SPEED_25000; 1701 case BNXT_LINK_SPEED_40GB: 1702 return SPEED_40000; 1703 case BNXT_LINK_SPEED_50GB: 1704 return SPEED_50000; 1705 case BNXT_LINK_SPEED_100GB: 1706 return SPEED_100000; 1707 default: 1708 return SPEED_UNKNOWN; 1709 } 1710 } 1711 1712 static int bnxt_get_link_ksettings(struct net_device *dev, 1713 struct ethtool_link_ksettings *lk_ksettings) 1714 { 1715 struct bnxt *bp = netdev_priv(dev); 1716 struct bnxt_link_info *link_info = &bp->link_info; 1717 struct ethtool_link_settings *base = &lk_ksettings->base; 1718 u32 ethtool_speed; 1719 1720 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1721 mutex_lock(&bp->link_lock); 1722 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1723 1724 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1725 if (link_info->autoneg) { 1726 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1727 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1728 advertising, Autoneg); 1729 base->autoneg = AUTONEG_ENABLE; 1730 base->duplex = DUPLEX_UNKNOWN; 1731 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1732 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1733 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1734 base->duplex = DUPLEX_FULL; 1735 else 1736 base->duplex = DUPLEX_HALF; 1737 } 1738 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1739 } else { 1740 base->autoneg = AUTONEG_DISABLE; 1741 ethtool_speed = 1742 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1743 base->duplex = DUPLEX_HALF; 1744 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1745 base->duplex = DUPLEX_FULL; 1746 } 1747 base->speed = ethtool_speed; 1748 1749 base->port = PORT_NONE; 1750 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1751 base->port = PORT_TP; 1752 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1753 TP); 1754 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1755 TP); 1756 } else { 1757 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1758 FIBRE); 1759 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1760 FIBRE); 1761 1762 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1763 base->port = PORT_DA; 1764 else if (link_info->media_type == 1765 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1766 base->port = PORT_FIBRE; 1767 } 1768 base->phy_address = link_info->phy_addr; 1769 mutex_unlock(&bp->link_lock); 1770 1771 return 0; 1772 } 1773 1774 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed) 1775 { 1776 struct bnxt *bp = netdev_priv(dev); 1777 struct bnxt_link_info *link_info = &bp->link_info; 1778 u16 support_pam4_spds = link_info->support_pam4_speeds; 1779 u16 support_spds = link_info->support_speeds; 1780 u8 sig_mode = BNXT_SIG_MODE_NRZ; 1781 u16 fw_speed = 0; 1782 1783 switch (ethtool_speed) { 1784 case SPEED_100: 1785 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1786 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 1787 break; 1788 case SPEED_1000: 1789 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1790 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 1791 break; 1792 case SPEED_2500: 1793 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1794 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 1795 break; 1796 case SPEED_10000: 1797 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1798 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 1799 break; 1800 case SPEED_20000: 1801 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1802 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 1803 break; 1804 case SPEED_25000: 1805 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1806 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 1807 break; 1808 case SPEED_40000: 1809 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1810 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 1811 break; 1812 case SPEED_50000: 1813 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) { 1814 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 1815 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 1816 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 1817 sig_mode = BNXT_SIG_MODE_PAM4; 1818 } 1819 break; 1820 case SPEED_100000: 1821 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) { 1822 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 1823 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 1824 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 1825 sig_mode = BNXT_SIG_MODE_PAM4; 1826 } 1827 break; 1828 case SPEED_200000: 1829 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 1830 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 1831 sig_mode = BNXT_SIG_MODE_PAM4; 1832 } 1833 break; 1834 } 1835 1836 if (!fw_speed) { 1837 netdev_err(dev, "unsupported speed!\n"); 1838 return -EINVAL; 1839 } 1840 1841 if (link_info->req_link_speed == fw_speed && 1842 link_info->req_signal_mode == sig_mode && 1843 link_info->autoneg == 0) 1844 return -EALREADY; 1845 1846 link_info->req_link_speed = fw_speed; 1847 link_info->req_signal_mode = sig_mode; 1848 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1849 link_info->autoneg = 0; 1850 link_info->advertising = 0; 1851 link_info->advertising_pam4 = 0; 1852 1853 return 0; 1854 } 1855 1856 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1857 { 1858 u16 fw_speed_mask = 0; 1859 1860 /* only support autoneg at speed 100, 1000, and 10000 */ 1861 if (advertising & (ADVERTISED_100baseT_Full | 1862 ADVERTISED_100baseT_Half)) { 1863 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1864 } 1865 if (advertising & (ADVERTISED_1000baseT_Full | 1866 ADVERTISED_1000baseT_Half)) { 1867 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1868 } 1869 if (advertising & ADVERTISED_10000baseT_Full) 1870 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1871 1872 if (advertising & ADVERTISED_40000baseCR4_Full) 1873 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1874 1875 return fw_speed_mask; 1876 } 1877 1878 static int bnxt_set_link_ksettings(struct net_device *dev, 1879 const struct ethtool_link_ksettings *lk_ksettings) 1880 { 1881 struct bnxt *bp = netdev_priv(dev); 1882 struct bnxt_link_info *link_info = &bp->link_info; 1883 const struct ethtool_link_settings *base = &lk_ksettings->base; 1884 bool set_pause = false; 1885 u32 speed; 1886 int rc = 0; 1887 1888 if (!BNXT_PHY_CFG_ABLE(bp)) 1889 return -EOPNOTSUPP; 1890 1891 mutex_lock(&bp->link_lock); 1892 if (base->autoneg == AUTONEG_ENABLE) { 1893 link_info->advertising = 0; 1894 link_info->advertising_pam4 = 0; 1895 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings, 1896 advertising); 1897 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4, 1898 lk_ksettings, advertising); 1899 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1900 if (!link_info->advertising && !link_info->advertising_pam4) { 1901 link_info->advertising = link_info->support_auto_speeds; 1902 link_info->advertising_pam4 = 1903 link_info->support_pam4_auto_speeds; 1904 } 1905 /* any change to autoneg will cause link change, therefore the 1906 * driver should put back the original pause setting in autoneg 1907 */ 1908 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 1909 set_pause = true; 1910 } else { 1911 u8 phy_type = link_info->phy_type; 1912 1913 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1914 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1915 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1916 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1917 rc = -EINVAL; 1918 goto set_setting_exit; 1919 } 1920 if (base->duplex == DUPLEX_HALF) { 1921 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1922 rc = -EINVAL; 1923 goto set_setting_exit; 1924 } 1925 speed = base->speed; 1926 rc = bnxt_force_link_speed(dev, speed); 1927 if (rc) { 1928 if (rc == -EALREADY) 1929 rc = 0; 1930 goto set_setting_exit; 1931 } 1932 } 1933 1934 if (netif_running(dev)) 1935 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1936 1937 set_setting_exit: 1938 mutex_unlock(&bp->link_lock); 1939 return rc; 1940 } 1941 1942 static int bnxt_get_fecparam(struct net_device *dev, 1943 struct ethtool_fecparam *fec) 1944 { 1945 struct bnxt *bp = netdev_priv(dev); 1946 struct bnxt_link_info *link_info; 1947 u8 active_fec; 1948 u16 fec_cfg; 1949 1950 link_info = &bp->link_info; 1951 fec_cfg = link_info->fec_cfg; 1952 active_fec = link_info->active_fec_sig_mode & 1953 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 1954 if (fec_cfg & BNXT_FEC_NONE) { 1955 fec->fec = ETHTOOL_FEC_NONE; 1956 fec->active_fec = ETHTOOL_FEC_NONE; 1957 return 0; 1958 } 1959 if (fec_cfg & BNXT_FEC_AUTONEG) 1960 fec->fec |= ETHTOOL_FEC_AUTO; 1961 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1962 fec->fec |= ETHTOOL_FEC_BASER; 1963 if (fec_cfg & BNXT_FEC_ENC_RS) 1964 fec->fec |= ETHTOOL_FEC_RS; 1965 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1966 fec->fec |= ETHTOOL_FEC_LLRS; 1967 1968 switch (active_fec) { 1969 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 1970 fec->active_fec |= ETHTOOL_FEC_BASER; 1971 break; 1972 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 1973 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 1974 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 1975 fec->active_fec |= ETHTOOL_FEC_RS; 1976 break; 1977 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 1978 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 1979 fec->active_fec |= ETHTOOL_FEC_LLRS; 1980 break; 1981 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 1982 fec->active_fec |= ETHTOOL_FEC_OFF; 1983 break; 1984 } 1985 return 0; 1986 } 1987 1988 static void bnxt_get_fec_stats(struct net_device *dev, 1989 struct ethtool_fec_stats *fec_stats) 1990 { 1991 struct bnxt *bp = netdev_priv(dev); 1992 u64 *rx; 1993 1994 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 1995 return; 1996 1997 rx = bp->rx_port_stats_ext.sw_stats; 1998 fec_stats->corrected_bits.total = 1999 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 2000 } 2001 2002 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 2003 u32 fec) 2004 { 2005 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 2006 2007 if (fec & ETHTOOL_FEC_BASER) 2008 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 2009 else if (fec & ETHTOOL_FEC_RS) 2010 fw_fec |= BNXT_FEC_RS_ON(link_info); 2011 else if (fec & ETHTOOL_FEC_LLRS) 2012 fw_fec |= BNXT_FEC_LLRS_ON; 2013 return fw_fec; 2014 } 2015 2016 static int bnxt_set_fecparam(struct net_device *dev, 2017 struct ethtool_fecparam *fecparam) 2018 { 2019 struct hwrm_port_phy_cfg_input *req; 2020 struct bnxt *bp = netdev_priv(dev); 2021 struct bnxt_link_info *link_info; 2022 u32 new_cfg, fec = fecparam->fec; 2023 u16 fec_cfg; 2024 int rc; 2025 2026 link_info = &bp->link_info; 2027 fec_cfg = link_info->fec_cfg; 2028 if (fec_cfg & BNXT_FEC_NONE) 2029 return -EOPNOTSUPP; 2030 2031 if (fec & ETHTOOL_FEC_OFF) { 2032 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 2033 BNXT_FEC_ALL_OFF(link_info); 2034 goto apply_fec; 2035 } 2036 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2037 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2038 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2039 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2040 return -EINVAL; 2041 2042 if (fec & ETHTOOL_FEC_AUTO) { 2043 if (!link_info->autoneg) 2044 return -EINVAL; 2045 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2046 } else { 2047 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2048 } 2049 2050 apply_fec: 2051 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2052 if (rc) 2053 return rc; 2054 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2055 rc = hwrm_req_send(bp, req); 2056 /* update current settings */ 2057 if (!rc) { 2058 mutex_lock(&bp->link_lock); 2059 bnxt_update_link(bp, false); 2060 mutex_unlock(&bp->link_lock); 2061 } 2062 return rc; 2063 } 2064 2065 static void bnxt_get_pauseparam(struct net_device *dev, 2066 struct ethtool_pauseparam *epause) 2067 { 2068 struct bnxt *bp = netdev_priv(dev); 2069 struct bnxt_link_info *link_info = &bp->link_info; 2070 2071 if (BNXT_VF(bp)) 2072 return; 2073 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2074 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2075 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2076 } 2077 2078 static void bnxt_get_pause_stats(struct net_device *dev, 2079 struct ethtool_pause_stats *epstat) 2080 { 2081 struct bnxt *bp = netdev_priv(dev); 2082 u64 *rx, *tx; 2083 2084 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2085 return; 2086 2087 rx = bp->port_stats.sw_stats; 2088 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2089 2090 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2091 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2092 } 2093 2094 static int bnxt_set_pauseparam(struct net_device *dev, 2095 struct ethtool_pauseparam *epause) 2096 { 2097 int rc = 0; 2098 struct bnxt *bp = netdev_priv(dev); 2099 struct bnxt_link_info *link_info = &bp->link_info; 2100 2101 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2102 return -EOPNOTSUPP; 2103 2104 mutex_lock(&bp->link_lock); 2105 if (epause->autoneg) { 2106 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2107 rc = -EINVAL; 2108 goto pause_exit; 2109 } 2110 2111 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2112 if (bp->hwrm_spec_code >= 0x10201) 2113 link_info->req_flow_ctrl = 2114 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 2115 } else { 2116 /* when transition from auto pause to force pause, 2117 * force a link change 2118 */ 2119 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2120 link_info->force_link_chng = true; 2121 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2122 link_info->req_flow_ctrl = 0; 2123 } 2124 if (epause->rx_pause) 2125 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2126 2127 if (epause->tx_pause) 2128 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2129 2130 if (netif_running(dev)) 2131 rc = bnxt_hwrm_set_pause(bp); 2132 2133 pause_exit: 2134 mutex_unlock(&bp->link_lock); 2135 return rc; 2136 } 2137 2138 static u32 bnxt_get_link(struct net_device *dev) 2139 { 2140 struct bnxt *bp = netdev_priv(dev); 2141 2142 /* TODO: handle MF, VF, driver close case */ 2143 return BNXT_LINK_IS_UP(bp); 2144 } 2145 2146 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2147 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2148 { 2149 struct hwrm_nvm_get_dev_info_output *resp; 2150 struct hwrm_nvm_get_dev_info_input *req; 2151 int rc; 2152 2153 if (BNXT_VF(bp)) 2154 return -EOPNOTSUPP; 2155 2156 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2157 if (rc) 2158 return rc; 2159 2160 resp = hwrm_req_hold(bp, req); 2161 rc = hwrm_req_send(bp, req); 2162 if (!rc) 2163 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2164 hwrm_req_drop(bp, req); 2165 return rc; 2166 } 2167 2168 static void bnxt_print_admin_err(struct bnxt *bp) 2169 { 2170 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2171 } 2172 2173 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2174 u16 ext, u16 *index, u32 *item_length, 2175 u32 *data_length); 2176 2177 static int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2178 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2179 u32 dir_item_len, const u8 *data, 2180 size_t data_len) 2181 { 2182 struct bnxt *bp = netdev_priv(dev); 2183 struct hwrm_nvm_write_input *req; 2184 int rc; 2185 2186 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2187 if (rc) 2188 return rc; 2189 2190 if (data_len && data) { 2191 dma_addr_t dma_handle; 2192 u8 *kmem; 2193 2194 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2195 if (!kmem) { 2196 hwrm_req_drop(bp, req); 2197 return -ENOMEM; 2198 } 2199 2200 req->dir_data_length = cpu_to_le32(data_len); 2201 2202 memcpy(kmem, data, data_len); 2203 req->host_src_addr = cpu_to_le64(dma_handle); 2204 } 2205 2206 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 2207 req->dir_type = cpu_to_le16(dir_type); 2208 req->dir_ordinal = cpu_to_le16(dir_ordinal); 2209 req->dir_ext = cpu_to_le16(dir_ext); 2210 req->dir_attr = cpu_to_le16(dir_attr); 2211 req->dir_item_length = cpu_to_le32(dir_item_len); 2212 rc = hwrm_req_send(bp, req); 2213 2214 if (rc == -EACCES) 2215 bnxt_print_admin_err(bp); 2216 return rc; 2217 } 2218 2219 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2220 u8 self_reset, u8 flags) 2221 { 2222 struct bnxt *bp = netdev_priv(dev); 2223 struct hwrm_fw_reset_input *req; 2224 int rc; 2225 2226 if (!bnxt_hwrm_reset_permitted(bp)) { 2227 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 2228 return -EPERM; 2229 } 2230 2231 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 2232 if (rc) 2233 return rc; 2234 2235 req->embedded_proc_type = proc_type; 2236 req->selfrst_status = self_reset; 2237 req->flags = flags; 2238 2239 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2240 rc = hwrm_req_send_silent(bp, req); 2241 } else { 2242 rc = hwrm_req_send(bp, req); 2243 if (rc == -EACCES) 2244 bnxt_print_admin_err(bp); 2245 } 2246 return rc; 2247 } 2248 2249 static int bnxt_firmware_reset(struct net_device *dev, 2250 enum bnxt_nvm_directory_type dir_type) 2251 { 2252 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2253 u8 proc_type, flags = 0; 2254 2255 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2256 /* (e.g. when firmware isn't already running) */ 2257 switch (dir_type) { 2258 case BNX_DIR_TYPE_CHIMP_PATCH: 2259 case BNX_DIR_TYPE_BOOTCODE: 2260 case BNX_DIR_TYPE_BOOTCODE_2: 2261 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2262 /* Self-reset ChiMP upon next PCIe reset: */ 2263 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2264 break; 2265 case BNX_DIR_TYPE_APE_FW: 2266 case BNX_DIR_TYPE_APE_PATCH: 2267 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2268 /* Self-reset APE upon next PCIe reset: */ 2269 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2270 break; 2271 case BNX_DIR_TYPE_KONG_FW: 2272 case BNX_DIR_TYPE_KONG_PATCH: 2273 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2274 break; 2275 case BNX_DIR_TYPE_BONO_FW: 2276 case BNX_DIR_TYPE_BONO_PATCH: 2277 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2278 break; 2279 default: 2280 return -EINVAL; 2281 } 2282 2283 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2284 } 2285 2286 static int bnxt_firmware_reset_chip(struct net_device *dev) 2287 { 2288 struct bnxt *bp = netdev_priv(dev); 2289 u8 flags = 0; 2290 2291 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2292 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2293 2294 return bnxt_hwrm_firmware_reset(dev, 2295 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2296 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2297 flags); 2298 } 2299 2300 static int bnxt_firmware_reset_ap(struct net_device *dev) 2301 { 2302 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2303 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2304 0); 2305 } 2306 2307 static int bnxt_flash_firmware(struct net_device *dev, 2308 u16 dir_type, 2309 const u8 *fw_data, 2310 size_t fw_size) 2311 { 2312 int rc = 0; 2313 u16 code_type; 2314 u32 stored_crc; 2315 u32 calculated_crc; 2316 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2317 2318 switch (dir_type) { 2319 case BNX_DIR_TYPE_BOOTCODE: 2320 case BNX_DIR_TYPE_BOOTCODE_2: 2321 code_type = CODE_BOOT; 2322 break; 2323 case BNX_DIR_TYPE_CHIMP_PATCH: 2324 code_type = CODE_CHIMP_PATCH; 2325 break; 2326 case BNX_DIR_TYPE_APE_FW: 2327 code_type = CODE_MCTP_PASSTHRU; 2328 break; 2329 case BNX_DIR_TYPE_APE_PATCH: 2330 code_type = CODE_APE_PATCH; 2331 break; 2332 case BNX_DIR_TYPE_KONG_FW: 2333 code_type = CODE_KONG_FW; 2334 break; 2335 case BNX_DIR_TYPE_KONG_PATCH: 2336 code_type = CODE_KONG_PATCH; 2337 break; 2338 case BNX_DIR_TYPE_BONO_FW: 2339 code_type = CODE_BONO_FW; 2340 break; 2341 case BNX_DIR_TYPE_BONO_PATCH: 2342 code_type = CODE_BONO_PATCH; 2343 break; 2344 default: 2345 netdev_err(dev, "Unsupported directory entry type: %u\n", 2346 dir_type); 2347 return -EINVAL; 2348 } 2349 if (fw_size < sizeof(struct bnxt_fw_header)) { 2350 netdev_err(dev, "Invalid firmware file size: %u\n", 2351 (unsigned int)fw_size); 2352 return -EINVAL; 2353 } 2354 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2355 netdev_err(dev, "Invalid firmware signature: %08X\n", 2356 le32_to_cpu(header->signature)); 2357 return -EINVAL; 2358 } 2359 if (header->code_type != code_type) { 2360 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2361 code_type, header->code_type); 2362 return -EINVAL; 2363 } 2364 if (header->device != DEVICE_CUMULUS_FAMILY) { 2365 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2366 DEVICE_CUMULUS_FAMILY, header->device); 2367 return -EINVAL; 2368 } 2369 /* Confirm the CRC32 checksum of the file: */ 2370 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2371 sizeof(stored_crc))); 2372 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2373 if (calculated_crc != stored_crc) { 2374 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2375 (unsigned long)stored_crc, 2376 (unsigned long)calculated_crc); 2377 return -EINVAL; 2378 } 2379 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2380 0, 0, 0, fw_data, fw_size); 2381 if (rc == 0) /* Firmware update successful */ 2382 rc = bnxt_firmware_reset(dev, dir_type); 2383 2384 return rc; 2385 } 2386 2387 static int bnxt_flash_microcode(struct net_device *dev, 2388 u16 dir_type, 2389 const u8 *fw_data, 2390 size_t fw_size) 2391 { 2392 struct bnxt_ucode_trailer *trailer; 2393 u32 calculated_crc; 2394 u32 stored_crc; 2395 int rc = 0; 2396 2397 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2398 netdev_err(dev, "Invalid microcode file size: %u\n", 2399 (unsigned int)fw_size); 2400 return -EINVAL; 2401 } 2402 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2403 sizeof(*trailer))); 2404 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2405 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2406 le32_to_cpu(trailer->sig)); 2407 return -EINVAL; 2408 } 2409 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2410 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2411 dir_type, le16_to_cpu(trailer->dir_type)); 2412 return -EINVAL; 2413 } 2414 if (le16_to_cpu(trailer->trailer_length) < 2415 sizeof(struct bnxt_ucode_trailer)) { 2416 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2417 le16_to_cpu(trailer->trailer_length)); 2418 return -EINVAL; 2419 } 2420 2421 /* Confirm the CRC32 checksum of the file: */ 2422 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2423 sizeof(stored_crc))); 2424 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2425 if (calculated_crc != stored_crc) { 2426 netdev_err(dev, 2427 "CRC32 (%08lX) does not match calculated: %08lX\n", 2428 (unsigned long)stored_crc, 2429 (unsigned long)calculated_crc); 2430 return -EINVAL; 2431 } 2432 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2433 0, 0, 0, fw_data, fw_size); 2434 2435 return rc; 2436 } 2437 2438 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2439 { 2440 switch (dir_type) { 2441 case BNX_DIR_TYPE_CHIMP_PATCH: 2442 case BNX_DIR_TYPE_BOOTCODE: 2443 case BNX_DIR_TYPE_BOOTCODE_2: 2444 case BNX_DIR_TYPE_APE_FW: 2445 case BNX_DIR_TYPE_APE_PATCH: 2446 case BNX_DIR_TYPE_KONG_FW: 2447 case BNX_DIR_TYPE_KONG_PATCH: 2448 case BNX_DIR_TYPE_BONO_FW: 2449 case BNX_DIR_TYPE_BONO_PATCH: 2450 return true; 2451 } 2452 2453 return false; 2454 } 2455 2456 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2457 { 2458 switch (dir_type) { 2459 case BNX_DIR_TYPE_AVS: 2460 case BNX_DIR_TYPE_EXP_ROM_MBA: 2461 case BNX_DIR_TYPE_PCIE: 2462 case BNX_DIR_TYPE_TSCF_UCODE: 2463 case BNX_DIR_TYPE_EXT_PHY: 2464 case BNX_DIR_TYPE_CCM: 2465 case BNX_DIR_TYPE_ISCSI_BOOT: 2466 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2467 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2468 return true; 2469 } 2470 2471 return false; 2472 } 2473 2474 static bool bnxt_dir_type_is_executable(u16 dir_type) 2475 { 2476 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2477 bnxt_dir_type_is_other_exec_format(dir_type); 2478 } 2479 2480 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2481 u16 dir_type, 2482 const char *filename) 2483 { 2484 const struct firmware *fw; 2485 int rc; 2486 2487 rc = request_firmware(&fw, filename, &dev->dev); 2488 if (rc != 0) { 2489 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2490 rc, filename); 2491 return rc; 2492 } 2493 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2494 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2495 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2496 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2497 else 2498 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2499 0, 0, 0, fw->data, fw->size); 2500 release_firmware(fw); 2501 return rc; 2502 } 2503 2504 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result) 2505 { 2506 switch (result) { 2507 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 2508 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 2509 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 2510 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 2511 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 2512 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 2513 netdev_err(dev, "PKG install error : Data integrity on NVM\n"); 2514 return -EINVAL; 2515 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 2516 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 2517 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 2518 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 2519 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 2520 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 2521 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 2522 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 2523 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 2524 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 2525 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 2526 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 2527 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 2528 netdev_err(dev, "PKG install error : Invalid package\n"); 2529 return -ENOPKG; 2530 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 2531 netdev_err(dev, "PKG install error : Authentication error\n"); 2532 return -EPERM; 2533 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 2534 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 2535 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 2536 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 2537 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 2538 netdev_err(dev, "PKG install error : Invalid device\n"); 2539 return -EOPNOTSUPP; 2540 default: 2541 netdev_err(dev, "PKG install error : Internal error\n"); 2542 return -EIO; 2543 } 2544 } 2545 2546 #define BNXT_PKG_DMA_SIZE 0x40000 2547 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2548 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2549 2550 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2551 u32 install_type) 2552 { 2553 struct hwrm_nvm_install_update_input *install; 2554 struct hwrm_nvm_install_update_output *resp; 2555 struct hwrm_nvm_modify_input *modify; 2556 struct bnxt *bp = netdev_priv(dev); 2557 bool defrag_attempted = false; 2558 dma_addr_t dma_handle; 2559 u8 *kmem = NULL; 2560 u32 modify_len; 2561 u32 item_len; 2562 u8 cmd_err; 2563 u16 index; 2564 int rc; 2565 2566 bnxt_hwrm_fw_set_time(bp); 2567 2568 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 2569 if (rc) 2570 return rc; 2571 2572 /* Try allocating a large DMA buffer first. Older fw will 2573 * cause excessive NVRAM erases when using small blocks. 2574 */ 2575 modify_len = roundup_pow_of_two(fw->size); 2576 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 2577 while (1) { 2578 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 2579 if (!kmem && modify_len > PAGE_SIZE) 2580 modify_len /= 2; 2581 else 2582 break; 2583 } 2584 if (!kmem) { 2585 hwrm_req_drop(bp, modify); 2586 return -ENOMEM; 2587 } 2588 2589 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 2590 if (rc) { 2591 hwrm_req_drop(bp, modify); 2592 return rc; 2593 } 2594 2595 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 2596 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 2597 2598 hwrm_req_hold(bp, modify); 2599 modify->host_src_addr = cpu_to_le64(dma_handle); 2600 2601 resp = hwrm_req_hold(bp, install); 2602 if ((install_type & 0xffff) == 0) 2603 install_type >>= 16; 2604 install->install_type = cpu_to_le32(install_type); 2605 2606 do { 2607 u32 copied = 0, len = modify_len; 2608 2609 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2610 BNX_DIR_ORDINAL_FIRST, 2611 BNX_DIR_EXT_NONE, 2612 &index, &item_len, NULL); 2613 if (rc) { 2614 netdev_err(dev, "PKG update area not created in nvram\n"); 2615 break; 2616 } 2617 if (fw->size > item_len) { 2618 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2619 (unsigned long)fw->size); 2620 rc = -EFBIG; 2621 break; 2622 } 2623 2624 modify->dir_idx = cpu_to_le16(index); 2625 2626 if (fw->size > modify_len) 2627 modify->flags = BNXT_NVM_MORE_FLAG; 2628 while (copied < fw->size) { 2629 u32 balance = fw->size - copied; 2630 2631 if (balance <= modify_len) { 2632 len = balance; 2633 if (copied) 2634 modify->flags |= BNXT_NVM_LAST_FLAG; 2635 } 2636 memcpy(kmem, fw->data + copied, len); 2637 modify->len = cpu_to_le32(len); 2638 modify->offset = cpu_to_le32(copied); 2639 rc = hwrm_req_send(bp, modify); 2640 if (rc) 2641 goto pkg_abort; 2642 copied += len; 2643 } 2644 2645 rc = hwrm_req_send_silent(bp, install); 2646 if (!rc) 2647 break; 2648 2649 if (defrag_attempted) { 2650 /* We have tried to defragment already in the previous 2651 * iteration. Return with the result for INSTALL_UPDATE 2652 */ 2653 break; 2654 } 2655 2656 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 2657 2658 switch (cmd_err) { 2659 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 2660 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure Anti-rollback detected\n"); 2661 rc = -EALREADY; 2662 break; 2663 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 2664 install->flags = 2665 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2666 2667 rc = hwrm_req_send_silent(bp, install); 2668 if (!rc) 2669 break; 2670 2671 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 2672 2673 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 2674 /* FW has cleared NVM area, driver will create 2675 * UPDATE directory and try the flash again 2676 */ 2677 defrag_attempted = true; 2678 install->flags = 0; 2679 rc = bnxt_flash_nvram(bp->dev, 2680 BNX_DIR_TYPE_UPDATE, 2681 BNX_DIR_ORDINAL_FIRST, 2682 0, 0, item_len, NULL, 0); 2683 if (!rc) 2684 break; 2685 } 2686 fallthrough; 2687 default: 2688 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x cmd_err :%x\n", 2689 rc, cmd_err); 2690 } 2691 } while (defrag_attempted && !rc); 2692 2693 pkg_abort: 2694 hwrm_req_drop(bp, modify); 2695 hwrm_req_drop(bp, install); 2696 2697 if (resp->result) { 2698 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2699 (s8)resp->result, (int)resp->problem_item); 2700 rc = nvm_update_err_to_stderr(dev, resp->result); 2701 } 2702 if (rc == -EACCES) 2703 bnxt_print_admin_err(bp); 2704 return rc; 2705 } 2706 2707 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2708 u32 install_type) 2709 { 2710 const struct firmware *fw; 2711 int rc; 2712 2713 rc = request_firmware(&fw, filename, &dev->dev); 2714 if (rc != 0) { 2715 netdev_err(dev, "PKG error %d requesting file: %s\n", 2716 rc, filename); 2717 return rc; 2718 } 2719 2720 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type); 2721 2722 release_firmware(fw); 2723 2724 return rc; 2725 } 2726 2727 static int bnxt_flash_device(struct net_device *dev, 2728 struct ethtool_flash *flash) 2729 { 2730 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2731 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2732 return -EINVAL; 2733 } 2734 2735 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2736 flash->region > 0xffff) 2737 return bnxt_flash_package_from_file(dev, flash->data, 2738 flash->region); 2739 2740 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2741 } 2742 2743 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2744 { 2745 struct hwrm_nvm_get_dir_info_output *output; 2746 struct hwrm_nvm_get_dir_info_input *req; 2747 struct bnxt *bp = netdev_priv(dev); 2748 int rc; 2749 2750 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 2751 if (rc) 2752 return rc; 2753 2754 output = hwrm_req_hold(bp, req); 2755 rc = hwrm_req_send(bp, req); 2756 if (!rc) { 2757 *entries = le32_to_cpu(output->entries); 2758 *length = le32_to_cpu(output->entry_length); 2759 } 2760 hwrm_req_drop(bp, req); 2761 return rc; 2762 } 2763 2764 static int bnxt_get_eeprom_len(struct net_device *dev) 2765 { 2766 struct bnxt *bp = netdev_priv(dev); 2767 2768 if (BNXT_VF(bp)) 2769 return 0; 2770 2771 /* The -1 return value allows the entire 32-bit range of offsets to be 2772 * passed via the ethtool command-line utility. 2773 */ 2774 return -1; 2775 } 2776 2777 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2778 { 2779 struct bnxt *bp = netdev_priv(dev); 2780 int rc; 2781 u32 dir_entries; 2782 u32 entry_length; 2783 u8 *buf; 2784 size_t buflen; 2785 dma_addr_t dma_handle; 2786 struct hwrm_nvm_get_dir_entries_input *req; 2787 2788 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2789 if (rc != 0) 2790 return rc; 2791 2792 if (!dir_entries || !entry_length) 2793 return -EIO; 2794 2795 /* Insert 2 bytes of directory info (count and size of entries) */ 2796 if (len < 2) 2797 return -EINVAL; 2798 2799 *data++ = dir_entries; 2800 *data++ = entry_length; 2801 len -= 2; 2802 memset(data, 0xff, len); 2803 2804 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 2805 if (rc) 2806 return rc; 2807 2808 buflen = dir_entries * entry_length; 2809 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 2810 if (!buf) { 2811 hwrm_req_drop(bp, req); 2812 return -ENOMEM; 2813 } 2814 req->host_dest_addr = cpu_to_le64(dma_handle); 2815 2816 hwrm_req_hold(bp, req); /* hold the slice */ 2817 rc = hwrm_req_send(bp, req); 2818 if (rc == 0) 2819 memcpy(data, buf, len > buflen ? buflen : len); 2820 hwrm_req_drop(bp, req); 2821 return rc; 2822 } 2823 2824 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2825 u32 length, u8 *data) 2826 { 2827 struct bnxt *bp = netdev_priv(dev); 2828 int rc; 2829 u8 *buf; 2830 dma_addr_t dma_handle; 2831 struct hwrm_nvm_read_input *req; 2832 2833 if (!length) 2834 return -EINVAL; 2835 2836 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 2837 if (rc) 2838 return rc; 2839 2840 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 2841 if (!buf) { 2842 hwrm_req_drop(bp, req); 2843 return -ENOMEM; 2844 } 2845 2846 req->host_dest_addr = cpu_to_le64(dma_handle); 2847 req->dir_idx = cpu_to_le16(index); 2848 req->offset = cpu_to_le32(offset); 2849 req->len = cpu_to_le32(length); 2850 2851 hwrm_req_hold(bp, req); /* hold the slice */ 2852 rc = hwrm_req_send(bp, req); 2853 if (rc == 0) 2854 memcpy(data, buf, length); 2855 hwrm_req_drop(bp, req); 2856 return rc; 2857 } 2858 2859 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2860 u16 ext, u16 *index, u32 *item_length, 2861 u32 *data_length) 2862 { 2863 struct hwrm_nvm_find_dir_entry_output *output; 2864 struct hwrm_nvm_find_dir_entry_input *req; 2865 struct bnxt *bp = netdev_priv(dev); 2866 int rc; 2867 2868 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 2869 if (rc) 2870 return rc; 2871 2872 req->enables = 0; 2873 req->dir_idx = 0; 2874 req->dir_type = cpu_to_le16(type); 2875 req->dir_ordinal = cpu_to_le16(ordinal); 2876 req->dir_ext = cpu_to_le16(ext); 2877 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2878 output = hwrm_req_hold(bp, req); 2879 rc = hwrm_req_send_silent(bp, req); 2880 if (rc == 0) { 2881 if (index) 2882 *index = le16_to_cpu(output->dir_idx); 2883 if (item_length) 2884 *item_length = le32_to_cpu(output->dir_item_length); 2885 if (data_length) 2886 *data_length = le32_to_cpu(output->dir_data_length); 2887 } 2888 hwrm_req_drop(bp, req); 2889 return rc; 2890 } 2891 2892 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2893 { 2894 char *retval = NULL; 2895 char *p; 2896 char *value; 2897 int field = 0; 2898 2899 if (datalen < 1) 2900 return NULL; 2901 /* null-terminate the log data (removing last '\n'): */ 2902 data[datalen - 1] = 0; 2903 for (p = data; *p != 0; p++) { 2904 field = 0; 2905 retval = NULL; 2906 while (*p != 0 && *p != '\n') { 2907 value = p; 2908 while (*p != 0 && *p != '\t' && *p != '\n') 2909 p++; 2910 if (field == desired_field) 2911 retval = value; 2912 if (*p != '\t') 2913 break; 2914 *p = 0; 2915 field++; 2916 p++; 2917 } 2918 if (*p == 0) 2919 break; 2920 *p = 0; 2921 } 2922 return retval; 2923 } 2924 2925 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 2926 { 2927 struct bnxt *bp = netdev_priv(dev); 2928 u16 index = 0; 2929 char *pkgver; 2930 u32 pkglen; 2931 u8 *pkgbuf; 2932 int rc; 2933 2934 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2935 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2936 &index, NULL, &pkglen); 2937 if (rc) 2938 return rc; 2939 2940 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2941 if (!pkgbuf) { 2942 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2943 pkglen); 2944 return -ENOMEM; 2945 } 2946 2947 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 2948 if (rc) 2949 goto err; 2950 2951 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2952 pkglen); 2953 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 2954 strscpy(ver, pkgver, size); 2955 else 2956 rc = -ENOENT; 2957 2958 err: 2959 kfree(pkgbuf); 2960 2961 return rc; 2962 } 2963 2964 static void bnxt_get_pkgver(struct net_device *dev) 2965 { 2966 struct bnxt *bp = netdev_priv(dev); 2967 char buf[FW_VER_STR_LEN]; 2968 int len; 2969 2970 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 2971 len = strlen(bp->fw_ver_str); 2972 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2973 "/pkg %s", buf); 2974 } 2975 } 2976 2977 static int bnxt_get_eeprom(struct net_device *dev, 2978 struct ethtool_eeprom *eeprom, 2979 u8 *data) 2980 { 2981 u32 index; 2982 u32 offset; 2983 2984 if (eeprom->offset == 0) /* special offset value to get directory */ 2985 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2986 2987 index = eeprom->offset >> 24; 2988 offset = eeprom->offset & 0xffffff; 2989 2990 if (index == 0) { 2991 netdev_err(dev, "unsupported index value: %d\n", index); 2992 return -EINVAL; 2993 } 2994 2995 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2996 } 2997 2998 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2999 { 3000 struct hwrm_nvm_erase_dir_entry_input *req; 3001 struct bnxt *bp = netdev_priv(dev); 3002 int rc; 3003 3004 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 3005 if (rc) 3006 return rc; 3007 3008 req->dir_idx = cpu_to_le16(index); 3009 return hwrm_req_send(bp, req); 3010 } 3011 3012 static int bnxt_set_eeprom(struct net_device *dev, 3013 struct ethtool_eeprom *eeprom, 3014 u8 *data) 3015 { 3016 struct bnxt *bp = netdev_priv(dev); 3017 u8 index, dir_op; 3018 u16 type, ext, ordinal, attr; 3019 3020 if (!BNXT_PF(bp)) { 3021 netdev_err(dev, "NVM write not supported from a virtual function\n"); 3022 return -EINVAL; 3023 } 3024 3025 type = eeprom->magic >> 16; 3026 3027 if (type == 0xffff) { /* special value for directory operations */ 3028 index = eeprom->magic & 0xff; 3029 dir_op = eeprom->magic >> 8; 3030 if (index == 0) 3031 return -EINVAL; 3032 switch (dir_op) { 3033 case 0x0e: /* erase */ 3034 if (eeprom->offset != ~eeprom->magic) 3035 return -EINVAL; 3036 return bnxt_erase_nvram_directory(dev, index - 1); 3037 default: 3038 return -EINVAL; 3039 } 3040 } 3041 3042 /* Create or re-write an NVM item: */ 3043 if (bnxt_dir_type_is_executable(type)) 3044 return -EOPNOTSUPP; 3045 ext = eeprom->magic & 0xffff; 3046 ordinal = eeprom->offset >> 16; 3047 attr = eeprom->offset & 0xffff; 3048 3049 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 3050 eeprom->len); 3051 } 3052 3053 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 3054 { 3055 struct bnxt *bp = netdev_priv(dev); 3056 struct ethtool_eee *eee = &bp->eee; 3057 struct bnxt_link_info *link_info = &bp->link_info; 3058 u32 advertising; 3059 int rc = 0; 3060 3061 if (!BNXT_PHY_CFG_ABLE(bp)) 3062 return -EOPNOTSUPP; 3063 3064 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3065 return -EOPNOTSUPP; 3066 3067 mutex_lock(&bp->link_lock); 3068 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 3069 if (!edata->eee_enabled) 3070 goto eee_ok; 3071 3072 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3073 netdev_warn(dev, "EEE requires autoneg\n"); 3074 rc = -EINVAL; 3075 goto eee_exit; 3076 } 3077 if (edata->tx_lpi_enabled) { 3078 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 3079 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 3080 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 3081 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 3082 rc = -EINVAL; 3083 goto eee_exit; 3084 } else if (!bp->lpi_tmr_hi) { 3085 edata->tx_lpi_timer = eee->tx_lpi_timer; 3086 } 3087 } 3088 if (!edata->advertised) { 3089 edata->advertised = advertising & eee->supported; 3090 } else if (edata->advertised & ~advertising) { 3091 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3092 edata->advertised, advertising); 3093 rc = -EINVAL; 3094 goto eee_exit; 3095 } 3096 3097 eee->advertised = edata->advertised; 3098 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3099 eee->tx_lpi_timer = edata->tx_lpi_timer; 3100 eee_ok: 3101 eee->eee_enabled = edata->eee_enabled; 3102 3103 if (netif_running(dev)) 3104 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3105 3106 eee_exit: 3107 mutex_unlock(&bp->link_lock); 3108 return rc; 3109 } 3110 3111 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3112 { 3113 struct bnxt *bp = netdev_priv(dev); 3114 3115 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3116 return -EOPNOTSUPP; 3117 3118 *edata = bp->eee; 3119 if (!bp->eee.eee_enabled) { 3120 /* Preserve tx_lpi_timer so that the last value will be used 3121 * by default when it is re-enabled. 3122 */ 3123 edata->advertised = 0; 3124 edata->tx_lpi_enabled = 0; 3125 } 3126 3127 if (!bp->eee.eee_active) 3128 edata->lp_advertised = 0; 3129 3130 return 0; 3131 } 3132 3133 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3134 u16 page_number, u16 start_addr, 3135 u16 data_length, u8 *buf) 3136 { 3137 struct hwrm_port_phy_i2c_read_output *output; 3138 struct hwrm_port_phy_i2c_read_input *req; 3139 int rc, byte_offset = 0; 3140 3141 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3142 if (rc) 3143 return rc; 3144 3145 output = hwrm_req_hold(bp, req); 3146 req->i2c_slave_addr = i2c_addr; 3147 req->page_number = cpu_to_le16(page_number); 3148 req->port_id = cpu_to_le16(bp->pf.port_id); 3149 do { 3150 u16 xfer_size; 3151 3152 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3153 data_length -= xfer_size; 3154 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3155 req->data_length = xfer_size; 3156 req->enables = cpu_to_le32(start_addr + byte_offset ? 3157 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 3158 rc = hwrm_req_send(bp, req); 3159 if (!rc) 3160 memcpy(buf + byte_offset, output->data, xfer_size); 3161 byte_offset += xfer_size; 3162 } while (!rc && data_length > 0); 3163 hwrm_req_drop(bp, req); 3164 3165 return rc; 3166 } 3167 3168 static int bnxt_get_module_info(struct net_device *dev, 3169 struct ethtool_modinfo *modinfo) 3170 { 3171 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 3172 struct bnxt *bp = netdev_priv(dev); 3173 int rc; 3174 3175 /* No point in going further if phy status indicates 3176 * module is not inserted or if it is powered down or 3177 * if it is of type 10GBase-T 3178 */ 3179 if (bp->link_info.module_status > 3180 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3181 return -EOPNOTSUPP; 3182 3183 /* This feature is not supported in older firmware versions */ 3184 if (bp->hwrm_spec_code < 0x10202) 3185 return -EOPNOTSUPP; 3186 3187 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3188 SFF_DIAG_SUPPORT_OFFSET + 1, 3189 data); 3190 if (!rc) { 3191 u8 module_id = data[0]; 3192 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 3193 3194 switch (module_id) { 3195 case SFF_MODULE_ID_SFP: 3196 modinfo->type = ETH_MODULE_SFF_8472; 3197 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3198 if (!diag_supported) 3199 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3200 break; 3201 case SFF_MODULE_ID_QSFP: 3202 case SFF_MODULE_ID_QSFP_PLUS: 3203 modinfo->type = ETH_MODULE_SFF_8436; 3204 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3205 break; 3206 case SFF_MODULE_ID_QSFP28: 3207 modinfo->type = ETH_MODULE_SFF_8636; 3208 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 3209 break; 3210 default: 3211 rc = -EOPNOTSUPP; 3212 break; 3213 } 3214 } 3215 return rc; 3216 } 3217 3218 static int bnxt_get_module_eeprom(struct net_device *dev, 3219 struct ethtool_eeprom *eeprom, 3220 u8 *data) 3221 { 3222 struct bnxt *bp = netdev_priv(dev); 3223 u16 start = eeprom->offset, length = eeprom->len; 3224 int rc = 0; 3225 3226 memset(data, 0, eeprom->len); 3227 3228 /* Read A0 portion of the EEPROM */ 3229 if (start < ETH_MODULE_SFF_8436_LEN) { 3230 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3231 length = ETH_MODULE_SFF_8436_LEN - start; 3232 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3233 start, length, data); 3234 if (rc) 3235 return rc; 3236 start += length; 3237 data += length; 3238 length = eeprom->len - length; 3239 } 3240 3241 /* Read A2 portion of the EEPROM */ 3242 if (length) { 3243 start -= ETH_MODULE_SFF_8436_LEN; 3244 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 3245 start, length, data); 3246 } 3247 return rc; 3248 } 3249 3250 static int bnxt_nway_reset(struct net_device *dev) 3251 { 3252 int rc = 0; 3253 3254 struct bnxt *bp = netdev_priv(dev); 3255 struct bnxt_link_info *link_info = &bp->link_info; 3256 3257 if (!BNXT_PHY_CFG_ABLE(bp)) 3258 return -EOPNOTSUPP; 3259 3260 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3261 return -EINVAL; 3262 3263 if (netif_running(dev)) 3264 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3265 3266 return rc; 3267 } 3268 3269 static int bnxt_set_phys_id(struct net_device *dev, 3270 enum ethtool_phys_id_state state) 3271 { 3272 struct hwrm_port_led_cfg_input *req; 3273 struct bnxt *bp = netdev_priv(dev); 3274 struct bnxt_pf_info *pf = &bp->pf; 3275 struct bnxt_led_cfg *led_cfg; 3276 u8 led_state; 3277 __le16 duration; 3278 int rc, i; 3279 3280 if (!bp->num_leds || BNXT_VF(bp)) 3281 return -EOPNOTSUPP; 3282 3283 if (state == ETHTOOL_ID_ACTIVE) { 3284 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3285 duration = cpu_to_le16(500); 3286 } else if (state == ETHTOOL_ID_INACTIVE) { 3287 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3288 duration = cpu_to_le16(0); 3289 } else { 3290 return -EINVAL; 3291 } 3292 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 3293 if (rc) 3294 return rc; 3295 3296 req->port_id = cpu_to_le16(pf->port_id); 3297 req->num_leds = bp->num_leds; 3298 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 3299 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3300 req->enables |= BNXT_LED_DFLT_ENABLES(i); 3301 led_cfg->led_id = bp->leds[i].led_id; 3302 led_cfg->led_state = led_state; 3303 led_cfg->led_blink_on = duration; 3304 led_cfg->led_blink_off = duration; 3305 led_cfg->led_group_id = bp->leds[i].led_group_id; 3306 } 3307 return hwrm_req_send(bp, req); 3308 } 3309 3310 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3311 { 3312 struct hwrm_selftest_irq_input *req; 3313 int rc; 3314 3315 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 3316 if (rc) 3317 return rc; 3318 3319 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3320 return hwrm_req_send(bp, req); 3321 } 3322 3323 static int bnxt_test_irq(struct bnxt *bp) 3324 { 3325 int i; 3326 3327 for (i = 0; i < bp->cp_nr_rings; i++) { 3328 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3329 int rc; 3330 3331 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3332 if (rc) 3333 return rc; 3334 } 3335 return 0; 3336 } 3337 3338 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3339 { 3340 struct hwrm_port_mac_cfg_input *req; 3341 int rc; 3342 3343 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 3344 if (rc) 3345 return rc; 3346 3347 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3348 if (enable) 3349 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3350 else 3351 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3352 return hwrm_req_send(bp, req); 3353 } 3354 3355 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3356 { 3357 struct hwrm_port_phy_qcaps_output *resp; 3358 struct hwrm_port_phy_qcaps_input *req; 3359 int rc; 3360 3361 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 3362 if (rc) 3363 return rc; 3364 3365 resp = hwrm_req_hold(bp, req); 3366 rc = hwrm_req_send(bp, req); 3367 if (!rc) 3368 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3369 3370 hwrm_req_drop(bp, req); 3371 return rc; 3372 } 3373 3374 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3375 struct hwrm_port_phy_cfg_input *req) 3376 { 3377 struct bnxt_link_info *link_info = &bp->link_info; 3378 u16 fw_advertising; 3379 u16 fw_speed; 3380 int rc; 3381 3382 if (!link_info->autoneg || 3383 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 3384 return 0; 3385 3386 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3387 if (rc) 3388 return rc; 3389 3390 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3391 if (BNXT_LINK_IS_UP(bp)) 3392 fw_speed = bp->link_info.link_speed; 3393 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3394 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3395 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3396 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3397 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3398 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3399 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3400 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3401 3402 req->force_link_speed = cpu_to_le16(fw_speed); 3403 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3404 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3405 rc = hwrm_req_send(bp, req); 3406 req->flags = 0; 3407 req->force_link_speed = cpu_to_le16(0); 3408 return rc; 3409 } 3410 3411 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3412 { 3413 struct hwrm_port_phy_cfg_input *req; 3414 int rc; 3415 3416 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3417 if (rc) 3418 return rc; 3419 3420 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 3421 hwrm_req_hold(bp, req); 3422 3423 if (enable) { 3424 bnxt_disable_an_for_lpbk(bp, req); 3425 if (ext) 3426 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3427 else 3428 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3429 } else { 3430 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3431 } 3432 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3433 rc = hwrm_req_send(bp, req); 3434 hwrm_req_drop(bp, req); 3435 return rc; 3436 } 3437 3438 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3439 u32 raw_cons, int pkt_size) 3440 { 3441 struct bnxt_napi *bnapi = cpr->bnapi; 3442 struct bnxt_rx_ring_info *rxr; 3443 struct bnxt_sw_rx_bd *rx_buf; 3444 struct rx_cmp *rxcmp; 3445 u16 cp_cons, cons; 3446 u8 *data; 3447 u32 len; 3448 int i; 3449 3450 rxr = bnapi->rx_ring; 3451 cp_cons = RING_CMP(raw_cons); 3452 rxcmp = (struct rx_cmp *) 3453 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3454 cons = rxcmp->rx_cmp_opaque; 3455 rx_buf = &rxr->rx_buf_ring[cons]; 3456 data = rx_buf->data_ptr; 3457 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3458 if (len != pkt_size) 3459 return -EIO; 3460 i = ETH_ALEN; 3461 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3462 return -EIO; 3463 i += ETH_ALEN; 3464 for ( ; i < pkt_size; i++) { 3465 if (data[i] != (u8)(i & 0xff)) 3466 return -EIO; 3467 } 3468 return 0; 3469 } 3470 3471 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3472 int pkt_size) 3473 { 3474 struct tx_cmp *txcmp; 3475 int rc = -EIO; 3476 u32 raw_cons; 3477 u32 cons; 3478 int i; 3479 3480 raw_cons = cpr->cp_raw_cons; 3481 for (i = 0; i < 200; i++) { 3482 cons = RING_CMP(raw_cons); 3483 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3484 3485 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3486 udelay(5); 3487 continue; 3488 } 3489 3490 /* The valid test of the entry must be done first before 3491 * reading any further. 3492 */ 3493 dma_rmb(); 3494 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3495 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3496 raw_cons = NEXT_RAW_CMP(raw_cons); 3497 raw_cons = NEXT_RAW_CMP(raw_cons); 3498 break; 3499 } 3500 raw_cons = NEXT_RAW_CMP(raw_cons); 3501 } 3502 cpr->cp_raw_cons = raw_cons; 3503 return rc; 3504 } 3505 3506 static int bnxt_run_loopback(struct bnxt *bp) 3507 { 3508 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3509 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3510 struct bnxt_cp_ring_info *cpr; 3511 int pkt_size, i = 0; 3512 struct sk_buff *skb; 3513 dma_addr_t map; 3514 u8 *data; 3515 int rc; 3516 3517 cpr = &rxr->bnapi->cp_ring; 3518 if (bp->flags & BNXT_FLAG_CHIP_P5) 3519 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3520 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3521 skb = netdev_alloc_skb(bp->dev, pkt_size); 3522 if (!skb) 3523 return -ENOMEM; 3524 data = skb_put(skb, pkt_size); 3525 ether_addr_copy(&data[i], bp->dev->dev_addr); 3526 i += ETH_ALEN; 3527 ether_addr_copy(&data[i], bp->dev->dev_addr); 3528 i += ETH_ALEN; 3529 for ( ; i < pkt_size; i++) 3530 data[i] = (u8)(i & 0xff); 3531 3532 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3533 DMA_TO_DEVICE); 3534 if (dma_mapping_error(&bp->pdev->dev, map)) { 3535 dev_kfree_skb(skb); 3536 return -EIO; 3537 } 3538 bnxt_xmit_bd(bp, txr, map, pkt_size); 3539 3540 /* Sync BD data before updating doorbell */ 3541 wmb(); 3542 3543 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3544 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3545 3546 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 3547 dev_kfree_skb(skb); 3548 return rc; 3549 } 3550 3551 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3552 { 3553 struct hwrm_selftest_exec_output *resp; 3554 struct hwrm_selftest_exec_input *req; 3555 int rc; 3556 3557 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 3558 if (rc) 3559 return rc; 3560 3561 hwrm_req_timeout(bp, req, bp->test_info->timeout); 3562 req->flags = test_mask; 3563 3564 resp = hwrm_req_hold(bp, req); 3565 rc = hwrm_req_send(bp, req); 3566 *test_results = resp->test_success; 3567 hwrm_req_drop(bp, req); 3568 return rc; 3569 } 3570 3571 #define BNXT_DRV_TESTS 4 3572 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3573 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3574 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3575 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3576 3577 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3578 u64 *buf) 3579 { 3580 struct bnxt *bp = netdev_priv(dev); 3581 bool do_ext_lpbk = false; 3582 bool offline = false; 3583 u8 test_results = 0; 3584 u8 test_mask = 0; 3585 int rc = 0, i; 3586 3587 if (!bp->num_tests || !BNXT_PF(bp)) 3588 return; 3589 memset(buf, 0, sizeof(u64) * bp->num_tests); 3590 if (!netif_running(dev)) { 3591 etest->flags |= ETH_TEST_FL_FAILED; 3592 return; 3593 } 3594 3595 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3596 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 3597 do_ext_lpbk = true; 3598 3599 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3600 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 3601 etest->flags |= ETH_TEST_FL_FAILED; 3602 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 3603 return; 3604 } 3605 offline = true; 3606 } 3607 3608 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3609 u8 bit_val = 1 << i; 3610 3611 if (!(bp->test_info->offline_mask & bit_val)) 3612 test_mask |= bit_val; 3613 else if (offline) 3614 test_mask |= bit_val; 3615 } 3616 if (!offline) { 3617 bnxt_run_fw_tests(bp, test_mask, &test_results); 3618 } else { 3619 bnxt_ulp_stop(bp); 3620 rc = bnxt_close_nic(bp, true, false); 3621 if (rc) { 3622 bnxt_ulp_start(bp, rc); 3623 return; 3624 } 3625 bnxt_run_fw_tests(bp, test_mask, &test_results); 3626 3627 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3628 bnxt_hwrm_mac_loopback(bp, true); 3629 msleep(250); 3630 rc = bnxt_half_open_nic(bp); 3631 if (rc) { 3632 bnxt_hwrm_mac_loopback(bp, false); 3633 etest->flags |= ETH_TEST_FL_FAILED; 3634 bnxt_ulp_start(bp, rc); 3635 return; 3636 } 3637 if (bnxt_run_loopback(bp)) 3638 etest->flags |= ETH_TEST_FL_FAILED; 3639 else 3640 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3641 3642 bnxt_hwrm_mac_loopback(bp, false); 3643 bnxt_hwrm_phy_loopback(bp, true, false); 3644 msleep(1000); 3645 if (bnxt_run_loopback(bp)) { 3646 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3647 etest->flags |= ETH_TEST_FL_FAILED; 3648 } 3649 if (do_ext_lpbk) { 3650 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3651 bnxt_hwrm_phy_loopback(bp, true, true); 3652 msleep(1000); 3653 if (bnxt_run_loopback(bp)) { 3654 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3655 etest->flags |= ETH_TEST_FL_FAILED; 3656 } 3657 } 3658 bnxt_hwrm_phy_loopback(bp, false, false); 3659 bnxt_half_close_nic(bp); 3660 rc = bnxt_open_nic(bp, true, true); 3661 bnxt_ulp_start(bp, rc); 3662 } 3663 if (rc || bnxt_test_irq(bp)) { 3664 buf[BNXT_IRQ_TEST_IDX] = 1; 3665 etest->flags |= ETH_TEST_FL_FAILED; 3666 } 3667 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3668 u8 bit_val = 1 << i; 3669 3670 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3671 buf[i] = 1; 3672 etest->flags |= ETH_TEST_FL_FAILED; 3673 } 3674 } 3675 } 3676 3677 static int bnxt_reset(struct net_device *dev, u32 *flags) 3678 { 3679 struct bnxt *bp = netdev_priv(dev); 3680 bool reload = false; 3681 u32 req = *flags; 3682 3683 if (!req) 3684 return -EINVAL; 3685 3686 if (!BNXT_PF(bp)) { 3687 netdev_err(dev, "Reset is not supported from a VF\n"); 3688 return -EOPNOTSUPP; 3689 } 3690 3691 if (pci_vfs_assigned(bp->pdev) && 3692 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3693 netdev_err(dev, 3694 "Reset not allowed when VFs are assigned to VMs\n"); 3695 return -EBUSY; 3696 } 3697 3698 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3699 /* This feature is not supported in older firmware versions */ 3700 if (bp->hwrm_spec_code >= 0x10803) { 3701 if (!bnxt_firmware_reset_chip(dev)) { 3702 netdev_info(dev, "Firmware reset request successful.\n"); 3703 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3704 reload = true; 3705 *flags &= ~BNXT_FW_RESET_CHIP; 3706 } 3707 } else if (req == BNXT_FW_RESET_CHIP) { 3708 return -EOPNOTSUPP; /* only request, fail hard */ 3709 } 3710 } 3711 3712 if (req & BNXT_FW_RESET_AP) { 3713 /* This feature is not supported in older firmware versions */ 3714 if (bp->hwrm_spec_code >= 0x10803) { 3715 if (!bnxt_firmware_reset_ap(dev)) { 3716 netdev_info(dev, "Reset application processor successful.\n"); 3717 reload = true; 3718 *flags &= ~BNXT_FW_RESET_AP; 3719 } 3720 } else if (req == BNXT_FW_RESET_AP) { 3721 return -EOPNOTSUPP; /* only request, fail hard */ 3722 } 3723 } 3724 3725 if (reload) 3726 netdev_info(dev, "Reload driver to complete reset\n"); 3727 3728 return 0; 3729 } 3730 3731 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3732 { 3733 struct bnxt *bp = netdev_priv(dev); 3734 3735 if (dump->flag > BNXT_DUMP_CRASH) { 3736 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3737 return -EINVAL; 3738 } 3739 3740 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3741 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3742 return -EOPNOTSUPP; 3743 } 3744 3745 bp->dump_flag = dump->flag; 3746 return 0; 3747 } 3748 3749 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3750 { 3751 struct bnxt *bp = netdev_priv(dev); 3752 3753 if (bp->hwrm_spec_code < 0x10801) 3754 return -EOPNOTSUPP; 3755 3756 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3757 bp->ver_resp.hwrm_fw_min_8b << 16 | 3758 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3759 bp->ver_resp.hwrm_fw_rsvd_8b; 3760 3761 dump->flag = bp->dump_flag; 3762 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 3763 return 0; 3764 } 3765 3766 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3767 void *buf) 3768 { 3769 struct bnxt *bp = netdev_priv(dev); 3770 3771 if (bp->hwrm_spec_code < 0x10801) 3772 return -EOPNOTSUPP; 3773 3774 memset(buf, 0, dump->len); 3775 3776 dump->flag = bp->dump_flag; 3777 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 3778 } 3779 3780 static int bnxt_get_ts_info(struct net_device *dev, 3781 struct ethtool_ts_info *info) 3782 { 3783 struct bnxt *bp = netdev_priv(dev); 3784 struct bnxt_ptp_cfg *ptp; 3785 3786 ptp = bp->ptp_cfg; 3787 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3788 SOF_TIMESTAMPING_RX_SOFTWARE | 3789 SOF_TIMESTAMPING_SOFTWARE; 3790 3791 info->phc_index = -1; 3792 if (!ptp) 3793 return 0; 3794 3795 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 3796 SOF_TIMESTAMPING_RX_HARDWARE | 3797 SOF_TIMESTAMPING_RAW_HARDWARE; 3798 if (ptp->ptp_clock) 3799 info->phc_index = ptp_clock_index(ptp->ptp_clock); 3800 3801 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 3802 3803 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3804 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 3805 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 3806 return 0; 3807 } 3808 3809 void bnxt_ethtool_init(struct bnxt *bp) 3810 { 3811 struct hwrm_selftest_qlist_output *resp; 3812 struct hwrm_selftest_qlist_input *req; 3813 struct bnxt_test_info *test_info; 3814 struct net_device *dev = bp->dev; 3815 int i, rc; 3816 3817 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3818 bnxt_get_pkgver(dev); 3819 3820 bp->num_tests = 0; 3821 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 3822 return; 3823 3824 test_info = bp->test_info; 3825 if (!test_info) { 3826 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3827 if (!test_info) 3828 return; 3829 bp->test_info = test_info; 3830 } 3831 3832 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 3833 return; 3834 3835 resp = hwrm_req_hold(bp, req); 3836 rc = hwrm_req_send_silent(bp, req); 3837 if (rc) 3838 goto ethtool_init_exit; 3839 3840 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3841 if (bp->num_tests > BNXT_MAX_TEST) 3842 bp->num_tests = BNXT_MAX_TEST; 3843 3844 test_info->offline_mask = resp->offline_tests; 3845 test_info->timeout = le16_to_cpu(resp->test_timeout); 3846 if (!test_info->timeout) 3847 test_info->timeout = HWRM_CMD_TIMEOUT; 3848 for (i = 0; i < bp->num_tests; i++) { 3849 char *str = test_info->string[i]; 3850 char *fw_str = resp->test0_name + i * 32; 3851 3852 if (i == BNXT_MACLPBK_TEST_IDX) { 3853 strcpy(str, "Mac loopback test (offline)"); 3854 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3855 strcpy(str, "Phy loopback test (offline)"); 3856 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3857 strcpy(str, "Ext loopback test (offline)"); 3858 } else if (i == BNXT_IRQ_TEST_IDX) { 3859 strcpy(str, "Interrupt_test (offline)"); 3860 } else { 3861 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3862 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3863 if (test_info->offline_mask & (1 << i)) 3864 strncat(str, " (offline)", 3865 ETH_GSTRING_LEN - strlen(str)); 3866 else 3867 strncat(str, " (online)", 3868 ETH_GSTRING_LEN - strlen(str)); 3869 } 3870 } 3871 3872 ethtool_init_exit: 3873 hwrm_req_drop(bp, req); 3874 } 3875 3876 static void bnxt_get_eth_phy_stats(struct net_device *dev, 3877 struct ethtool_eth_phy_stats *phy_stats) 3878 { 3879 struct bnxt *bp = netdev_priv(dev); 3880 u64 *rx; 3881 3882 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3883 return; 3884 3885 rx = bp->rx_port_stats_ext.sw_stats; 3886 phy_stats->SymbolErrorDuringCarrier = 3887 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 3888 } 3889 3890 static void bnxt_get_eth_mac_stats(struct net_device *dev, 3891 struct ethtool_eth_mac_stats *mac_stats) 3892 { 3893 struct bnxt *bp = netdev_priv(dev); 3894 u64 *rx, *tx; 3895 3896 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3897 return; 3898 3899 rx = bp->port_stats.sw_stats; 3900 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3901 3902 mac_stats->FramesReceivedOK = 3903 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 3904 mac_stats->FramesTransmittedOK = 3905 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 3906 mac_stats->FrameCheckSequenceErrors = 3907 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 3908 mac_stats->AlignmentErrors = 3909 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 3910 mac_stats->OutOfRangeLengthField = 3911 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 3912 } 3913 3914 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 3915 struct ethtool_eth_ctrl_stats *ctrl_stats) 3916 { 3917 struct bnxt *bp = netdev_priv(dev); 3918 u64 *rx; 3919 3920 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3921 return; 3922 3923 rx = bp->port_stats.sw_stats; 3924 ctrl_stats->MACControlFramesReceived = 3925 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 3926 } 3927 3928 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 3929 { 0, 64 }, 3930 { 65, 127 }, 3931 { 128, 255 }, 3932 { 256, 511 }, 3933 { 512, 1023 }, 3934 { 1024, 1518 }, 3935 { 1519, 2047 }, 3936 { 2048, 4095 }, 3937 { 4096, 9216 }, 3938 { 9217, 16383 }, 3939 {} 3940 }; 3941 3942 static void bnxt_get_rmon_stats(struct net_device *dev, 3943 struct ethtool_rmon_stats *rmon_stats, 3944 const struct ethtool_rmon_hist_range **ranges) 3945 { 3946 struct bnxt *bp = netdev_priv(dev); 3947 u64 *rx, *tx; 3948 3949 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3950 return; 3951 3952 rx = bp->port_stats.sw_stats; 3953 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3954 3955 rmon_stats->jabbers = 3956 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 3957 rmon_stats->oversize_pkts = 3958 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 3959 rmon_stats->undersize_pkts = 3960 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 3961 3962 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 3963 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 3964 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 3965 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 3966 rmon_stats->hist[4] = 3967 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 3968 rmon_stats->hist[5] = 3969 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 3970 rmon_stats->hist[6] = 3971 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 3972 rmon_stats->hist[7] = 3973 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 3974 rmon_stats->hist[8] = 3975 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 3976 rmon_stats->hist[9] = 3977 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 3978 3979 rmon_stats->hist_tx[0] = 3980 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 3981 rmon_stats->hist_tx[1] = 3982 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 3983 rmon_stats->hist_tx[2] = 3984 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 3985 rmon_stats->hist_tx[3] = 3986 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 3987 rmon_stats->hist_tx[4] = 3988 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 3989 rmon_stats->hist_tx[5] = 3990 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 3991 rmon_stats->hist_tx[6] = 3992 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 3993 rmon_stats->hist_tx[7] = 3994 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 3995 rmon_stats->hist_tx[8] = 3996 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 3997 rmon_stats->hist_tx[9] = 3998 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 3999 4000 *ranges = bnxt_rmon_ranges; 4001 } 4002 4003 void bnxt_ethtool_free(struct bnxt *bp) 4004 { 4005 kfree(bp->test_info); 4006 bp->test_info = NULL; 4007 } 4008 4009 const struct ethtool_ops bnxt_ethtool_ops = { 4010 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 4011 ETHTOOL_COALESCE_MAX_FRAMES | 4012 ETHTOOL_COALESCE_USECS_IRQ | 4013 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 4014 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 4015 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 4016 ETHTOOL_COALESCE_USE_CQE, 4017 .get_link_ksettings = bnxt_get_link_ksettings, 4018 .set_link_ksettings = bnxt_set_link_ksettings, 4019 .get_fec_stats = bnxt_get_fec_stats, 4020 .get_fecparam = bnxt_get_fecparam, 4021 .set_fecparam = bnxt_set_fecparam, 4022 .get_pause_stats = bnxt_get_pause_stats, 4023 .get_pauseparam = bnxt_get_pauseparam, 4024 .set_pauseparam = bnxt_set_pauseparam, 4025 .get_drvinfo = bnxt_get_drvinfo, 4026 .get_regs_len = bnxt_get_regs_len, 4027 .get_regs = bnxt_get_regs, 4028 .get_wol = bnxt_get_wol, 4029 .set_wol = bnxt_set_wol, 4030 .get_coalesce = bnxt_get_coalesce, 4031 .set_coalesce = bnxt_set_coalesce, 4032 .get_msglevel = bnxt_get_msglevel, 4033 .set_msglevel = bnxt_set_msglevel, 4034 .get_sset_count = bnxt_get_sset_count, 4035 .get_strings = bnxt_get_strings, 4036 .get_ethtool_stats = bnxt_get_ethtool_stats, 4037 .set_ringparam = bnxt_set_ringparam, 4038 .get_ringparam = bnxt_get_ringparam, 4039 .get_channels = bnxt_get_channels, 4040 .set_channels = bnxt_set_channels, 4041 .get_rxnfc = bnxt_get_rxnfc, 4042 .set_rxnfc = bnxt_set_rxnfc, 4043 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 4044 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 4045 .get_rxfh = bnxt_get_rxfh, 4046 .set_rxfh = bnxt_set_rxfh, 4047 .flash_device = bnxt_flash_device, 4048 .get_eeprom_len = bnxt_get_eeprom_len, 4049 .get_eeprom = bnxt_get_eeprom, 4050 .set_eeprom = bnxt_set_eeprom, 4051 .get_link = bnxt_get_link, 4052 .get_eee = bnxt_get_eee, 4053 .set_eee = bnxt_set_eee, 4054 .get_module_info = bnxt_get_module_info, 4055 .get_module_eeprom = bnxt_get_module_eeprom, 4056 .nway_reset = bnxt_nway_reset, 4057 .set_phys_id = bnxt_set_phys_id, 4058 .self_test = bnxt_self_test, 4059 .get_ts_info = bnxt_get_ts_info, 4060 .reset = bnxt_reset, 4061 .set_dump = bnxt_set_dump, 4062 .get_dump_flag = bnxt_get_dump_flag, 4063 .get_dump_data = bnxt_get_dump_data, 4064 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 4065 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 4066 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 4067 .get_rmon_stats = bnxt_get_rmon_stats, 4068 }; 4069