1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/linkmode.h> 15 #include <linux/interrupt.h> 16 #include <linux/pci.h> 17 #include <linux/etherdevice.h> 18 #include <linux/crc32.h> 19 #include <linux/firmware.h> 20 #include <linux/utsname.h> 21 #include <linux/time.h> 22 #include "bnxt_hsi.h" 23 #include "bnxt.h" 24 #include "bnxt_xdp.h" 25 #include "bnxt_ethtool.h" 26 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 27 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 28 #include "bnxt_coredump.h" 29 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 30 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 32 33 static u32 bnxt_get_msglevel(struct net_device *dev) 34 { 35 struct bnxt *bp = netdev_priv(dev); 36 37 return bp->msg_enable; 38 } 39 40 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 41 { 42 struct bnxt *bp = netdev_priv(dev); 43 44 bp->msg_enable = value; 45 } 46 47 static int bnxt_get_coalesce(struct net_device *dev, 48 struct ethtool_coalesce *coal) 49 { 50 struct bnxt *bp = netdev_priv(dev); 51 struct bnxt_coal *hw_coal; 52 u16 mult; 53 54 memset(coal, 0, sizeof(*coal)); 55 56 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 57 58 hw_coal = &bp->rx_coal; 59 mult = hw_coal->bufs_per_record; 60 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 61 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 62 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 63 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 64 65 hw_coal = &bp->tx_coal; 66 mult = hw_coal->bufs_per_record; 67 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 68 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 69 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 70 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 71 72 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 73 74 return 0; 75 } 76 77 static int bnxt_set_coalesce(struct net_device *dev, 78 struct ethtool_coalesce *coal) 79 { 80 struct bnxt *bp = netdev_priv(dev); 81 bool update_stats = false; 82 struct bnxt_coal *hw_coal; 83 int rc = 0; 84 u16 mult; 85 86 if (coal->use_adaptive_rx_coalesce) { 87 bp->flags |= BNXT_FLAG_DIM; 88 } else { 89 if (bp->flags & BNXT_FLAG_DIM) { 90 bp->flags &= ~(BNXT_FLAG_DIM); 91 goto reset_coalesce; 92 } 93 } 94 95 hw_coal = &bp->rx_coal; 96 mult = hw_coal->bufs_per_record; 97 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 98 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 99 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 100 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 101 102 hw_coal = &bp->tx_coal; 103 mult = hw_coal->bufs_per_record; 104 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 105 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 106 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 107 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 108 109 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 110 u32 stats_ticks = coal->stats_block_coalesce_usecs; 111 112 /* Allow 0, which means disable. */ 113 if (stats_ticks) 114 stats_ticks = clamp_t(u32, stats_ticks, 115 BNXT_MIN_STATS_COAL_TICKS, 116 BNXT_MAX_STATS_COAL_TICKS); 117 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 118 bp->stats_coal_ticks = stats_ticks; 119 if (bp->stats_coal_ticks) 120 bp->current_interval = 121 bp->stats_coal_ticks * HZ / 1000000; 122 else 123 bp->current_interval = BNXT_TIMER_INTERVAL; 124 update_stats = true; 125 } 126 127 reset_coalesce: 128 if (netif_running(dev)) { 129 if (update_stats) { 130 rc = bnxt_close_nic(bp, true, false); 131 if (!rc) 132 rc = bnxt_open_nic(bp, true, false); 133 } else { 134 rc = bnxt_hwrm_set_coal(bp); 135 } 136 } 137 138 return rc; 139 } 140 141 static const char * const bnxt_ring_rx_stats_str[] = { 142 "rx_ucast_packets", 143 "rx_mcast_packets", 144 "rx_bcast_packets", 145 "rx_discards", 146 "rx_errors", 147 "rx_ucast_bytes", 148 "rx_mcast_bytes", 149 "rx_bcast_bytes", 150 }; 151 152 static const char * const bnxt_ring_tx_stats_str[] = { 153 "tx_ucast_packets", 154 "tx_mcast_packets", 155 "tx_bcast_packets", 156 "tx_errors", 157 "tx_discards", 158 "tx_ucast_bytes", 159 "tx_mcast_bytes", 160 "tx_bcast_bytes", 161 }; 162 163 static const char * const bnxt_ring_tpa_stats_str[] = { 164 "tpa_packets", 165 "tpa_bytes", 166 "tpa_events", 167 "tpa_aborts", 168 }; 169 170 static const char * const bnxt_ring_tpa2_stats_str[] = { 171 "rx_tpa_eligible_pkt", 172 "rx_tpa_eligible_bytes", 173 "rx_tpa_pkt", 174 "rx_tpa_bytes", 175 "rx_tpa_errors", 176 "rx_tpa_events", 177 }; 178 179 static const char * const bnxt_rx_sw_stats_str[] = { 180 "rx_l4_csum_errors", 181 "rx_buf_errors", 182 }; 183 184 static const char * const bnxt_cmn_sw_stats_str[] = { 185 "missed_irqs", 186 }; 187 188 #define BNXT_RX_STATS_ENTRY(counter) \ 189 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 190 191 #define BNXT_TX_STATS_ENTRY(counter) \ 192 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 193 194 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 195 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 196 197 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 198 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 199 200 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 201 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 202 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 203 204 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 205 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 206 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 207 208 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 209 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 210 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 211 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 212 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 213 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 214 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 215 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 216 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 217 218 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 219 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 220 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 221 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 222 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 223 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 224 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 225 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 226 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 227 228 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 229 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 230 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 231 232 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 233 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 234 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 235 236 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 237 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 238 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 239 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 240 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 241 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 242 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 243 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 244 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 245 246 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 247 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 248 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 249 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 250 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 251 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 252 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 253 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 254 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 255 256 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 257 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 258 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 259 260 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 261 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 267 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 268 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 269 270 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 271 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 272 __stringify(counter##_pri##n) } 273 274 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 275 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 276 __stringify(counter##_pri##n) } 277 278 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 279 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 280 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 281 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 282 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 283 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 284 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 285 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 286 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 287 288 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 289 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 290 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 291 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 292 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 293 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 294 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 295 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 296 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 297 298 enum { 299 RX_TOTAL_DISCARDS, 300 TX_TOTAL_DISCARDS, 301 }; 302 303 static struct { 304 u64 counter; 305 char string[ETH_GSTRING_LEN]; 306 } bnxt_sw_func_stats[] = { 307 {0, "rx_total_discard_pkts"}, 308 {0, "tx_total_discard_pkts"}, 309 }; 310 311 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 312 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 313 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 314 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 315 316 static const struct { 317 long offset; 318 char string[ETH_GSTRING_LEN]; 319 } bnxt_port_stats_arr[] = { 320 BNXT_RX_STATS_ENTRY(rx_64b_frames), 321 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 322 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 323 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 324 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 325 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 326 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 327 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 328 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 329 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 330 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 331 BNXT_RX_STATS_ENTRY(rx_total_frames), 332 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 333 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 334 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 335 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 336 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 337 BNXT_RX_STATS_ENTRY(rx_pause_frames), 338 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 339 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 340 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 341 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 342 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 343 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 344 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 345 BNXT_RX_STATS_ENTRY(rx_good_frames), 346 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 354 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 355 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 357 BNXT_RX_STATS_ENTRY(rx_bytes), 358 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 359 BNXT_RX_STATS_ENTRY(rx_runt_frames), 360 BNXT_RX_STATS_ENTRY(rx_stat_discard), 361 BNXT_RX_STATS_ENTRY(rx_stat_err), 362 363 BNXT_TX_STATS_ENTRY(tx_64b_frames), 364 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 365 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 366 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 367 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 368 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 369 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 370 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 371 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 372 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 373 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 374 BNXT_TX_STATS_ENTRY(tx_good_frames), 375 BNXT_TX_STATS_ENTRY(tx_total_frames), 376 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 377 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 378 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 379 BNXT_TX_STATS_ENTRY(tx_pause_frames), 380 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 381 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 382 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 383 BNXT_TX_STATS_ENTRY(tx_err), 384 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 385 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 393 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 395 BNXT_TX_STATS_ENTRY(tx_total_collisions), 396 BNXT_TX_STATS_ENTRY(tx_bytes), 397 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 398 BNXT_TX_STATS_ENTRY(tx_stat_discard), 399 BNXT_TX_STATS_ENTRY(tx_stat_error), 400 }; 401 402 static const struct { 403 long offset; 404 char string[ETH_GSTRING_LEN]; 405 } bnxt_port_stats_ext_arr[] = { 406 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 407 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 408 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 409 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 410 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 411 BNXT_RX_STATS_EXT_COS_ENTRIES, 412 BNXT_RX_STATS_EXT_PFC_ENTRIES, 413 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 414 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 415 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 416 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 417 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 418 }; 419 420 static const struct { 421 long offset; 422 char string[ETH_GSTRING_LEN]; 423 } bnxt_tx_port_stats_ext_arr[] = { 424 BNXT_TX_STATS_EXT_COS_ENTRIES, 425 BNXT_TX_STATS_EXT_PFC_ENTRIES, 426 }; 427 428 static const struct { 429 long base_off; 430 char string[ETH_GSTRING_LEN]; 431 } bnxt_rx_bytes_pri_arr[] = { 432 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 433 }; 434 435 static const struct { 436 long base_off; 437 char string[ETH_GSTRING_LEN]; 438 } bnxt_rx_pkts_pri_arr[] = { 439 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 440 }; 441 442 static const struct { 443 long base_off; 444 char string[ETH_GSTRING_LEN]; 445 } bnxt_tx_bytes_pri_arr[] = { 446 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 447 }; 448 449 static const struct { 450 long base_off; 451 char string[ETH_GSTRING_LEN]; 452 } bnxt_tx_pkts_pri_arr[] = { 453 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 454 }; 455 456 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 457 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 458 #define BNXT_NUM_STATS_PRI \ 459 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 460 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 461 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 462 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 463 464 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 465 { 466 if (BNXT_SUPPORTS_TPA(bp)) { 467 if (bp->max_tpa_v2) { 468 if (BNXT_CHIP_P5_THOR(bp)) 469 return BNXT_NUM_TPA_RING_STATS_P5; 470 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 471 } 472 return BNXT_NUM_TPA_RING_STATS; 473 } 474 return 0; 475 } 476 477 static int bnxt_get_num_ring_stats(struct bnxt *bp) 478 { 479 int rx, tx, cmn; 480 481 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 482 bnxt_get_num_tpa_ring_stats(bp); 483 tx = NUM_RING_TX_HW_STATS; 484 cmn = NUM_RING_CMN_SW_STATS; 485 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 486 cmn * bp->cp_nr_rings; 487 } 488 489 static int bnxt_get_num_stats(struct bnxt *bp) 490 { 491 int num_stats = bnxt_get_num_ring_stats(bp); 492 493 num_stats += BNXT_NUM_SW_FUNC_STATS; 494 495 if (bp->flags & BNXT_FLAG_PORT_STATS) 496 num_stats += BNXT_NUM_PORT_STATS; 497 498 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 499 num_stats += bp->fw_rx_stats_ext_size + 500 bp->fw_tx_stats_ext_size; 501 if (bp->pri2cos_valid) 502 num_stats += BNXT_NUM_STATS_PRI; 503 } 504 505 return num_stats; 506 } 507 508 static int bnxt_get_sset_count(struct net_device *dev, int sset) 509 { 510 struct bnxt *bp = netdev_priv(dev); 511 512 switch (sset) { 513 case ETH_SS_STATS: 514 return bnxt_get_num_stats(bp); 515 case ETH_SS_TEST: 516 if (!bp->num_tests) 517 return -EOPNOTSUPP; 518 return bp->num_tests; 519 default: 520 return -EOPNOTSUPP; 521 } 522 } 523 524 static bool is_rx_ring(struct bnxt *bp, int ring_num) 525 { 526 return ring_num < bp->rx_nr_rings; 527 } 528 529 static bool is_tx_ring(struct bnxt *bp, int ring_num) 530 { 531 int tx_base = 0; 532 533 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 534 tx_base = bp->rx_nr_rings; 535 536 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 537 return true; 538 return false; 539 } 540 541 static void bnxt_get_ethtool_stats(struct net_device *dev, 542 struct ethtool_stats *stats, u64 *buf) 543 { 544 u32 i, j = 0; 545 struct bnxt *bp = netdev_priv(dev); 546 u32 tpa_stats; 547 548 if (!bp->bnapi) { 549 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 550 goto skip_ring_stats; 551 } 552 553 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 554 bnxt_sw_func_stats[i].counter = 0; 555 556 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 557 for (i = 0; i < bp->cp_nr_rings; i++) { 558 struct bnxt_napi *bnapi = bp->bnapi[i]; 559 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 560 u64 *sw_stats = cpr->stats.sw_stats; 561 u64 *sw; 562 int k; 563 564 if (is_rx_ring(bp, i)) { 565 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 566 buf[j] = sw_stats[k]; 567 } 568 if (is_tx_ring(bp, i)) { 569 k = NUM_RING_RX_HW_STATS; 570 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 571 j++, k++) 572 buf[j] = sw_stats[k]; 573 } 574 if (!tpa_stats || !is_rx_ring(bp, i)) 575 goto skip_tpa_ring_stats; 576 577 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 578 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 579 tpa_stats; j++, k++) 580 buf[j] = sw_stats[k]; 581 582 skip_tpa_ring_stats: 583 sw = (u64 *)&cpr->sw_stats.rx; 584 if (is_rx_ring(bp, i)) { 585 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 586 buf[j] = sw[k]; 587 } 588 589 sw = (u64 *)&cpr->sw_stats.cmn; 590 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 591 buf[j] = sw[k]; 592 593 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 594 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts); 595 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 596 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts); 597 } 598 599 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 600 buf[j] = bnxt_sw_func_stats[i].counter; 601 602 skip_ring_stats: 603 if (bp->flags & BNXT_FLAG_PORT_STATS) { 604 u64 *port_stats = bp->port_stats.sw_stats; 605 606 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 607 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 608 } 609 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 610 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 611 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 612 613 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 614 buf[j] = *(rx_port_stats_ext + 615 bnxt_port_stats_ext_arr[i].offset); 616 } 617 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 618 buf[j] = *(tx_port_stats_ext + 619 bnxt_tx_port_stats_ext_arr[i].offset); 620 } 621 if (bp->pri2cos_valid) { 622 for (i = 0; i < 8; i++, j++) { 623 long n = bnxt_rx_bytes_pri_arr[i].base_off + 624 bp->pri2cos_idx[i]; 625 626 buf[j] = *(rx_port_stats_ext + n); 627 } 628 for (i = 0; i < 8; i++, j++) { 629 long n = bnxt_rx_pkts_pri_arr[i].base_off + 630 bp->pri2cos_idx[i]; 631 632 buf[j] = *(rx_port_stats_ext + n); 633 } 634 for (i = 0; i < 8; i++, j++) { 635 long n = bnxt_tx_bytes_pri_arr[i].base_off + 636 bp->pri2cos_idx[i]; 637 638 buf[j] = *(tx_port_stats_ext + n); 639 } 640 for (i = 0; i < 8; i++, j++) { 641 long n = bnxt_tx_pkts_pri_arr[i].base_off + 642 bp->pri2cos_idx[i]; 643 644 buf[j] = *(tx_port_stats_ext + n); 645 } 646 } 647 } 648 } 649 650 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 651 { 652 struct bnxt *bp = netdev_priv(dev); 653 static const char * const *str; 654 u32 i, j, num_str; 655 656 switch (stringset) { 657 case ETH_SS_STATS: 658 for (i = 0; i < bp->cp_nr_rings; i++) { 659 if (is_rx_ring(bp, i)) { 660 num_str = NUM_RING_RX_HW_STATS; 661 for (j = 0; j < num_str; j++) { 662 sprintf(buf, "[%d]: %s", i, 663 bnxt_ring_rx_stats_str[j]); 664 buf += ETH_GSTRING_LEN; 665 } 666 } 667 if (is_tx_ring(bp, i)) { 668 num_str = NUM_RING_TX_HW_STATS; 669 for (j = 0; j < num_str; j++) { 670 sprintf(buf, "[%d]: %s", i, 671 bnxt_ring_tx_stats_str[j]); 672 buf += ETH_GSTRING_LEN; 673 } 674 } 675 num_str = bnxt_get_num_tpa_ring_stats(bp); 676 if (!num_str || !is_rx_ring(bp, i)) 677 goto skip_tpa_stats; 678 679 if (bp->max_tpa_v2) 680 str = bnxt_ring_tpa2_stats_str; 681 else 682 str = bnxt_ring_tpa_stats_str; 683 684 for (j = 0; j < num_str; j++) { 685 sprintf(buf, "[%d]: %s", i, str[j]); 686 buf += ETH_GSTRING_LEN; 687 } 688 skip_tpa_stats: 689 if (is_rx_ring(bp, i)) { 690 num_str = NUM_RING_RX_SW_STATS; 691 for (j = 0; j < num_str; j++) { 692 sprintf(buf, "[%d]: %s", i, 693 bnxt_rx_sw_stats_str[j]); 694 buf += ETH_GSTRING_LEN; 695 } 696 } 697 num_str = NUM_RING_CMN_SW_STATS; 698 for (j = 0; j < num_str; j++) { 699 sprintf(buf, "[%d]: %s", i, 700 bnxt_cmn_sw_stats_str[j]); 701 buf += ETH_GSTRING_LEN; 702 } 703 } 704 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 705 strcpy(buf, bnxt_sw_func_stats[i].string); 706 buf += ETH_GSTRING_LEN; 707 } 708 709 if (bp->flags & BNXT_FLAG_PORT_STATS) { 710 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 711 strcpy(buf, bnxt_port_stats_arr[i].string); 712 buf += ETH_GSTRING_LEN; 713 } 714 } 715 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 716 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 717 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 718 buf += ETH_GSTRING_LEN; 719 } 720 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 721 strcpy(buf, 722 bnxt_tx_port_stats_ext_arr[i].string); 723 buf += ETH_GSTRING_LEN; 724 } 725 if (bp->pri2cos_valid) { 726 for (i = 0; i < 8; i++) { 727 strcpy(buf, 728 bnxt_rx_bytes_pri_arr[i].string); 729 buf += ETH_GSTRING_LEN; 730 } 731 for (i = 0; i < 8; i++) { 732 strcpy(buf, 733 bnxt_rx_pkts_pri_arr[i].string); 734 buf += ETH_GSTRING_LEN; 735 } 736 for (i = 0; i < 8; i++) { 737 strcpy(buf, 738 bnxt_tx_bytes_pri_arr[i].string); 739 buf += ETH_GSTRING_LEN; 740 } 741 for (i = 0; i < 8; i++) { 742 strcpy(buf, 743 bnxt_tx_pkts_pri_arr[i].string); 744 buf += ETH_GSTRING_LEN; 745 } 746 } 747 } 748 break; 749 case ETH_SS_TEST: 750 if (bp->num_tests) 751 memcpy(buf, bp->test_info->string, 752 bp->num_tests * ETH_GSTRING_LEN); 753 break; 754 default: 755 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 756 stringset); 757 break; 758 } 759 } 760 761 static void bnxt_get_ringparam(struct net_device *dev, 762 struct ethtool_ringparam *ering) 763 { 764 struct bnxt *bp = netdev_priv(dev); 765 766 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 767 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 768 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 769 770 ering->rx_pending = bp->rx_ring_size; 771 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 772 ering->tx_pending = bp->tx_ring_size; 773 } 774 775 static int bnxt_set_ringparam(struct net_device *dev, 776 struct ethtool_ringparam *ering) 777 { 778 struct bnxt *bp = netdev_priv(dev); 779 780 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 781 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 782 (ering->tx_pending <= MAX_SKB_FRAGS)) 783 return -EINVAL; 784 785 if (netif_running(dev)) 786 bnxt_close_nic(bp, false, false); 787 788 bp->rx_ring_size = ering->rx_pending; 789 bp->tx_ring_size = ering->tx_pending; 790 bnxt_set_ring_params(bp); 791 792 if (netif_running(dev)) 793 return bnxt_open_nic(bp, false, false); 794 795 return 0; 796 } 797 798 static void bnxt_get_channels(struct net_device *dev, 799 struct ethtool_channels *channel) 800 { 801 struct bnxt *bp = netdev_priv(dev); 802 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 803 int max_rx_rings, max_tx_rings, tcs; 804 int max_tx_sch_inputs, tx_grps; 805 806 /* Get the most up-to-date max_tx_sch_inputs. */ 807 if (netif_running(dev) && BNXT_NEW_RM(bp)) 808 bnxt_hwrm_func_resc_qcaps(bp, false); 809 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 810 811 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 812 if (max_tx_sch_inputs) 813 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 814 815 tcs = netdev_get_num_tc(dev); 816 tx_grps = max(tcs, 1); 817 if (bp->tx_nr_rings_xdp) 818 tx_grps++; 819 max_tx_rings /= tx_grps; 820 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 821 822 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 823 max_rx_rings = 0; 824 max_tx_rings = 0; 825 } 826 if (max_tx_sch_inputs) 827 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 828 829 if (tcs > 1) 830 max_tx_rings /= tcs; 831 832 channel->max_rx = max_rx_rings; 833 channel->max_tx = max_tx_rings; 834 channel->max_other = 0; 835 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 836 channel->combined_count = bp->rx_nr_rings; 837 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 838 channel->combined_count--; 839 } else { 840 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 841 channel->rx_count = bp->rx_nr_rings; 842 channel->tx_count = bp->tx_nr_rings_per_tc; 843 } 844 } 845 } 846 847 static int bnxt_set_channels(struct net_device *dev, 848 struct ethtool_channels *channel) 849 { 850 struct bnxt *bp = netdev_priv(dev); 851 int req_tx_rings, req_rx_rings, tcs; 852 bool sh = false; 853 int tx_xdp = 0; 854 int rc = 0; 855 856 if (channel->other_count) 857 return -EINVAL; 858 859 if (!channel->combined_count && 860 (!channel->rx_count || !channel->tx_count)) 861 return -EINVAL; 862 863 if (channel->combined_count && 864 (channel->rx_count || channel->tx_count)) 865 return -EINVAL; 866 867 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 868 channel->tx_count)) 869 return -EINVAL; 870 871 if (channel->combined_count) 872 sh = true; 873 874 tcs = netdev_get_num_tc(dev); 875 876 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 877 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 878 if (bp->tx_nr_rings_xdp) { 879 if (!sh) { 880 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 881 return -EINVAL; 882 } 883 tx_xdp = req_rx_rings; 884 } 885 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 886 if (rc) { 887 netdev_warn(dev, "Unable to allocate the requested rings\n"); 888 return rc; 889 } 890 891 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 892 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 893 (dev->priv_flags & IFF_RXFH_CONFIGURED)) { 894 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 895 return -EINVAL; 896 } 897 898 if (netif_running(dev)) { 899 if (BNXT_PF(bp)) { 900 /* TODO CHIMP_FW: Send message to all VF's 901 * before PF unload 902 */ 903 } 904 rc = bnxt_close_nic(bp, true, false); 905 if (rc) { 906 netdev_err(bp->dev, "Set channel failure rc :%x\n", 907 rc); 908 return rc; 909 } 910 } 911 912 if (sh) { 913 bp->flags |= BNXT_FLAG_SHARED_RINGS; 914 bp->rx_nr_rings = channel->combined_count; 915 bp->tx_nr_rings_per_tc = channel->combined_count; 916 } else { 917 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 918 bp->rx_nr_rings = channel->rx_count; 919 bp->tx_nr_rings_per_tc = channel->tx_count; 920 } 921 bp->tx_nr_rings_xdp = tx_xdp; 922 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 923 if (tcs > 1) 924 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 925 926 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 927 bp->tx_nr_rings + bp->rx_nr_rings; 928 929 /* After changing number of rx channels, update NTUPLE feature. */ 930 netdev_update_features(dev); 931 if (netif_running(dev)) { 932 rc = bnxt_open_nic(bp, true, false); 933 if ((!rc) && BNXT_PF(bp)) { 934 /* TODO CHIMP_FW: Send message to all VF's 935 * to renable 936 */ 937 } 938 } else { 939 rc = bnxt_reserve_rings(bp, true); 940 } 941 942 return rc; 943 } 944 945 #ifdef CONFIG_RFS_ACCEL 946 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 947 u32 *rule_locs) 948 { 949 int i, j = 0; 950 951 cmd->data = bp->ntp_fltr_count; 952 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 953 struct hlist_head *head; 954 struct bnxt_ntuple_filter *fltr; 955 956 head = &bp->ntp_fltr_hash_tbl[i]; 957 rcu_read_lock(); 958 hlist_for_each_entry_rcu(fltr, head, hash) { 959 if (j == cmd->rule_cnt) 960 break; 961 rule_locs[j++] = fltr->sw_id; 962 } 963 rcu_read_unlock(); 964 if (j == cmd->rule_cnt) 965 break; 966 } 967 cmd->rule_cnt = j; 968 return 0; 969 } 970 971 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 972 { 973 struct ethtool_rx_flow_spec *fs = 974 (struct ethtool_rx_flow_spec *)&cmd->fs; 975 struct bnxt_ntuple_filter *fltr; 976 struct flow_keys *fkeys; 977 int i, rc = -EINVAL; 978 979 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 980 return rc; 981 982 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 983 struct hlist_head *head; 984 985 head = &bp->ntp_fltr_hash_tbl[i]; 986 rcu_read_lock(); 987 hlist_for_each_entry_rcu(fltr, head, hash) { 988 if (fltr->sw_id == fs->location) 989 goto fltr_found; 990 } 991 rcu_read_unlock(); 992 } 993 return rc; 994 995 fltr_found: 996 fkeys = &fltr->fkeys; 997 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 998 if (fkeys->basic.ip_proto == IPPROTO_TCP) 999 fs->flow_type = TCP_V4_FLOW; 1000 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1001 fs->flow_type = UDP_V4_FLOW; 1002 else 1003 goto fltr_err; 1004 1005 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1006 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1007 1008 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1009 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1010 1011 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1012 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1013 1014 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1015 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1016 } else { 1017 int i; 1018 1019 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1020 fs->flow_type = TCP_V6_FLOW; 1021 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1022 fs->flow_type = UDP_V6_FLOW; 1023 else 1024 goto fltr_err; 1025 1026 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1027 fkeys->addrs.v6addrs.src; 1028 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1029 fkeys->addrs.v6addrs.dst; 1030 for (i = 0; i < 4; i++) { 1031 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1032 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1033 } 1034 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1035 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1036 1037 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1038 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1039 } 1040 1041 fs->ring_cookie = fltr->rxq; 1042 rc = 0; 1043 1044 fltr_err: 1045 rcu_read_unlock(); 1046 1047 return rc; 1048 } 1049 #endif 1050 1051 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1052 { 1053 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1054 return RXH_IP_SRC | RXH_IP_DST; 1055 return 0; 1056 } 1057 1058 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1059 { 1060 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1061 return RXH_IP_SRC | RXH_IP_DST; 1062 return 0; 1063 } 1064 1065 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1066 { 1067 cmd->data = 0; 1068 switch (cmd->flow_type) { 1069 case TCP_V4_FLOW: 1070 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1071 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1072 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1073 cmd->data |= get_ethtool_ipv4_rss(bp); 1074 break; 1075 case UDP_V4_FLOW: 1076 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1077 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1078 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1079 fallthrough; 1080 case SCTP_V4_FLOW: 1081 case AH_ESP_V4_FLOW: 1082 case AH_V4_FLOW: 1083 case ESP_V4_FLOW: 1084 case IPV4_FLOW: 1085 cmd->data |= get_ethtool_ipv4_rss(bp); 1086 break; 1087 1088 case TCP_V6_FLOW: 1089 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1090 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1091 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1092 cmd->data |= get_ethtool_ipv6_rss(bp); 1093 break; 1094 case UDP_V6_FLOW: 1095 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1096 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1097 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1098 fallthrough; 1099 case SCTP_V6_FLOW: 1100 case AH_ESP_V6_FLOW: 1101 case AH_V6_FLOW: 1102 case ESP_V6_FLOW: 1103 case IPV6_FLOW: 1104 cmd->data |= get_ethtool_ipv6_rss(bp); 1105 break; 1106 } 1107 return 0; 1108 } 1109 1110 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1111 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1112 1113 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1114 { 1115 u32 rss_hash_cfg = bp->rss_hash_cfg; 1116 int tuple, rc = 0; 1117 1118 if (cmd->data == RXH_4TUPLE) 1119 tuple = 4; 1120 else if (cmd->data == RXH_2TUPLE) 1121 tuple = 2; 1122 else if (!cmd->data) 1123 tuple = 0; 1124 else 1125 return -EINVAL; 1126 1127 if (cmd->flow_type == TCP_V4_FLOW) { 1128 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1129 if (tuple == 4) 1130 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1131 } else if (cmd->flow_type == UDP_V4_FLOW) { 1132 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1133 return -EINVAL; 1134 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1135 if (tuple == 4) 1136 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1137 } else if (cmd->flow_type == TCP_V6_FLOW) { 1138 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1139 if (tuple == 4) 1140 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1141 } else if (cmd->flow_type == UDP_V6_FLOW) { 1142 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1143 return -EINVAL; 1144 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1145 if (tuple == 4) 1146 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1147 } else if (tuple == 4) { 1148 return -EINVAL; 1149 } 1150 1151 switch (cmd->flow_type) { 1152 case TCP_V4_FLOW: 1153 case UDP_V4_FLOW: 1154 case SCTP_V4_FLOW: 1155 case AH_ESP_V4_FLOW: 1156 case AH_V4_FLOW: 1157 case ESP_V4_FLOW: 1158 case IPV4_FLOW: 1159 if (tuple == 2) 1160 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1161 else if (!tuple) 1162 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1163 break; 1164 1165 case TCP_V6_FLOW: 1166 case UDP_V6_FLOW: 1167 case SCTP_V6_FLOW: 1168 case AH_ESP_V6_FLOW: 1169 case AH_V6_FLOW: 1170 case ESP_V6_FLOW: 1171 case IPV6_FLOW: 1172 if (tuple == 2) 1173 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1174 else if (!tuple) 1175 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1176 break; 1177 } 1178 1179 if (bp->rss_hash_cfg == rss_hash_cfg) 1180 return 0; 1181 1182 bp->rss_hash_cfg = rss_hash_cfg; 1183 if (netif_running(bp->dev)) { 1184 bnxt_close_nic(bp, false, false); 1185 rc = bnxt_open_nic(bp, false, false); 1186 } 1187 return rc; 1188 } 1189 1190 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1191 u32 *rule_locs) 1192 { 1193 struct bnxt *bp = netdev_priv(dev); 1194 int rc = 0; 1195 1196 switch (cmd->cmd) { 1197 #ifdef CONFIG_RFS_ACCEL 1198 case ETHTOOL_GRXRINGS: 1199 cmd->data = bp->rx_nr_rings; 1200 break; 1201 1202 case ETHTOOL_GRXCLSRLCNT: 1203 cmd->rule_cnt = bp->ntp_fltr_count; 1204 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1205 break; 1206 1207 case ETHTOOL_GRXCLSRLALL: 1208 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1209 break; 1210 1211 case ETHTOOL_GRXCLSRULE: 1212 rc = bnxt_grxclsrule(bp, cmd); 1213 break; 1214 #endif 1215 1216 case ETHTOOL_GRXFH: 1217 rc = bnxt_grxfh(bp, cmd); 1218 break; 1219 1220 default: 1221 rc = -EOPNOTSUPP; 1222 break; 1223 } 1224 1225 return rc; 1226 } 1227 1228 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1229 { 1230 struct bnxt *bp = netdev_priv(dev); 1231 int rc; 1232 1233 switch (cmd->cmd) { 1234 case ETHTOOL_SRXFH: 1235 rc = bnxt_srxfh(bp, cmd); 1236 break; 1237 1238 default: 1239 rc = -EOPNOTSUPP; 1240 break; 1241 } 1242 return rc; 1243 } 1244 1245 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1246 { 1247 struct bnxt *bp = netdev_priv(dev); 1248 1249 if (bp->flags & BNXT_FLAG_CHIP_P5) 1250 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1251 return HW_HASH_INDEX_SIZE; 1252 } 1253 1254 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1255 { 1256 return HW_HASH_KEY_SIZE; 1257 } 1258 1259 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1260 u8 *hfunc) 1261 { 1262 struct bnxt *bp = netdev_priv(dev); 1263 struct bnxt_vnic_info *vnic; 1264 u32 i, tbl_size; 1265 1266 if (hfunc) 1267 *hfunc = ETH_RSS_HASH_TOP; 1268 1269 if (!bp->vnic_info) 1270 return 0; 1271 1272 vnic = &bp->vnic_info[0]; 1273 if (indir && bp->rss_indir_tbl) { 1274 tbl_size = bnxt_get_rxfh_indir_size(dev); 1275 for (i = 0; i < tbl_size; i++) 1276 indir[i] = bp->rss_indir_tbl[i]; 1277 } 1278 1279 if (key && vnic->rss_hash_key) 1280 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1281 1282 return 0; 1283 } 1284 1285 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1286 const u8 *key, const u8 hfunc) 1287 { 1288 struct bnxt *bp = netdev_priv(dev); 1289 int rc = 0; 1290 1291 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1292 return -EOPNOTSUPP; 1293 1294 if (key) 1295 return -EOPNOTSUPP; 1296 1297 if (indir) { 1298 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1299 1300 for (i = 0; i < tbl_size; i++) 1301 bp->rss_indir_tbl[i] = indir[i]; 1302 pad = bp->rss_indir_tbl_entries - tbl_size; 1303 if (pad) 1304 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1305 } 1306 1307 if (netif_running(bp->dev)) { 1308 bnxt_close_nic(bp, false, false); 1309 rc = bnxt_open_nic(bp, false, false); 1310 } 1311 return rc; 1312 } 1313 1314 static void bnxt_get_drvinfo(struct net_device *dev, 1315 struct ethtool_drvinfo *info) 1316 { 1317 struct bnxt *bp = netdev_priv(dev); 1318 1319 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1320 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1321 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1322 info->n_stats = bnxt_get_num_stats(bp); 1323 info->testinfo_len = bp->num_tests; 1324 /* TODO CHIMP_FW: eeprom dump details */ 1325 info->eedump_len = 0; 1326 /* TODO CHIMP FW: reg dump details */ 1327 info->regdump_len = 0; 1328 } 1329 1330 static int bnxt_get_regs_len(struct net_device *dev) 1331 { 1332 struct bnxt *bp = netdev_priv(dev); 1333 int reg_len; 1334 1335 if (!BNXT_PF(bp)) 1336 return -EOPNOTSUPP; 1337 1338 reg_len = BNXT_PXP_REG_LEN; 1339 1340 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1341 reg_len += sizeof(struct pcie_ctx_hw_stats); 1342 1343 return reg_len; 1344 } 1345 1346 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1347 void *_p) 1348 { 1349 struct pcie_ctx_hw_stats *hw_pcie_stats; 1350 struct hwrm_pcie_qstats_input req = {0}; 1351 struct bnxt *bp = netdev_priv(dev); 1352 dma_addr_t hw_pcie_stats_addr; 1353 int rc; 1354 1355 regs->version = 0; 1356 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1357 1358 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1359 return; 1360 1361 hw_pcie_stats = dma_alloc_coherent(&bp->pdev->dev, 1362 sizeof(*hw_pcie_stats), 1363 &hw_pcie_stats_addr, GFP_KERNEL); 1364 if (!hw_pcie_stats) 1365 return; 1366 1367 regs->version = 1; 1368 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 1369 req.pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1370 req.pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1371 mutex_lock(&bp->hwrm_cmd_lock); 1372 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1373 if (!rc) { 1374 __le64 *src = (__le64 *)hw_pcie_stats; 1375 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1376 int i; 1377 1378 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1379 dst[i] = le64_to_cpu(src[i]); 1380 } 1381 mutex_unlock(&bp->hwrm_cmd_lock); 1382 dma_free_coherent(&bp->pdev->dev, sizeof(*hw_pcie_stats), hw_pcie_stats, 1383 hw_pcie_stats_addr); 1384 } 1385 1386 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1387 { 1388 struct bnxt *bp = netdev_priv(dev); 1389 1390 wol->supported = 0; 1391 wol->wolopts = 0; 1392 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1393 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1394 wol->supported = WAKE_MAGIC; 1395 if (bp->wol) 1396 wol->wolopts = WAKE_MAGIC; 1397 } 1398 } 1399 1400 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1401 { 1402 struct bnxt *bp = netdev_priv(dev); 1403 1404 if (wol->wolopts & ~WAKE_MAGIC) 1405 return -EINVAL; 1406 1407 if (wol->wolopts & WAKE_MAGIC) { 1408 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1409 return -EINVAL; 1410 if (!bp->wol) { 1411 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1412 return -EBUSY; 1413 bp->wol = 1; 1414 } 1415 } else { 1416 if (bp->wol) { 1417 if (bnxt_hwrm_free_wol_fltr(bp)) 1418 return -EBUSY; 1419 bp->wol = 0; 1420 } 1421 } 1422 return 0; 1423 } 1424 1425 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1426 { 1427 u32 speed_mask = 0; 1428 1429 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1430 /* set the advertised speeds */ 1431 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1432 speed_mask |= ADVERTISED_100baseT_Full; 1433 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1434 speed_mask |= ADVERTISED_1000baseT_Full; 1435 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1436 speed_mask |= ADVERTISED_2500baseX_Full; 1437 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1438 speed_mask |= ADVERTISED_10000baseT_Full; 1439 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1440 speed_mask |= ADVERTISED_40000baseCR4_Full; 1441 1442 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1443 speed_mask |= ADVERTISED_Pause; 1444 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1445 speed_mask |= ADVERTISED_Asym_Pause; 1446 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1447 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1448 1449 return speed_mask; 1450 } 1451 1452 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1453 { \ 1454 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1455 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1456 100baseT_Full); \ 1457 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1458 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1459 1000baseT_Full); \ 1460 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1461 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1462 10000baseT_Full); \ 1463 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1464 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1465 25000baseCR_Full); \ 1466 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1467 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1468 40000baseCR4_Full);\ 1469 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1470 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1471 50000baseCR2_Full);\ 1472 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1473 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1474 100000baseCR4_Full);\ 1475 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1476 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1477 Pause); \ 1478 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1479 ethtool_link_ksettings_add_link_mode( \ 1480 lk_ksettings, name, Asym_Pause);\ 1481 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1482 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1483 Asym_Pause); \ 1484 } \ 1485 } 1486 1487 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1488 { \ 1489 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1490 100baseT_Full) || \ 1491 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1492 100baseT_Half)) \ 1493 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1494 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1495 1000baseT_Full) || \ 1496 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1497 1000baseT_Half)) \ 1498 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1499 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1500 10000baseT_Full)) \ 1501 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1502 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1503 25000baseCR_Full)) \ 1504 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1505 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1506 40000baseCR4_Full)) \ 1507 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1508 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1509 50000baseCR2_Full)) \ 1510 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1511 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1512 100000baseCR4_Full)) \ 1513 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1514 } 1515 1516 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1517 { \ 1518 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \ 1519 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1520 50000baseCR_Full); \ 1521 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \ 1522 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1523 100000baseCR2_Full);\ 1524 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \ 1525 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1526 200000baseCR4_Full);\ 1527 } 1528 1529 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1530 { \ 1531 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1532 50000baseCR_Full)) \ 1533 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \ 1534 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1535 100000baseCR2_Full)) \ 1536 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \ 1537 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1538 200000baseCR4_Full)) \ 1539 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \ 1540 } 1541 1542 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1543 struct ethtool_link_ksettings *lk_ksettings) 1544 { 1545 u16 fec_cfg = link_info->fec_cfg; 1546 1547 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1548 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1549 lk_ksettings->link_modes.advertising); 1550 return; 1551 } 1552 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1553 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1554 lk_ksettings->link_modes.advertising); 1555 if (fec_cfg & BNXT_FEC_ENC_RS) 1556 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1557 lk_ksettings->link_modes.advertising); 1558 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1559 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1560 lk_ksettings->link_modes.advertising); 1561 } 1562 1563 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1564 struct ethtool_link_ksettings *lk_ksettings) 1565 { 1566 u16 fw_speeds = link_info->advertising; 1567 u8 fw_pause = 0; 1568 1569 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1570 fw_pause = link_info->auto_pause_setting; 1571 1572 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1573 fw_speeds = link_info->advertising_pam4; 1574 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising); 1575 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 1576 } 1577 1578 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1579 struct ethtool_link_ksettings *lk_ksettings) 1580 { 1581 u16 fw_speeds = link_info->lp_auto_link_speeds; 1582 u8 fw_pause = 0; 1583 1584 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1585 fw_pause = link_info->lp_pause; 1586 1587 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1588 lp_advertising); 1589 fw_speeds = link_info->lp_auto_pam4_link_speeds; 1590 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising); 1591 } 1592 1593 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1594 struct ethtool_link_ksettings *lk_ksettings) 1595 { 1596 u16 fec_cfg = link_info->fec_cfg; 1597 1598 if (fec_cfg & BNXT_FEC_NONE) { 1599 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1600 lk_ksettings->link_modes.supported); 1601 return; 1602 } 1603 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1604 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1605 lk_ksettings->link_modes.supported); 1606 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1607 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1608 lk_ksettings->link_modes.supported); 1609 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1610 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1611 lk_ksettings->link_modes.supported); 1612 } 1613 1614 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1615 struct ethtool_link_ksettings *lk_ksettings) 1616 { 1617 u16 fw_speeds = link_info->support_speeds; 1618 1619 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1620 fw_speeds = link_info->support_pam4_speeds; 1621 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported); 1622 1623 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1624 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1625 Asym_Pause); 1626 1627 if (link_info->support_auto_speeds || 1628 link_info->support_pam4_auto_speeds) 1629 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1630 Autoneg); 1631 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 1632 } 1633 1634 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1635 { 1636 switch (fw_link_speed) { 1637 case BNXT_LINK_SPEED_100MB: 1638 return SPEED_100; 1639 case BNXT_LINK_SPEED_1GB: 1640 return SPEED_1000; 1641 case BNXT_LINK_SPEED_2_5GB: 1642 return SPEED_2500; 1643 case BNXT_LINK_SPEED_10GB: 1644 return SPEED_10000; 1645 case BNXT_LINK_SPEED_20GB: 1646 return SPEED_20000; 1647 case BNXT_LINK_SPEED_25GB: 1648 return SPEED_25000; 1649 case BNXT_LINK_SPEED_40GB: 1650 return SPEED_40000; 1651 case BNXT_LINK_SPEED_50GB: 1652 return SPEED_50000; 1653 case BNXT_LINK_SPEED_100GB: 1654 return SPEED_100000; 1655 default: 1656 return SPEED_UNKNOWN; 1657 } 1658 } 1659 1660 static int bnxt_get_link_ksettings(struct net_device *dev, 1661 struct ethtool_link_ksettings *lk_ksettings) 1662 { 1663 struct bnxt *bp = netdev_priv(dev); 1664 struct bnxt_link_info *link_info = &bp->link_info; 1665 struct ethtool_link_settings *base = &lk_ksettings->base; 1666 u32 ethtool_speed; 1667 1668 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1669 mutex_lock(&bp->link_lock); 1670 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1671 1672 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1673 if (link_info->autoneg) { 1674 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1675 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1676 advertising, Autoneg); 1677 base->autoneg = AUTONEG_ENABLE; 1678 base->duplex = DUPLEX_UNKNOWN; 1679 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1680 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1681 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1682 base->duplex = DUPLEX_FULL; 1683 else 1684 base->duplex = DUPLEX_HALF; 1685 } 1686 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1687 } else { 1688 base->autoneg = AUTONEG_DISABLE; 1689 ethtool_speed = 1690 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1691 base->duplex = DUPLEX_HALF; 1692 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1693 base->duplex = DUPLEX_FULL; 1694 } 1695 base->speed = ethtool_speed; 1696 1697 base->port = PORT_NONE; 1698 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1699 base->port = PORT_TP; 1700 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1701 TP); 1702 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1703 TP); 1704 } else { 1705 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1706 FIBRE); 1707 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1708 FIBRE); 1709 1710 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1711 base->port = PORT_DA; 1712 else if (link_info->media_type == 1713 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1714 base->port = PORT_FIBRE; 1715 } 1716 base->phy_address = link_info->phy_addr; 1717 mutex_unlock(&bp->link_lock); 1718 1719 return 0; 1720 } 1721 1722 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed) 1723 { 1724 struct bnxt *bp = netdev_priv(dev); 1725 struct bnxt_link_info *link_info = &bp->link_info; 1726 u16 support_pam4_spds = link_info->support_pam4_speeds; 1727 u16 support_spds = link_info->support_speeds; 1728 u8 sig_mode = BNXT_SIG_MODE_NRZ; 1729 u16 fw_speed = 0; 1730 1731 switch (ethtool_speed) { 1732 case SPEED_100: 1733 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1734 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 1735 break; 1736 case SPEED_1000: 1737 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1738 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 1739 break; 1740 case SPEED_2500: 1741 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1742 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 1743 break; 1744 case SPEED_10000: 1745 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1746 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 1747 break; 1748 case SPEED_20000: 1749 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1750 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 1751 break; 1752 case SPEED_25000: 1753 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1754 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 1755 break; 1756 case SPEED_40000: 1757 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1758 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 1759 break; 1760 case SPEED_50000: 1761 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) { 1762 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 1763 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 1764 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 1765 sig_mode = BNXT_SIG_MODE_PAM4; 1766 } 1767 break; 1768 case SPEED_100000: 1769 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) { 1770 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 1771 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 1772 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 1773 sig_mode = BNXT_SIG_MODE_PAM4; 1774 } 1775 break; 1776 case SPEED_200000: 1777 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 1778 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 1779 sig_mode = BNXT_SIG_MODE_PAM4; 1780 } 1781 break; 1782 } 1783 1784 if (!fw_speed) { 1785 netdev_err(dev, "unsupported speed!\n"); 1786 return -EINVAL; 1787 } 1788 1789 if (link_info->req_link_speed == fw_speed && 1790 link_info->req_signal_mode == sig_mode && 1791 link_info->autoneg == 0) 1792 return -EALREADY; 1793 1794 link_info->req_link_speed = fw_speed; 1795 link_info->req_signal_mode = sig_mode; 1796 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1797 link_info->autoneg = 0; 1798 link_info->advertising = 0; 1799 link_info->advertising_pam4 = 0; 1800 1801 return 0; 1802 } 1803 1804 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1805 { 1806 u16 fw_speed_mask = 0; 1807 1808 /* only support autoneg at speed 100, 1000, and 10000 */ 1809 if (advertising & (ADVERTISED_100baseT_Full | 1810 ADVERTISED_100baseT_Half)) { 1811 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1812 } 1813 if (advertising & (ADVERTISED_1000baseT_Full | 1814 ADVERTISED_1000baseT_Half)) { 1815 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1816 } 1817 if (advertising & ADVERTISED_10000baseT_Full) 1818 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1819 1820 if (advertising & ADVERTISED_40000baseCR4_Full) 1821 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1822 1823 return fw_speed_mask; 1824 } 1825 1826 static int bnxt_set_link_ksettings(struct net_device *dev, 1827 const struct ethtool_link_ksettings *lk_ksettings) 1828 { 1829 struct bnxt *bp = netdev_priv(dev); 1830 struct bnxt_link_info *link_info = &bp->link_info; 1831 const struct ethtool_link_settings *base = &lk_ksettings->base; 1832 bool set_pause = false; 1833 u32 speed; 1834 int rc = 0; 1835 1836 if (!BNXT_PHY_CFG_ABLE(bp)) 1837 return -EOPNOTSUPP; 1838 1839 mutex_lock(&bp->link_lock); 1840 if (base->autoneg == AUTONEG_ENABLE) { 1841 link_info->advertising = 0; 1842 link_info->advertising_pam4 = 0; 1843 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings, 1844 advertising); 1845 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4, 1846 lk_ksettings, advertising); 1847 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1848 if (!link_info->advertising && !link_info->advertising_pam4) { 1849 link_info->advertising = link_info->support_auto_speeds; 1850 link_info->advertising_pam4 = 1851 link_info->support_pam4_auto_speeds; 1852 } 1853 /* any change to autoneg will cause link change, therefore the 1854 * driver should put back the original pause setting in autoneg 1855 */ 1856 set_pause = true; 1857 } else { 1858 u8 phy_type = link_info->phy_type; 1859 1860 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1861 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1862 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1863 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1864 rc = -EINVAL; 1865 goto set_setting_exit; 1866 } 1867 if (base->duplex == DUPLEX_HALF) { 1868 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1869 rc = -EINVAL; 1870 goto set_setting_exit; 1871 } 1872 speed = base->speed; 1873 rc = bnxt_force_link_speed(dev, speed); 1874 if (rc) { 1875 if (rc == -EALREADY) 1876 rc = 0; 1877 goto set_setting_exit; 1878 } 1879 } 1880 1881 if (netif_running(dev)) 1882 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1883 1884 set_setting_exit: 1885 mutex_unlock(&bp->link_lock); 1886 return rc; 1887 } 1888 1889 static int bnxt_get_fecparam(struct net_device *dev, 1890 struct ethtool_fecparam *fec) 1891 { 1892 struct bnxt *bp = netdev_priv(dev); 1893 struct bnxt_link_info *link_info; 1894 u8 active_fec; 1895 u16 fec_cfg; 1896 1897 link_info = &bp->link_info; 1898 fec_cfg = link_info->fec_cfg; 1899 active_fec = link_info->active_fec_sig_mode & 1900 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 1901 if (fec_cfg & BNXT_FEC_NONE) { 1902 fec->fec = ETHTOOL_FEC_NONE; 1903 fec->active_fec = ETHTOOL_FEC_NONE; 1904 return 0; 1905 } 1906 if (fec_cfg & BNXT_FEC_AUTONEG) 1907 fec->fec |= ETHTOOL_FEC_AUTO; 1908 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1909 fec->fec |= ETHTOOL_FEC_BASER; 1910 if (fec_cfg & BNXT_FEC_ENC_RS) 1911 fec->fec |= ETHTOOL_FEC_RS; 1912 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1913 fec->fec |= ETHTOOL_FEC_LLRS; 1914 1915 switch (active_fec) { 1916 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 1917 fec->active_fec |= ETHTOOL_FEC_BASER; 1918 break; 1919 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 1920 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 1921 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 1922 fec->active_fec |= ETHTOOL_FEC_RS; 1923 break; 1924 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 1925 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 1926 fec->active_fec |= ETHTOOL_FEC_LLRS; 1927 break; 1928 } 1929 return 0; 1930 } 1931 1932 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 1933 u32 fec) 1934 { 1935 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 1936 1937 if (fec & ETHTOOL_FEC_BASER) 1938 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 1939 else if (fec & ETHTOOL_FEC_RS) 1940 fw_fec |= BNXT_FEC_RS_ON(link_info); 1941 else if (fec & ETHTOOL_FEC_LLRS) 1942 fw_fec |= BNXT_FEC_LLRS_ON; 1943 return fw_fec; 1944 } 1945 1946 static int bnxt_set_fecparam(struct net_device *dev, 1947 struct ethtool_fecparam *fecparam) 1948 { 1949 struct hwrm_port_phy_cfg_input req = {0}; 1950 struct bnxt *bp = netdev_priv(dev); 1951 struct bnxt_link_info *link_info; 1952 u32 new_cfg, fec = fecparam->fec; 1953 u16 fec_cfg; 1954 int rc; 1955 1956 link_info = &bp->link_info; 1957 fec_cfg = link_info->fec_cfg; 1958 if (fec_cfg & BNXT_FEC_NONE) 1959 return -EOPNOTSUPP; 1960 1961 if (fec & ETHTOOL_FEC_OFF) { 1962 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 1963 BNXT_FEC_ALL_OFF(link_info); 1964 goto apply_fec; 1965 } 1966 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 1967 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 1968 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 1969 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 1970 return -EINVAL; 1971 1972 if (fec & ETHTOOL_FEC_AUTO) { 1973 if (!link_info->autoneg) 1974 return -EINVAL; 1975 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 1976 } else { 1977 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 1978 } 1979 1980 apply_fec: 1981 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 1982 req.flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 1983 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1984 /* update current settings */ 1985 if (!rc) { 1986 mutex_lock(&bp->link_lock); 1987 bnxt_update_link(bp, false); 1988 mutex_unlock(&bp->link_lock); 1989 } 1990 return rc; 1991 } 1992 1993 static void bnxt_get_pauseparam(struct net_device *dev, 1994 struct ethtool_pauseparam *epause) 1995 { 1996 struct bnxt *bp = netdev_priv(dev); 1997 struct bnxt_link_info *link_info = &bp->link_info; 1998 1999 if (BNXT_VF(bp)) 2000 return; 2001 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2002 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2003 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2004 } 2005 2006 static void bnxt_get_pause_stats(struct net_device *dev, 2007 struct ethtool_pause_stats *epstat) 2008 { 2009 struct bnxt *bp = netdev_priv(dev); 2010 u64 *rx, *tx; 2011 2012 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2013 return; 2014 2015 rx = bp->port_stats.sw_stats; 2016 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2017 2018 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2019 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2020 } 2021 2022 static int bnxt_set_pauseparam(struct net_device *dev, 2023 struct ethtool_pauseparam *epause) 2024 { 2025 int rc = 0; 2026 struct bnxt *bp = netdev_priv(dev); 2027 struct bnxt_link_info *link_info = &bp->link_info; 2028 2029 if (!BNXT_PHY_CFG_ABLE(bp)) 2030 return -EOPNOTSUPP; 2031 2032 mutex_lock(&bp->link_lock); 2033 if (epause->autoneg) { 2034 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2035 rc = -EINVAL; 2036 goto pause_exit; 2037 } 2038 2039 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2040 if (bp->hwrm_spec_code >= 0x10201) 2041 link_info->req_flow_ctrl = 2042 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 2043 } else { 2044 /* when transition from auto pause to force pause, 2045 * force a link change 2046 */ 2047 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2048 link_info->force_link_chng = true; 2049 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2050 link_info->req_flow_ctrl = 0; 2051 } 2052 if (epause->rx_pause) 2053 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2054 2055 if (epause->tx_pause) 2056 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2057 2058 if (netif_running(dev)) 2059 rc = bnxt_hwrm_set_pause(bp); 2060 2061 pause_exit: 2062 mutex_unlock(&bp->link_lock); 2063 return rc; 2064 } 2065 2066 static u32 bnxt_get_link(struct net_device *dev) 2067 { 2068 struct bnxt *bp = netdev_priv(dev); 2069 2070 /* TODO: handle MF, VF, driver close case */ 2071 return bp->link_info.link_up; 2072 } 2073 2074 static void bnxt_print_admin_err(struct bnxt *bp) 2075 { 2076 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2077 } 2078 2079 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2080 u16 ext, u16 *index, u32 *item_length, 2081 u32 *data_length); 2082 2083 static int bnxt_flash_nvram(struct net_device *dev, 2084 u16 dir_type, 2085 u16 dir_ordinal, 2086 u16 dir_ext, 2087 u16 dir_attr, 2088 const u8 *data, 2089 size_t data_len) 2090 { 2091 struct bnxt *bp = netdev_priv(dev); 2092 int rc; 2093 struct hwrm_nvm_write_input req = {0}; 2094 dma_addr_t dma_handle; 2095 u8 *kmem; 2096 2097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 2098 2099 req.dir_type = cpu_to_le16(dir_type); 2100 req.dir_ordinal = cpu_to_le16(dir_ordinal); 2101 req.dir_ext = cpu_to_le16(dir_ext); 2102 req.dir_attr = cpu_to_le16(dir_attr); 2103 req.dir_data_length = cpu_to_le32(data_len); 2104 2105 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 2106 GFP_KERNEL); 2107 if (!kmem) { 2108 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2109 (unsigned)data_len); 2110 return -ENOMEM; 2111 } 2112 memcpy(kmem, data, data_len); 2113 req.host_src_addr = cpu_to_le64(dma_handle); 2114 2115 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 2116 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 2117 2118 if (rc == -EACCES) 2119 bnxt_print_admin_err(bp); 2120 return rc; 2121 } 2122 2123 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2124 u8 self_reset, u8 flags) 2125 { 2126 struct hwrm_fw_reset_input req = {0}; 2127 struct bnxt *bp = netdev_priv(dev); 2128 int rc; 2129 2130 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 2131 2132 req.embedded_proc_type = proc_type; 2133 req.selfrst_status = self_reset; 2134 req.flags = flags; 2135 2136 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2137 rc = hwrm_send_message_silent(bp, &req, sizeof(req), 2138 HWRM_CMD_TIMEOUT); 2139 } else { 2140 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2141 if (rc == -EACCES) 2142 bnxt_print_admin_err(bp); 2143 } 2144 return rc; 2145 } 2146 2147 static int bnxt_firmware_reset(struct net_device *dev, 2148 enum bnxt_nvm_directory_type dir_type) 2149 { 2150 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2151 u8 proc_type, flags = 0; 2152 2153 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2154 /* (e.g. when firmware isn't already running) */ 2155 switch (dir_type) { 2156 case BNX_DIR_TYPE_CHIMP_PATCH: 2157 case BNX_DIR_TYPE_BOOTCODE: 2158 case BNX_DIR_TYPE_BOOTCODE_2: 2159 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2160 /* Self-reset ChiMP upon next PCIe reset: */ 2161 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2162 break; 2163 case BNX_DIR_TYPE_APE_FW: 2164 case BNX_DIR_TYPE_APE_PATCH: 2165 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2166 /* Self-reset APE upon next PCIe reset: */ 2167 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2168 break; 2169 case BNX_DIR_TYPE_KONG_FW: 2170 case BNX_DIR_TYPE_KONG_PATCH: 2171 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2172 break; 2173 case BNX_DIR_TYPE_BONO_FW: 2174 case BNX_DIR_TYPE_BONO_PATCH: 2175 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2176 break; 2177 default: 2178 return -EINVAL; 2179 } 2180 2181 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2182 } 2183 2184 static int bnxt_firmware_reset_chip(struct net_device *dev) 2185 { 2186 struct bnxt *bp = netdev_priv(dev); 2187 u8 flags = 0; 2188 2189 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2190 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2191 2192 return bnxt_hwrm_firmware_reset(dev, 2193 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2194 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2195 flags); 2196 } 2197 2198 static int bnxt_firmware_reset_ap(struct net_device *dev) 2199 { 2200 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2201 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2202 0); 2203 } 2204 2205 static int bnxt_flash_firmware(struct net_device *dev, 2206 u16 dir_type, 2207 const u8 *fw_data, 2208 size_t fw_size) 2209 { 2210 int rc = 0; 2211 u16 code_type; 2212 u32 stored_crc; 2213 u32 calculated_crc; 2214 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2215 2216 switch (dir_type) { 2217 case BNX_DIR_TYPE_BOOTCODE: 2218 case BNX_DIR_TYPE_BOOTCODE_2: 2219 code_type = CODE_BOOT; 2220 break; 2221 case BNX_DIR_TYPE_CHIMP_PATCH: 2222 code_type = CODE_CHIMP_PATCH; 2223 break; 2224 case BNX_DIR_TYPE_APE_FW: 2225 code_type = CODE_MCTP_PASSTHRU; 2226 break; 2227 case BNX_DIR_TYPE_APE_PATCH: 2228 code_type = CODE_APE_PATCH; 2229 break; 2230 case BNX_DIR_TYPE_KONG_FW: 2231 code_type = CODE_KONG_FW; 2232 break; 2233 case BNX_DIR_TYPE_KONG_PATCH: 2234 code_type = CODE_KONG_PATCH; 2235 break; 2236 case BNX_DIR_TYPE_BONO_FW: 2237 code_type = CODE_BONO_FW; 2238 break; 2239 case BNX_DIR_TYPE_BONO_PATCH: 2240 code_type = CODE_BONO_PATCH; 2241 break; 2242 default: 2243 netdev_err(dev, "Unsupported directory entry type: %u\n", 2244 dir_type); 2245 return -EINVAL; 2246 } 2247 if (fw_size < sizeof(struct bnxt_fw_header)) { 2248 netdev_err(dev, "Invalid firmware file size: %u\n", 2249 (unsigned int)fw_size); 2250 return -EINVAL; 2251 } 2252 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2253 netdev_err(dev, "Invalid firmware signature: %08X\n", 2254 le32_to_cpu(header->signature)); 2255 return -EINVAL; 2256 } 2257 if (header->code_type != code_type) { 2258 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2259 code_type, header->code_type); 2260 return -EINVAL; 2261 } 2262 if (header->device != DEVICE_CUMULUS_FAMILY) { 2263 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2264 DEVICE_CUMULUS_FAMILY, header->device); 2265 return -EINVAL; 2266 } 2267 /* Confirm the CRC32 checksum of the file: */ 2268 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2269 sizeof(stored_crc))); 2270 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2271 if (calculated_crc != stored_crc) { 2272 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2273 (unsigned long)stored_crc, 2274 (unsigned long)calculated_crc); 2275 return -EINVAL; 2276 } 2277 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2278 0, 0, fw_data, fw_size); 2279 if (rc == 0) /* Firmware update successful */ 2280 rc = bnxt_firmware_reset(dev, dir_type); 2281 2282 return rc; 2283 } 2284 2285 static int bnxt_flash_microcode(struct net_device *dev, 2286 u16 dir_type, 2287 const u8 *fw_data, 2288 size_t fw_size) 2289 { 2290 struct bnxt_ucode_trailer *trailer; 2291 u32 calculated_crc; 2292 u32 stored_crc; 2293 int rc = 0; 2294 2295 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2296 netdev_err(dev, "Invalid microcode file size: %u\n", 2297 (unsigned int)fw_size); 2298 return -EINVAL; 2299 } 2300 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2301 sizeof(*trailer))); 2302 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2303 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2304 le32_to_cpu(trailer->sig)); 2305 return -EINVAL; 2306 } 2307 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2308 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2309 dir_type, le16_to_cpu(trailer->dir_type)); 2310 return -EINVAL; 2311 } 2312 if (le16_to_cpu(trailer->trailer_length) < 2313 sizeof(struct bnxt_ucode_trailer)) { 2314 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2315 le16_to_cpu(trailer->trailer_length)); 2316 return -EINVAL; 2317 } 2318 2319 /* Confirm the CRC32 checksum of the file: */ 2320 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2321 sizeof(stored_crc))); 2322 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2323 if (calculated_crc != stored_crc) { 2324 netdev_err(dev, 2325 "CRC32 (%08lX) does not match calculated: %08lX\n", 2326 (unsigned long)stored_crc, 2327 (unsigned long)calculated_crc); 2328 return -EINVAL; 2329 } 2330 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2331 0, 0, fw_data, fw_size); 2332 2333 return rc; 2334 } 2335 2336 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2337 { 2338 switch (dir_type) { 2339 case BNX_DIR_TYPE_CHIMP_PATCH: 2340 case BNX_DIR_TYPE_BOOTCODE: 2341 case BNX_DIR_TYPE_BOOTCODE_2: 2342 case BNX_DIR_TYPE_APE_FW: 2343 case BNX_DIR_TYPE_APE_PATCH: 2344 case BNX_DIR_TYPE_KONG_FW: 2345 case BNX_DIR_TYPE_KONG_PATCH: 2346 case BNX_DIR_TYPE_BONO_FW: 2347 case BNX_DIR_TYPE_BONO_PATCH: 2348 return true; 2349 } 2350 2351 return false; 2352 } 2353 2354 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2355 { 2356 switch (dir_type) { 2357 case BNX_DIR_TYPE_AVS: 2358 case BNX_DIR_TYPE_EXP_ROM_MBA: 2359 case BNX_DIR_TYPE_PCIE: 2360 case BNX_DIR_TYPE_TSCF_UCODE: 2361 case BNX_DIR_TYPE_EXT_PHY: 2362 case BNX_DIR_TYPE_CCM: 2363 case BNX_DIR_TYPE_ISCSI_BOOT: 2364 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2365 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2366 return true; 2367 } 2368 2369 return false; 2370 } 2371 2372 static bool bnxt_dir_type_is_executable(u16 dir_type) 2373 { 2374 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2375 bnxt_dir_type_is_other_exec_format(dir_type); 2376 } 2377 2378 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2379 u16 dir_type, 2380 const char *filename) 2381 { 2382 const struct firmware *fw; 2383 int rc; 2384 2385 rc = request_firmware(&fw, filename, &dev->dev); 2386 if (rc != 0) { 2387 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2388 rc, filename); 2389 return rc; 2390 } 2391 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2392 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2393 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2394 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2395 else 2396 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2397 0, 0, fw->data, fw->size); 2398 release_firmware(fw); 2399 return rc; 2400 } 2401 2402 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2403 u32 install_type) 2404 { 2405 struct bnxt *bp = netdev_priv(dev); 2406 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2407 struct hwrm_nvm_install_update_input install = {0}; 2408 const struct firmware *fw; 2409 u32 item_len; 2410 int rc = 0; 2411 u16 index; 2412 2413 bnxt_hwrm_fw_set_time(bp); 2414 2415 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2416 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2417 &index, &item_len, NULL); 2418 if (rc) { 2419 netdev_err(dev, "PKG update area not created in nvram\n"); 2420 return rc; 2421 } 2422 2423 rc = request_firmware(&fw, filename, &dev->dev); 2424 if (rc != 0) { 2425 netdev_err(dev, "PKG error %d requesting file: %s\n", 2426 rc, filename); 2427 return rc; 2428 } 2429 2430 if (fw->size > item_len) { 2431 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2432 (unsigned long)fw->size); 2433 rc = -EFBIG; 2434 } else { 2435 dma_addr_t dma_handle; 2436 u8 *kmem; 2437 struct hwrm_nvm_modify_input modify = {0}; 2438 2439 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2440 2441 modify.dir_idx = cpu_to_le16(index); 2442 modify.len = cpu_to_le32(fw->size); 2443 2444 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2445 &dma_handle, GFP_KERNEL); 2446 if (!kmem) { 2447 netdev_err(dev, 2448 "dma_alloc_coherent failure, length = %u\n", 2449 (unsigned int)fw->size); 2450 rc = -ENOMEM; 2451 } else { 2452 memcpy(kmem, fw->data, fw->size); 2453 modify.host_src_addr = cpu_to_le64(dma_handle); 2454 2455 rc = hwrm_send_message(bp, &modify, sizeof(modify), 2456 FLASH_PACKAGE_TIMEOUT); 2457 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2458 dma_handle); 2459 } 2460 } 2461 release_firmware(fw); 2462 if (rc) 2463 goto err_exit; 2464 2465 if ((install_type & 0xffff) == 0) 2466 install_type >>= 16; 2467 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2468 install.install_type = cpu_to_le32(install_type); 2469 2470 mutex_lock(&bp->hwrm_cmd_lock); 2471 rc = _hwrm_send_message(bp, &install, sizeof(install), 2472 INSTALL_PACKAGE_TIMEOUT); 2473 if (rc) { 2474 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2475 2476 if (resp->error_code && error_code == 2477 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2478 install.flags |= cpu_to_le16( 2479 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2480 rc = _hwrm_send_message(bp, &install, sizeof(install), 2481 INSTALL_PACKAGE_TIMEOUT); 2482 } 2483 if (rc) 2484 goto flash_pkg_exit; 2485 } 2486 2487 if (resp->result) { 2488 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2489 (s8)resp->result, (int)resp->problem_item); 2490 rc = -ENOPKG; 2491 } 2492 flash_pkg_exit: 2493 mutex_unlock(&bp->hwrm_cmd_lock); 2494 err_exit: 2495 if (rc == -EACCES) 2496 bnxt_print_admin_err(bp); 2497 return rc; 2498 } 2499 2500 static int bnxt_flash_device(struct net_device *dev, 2501 struct ethtool_flash *flash) 2502 { 2503 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2504 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2505 return -EINVAL; 2506 } 2507 2508 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2509 flash->region > 0xffff) 2510 return bnxt_flash_package_from_file(dev, flash->data, 2511 flash->region); 2512 2513 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2514 } 2515 2516 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2517 { 2518 struct bnxt *bp = netdev_priv(dev); 2519 int rc; 2520 struct hwrm_nvm_get_dir_info_input req = {0}; 2521 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2522 2523 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2524 2525 mutex_lock(&bp->hwrm_cmd_lock); 2526 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2527 if (!rc) { 2528 *entries = le32_to_cpu(output->entries); 2529 *length = le32_to_cpu(output->entry_length); 2530 } 2531 mutex_unlock(&bp->hwrm_cmd_lock); 2532 return rc; 2533 } 2534 2535 static int bnxt_get_eeprom_len(struct net_device *dev) 2536 { 2537 struct bnxt *bp = netdev_priv(dev); 2538 2539 if (BNXT_VF(bp)) 2540 return 0; 2541 2542 /* The -1 return value allows the entire 32-bit range of offsets to be 2543 * passed via the ethtool command-line utility. 2544 */ 2545 return -1; 2546 } 2547 2548 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2549 { 2550 struct bnxt *bp = netdev_priv(dev); 2551 int rc; 2552 u32 dir_entries; 2553 u32 entry_length; 2554 u8 *buf; 2555 size_t buflen; 2556 dma_addr_t dma_handle; 2557 struct hwrm_nvm_get_dir_entries_input req = {0}; 2558 2559 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2560 if (rc != 0) 2561 return rc; 2562 2563 if (!dir_entries || !entry_length) 2564 return -EIO; 2565 2566 /* Insert 2 bytes of directory info (count and size of entries) */ 2567 if (len < 2) 2568 return -EINVAL; 2569 2570 *data++ = dir_entries; 2571 *data++ = entry_length; 2572 len -= 2; 2573 memset(data, 0xff, len); 2574 2575 buflen = dir_entries * entry_length; 2576 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2577 GFP_KERNEL); 2578 if (!buf) { 2579 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2580 (unsigned)buflen); 2581 return -ENOMEM; 2582 } 2583 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2584 req.host_dest_addr = cpu_to_le64(dma_handle); 2585 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2586 if (rc == 0) 2587 memcpy(data, buf, len > buflen ? buflen : len); 2588 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2589 return rc; 2590 } 2591 2592 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2593 u32 length, u8 *data) 2594 { 2595 struct bnxt *bp = netdev_priv(dev); 2596 int rc; 2597 u8 *buf; 2598 dma_addr_t dma_handle; 2599 struct hwrm_nvm_read_input req = {0}; 2600 2601 if (!length) 2602 return -EINVAL; 2603 2604 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2605 GFP_KERNEL); 2606 if (!buf) { 2607 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2608 (unsigned)length); 2609 return -ENOMEM; 2610 } 2611 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2612 req.host_dest_addr = cpu_to_le64(dma_handle); 2613 req.dir_idx = cpu_to_le16(index); 2614 req.offset = cpu_to_le32(offset); 2615 req.len = cpu_to_le32(length); 2616 2617 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2618 if (rc == 0) 2619 memcpy(data, buf, length); 2620 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2621 return rc; 2622 } 2623 2624 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2625 u16 ext, u16 *index, u32 *item_length, 2626 u32 *data_length) 2627 { 2628 struct bnxt *bp = netdev_priv(dev); 2629 int rc; 2630 struct hwrm_nvm_find_dir_entry_input req = {0}; 2631 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2632 2633 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2634 req.enables = 0; 2635 req.dir_idx = 0; 2636 req.dir_type = cpu_to_le16(type); 2637 req.dir_ordinal = cpu_to_le16(ordinal); 2638 req.dir_ext = cpu_to_le16(ext); 2639 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2640 mutex_lock(&bp->hwrm_cmd_lock); 2641 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2642 if (rc == 0) { 2643 if (index) 2644 *index = le16_to_cpu(output->dir_idx); 2645 if (item_length) 2646 *item_length = le32_to_cpu(output->dir_item_length); 2647 if (data_length) 2648 *data_length = le32_to_cpu(output->dir_data_length); 2649 } 2650 mutex_unlock(&bp->hwrm_cmd_lock); 2651 return rc; 2652 } 2653 2654 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2655 { 2656 char *retval = NULL; 2657 char *p; 2658 char *value; 2659 int field = 0; 2660 2661 if (datalen < 1) 2662 return NULL; 2663 /* null-terminate the log data (removing last '\n'): */ 2664 data[datalen - 1] = 0; 2665 for (p = data; *p != 0; p++) { 2666 field = 0; 2667 retval = NULL; 2668 while (*p != 0 && *p != '\n') { 2669 value = p; 2670 while (*p != 0 && *p != '\t' && *p != '\n') 2671 p++; 2672 if (field == desired_field) 2673 retval = value; 2674 if (*p != '\t') 2675 break; 2676 *p = 0; 2677 field++; 2678 p++; 2679 } 2680 if (*p == 0) 2681 break; 2682 *p = 0; 2683 } 2684 return retval; 2685 } 2686 2687 static void bnxt_get_pkgver(struct net_device *dev) 2688 { 2689 struct bnxt *bp = netdev_priv(dev); 2690 u16 index = 0; 2691 char *pkgver; 2692 u32 pkglen; 2693 u8 *pkgbuf; 2694 int len; 2695 2696 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2697 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2698 &index, NULL, &pkglen) != 0) 2699 return; 2700 2701 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2702 if (!pkgbuf) { 2703 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2704 pkglen); 2705 return; 2706 } 2707 2708 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2709 goto err; 2710 2711 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2712 pkglen); 2713 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2714 len = strlen(bp->fw_ver_str); 2715 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2716 "/pkg %s", pkgver); 2717 } 2718 err: 2719 kfree(pkgbuf); 2720 } 2721 2722 static int bnxt_get_eeprom(struct net_device *dev, 2723 struct ethtool_eeprom *eeprom, 2724 u8 *data) 2725 { 2726 u32 index; 2727 u32 offset; 2728 2729 if (eeprom->offset == 0) /* special offset value to get directory */ 2730 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2731 2732 index = eeprom->offset >> 24; 2733 offset = eeprom->offset & 0xffffff; 2734 2735 if (index == 0) { 2736 netdev_err(dev, "unsupported index value: %d\n", index); 2737 return -EINVAL; 2738 } 2739 2740 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2741 } 2742 2743 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2744 { 2745 struct bnxt *bp = netdev_priv(dev); 2746 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2747 2748 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2749 req.dir_idx = cpu_to_le16(index); 2750 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2751 } 2752 2753 static int bnxt_set_eeprom(struct net_device *dev, 2754 struct ethtool_eeprom *eeprom, 2755 u8 *data) 2756 { 2757 struct bnxt *bp = netdev_priv(dev); 2758 u8 index, dir_op; 2759 u16 type, ext, ordinal, attr; 2760 2761 if (!BNXT_PF(bp)) { 2762 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2763 return -EINVAL; 2764 } 2765 2766 type = eeprom->magic >> 16; 2767 2768 if (type == 0xffff) { /* special value for directory operations */ 2769 index = eeprom->magic & 0xff; 2770 dir_op = eeprom->magic >> 8; 2771 if (index == 0) 2772 return -EINVAL; 2773 switch (dir_op) { 2774 case 0x0e: /* erase */ 2775 if (eeprom->offset != ~eeprom->magic) 2776 return -EINVAL; 2777 return bnxt_erase_nvram_directory(dev, index - 1); 2778 default: 2779 return -EINVAL; 2780 } 2781 } 2782 2783 /* Create or re-write an NVM item: */ 2784 if (bnxt_dir_type_is_executable(type)) 2785 return -EOPNOTSUPP; 2786 ext = eeprom->magic & 0xffff; 2787 ordinal = eeprom->offset >> 16; 2788 attr = eeprom->offset & 0xffff; 2789 2790 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2791 eeprom->len); 2792 } 2793 2794 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2795 { 2796 struct bnxt *bp = netdev_priv(dev); 2797 struct ethtool_eee *eee = &bp->eee; 2798 struct bnxt_link_info *link_info = &bp->link_info; 2799 u32 advertising; 2800 int rc = 0; 2801 2802 if (!BNXT_PHY_CFG_ABLE(bp)) 2803 return -EOPNOTSUPP; 2804 2805 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2806 return -EOPNOTSUPP; 2807 2808 mutex_lock(&bp->link_lock); 2809 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2810 if (!edata->eee_enabled) 2811 goto eee_ok; 2812 2813 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2814 netdev_warn(dev, "EEE requires autoneg\n"); 2815 rc = -EINVAL; 2816 goto eee_exit; 2817 } 2818 if (edata->tx_lpi_enabled) { 2819 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2820 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2821 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2822 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2823 rc = -EINVAL; 2824 goto eee_exit; 2825 } else if (!bp->lpi_tmr_hi) { 2826 edata->tx_lpi_timer = eee->tx_lpi_timer; 2827 } 2828 } 2829 if (!edata->advertised) { 2830 edata->advertised = advertising & eee->supported; 2831 } else if (edata->advertised & ~advertising) { 2832 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2833 edata->advertised, advertising); 2834 rc = -EINVAL; 2835 goto eee_exit; 2836 } 2837 2838 eee->advertised = edata->advertised; 2839 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2840 eee->tx_lpi_timer = edata->tx_lpi_timer; 2841 eee_ok: 2842 eee->eee_enabled = edata->eee_enabled; 2843 2844 if (netif_running(dev)) 2845 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2846 2847 eee_exit: 2848 mutex_unlock(&bp->link_lock); 2849 return rc; 2850 } 2851 2852 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2853 { 2854 struct bnxt *bp = netdev_priv(dev); 2855 2856 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2857 return -EOPNOTSUPP; 2858 2859 *edata = bp->eee; 2860 if (!bp->eee.eee_enabled) { 2861 /* Preserve tx_lpi_timer so that the last value will be used 2862 * by default when it is re-enabled. 2863 */ 2864 edata->advertised = 0; 2865 edata->tx_lpi_enabled = 0; 2866 } 2867 2868 if (!bp->eee.eee_active) 2869 edata->lp_advertised = 0; 2870 2871 return 0; 2872 } 2873 2874 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2875 u16 page_number, u16 start_addr, 2876 u16 data_length, u8 *buf) 2877 { 2878 struct hwrm_port_phy_i2c_read_input req = {0}; 2879 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2880 int rc, byte_offset = 0; 2881 2882 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2883 req.i2c_slave_addr = i2c_addr; 2884 req.page_number = cpu_to_le16(page_number); 2885 req.port_id = cpu_to_le16(bp->pf.port_id); 2886 do { 2887 u16 xfer_size; 2888 2889 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2890 data_length -= xfer_size; 2891 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2892 req.data_length = xfer_size; 2893 req.enables = cpu_to_le32(start_addr + byte_offset ? 2894 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2895 mutex_lock(&bp->hwrm_cmd_lock); 2896 rc = _hwrm_send_message(bp, &req, sizeof(req), 2897 HWRM_CMD_TIMEOUT); 2898 if (!rc) 2899 memcpy(buf + byte_offset, output->data, xfer_size); 2900 mutex_unlock(&bp->hwrm_cmd_lock); 2901 byte_offset += xfer_size; 2902 } while (!rc && data_length > 0); 2903 2904 return rc; 2905 } 2906 2907 static int bnxt_get_module_info(struct net_device *dev, 2908 struct ethtool_modinfo *modinfo) 2909 { 2910 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2911 struct bnxt *bp = netdev_priv(dev); 2912 int rc; 2913 2914 /* No point in going further if phy status indicates 2915 * module is not inserted or if it is powered down or 2916 * if it is of type 10GBase-T 2917 */ 2918 if (bp->link_info.module_status > 2919 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2920 return -EOPNOTSUPP; 2921 2922 /* This feature is not supported in older firmware versions */ 2923 if (bp->hwrm_spec_code < 0x10202) 2924 return -EOPNOTSUPP; 2925 2926 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2927 SFF_DIAG_SUPPORT_OFFSET + 1, 2928 data); 2929 if (!rc) { 2930 u8 module_id = data[0]; 2931 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2932 2933 switch (module_id) { 2934 case SFF_MODULE_ID_SFP: 2935 modinfo->type = ETH_MODULE_SFF_8472; 2936 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2937 if (!diag_supported) 2938 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2939 break; 2940 case SFF_MODULE_ID_QSFP: 2941 case SFF_MODULE_ID_QSFP_PLUS: 2942 modinfo->type = ETH_MODULE_SFF_8436; 2943 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2944 break; 2945 case SFF_MODULE_ID_QSFP28: 2946 modinfo->type = ETH_MODULE_SFF_8636; 2947 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2948 break; 2949 default: 2950 rc = -EOPNOTSUPP; 2951 break; 2952 } 2953 } 2954 return rc; 2955 } 2956 2957 static int bnxt_get_module_eeprom(struct net_device *dev, 2958 struct ethtool_eeprom *eeprom, 2959 u8 *data) 2960 { 2961 struct bnxt *bp = netdev_priv(dev); 2962 u16 start = eeprom->offset, length = eeprom->len; 2963 int rc = 0; 2964 2965 memset(data, 0, eeprom->len); 2966 2967 /* Read A0 portion of the EEPROM */ 2968 if (start < ETH_MODULE_SFF_8436_LEN) { 2969 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 2970 length = ETH_MODULE_SFF_8436_LEN - start; 2971 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 2972 start, length, data); 2973 if (rc) 2974 return rc; 2975 start += length; 2976 data += length; 2977 length = eeprom->len - length; 2978 } 2979 2980 /* Read A2 portion of the EEPROM */ 2981 if (length) { 2982 start -= ETH_MODULE_SFF_8436_LEN; 2983 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, 2984 start, length, data); 2985 } 2986 return rc; 2987 } 2988 2989 static int bnxt_nway_reset(struct net_device *dev) 2990 { 2991 int rc = 0; 2992 2993 struct bnxt *bp = netdev_priv(dev); 2994 struct bnxt_link_info *link_info = &bp->link_info; 2995 2996 if (!BNXT_PHY_CFG_ABLE(bp)) 2997 return -EOPNOTSUPP; 2998 2999 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3000 return -EINVAL; 3001 3002 if (netif_running(dev)) 3003 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3004 3005 return rc; 3006 } 3007 3008 static int bnxt_set_phys_id(struct net_device *dev, 3009 enum ethtool_phys_id_state state) 3010 { 3011 struct hwrm_port_led_cfg_input req = {0}; 3012 struct bnxt *bp = netdev_priv(dev); 3013 struct bnxt_pf_info *pf = &bp->pf; 3014 struct bnxt_led_cfg *led_cfg; 3015 u8 led_state; 3016 __le16 duration; 3017 int i; 3018 3019 if (!bp->num_leds || BNXT_VF(bp)) 3020 return -EOPNOTSUPP; 3021 3022 if (state == ETHTOOL_ID_ACTIVE) { 3023 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3024 duration = cpu_to_le16(500); 3025 } else if (state == ETHTOOL_ID_INACTIVE) { 3026 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3027 duration = cpu_to_le16(0); 3028 } else { 3029 return -EINVAL; 3030 } 3031 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 3032 req.port_id = cpu_to_le16(pf->port_id); 3033 req.num_leds = bp->num_leds; 3034 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 3035 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3036 req.enables |= BNXT_LED_DFLT_ENABLES(i); 3037 led_cfg->led_id = bp->leds[i].led_id; 3038 led_cfg->led_state = led_state; 3039 led_cfg->led_blink_on = duration; 3040 led_cfg->led_blink_off = duration; 3041 led_cfg->led_group_id = bp->leds[i].led_group_id; 3042 } 3043 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3044 } 3045 3046 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3047 { 3048 struct hwrm_selftest_irq_input req = {0}; 3049 3050 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 3051 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3052 } 3053 3054 static int bnxt_test_irq(struct bnxt *bp) 3055 { 3056 int i; 3057 3058 for (i = 0; i < bp->cp_nr_rings; i++) { 3059 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3060 int rc; 3061 3062 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3063 if (rc) 3064 return rc; 3065 } 3066 return 0; 3067 } 3068 3069 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3070 { 3071 struct hwrm_port_mac_cfg_input req = {0}; 3072 3073 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 3074 3075 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3076 if (enable) 3077 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3078 else 3079 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3080 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3081 } 3082 3083 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3084 { 3085 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 3086 struct hwrm_port_phy_qcaps_input req = {0}; 3087 int rc; 3088 3089 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 3090 mutex_lock(&bp->hwrm_cmd_lock); 3091 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3092 if (!rc) 3093 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3094 3095 mutex_unlock(&bp->hwrm_cmd_lock); 3096 return rc; 3097 } 3098 3099 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3100 struct hwrm_port_phy_cfg_input *req) 3101 { 3102 struct bnxt_link_info *link_info = &bp->link_info; 3103 u16 fw_advertising; 3104 u16 fw_speed; 3105 int rc; 3106 3107 if (!link_info->autoneg || 3108 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK)) 3109 return 0; 3110 3111 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3112 if (rc) 3113 return rc; 3114 3115 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3116 if (bp->link_info.link_up) 3117 fw_speed = bp->link_info.link_speed; 3118 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3119 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3120 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3121 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3122 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3123 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3124 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3125 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3126 3127 req->force_link_speed = cpu_to_le16(fw_speed); 3128 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3129 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3130 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 3131 req->flags = 0; 3132 req->force_link_speed = cpu_to_le16(0); 3133 return rc; 3134 } 3135 3136 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3137 { 3138 struct hwrm_port_phy_cfg_input req = {0}; 3139 3140 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 3141 3142 if (enable) { 3143 bnxt_disable_an_for_lpbk(bp, &req); 3144 if (ext) 3145 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3146 else 3147 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3148 } else { 3149 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3150 } 3151 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3152 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3153 } 3154 3155 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3156 u32 raw_cons, int pkt_size) 3157 { 3158 struct bnxt_napi *bnapi = cpr->bnapi; 3159 struct bnxt_rx_ring_info *rxr; 3160 struct bnxt_sw_rx_bd *rx_buf; 3161 struct rx_cmp *rxcmp; 3162 u16 cp_cons, cons; 3163 u8 *data; 3164 u32 len; 3165 int i; 3166 3167 rxr = bnapi->rx_ring; 3168 cp_cons = RING_CMP(raw_cons); 3169 rxcmp = (struct rx_cmp *) 3170 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3171 cons = rxcmp->rx_cmp_opaque; 3172 rx_buf = &rxr->rx_buf_ring[cons]; 3173 data = rx_buf->data_ptr; 3174 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3175 if (len != pkt_size) 3176 return -EIO; 3177 i = ETH_ALEN; 3178 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3179 return -EIO; 3180 i += ETH_ALEN; 3181 for ( ; i < pkt_size; i++) { 3182 if (data[i] != (u8)(i & 0xff)) 3183 return -EIO; 3184 } 3185 return 0; 3186 } 3187 3188 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3189 int pkt_size) 3190 { 3191 struct tx_cmp *txcmp; 3192 int rc = -EIO; 3193 u32 raw_cons; 3194 u32 cons; 3195 int i; 3196 3197 raw_cons = cpr->cp_raw_cons; 3198 for (i = 0; i < 200; i++) { 3199 cons = RING_CMP(raw_cons); 3200 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3201 3202 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3203 udelay(5); 3204 continue; 3205 } 3206 3207 /* The valid test of the entry must be done first before 3208 * reading any further. 3209 */ 3210 dma_rmb(); 3211 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3212 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3213 raw_cons = NEXT_RAW_CMP(raw_cons); 3214 raw_cons = NEXT_RAW_CMP(raw_cons); 3215 break; 3216 } 3217 raw_cons = NEXT_RAW_CMP(raw_cons); 3218 } 3219 cpr->cp_raw_cons = raw_cons; 3220 return rc; 3221 } 3222 3223 static int bnxt_run_loopback(struct bnxt *bp) 3224 { 3225 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3226 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3227 struct bnxt_cp_ring_info *cpr; 3228 int pkt_size, i = 0; 3229 struct sk_buff *skb; 3230 dma_addr_t map; 3231 u8 *data; 3232 int rc; 3233 3234 cpr = &rxr->bnapi->cp_ring; 3235 if (bp->flags & BNXT_FLAG_CHIP_P5) 3236 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3237 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3238 skb = netdev_alloc_skb(bp->dev, pkt_size); 3239 if (!skb) 3240 return -ENOMEM; 3241 data = skb_put(skb, pkt_size); 3242 eth_broadcast_addr(data); 3243 i += ETH_ALEN; 3244 ether_addr_copy(&data[i], bp->dev->dev_addr); 3245 i += ETH_ALEN; 3246 for ( ; i < pkt_size; i++) 3247 data[i] = (u8)(i & 0xff); 3248 3249 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3250 PCI_DMA_TODEVICE); 3251 if (dma_mapping_error(&bp->pdev->dev, map)) { 3252 dev_kfree_skb(skb); 3253 return -EIO; 3254 } 3255 bnxt_xmit_bd(bp, txr, map, pkt_size); 3256 3257 /* Sync BD data before updating doorbell */ 3258 wmb(); 3259 3260 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3261 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3262 3263 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 3264 dev_kfree_skb(skb); 3265 return rc; 3266 } 3267 3268 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3269 { 3270 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 3271 struct hwrm_selftest_exec_input req = {0}; 3272 int rc; 3273 3274 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 3275 mutex_lock(&bp->hwrm_cmd_lock); 3276 resp->test_success = 0; 3277 req.flags = test_mask; 3278 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 3279 *test_results = resp->test_success; 3280 mutex_unlock(&bp->hwrm_cmd_lock); 3281 return rc; 3282 } 3283 3284 #define BNXT_DRV_TESTS 4 3285 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3286 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3287 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3288 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3289 3290 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3291 u64 *buf) 3292 { 3293 struct bnxt *bp = netdev_priv(dev); 3294 bool do_ext_lpbk = false; 3295 bool offline = false; 3296 u8 test_results = 0; 3297 u8 test_mask = 0; 3298 int rc = 0, i; 3299 3300 if (!bp->num_tests || !BNXT_SINGLE_PF(bp)) 3301 return; 3302 memset(buf, 0, sizeof(u64) * bp->num_tests); 3303 if (!netif_running(dev)) { 3304 etest->flags |= ETH_TEST_FL_FAILED; 3305 return; 3306 } 3307 3308 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3309 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 3310 do_ext_lpbk = true; 3311 3312 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3313 if (bp->pf.active_vfs) { 3314 etest->flags |= ETH_TEST_FL_FAILED; 3315 netdev_warn(dev, "Offline tests cannot be run with active VFs\n"); 3316 return; 3317 } 3318 offline = true; 3319 } 3320 3321 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3322 u8 bit_val = 1 << i; 3323 3324 if (!(bp->test_info->offline_mask & bit_val)) 3325 test_mask |= bit_val; 3326 else if (offline) 3327 test_mask |= bit_val; 3328 } 3329 if (!offline) { 3330 bnxt_run_fw_tests(bp, test_mask, &test_results); 3331 } else { 3332 rc = bnxt_close_nic(bp, false, false); 3333 if (rc) 3334 return; 3335 bnxt_run_fw_tests(bp, test_mask, &test_results); 3336 3337 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3338 bnxt_hwrm_mac_loopback(bp, true); 3339 msleep(250); 3340 rc = bnxt_half_open_nic(bp); 3341 if (rc) { 3342 bnxt_hwrm_mac_loopback(bp, false); 3343 etest->flags |= ETH_TEST_FL_FAILED; 3344 return; 3345 } 3346 if (bnxt_run_loopback(bp)) 3347 etest->flags |= ETH_TEST_FL_FAILED; 3348 else 3349 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3350 3351 bnxt_hwrm_mac_loopback(bp, false); 3352 bnxt_hwrm_phy_loopback(bp, true, false); 3353 msleep(1000); 3354 if (bnxt_run_loopback(bp)) { 3355 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3356 etest->flags |= ETH_TEST_FL_FAILED; 3357 } 3358 if (do_ext_lpbk) { 3359 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3360 bnxt_hwrm_phy_loopback(bp, true, true); 3361 msleep(1000); 3362 if (bnxt_run_loopback(bp)) { 3363 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3364 etest->flags |= ETH_TEST_FL_FAILED; 3365 } 3366 } 3367 bnxt_hwrm_phy_loopback(bp, false, false); 3368 bnxt_half_close_nic(bp); 3369 rc = bnxt_open_nic(bp, false, true); 3370 } 3371 if (rc || bnxt_test_irq(bp)) { 3372 buf[BNXT_IRQ_TEST_IDX] = 1; 3373 etest->flags |= ETH_TEST_FL_FAILED; 3374 } 3375 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3376 u8 bit_val = 1 << i; 3377 3378 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3379 buf[i] = 1; 3380 etest->flags |= ETH_TEST_FL_FAILED; 3381 } 3382 } 3383 } 3384 3385 static int bnxt_reset(struct net_device *dev, u32 *flags) 3386 { 3387 struct bnxt *bp = netdev_priv(dev); 3388 bool reload = false; 3389 u32 req = *flags; 3390 3391 if (!req) 3392 return -EINVAL; 3393 3394 if (!BNXT_PF(bp)) { 3395 netdev_err(dev, "Reset is not supported from a VF\n"); 3396 return -EOPNOTSUPP; 3397 } 3398 3399 if (pci_vfs_assigned(bp->pdev) && 3400 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3401 netdev_err(dev, 3402 "Reset not allowed when VFs are assigned to VMs\n"); 3403 return -EBUSY; 3404 } 3405 3406 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3407 /* This feature is not supported in older firmware versions */ 3408 if (bp->hwrm_spec_code >= 0x10803) { 3409 if (!bnxt_firmware_reset_chip(dev)) { 3410 netdev_info(dev, "Firmware reset request successful.\n"); 3411 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3412 reload = true; 3413 *flags &= ~BNXT_FW_RESET_CHIP; 3414 } 3415 } else if (req == BNXT_FW_RESET_CHIP) { 3416 return -EOPNOTSUPP; /* only request, fail hard */ 3417 } 3418 } 3419 3420 if (req & BNXT_FW_RESET_AP) { 3421 /* This feature is not supported in older firmware versions */ 3422 if (bp->hwrm_spec_code >= 0x10803) { 3423 if (!bnxt_firmware_reset_ap(dev)) { 3424 netdev_info(dev, "Reset application processor successful.\n"); 3425 reload = true; 3426 *flags &= ~BNXT_FW_RESET_AP; 3427 } 3428 } else if (req == BNXT_FW_RESET_AP) { 3429 return -EOPNOTSUPP; /* only request, fail hard */ 3430 } 3431 } 3432 3433 if (reload) 3434 netdev_info(dev, "Reload driver to complete reset\n"); 3435 3436 return 0; 3437 } 3438 3439 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3440 struct bnxt_hwrm_dbg_dma_info *info) 3441 { 3442 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3443 struct hwrm_dbg_cmn_input *cmn_req = msg; 3444 __le16 *seq_ptr = msg + info->seq_off; 3445 u16 seq = 0, len, segs_off; 3446 void *resp = cmn_resp; 3447 dma_addr_t dma_handle; 3448 int rc, off = 0; 3449 void *dma_buf; 3450 3451 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3452 GFP_KERNEL); 3453 if (!dma_buf) 3454 return -ENOMEM; 3455 3456 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3457 total_segments); 3458 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3459 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3460 mutex_lock(&bp->hwrm_cmd_lock); 3461 while (1) { 3462 *seq_ptr = cpu_to_le16(seq); 3463 rc = _hwrm_send_message(bp, msg, msg_len, 3464 HWRM_COREDUMP_TIMEOUT); 3465 if (rc) 3466 break; 3467 3468 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3469 if (!seq && 3470 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3471 info->segs = le16_to_cpu(*((__le16 *)(resp + 3472 segs_off))); 3473 if (!info->segs) { 3474 rc = -EIO; 3475 break; 3476 } 3477 3478 info->dest_buf_size = info->segs * 3479 sizeof(struct coredump_segment_record); 3480 info->dest_buf = kmalloc(info->dest_buf_size, 3481 GFP_KERNEL); 3482 if (!info->dest_buf) { 3483 rc = -ENOMEM; 3484 break; 3485 } 3486 } 3487 3488 if (info->dest_buf) { 3489 if ((info->seg_start + off + len) <= 3490 BNXT_COREDUMP_BUF_LEN(info->buf_len)) { 3491 memcpy(info->dest_buf + off, dma_buf, len); 3492 } else { 3493 rc = -ENOBUFS; 3494 break; 3495 } 3496 } 3497 3498 if (cmn_req->req_type == 3499 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3500 info->dest_buf_size += len; 3501 3502 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3503 break; 3504 3505 seq++; 3506 off += len; 3507 } 3508 mutex_unlock(&bp->hwrm_cmd_lock); 3509 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3510 return rc; 3511 } 3512 3513 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3514 struct bnxt_coredump *coredump) 3515 { 3516 struct hwrm_dbg_coredump_list_input req = {0}; 3517 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3518 int rc; 3519 3520 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3521 3522 info.dma_len = COREDUMP_LIST_BUF_LEN; 3523 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3524 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3525 data_len); 3526 3527 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3528 if (!rc) { 3529 coredump->data = info.dest_buf; 3530 coredump->data_size = info.dest_buf_size; 3531 coredump->total_segs = info.segs; 3532 } 3533 return rc; 3534 } 3535 3536 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3537 u16 segment_id) 3538 { 3539 struct hwrm_dbg_coredump_initiate_input req = {0}; 3540 3541 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3542 req.component_id = cpu_to_le16(component_id); 3543 req.segment_id = cpu_to_le16(segment_id); 3544 3545 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3546 } 3547 3548 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3549 u16 segment_id, u32 *seg_len, 3550 void *buf, u32 buf_len, u32 offset) 3551 { 3552 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3553 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3554 int rc; 3555 3556 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3557 req.component_id = cpu_to_le16(component_id); 3558 req.segment_id = cpu_to_le16(segment_id); 3559 3560 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3561 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3562 seq_no); 3563 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3564 data_len); 3565 if (buf) { 3566 info.dest_buf = buf + offset; 3567 info.buf_len = buf_len; 3568 info.seg_start = offset; 3569 } 3570 3571 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3572 if (!rc) 3573 *seg_len = info.dest_buf_size; 3574 3575 return rc; 3576 } 3577 3578 static void 3579 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3580 struct bnxt_coredump_segment_hdr *seg_hdr, 3581 struct coredump_segment_record *seg_rec, u32 seg_len, 3582 int status, u32 duration, u32 instance) 3583 { 3584 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3585 memcpy(seg_hdr->signature, "sEgM", 4); 3586 if (seg_rec) { 3587 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3588 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3589 seg_hdr->low_version = seg_rec->version_low; 3590 seg_hdr->high_version = seg_rec->version_hi; 3591 } else { 3592 /* For hwrm_ver_get response Component id = 2 3593 * and Segment id = 0 3594 */ 3595 seg_hdr->component_id = cpu_to_le32(2); 3596 seg_hdr->segment_id = 0; 3597 } 3598 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3599 seg_hdr->length = cpu_to_le32(seg_len); 3600 seg_hdr->status = cpu_to_le32(status); 3601 seg_hdr->duration = cpu_to_le32(duration); 3602 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3603 seg_hdr->instance = cpu_to_le32(instance); 3604 } 3605 3606 static void 3607 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3608 time64_t start, s16 start_utc, u16 total_segs, 3609 int status) 3610 { 3611 time64_t end = ktime_get_real_seconds(); 3612 u32 os_ver_major = 0, os_ver_minor = 0; 3613 struct tm tm; 3614 3615 time64_to_tm(start, 0, &tm); 3616 memset(record, 0, sizeof(*record)); 3617 memcpy(record->signature, "cOrE", 4); 3618 record->flags = 0; 3619 record->low_version = 0; 3620 record->high_version = 1; 3621 record->asic_state = 0; 3622 strlcpy(record->system_name, utsname()->nodename, 3623 sizeof(record->system_name)); 3624 record->year = cpu_to_le16(tm.tm_year + 1900); 3625 record->month = cpu_to_le16(tm.tm_mon + 1); 3626 record->day = cpu_to_le16(tm.tm_mday); 3627 record->hour = cpu_to_le16(tm.tm_hour); 3628 record->minute = cpu_to_le16(tm.tm_min); 3629 record->second = cpu_to_le16(tm.tm_sec); 3630 record->utc_bias = cpu_to_le16(start_utc); 3631 strcpy(record->commandline, "ethtool -w"); 3632 record->total_segments = cpu_to_le32(total_segs); 3633 3634 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3635 record->os_ver_major = cpu_to_le32(os_ver_major); 3636 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3637 3638 strlcpy(record->os_name, utsname()->sysname, 32); 3639 time64_to_tm(end, 0, &tm); 3640 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3641 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3642 record->end_day = cpu_to_le16(tm.tm_mday); 3643 record->end_hour = cpu_to_le16(tm.tm_hour); 3644 record->end_minute = cpu_to_le16(tm.tm_min); 3645 record->end_second = cpu_to_le16(tm.tm_sec); 3646 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3647 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3648 bp->ver_resp.chip_rev << 8 | 3649 bp->ver_resp.chip_metal); 3650 record->asic_id2 = 0; 3651 record->coredump_status = cpu_to_le32(status); 3652 record->ioctl_low_version = 0; 3653 record->ioctl_high_version = 0; 3654 } 3655 3656 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3657 { 3658 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3659 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0; 3660 struct coredump_segment_record *seg_record = NULL; 3661 struct bnxt_coredump_segment_hdr seg_hdr; 3662 struct bnxt_coredump coredump = {NULL}; 3663 time64_t start_time; 3664 u16 start_utc; 3665 int rc = 0, i; 3666 3667 if (buf) 3668 buf_len = *dump_len; 3669 3670 start_time = ktime_get_real_seconds(); 3671 start_utc = sys_tz.tz_minuteswest * 60; 3672 seg_hdr_len = sizeof(seg_hdr); 3673 3674 /* First segment should be hwrm_ver_get response */ 3675 *dump_len = seg_hdr_len + ver_get_resp_len; 3676 if (buf) { 3677 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3678 0, 0, 0); 3679 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3680 offset += seg_hdr_len; 3681 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3682 offset += ver_get_resp_len; 3683 } 3684 3685 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3686 if (rc) { 3687 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3688 goto err; 3689 } 3690 3691 *dump_len += seg_hdr_len * coredump.total_segs; 3692 3693 seg_record = (struct coredump_segment_record *)coredump.data; 3694 seg_record_len = sizeof(*seg_record); 3695 3696 for (i = 0; i < coredump.total_segs; i++) { 3697 u16 comp_id = le16_to_cpu(seg_record->component_id); 3698 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3699 u32 duration = 0, seg_len = 0; 3700 unsigned long start, end; 3701 3702 if (buf && ((offset + seg_hdr_len) > 3703 BNXT_COREDUMP_BUF_LEN(buf_len))) { 3704 rc = -ENOBUFS; 3705 goto err; 3706 } 3707 3708 start = jiffies; 3709 3710 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3711 if (rc) { 3712 netdev_err(bp->dev, 3713 "Failed to initiate coredump for seg = %d\n", 3714 seg_record->segment_id); 3715 goto next_seg; 3716 } 3717 3718 /* Write segment data into the buffer */ 3719 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3720 &seg_len, buf, buf_len, 3721 offset + seg_hdr_len); 3722 if (rc && rc == -ENOBUFS) 3723 goto err; 3724 else if (rc) 3725 netdev_err(bp->dev, 3726 "Failed to retrieve coredump for seg = %d\n", 3727 seg_record->segment_id); 3728 3729 next_seg: 3730 end = jiffies; 3731 duration = jiffies_to_msecs(end - start); 3732 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3733 rc, duration, 0); 3734 3735 if (buf) { 3736 /* Write segment header into the buffer */ 3737 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3738 offset += seg_hdr_len + seg_len; 3739 } 3740 3741 *dump_len += seg_len; 3742 seg_record = 3743 (struct coredump_segment_record *)((u8 *)seg_record + 3744 seg_record_len); 3745 } 3746 3747 err: 3748 if (buf) 3749 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3750 start_utc, coredump.total_segs + 1, 3751 rc); 3752 kfree(coredump.data); 3753 *dump_len += sizeof(struct bnxt_coredump_record); 3754 if (rc == -ENOBUFS) 3755 netdev_err(bp->dev, "Firmware returned large coredump buffer\n"); 3756 return rc; 3757 } 3758 3759 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3760 { 3761 struct bnxt *bp = netdev_priv(dev); 3762 3763 if (dump->flag > BNXT_DUMP_CRASH) { 3764 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3765 return -EINVAL; 3766 } 3767 3768 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3769 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3770 return -EOPNOTSUPP; 3771 } 3772 3773 bp->dump_flag = dump->flag; 3774 return 0; 3775 } 3776 3777 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3778 { 3779 struct bnxt *bp = netdev_priv(dev); 3780 3781 if (bp->hwrm_spec_code < 0x10801) 3782 return -EOPNOTSUPP; 3783 3784 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3785 bp->ver_resp.hwrm_fw_min_8b << 16 | 3786 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3787 bp->ver_resp.hwrm_fw_rsvd_8b; 3788 3789 dump->flag = bp->dump_flag; 3790 if (bp->dump_flag == BNXT_DUMP_CRASH) 3791 dump->len = BNXT_CRASH_DUMP_LEN; 3792 else 3793 bnxt_get_coredump(bp, NULL, &dump->len); 3794 return 0; 3795 } 3796 3797 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3798 void *buf) 3799 { 3800 struct bnxt *bp = netdev_priv(dev); 3801 3802 if (bp->hwrm_spec_code < 0x10801) 3803 return -EOPNOTSUPP; 3804 3805 memset(buf, 0, dump->len); 3806 3807 dump->flag = bp->dump_flag; 3808 if (dump->flag == BNXT_DUMP_CRASH) { 3809 #ifdef CONFIG_TEE_BNXT_FW 3810 return tee_bnxt_copy_coredump(buf, 0, dump->len); 3811 #endif 3812 } else { 3813 return bnxt_get_coredump(bp, buf, &dump->len); 3814 } 3815 3816 return 0; 3817 } 3818 3819 void bnxt_ethtool_init(struct bnxt *bp) 3820 { 3821 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3822 struct hwrm_selftest_qlist_input req = {0}; 3823 struct bnxt_test_info *test_info; 3824 struct net_device *dev = bp->dev; 3825 int i, rc; 3826 3827 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3828 bnxt_get_pkgver(dev); 3829 3830 bp->num_tests = 0; 3831 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp)) 3832 return; 3833 3834 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3835 mutex_lock(&bp->hwrm_cmd_lock); 3836 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3837 if (rc) 3838 goto ethtool_init_exit; 3839 3840 test_info = bp->test_info; 3841 if (!test_info) 3842 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3843 if (!test_info) 3844 goto ethtool_init_exit; 3845 3846 bp->test_info = test_info; 3847 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3848 if (bp->num_tests > BNXT_MAX_TEST) 3849 bp->num_tests = BNXT_MAX_TEST; 3850 3851 test_info->offline_mask = resp->offline_tests; 3852 test_info->timeout = le16_to_cpu(resp->test_timeout); 3853 if (!test_info->timeout) 3854 test_info->timeout = HWRM_CMD_TIMEOUT; 3855 for (i = 0; i < bp->num_tests; i++) { 3856 char *str = test_info->string[i]; 3857 char *fw_str = resp->test0_name + i * 32; 3858 3859 if (i == BNXT_MACLPBK_TEST_IDX) { 3860 strcpy(str, "Mac loopback test (offline)"); 3861 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3862 strcpy(str, "Phy loopback test (offline)"); 3863 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3864 strcpy(str, "Ext loopback test (offline)"); 3865 } else if (i == BNXT_IRQ_TEST_IDX) { 3866 strcpy(str, "Interrupt_test (offline)"); 3867 } else { 3868 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3869 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3870 if (test_info->offline_mask & (1 << i)) 3871 strncat(str, " (offline)", 3872 ETH_GSTRING_LEN - strlen(str)); 3873 else 3874 strncat(str, " (online)", 3875 ETH_GSTRING_LEN - strlen(str)); 3876 } 3877 } 3878 3879 ethtool_init_exit: 3880 mutex_unlock(&bp->hwrm_cmd_lock); 3881 } 3882 3883 void bnxt_ethtool_free(struct bnxt *bp) 3884 { 3885 kfree(bp->test_info); 3886 bp->test_info = NULL; 3887 } 3888 3889 const struct ethtool_ops bnxt_ethtool_ops = { 3890 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3891 ETHTOOL_COALESCE_MAX_FRAMES | 3892 ETHTOOL_COALESCE_USECS_IRQ | 3893 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3894 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3895 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3896 .get_link_ksettings = bnxt_get_link_ksettings, 3897 .set_link_ksettings = bnxt_set_link_ksettings, 3898 .get_fecparam = bnxt_get_fecparam, 3899 .set_fecparam = bnxt_set_fecparam, 3900 .get_pause_stats = bnxt_get_pause_stats, 3901 .get_pauseparam = bnxt_get_pauseparam, 3902 .set_pauseparam = bnxt_set_pauseparam, 3903 .get_drvinfo = bnxt_get_drvinfo, 3904 .get_regs_len = bnxt_get_regs_len, 3905 .get_regs = bnxt_get_regs, 3906 .get_wol = bnxt_get_wol, 3907 .set_wol = bnxt_set_wol, 3908 .get_coalesce = bnxt_get_coalesce, 3909 .set_coalesce = bnxt_set_coalesce, 3910 .get_msglevel = bnxt_get_msglevel, 3911 .set_msglevel = bnxt_set_msglevel, 3912 .get_sset_count = bnxt_get_sset_count, 3913 .get_strings = bnxt_get_strings, 3914 .get_ethtool_stats = bnxt_get_ethtool_stats, 3915 .set_ringparam = bnxt_set_ringparam, 3916 .get_ringparam = bnxt_get_ringparam, 3917 .get_channels = bnxt_get_channels, 3918 .set_channels = bnxt_set_channels, 3919 .get_rxnfc = bnxt_get_rxnfc, 3920 .set_rxnfc = bnxt_set_rxnfc, 3921 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3922 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3923 .get_rxfh = bnxt_get_rxfh, 3924 .set_rxfh = bnxt_set_rxfh, 3925 .flash_device = bnxt_flash_device, 3926 .get_eeprom_len = bnxt_get_eeprom_len, 3927 .get_eeprom = bnxt_get_eeprom, 3928 .set_eeprom = bnxt_set_eeprom, 3929 .get_link = bnxt_get_link, 3930 .get_eee = bnxt_get_eee, 3931 .set_eee = bnxt_set_eee, 3932 .get_module_info = bnxt_get_module_info, 3933 .get_module_eeprom = bnxt_get_module_eeprom, 3934 .nway_reset = bnxt_nway_reset, 3935 .set_phys_id = bnxt_set_phys_id, 3936 .self_test = bnxt_self_test, 3937 .reset = bnxt_reset, 3938 .set_dump = bnxt_set_dump, 3939 .get_dump_flag = bnxt_get_dump_flag, 3940 .get_dump_data = bnxt_get_dump_data, 3941 }; 3942