1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/ethtool_netlink.h> 15 #include <linux/linkmode.h> 16 #include <linux/interrupt.h> 17 #include <linux/pci.h> 18 #include <linux/etherdevice.h> 19 #include <linux/crc32.h> 20 #include <linux/firmware.h> 21 #include <linux/utsname.h> 22 #include <linux/time.h> 23 #include <linux/ptp_clock_kernel.h> 24 #include <linux/net_tstamp.h> 25 #include <linux/timecounter.h> 26 #include <net/netlink.h> 27 #include "bnxt_hsi.h" 28 #include "bnxt.h" 29 #include "bnxt_hwrm.h" 30 #include "bnxt_ulp.h" 31 #include "bnxt_xdp.h" 32 #include "bnxt_ptp.h" 33 #include "bnxt_ethtool.h" 34 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 35 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 36 #include "bnxt_coredump.h" 37 38 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 39 do { \ 40 if (extack) \ 41 NL_SET_ERR_MSG_MOD(extack, msg); \ 42 netdev_err(dev, "%s\n", msg); \ 43 } while (0) 44 45 static u32 bnxt_get_msglevel(struct net_device *dev) 46 { 47 struct bnxt *bp = netdev_priv(dev); 48 49 return bp->msg_enable; 50 } 51 52 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 53 { 54 struct bnxt *bp = netdev_priv(dev); 55 56 bp->msg_enable = value; 57 } 58 59 static int bnxt_get_coalesce(struct net_device *dev, 60 struct ethtool_coalesce *coal, 61 struct kernel_ethtool_coalesce *kernel_coal, 62 struct netlink_ext_ack *extack) 63 { 64 struct bnxt *bp = netdev_priv(dev); 65 struct bnxt_coal *hw_coal; 66 u16 mult; 67 68 memset(coal, 0, sizeof(*coal)); 69 70 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 71 72 hw_coal = &bp->rx_coal; 73 mult = hw_coal->bufs_per_record; 74 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 75 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 76 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 77 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 78 if (hw_coal->flags & 79 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 80 kernel_coal->use_cqe_mode_rx = true; 81 82 hw_coal = &bp->tx_coal; 83 mult = hw_coal->bufs_per_record; 84 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 85 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 86 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 87 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 88 if (hw_coal->flags & 89 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 90 kernel_coal->use_cqe_mode_tx = true; 91 92 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 93 94 return 0; 95 } 96 97 static int bnxt_set_coalesce(struct net_device *dev, 98 struct ethtool_coalesce *coal, 99 struct kernel_ethtool_coalesce *kernel_coal, 100 struct netlink_ext_ack *extack) 101 { 102 struct bnxt *bp = netdev_priv(dev); 103 bool update_stats = false; 104 struct bnxt_coal *hw_coal; 105 int rc = 0; 106 u16 mult; 107 108 if (coal->use_adaptive_rx_coalesce) { 109 bp->flags |= BNXT_FLAG_DIM; 110 } else { 111 if (bp->flags & BNXT_FLAG_DIM) { 112 bp->flags &= ~(BNXT_FLAG_DIM); 113 goto reset_coalesce; 114 } 115 } 116 117 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 118 !(bp->coal_cap.cmpl_params & 119 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 120 return -EOPNOTSUPP; 121 122 hw_coal = &bp->rx_coal; 123 mult = hw_coal->bufs_per_record; 124 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 125 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 126 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 127 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 128 hw_coal->flags &= 129 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 130 if (kernel_coal->use_cqe_mode_rx) 131 hw_coal->flags |= 132 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 133 134 hw_coal = &bp->tx_coal; 135 mult = hw_coal->bufs_per_record; 136 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 137 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 138 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 139 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 140 hw_coal->flags &= 141 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 142 if (kernel_coal->use_cqe_mode_tx) 143 hw_coal->flags |= 144 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 145 146 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 147 u32 stats_ticks = coal->stats_block_coalesce_usecs; 148 149 /* Allow 0, which means disable. */ 150 if (stats_ticks) 151 stats_ticks = clamp_t(u32, stats_ticks, 152 BNXT_MIN_STATS_COAL_TICKS, 153 BNXT_MAX_STATS_COAL_TICKS); 154 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 155 bp->stats_coal_ticks = stats_ticks; 156 if (bp->stats_coal_ticks) 157 bp->current_interval = 158 bp->stats_coal_ticks * HZ / 1000000; 159 else 160 bp->current_interval = BNXT_TIMER_INTERVAL; 161 update_stats = true; 162 } 163 164 reset_coalesce: 165 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 166 if (update_stats) { 167 bnxt_close_nic(bp, true, false); 168 rc = bnxt_open_nic(bp, true, false); 169 } else { 170 rc = bnxt_hwrm_set_coal(bp); 171 } 172 } 173 174 return rc; 175 } 176 177 static const char * const bnxt_ring_rx_stats_str[] = { 178 "rx_ucast_packets", 179 "rx_mcast_packets", 180 "rx_bcast_packets", 181 "rx_discards", 182 "rx_errors", 183 "rx_ucast_bytes", 184 "rx_mcast_bytes", 185 "rx_bcast_bytes", 186 }; 187 188 static const char * const bnxt_ring_tx_stats_str[] = { 189 "tx_ucast_packets", 190 "tx_mcast_packets", 191 "tx_bcast_packets", 192 "tx_errors", 193 "tx_discards", 194 "tx_ucast_bytes", 195 "tx_mcast_bytes", 196 "tx_bcast_bytes", 197 }; 198 199 static const char * const bnxt_ring_tpa_stats_str[] = { 200 "tpa_packets", 201 "tpa_bytes", 202 "tpa_events", 203 "tpa_aborts", 204 }; 205 206 static const char * const bnxt_ring_tpa2_stats_str[] = { 207 "rx_tpa_eligible_pkt", 208 "rx_tpa_eligible_bytes", 209 "rx_tpa_pkt", 210 "rx_tpa_bytes", 211 "rx_tpa_errors", 212 "rx_tpa_events", 213 }; 214 215 static const char * const bnxt_rx_sw_stats_str[] = { 216 "rx_l4_csum_errors", 217 "rx_resets", 218 "rx_buf_errors", 219 }; 220 221 static const char * const bnxt_cmn_sw_stats_str[] = { 222 "missed_irqs", 223 }; 224 225 #define BNXT_RX_STATS_ENTRY(counter) \ 226 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 227 228 #define BNXT_TX_STATS_ENTRY(counter) \ 229 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 230 231 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 232 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 233 234 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 235 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 236 237 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 238 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 240 241 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 242 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 244 245 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 246 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 247 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 254 255 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 256 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 257 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 264 265 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 266 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 268 269 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 270 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 271 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 272 273 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 274 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 275 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 282 283 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 284 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 285 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 292 293 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 294 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 296 297 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 298 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 306 307 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 308 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 309 __stringify(counter##_pri##n) } 310 311 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 312 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 313 __stringify(counter##_pri##n) } 314 315 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 316 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 317 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 324 325 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 326 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 327 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 334 335 enum { 336 RX_TOTAL_DISCARDS, 337 TX_TOTAL_DISCARDS, 338 RX_NETPOLL_DISCARDS, 339 }; 340 341 static const char *const bnxt_ring_err_stats_arr[] = { 342 "rx_total_l4_csum_errors", 343 "rx_total_resets", 344 "rx_total_buf_errors", 345 "rx_total_oom_discards", 346 "rx_total_netpoll_discards", 347 "rx_total_ring_discards", 348 "tx_total_resets", 349 "tx_total_ring_discards", 350 "total_missed_irqs", 351 }; 352 353 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 354 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 355 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 356 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 357 358 static const struct { 359 long offset; 360 char string[ETH_GSTRING_LEN]; 361 } bnxt_port_stats_arr[] = { 362 BNXT_RX_STATS_ENTRY(rx_64b_frames), 363 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 364 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 365 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 366 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 367 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 368 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 369 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 370 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 371 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 372 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 373 BNXT_RX_STATS_ENTRY(rx_total_frames), 374 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 375 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 376 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 377 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 378 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 379 BNXT_RX_STATS_ENTRY(rx_pause_frames), 380 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 381 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 382 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 383 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 384 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 385 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 386 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 387 BNXT_RX_STATS_ENTRY(rx_good_frames), 388 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 396 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 397 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 399 BNXT_RX_STATS_ENTRY(rx_bytes), 400 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 401 BNXT_RX_STATS_ENTRY(rx_runt_frames), 402 BNXT_RX_STATS_ENTRY(rx_stat_discard), 403 BNXT_RX_STATS_ENTRY(rx_stat_err), 404 405 BNXT_TX_STATS_ENTRY(tx_64b_frames), 406 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 407 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 408 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 409 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 410 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 411 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 412 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 413 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 414 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 415 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 416 BNXT_TX_STATS_ENTRY(tx_good_frames), 417 BNXT_TX_STATS_ENTRY(tx_total_frames), 418 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 419 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 420 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 421 BNXT_TX_STATS_ENTRY(tx_pause_frames), 422 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 423 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 424 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 425 BNXT_TX_STATS_ENTRY(tx_err), 426 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 427 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 435 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 437 BNXT_TX_STATS_ENTRY(tx_total_collisions), 438 BNXT_TX_STATS_ENTRY(tx_bytes), 439 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 440 BNXT_TX_STATS_ENTRY(tx_stat_discard), 441 BNXT_TX_STATS_ENTRY(tx_stat_error), 442 }; 443 444 static const struct { 445 long offset; 446 char string[ETH_GSTRING_LEN]; 447 } bnxt_port_stats_ext_arr[] = { 448 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 449 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 450 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 451 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 453 BNXT_RX_STATS_EXT_COS_ENTRIES, 454 BNXT_RX_STATS_EXT_PFC_ENTRIES, 455 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 456 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 457 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 458 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 459 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 460 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 462 }; 463 464 static const struct { 465 long offset; 466 char string[ETH_GSTRING_LEN]; 467 } bnxt_tx_port_stats_ext_arr[] = { 468 BNXT_TX_STATS_EXT_COS_ENTRIES, 469 BNXT_TX_STATS_EXT_PFC_ENTRIES, 470 }; 471 472 static const struct { 473 long base_off; 474 char string[ETH_GSTRING_LEN]; 475 } bnxt_rx_bytes_pri_arr[] = { 476 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 477 }; 478 479 static const struct { 480 long base_off; 481 char string[ETH_GSTRING_LEN]; 482 } bnxt_rx_pkts_pri_arr[] = { 483 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 484 }; 485 486 static const struct { 487 long base_off; 488 char string[ETH_GSTRING_LEN]; 489 } bnxt_tx_bytes_pri_arr[] = { 490 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 491 }; 492 493 static const struct { 494 long base_off; 495 char string[ETH_GSTRING_LEN]; 496 } bnxt_tx_pkts_pri_arr[] = { 497 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 498 }; 499 500 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 501 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 502 #define BNXT_NUM_STATS_PRI \ 503 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 504 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 505 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 507 508 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 509 { 510 if (BNXT_SUPPORTS_TPA(bp)) { 511 if (bp->max_tpa_v2) { 512 if (BNXT_CHIP_P5_THOR(bp)) 513 return BNXT_NUM_TPA_RING_STATS_P5; 514 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 515 } 516 return BNXT_NUM_TPA_RING_STATS; 517 } 518 return 0; 519 } 520 521 static int bnxt_get_num_ring_stats(struct bnxt *bp) 522 { 523 int rx, tx, cmn; 524 525 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 526 bnxt_get_num_tpa_ring_stats(bp); 527 tx = NUM_RING_TX_HW_STATS; 528 cmn = NUM_RING_CMN_SW_STATS; 529 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 530 cmn * bp->cp_nr_rings; 531 } 532 533 static int bnxt_get_num_stats(struct bnxt *bp) 534 { 535 int num_stats = bnxt_get_num_ring_stats(bp); 536 537 num_stats += BNXT_NUM_RING_ERR_STATS; 538 539 if (bp->flags & BNXT_FLAG_PORT_STATS) 540 num_stats += BNXT_NUM_PORT_STATS; 541 542 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 543 num_stats += bp->fw_rx_stats_ext_size + 544 bp->fw_tx_stats_ext_size; 545 if (bp->pri2cos_valid) 546 num_stats += BNXT_NUM_STATS_PRI; 547 } 548 549 return num_stats; 550 } 551 552 static int bnxt_get_sset_count(struct net_device *dev, int sset) 553 { 554 struct bnxt *bp = netdev_priv(dev); 555 556 switch (sset) { 557 case ETH_SS_STATS: 558 return bnxt_get_num_stats(bp); 559 case ETH_SS_TEST: 560 if (!bp->num_tests) 561 return -EOPNOTSUPP; 562 return bp->num_tests; 563 default: 564 return -EOPNOTSUPP; 565 } 566 } 567 568 static bool is_rx_ring(struct bnxt *bp, int ring_num) 569 { 570 return ring_num < bp->rx_nr_rings; 571 } 572 573 static bool is_tx_ring(struct bnxt *bp, int ring_num) 574 { 575 int tx_base = 0; 576 577 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 578 tx_base = bp->rx_nr_rings; 579 580 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 581 return true; 582 return false; 583 } 584 585 static void bnxt_get_ethtool_stats(struct net_device *dev, 586 struct ethtool_stats *stats, u64 *buf) 587 { 588 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 589 struct bnxt *bp = netdev_priv(dev); 590 u64 *curr, *prev; 591 u32 tpa_stats; 592 u32 i, j = 0; 593 594 if (!bp->bnapi) { 595 j += bnxt_get_num_ring_stats(bp); 596 goto skip_ring_stats; 597 } 598 599 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 600 for (i = 0; i < bp->cp_nr_rings; i++) { 601 struct bnxt_napi *bnapi = bp->bnapi[i]; 602 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 603 u64 *sw_stats = cpr->stats.sw_stats; 604 u64 *sw; 605 int k; 606 607 if (is_rx_ring(bp, i)) { 608 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 609 buf[j] = sw_stats[k]; 610 } 611 if (is_tx_ring(bp, i)) { 612 k = NUM_RING_RX_HW_STATS; 613 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 614 j++, k++) 615 buf[j] = sw_stats[k]; 616 } 617 if (!tpa_stats || !is_rx_ring(bp, i)) 618 goto skip_tpa_ring_stats; 619 620 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 622 tpa_stats; j++, k++) 623 buf[j] = sw_stats[k]; 624 625 skip_tpa_ring_stats: 626 sw = (u64 *)&cpr->sw_stats.rx; 627 if (is_rx_ring(bp, i)) { 628 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 629 buf[j] = sw[k]; 630 } 631 632 sw = (u64 *)&cpr->sw_stats.cmn; 633 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 634 buf[j] = sw[k]; 635 } 636 637 bnxt_get_ring_err_stats(bp, &ring_err_stats); 638 639 skip_ring_stats: 640 curr = &ring_err_stats.rx_total_l4_csum_errors; 641 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 642 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 643 buf[j] = *curr + *prev; 644 645 if (bp->flags & BNXT_FLAG_PORT_STATS) { 646 u64 *port_stats = bp->port_stats.sw_stats; 647 648 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 649 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 650 } 651 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 652 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 653 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 654 655 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 656 buf[j] = *(rx_port_stats_ext + 657 bnxt_port_stats_ext_arr[i].offset); 658 } 659 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 660 buf[j] = *(tx_port_stats_ext + 661 bnxt_tx_port_stats_ext_arr[i].offset); 662 } 663 if (bp->pri2cos_valid) { 664 for (i = 0; i < 8; i++, j++) { 665 long n = bnxt_rx_bytes_pri_arr[i].base_off + 666 bp->pri2cos_idx[i]; 667 668 buf[j] = *(rx_port_stats_ext + n); 669 } 670 for (i = 0; i < 8; i++, j++) { 671 long n = bnxt_rx_pkts_pri_arr[i].base_off + 672 bp->pri2cos_idx[i]; 673 674 buf[j] = *(rx_port_stats_ext + n); 675 } 676 for (i = 0; i < 8; i++, j++) { 677 long n = bnxt_tx_bytes_pri_arr[i].base_off + 678 bp->pri2cos_idx[i]; 679 680 buf[j] = *(tx_port_stats_ext + n); 681 } 682 for (i = 0; i < 8; i++, j++) { 683 long n = bnxt_tx_pkts_pri_arr[i].base_off + 684 bp->pri2cos_idx[i]; 685 686 buf[j] = *(tx_port_stats_ext + n); 687 } 688 } 689 } 690 } 691 692 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 693 { 694 struct bnxt *bp = netdev_priv(dev); 695 static const char * const *str; 696 u32 i, j, num_str; 697 698 switch (stringset) { 699 case ETH_SS_STATS: 700 for (i = 0; i < bp->cp_nr_rings; i++) { 701 if (is_rx_ring(bp, i)) { 702 num_str = NUM_RING_RX_HW_STATS; 703 for (j = 0; j < num_str; j++) { 704 sprintf(buf, "[%d]: %s", i, 705 bnxt_ring_rx_stats_str[j]); 706 buf += ETH_GSTRING_LEN; 707 } 708 } 709 if (is_tx_ring(bp, i)) { 710 num_str = NUM_RING_TX_HW_STATS; 711 for (j = 0; j < num_str; j++) { 712 sprintf(buf, "[%d]: %s", i, 713 bnxt_ring_tx_stats_str[j]); 714 buf += ETH_GSTRING_LEN; 715 } 716 } 717 num_str = bnxt_get_num_tpa_ring_stats(bp); 718 if (!num_str || !is_rx_ring(bp, i)) 719 goto skip_tpa_stats; 720 721 if (bp->max_tpa_v2) 722 str = bnxt_ring_tpa2_stats_str; 723 else 724 str = bnxt_ring_tpa_stats_str; 725 726 for (j = 0; j < num_str; j++) { 727 sprintf(buf, "[%d]: %s", i, str[j]); 728 buf += ETH_GSTRING_LEN; 729 } 730 skip_tpa_stats: 731 if (is_rx_ring(bp, i)) { 732 num_str = NUM_RING_RX_SW_STATS; 733 for (j = 0; j < num_str; j++) { 734 sprintf(buf, "[%d]: %s", i, 735 bnxt_rx_sw_stats_str[j]); 736 buf += ETH_GSTRING_LEN; 737 } 738 } 739 num_str = NUM_RING_CMN_SW_STATS; 740 for (j = 0; j < num_str; j++) { 741 sprintf(buf, "[%d]: %s", i, 742 bnxt_cmn_sw_stats_str[j]); 743 buf += ETH_GSTRING_LEN; 744 } 745 } 746 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) { 747 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN); 748 buf += ETH_GSTRING_LEN; 749 } 750 751 if (bp->flags & BNXT_FLAG_PORT_STATS) { 752 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 753 strcpy(buf, bnxt_port_stats_arr[i].string); 754 buf += ETH_GSTRING_LEN; 755 } 756 } 757 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 758 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 759 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 760 buf += ETH_GSTRING_LEN; 761 } 762 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 763 strcpy(buf, 764 bnxt_tx_port_stats_ext_arr[i].string); 765 buf += ETH_GSTRING_LEN; 766 } 767 if (bp->pri2cos_valid) { 768 for (i = 0; i < 8; i++) { 769 strcpy(buf, 770 bnxt_rx_bytes_pri_arr[i].string); 771 buf += ETH_GSTRING_LEN; 772 } 773 for (i = 0; i < 8; i++) { 774 strcpy(buf, 775 bnxt_rx_pkts_pri_arr[i].string); 776 buf += ETH_GSTRING_LEN; 777 } 778 for (i = 0; i < 8; i++) { 779 strcpy(buf, 780 bnxt_tx_bytes_pri_arr[i].string); 781 buf += ETH_GSTRING_LEN; 782 } 783 for (i = 0; i < 8; i++) { 784 strcpy(buf, 785 bnxt_tx_pkts_pri_arr[i].string); 786 buf += ETH_GSTRING_LEN; 787 } 788 } 789 } 790 break; 791 case ETH_SS_TEST: 792 if (bp->num_tests) 793 memcpy(buf, bp->test_info->string, 794 bp->num_tests * ETH_GSTRING_LEN); 795 break; 796 default: 797 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 798 stringset); 799 break; 800 } 801 } 802 803 static void bnxt_get_ringparam(struct net_device *dev, 804 struct ethtool_ringparam *ering, 805 struct kernel_ethtool_ringparam *kernel_ering, 806 struct netlink_ext_ack *extack) 807 { 808 struct bnxt *bp = netdev_priv(dev); 809 810 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 811 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 812 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 813 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 814 } else { 815 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 816 ering->rx_jumbo_max_pending = 0; 817 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 818 } 819 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 820 821 ering->rx_pending = bp->rx_ring_size; 822 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 823 ering->tx_pending = bp->tx_ring_size; 824 } 825 826 static int bnxt_set_ringparam(struct net_device *dev, 827 struct ethtool_ringparam *ering, 828 struct kernel_ethtool_ringparam *kernel_ering, 829 struct netlink_ext_ack *extack) 830 { 831 struct bnxt *bp = netdev_priv(dev); 832 833 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 834 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 835 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 836 return -EINVAL; 837 838 if (netif_running(dev)) 839 bnxt_close_nic(bp, false, false); 840 841 bp->rx_ring_size = ering->rx_pending; 842 bp->tx_ring_size = ering->tx_pending; 843 bnxt_set_ring_params(bp); 844 845 if (netif_running(dev)) 846 return bnxt_open_nic(bp, false, false); 847 848 return 0; 849 } 850 851 static void bnxt_get_channels(struct net_device *dev, 852 struct ethtool_channels *channel) 853 { 854 struct bnxt *bp = netdev_priv(dev); 855 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 856 int max_rx_rings, max_tx_rings, tcs; 857 int max_tx_sch_inputs, tx_grps; 858 859 /* Get the most up-to-date max_tx_sch_inputs. */ 860 if (netif_running(dev) && BNXT_NEW_RM(bp)) 861 bnxt_hwrm_func_resc_qcaps(bp, false); 862 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 863 864 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 865 if (max_tx_sch_inputs) 866 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 867 868 tcs = netdev_get_num_tc(dev); 869 tx_grps = max(tcs, 1); 870 if (bp->tx_nr_rings_xdp) 871 tx_grps++; 872 max_tx_rings /= tx_grps; 873 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 874 875 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 876 max_rx_rings = 0; 877 max_tx_rings = 0; 878 } 879 if (max_tx_sch_inputs) 880 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 881 882 if (tcs > 1) 883 max_tx_rings /= tcs; 884 885 channel->max_rx = max_rx_rings; 886 channel->max_tx = max_tx_rings; 887 channel->max_other = 0; 888 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 889 channel->combined_count = bp->rx_nr_rings; 890 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 891 channel->combined_count--; 892 } else { 893 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 894 channel->rx_count = bp->rx_nr_rings; 895 channel->tx_count = bp->tx_nr_rings_per_tc; 896 } 897 } 898 } 899 900 static int bnxt_set_channels(struct net_device *dev, 901 struct ethtool_channels *channel) 902 { 903 struct bnxt *bp = netdev_priv(dev); 904 int req_tx_rings, req_rx_rings, tcs; 905 bool sh = false; 906 int tx_xdp = 0; 907 int rc = 0; 908 909 if (channel->other_count) 910 return -EINVAL; 911 912 if (!channel->combined_count && 913 (!channel->rx_count || !channel->tx_count)) 914 return -EINVAL; 915 916 if (channel->combined_count && 917 (channel->rx_count || channel->tx_count)) 918 return -EINVAL; 919 920 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 921 channel->tx_count)) 922 return -EINVAL; 923 924 if (channel->combined_count) 925 sh = true; 926 927 tcs = netdev_get_num_tc(dev); 928 929 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 930 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 931 if (bp->tx_nr_rings_xdp) { 932 if (!sh) { 933 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 934 return -EINVAL; 935 } 936 tx_xdp = req_rx_rings; 937 } 938 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 939 if (rc) { 940 netdev_warn(dev, "Unable to allocate the requested rings\n"); 941 return rc; 942 } 943 944 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 945 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 946 netif_is_rxfh_configured(dev)) { 947 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 948 return -EINVAL; 949 } 950 951 if (netif_running(dev)) { 952 if (BNXT_PF(bp)) { 953 /* TODO CHIMP_FW: Send message to all VF's 954 * before PF unload 955 */ 956 } 957 bnxt_close_nic(bp, true, false); 958 } 959 960 if (sh) { 961 bp->flags |= BNXT_FLAG_SHARED_RINGS; 962 bp->rx_nr_rings = channel->combined_count; 963 bp->tx_nr_rings_per_tc = channel->combined_count; 964 } else { 965 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 966 bp->rx_nr_rings = channel->rx_count; 967 bp->tx_nr_rings_per_tc = channel->tx_count; 968 } 969 bp->tx_nr_rings_xdp = tx_xdp; 970 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 971 if (tcs > 1) 972 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 973 974 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 975 bp->tx_nr_rings + bp->rx_nr_rings; 976 977 /* After changing number of rx channels, update NTUPLE feature. */ 978 netdev_update_features(dev); 979 if (netif_running(dev)) { 980 rc = bnxt_open_nic(bp, true, false); 981 if ((!rc) && BNXT_PF(bp)) { 982 /* TODO CHIMP_FW: Send message to all VF's 983 * to renable 984 */ 985 } 986 } else { 987 rc = bnxt_reserve_rings(bp, true); 988 } 989 990 return rc; 991 } 992 993 #ifdef CONFIG_RFS_ACCEL 994 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 995 u32 *rule_locs) 996 { 997 int i, j = 0; 998 999 cmd->data = bp->ntp_fltr_count; 1000 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1001 struct hlist_head *head; 1002 struct bnxt_ntuple_filter *fltr; 1003 1004 head = &bp->ntp_fltr_hash_tbl[i]; 1005 rcu_read_lock(); 1006 hlist_for_each_entry_rcu(fltr, head, hash) { 1007 if (j == cmd->rule_cnt) 1008 break; 1009 rule_locs[j++] = fltr->sw_id; 1010 } 1011 rcu_read_unlock(); 1012 if (j == cmd->rule_cnt) 1013 break; 1014 } 1015 cmd->rule_cnt = j; 1016 return 0; 1017 } 1018 1019 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1020 { 1021 struct ethtool_rx_flow_spec *fs = 1022 (struct ethtool_rx_flow_spec *)&cmd->fs; 1023 struct bnxt_ntuple_filter *fltr; 1024 struct flow_keys *fkeys; 1025 int i, rc = -EINVAL; 1026 1027 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1028 return rc; 1029 1030 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1031 struct hlist_head *head; 1032 1033 head = &bp->ntp_fltr_hash_tbl[i]; 1034 rcu_read_lock(); 1035 hlist_for_each_entry_rcu(fltr, head, hash) { 1036 if (fltr->sw_id == fs->location) 1037 goto fltr_found; 1038 } 1039 rcu_read_unlock(); 1040 } 1041 return rc; 1042 1043 fltr_found: 1044 fkeys = &fltr->fkeys; 1045 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1046 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1047 fs->flow_type = TCP_V4_FLOW; 1048 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1049 fs->flow_type = UDP_V4_FLOW; 1050 else 1051 goto fltr_err; 1052 1053 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1054 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1055 1056 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1057 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1058 1059 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1060 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1061 1062 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1063 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1064 } else { 1065 int i; 1066 1067 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1068 fs->flow_type = TCP_V6_FLOW; 1069 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1070 fs->flow_type = UDP_V6_FLOW; 1071 else 1072 goto fltr_err; 1073 1074 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1075 fkeys->addrs.v6addrs.src; 1076 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1077 fkeys->addrs.v6addrs.dst; 1078 for (i = 0; i < 4; i++) { 1079 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1080 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1081 } 1082 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1083 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1084 1085 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1086 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1087 } 1088 1089 fs->ring_cookie = fltr->rxq; 1090 rc = 0; 1091 1092 fltr_err: 1093 rcu_read_unlock(); 1094 1095 return rc; 1096 } 1097 #endif 1098 1099 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1100 { 1101 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1102 return RXH_IP_SRC | RXH_IP_DST; 1103 return 0; 1104 } 1105 1106 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1107 { 1108 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1109 return RXH_IP_SRC | RXH_IP_DST; 1110 return 0; 1111 } 1112 1113 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1114 { 1115 cmd->data = 0; 1116 switch (cmd->flow_type) { 1117 case TCP_V4_FLOW: 1118 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1119 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1120 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1121 cmd->data |= get_ethtool_ipv4_rss(bp); 1122 break; 1123 case UDP_V4_FLOW: 1124 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1125 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1126 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1127 fallthrough; 1128 case SCTP_V4_FLOW: 1129 case AH_ESP_V4_FLOW: 1130 case AH_V4_FLOW: 1131 case ESP_V4_FLOW: 1132 case IPV4_FLOW: 1133 cmd->data |= get_ethtool_ipv4_rss(bp); 1134 break; 1135 1136 case TCP_V6_FLOW: 1137 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1138 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1139 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1140 cmd->data |= get_ethtool_ipv6_rss(bp); 1141 break; 1142 case UDP_V6_FLOW: 1143 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1144 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1145 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1146 fallthrough; 1147 case SCTP_V6_FLOW: 1148 case AH_ESP_V6_FLOW: 1149 case AH_V6_FLOW: 1150 case ESP_V6_FLOW: 1151 case IPV6_FLOW: 1152 cmd->data |= get_ethtool_ipv6_rss(bp); 1153 break; 1154 } 1155 return 0; 1156 } 1157 1158 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1159 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1160 1161 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1162 { 1163 u32 rss_hash_cfg = bp->rss_hash_cfg; 1164 int tuple, rc = 0; 1165 1166 if (cmd->data == RXH_4TUPLE) 1167 tuple = 4; 1168 else if (cmd->data == RXH_2TUPLE) 1169 tuple = 2; 1170 else if (!cmd->data) 1171 tuple = 0; 1172 else 1173 return -EINVAL; 1174 1175 if (cmd->flow_type == TCP_V4_FLOW) { 1176 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1177 if (tuple == 4) 1178 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1179 } else if (cmd->flow_type == UDP_V4_FLOW) { 1180 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1181 return -EINVAL; 1182 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1183 if (tuple == 4) 1184 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1185 } else if (cmd->flow_type == TCP_V6_FLOW) { 1186 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1187 if (tuple == 4) 1188 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1189 } else if (cmd->flow_type == UDP_V6_FLOW) { 1190 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1191 return -EINVAL; 1192 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1193 if (tuple == 4) 1194 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1195 } else if (tuple == 4) { 1196 return -EINVAL; 1197 } 1198 1199 switch (cmd->flow_type) { 1200 case TCP_V4_FLOW: 1201 case UDP_V4_FLOW: 1202 case SCTP_V4_FLOW: 1203 case AH_ESP_V4_FLOW: 1204 case AH_V4_FLOW: 1205 case ESP_V4_FLOW: 1206 case IPV4_FLOW: 1207 if (tuple == 2) 1208 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1209 else if (!tuple) 1210 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1211 break; 1212 1213 case TCP_V6_FLOW: 1214 case UDP_V6_FLOW: 1215 case SCTP_V6_FLOW: 1216 case AH_ESP_V6_FLOW: 1217 case AH_V6_FLOW: 1218 case ESP_V6_FLOW: 1219 case IPV6_FLOW: 1220 if (tuple == 2) 1221 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1222 else if (!tuple) 1223 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1224 break; 1225 } 1226 1227 if (bp->rss_hash_cfg == rss_hash_cfg) 1228 return 0; 1229 1230 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA) 1231 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1232 bp->rss_hash_cfg = rss_hash_cfg; 1233 if (netif_running(bp->dev)) { 1234 bnxt_close_nic(bp, false, false); 1235 rc = bnxt_open_nic(bp, false, false); 1236 } 1237 return rc; 1238 } 1239 1240 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1241 u32 *rule_locs) 1242 { 1243 struct bnxt *bp = netdev_priv(dev); 1244 int rc = 0; 1245 1246 switch (cmd->cmd) { 1247 #ifdef CONFIG_RFS_ACCEL 1248 case ETHTOOL_GRXRINGS: 1249 cmd->data = bp->rx_nr_rings; 1250 break; 1251 1252 case ETHTOOL_GRXCLSRLCNT: 1253 cmd->rule_cnt = bp->ntp_fltr_count; 1254 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1255 break; 1256 1257 case ETHTOOL_GRXCLSRLALL: 1258 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1259 break; 1260 1261 case ETHTOOL_GRXCLSRULE: 1262 rc = bnxt_grxclsrule(bp, cmd); 1263 break; 1264 #endif 1265 1266 case ETHTOOL_GRXFH: 1267 rc = bnxt_grxfh(bp, cmd); 1268 break; 1269 1270 default: 1271 rc = -EOPNOTSUPP; 1272 break; 1273 } 1274 1275 return rc; 1276 } 1277 1278 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1279 { 1280 struct bnxt *bp = netdev_priv(dev); 1281 int rc; 1282 1283 switch (cmd->cmd) { 1284 case ETHTOOL_SRXFH: 1285 rc = bnxt_srxfh(bp, cmd); 1286 break; 1287 1288 default: 1289 rc = -EOPNOTSUPP; 1290 break; 1291 } 1292 return rc; 1293 } 1294 1295 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1296 { 1297 struct bnxt *bp = netdev_priv(dev); 1298 1299 if (bp->flags & BNXT_FLAG_CHIP_P5) 1300 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1301 return HW_HASH_INDEX_SIZE; 1302 } 1303 1304 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1305 { 1306 return HW_HASH_KEY_SIZE; 1307 } 1308 1309 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1310 u8 *hfunc) 1311 { 1312 struct bnxt *bp = netdev_priv(dev); 1313 struct bnxt_vnic_info *vnic; 1314 u32 i, tbl_size; 1315 1316 if (hfunc) 1317 *hfunc = ETH_RSS_HASH_TOP; 1318 1319 if (!bp->vnic_info) 1320 return 0; 1321 1322 vnic = &bp->vnic_info[0]; 1323 if (indir && bp->rss_indir_tbl) { 1324 tbl_size = bnxt_get_rxfh_indir_size(dev); 1325 for (i = 0; i < tbl_size; i++) 1326 indir[i] = bp->rss_indir_tbl[i]; 1327 } 1328 1329 if (key && vnic->rss_hash_key) 1330 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1331 1332 return 0; 1333 } 1334 1335 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1336 const u8 *key, const u8 hfunc) 1337 { 1338 struct bnxt *bp = netdev_priv(dev); 1339 int rc = 0; 1340 1341 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1342 return -EOPNOTSUPP; 1343 1344 if (key) 1345 return -EOPNOTSUPP; 1346 1347 if (indir) { 1348 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1349 1350 for (i = 0; i < tbl_size; i++) 1351 bp->rss_indir_tbl[i] = indir[i]; 1352 pad = bp->rss_indir_tbl_entries - tbl_size; 1353 if (pad) 1354 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1355 } 1356 1357 if (netif_running(bp->dev)) { 1358 bnxt_close_nic(bp, false, false); 1359 rc = bnxt_open_nic(bp, false, false); 1360 } 1361 return rc; 1362 } 1363 1364 static void bnxt_get_drvinfo(struct net_device *dev, 1365 struct ethtool_drvinfo *info) 1366 { 1367 struct bnxt *bp = netdev_priv(dev); 1368 1369 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1370 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1371 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1372 info->n_stats = bnxt_get_num_stats(bp); 1373 info->testinfo_len = bp->num_tests; 1374 /* TODO CHIMP_FW: eeprom dump details */ 1375 info->eedump_len = 0; 1376 /* TODO CHIMP FW: reg dump details */ 1377 info->regdump_len = 0; 1378 } 1379 1380 static int bnxt_get_regs_len(struct net_device *dev) 1381 { 1382 struct bnxt *bp = netdev_priv(dev); 1383 int reg_len; 1384 1385 if (!BNXT_PF(bp)) 1386 return -EOPNOTSUPP; 1387 1388 reg_len = BNXT_PXP_REG_LEN; 1389 1390 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1391 reg_len += sizeof(struct pcie_ctx_hw_stats); 1392 1393 return reg_len; 1394 } 1395 1396 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1397 void *_p) 1398 { 1399 struct pcie_ctx_hw_stats *hw_pcie_stats; 1400 struct hwrm_pcie_qstats_input *req; 1401 struct bnxt *bp = netdev_priv(dev); 1402 dma_addr_t hw_pcie_stats_addr; 1403 int rc; 1404 1405 regs->version = 0; 1406 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1407 1408 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1409 return; 1410 1411 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1412 return; 1413 1414 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1415 &hw_pcie_stats_addr); 1416 if (!hw_pcie_stats) { 1417 hwrm_req_drop(bp, req); 1418 return; 1419 } 1420 1421 regs->version = 1; 1422 hwrm_req_hold(bp, req); /* hold on to slice */ 1423 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1424 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1425 rc = hwrm_req_send(bp, req); 1426 if (!rc) { 1427 __le64 *src = (__le64 *)hw_pcie_stats; 1428 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1429 int i; 1430 1431 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1432 dst[i] = le64_to_cpu(src[i]); 1433 } 1434 hwrm_req_drop(bp, req); 1435 } 1436 1437 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1438 { 1439 struct bnxt *bp = netdev_priv(dev); 1440 1441 wol->supported = 0; 1442 wol->wolopts = 0; 1443 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1444 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1445 wol->supported = WAKE_MAGIC; 1446 if (bp->wol) 1447 wol->wolopts = WAKE_MAGIC; 1448 } 1449 } 1450 1451 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1452 { 1453 struct bnxt *bp = netdev_priv(dev); 1454 1455 if (wol->wolopts & ~WAKE_MAGIC) 1456 return -EINVAL; 1457 1458 if (wol->wolopts & WAKE_MAGIC) { 1459 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1460 return -EINVAL; 1461 if (!bp->wol) { 1462 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1463 return -EBUSY; 1464 bp->wol = 1; 1465 } 1466 } else { 1467 if (bp->wol) { 1468 if (bnxt_hwrm_free_wol_fltr(bp)) 1469 return -EBUSY; 1470 bp->wol = 0; 1471 } 1472 } 1473 return 0; 1474 } 1475 1476 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1477 { 1478 u32 speed_mask = 0; 1479 1480 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1481 /* set the advertised speeds */ 1482 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1483 speed_mask |= ADVERTISED_100baseT_Full; 1484 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1485 speed_mask |= ADVERTISED_1000baseT_Full; 1486 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1487 speed_mask |= ADVERTISED_2500baseX_Full; 1488 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1489 speed_mask |= ADVERTISED_10000baseT_Full; 1490 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1491 speed_mask |= ADVERTISED_40000baseCR4_Full; 1492 1493 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1494 speed_mask |= ADVERTISED_Pause; 1495 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1496 speed_mask |= ADVERTISED_Asym_Pause; 1497 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1498 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1499 1500 return speed_mask; 1501 } 1502 1503 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1504 { \ 1505 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1506 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1507 100baseT_Full); \ 1508 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1509 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1510 1000baseT_Full); \ 1511 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1512 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1513 10000baseT_Full); \ 1514 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1515 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1516 25000baseCR_Full); \ 1517 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1518 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1519 40000baseCR4_Full);\ 1520 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1521 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1522 50000baseCR2_Full);\ 1523 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1524 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1525 100000baseCR4_Full);\ 1526 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1527 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1528 Pause); \ 1529 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1530 ethtool_link_ksettings_add_link_mode( \ 1531 lk_ksettings, name, Asym_Pause);\ 1532 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1533 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1534 Asym_Pause); \ 1535 } \ 1536 } 1537 1538 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1539 { \ 1540 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1541 100baseT_Full) || \ 1542 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1543 100baseT_Half)) \ 1544 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1545 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1546 1000baseT_Full) || \ 1547 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1548 1000baseT_Half)) \ 1549 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1550 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1551 10000baseT_Full)) \ 1552 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1553 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1554 25000baseCR_Full)) \ 1555 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1556 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1557 40000baseCR4_Full)) \ 1558 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1559 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1560 50000baseCR2_Full)) \ 1561 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1562 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1563 100000baseCR4_Full)) \ 1564 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1565 } 1566 1567 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1568 { \ 1569 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \ 1570 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1571 50000baseCR_Full); \ 1572 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \ 1573 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1574 100000baseCR2_Full);\ 1575 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \ 1576 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1577 200000baseCR4_Full);\ 1578 } 1579 1580 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1581 { \ 1582 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1583 50000baseCR_Full)) \ 1584 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \ 1585 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1586 100000baseCR2_Full)) \ 1587 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \ 1588 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1589 200000baseCR4_Full)) \ 1590 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \ 1591 } 1592 1593 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1594 struct ethtool_link_ksettings *lk_ksettings) 1595 { 1596 u16 fec_cfg = link_info->fec_cfg; 1597 1598 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1599 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1600 lk_ksettings->link_modes.advertising); 1601 return; 1602 } 1603 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1604 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1605 lk_ksettings->link_modes.advertising); 1606 if (fec_cfg & BNXT_FEC_ENC_RS) 1607 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1608 lk_ksettings->link_modes.advertising); 1609 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1610 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1611 lk_ksettings->link_modes.advertising); 1612 } 1613 1614 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1615 struct ethtool_link_ksettings *lk_ksettings) 1616 { 1617 u16 fw_speeds = link_info->advertising; 1618 u8 fw_pause = 0; 1619 1620 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1621 fw_pause = link_info->auto_pause_setting; 1622 1623 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1624 fw_speeds = link_info->advertising_pam4; 1625 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising); 1626 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 1627 } 1628 1629 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1630 struct ethtool_link_ksettings *lk_ksettings) 1631 { 1632 u16 fw_speeds = link_info->lp_auto_link_speeds; 1633 u8 fw_pause = 0; 1634 1635 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1636 fw_pause = link_info->lp_pause; 1637 1638 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1639 lp_advertising); 1640 fw_speeds = link_info->lp_auto_pam4_link_speeds; 1641 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising); 1642 } 1643 1644 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1645 struct ethtool_link_ksettings *lk_ksettings) 1646 { 1647 u16 fec_cfg = link_info->fec_cfg; 1648 1649 if (fec_cfg & BNXT_FEC_NONE) { 1650 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1651 lk_ksettings->link_modes.supported); 1652 return; 1653 } 1654 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1655 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1656 lk_ksettings->link_modes.supported); 1657 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1658 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1659 lk_ksettings->link_modes.supported); 1660 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1661 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1662 lk_ksettings->link_modes.supported); 1663 } 1664 1665 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1666 struct ethtool_link_ksettings *lk_ksettings) 1667 { 1668 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 1669 u16 fw_speeds = link_info->support_speeds; 1670 1671 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1672 fw_speeds = link_info->support_pam4_speeds; 1673 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported); 1674 1675 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 1676 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1677 Pause); 1678 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1679 Asym_Pause); 1680 } 1681 1682 if (link_info->support_auto_speeds || 1683 link_info->support_pam4_auto_speeds) 1684 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1685 Autoneg); 1686 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 1687 } 1688 1689 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1690 { 1691 switch (fw_link_speed) { 1692 case BNXT_LINK_SPEED_100MB: 1693 return SPEED_100; 1694 case BNXT_LINK_SPEED_1GB: 1695 return SPEED_1000; 1696 case BNXT_LINK_SPEED_2_5GB: 1697 return SPEED_2500; 1698 case BNXT_LINK_SPEED_10GB: 1699 return SPEED_10000; 1700 case BNXT_LINK_SPEED_20GB: 1701 return SPEED_20000; 1702 case BNXT_LINK_SPEED_25GB: 1703 return SPEED_25000; 1704 case BNXT_LINK_SPEED_40GB: 1705 return SPEED_40000; 1706 case BNXT_LINK_SPEED_50GB: 1707 return SPEED_50000; 1708 case BNXT_LINK_SPEED_100GB: 1709 return SPEED_100000; 1710 case BNXT_LINK_SPEED_200GB: 1711 return SPEED_200000; 1712 default: 1713 return SPEED_UNKNOWN; 1714 } 1715 } 1716 1717 static int bnxt_get_link_ksettings(struct net_device *dev, 1718 struct ethtool_link_ksettings *lk_ksettings) 1719 { 1720 struct bnxt *bp = netdev_priv(dev); 1721 struct bnxt_link_info *link_info = &bp->link_info; 1722 struct ethtool_link_settings *base = &lk_ksettings->base; 1723 u32 ethtool_speed; 1724 1725 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1726 mutex_lock(&bp->link_lock); 1727 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1728 1729 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1730 if (link_info->autoneg) { 1731 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1732 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1733 advertising, Autoneg); 1734 base->autoneg = AUTONEG_ENABLE; 1735 base->duplex = DUPLEX_UNKNOWN; 1736 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1737 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1738 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1739 base->duplex = DUPLEX_FULL; 1740 else 1741 base->duplex = DUPLEX_HALF; 1742 } 1743 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1744 } else { 1745 base->autoneg = AUTONEG_DISABLE; 1746 ethtool_speed = 1747 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1748 base->duplex = DUPLEX_HALF; 1749 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1750 base->duplex = DUPLEX_FULL; 1751 } 1752 base->speed = ethtool_speed; 1753 1754 base->port = PORT_NONE; 1755 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1756 base->port = PORT_TP; 1757 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1758 TP); 1759 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1760 TP); 1761 } else { 1762 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1763 FIBRE); 1764 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1765 FIBRE); 1766 1767 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1768 base->port = PORT_DA; 1769 else if (link_info->media_type == 1770 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1771 base->port = PORT_FIBRE; 1772 } 1773 base->phy_address = link_info->phy_addr; 1774 mutex_unlock(&bp->link_lock); 1775 1776 return 0; 1777 } 1778 1779 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed) 1780 { 1781 struct bnxt *bp = netdev_priv(dev); 1782 struct bnxt_link_info *link_info = &bp->link_info; 1783 u16 support_pam4_spds = link_info->support_pam4_speeds; 1784 u16 support_spds = link_info->support_speeds; 1785 u8 sig_mode = BNXT_SIG_MODE_NRZ; 1786 u16 fw_speed = 0; 1787 1788 switch (ethtool_speed) { 1789 case SPEED_100: 1790 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1791 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 1792 break; 1793 case SPEED_1000: 1794 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1795 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 1796 break; 1797 case SPEED_2500: 1798 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1799 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 1800 break; 1801 case SPEED_10000: 1802 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1803 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 1804 break; 1805 case SPEED_20000: 1806 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1807 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 1808 break; 1809 case SPEED_25000: 1810 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1811 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 1812 break; 1813 case SPEED_40000: 1814 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1815 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 1816 break; 1817 case SPEED_50000: 1818 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) { 1819 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 1820 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 1821 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 1822 sig_mode = BNXT_SIG_MODE_PAM4; 1823 } 1824 break; 1825 case SPEED_100000: 1826 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) { 1827 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 1828 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 1829 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 1830 sig_mode = BNXT_SIG_MODE_PAM4; 1831 } 1832 break; 1833 case SPEED_200000: 1834 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 1835 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 1836 sig_mode = BNXT_SIG_MODE_PAM4; 1837 } 1838 break; 1839 } 1840 1841 if (!fw_speed) { 1842 netdev_err(dev, "unsupported speed!\n"); 1843 return -EINVAL; 1844 } 1845 1846 if (link_info->req_link_speed == fw_speed && 1847 link_info->req_signal_mode == sig_mode && 1848 link_info->autoneg == 0) 1849 return -EALREADY; 1850 1851 link_info->req_link_speed = fw_speed; 1852 link_info->req_signal_mode = sig_mode; 1853 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1854 link_info->autoneg = 0; 1855 link_info->advertising = 0; 1856 link_info->advertising_pam4 = 0; 1857 1858 return 0; 1859 } 1860 1861 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1862 { 1863 u16 fw_speed_mask = 0; 1864 1865 /* only support autoneg at speed 100, 1000, and 10000 */ 1866 if (advertising & (ADVERTISED_100baseT_Full | 1867 ADVERTISED_100baseT_Half)) { 1868 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1869 } 1870 if (advertising & (ADVERTISED_1000baseT_Full | 1871 ADVERTISED_1000baseT_Half)) { 1872 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1873 } 1874 if (advertising & ADVERTISED_10000baseT_Full) 1875 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1876 1877 if (advertising & ADVERTISED_40000baseCR4_Full) 1878 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1879 1880 return fw_speed_mask; 1881 } 1882 1883 static int bnxt_set_link_ksettings(struct net_device *dev, 1884 const struct ethtool_link_ksettings *lk_ksettings) 1885 { 1886 struct bnxt *bp = netdev_priv(dev); 1887 struct bnxt_link_info *link_info = &bp->link_info; 1888 const struct ethtool_link_settings *base = &lk_ksettings->base; 1889 bool set_pause = false; 1890 u32 speed; 1891 int rc = 0; 1892 1893 if (!BNXT_PHY_CFG_ABLE(bp)) 1894 return -EOPNOTSUPP; 1895 1896 mutex_lock(&bp->link_lock); 1897 if (base->autoneg == AUTONEG_ENABLE) { 1898 link_info->advertising = 0; 1899 link_info->advertising_pam4 = 0; 1900 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings, 1901 advertising); 1902 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4, 1903 lk_ksettings, advertising); 1904 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1905 if (!link_info->advertising && !link_info->advertising_pam4) { 1906 link_info->advertising = link_info->support_auto_speeds; 1907 link_info->advertising_pam4 = 1908 link_info->support_pam4_auto_speeds; 1909 } 1910 /* any change to autoneg will cause link change, therefore the 1911 * driver should put back the original pause setting in autoneg 1912 */ 1913 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 1914 set_pause = true; 1915 } else { 1916 u8 phy_type = link_info->phy_type; 1917 1918 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1919 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1920 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1921 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1922 rc = -EINVAL; 1923 goto set_setting_exit; 1924 } 1925 if (base->duplex == DUPLEX_HALF) { 1926 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1927 rc = -EINVAL; 1928 goto set_setting_exit; 1929 } 1930 speed = base->speed; 1931 rc = bnxt_force_link_speed(dev, speed); 1932 if (rc) { 1933 if (rc == -EALREADY) 1934 rc = 0; 1935 goto set_setting_exit; 1936 } 1937 } 1938 1939 if (netif_running(dev)) 1940 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1941 1942 set_setting_exit: 1943 mutex_unlock(&bp->link_lock); 1944 return rc; 1945 } 1946 1947 static int bnxt_get_fecparam(struct net_device *dev, 1948 struct ethtool_fecparam *fec) 1949 { 1950 struct bnxt *bp = netdev_priv(dev); 1951 struct bnxt_link_info *link_info; 1952 u8 active_fec; 1953 u16 fec_cfg; 1954 1955 link_info = &bp->link_info; 1956 fec_cfg = link_info->fec_cfg; 1957 active_fec = link_info->active_fec_sig_mode & 1958 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 1959 if (fec_cfg & BNXT_FEC_NONE) { 1960 fec->fec = ETHTOOL_FEC_NONE; 1961 fec->active_fec = ETHTOOL_FEC_NONE; 1962 return 0; 1963 } 1964 if (fec_cfg & BNXT_FEC_AUTONEG) 1965 fec->fec |= ETHTOOL_FEC_AUTO; 1966 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1967 fec->fec |= ETHTOOL_FEC_BASER; 1968 if (fec_cfg & BNXT_FEC_ENC_RS) 1969 fec->fec |= ETHTOOL_FEC_RS; 1970 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1971 fec->fec |= ETHTOOL_FEC_LLRS; 1972 1973 switch (active_fec) { 1974 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 1975 fec->active_fec |= ETHTOOL_FEC_BASER; 1976 break; 1977 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 1978 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 1979 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 1980 fec->active_fec |= ETHTOOL_FEC_RS; 1981 break; 1982 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 1983 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 1984 fec->active_fec |= ETHTOOL_FEC_LLRS; 1985 break; 1986 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 1987 fec->active_fec |= ETHTOOL_FEC_OFF; 1988 break; 1989 } 1990 return 0; 1991 } 1992 1993 static void bnxt_get_fec_stats(struct net_device *dev, 1994 struct ethtool_fec_stats *fec_stats) 1995 { 1996 struct bnxt *bp = netdev_priv(dev); 1997 u64 *rx; 1998 1999 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 2000 return; 2001 2002 rx = bp->rx_port_stats_ext.sw_stats; 2003 fec_stats->corrected_bits.total = 2004 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 2005 2006 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 2007 return; 2008 2009 fec_stats->corrected_blocks.total = 2010 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 2011 fec_stats->uncorrectable_blocks.total = 2012 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 2013 } 2014 2015 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 2016 u32 fec) 2017 { 2018 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 2019 2020 if (fec & ETHTOOL_FEC_BASER) 2021 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 2022 else if (fec & ETHTOOL_FEC_RS) 2023 fw_fec |= BNXT_FEC_RS_ON(link_info); 2024 else if (fec & ETHTOOL_FEC_LLRS) 2025 fw_fec |= BNXT_FEC_LLRS_ON; 2026 return fw_fec; 2027 } 2028 2029 static int bnxt_set_fecparam(struct net_device *dev, 2030 struct ethtool_fecparam *fecparam) 2031 { 2032 struct hwrm_port_phy_cfg_input *req; 2033 struct bnxt *bp = netdev_priv(dev); 2034 struct bnxt_link_info *link_info; 2035 u32 new_cfg, fec = fecparam->fec; 2036 u16 fec_cfg; 2037 int rc; 2038 2039 link_info = &bp->link_info; 2040 fec_cfg = link_info->fec_cfg; 2041 if (fec_cfg & BNXT_FEC_NONE) 2042 return -EOPNOTSUPP; 2043 2044 if (fec & ETHTOOL_FEC_OFF) { 2045 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 2046 BNXT_FEC_ALL_OFF(link_info); 2047 goto apply_fec; 2048 } 2049 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2050 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2051 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2052 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2053 return -EINVAL; 2054 2055 if (fec & ETHTOOL_FEC_AUTO) { 2056 if (!link_info->autoneg) 2057 return -EINVAL; 2058 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2059 } else { 2060 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2061 } 2062 2063 apply_fec: 2064 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2065 if (rc) 2066 return rc; 2067 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2068 rc = hwrm_req_send(bp, req); 2069 /* update current settings */ 2070 if (!rc) { 2071 mutex_lock(&bp->link_lock); 2072 bnxt_update_link(bp, false); 2073 mutex_unlock(&bp->link_lock); 2074 } 2075 return rc; 2076 } 2077 2078 static void bnxt_get_pauseparam(struct net_device *dev, 2079 struct ethtool_pauseparam *epause) 2080 { 2081 struct bnxt *bp = netdev_priv(dev); 2082 struct bnxt_link_info *link_info = &bp->link_info; 2083 2084 if (BNXT_VF(bp)) 2085 return; 2086 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2087 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2088 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2089 } 2090 2091 static void bnxt_get_pause_stats(struct net_device *dev, 2092 struct ethtool_pause_stats *epstat) 2093 { 2094 struct bnxt *bp = netdev_priv(dev); 2095 u64 *rx, *tx; 2096 2097 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2098 return; 2099 2100 rx = bp->port_stats.sw_stats; 2101 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2102 2103 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2104 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2105 } 2106 2107 static int bnxt_set_pauseparam(struct net_device *dev, 2108 struct ethtool_pauseparam *epause) 2109 { 2110 int rc = 0; 2111 struct bnxt *bp = netdev_priv(dev); 2112 struct bnxt_link_info *link_info = &bp->link_info; 2113 2114 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2115 return -EOPNOTSUPP; 2116 2117 mutex_lock(&bp->link_lock); 2118 if (epause->autoneg) { 2119 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2120 rc = -EINVAL; 2121 goto pause_exit; 2122 } 2123 2124 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2125 link_info->req_flow_ctrl = 0; 2126 } else { 2127 /* when transition from auto pause to force pause, 2128 * force a link change 2129 */ 2130 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2131 link_info->force_link_chng = true; 2132 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2133 link_info->req_flow_ctrl = 0; 2134 } 2135 if (epause->rx_pause) 2136 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2137 2138 if (epause->tx_pause) 2139 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2140 2141 if (netif_running(dev)) 2142 rc = bnxt_hwrm_set_pause(bp); 2143 2144 pause_exit: 2145 mutex_unlock(&bp->link_lock); 2146 return rc; 2147 } 2148 2149 static u32 bnxt_get_link(struct net_device *dev) 2150 { 2151 struct bnxt *bp = netdev_priv(dev); 2152 2153 /* TODO: handle MF, VF, driver close case */ 2154 return BNXT_LINK_IS_UP(bp); 2155 } 2156 2157 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2158 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2159 { 2160 struct hwrm_nvm_get_dev_info_output *resp; 2161 struct hwrm_nvm_get_dev_info_input *req; 2162 int rc; 2163 2164 if (BNXT_VF(bp)) 2165 return -EOPNOTSUPP; 2166 2167 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2168 if (rc) 2169 return rc; 2170 2171 resp = hwrm_req_hold(bp, req); 2172 rc = hwrm_req_send(bp, req); 2173 if (!rc) 2174 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2175 hwrm_req_drop(bp, req); 2176 return rc; 2177 } 2178 2179 static void bnxt_print_admin_err(struct bnxt *bp) 2180 { 2181 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2182 } 2183 2184 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2185 u16 ext, u16 *index, u32 *item_length, 2186 u32 *data_length); 2187 2188 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2189 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2190 u32 dir_item_len, const u8 *data, 2191 size_t data_len) 2192 { 2193 struct bnxt *bp = netdev_priv(dev); 2194 struct hwrm_nvm_write_input *req; 2195 int rc; 2196 2197 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2198 if (rc) 2199 return rc; 2200 2201 if (data_len && data) { 2202 dma_addr_t dma_handle; 2203 u8 *kmem; 2204 2205 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2206 if (!kmem) { 2207 hwrm_req_drop(bp, req); 2208 return -ENOMEM; 2209 } 2210 2211 req->dir_data_length = cpu_to_le32(data_len); 2212 2213 memcpy(kmem, data, data_len); 2214 req->host_src_addr = cpu_to_le64(dma_handle); 2215 } 2216 2217 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 2218 req->dir_type = cpu_to_le16(dir_type); 2219 req->dir_ordinal = cpu_to_le16(dir_ordinal); 2220 req->dir_ext = cpu_to_le16(dir_ext); 2221 req->dir_attr = cpu_to_le16(dir_attr); 2222 req->dir_item_length = cpu_to_le32(dir_item_len); 2223 rc = hwrm_req_send(bp, req); 2224 2225 if (rc == -EACCES) 2226 bnxt_print_admin_err(bp); 2227 return rc; 2228 } 2229 2230 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2231 u8 self_reset, u8 flags) 2232 { 2233 struct bnxt *bp = netdev_priv(dev); 2234 struct hwrm_fw_reset_input *req; 2235 int rc; 2236 2237 if (!bnxt_hwrm_reset_permitted(bp)) { 2238 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 2239 return -EPERM; 2240 } 2241 2242 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 2243 if (rc) 2244 return rc; 2245 2246 req->embedded_proc_type = proc_type; 2247 req->selfrst_status = self_reset; 2248 req->flags = flags; 2249 2250 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2251 rc = hwrm_req_send_silent(bp, req); 2252 } else { 2253 rc = hwrm_req_send(bp, req); 2254 if (rc == -EACCES) 2255 bnxt_print_admin_err(bp); 2256 } 2257 return rc; 2258 } 2259 2260 static int bnxt_firmware_reset(struct net_device *dev, 2261 enum bnxt_nvm_directory_type dir_type) 2262 { 2263 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2264 u8 proc_type, flags = 0; 2265 2266 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2267 /* (e.g. when firmware isn't already running) */ 2268 switch (dir_type) { 2269 case BNX_DIR_TYPE_CHIMP_PATCH: 2270 case BNX_DIR_TYPE_BOOTCODE: 2271 case BNX_DIR_TYPE_BOOTCODE_2: 2272 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2273 /* Self-reset ChiMP upon next PCIe reset: */ 2274 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2275 break; 2276 case BNX_DIR_TYPE_APE_FW: 2277 case BNX_DIR_TYPE_APE_PATCH: 2278 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2279 /* Self-reset APE upon next PCIe reset: */ 2280 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2281 break; 2282 case BNX_DIR_TYPE_KONG_FW: 2283 case BNX_DIR_TYPE_KONG_PATCH: 2284 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2285 break; 2286 case BNX_DIR_TYPE_BONO_FW: 2287 case BNX_DIR_TYPE_BONO_PATCH: 2288 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2289 break; 2290 default: 2291 return -EINVAL; 2292 } 2293 2294 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2295 } 2296 2297 static int bnxt_firmware_reset_chip(struct net_device *dev) 2298 { 2299 struct bnxt *bp = netdev_priv(dev); 2300 u8 flags = 0; 2301 2302 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2303 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2304 2305 return bnxt_hwrm_firmware_reset(dev, 2306 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2307 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2308 flags); 2309 } 2310 2311 static int bnxt_firmware_reset_ap(struct net_device *dev) 2312 { 2313 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2314 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2315 0); 2316 } 2317 2318 static int bnxt_flash_firmware(struct net_device *dev, 2319 u16 dir_type, 2320 const u8 *fw_data, 2321 size_t fw_size) 2322 { 2323 int rc = 0; 2324 u16 code_type; 2325 u32 stored_crc; 2326 u32 calculated_crc; 2327 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2328 2329 switch (dir_type) { 2330 case BNX_DIR_TYPE_BOOTCODE: 2331 case BNX_DIR_TYPE_BOOTCODE_2: 2332 code_type = CODE_BOOT; 2333 break; 2334 case BNX_DIR_TYPE_CHIMP_PATCH: 2335 code_type = CODE_CHIMP_PATCH; 2336 break; 2337 case BNX_DIR_TYPE_APE_FW: 2338 code_type = CODE_MCTP_PASSTHRU; 2339 break; 2340 case BNX_DIR_TYPE_APE_PATCH: 2341 code_type = CODE_APE_PATCH; 2342 break; 2343 case BNX_DIR_TYPE_KONG_FW: 2344 code_type = CODE_KONG_FW; 2345 break; 2346 case BNX_DIR_TYPE_KONG_PATCH: 2347 code_type = CODE_KONG_PATCH; 2348 break; 2349 case BNX_DIR_TYPE_BONO_FW: 2350 code_type = CODE_BONO_FW; 2351 break; 2352 case BNX_DIR_TYPE_BONO_PATCH: 2353 code_type = CODE_BONO_PATCH; 2354 break; 2355 default: 2356 netdev_err(dev, "Unsupported directory entry type: %u\n", 2357 dir_type); 2358 return -EINVAL; 2359 } 2360 if (fw_size < sizeof(struct bnxt_fw_header)) { 2361 netdev_err(dev, "Invalid firmware file size: %u\n", 2362 (unsigned int)fw_size); 2363 return -EINVAL; 2364 } 2365 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2366 netdev_err(dev, "Invalid firmware signature: %08X\n", 2367 le32_to_cpu(header->signature)); 2368 return -EINVAL; 2369 } 2370 if (header->code_type != code_type) { 2371 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2372 code_type, header->code_type); 2373 return -EINVAL; 2374 } 2375 if (header->device != DEVICE_CUMULUS_FAMILY) { 2376 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2377 DEVICE_CUMULUS_FAMILY, header->device); 2378 return -EINVAL; 2379 } 2380 /* Confirm the CRC32 checksum of the file: */ 2381 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2382 sizeof(stored_crc))); 2383 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2384 if (calculated_crc != stored_crc) { 2385 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2386 (unsigned long)stored_crc, 2387 (unsigned long)calculated_crc); 2388 return -EINVAL; 2389 } 2390 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2391 0, 0, 0, fw_data, fw_size); 2392 if (rc == 0) /* Firmware update successful */ 2393 rc = bnxt_firmware_reset(dev, dir_type); 2394 2395 return rc; 2396 } 2397 2398 static int bnxt_flash_microcode(struct net_device *dev, 2399 u16 dir_type, 2400 const u8 *fw_data, 2401 size_t fw_size) 2402 { 2403 struct bnxt_ucode_trailer *trailer; 2404 u32 calculated_crc; 2405 u32 stored_crc; 2406 int rc = 0; 2407 2408 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2409 netdev_err(dev, "Invalid microcode file size: %u\n", 2410 (unsigned int)fw_size); 2411 return -EINVAL; 2412 } 2413 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2414 sizeof(*trailer))); 2415 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2416 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2417 le32_to_cpu(trailer->sig)); 2418 return -EINVAL; 2419 } 2420 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2421 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2422 dir_type, le16_to_cpu(trailer->dir_type)); 2423 return -EINVAL; 2424 } 2425 if (le16_to_cpu(trailer->trailer_length) < 2426 sizeof(struct bnxt_ucode_trailer)) { 2427 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2428 le16_to_cpu(trailer->trailer_length)); 2429 return -EINVAL; 2430 } 2431 2432 /* Confirm the CRC32 checksum of the file: */ 2433 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2434 sizeof(stored_crc))); 2435 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2436 if (calculated_crc != stored_crc) { 2437 netdev_err(dev, 2438 "CRC32 (%08lX) does not match calculated: %08lX\n", 2439 (unsigned long)stored_crc, 2440 (unsigned long)calculated_crc); 2441 return -EINVAL; 2442 } 2443 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2444 0, 0, 0, fw_data, fw_size); 2445 2446 return rc; 2447 } 2448 2449 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2450 { 2451 switch (dir_type) { 2452 case BNX_DIR_TYPE_CHIMP_PATCH: 2453 case BNX_DIR_TYPE_BOOTCODE: 2454 case BNX_DIR_TYPE_BOOTCODE_2: 2455 case BNX_DIR_TYPE_APE_FW: 2456 case BNX_DIR_TYPE_APE_PATCH: 2457 case BNX_DIR_TYPE_KONG_FW: 2458 case BNX_DIR_TYPE_KONG_PATCH: 2459 case BNX_DIR_TYPE_BONO_FW: 2460 case BNX_DIR_TYPE_BONO_PATCH: 2461 return true; 2462 } 2463 2464 return false; 2465 } 2466 2467 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2468 { 2469 switch (dir_type) { 2470 case BNX_DIR_TYPE_AVS: 2471 case BNX_DIR_TYPE_EXP_ROM_MBA: 2472 case BNX_DIR_TYPE_PCIE: 2473 case BNX_DIR_TYPE_TSCF_UCODE: 2474 case BNX_DIR_TYPE_EXT_PHY: 2475 case BNX_DIR_TYPE_CCM: 2476 case BNX_DIR_TYPE_ISCSI_BOOT: 2477 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2478 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2479 return true; 2480 } 2481 2482 return false; 2483 } 2484 2485 static bool bnxt_dir_type_is_executable(u16 dir_type) 2486 { 2487 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2488 bnxt_dir_type_is_other_exec_format(dir_type); 2489 } 2490 2491 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2492 u16 dir_type, 2493 const char *filename) 2494 { 2495 const struct firmware *fw; 2496 int rc; 2497 2498 rc = request_firmware(&fw, filename, &dev->dev); 2499 if (rc != 0) { 2500 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2501 rc, filename); 2502 return rc; 2503 } 2504 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2505 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2506 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2507 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2508 else 2509 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2510 0, 0, 0, fw->data, fw->size); 2511 release_firmware(fw); 2512 return rc; 2513 } 2514 2515 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 2516 #define MSG_INVALID_PKG "PKG install error : Invalid package" 2517 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 2518 #define MSG_INVALID_DEV "PKG install error : Invalid device" 2519 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 2520 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 2521 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 2522 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 2523 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 2524 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 2525 2526 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 2527 struct netlink_ext_ack *extack) 2528 { 2529 switch (result) { 2530 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 2531 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 2532 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 2533 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 2534 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 2535 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 2536 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 2537 return -EINVAL; 2538 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 2539 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 2540 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 2541 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 2542 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 2543 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 2544 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 2545 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 2546 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 2547 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 2548 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 2549 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 2550 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 2551 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 2552 return -ENOPKG; 2553 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 2554 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 2555 return -EPERM; 2556 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 2557 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 2558 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 2559 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 2560 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 2561 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 2562 return -EOPNOTSUPP; 2563 default: 2564 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 2565 return -EIO; 2566 } 2567 } 2568 2569 #define BNXT_PKG_DMA_SIZE 0x40000 2570 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2571 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2572 2573 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 2574 struct netlink_ext_ack *extack) 2575 { 2576 u32 item_len; 2577 int rc; 2578 2579 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2580 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 2581 &item_len, NULL); 2582 if (rc) { 2583 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 2584 return rc; 2585 } 2586 2587 if (fw_size > item_len) { 2588 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 2589 BNX_DIR_ORDINAL_FIRST, 0, 1, 2590 round_up(fw_size, 4096), NULL, 0); 2591 if (rc) { 2592 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 2593 return rc; 2594 } 2595 } 2596 return 0; 2597 } 2598 2599 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2600 u32 install_type, struct netlink_ext_ack *extack) 2601 { 2602 struct hwrm_nvm_install_update_input *install; 2603 struct hwrm_nvm_install_update_output *resp; 2604 struct hwrm_nvm_modify_input *modify; 2605 struct bnxt *bp = netdev_priv(dev); 2606 bool defrag_attempted = false; 2607 dma_addr_t dma_handle; 2608 u8 *kmem = NULL; 2609 u32 modify_len; 2610 u32 item_len; 2611 u8 cmd_err; 2612 u16 index; 2613 int rc; 2614 2615 /* resize before flashing larger image than available space */ 2616 rc = bnxt_resize_update_entry(dev, fw->size, extack); 2617 if (rc) 2618 return rc; 2619 2620 bnxt_hwrm_fw_set_time(bp); 2621 2622 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 2623 if (rc) 2624 return rc; 2625 2626 /* Try allocating a large DMA buffer first. Older fw will 2627 * cause excessive NVRAM erases when using small blocks. 2628 */ 2629 modify_len = roundup_pow_of_two(fw->size); 2630 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 2631 while (1) { 2632 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 2633 if (!kmem && modify_len > PAGE_SIZE) 2634 modify_len /= 2; 2635 else 2636 break; 2637 } 2638 if (!kmem) { 2639 hwrm_req_drop(bp, modify); 2640 return -ENOMEM; 2641 } 2642 2643 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 2644 if (rc) { 2645 hwrm_req_drop(bp, modify); 2646 return rc; 2647 } 2648 2649 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 2650 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 2651 2652 hwrm_req_hold(bp, modify); 2653 modify->host_src_addr = cpu_to_le64(dma_handle); 2654 2655 resp = hwrm_req_hold(bp, install); 2656 if ((install_type & 0xffff) == 0) 2657 install_type >>= 16; 2658 install->install_type = cpu_to_le32(install_type); 2659 2660 do { 2661 u32 copied = 0, len = modify_len; 2662 2663 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2664 BNX_DIR_ORDINAL_FIRST, 2665 BNX_DIR_EXT_NONE, 2666 &index, &item_len, NULL); 2667 if (rc) { 2668 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 2669 break; 2670 } 2671 if (fw->size > item_len) { 2672 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 2673 rc = -EFBIG; 2674 break; 2675 } 2676 2677 modify->dir_idx = cpu_to_le16(index); 2678 2679 if (fw->size > modify_len) 2680 modify->flags = BNXT_NVM_MORE_FLAG; 2681 while (copied < fw->size) { 2682 u32 balance = fw->size - copied; 2683 2684 if (balance <= modify_len) { 2685 len = balance; 2686 if (copied) 2687 modify->flags |= BNXT_NVM_LAST_FLAG; 2688 } 2689 memcpy(kmem, fw->data + copied, len); 2690 modify->len = cpu_to_le32(len); 2691 modify->offset = cpu_to_le32(copied); 2692 rc = hwrm_req_send(bp, modify); 2693 if (rc) 2694 goto pkg_abort; 2695 copied += len; 2696 } 2697 2698 rc = hwrm_req_send_silent(bp, install); 2699 if (!rc) 2700 break; 2701 2702 if (defrag_attempted) { 2703 /* We have tried to defragment already in the previous 2704 * iteration. Return with the result for INSTALL_UPDATE 2705 */ 2706 break; 2707 } 2708 2709 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 2710 2711 switch (cmd_err) { 2712 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 2713 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 2714 rc = -EALREADY; 2715 break; 2716 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 2717 install->flags = 2718 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2719 2720 rc = hwrm_req_send_silent(bp, install); 2721 if (!rc) 2722 break; 2723 2724 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 2725 2726 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 2727 /* FW has cleared NVM area, driver will create 2728 * UPDATE directory and try the flash again 2729 */ 2730 defrag_attempted = true; 2731 install->flags = 0; 2732 rc = bnxt_flash_nvram(bp->dev, 2733 BNX_DIR_TYPE_UPDATE, 2734 BNX_DIR_ORDINAL_FIRST, 2735 0, 0, item_len, NULL, 0); 2736 if (!rc) 2737 break; 2738 } 2739 fallthrough; 2740 default: 2741 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 2742 } 2743 } while (defrag_attempted && !rc); 2744 2745 pkg_abort: 2746 hwrm_req_drop(bp, modify); 2747 hwrm_req_drop(bp, install); 2748 2749 if (resp->result) { 2750 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2751 (s8)resp->result, (int)resp->problem_item); 2752 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 2753 } 2754 if (rc == -EACCES) 2755 bnxt_print_admin_err(bp); 2756 return rc; 2757 } 2758 2759 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2760 u32 install_type, struct netlink_ext_ack *extack) 2761 { 2762 const struct firmware *fw; 2763 int rc; 2764 2765 rc = request_firmware(&fw, filename, &dev->dev); 2766 if (rc != 0) { 2767 netdev_err(dev, "PKG error %d requesting file: %s\n", 2768 rc, filename); 2769 return rc; 2770 } 2771 2772 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 2773 2774 release_firmware(fw); 2775 2776 return rc; 2777 } 2778 2779 static int bnxt_flash_device(struct net_device *dev, 2780 struct ethtool_flash *flash) 2781 { 2782 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2783 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2784 return -EINVAL; 2785 } 2786 2787 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2788 flash->region > 0xffff) 2789 return bnxt_flash_package_from_file(dev, flash->data, 2790 flash->region, NULL); 2791 2792 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2793 } 2794 2795 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2796 { 2797 struct hwrm_nvm_get_dir_info_output *output; 2798 struct hwrm_nvm_get_dir_info_input *req; 2799 struct bnxt *bp = netdev_priv(dev); 2800 int rc; 2801 2802 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 2803 if (rc) 2804 return rc; 2805 2806 output = hwrm_req_hold(bp, req); 2807 rc = hwrm_req_send(bp, req); 2808 if (!rc) { 2809 *entries = le32_to_cpu(output->entries); 2810 *length = le32_to_cpu(output->entry_length); 2811 } 2812 hwrm_req_drop(bp, req); 2813 return rc; 2814 } 2815 2816 static int bnxt_get_eeprom_len(struct net_device *dev) 2817 { 2818 struct bnxt *bp = netdev_priv(dev); 2819 2820 if (BNXT_VF(bp)) 2821 return 0; 2822 2823 /* The -1 return value allows the entire 32-bit range of offsets to be 2824 * passed via the ethtool command-line utility. 2825 */ 2826 return -1; 2827 } 2828 2829 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2830 { 2831 struct bnxt *bp = netdev_priv(dev); 2832 int rc; 2833 u32 dir_entries; 2834 u32 entry_length; 2835 u8 *buf; 2836 size_t buflen; 2837 dma_addr_t dma_handle; 2838 struct hwrm_nvm_get_dir_entries_input *req; 2839 2840 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2841 if (rc != 0) 2842 return rc; 2843 2844 if (!dir_entries || !entry_length) 2845 return -EIO; 2846 2847 /* Insert 2 bytes of directory info (count and size of entries) */ 2848 if (len < 2) 2849 return -EINVAL; 2850 2851 *data++ = dir_entries; 2852 *data++ = entry_length; 2853 len -= 2; 2854 memset(data, 0xff, len); 2855 2856 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 2857 if (rc) 2858 return rc; 2859 2860 buflen = mul_u32_u32(dir_entries, entry_length); 2861 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 2862 if (!buf) { 2863 hwrm_req_drop(bp, req); 2864 return -ENOMEM; 2865 } 2866 req->host_dest_addr = cpu_to_le64(dma_handle); 2867 2868 hwrm_req_hold(bp, req); /* hold the slice */ 2869 rc = hwrm_req_send(bp, req); 2870 if (rc == 0) 2871 memcpy(data, buf, len > buflen ? buflen : len); 2872 hwrm_req_drop(bp, req); 2873 return rc; 2874 } 2875 2876 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2877 u32 length, u8 *data) 2878 { 2879 struct bnxt *bp = netdev_priv(dev); 2880 int rc; 2881 u8 *buf; 2882 dma_addr_t dma_handle; 2883 struct hwrm_nvm_read_input *req; 2884 2885 if (!length) 2886 return -EINVAL; 2887 2888 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 2889 if (rc) 2890 return rc; 2891 2892 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 2893 if (!buf) { 2894 hwrm_req_drop(bp, req); 2895 return -ENOMEM; 2896 } 2897 2898 req->host_dest_addr = cpu_to_le64(dma_handle); 2899 req->dir_idx = cpu_to_le16(index); 2900 req->offset = cpu_to_le32(offset); 2901 req->len = cpu_to_le32(length); 2902 2903 hwrm_req_hold(bp, req); /* hold the slice */ 2904 rc = hwrm_req_send(bp, req); 2905 if (rc == 0) 2906 memcpy(data, buf, length); 2907 hwrm_req_drop(bp, req); 2908 return rc; 2909 } 2910 2911 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2912 u16 ext, u16 *index, u32 *item_length, 2913 u32 *data_length) 2914 { 2915 struct hwrm_nvm_find_dir_entry_output *output; 2916 struct hwrm_nvm_find_dir_entry_input *req; 2917 struct bnxt *bp = netdev_priv(dev); 2918 int rc; 2919 2920 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 2921 if (rc) 2922 return rc; 2923 2924 req->enables = 0; 2925 req->dir_idx = 0; 2926 req->dir_type = cpu_to_le16(type); 2927 req->dir_ordinal = cpu_to_le16(ordinal); 2928 req->dir_ext = cpu_to_le16(ext); 2929 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2930 output = hwrm_req_hold(bp, req); 2931 rc = hwrm_req_send_silent(bp, req); 2932 if (rc == 0) { 2933 if (index) 2934 *index = le16_to_cpu(output->dir_idx); 2935 if (item_length) 2936 *item_length = le32_to_cpu(output->dir_item_length); 2937 if (data_length) 2938 *data_length = le32_to_cpu(output->dir_data_length); 2939 } 2940 hwrm_req_drop(bp, req); 2941 return rc; 2942 } 2943 2944 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2945 { 2946 char *retval = NULL; 2947 char *p; 2948 char *value; 2949 int field = 0; 2950 2951 if (datalen < 1) 2952 return NULL; 2953 /* null-terminate the log data (removing last '\n'): */ 2954 data[datalen - 1] = 0; 2955 for (p = data; *p != 0; p++) { 2956 field = 0; 2957 retval = NULL; 2958 while (*p != 0 && *p != '\n') { 2959 value = p; 2960 while (*p != 0 && *p != '\t' && *p != '\n') 2961 p++; 2962 if (field == desired_field) 2963 retval = value; 2964 if (*p != '\t') 2965 break; 2966 *p = 0; 2967 field++; 2968 p++; 2969 } 2970 if (*p == 0) 2971 break; 2972 *p = 0; 2973 } 2974 return retval; 2975 } 2976 2977 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 2978 { 2979 struct bnxt *bp = netdev_priv(dev); 2980 u16 index = 0; 2981 char *pkgver; 2982 u32 pkglen; 2983 u8 *pkgbuf; 2984 int rc; 2985 2986 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2987 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2988 &index, NULL, &pkglen); 2989 if (rc) 2990 return rc; 2991 2992 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2993 if (!pkgbuf) { 2994 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2995 pkglen); 2996 return -ENOMEM; 2997 } 2998 2999 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 3000 if (rc) 3001 goto err; 3002 3003 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 3004 pkglen); 3005 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 3006 strscpy(ver, pkgver, size); 3007 else 3008 rc = -ENOENT; 3009 3010 err: 3011 kfree(pkgbuf); 3012 3013 return rc; 3014 } 3015 3016 static void bnxt_get_pkgver(struct net_device *dev) 3017 { 3018 struct bnxt *bp = netdev_priv(dev); 3019 char buf[FW_VER_STR_LEN]; 3020 int len; 3021 3022 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 3023 len = strlen(bp->fw_ver_str); 3024 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len, 3025 "/pkg %s", buf); 3026 } 3027 } 3028 3029 static int bnxt_get_eeprom(struct net_device *dev, 3030 struct ethtool_eeprom *eeprom, 3031 u8 *data) 3032 { 3033 u32 index; 3034 u32 offset; 3035 3036 if (eeprom->offset == 0) /* special offset value to get directory */ 3037 return bnxt_get_nvram_directory(dev, eeprom->len, data); 3038 3039 index = eeprom->offset >> 24; 3040 offset = eeprom->offset & 0xffffff; 3041 3042 if (index == 0) { 3043 netdev_err(dev, "unsupported index value: %d\n", index); 3044 return -EINVAL; 3045 } 3046 3047 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 3048 } 3049 3050 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 3051 { 3052 struct hwrm_nvm_erase_dir_entry_input *req; 3053 struct bnxt *bp = netdev_priv(dev); 3054 int rc; 3055 3056 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 3057 if (rc) 3058 return rc; 3059 3060 req->dir_idx = cpu_to_le16(index); 3061 return hwrm_req_send(bp, req); 3062 } 3063 3064 static int bnxt_set_eeprom(struct net_device *dev, 3065 struct ethtool_eeprom *eeprom, 3066 u8 *data) 3067 { 3068 struct bnxt *bp = netdev_priv(dev); 3069 u8 index, dir_op; 3070 u16 type, ext, ordinal, attr; 3071 3072 if (!BNXT_PF(bp)) { 3073 netdev_err(dev, "NVM write not supported from a virtual function\n"); 3074 return -EINVAL; 3075 } 3076 3077 type = eeprom->magic >> 16; 3078 3079 if (type == 0xffff) { /* special value for directory operations */ 3080 index = eeprom->magic & 0xff; 3081 dir_op = eeprom->magic >> 8; 3082 if (index == 0) 3083 return -EINVAL; 3084 switch (dir_op) { 3085 case 0x0e: /* erase */ 3086 if (eeprom->offset != ~eeprom->magic) 3087 return -EINVAL; 3088 return bnxt_erase_nvram_directory(dev, index - 1); 3089 default: 3090 return -EINVAL; 3091 } 3092 } 3093 3094 /* Create or re-write an NVM item: */ 3095 if (bnxt_dir_type_is_executable(type)) 3096 return -EOPNOTSUPP; 3097 ext = eeprom->magic & 0xffff; 3098 ordinal = eeprom->offset >> 16; 3099 attr = eeprom->offset & 0xffff; 3100 3101 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 3102 eeprom->len); 3103 } 3104 3105 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 3106 { 3107 struct bnxt *bp = netdev_priv(dev); 3108 struct ethtool_eee *eee = &bp->eee; 3109 struct bnxt_link_info *link_info = &bp->link_info; 3110 u32 advertising; 3111 int rc = 0; 3112 3113 if (!BNXT_PHY_CFG_ABLE(bp)) 3114 return -EOPNOTSUPP; 3115 3116 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3117 return -EOPNOTSUPP; 3118 3119 mutex_lock(&bp->link_lock); 3120 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 3121 if (!edata->eee_enabled) 3122 goto eee_ok; 3123 3124 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3125 netdev_warn(dev, "EEE requires autoneg\n"); 3126 rc = -EINVAL; 3127 goto eee_exit; 3128 } 3129 if (edata->tx_lpi_enabled) { 3130 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 3131 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 3132 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 3133 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 3134 rc = -EINVAL; 3135 goto eee_exit; 3136 } else if (!bp->lpi_tmr_hi) { 3137 edata->tx_lpi_timer = eee->tx_lpi_timer; 3138 } 3139 } 3140 if (!edata->advertised) { 3141 edata->advertised = advertising & eee->supported; 3142 } else if (edata->advertised & ~advertising) { 3143 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3144 edata->advertised, advertising); 3145 rc = -EINVAL; 3146 goto eee_exit; 3147 } 3148 3149 eee->advertised = edata->advertised; 3150 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3151 eee->tx_lpi_timer = edata->tx_lpi_timer; 3152 eee_ok: 3153 eee->eee_enabled = edata->eee_enabled; 3154 3155 if (netif_running(dev)) 3156 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3157 3158 eee_exit: 3159 mutex_unlock(&bp->link_lock); 3160 return rc; 3161 } 3162 3163 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3164 { 3165 struct bnxt *bp = netdev_priv(dev); 3166 3167 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3168 return -EOPNOTSUPP; 3169 3170 *edata = bp->eee; 3171 if (!bp->eee.eee_enabled) { 3172 /* Preserve tx_lpi_timer so that the last value will be used 3173 * by default when it is re-enabled. 3174 */ 3175 edata->advertised = 0; 3176 edata->tx_lpi_enabled = 0; 3177 } 3178 3179 if (!bp->eee.eee_active) 3180 edata->lp_advertised = 0; 3181 3182 return 0; 3183 } 3184 3185 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3186 u16 page_number, u8 bank, 3187 u16 start_addr, u16 data_length, 3188 u8 *buf) 3189 { 3190 struct hwrm_port_phy_i2c_read_output *output; 3191 struct hwrm_port_phy_i2c_read_input *req; 3192 int rc, byte_offset = 0; 3193 3194 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3195 if (rc) 3196 return rc; 3197 3198 output = hwrm_req_hold(bp, req); 3199 req->i2c_slave_addr = i2c_addr; 3200 req->page_number = cpu_to_le16(page_number); 3201 req->port_id = cpu_to_le16(bp->pf.port_id); 3202 do { 3203 u16 xfer_size; 3204 3205 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3206 data_length -= xfer_size; 3207 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3208 req->data_length = xfer_size; 3209 req->enables = 3210 cpu_to_le32((start_addr + byte_offset ? 3211 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 3212 0) | 3213 (bank ? 3214 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 3215 0)); 3216 rc = hwrm_req_send(bp, req); 3217 if (!rc) 3218 memcpy(buf + byte_offset, output->data, xfer_size); 3219 byte_offset += xfer_size; 3220 } while (!rc && data_length > 0); 3221 hwrm_req_drop(bp, req); 3222 3223 return rc; 3224 } 3225 3226 static int bnxt_get_module_info(struct net_device *dev, 3227 struct ethtool_modinfo *modinfo) 3228 { 3229 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 3230 struct bnxt *bp = netdev_priv(dev); 3231 int rc; 3232 3233 /* No point in going further if phy status indicates 3234 * module is not inserted or if it is powered down or 3235 * if it is of type 10GBase-T 3236 */ 3237 if (bp->link_info.module_status > 3238 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3239 return -EOPNOTSUPP; 3240 3241 /* This feature is not supported in older firmware versions */ 3242 if (bp->hwrm_spec_code < 0x10202) 3243 return -EOPNOTSUPP; 3244 3245 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 3246 SFF_DIAG_SUPPORT_OFFSET + 1, 3247 data); 3248 if (!rc) { 3249 u8 module_id = data[0]; 3250 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 3251 3252 switch (module_id) { 3253 case SFF_MODULE_ID_SFP: 3254 modinfo->type = ETH_MODULE_SFF_8472; 3255 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3256 if (!diag_supported) 3257 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3258 break; 3259 case SFF_MODULE_ID_QSFP: 3260 case SFF_MODULE_ID_QSFP_PLUS: 3261 modinfo->type = ETH_MODULE_SFF_8436; 3262 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3263 break; 3264 case SFF_MODULE_ID_QSFP28: 3265 modinfo->type = ETH_MODULE_SFF_8636; 3266 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 3267 break; 3268 default: 3269 rc = -EOPNOTSUPP; 3270 break; 3271 } 3272 } 3273 return rc; 3274 } 3275 3276 static int bnxt_get_module_eeprom(struct net_device *dev, 3277 struct ethtool_eeprom *eeprom, 3278 u8 *data) 3279 { 3280 struct bnxt *bp = netdev_priv(dev); 3281 u16 start = eeprom->offset, length = eeprom->len; 3282 int rc = 0; 3283 3284 memset(data, 0, eeprom->len); 3285 3286 /* Read A0 portion of the EEPROM */ 3287 if (start < ETH_MODULE_SFF_8436_LEN) { 3288 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3289 length = ETH_MODULE_SFF_8436_LEN - start; 3290 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3291 start, length, data); 3292 if (rc) 3293 return rc; 3294 start += length; 3295 data += length; 3296 length = eeprom->len - length; 3297 } 3298 3299 /* Read A2 portion of the EEPROM */ 3300 if (length) { 3301 start -= ETH_MODULE_SFF_8436_LEN; 3302 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 3303 start, length, data); 3304 } 3305 return rc; 3306 } 3307 3308 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 3309 { 3310 if (bp->link_info.module_status <= 3311 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3312 return 0; 3313 3314 switch (bp->link_info.module_status) { 3315 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 3316 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 3317 break; 3318 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 3319 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 3320 break; 3321 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 3322 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 3323 break; 3324 default: 3325 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 3326 break; 3327 } 3328 return -EINVAL; 3329 } 3330 3331 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 3332 const struct ethtool_module_eeprom *page_data, 3333 struct netlink_ext_ack *extack) 3334 { 3335 struct bnxt *bp = netdev_priv(dev); 3336 int rc; 3337 3338 rc = bnxt_get_module_status(bp, extack); 3339 if (rc) 3340 return rc; 3341 3342 if (bp->hwrm_spec_code < 0x10202) { 3343 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 3344 return -EINVAL; 3345 } 3346 3347 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 3348 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 3349 return -EINVAL; 3350 } 3351 3352 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 3353 page_data->page, page_data->bank, 3354 page_data->offset, 3355 page_data->length, 3356 page_data->data); 3357 if (rc) { 3358 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 3359 return rc; 3360 } 3361 return page_data->length; 3362 } 3363 3364 static int bnxt_nway_reset(struct net_device *dev) 3365 { 3366 int rc = 0; 3367 3368 struct bnxt *bp = netdev_priv(dev); 3369 struct bnxt_link_info *link_info = &bp->link_info; 3370 3371 if (!BNXT_PHY_CFG_ABLE(bp)) 3372 return -EOPNOTSUPP; 3373 3374 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3375 return -EINVAL; 3376 3377 if (netif_running(dev)) 3378 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3379 3380 return rc; 3381 } 3382 3383 static int bnxt_set_phys_id(struct net_device *dev, 3384 enum ethtool_phys_id_state state) 3385 { 3386 struct hwrm_port_led_cfg_input *req; 3387 struct bnxt *bp = netdev_priv(dev); 3388 struct bnxt_pf_info *pf = &bp->pf; 3389 struct bnxt_led_cfg *led_cfg; 3390 u8 led_state; 3391 __le16 duration; 3392 int rc, i; 3393 3394 if (!bp->num_leds || BNXT_VF(bp)) 3395 return -EOPNOTSUPP; 3396 3397 if (state == ETHTOOL_ID_ACTIVE) { 3398 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3399 duration = cpu_to_le16(500); 3400 } else if (state == ETHTOOL_ID_INACTIVE) { 3401 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3402 duration = cpu_to_le16(0); 3403 } else { 3404 return -EINVAL; 3405 } 3406 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 3407 if (rc) 3408 return rc; 3409 3410 req->port_id = cpu_to_le16(pf->port_id); 3411 req->num_leds = bp->num_leds; 3412 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 3413 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3414 req->enables |= BNXT_LED_DFLT_ENABLES(i); 3415 led_cfg->led_id = bp->leds[i].led_id; 3416 led_cfg->led_state = led_state; 3417 led_cfg->led_blink_on = duration; 3418 led_cfg->led_blink_off = duration; 3419 led_cfg->led_group_id = bp->leds[i].led_group_id; 3420 } 3421 return hwrm_req_send(bp, req); 3422 } 3423 3424 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3425 { 3426 struct hwrm_selftest_irq_input *req; 3427 int rc; 3428 3429 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 3430 if (rc) 3431 return rc; 3432 3433 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3434 return hwrm_req_send(bp, req); 3435 } 3436 3437 static int bnxt_test_irq(struct bnxt *bp) 3438 { 3439 int i; 3440 3441 for (i = 0; i < bp->cp_nr_rings; i++) { 3442 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3443 int rc; 3444 3445 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3446 if (rc) 3447 return rc; 3448 } 3449 return 0; 3450 } 3451 3452 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3453 { 3454 struct hwrm_port_mac_cfg_input *req; 3455 int rc; 3456 3457 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 3458 if (rc) 3459 return rc; 3460 3461 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3462 if (enable) 3463 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3464 else 3465 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3466 return hwrm_req_send(bp, req); 3467 } 3468 3469 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3470 { 3471 struct hwrm_port_phy_qcaps_output *resp; 3472 struct hwrm_port_phy_qcaps_input *req; 3473 int rc; 3474 3475 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 3476 if (rc) 3477 return rc; 3478 3479 resp = hwrm_req_hold(bp, req); 3480 rc = hwrm_req_send(bp, req); 3481 if (!rc) 3482 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3483 3484 hwrm_req_drop(bp, req); 3485 return rc; 3486 } 3487 3488 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3489 struct hwrm_port_phy_cfg_input *req) 3490 { 3491 struct bnxt_link_info *link_info = &bp->link_info; 3492 u16 fw_advertising; 3493 u16 fw_speed; 3494 int rc; 3495 3496 if (!link_info->autoneg || 3497 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 3498 return 0; 3499 3500 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3501 if (rc) 3502 return rc; 3503 3504 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3505 if (BNXT_LINK_IS_UP(bp)) 3506 fw_speed = bp->link_info.link_speed; 3507 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3508 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3509 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3510 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3511 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3512 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3513 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3514 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3515 3516 req->force_link_speed = cpu_to_le16(fw_speed); 3517 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3518 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3519 rc = hwrm_req_send(bp, req); 3520 req->flags = 0; 3521 req->force_link_speed = cpu_to_le16(0); 3522 return rc; 3523 } 3524 3525 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3526 { 3527 struct hwrm_port_phy_cfg_input *req; 3528 int rc; 3529 3530 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3531 if (rc) 3532 return rc; 3533 3534 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 3535 hwrm_req_hold(bp, req); 3536 3537 if (enable) { 3538 bnxt_disable_an_for_lpbk(bp, req); 3539 if (ext) 3540 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3541 else 3542 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3543 } else { 3544 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3545 } 3546 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3547 rc = hwrm_req_send(bp, req); 3548 hwrm_req_drop(bp, req); 3549 return rc; 3550 } 3551 3552 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3553 u32 raw_cons, int pkt_size) 3554 { 3555 struct bnxt_napi *bnapi = cpr->bnapi; 3556 struct bnxt_rx_ring_info *rxr; 3557 struct bnxt_sw_rx_bd *rx_buf; 3558 struct rx_cmp *rxcmp; 3559 u16 cp_cons, cons; 3560 u8 *data; 3561 u32 len; 3562 int i; 3563 3564 rxr = bnapi->rx_ring; 3565 cp_cons = RING_CMP(raw_cons); 3566 rxcmp = (struct rx_cmp *) 3567 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3568 cons = rxcmp->rx_cmp_opaque; 3569 rx_buf = &rxr->rx_buf_ring[cons]; 3570 data = rx_buf->data_ptr; 3571 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3572 if (len != pkt_size) 3573 return -EIO; 3574 i = ETH_ALEN; 3575 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3576 return -EIO; 3577 i += ETH_ALEN; 3578 for ( ; i < pkt_size; i++) { 3579 if (data[i] != (u8)(i & 0xff)) 3580 return -EIO; 3581 } 3582 return 0; 3583 } 3584 3585 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3586 int pkt_size) 3587 { 3588 struct tx_cmp *txcmp; 3589 int rc = -EIO; 3590 u32 raw_cons; 3591 u32 cons; 3592 int i; 3593 3594 raw_cons = cpr->cp_raw_cons; 3595 for (i = 0; i < 200; i++) { 3596 cons = RING_CMP(raw_cons); 3597 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3598 3599 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3600 udelay(5); 3601 continue; 3602 } 3603 3604 /* The valid test of the entry must be done first before 3605 * reading any further. 3606 */ 3607 dma_rmb(); 3608 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3609 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3610 raw_cons = NEXT_RAW_CMP(raw_cons); 3611 raw_cons = NEXT_RAW_CMP(raw_cons); 3612 break; 3613 } 3614 raw_cons = NEXT_RAW_CMP(raw_cons); 3615 } 3616 cpr->cp_raw_cons = raw_cons; 3617 return rc; 3618 } 3619 3620 static int bnxt_run_loopback(struct bnxt *bp) 3621 { 3622 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3623 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3624 struct bnxt_cp_ring_info *cpr; 3625 int pkt_size, i = 0; 3626 struct sk_buff *skb; 3627 dma_addr_t map; 3628 u8 *data; 3629 int rc; 3630 3631 cpr = &rxr->bnapi->cp_ring; 3632 if (bp->flags & BNXT_FLAG_CHIP_P5) 3633 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3634 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3635 skb = netdev_alloc_skb(bp->dev, pkt_size); 3636 if (!skb) 3637 return -ENOMEM; 3638 data = skb_put(skb, pkt_size); 3639 ether_addr_copy(&data[i], bp->dev->dev_addr); 3640 i += ETH_ALEN; 3641 ether_addr_copy(&data[i], bp->dev->dev_addr); 3642 i += ETH_ALEN; 3643 for ( ; i < pkt_size; i++) 3644 data[i] = (u8)(i & 0xff); 3645 3646 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3647 DMA_TO_DEVICE); 3648 if (dma_mapping_error(&bp->pdev->dev, map)) { 3649 dev_kfree_skb(skb); 3650 return -EIO; 3651 } 3652 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 3653 3654 /* Sync BD data before updating doorbell */ 3655 wmb(); 3656 3657 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3658 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3659 3660 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 3661 dev_kfree_skb(skb); 3662 return rc; 3663 } 3664 3665 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3666 { 3667 struct hwrm_selftest_exec_output *resp; 3668 struct hwrm_selftest_exec_input *req; 3669 int rc; 3670 3671 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 3672 if (rc) 3673 return rc; 3674 3675 hwrm_req_timeout(bp, req, bp->test_info->timeout); 3676 req->flags = test_mask; 3677 3678 resp = hwrm_req_hold(bp, req); 3679 rc = hwrm_req_send(bp, req); 3680 *test_results = resp->test_success; 3681 hwrm_req_drop(bp, req); 3682 return rc; 3683 } 3684 3685 #define BNXT_DRV_TESTS 4 3686 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3687 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3688 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3689 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3690 3691 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3692 u64 *buf) 3693 { 3694 struct bnxt *bp = netdev_priv(dev); 3695 bool do_ext_lpbk = false; 3696 bool offline = false; 3697 u8 test_results = 0; 3698 u8 test_mask = 0; 3699 int rc = 0, i; 3700 3701 if (!bp->num_tests || !BNXT_PF(bp)) 3702 return; 3703 memset(buf, 0, sizeof(u64) * bp->num_tests); 3704 if (!netif_running(dev)) { 3705 etest->flags |= ETH_TEST_FL_FAILED; 3706 return; 3707 } 3708 3709 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3710 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 3711 do_ext_lpbk = true; 3712 3713 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3714 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 3715 etest->flags |= ETH_TEST_FL_FAILED; 3716 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 3717 return; 3718 } 3719 offline = true; 3720 } 3721 3722 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3723 u8 bit_val = 1 << i; 3724 3725 if (!(bp->test_info->offline_mask & bit_val)) 3726 test_mask |= bit_val; 3727 else if (offline) 3728 test_mask |= bit_val; 3729 } 3730 if (!offline) { 3731 bnxt_run_fw_tests(bp, test_mask, &test_results); 3732 } else { 3733 bnxt_ulp_stop(bp); 3734 bnxt_close_nic(bp, true, false); 3735 bnxt_run_fw_tests(bp, test_mask, &test_results); 3736 3737 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3738 bnxt_hwrm_mac_loopback(bp, true); 3739 msleep(250); 3740 rc = bnxt_half_open_nic(bp); 3741 if (rc) { 3742 bnxt_hwrm_mac_loopback(bp, false); 3743 etest->flags |= ETH_TEST_FL_FAILED; 3744 bnxt_ulp_start(bp, rc); 3745 return; 3746 } 3747 if (bnxt_run_loopback(bp)) 3748 etest->flags |= ETH_TEST_FL_FAILED; 3749 else 3750 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3751 3752 bnxt_hwrm_mac_loopback(bp, false); 3753 bnxt_hwrm_phy_loopback(bp, true, false); 3754 msleep(1000); 3755 if (bnxt_run_loopback(bp)) { 3756 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3757 etest->flags |= ETH_TEST_FL_FAILED; 3758 } 3759 if (do_ext_lpbk) { 3760 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3761 bnxt_hwrm_phy_loopback(bp, true, true); 3762 msleep(1000); 3763 if (bnxt_run_loopback(bp)) { 3764 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3765 etest->flags |= ETH_TEST_FL_FAILED; 3766 } 3767 } 3768 bnxt_hwrm_phy_loopback(bp, false, false); 3769 bnxt_half_close_nic(bp); 3770 rc = bnxt_open_nic(bp, true, true); 3771 bnxt_ulp_start(bp, rc); 3772 } 3773 if (rc || bnxt_test_irq(bp)) { 3774 buf[BNXT_IRQ_TEST_IDX] = 1; 3775 etest->flags |= ETH_TEST_FL_FAILED; 3776 } 3777 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3778 u8 bit_val = 1 << i; 3779 3780 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3781 buf[i] = 1; 3782 etest->flags |= ETH_TEST_FL_FAILED; 3783 } 3784 } 3785 } 3786 3787 static int bnxt_reset(struct net_device *dev, u32 *flags) 3788 { 3789 struct bnxt *bp = netdev_priv(dev); 3790 bool reload = false; 3791 u32 req = *flags; 3792 3793 if (!req) 3794 return -EINVAL; 3795 3796 if (!BNXT_PF(bp)) { 3797 netdev_err(dev, "Reset is not supported from a VF\n"); 3798 return -EOPNOTSUPP; 3799 } 3800 3801 if (pci_vfs_assigned(bp->pdev) && 3802 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3803 netdev_err(dev, 3804 "Reset not allowed when VFs are assigned to VMs\n"); 3805 return -EBUSY; 3806 } 3807 3808 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3809 /* This feature is not supported in older firmware versions */ 3810 if (bp->hwrm_spec_code >= 0x10803) { 3811 if (!bnxt_firmware_reset_chip(dev)) { 3812 netdev_info(dev, "Firmware reset request successful.\n"); 3813 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3814 reload = true; 3815 *flags &= ~BNXT_FW_RESET_CHIP; 3816 } 3817 } else if (req == BNXT_FW_RESET_CHIP) { 3818 return -EOPNOTSUPP; /* only request, fail hard */ 3819 } 3820 } 3821 3822 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 3823 /* This feature is not supported in older firmware versions */ 3824 if (bp->hwrm_spec_code >= 0x10803) { 3825 if (!bnxt_firmware_reset_ap(dev)) { 3826 netdev_info(dev, "Reset application processor successful.\n"); 3827 reload = true; 3828 *flags &= ~BNXT_FW_RESET_AP; 3829 } 3830 } else if (req == BNXT_FW_RESET_AP) { 3831 return -EOPNOTSUPP; /* only request, fail hard */ 3832 } 3833 } 3834 3835 if (reload) 3836 netdev_info(dev, "Reload driver to complete reset\n"); 3837 3838 return 0; 3839 } 3840 3841 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3842 { 3843 struct bnxt *bp = netdev_priv(dev); 3844 3845 if (dump->flag > BNXT_DUMP_CRASH) { 3846 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3847 return -EINVAL; 3848 } 3849 3850 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3851 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3852 return -EOPNOTSUPP; 3853 } 3854 3855 bp->dump_flag = dump->flag; 3856 return 0; 3857 } 3858 3859 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3860 { 3861 struct bnxt *bp = netdev_priv(dev); 3862 3863 if (bp->hwrm_spec_code < 0x10801) 3864 return -EOPNOTSUPP; 3865 3866 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3867 bp->ver_resp.hwrm_fw_min_8b << 16 | 3868 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3869 bp->ver_resp.hwrm_fw_rsvd_8b; 3870 3871 dump->flag = bp->dump_flag; 3872 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 3873 return 0; 3874 } 3875 3876 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3877 void *buf) 3878 { 3879 struct bnxt *bp = netdev_priv(dev); 3880 3881 if (bp->hwrm_spec_code < 0x10801) 3882 return -EOPNOTSUPP; 3883 3884 memset(buf, 0, dump->len); 3885 3886 dump->flag = bp->dump_flag; 3887 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 3888 } 3889 3890 static int bnxt_get_ts_info(struct net_device *dev, 3891 struct ethtool_ts_info *info) 3892 { 3893 struct bnxt *bp = netdev_priv(dev); 3894 struct bnxt_ptp_cfg *ptp; 3895 3896 ptp = bp->ptp_cfg; 3897 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3898 SOF_TIMESTAMPING_RX_SOFTWARE | 3899 SOF_TIMESTAMPING_SOFTWARE; 3900 3901 info->phc_index = -1; 3902 if (!ptp) 3903 return 0; 3904 3905 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 3906 SOF_TIMESTAMPING_RX_HARDWARE | 3907 SOF_TIMESTAMPING_RAW_HARDWARE; 3908 if (ptp->ptp_clock) 3909 info->phc_index = ptp_clock_index(ptp->ptp_clock); 3910 3911 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 3912 3913 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3914 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 3915 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 3916 3917 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 3918 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 3919 return 0; 3920 } 3921 3922 void bnxt_ethtool_init(struct bnxt *bp) 3923 { 3924 struct hwrm_selftest_qlist_output *resp; 3925 struct hwrm_selftest_qlist_input *req; 3926 struct bnxt_test_info *test_info; 3927 struct net_device *dev = bp->dev; 3928 int i, rc; 3929 3930 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3931 bnxt_get_pkgver(dev); 3932 3933 bp->num_tests = 0; 3934 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 3935 return; 3936 3937 test_info = bp->test_info; 3938 if (!test_info) { 3939 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3940 if (!test_info) 3941 return; 3942 bp->test_info = test_info; 3943 } 3944 3945 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 3946 return; 3947 3948 resp = hwrm_req_hold(bp, req); 3949 rc = hwrm_req_send_silent(bp, req); 3950 if (rc) 3951 goto ethtool_init_exit; 3952 3953 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3954 if (bp->num_tests > BNXT_MAX_TEST) 3955 bp->num_tests = BNXT_MAX_TEST; 3956 3957 test_info->offline_mask = resp->offline_tests; 3958 test_info->timeout = le16_to_cpu(resp->test_timeout); 3959 if (!test_info->timeout) 3960 test_info->timeout = HWRM_CMD_TIMEOUT; 3961 for (i = 0; i < bp->num_tests; i++) { 3962 char *str = test_info->string[i]; 3963 char *fw_str = resp->test_name[i]; 3964 3965 if (i == BNXT_MACLPBK_TEST_IDX) { 3966 strcpy(str, "Mac loopback test (offline)"); 3967 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3968 strcpy(str, "Phy loopback test (offline)"); 3969 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3970 strcpy(str, "Ext loopback test (offline)"); 3971 } else if (i == BNXT_IRQ_TEST_IDX) { 3972 strcpy(str, "Interrupt_test (offline)"); 3973 } else { 3974 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 3975 fw_str, test_info->offline_mask & (1 << i) ? 3976 "offline" : "online"); 3977 } 3978 } 3979 3980 ethtool_init_exit: 3981 hwrm_req_drop(bp, req); 3982 } 3983 3984 static void bnxt_get_eth_phy_stats(struct net_device *dev, 3985 struct ethtool_eth_phy_stats *phy_stats) 3986 { 3987 struct bnxt *bp = netdev_priv(dev); 3988 u64 *rx; 3989 3990 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3991 return; 3992 3993 rx = bp->rx_port_stats_ext.sw_stats; 3994 phy_stats->SymbolErrorDuringCarrier = 3995 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 3996 } 3997 3998 static void bnxt_get_eth_mac_stats(struct net_device *dev, 3999 struct ethtool_eth_mac_stats *mac_stats) 4000 { 4001 struct bnxt *bp = netdev_priv(dev); 4002 u64 *rx, *tx; 4003 4004 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4005 return; 4006 4007 rx = bp->port_stats.sw_stats; 4008 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4009 4010 mac_stats->FramesReceivedOK = 4011 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 4012 mac_stats->FramesTransmittedOK = 4013 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 4014 mac_stats->FrameCheckSequenceErrors = 4015 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 4016 mac_stats->AlignmentErrors = 4017 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 4018 mac_stats->OutOfRangeLengthField = 4019 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 4020 } 4021 4022 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 4023 struct ethtool_eth_ctrl_stats *ctrl_stats) 4024 { 4025 struct bnxt *bp = netdev_priv(dev); 4026 u64 *rx; 4027 4028 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4029 return; 4030 4031 rx = bp->port_stats.sw_stats; 4032 ctrl_stats->MACControlFramesReceived = 4033 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 4034 } 4035 4036 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 4037 { 0, 64 }, 4038 { 65, 127 }, 4039 { 128, 255 }, 4040 { 256, 511 }, 4041 { 512, 1023 }, 4042 { 1024, 1518 }, 4043 { 1519, 2047 }, 4044 { 2048, 4095 }, 4045 { 4096, 9216 }, 4046 { 9217, 16383 }, 4047 {} 4048 }; 4049 4050 static void bnxt_get_rmon_stats(struct net_device *dev, 4051 struct ethtool_rmon_stats *rmon_stats, 4052 const struct ethtool_rmon_hist_range **ranges) 4053 { 4054 struct bnxt *bp = netdev_priv(dev); 4055 u64 *rx, *tx; 4056 4057 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4058 return; 4059 4060 rx = bp->port_stats.sw_stats; 4061 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4062 4063 rmon_stats->jabbers = 4064 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 4065 rmon_stats->oversize_pkts = 4066 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 4067 rmon_stats->undersize_pkts = 4068 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 4069 4070 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 4071 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 4072 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 4073 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 4074 rmon_stats->hist[4] = 4075 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 4076 rmon_stats->hist[5] = 4077 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 4078 rmon_stats->hist[6] = 4079 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 4080 rmon_stats->hist[7] = 4081 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 4082 rmon_stats->hist[8] = 4083 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 4084 rmon_stats->hist[9] = 4085 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 4086 4087 rmon_stats->hist_tx[0] = 4088 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 4089 rmon_stats->hist_tx[1] = 4090 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 4091 rmon_stats->hist_tx[2] = 4092 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 4093 rmon_stats->hist_tx[3] = 4094 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 4095 rmon_stats->hist_tx[4] = 4096 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 4097 rmon_stats->hist_tx[5] = 4098 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 4099 rmon_stats->hist_tx[6] = 4100 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 4101 rmon_stats->hist_tx[7] = 4102 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 4103 rmon_stats->hist_tx[8] = 4104 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 4105 rmon_stats->hist_tx[9] = 4106 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 4107 4108 *ranges = bnxt_rmon_ranges; 4109 } 4110 4111 static void bnxt_get_link_ext_stats(struct net_device *dev, 4112 struct ethtool_link_ext_stats *stats) 4113 { 4114 struct bnxt *bp = netdev_priv(dev); 4115 u64 *rx; 4116 4117 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 4118 return; 4119 4120 rx = bp->rx_port_stats_ext.sw_stats; 4121 stats->link_down_events = 4122 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 4123 } 4124 4125 void bnxt_ethtool_free(struct bnxt *bp) 4126 { 4127 kfree(bp->test_info); 4128 bp->test_info = NULL; 4129 } 4130 4131 const struct ethtool_ops bnxt_ethtool_ops = { 4132 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 4133 ETHTOOL_COALESCE_MAX_FRAMES | 4134 ETHTOOL_COALESCE_USECS_IRQ | 4135 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 4136 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 4137 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 4138 ETHTOOL_COALESCE_USE_CQE, 4139 .get_link_ksettings = bnxt_get_link_ksettings, 4140 .set_link_ksettings = bnxt_set_link_ksettings, 4141 .get_fec_stats = bnxt_get_fec_stats, 4142 .get_fecparam = bnxt_get_fecparam, 4143 .set_fecparam = bnxt_set_fecparam, 4144 .get_pause_stats = bnxt_get_pause_stats, 4145 .get_pauseparam = bnxt_get_pauseparam, 4146 .set_pauseparam = bnxt_set_pauseparam, 4147 .get_drvinfo = bnxt_get_drvinfo, 4148 .get_regs_len = bnxt_get_regs_len, 4149 .get_regs = bnxt_get_regs, 4150 .get_wol = bnxt_get_wol, 4151 .set_wol = bnxt_set_wol, 4152 .get_coalesce = bnxt_get_coalesce, 4153 .set_coalesce = bnxt_set_coalesce, 4154 .get_msglevel = bnxt_get_msglevel, 4155 .set_msglevel = bnxt_set_msglevel, 4156 .get_sset_count = bnxt_get_sset_count, 4157 .get_strings = bnxt_get_strings, 4158 .get_ethtool_stats = bnxt_get_ethtool_stats, 4159 .set_ringparam = bnxt_set_ringparam, 4160 .get_ringparam = bnxt_get_ringparam, 4161 .get_channels = bnxt_get_channels, 4162 .set_channels = bnxt_set_channels, 4163 .get_rxnfc = bnxt_get_rxnfc, 4164 .set_rxnfc = bnxt_set_rxnfc, 4165 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 4166 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 4167 .get_rxfh = bnxt_get_rxfh, 4168 .set_rxfh = bnxt_set_rxfh, 4169 .flash_device = bnxt_flash_device, 4170 .get_eeprom_len = bnxt_get_eeprom_len, 4171 .get_eeprom = bnxt_get_eeprom, 4172 .set_eeprom = bnxt_set_eeprom, 4173 .get_link = bnxt_get_link, 4174 .get_link_ext_stats = bnxt_get_link_ext_stats, 4175 .get_eee = bnxt_get_eee, 4176 .set_eee = bnxt_set_eee, 4177 .get_module_info = bnxt_get_module_info, 4178 .get_module_eeprom = bnxt_get_module_eeprom, 4179 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 4180 .nway_reset = bnxt_nway_reset, 4181 .set_phys_id = bnxt_set_phys_id, 4182 .self_test = bnxt_self_test, 4183 .get_ts_info = bnxt_get_ts_info, 4184 .reset = bnxt_reset, 4185 .set_dump = bnxt_set_dump, 4186 .get_dump_flag = bnxt_get_dump_flag, 4187 .get_dump_data = bnxt_get_dump_data, 4188 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 4189 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 4190 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 4191 .get_rmon_stats = bnxt_get_rmon_stats, 4192 }; 4193