1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/etherdevice.h> 17 #include <linux/crc32.h> 18 #include <linux/firmware.h> 19 #include <linux/utsname.h> 20 #include <linux/time.h> 21 #include "bnxt_hsi.h" 22 #include "bnxt.h" 23 #include "bnxt_xdp.h" 24 #include "bnxt_ethtool.h" 25 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 26 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 27 #include "bnxt_coredump.h" 28 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 29 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 30 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 32 static u32 bnxt_get_msglevel(struct net_device *dev) 33 { 34 struct bnxt *bp = netdev_priv(dev); 35 36 return bp->msg_enable; 37 } 38 39 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 40 { 41 struct bnxt *bp = netdev_priv(dev); 42 43 bp->msg_enable = value; 44 } 45 46 static int bnxt_get_coalesce(struct net_device *dev, 47 struct ethtool_coalesce *coal) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 struct bnxt_coal *hw_coal; 51 u16 mult; 52 53 memset(coal, 0, sizeof(*coal)); 54 55 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 56 57 hw_coal = &bp->rx_coal; 58 mult = hw_coal->bufs_per_record; 59 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 60 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 61 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 62 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 63 64 hw_coal = &bp->tx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 71 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 72 73 return 0; 74 } 75 76 static int bnxt_set_coalesce(struct net_device *dev, 77 struct ethtool_coalesce *coal) 78 { 79 struct bnxt *bp = netdev_priv(dev); 80 bool update_stats = false; 81 struct bnxt_coal *hw_coal; 82 int rc = 0; 83 u16 mult; 84 85 if (coal->use_adaptive_rx_coalesce) { 86 bp->flags |= BNXT_FLAG_DIM; 87 } else { 88 if (bp->flags & BNXT_FLAG_DIM) { 89 bp->flags &= ~(BNXT_FLAG_DIM); 90 goto reset_coalesce; 91 } 92 } 93 94 hw_coal = &bp->rx_coal; 95 mult = hw_coal->bufs_per_record; 96 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 97 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 98 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 99 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 100 101 hw_coal = &bp->tx_coal; 102 mult = hw_coal->bufs_per_record; 103 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 104 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 105 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 106 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 107 108 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 109 u32 stats_ticks = coal->stats_block_coalesce_usecs; 110 111 /* Allow 0, which means disable. */ 112 if (stats_ticks) 113 stats_ticks = clamp_t(u32, stats_ticks, 114 BNXT_MIN_STATS_COAL_TICKS, 115 BNXT_MAX_STATS_COAL_TICKS); 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 117 bp->stats_coal_ticks = stats_ticks; 118 if (bp->stats_coal_ticks) 119 bp->current_interval = 120 bp->stats_coal_ticks * HZ / 1000000; 121 else 122 bp->current_interval = BNXT_TIMER_INTERVAL; 123 update_stats = true; 124 } 125 126 reset_coalesce: 127 if (netif_running(dev)) { 128 if (update_stats) { 129 rc = bnxt_close_nic(bp, true, false); 130 if (!rc) 131 rc = bnxt_open_nic(bp, true, false); 132 } else { 133 rc = bnxt_hwrm_set_coal(bp); 134 } 135 } 136 137 return rc; 138 } 139 140 static const char * const bnxt_ring_stats_str[] = { 141 "rx_ucast_packets", 142 "rx_mcast_packets", 143 "rx_bcast_packets", 144 "rx_discards", 145 "rx_drops", 146 "rx_ucast_bytes", 147 "rx_mcast_bytes", 148 "rx_bcast_bytes", 149 "tx_ucast_packets", 150 "tx_mcast_packets", 151 "tx_bcast_packets", 152 "tx_discards", 153 "tx_drops", 154 "tx_ucast_bytes", 155 "tx_mcast_bytes", 156 "tx_bcast_bytes", 157 }; 158 159 static const char * const bnxt_ring_tpa_stats_str[] = { 160 "tpa_packets", 161 "tpa_bytes", 162 "tpa_events", 163 "tpa_aborts", 164 }; 165 166 static const char * const bnxt_ring_tpa2_stats_str[] = { 167 "rx_tpa_eligible_pkt", 168 "rx_tpa_eligible_bytes", 169 "rx_tpa_pkt", 170 "rx_tpa_bytes", 171 "rx_tpa_errors", 172 }; 173 174 static const char * const bnxt_ring_sw_stats_str[] = { 175 "rx_l4_csum_errors", 176 "rx_buf_errors", 177 "missed_irqs", 178 }; 179 180 #define BNXT_RX_STATS_ENTRY(counter) \ 181 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 182 183 #define BNXT_TX_STATS_ENTRY(counter) \ 184 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 185 186 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 187 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 188 189 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 190 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 191 192 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 193 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 194 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 195 196 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 197 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 198 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 199 200 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 201 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 202 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 203 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 204 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 205 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 206 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 207 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 208 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 209 210 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 211 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 212 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 213 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 214 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 215 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 216 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 217 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 218 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 219 220 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 221 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 222 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 223 224 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 225 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 226 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 227 228 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 229 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 230 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 231 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 232 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 233 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 234 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 235 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 236 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 237 238 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 239 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 240 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 241 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 242 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 243 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 244 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 245 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 246 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 247 248 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 249 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 250 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 251 252 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 253 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 254 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 255 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 256 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 257 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 258 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 259 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 260 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 261 262 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 263 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 264 __stringify(counter##_pri##n) } 265 266 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 267 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 268 __stringify(counter##_pri##n) } 269 270 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 271 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 272 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 273 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 274 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 275 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 276 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 277 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 278 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 279 280 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 281 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 282 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 283 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 284 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 285 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 286 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 287 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 288 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 289 290 #define BNXT_PCIE_STATS_ENTRY(counter) \ 291 { BNXT_PCIE_STATS_OFFSET(counter), __stringify(counter) } 292 293 enum { 294 RX_TOTAL_DISCARDS, 295 TX_TOTAL_DISCARDS, 296 }; 297 298 static struct { 299 u64 counter; 300 char string[ETH_GSTRING_LEN]; 301 } bnxt_sw_func_stats[] = { 302 {0, "rx_total_discard_pkts"}, 303 {0, "tx_total_discard_pkts"}, 304 }; 305 306 static const struct { 307 long offset; 308 char string[ETH_GSTRING_LEN]; 309 } bnxt_port_stats_arr[] = { 310 BNXT_RX_STATS_ENTRY(rx_64b_frames), 311 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 312 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 313 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 314 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 315 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 316 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 317 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 318 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 319 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 320 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 321 BNXT_RX_STATS_ENTRY(rx_total_frames), 322 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 323 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 324 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 325 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 326 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 327 BNXT_RX_STATS_ENTRY(rx_pause_frames), 328 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 329 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 330 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 331 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 332 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 333 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 334 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 335 BNXT_RX_STATS_ENTRY(rx_good_frames), 336 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 337 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 338 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 339 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 340 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 341 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 342 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 343 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 344 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 345 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 346 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 347 BNXT_RX_STATS_ENTRY(rx_bytes), 348 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 349 BNXT_RX_STATS_ENTRY(rx_runt_frames), 350 BNXT_RX_STATS_ENTRY(rx_stat_discard), 351 BNXT_RX_STATS_ENTRY(rx_stat_err), 352 353 BNXT_TX_STATS_ENTRY(tx_64b_frames), 354 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 355 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 356 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 357 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 358 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 359 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 360 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 361 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 362 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 363 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 364 BNXT_TX_STATS_ENTRY(tx_good_frames), 365 BNXT_TX_STATS_ENTRY(tx_total_frames), 366 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 367 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 368 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 369 BNXT_TX_STATS_ENTRY(tx_pause_frames), 370 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 371 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 372 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 373 BNXT_TX_STATS_ENTRY(tx_err), 374 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 375 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 376 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 377 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 378 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 379 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 380 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 381 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 382 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 383 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 384 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 385 BNXT_TX_STATS_ENTRY(tx_total_collisions), 386 BNXT_TX_STATS_ENTRY(tx_bytes), 387 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 388 BNXT_TX_STATS_ENTRY(tx_stat_discard), 389 BNXT_TX_STATS_ENTRY(tx_stat_error), 390 }; 391 392 static const struct { 393 long offset; 394 char string[ETH_GSTRING_LEN]; 395 } bnxt_port_stats_ext_arr[] = { 396 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 397 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 398 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 399 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 400 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 401 BNXT_RX_STATS_EXT_COS_ENTRIES, 402 BNXT_RX_STATS_EXT_PFC_ENTRIES, 403 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 404 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 405 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 406 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 407 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 408 }; 409 410 static const struct { 411 long offset; 412 char string[ETH_GSTRING_LEN]; 413 } bnxt_tx_port_stats_ext_arr[] = { 414 BNXT_TX_STATS_EXT_COS_ENTRIES, 415 BNXT_TX_STATS_EXT_PFC_ENTRIES, 416 }; 417 418 static const struct { 419 long base_off; 420 char string[ETH_GSTRING_LEN]; 421 } bnxt_rx_bytes_pri_arr[] = { 422 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 423 }; 424 425 static const struct { 426 long base_off; 427 char string[ETH_GSTRING_LEN]; 428 } bnxt_rx_pkts_pri_arr[] = { 429 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 430 }; 431 432 static const struct { 433 long base_off; 434 char string[ETH_GSTRING_LEN]; 435 } bnxt_tx_bytes_pri_arr[] = { 436 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 437 }; 438 439 static const struct { 440 long base_off; 441 char string[ETH_GSTRING_LEN]; 442 } bnxt_tx_pkts_pri_arr[] = { 443 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 444 }; 445 446 static const struct { 447 long offset; 448 char string[ETH_GSTRING_LEN]; 449 } bnxt_pcie_stats_arr[] = { 450 BNXT_PCIE_STATS_ENTRY(pcie_pl_signal_integrity), 451 BNXT_PCIE_STATS_ENTRY(pcie_dl_signal_integrity), 452 BNXT_PCIE_STATS_ENTRY(pcie_tl_signal_integrity), 453 BNXT_PCIE_STATS_ENTRY(pcie_link_integrity), 454 BNXT_PCIE_STATS_ENTRY(pcie_tx_traffic_rate), 455 BNXT_PCIE_STATS_ENTRY(pcie_rx_traffic_rate), 456 BNXT_PCIE_STATS_ENTRY(pcie_tx_dllp_statistics), 457 BNXT_PCIE_STATS_ENTRY(pcie_rx_dllp_statistics), 458 BNXT_PCIE_STATS_ENTRY(pcie_equalization_time), 459 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[0]), 460 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[2]), 461 BNXT_PCIE_STATS_ENTRY(pcie_recovery_histogram), 462 }; 463 464 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 465 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 466 #define BNXT_NUM_STATS_PRI \ 467 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 468 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 469 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 470 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 471 #define BNXT_NUM_PCIE_STATS ARRAY_SIZE(bnxt_pcie_stats_arr) 472 473 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 474 { 475 if (BNXT_SUPPORTS_TPA(bp)) { 476 if (bp->max_tpa_v2) 477 return ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 478 return ARRAY_SIZE(bnxt_ring_tpa_stats_str); 479 } 480 return 0; 481 } 482 483 static int bnxt_get_num_ring_stats(struct bnxt *bp) 484 { 485 int num_stats; 486 487 num_stats = ARRAY_SIZE(bnxt_ring_stats_str) + 488 ARRAY_SIZE(bnxt_ring_sw_stats_str) + 489 bnxt_get_num_tpa_ring_stats(bp); 490 return num_stats * bp->cp_nr_rings; 491 } 492 493 static int bnxt_get_num_stats(struct bnxt *bp) 494 { 495 int num_stats = bnxt_get_num_ring_stats(bp); 496 497 num_stats += BNXT_NUM_SW_FUNC_STATS; 498 499 if (bp->flags & BNXT_FLAG_PORT_STATS) 500 num_stats += BNXT_NUM_PORT_STATS; 501 502 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 503 num_stats += bp->fw_rx_stats_ext_size + 504 bp->fw_tx_stats_ext_size; 505 if (bp->pri2cos_valid) 506 num_stats += BNXT_NUM_STATS_PRI; 507 } 508 509 if (bp->flags & BNXT_FLAG_PCIE_STATS) 510 num_stats += BNXT_NUM_PCIE_STATS; 511 512 return num_stats; 513 } 514 515 static int bnxt_get_sset_count(struct net_device *dev, int sset) 516 { 517 struct bnxt *bp = netdev_priv(dev); 518 519 switch (sset) { 520 case ETH_SS_STATS: 521 return bnxt_get_num_stats(bp); 522 case ETH_SS_TEST: 523 if (!bp->num_tests) 524 return -EOPNOTSUPP; 525 return bp->num_tests; 526 default: 527 return -EOPNOTSUPP; 528 } 529 } 530 531 static void bnxt_get_ethtool_stats(struct net_device *dev, 532 struct ethtool_stats *stats, u64 *buf) 533 { 534 u32 i, j = 0; 535 struct bnxt *bp = netdev_priv(dev); 536 u32 stat_fields = ARRAY_SIZE(bnxt_ring_stats_str) + 537 bnxt_get_num_tpa_ring_stats(bp); 538 539 if (!bp->bnapi) { 540 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 541 goto skip_ring_stats; 542 } 543 544 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 545 bnxt_sw_func_stats[i].counter = 0; 546 547 for (i = 0; i < bp->cp_nr_rings; i++) { 548 struct bnxt_napi *bnapi = bp->bnapi[i]; 549 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 550 __le64 *hw_stats = (__le64 *)cpr->hw_stats; 551 int k; 552 553 for (k = 0; k < stat_fields; j++, k++) 554 buf[j] = le64_to_cpu(hw_stats[k]); 555 buf[j++] = cpr->rx_l4_csum_errors; 556 buf[j++] = cpr->rx_buf_errors; 557 buf[j++] = cpr->missed_irqs; 558 559 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 560 le64_to_cpu(cpr->hw_stats->rx_discard_pkts); 561 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 562 le64_to_cpu(cpr->hw_stats->tx_discard_pkts); 563 } 564 565 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 566 buf[j] = bnxt_sw_func_stats[i].counter; 567 568 skip_ring_stats: 569 if (bp->flags & BNXT_FLAG_PORT_STATS) { 570 __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats; 571 572 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) { 573 buf[j] = le64_to_cpu(*(port_stats + 574 bnxt_port_stats_arr[i].offset)); 575 } 576 } 577 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 578 __le64 *rx_port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext; 579 __le64 *tx_port_stats_ext = (__le64 *)bp->hw_tx_port_stats_ext; 580 581 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 582 buf[j] = le64_to_cpu(*(rx_port_stats_ext + 583 bnxt_port_stats_ext_arr[i].offset)); 584 } 585 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 586 buf[j] = le64_to_cpu(*(tx_port_stats_ext + 587 bnxt_tx_port_stats_ext_arr[i].offset)); 588 } 589 if (bp->pri2cos_valid) { 590 for (i = 0; i < 8; i++, j++) { 591 long n = bnxt_rx_bytes_pri_arr[i].base_off + 592 bp->pri2cos[i]; 593 594 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 595 } 596 for (i = 0; i < 8; i++, j++) { 597 long n = bnxt_rx_pkts_pri_arr[i].base_off + 598 bp->pri2cos[i]; 599 600 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 601 } 602 for (i = 0; i < 8; i++, j++) { 603 long n = bnxt_tx_bytes_pri_arr[i].base_off + 604 bp->pri2cos[i]; 605 606 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 607 } 608 for (i = 0; i < 8; i++, j++) { 609 long n = bnxt_tx_pkts_pri_arr[i].base_off + 610 bp->pri2cos[i]; 611 612 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 613 } 614 } 615 } 616 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 617 __le64 *pcie_stats = (__le64 *)bp->hw_pcie_stats; 618 619 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++, j++) { 620 buf[j] = le64_to_cpu(*(pcie_stats + 621 bnxt_pcie_stats_arr[i].offset)); 622 } 623 } 624 } 625 626 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 627 { 628 struct bnxt *bp = netdev_priv(dev); 629 static const char * const *str; 630 u32 i, j, num_str; 631 632 switch (stringset) { 633 case ETH_SS_STATS: 634 for (i = 0; i < bp->cp_nr_rings; i++) { 635 num_str = ARRAY_SIZE(bnxt_ring_stats_str); 636 for (j = 0; j < num_str; j++) { 637 sprintf(buf, "[%d]: %s", i, 638 bnxt_ring_stats_str[j]); 639 buf += ETH_GSTRING_LEN; 640 } 641 if (!BNXT_SUPPORTS_TPA(bp)) 642 goto skip_tpa_stats; 643 644 if (bp->max_tpa_v2) { 645 num_str = ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 646 str = bnxt_ring_tpa2_stats_str; 647 } else { 648 num_str = ARRAY_SIZE(bnxt_ring_tpa_stats_str); 649 str = bnxt_ring_tpa_stats_str; 650 } 651 for (j = 0; j < num_str; j++) { 652 sprintf(buf, "[%d]: %s", i, str[j]); 653 buf += ETH_GSTRING_LEN; 654 } 655 skip_tpa_stats: 656 num_str = ARRAY_SIZE(bnxt_ring_sw_stats_str); 657 for (j = 0; j < num_str; j++) { 658 sprintf(buf, "[%d]: %s", i, 659 bnxt_ring_sw_stats_str[j]); 660 buf += ETH_GSTRING_LEN; 661 } 662 } 663 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 664 strcpy(buf, bnxt_sw_func_stats[i].string); 665 buf += ETH_GSTRING_LEN; 666 } 667 668 if (bp->flags & BNXT_FLAG_PORT_STATS) { 669 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 670 strcpy(buf, bnxt_port_stats_arr[i].string); 671 buf += ETH_GSTRING_LEN; 672 } 673 } 674 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 675 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 676 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 677 buf += ETH_GSTRING_LEN; 678 } 679 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 680 strcpy(buf, 681 bnxt_tx_port_stats_ext_arr[i].string); 682 buf += ETH_GSTRING_LEN; 683 } 684 if (bp->pri2cos_valid) { 685 for (i = 0; i < 8; i++) { 686 strcpy(buf, 687 bnxt_rx_bytes_pri_arr[i].string); 688 buf += ETH_GSTRING_LEN; 689 } 690 for (i = 0; i < 8; i++) { 691 strcpy(buf, 692 bnxt_rx_pkts_pri_arr[i].string); 693 buf += ETH_GSTRING_LEN; 694 } 695 for (i = 0; i < 8; i++) { 696 strcpy(buf, 697 bnxt_tx_bytes_pri_arr[i].string); 698 buf += ETH_GSTRING_LEN; 699 } 700 for (i = 0; i < 8; i++) { 701 strcpy(buf, 702 bnxt_tx_pkts_pri_arr[i].string); 703 buf += ETH_GSTRING_LEN; 704 } 705 } 706 } 707 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 708 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++) { 709 strcpy(buf, bnxt_pcie_stats_arr[i].string); 710 buf += ETH_GSTRING_LEN; 711 } 712 } 713 break; 714 case ETH_SS_TEST: 715 if (bp->num_tests) 716 memcpy(buf, bp->test_info->string, 717 bp->num_tests * ETH_GSTRING_LEN); 718 break; 719 default: 720 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 721 stringset); 722 break; 723 } 724 } 725 726 static void bnxt_get_ringparam(struct net_device *dev, 727 struct ethtool_ringparam *ering) 728 { 729 struct bnxt *bp = netdev_priv(dev); 730 731 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 732 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 733 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 734 735 ering->rx_pending = bp->rx_ring_size; 736 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 737 ering->tx_pending = bp->tx_ring_size; 738 } 739 740 static int bnxt_set_ringparam(struct net_device *dev, 741 struct ethtool_ringparam *ering) 742 { 743 struct bnxt *bp = netdev_priv(dev); 744 745 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 746 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 747 (ering->tx_pending <= MAX_SKB_FRAGS)) 748 return -EINVAL; 749 750 if (netif_running(dev)) 751 bnxt_close_nic(bp, false, false); 752 753 bp->rx_ring_size = ering->rx_pending; 754 bp->tx_ring_size = ering->tx_pending; 755 bnxt_set_ring_params(bp); 756 757 if (netif_running(dev)) 758 return bnxt_open_nic(bp, false, false); 759 760 return 0; 761 } 762 763 static void bnxt_get_channels(struct net_device *dev, 764 struct ethtool_channels *channel) 765 { 766 struct bnxt *bp = netdev_priv(dev); 767 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 768 int max_rx_rings, max_tx_rings, tcs; 769 int max_tx_sch_inputs; 770 771 /* Get the most up-to-date max_tx_sch_inputs. */ 772 if (BNXT_NEW_RM(bp)) 773 bnxt_hwrm_func_resc_qcaps(bp, false); 774 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 775 776 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 777 if (max_tx_sch_inputs) 778 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 779 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 780 781 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 782 max_rx_rings = 0; 783 max_tx_rings = 0; 784 } 785 if (max_tx_sch_inputs) 786 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 787 788 tcs = netdev_get_num_tc(dev); 789 if (tcs > 1) 790 max_tx_rings /= tcs; 791 792 channel->max_rx = max_rx_rings; 793 channel->max_tx = max_tx_rings; 794 channel->max_other = 0; 795 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 796 channel->combined_count = bp->rx_nr_rings; 797 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 798 channel->combined_count--; 799 } else { 800 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 801 channel->rx_count = bp->rx_nr_rings; 802 channel->tx_count = bp->tx_nr_rings_per_tc; 803 } 804 } 805 } 806 807 static int bnxt_set_channels(struct net_device *dev, 808 struct ethtool_channels *channel) 809 { 810 struct bnxt *bp = netdev_priv(dev); 811 int req_tx_rings, req_rx_rings, tcs; 812 bool sh = false; 813 int tx_xdp = 0; 814 int rc = 0; 815 816 if (channel->other_count) 817 return -EINVAL; 818 819 if (!channel->combined_count && 820 (!channel->rx_count || !channel->tx_count)) 821 return -EINVAL; 822 823 if (channel->combined_count && 824 (channel->rx_count || channel->tx_count)) 825 return -EINVAL; 826 827 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 828 channel->tx_count)) 829 return -EINVAL; 830 831 if (channel->combined_count) 832 sh = true; 833 834 tcs = netdev_get_num_tc(dev); 835 836 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 837 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 838 if (bp->tx_nr_rings_xdp) { 839 if (!sh) { 840 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 841 return -EINVAL; 842 } 843 tx_xdp = req_rx_rings; 844 } 845 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 846 if (rc) { 847 netdev_warn(dev, "Unable to allocate the requested rings\n"); 848 return rc; 849 } 850 851 if (netif_running(dev)) { 852 if (BNXT_PF(bp)) { 853 /* TODO CHIMP_FW: Send message to all VF's 854 * before PF unload 855 */ 856 } 857 rc = bnxt_close_nic(bp, true, false); 858 if (rc) { 859 netdev_err(bp->dev, "Set channel failure rc :%x\n", 860 rc); 861 return rc; 862 } 863 } 864 865 if (sh) { 866 bp->flags |= BNXT_FLAG_SHARED_RINGS; 867 bp->rx_nr_rings = channel->combined_count; 868 bp->tx_nr_rings_per_tc = channel->combined_count; 869 } else { 870 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 871 bp->rx_nr_rings = channel->rx_count; 872 bp->tx_nr_rings_per_tc = channel->tx_count; 873 } 874 bp->tx_nr_rings_xdp = tx_xdp; 875 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 876 if (tcs > 1) 877 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 878 879 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 880 bp->tx_nr_rings + bp->rx_nr_rings; 881 882 /* After changing number of rx channels, update NTUPLE feature. */ 883 netdev_update_features(dev); 884 if (netif_running(dev)) { 885 rc = bnxt_open_nic(bp, true, false); 886 if ((!rc) && BNXT_PF(bp)) { 887 /* TODO CHIMP_FW: Send message to all VF's 888 * to renable 889 */ 890 } 891 } else { 892 rc = bnxt_reserve_rings(bp, true); 893 } 894 895 return rc; 896 } 897 898 #ifdef CONFIG_RFS_ACCEL 899 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 900 u32 *rule_locs) 901 { 902 int i, j = 0; 903 904 cmd->data = bp->ntp_fltr_count; 905 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 906 struct hlist_head *head; 907 struct bnxt_ntuple_filter *fltr; 908 909 head = &bp->ntp_fltr_hash_tbl[i]; 910 rcu_read_lock(); 911 hlist_for_each_entry_rcu(fltr, head, hash) { 912 if (j == cmd->rule_cnt) 913 break; 914 rule_locs[j++] = fltr->sw_id; 915 } 916 rcu_read_unlock(); 917 if (j == cmd->rule_cnt) 918 break; 919 } 920 cmd->rule_cnt = j; 921 return 0; 922 } 923 924 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 925 { 926 struct ethtool_rx_flow_spec *fs = 927 (struct ethtool_rx_flow_spec *)&cmd->fs; 928 struct bnxt_ntuple_filter *fltr; 929 struct flow_keys *fkeys; 930 int i, rc = -EINVAL; 931 932 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 933 return rc; 934 935 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 936 struct hlist_head *head; 937 938 head = &bp->ntp_fltr_hash_tbl[i]; 939 rcu_read_lock(); 940 hlist_for_each_entry_rcu(fltr, head, hash) { 941 if (fltr->sw_id == fs->location) 942 goto fltr_found; 943 } 944 rcu_read_unlock(); 945 } 946 return rc; 947 948 fltr_found: 949 fkeys = &fltr->fkeys; 950 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 951 if (fkeys->basic.ip_proto == IPPROTO_TCP) 952 fs->flow_type = TCP_V4_FLOW; 953 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 954 fs->flow_type = UDP_V4_FLOW; 955 else 956 goto fltr_err; 957 958 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 959 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 960 961 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 962 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 963 964 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 965 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 966 967 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 968 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 969 } else { 970 int i; 971 972 if (fkeys->basic.ip_proto == IPPROTO_TCP) 973 fs->flow_type = TCP_V6_FLOW; 974 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 975 fs->flow_type = UDP_V6_FLOW; 976 else 977 goto fltr_err; 978 979 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 980 fkeys->addrs.v6addrs.src; 981 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 982 fkeys->addrs.v6addrs.dst; 983 for (i = 0; i < 4; i++) { 984 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 985 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 986 } 987 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 988 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 989 990 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 991 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 992 } 993 994 fs->ring_cookie = fltr->rxq; 995 rc = 0; 996 997 fltr_err: 998 rcu_read_unlock(); 999 1000 return rc; 1001 } 1002 #endif 1003 1004 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1005 { 1006 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1007 return RXH_IP_SRC | RXH_IP_DST; 1008 return 0; 1009 } 1010 1011 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1012 { 1013 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1014 return RXH_IP_SRC | RXH_IP_DST; 1015 return 0; 1016 } 1017 1018 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1019 { 1020 cmd->data = 0; 1021 switch (cmd->flow_type) { 1022 case TCP_V4_FLOW: 1023 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1024 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1025 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1026 cmd->data |= get_ethtool_ipv4_rss(bp); 1027 break; 1028 case UDP_V4_FLOW: 1029 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1030 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1031 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1032 /* fall through */ 1033 case SCTP_V4_FLOW: 1034 case AH_ESP_V4_FLOW: 1035 case AH_V4_FLOW: 1036 case ESP_V4_FLOW: 1037 case IPV4_FLOW: 1038 cmd->data |= get_ethtool_ipv4_rss(bp); 1039 break; 1040 1041 case TCP_V6_FLOW: 1042 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1043 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1044 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1045 cmd->data |= get_ethtool_ipv6_rss(bp); 1046 break; 1047 case UDP_V6_FLOW: 1048 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1049 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1050 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1051 /* fall through */ 1052 case SCTP_V6_FLOW: 1053 case AH_ESP_V6_FLOW: 1054 case AH_V6_FLOW: 1055 case ESP_V6_FLOW: 1056 case IPV6_FLOW: 1057 cmd->data |= get_ethtool_ipv6_rss(bp); 1058 break; 1059 } 1060 return 0; 1061 } 1062 1063 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1064 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1065 1066 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1067 { 1068 u32 rss_hash_cfg = bp->rss_hash_cfg; 1069 int tuple, rc = 0; 1070 1071 if (cmd->data == RXH_4TUPLE) 1072 tuple = 4; 1073 else if (cmd->data == RXH_2TUPLE) 1074 tuple = 2; 1075 else if (!cmd->data) 1076 tuple = 0; 1077 else 1078 return -EINVAL; 1079 1080 if (cmd->flow_type == TCP_V4_FLOW) { 1081 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1082 if (tuple == 4) 1083 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1084 } else if (cmd->flow_type == UDP_V4_FLOW) { 1085 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1086 return -EINVAL; 1087 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1088 if (tuple == 4) 1089 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1090 } else if (cmd->flow_type == TCP_V6_FLOW) { 1091 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1092 if (tuple == 4) 1093 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1094 } else if (cmd->flow_type == UDP_V6_FLOW) { 1095 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1096 return -EINVAL; 1097 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1098 if (tuple == 4) 1099 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1100 } else if (tuple == 4) { 1101 return -EINVAL; 1102 } 1103 1104 switch (cmd->flow_type) { 1105 case TCP_V4_FLOW: 1106 case UDP_V4_FLOW: 1107 case SCTP_V4_FLOW: 1108 case AH_ESP_V4_FLOW: 1109 case AH_V4_FLOW: 1110 case ESP_V4_FLOW: 1111 case IPV4_FLOW: 1112 if (tuple == 2) 1113 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1114 else if (!tuple) 1115 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1116 break; 1117 1118 case TCP_V6_FLOW: 1119 case UDP_V6_FLOW: 1120 case SCTP_V6_FLOW: 1121 case AH_ESP_V6_FLOW: 1122 case AH_V6_FLOW: 1123 case ESP_V6_FLOW: 1124 case IPV6_FLOW: 1125 if (tuple == 2) 1126 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1127 else if (!tuple) 1128 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1129 break; 1130 } 1131 1132 if (bp->rss_hash_cfg == rss_hash_cfg) 1133 return 0; 1134 1135 bp->rss_hash_cfg = rss_hash_cfg; 1136 if (netif_running(bp->dev)) { 1137 bnxt_close_nic(bp, false, false); 1138 rc = bnxt_open_nic(bp, false, false); 1139 } 1140 return rc; 1141 } 1142 1143 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1144 u32 *rule_locs) 1145 { 1146 struct bnxt *bp = netdev_priv(dev); 1147 int rc = 0; 1148 1149 switch (cmd->cmd) { 1150 #ifdef CONFIG_RFS_ACCEL 1151 case ETHTOOL_GRXRINGS: 1152 cmd->data = bp->rx_nr_rings; 1153 break; 1154 1155 case ETHTOOL_GRXCLSRLCNT: 1156 cmd->rule_cnt = bp->ntp_fltr_count; 1157 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1158 break; 1159 1160 case ETHTOOL_GRXCLSRLALL: 1161 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1162 break; 1163 1164 case ETHTOOL_GRXCLSRULE: 1165 rc = bnxt_grxclsrule(bp, cmd); 1166 break; 1167 #endif 1168 1169 case ETHTOOL_GRXFH: 1170 rc = bnxt_grxfh(bp, cmd); 1171 break; 1172 1173 default: 1174 rc = -EOPNOTSUPP; 1175 break; 1176 } 1177 1178 return rc; 1179 } 1180 1181 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1182 { 1183 struct bnxt *bp = netdev_priv(dev); 1184 int rc; 1185 1186 switch (cmd->cmd) { 1187 case ETHTOOL_SRXFH: 1188 rc = bnxt_srxfh(bp, cmd); 1189 break; 1190 1191 default: 1192 rc = -EOPNOTSUPP; 1193 break; 1194 } 1195 return rc; 1196 } 1197 1198 static u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1199 { 1200 return HW_HASH_INDEX_SIZE; 1201 } 1202 1203 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1204 { 1205 return HW_HASH_KEY_SIZE; 1206 } 1207 1208 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1209 u8 *hfunc) 1210 { 1211 struct bnxt *bp = netdev_priv(dev); 1212 struct bnxt_vnic_info *vnic; 1213 int i = 0; 1214 1215 if (hfunc) 1216 *hfunc = ETH_RSS_HASH_TOP; 1217 1218 if (!bp->vnic_info) 1219 return 0; 1220 1221 vnic = &bp->vnic_info[0]; 1222 if (indir && vnic->rss_table) { 1223 for (i = 0; i < HW_HASH_INDEX_SIZE; i++) 1224 indir[i] = le16_to_cpu(vnic->rss_table[i]); 1225 } 1226 1227 if (key && vnic->rss_hash_key) 1228 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1229 1230 return 0; 1231 } 1232 1233 static void bnxt_get_drvinfo(struct net_device *dev, 1234 struct ethtool_drvinfo *info) 1235 { 1236 struct bnxt *bp = netdev_priv(dev); 1237 1238 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1239 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1240 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1241 info->n_stats = bnxt_get_num_stats(bp); 1242 info->testinfo_len = bp->num_tests; 1243 /* TODO CHIMP_FW: eeprom dump details */ 1244 info->eedump_len = 0; 1245 /* TODO CHIMP FW: reg dump details */ 1246 info->regdump_len = 0; 1247 } 1248 1249 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1250 { 1251 struct bnxt *bp = netdev_priv(dev); 1252 1253 wol->supported = 0; 1254 wol->wolopts = 0; 1255 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1256 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1257 wol->supported = WAKE_MAGIC; 1258 if (bp->wol) 1259 wol->wolopts = WAKE_MAGIC; 1260 } 1261 } 1262 1263 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1264 { 1265 struct bnxt *bp = netdev_priv(dev); 1266 1267 if (wol->wolopts & ~WAKE_MAGIC) 1268 return -EINVAL; 1269 1270 if (wol->wolopts & WAKE_MAGIC) { 1271 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1272 return -EINVAL; 1273 if (!bp->wol) { 1274 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1275 return -EBUSY; 1276 bp->wol = 1; 1277 } 1278 } else { 1279 if (bp->wol) { 1280 if (bnxt_hwrm_free_wol_fltr(bp)) 1281 return -EBUSY; 1282 bp->wol = 0; 1283 } 1284 } 1285 return 0; 1286 } 1287 1288 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1289 { 1290 u32 speed_mask = 0; 1291 1292 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1293 /* set the advertised speeds */ 1294 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1295 speed_mask |= ADVERTISED_100baseT_Full; 1296 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1297 speed_mask |= ADVERTISED_1000baseT_Full; 1298 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1299 speed_mask |= ADVERTISED_2500baseX_Full; 1300 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1301 speed_mask |= ADVERTISED_10000baseT_Full; 1302 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1303 speed_mask |= ADVERTISED_40000baseCR4_Full; 1304 1305 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1306 speed_mask |= ADVERTISED_Pause; 1307 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1308 speed_mask |= ADVERTISED_Asym_Pause; 1309 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1310 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1311 1312 return speed_mask; 1313 } 1314 1315 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1316 { \ 1317 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1318 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1319 100baseT_Full); \ 1320 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1321 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1322 1000baseT_Full); \ 1323 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1324 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1325 10000baseT_Full); \ 1326 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1327 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1328 25000baseCR_Full); \ 1329 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1330 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1331 40000baseCR4_Full);\ 1332 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1333 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1334 50000baseCR2_Full);\ 1335 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1336 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1337 100000baseCR4_Full);\ 1338 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1339 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1340 Pause); \ 1341 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1342 ethtool_link_ksettings_add_link_mode( \ 1343 lk_ksettings, name, Asym_Pause);\ 1344 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1345 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1346 Asym_Pause); \ 1347 } \ 1348 } 1349 1350 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1351 { \ 1352 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1353 100baseT_Full) || \ 1354 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1355 100baseT_Half)) \ 1356 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1357 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1358 1000baseT_Full) || \ 1359 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1360 1000baseT_Half)) \ 1361 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1362 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1363 10000baseT_Full)) \ 1364 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1365 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1366 25000baseCR_Full)) \ 1367 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1368 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1369 40000baseCR4_Full)) \ 1370 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1371 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1372 50000baseCR2_Full)) \ 1373 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1374 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1375 100000baseCR4_Full)) \ 1376 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1377 } 1378 1379 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1380 struct ethtool_link_ksettings *lk_ksettings) 1381 { 1382 u16 fw_speeds = link_info->advertising; 1383 u8 fw_pause = 0; 1384 1385 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1386 fw_pause = link_info->auto_pause_setting; 1387 1388 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1389 } 1390 1391 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1392 struct ethtool_link_ksettings *lk_ksettings) 1393 { 1394 u16 fw_speeds = link_info->lp_auto_link_speeds; 1395 u8 fw_pause = 0; 1396 1397 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1398 fw_pause = link_info->lp_pause; 1399 1400 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1401 lp_advertising); 1402 } 1403 1404 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1405 struct ethtool_link_ksettings *lk_ksettings) 1406 { 1407 u16 fw_speeds = link_info->support_speeds; 1408 1409 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1410 1411 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1412 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1413 Asym_Pause); 1414 1415 if (link_info->support_auto_speeds) 1416 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1417 Autoneg); 1418 } 1419 1420 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1421 { 1422 switch (fw_link_speed) { 1423 case BNXT_LINK_SPEED_100MB: 1424 return SPEED_100; 1425 case BNXT_LINK_SPEED_1GB: 1426 return SPEED_1000; 1427 case BNXT_LINK_SPEED_2_5GB: 1428 return SPEED_2500; 1429 case BNXT_LINK_SPEED_10GB: 1430 return SPEED_10000; 1431 case BNXT_LINK_SPEED_20GB: 1432 return SPEED_20000; 1433 case BNXT_LINK_SPEED_25GB: 1434 return SPEED_25000; 1435 case BNXT_LINK_SPEED_40GB: 1436 return SPEED_40000; 1437 case BNXT_LINK_SPEED_50GB: 1438 return SPEED_50000; 1439 case BNXT_LINK_SPEED_100GB: 1440 return SPEED_100000; 1441 default: 1442 return SPEED_UNKNOWN; 1443 } 1444 } 1445 1446 static int bnxt_get_link_ksettings(struct net_device *dev, 1447 struct ethtool_link_ksettings *lk_ksettings) 1448 { 1449 struct bnxt *bp = netdev_priv(dev); 1450 struct bnxt_link_info *link_info = &bp->link_info; 1451 struct ethtool_link_settings *base = &lk_ksettings->base; 1452 u32 ethtool_speed; 1453 1454 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1455 mutex_lock(&bp->link_lock); 1456 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1457 1458 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1459 if (link_info->autoneg) { 1460 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1461 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1462 advertising, Autoneg); 1463 base->autoneg = AUTONEG_ENABLE; 1464 base->duplex = DUPLEX_UNKNOWN; 1465 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1466 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1467 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1468 base->duplex = DUPLEX_FULL; 1469 else 1470 base->duplex = DUPLEX_HALF; 1471 } 1472 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1473 } else { 1474 base->autoneg = AUTONEG_DISABLE; 1475 ethtool_speed = 1476 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1477 base->duplex = DUPLEX_HALF; 1478 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1479 base->duplex = DUPLEX_FULL; 1480 } 1481 base->speed = ethtool_speed; 1482 1483 base->port = PORT_NONE; 1484 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1485 base->port = PORT_TP; 1486 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1487 TP); 1488 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1489 TP); 1490 } else { 1491 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1492 FIBRE); 1493 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1494 FIBRE); 1495 1496 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1497 base->port = PORT_DA; 1498 else if (link_info->media_type == 1499 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1500 base->port = PORT_FIBRE; 1501 } 1502 base->phy_address = link_info->phy_addr; 1503 mutex_unlock(&bp->link_lock); 1504 1505 return 0; 1506 } 1507 1508 static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed) 1509 { 1510 struct bnxt *bp = netdev_priv(dev); 1511 struct bnxt_link_info *link_info = &bp->link_info; 1512 u16 support_spds = link_info->support_speeds; 1513 u32 fw_speed = 0; 1514 1515 switch (ethtool_speed) { 1516 case SPEED_100: 1517 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1518 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB; 1519 break; 1520 case SPEED_1000: 1521 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1522 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB; 1523 break; 1524 case SPEED_2500: 1525 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1526 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB; 1527 break; 1528 case SPEED_10000: 1529 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1530 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB; 1531 break; 1532 case SPEED_20000: 1533 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1534 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB; 1535 break; 1536 case SPEED_25000: 1537 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1538 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB; 1539 break; 1540 case SPEED_40000: 1541 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1542 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB; 1543 break; 1544 case SPEED_50000: 1545 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) 1546 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB; 1547 break; 1548 case SPEED_100000: 1549 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) 1550 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB; 1551 break; 1552 default: 1553 netdev_err(dev, "unsupported speed!\n"); 1554 break; 1555 } 1556 return fw_speed; 1557 } 1558 1559 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1560 { 1561 u16 fw_speed_mask = 0; 1562 1563 /* only support autoneg at speed 100, 1000, and 10000 */ 1564 if (advertising & (ADVERTISED_100baseT_Full | 1565 ADVERTISED_100baseT_Half)) { 1566 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1567 } 1568 if (advertising & (ADVERTISED_1000baseT_Full | 1569 ADVERTISED_1000baseT_Half)) { 1570 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1571 } 1572 if (advertising & ADVERTISED_10000baseT_Full) 1573 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1574 1575 if (advertising & ADVERTISED_40000baseCR4_Full) 1576 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1577 1578 return fw_speed_mask; 1579 } 1580 1581 static int bnxt_set_link_ksettings(struct net_device *dev, 1582 const struct ethtool_link_ksettings *lk_ksettings) 1583 { 1584 struct bnxt *bp = netdev_priv(dev); 1585 struct bnxt_link_info *link_info = &bp->link_info; 1586 const struct ethtool_link_settings *base = &lk_ksettings->base; 1587 bool set_pause = false; 1588 u16 fw_advertising = 0; 1589 u32 speed; 1590 int rc = 0; 1591 1592 if (!BNXT_PHY_CFG_ABLE(bp)) 1593 return -EOPNOTSUPP; 1594 1595 mutex_lock(&bp->link_lock); 1596 if (base->autoneg == AUTONEG_ENABLE) { 1597 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings, 1598 advertising); 1599 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1600 if (!fw_advertising) 1601 link_info->advertising = link_info->support_auto_speeds; 1602 else 1603 link_info->advertising = fw_advertising; 1604 /* any change to autoneg will cause link change, therefore the 1605 * driver should put back the original pause setting in autoneg 1606 */ 1607 set_pause = true; 1608 } else { 1609 u16 fw_speed; 1610 u8 phy_type = link_info->phy_type; 1611 1612 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1613 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1614 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1615 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1616 rc = -EINVAL; 1617 goto set_setting_exit; 1618 } 1619 if (base->duplex == DUPLEX_HALF) { 1620 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1621 rc = -EINVAL; 1622 goto set_setting_exit; 1623 } 1624 speed = base->speed; 1625 fw_speed = bnxt_get_fw_speed(dev, speed); 1626 if (!fw_speed) { 1627 rc = -EINVAL; 1628 goto set_setting_exit; 1629 } 1630 link_info->req_link_speed = fw_speed; 1631 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1632 link_info->autoneg = 0; 1633 link_info->advertising = 0; 1634 } 1635 1636 if (netif_running(dev)) 1637 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1638 1639 set_setting_exit: 1640 mutex_unlock(&bp->link_lock); 1641 return rc; 1642 } 1643 1644 static void bnxt_get_pauseparam(struct net_device *dev, 1645 struct ethtool_pauseparam *epause) 1646 { 1647 struct bnxt *bp = netdev_priv(dev); 1648 struct bnxt_link_info *link_info = &bp->link_info; 1649 1650 if (BNXT_VF(bp)) 1651 return; 1652 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 1653 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 1654 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 1655 } 1656 1657 static int bnxt_set_pauseparam(struct net_device *dev, 1658 struct ethtool_pauseparam *epause) 1659 { 1660 int rc = 0; 1661 struct bnxt *bp = netdev_priv(dev); 1662 struct bnxt_link_info *link_info = &bp->link_info; 1663 1664 if (!BNXT_PHY_CFG_ABLE(bp)) 1665 return -EOPNOTSUPP; 1666 1667 if (epause->autoneg) { 1668 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 1669 return -EINVAL; 1670 1671 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 1672 if (bp->hwrm_spec_code >= 0x10201) 1673 link_info->req_flow_ctrl = 1674 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 1675 } else { 1676 /* when transition from auto pause to force pause, 1677 * force a link change 1678 */ 1679 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1680 link_info->force_link_chng = true; 1681 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 1682 link_info->req_flow_ctrl = 0; 1683 } 1684 if (epause->rx_pause) 1685 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 1686 1687 if (epause->tx_pause) 1688 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 1689 1690 if (netif_running(dev)) 1691 rc = bnxt_hwrm_set_pause(bp); 1692 return rc; 1693 } 1694 1695 static u32 bnxt_get_link(struct net_device *dev) 1696 { 1697 struct bnxt *bp = netdev_priv(dev); 1698 1699 /* TODO: handle MF, VF, driver close case */ 1700 return bp->link_info.link_up; 1701 } 1702 1703 static void bnxt_print_admin_err(struct bnxt *bp) 1704 { 1705 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 1706 } 1707 1708 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 1709 u16 ext, u16 *index, u32 *item_length, 1710 u32 *data_length); 1711 1712 static int bnxt_flash_nvram(struct net_device *dev, 1713 u16 dir_type, 1714 u16 dir_ordinal, 1715 u16 dir_ext, 1716 u16 dir_attr, 1717 const u8 *data, 1718 size_t data_len) 1719 { 1720 struct bnxt *bp = netdev_priv(dev); 1721 int rc; 1722 struct hwrm_nvm_write_input req = {0}; 1723 dma_addr_t dma_handle; 1724 u8 *kmem; 1725 1726 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 1727 1728 req.dir_type = cpu_to_le16(dir_type); 1729 req.dir_ordinal = cpu_to_le16(dir_ordinal); 1730 req.dir_ext = cpu_to_le16(dir_ext); 1731 req.dir_attr = cpu_to_le16(dir_attr); 1732 req.dir_data_length = cpu_to_le32(data_len); 1733 1734 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 1735 GFP_KERNEL); 1736 if (!kmem) { 1737 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 1738 (unsigned)data_len); 1739 return -ENOMEM; 1740 } 1741 memcpy(kmem, data, data_len); 1742 req.host_src_addr = cpu_to_le64(dma_handle); 1743 1744 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 1745 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 1746 1747 if (rc == -EACCES) 1748 bnxt_print_admin_err(bp); 1749 return rc; 1750 } 1751 1752 static int bnxt_firmware_reset(struct net_device *dev, 1753 u16 dir_type) 1754 { 1755 struct hwrm_fw_reset_input req = {0}; 1756 struct bnxt *bp = netdev_priv(dev); 1757 int rc; 1758 1759 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 1760 1761 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 1762 /* (e.g. when firmware isn't already running) */ 1763 switch (dir_type) { 1764 case BNX_DIR_TYPE_CHIMP_PATCH: 1765 case BNX_DIR_TYPE_BOOTCODE: 1766 case BNX_DIR_TYPE_BOOTCODE_2: 1767 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 1768 /* Self-reset ChiMP upon next PCIe reset: */ 1769 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1770 break; 1771 case BNX_DIR_TYPE_APE_FW: 1772 case BNX_DIR_TYPE_APE_PATCH: 1773 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 1774 /* Self-reset APE upon next PCIe reset: */ 1775 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1776 break; 1777 case BNX_DIR_TYPE_KONG_FW: 1778 case BNX_DIR_TYPE_KONG_PATCH: 1779 req.embedded_proc_type = 1780 FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 1781 break; 1782 case BNX_DIR_TYPE_BONO_FW: 1783 case BNX_DIR_TYPE_BONO_PATCH: 1784 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 1785 break; 1786 case BNXT_FW_RESET_CHIP: 1787 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 1788 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 1789 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 1790 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 1791 break; 1792 case BNXT_FW_RESET_AP: 1793 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP; 1794 break; 1795 default: 1796 return -EINVAL; 1797 } 1798 1799 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1800 if (rc == -EACCES) 1801 bnxt_print_admin_err(bp); 1802 return rc; 1803 } 1804 1805 static int bnxt_flash_firmware(struct net_device *dev, 1806 u16 dir_type, 1807 const u8 *fw_data, 1808 size_t fw_size) 1809 { 1810 int rc = 0; 1811 u16 code_type; 1812 u32 stored_crc; 1813 u32 calculated_crc; 1814 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 1815 1816 switch (dir_type) { 1817 case BNX_DIR_TYPE_BOOTCODE: 1818 case BNX_DIR_TYPE_BOOTCODE_2: 1819 code_type = CODE_BOOT; 1820 break; 1821 case BNX_DIR_TYPE_CHIMP_PATCH: 1822 code_type = CODE_CHIMP_PATCH; 1823 break; 1824 case BNX_DIR_TYPE_APE_FW: 1825 code_type = CODE_MCTP_PASSTHRU; 1826 break; 1827 case BNX_DIR_TYPE_APE_PATCH: 1828 code_type = CODE_APE_PATCH; 1829 break; 1830 case BNX_DIR_TYPE_KONG_FW: 1831 code_type = CODE_KONG_FW; 1832 break; 1833 case BNX_DIR_TYPE_KONG_PATCH: 1834 code_type = CODE_KONG_PATCH; 1835 break; 1836 case BNX_DIR_TYPE_BONO_FW: 1837 code_type = CODE_BONO_FW; 1838 break; 1839 case BNX_DIR_TYPE_BONO_PATCH: 1840 code_type = CODE_BONO_PATCH; 1841 break; 1842 default: 1843 netdev_err(dev, "Unsupported directory entry type: %u\n", 1844 dir_type); 1845 return -EINVAL; 1846 } 1847 if (fw_size < sizeof(struct bnxt_fw_header)) { 1848 netdev_err(dev, "Invalid firmware file size: %u\n", 1849 (unsigned int)fw_size); 1850 return -EINVAL; 1851 } 1852 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 1853 netdev_err(dev, "Invalid firmware signature: %08X\n", 1854 le32_to_cpu(header->signature)); 1855 return -EINVAL; 1856 } 1857 if (header->code_type != code_type) { 1858 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 1859 code_type, header->code_type); 1860 return -EINVAL; 1861 } 1862 if (header->device != DEVICE_CUMULUS_FAMILY) { 1863 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 1864 DEVICE_CUMULUS_FAMILY, header->device); 1865 return -EINVAL; 1866 } 1867 /* Confirm the CRC32 checksum of the file: */ 1868 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 1869 sizeof(stored_crc))); 1870 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 1871 if (calculated_crc != stored_crc) { 1872 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 1873 (unsigned long)stored_crc, 1874 (unsigned long)calculated_crc); 1875 return -EINVAL; 1876 } 1877 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1878 0, 0, fw_data, fw_size); 1879 if (rc == 0) /* Firmware update successful */ 1880 rc = bnxt_firmware_reset(dev, dir_type); 1881 1882 return rc; 1883 } 1884 1885 static int bnxt_flash_microcode(struct net_device *dev, 1886 u16 dir_type, 1887 const u8 *fw_data, 1888 size_t fw_size) 1889 { 1890 struct bnxt_ucode_trailer *trailer; 1891 u32 calculated_crc; 1892 u32 stored_crc; 1893 int rc = 0; 1894 1895 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 1896 netdev_err(dev, "Invalid microcode file size: %u\n", 1897 (unsigned int)fw_size); 1898 return -EINVAL; 1899 } 1900 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 1901 sizeof(*trailer))); 1902 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 1903 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 1904 le32_to_cpu(trailer->sig)); 1905 return -EINVAL; 1906 } 1907 if (le16_to_cpu(trailer->dir_type) != dir_type) { 1908 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 1909 dir_type, le16_to_cpu(trailer->dir_type)); 1910 return -EINVAL; 1911 } 1912 if (le16_to_cpu(trailer->trailer_length) < 1913 sizeof(struct bnxt_ucode_trailer)) { 1914 netdev_err(dev, "Invalid microcode trailer length: %d\n", 1915 le16_to_cpu(trailer->trailer_length)); 1916 return -EINVAL; 1917 } 1918 1919 /* Confirm the CRC32 checksum of the file: */ 1920 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 1921 sizeof(stored_crc))); 1922 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 1923 if (calculated_crc != stored_crc) { 1924 netdev_err(dev, 1925 "CRC32 (%08lX) does not match calculated: %08lX\n", 1926 (unsigned long)stored_crc, 1927 (unsigned long)calculated_crc); 1928 return -EINVAL; 1929 } 1930 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1931 0, 0, fw_data, fw_size); 1932 1933 return rc; 1934 } 1935 1936 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 1937 { 1938 switch (dir_type) { 1939 case BNX_DIR_TYPE_CHIMP_PATCH: 1940 case BNX_DIR_TYPE_BOOTCODE: 1941 case BNX_DIR_TYPE_BOOTCODE_2: 1942 case BNX_DIR_TYPE_APE_FW: 1943 case BNX_DIR_TYPE_APE_PATCH: 1944 case BNX_DIR_TYPE_KONG_FW: 1945 case BNX_DIR_TYPE_KONG_PATCH: 1946 case BNX_DIR_TYPE_BONO_FW: 1947 case BNX_DIR_TYPE_BONO_PATCH: 1948 return true; 1949 } 1950 1951 return false; 1952 } 1953 1954 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 1955 { 1956 switch (dir_type) { 1957 case BNX_DIR_TYPE_AVS: 1958 case BNX_DIR_TYPE_EXP_ROM_MBA: 1959 case BNX_DIR_TYPE_PCIE: 1960 case BNX_DIR_TYPE_TSCF_UCODE: 1961 case BNX_DIR_TYPE_EXT_PHY: 1962 case BNX_DIR_TYPE_CCM: 1963 case BNX_DIR_TYPE_ISCSI_BOOT: 1964 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 1965 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 1966 return true; 1967 } 1968 1969 return false; 1970 } 1971 1972 static bool bnxt_dir_type_is_executable(u16 dir_type) 1973 { 1974 return bnxt_dir_type_is_ape_bin_format(dir_type) || 1975 bnxt_dir_type_is_other_exec_format(dir_type); 1976 } 1977 1978 static int bnxt_flash_firmware_from_file(struct net_device *dev, 1979 u16 dir_type, 1980 const char *filename) 1981 { 1982 const struct firmware *fw; 1983 int rc; 1984 1985 rc = request_firmware(&fw, filename, &dev->dev); 1986 if (rc != 0) { 1987 netdev_err(dev, "Error %d requesting firmware file: %s\n", 1988 rc, filename); 1989 return rc; 1990 } 1991 if (bnxt_dir_type_is_ape_bin_format(dir_type) == true) 1992 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 1993 else if (bnxt_dir_type_is_other_exec_format(dir_type) == true) 1994 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 1995 else 1996 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1997 0, 0, fw->data, fw->size); 1998 release_firmware(fw); 1999 return rc; 2000 } 2001 2002 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2003 u32 install_type) 2004 { 2005 struct bnxt *bp = netdev_priv(dev); 2006 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2007 struct hwrm_nvm_install_update_input install = {0}; 2008 const struct firmware *fw; 2009 int rc, hwrm_err = 0; 2010 u32 item_len; 2011 u16 index; 2012 2013 bnxt_hwrm_fw_set_time(bp); 2014 2015 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2016 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2017 &index, &item_len, NULL) != 0) { 2018 netdev_err(dev, "PKG update area not created in nvram\n"); 2019 return -ENOBUFS; 2020 } 2021 2022 rc = request_firmware(&fw, filename, &dev->dev); 2023 if (rc != 0) { 2024 netdev_err(dev, "PKG error %d requesting file: %s\n", 2025 rc, filename); 2026 return rc; 2027 } 2028 2029 if (fw->size > item_len) { 2030 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2031 (unsigned long)fw->size); 2032 rc = -EFBIG; 2033 } else { 2034 dma_addr_t dma_handle; 2035 u8 *kmem; 2036 struct hwrm_nvm_modify_input modify = {0}; 2037 2038 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2039 2040 modify.dir_idx = cpu_to_le16(index); 2041 modify.len = cpu_to_le32(fw->size); 2042 2043 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2044 &dma_handle, GFP_KERNEL); 2045 if (!kmem) { 2046 netdev_err(dev, 2047 "dma_alloc_coherent failure, length = %u\n", 2048 (unsigned int)fw->size); 2049 rc = -ENOMEM; 2050 } else { 2051 memcpy(kmem, fw->data, fw->size); 2052 modify.host_src_addr = cpu_to_le64(dma_handle); 2053 2054 hwrm_err = hwrm_send_message(bp, &modify, 2055 sizeof(modify), 2056 FLASH_PACKAGE_TIMEOUT); 2057 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2058 dma_handle); 2059 } 2060 } 2061 release_firmware(fw); 2062 if (rc || hwrm_err) 2063 goto err_exit; 2064 2065 if ((install_type & 0xffff) == 0) 2066 install_type >>= 16; 2067 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2068 install.install_type = cpu_to_le32(install_type); 2069 2070 mutex_lock(&bp->hwrm_cmd_lock); 2071 hwrm_err = _hwrm_send_message(bp, &install, sizeof(install), 2072 INSTALL_PACKAGE_TIMEOUT); 2073 if (hwrm_err) { 2074 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2075 2076 if (resp->error_code && error_code == 2077 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2078 install.flags |= cpu_to_le16( 2079 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2080 hwrm_err = _hwrm_send_message(bp, &install, 2081 sizeof(install), 2082 INSTALL_PACKAGE_TIMEOUT); 2083 } 2084 if (hwrm_err) 2085 goto flash_pkg_exit; 2086 } 2087 2088 if (resp->result) { 2089 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2090 (s8)resp->result, (int)resp->problem_item); 2091 rc = -ENOPKG; 2092 } 2093 flash_pkg_exit: 2094 mutex_unlock(&bp->hwrm_cmd_lock); 2095 err_exit: 2096 if (hwrm_err == -EACCES) 2097 bnxt_print_admin_err(bp); 2098 return rc; 2099 } 2100 2101 static int bnxt_flash_device(struct net_device *dev, 2102 struct ethtool_flash *flash) 2103 { 2104 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2105 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2106 return -EINVAL; 2107 } 2108 2109 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2110 flash->region > 0xffff) 2111 return bnxt_flash_package_from_file(dev, flash->data, 2112 flash->region); 2113 2114 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2115 } 2116 2117 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2118 { 2119 struct bnxt *bp = netdev_priv(dev); 2120 int rc; 2121 struct hwrm_nvm_get_dir_info_input req = {0}; 2122 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2123 2124 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2125 2126 mutex_lock(&bp->hwrm_cmd_lock); 2127 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2128 if (!rc) { 2129 *entries = le32_to_cpu(output->entries); 2130 *length = le32_to_cpu(output->entry_length); 2131 } 2132 mutex_unlock(&bp->hwrm_cmd_lock); 2133 return rc; 2134 } 2135 2136 static int bnxt_get_eeprom_len(struct net_device *dev) 2137 { 2138 struct bnxt *bp = netdev_priv(dev); 2139 2140 if (BNXT_VF(bp)) 2141 return 0; 2142 2143 /* The -1 return value allows the entire 32-bit range of offsets to be 2144 * passed via the ethtool command-line utility. 2145 */ 2146 return -1; 2147 } 2148 2149 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2150 { 2151 struct bnxt *bp = netdev_priv(dev); 2152 int rc; 2153 u32 dir_entries; 2154 u32 entry_length; 2155 u8 *buf; 2156 size_t buflen; 2157 dma_addr_t dma_handle; 2158 struct hwrm_nvm_get_dir_entries_input req = {0}; 2159 2160 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2161 if (rc != 0) 2162 return rc; 2163 2164 /* Insert 2 bytes of directory info (count and size of entries) */ 2165 if (len < 2) 2166 return -EINVAL; 2167 2168 *data++ = dir_entries; 2169 *data++ = entry_length; 2170 len -= 2; 2171 memset(data, 0xff, len); 2172 2173 buflen = dir_entries * entry_length; 2174 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2175 GFP_KERNEL); 2176 if (!buf) { 2177 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2178 (unsigned)buflen); 2179 return -ENOMEM; 2180 } 2181 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2182 req.host_dest_addr = cpu_to_le64(dma_handle); 2183 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2184 if (rc == 0) 2185 memcpy(data, buf, len > buflen ? buflen : len); 2186 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2187 return rc; 2188 } 2189 2190 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2191 u32 length, u8 *data) 2192 { 2193 struct bnxt *bp = netdev_priv(dev); 2194 int rc; 2195 u8 *buf; 2196 dma_addr_t dma_handle; 2197 struct hwrm_nvm_read_input req = {0}; 2198 2199 if (!length) 2200 return -EINVAL; 2201 2202 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2203 GFP_KERNEL); 2204 if (!buf) { 2205 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2206 (unsigned)length); 2207 return -ENOMEM; 2208 } 2209 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2210 req.host_dest_addr = cpu_to_le64(dma_handle); 2211 req.dir_idx = cpu_to_le16(index); 2212 req.offset = cpu_to_le32(offset); 2213 req.len = cpu_to_le32(length); 2214 2215 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2216 if (rc == 0) 2217 memcpy(data, buf, length); 2218 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2219 return rc; 2220 } 2221 2222 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2223 u16 ext, u16 *index, u32 *item_length, 2224 u32 *data_length) 2225 { 2226 struct bnxt *bp = netdev_priv(dev); 2227 int rc; 2228 struct hwrm_nvm_find_dir_entry_input req = {0}; 2229 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2230 2231 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2232 req.enables = 0; 2233 req.dir_idx = 0; 2234 req.dir_type = cpu_to_le16(type); 2235 req.dir_ordinal = cpu_to_le16(ordinal); 2236 req.dir_ext = cpu_to_le16(ext); 2237 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2238 mutex_lock(&bp->hwrm_cmd_lock); 2239 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2240 if (rc == 0) { 2241 if (index) 2242 *index = le16_to_cpu(output->dir_idx); 2243 if (item_length) 2244 *item_length = le32_to_cpu(output->dir_item_length); 2245 if (data_length) 2246 *data_length = le32_to_cpu(output->dir_data_length); 2247 } 2248 mutex_unlock(&bp->hwrm_cmd_lock); 2249 return rc; 2250 } 2251 2252 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2253 { 2254 char *retval = NULL; 2255 char *p; 2256 char *value; 2257 int field = 0; 2258 2259 if (datalen < 1) 2260 return NULL; 2261 /* null-terminate the log data (removing last '\n'): */ 2262 data[datalen - 1] = 0; 2263 for (p = data; *p != 0; p++) { 2264 field = 0; 2265 retval = NULL; 2266 while (*p != 0 && *p != '\n') { 2267 value = p; 2268 while (*p != 0 && *p != '\t' && *p != '\n') 2269 p++; 2270 if (field == desired_field) 2271 retval = value; 2272 if (*p != '\t') 2273 break; 2274 *p = 0; 2275 field++; 2276 p++; 2277 } 2278 if (*p == 0) 2279 break; 2280 *p = 0; 2281 } 2282 return retval; 2283 } 2284 2285 static void bnxt_get_pkgver(struct net_device *dev) 2286 { 2287 struct bnxt *bp = netdev_priv(dev); 2288 u16 index = 0; 2289 char *pkgver; 2290 u32 pkglen; 2291 u8 *pkgbuf; 2292 int len; 2293 2294 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2295 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2296 &index, NULL, &pkglen) != 0) 2297 return; 2298 2299 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2300 if (!pkgbuf) { 2301 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2302 pkglen); 2303 return; 2304 } 2305 2306 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2307 goto err; 2308 2309 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2310 pkglen); 2311 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2312 len = strlen(bp->fw_ver_str); 2313 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2314 "/pkg %s", pkgver); 2315 } 2316 err: 2317 kfree(pkgbuf); 2318 } 2319 2320 static int bnxt_get_eeprom(struct net_device *dev, 2321 struct ethtool_eeprom *eeprom, 2322 u8 *data) 2323 { 2324 u32 index; 2325 u32 offset; 2326 2327 if (eeprom->offset == 0) /* special offset value to get directory */ 2328 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2329 2330 index = eeprom->offset >> 24; 2331 offset = eeprom->offset & 0xffffff; 2332 2333 if (index == 0) { 2334 netdev_err(dev, "unsupported index value: %d\n", index); 2335 return -EINVAL; 2336 } 2337 2338 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2339 } 2340 2341 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2342 { 2343 struct bnxt *bp = netdev_priv(dev); 2344 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2345 2346 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2347 req.dir_idx = cpu_to_le16(index); 2348 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2349 } 2350 2351 static int bnxt_set_eeprom(struct net_device *dev, 2352 struct ethtool_eeprom *eeprom, 2353 u8 *data) 2354 { 2355 struct bnxt *bp = netdev_priv(dev); 2356 u8 index, dir_op; 2357 u16 type, ext, ordinal, attr; 2358 2359 if (!BNXT_PF(bp)) { 2360 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2361 return -EINVAL; 2362 } 2363 2364 type = eeprom->magic >> 16; 2365 2366 if (type == 0xffff) { /* special value for directory operations */ 2367 index = eeprom->magic & 0xff; 2368 dir_op = eeprom->magic >> 8; 2369 if (index == 0) 2370 return -EINVAL; 2371 switch (dir_op) { 2372 case 0x0e: /* erase */ 2373 if (eeprom->offset != ~eeprom->magic) 2374 return -EINVAL; 2375 return bnxt_erase_nvram_directory(dev, index - 1); 2376 default: 2377 return -EINVAL; 2378 } 2379 } 2380 2381 /* Create or re-write an NVM item: */ 2382 if (bnxt_dir_type_is_executable(type) == true) 2383 return -EOPNOTSUPP; 2384 ext = eeprom->magic & 0xffff; 2385 ordinal = eeprom->offset >> 16; 2386 attr = eeprom->offset & 0xffff; 2387 2388 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2389 eeprom->len); 2390 } 2391 2392 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2393 { 2394 struct bnxt *bp = netdev_priv(dev); 2395 struct ethtool_eee *eee = &bp->eee; 2396 struct bnxt_link_info *link_info = &bp->link_info; 2397 u32 advertising = 2398 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2399 int rc = 0; 2400 2401 if (!BNXT_PHY_CFG_ABLE(bp)) 2402 return -EOPNOTSUPP; 2403 2404 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2405 return -EOPNOTSUPP; 2406 2407 if (!edata->eee_enabled) 2408 goto eee_ok; 2409 2410 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2411 netdev_warn(dev, "EEE requires autoneg\n"); 2412 return -EINVAL; 2413 } 2414 if (edata->tx_lpi_enabled) { 2415 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2416 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2417 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2418 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2419 return -EINVAL; 2420 } else if (!bp->lpi_tmr_hi) { 2421 edata->tx_lpi_timer = eee->tx_lpi_timer; 2422 } 2423 } 2424 if (!edata->advertised) { 2425 edata->advertised = advertising & eee->supported; 2426 } else if (edata->advertised & ~advertising) { 2427 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2428 edata->advertised, advertising); 2429 return -EINVAL; 2430 } 2431 2432 eee->advertised = edata->advertised; 2433 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2434 eee->tx_lpi_timer = edata->tx_lpi_timer; 2435 eee_ok: 2436 eee->eee_enabled = edata->eee_enabled; 2437 2438 if (netif_running(dev)) 2439 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2440 2441 return rc; 2442 } 2443 2444 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2445 { 2446 struct bnxt *bp = netdev_priv(dev); 2447 2448 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2449 return -EOPNOTSUPP; 2450 2451 *edata = bp->eee; 2452 if (!bp->eee.eee_enabled) { 2453 /* Preserve tx_lpi_timer so that the last value will be used 2454 * by default when it is re-enabled. 2455 */ 2456 edata->advertised = 0; 2457 edata->tx_lpi_enabled = 0; 2458 } 2459 2460 if (!bp->eee.eee_active) 2461 edata->lp_advertised = 0; 2462 2463 return 0; 2464 } 2465 2466 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2467 u16 page_number, u16 start_addr, 2468 u16 data_length, u8 *buf) 2469 { 2470 struct hwrm_port_phy_i2c_read_input req = {0}; 2471 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2472 int rc, byte_offset = 0; 2473 2474 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2475 req.i2c_slave_addr = i2c_addr; 2476 req.page_number = cpu_to_le16(page_number); 2477 req.port_id = cpu_to_le16(bp->pf.port_id); 2478 do { 2479 u16 xfer_size; 2480 2481 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2482 data_length -= xfer_size; 2483 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2484 req.data_length = xfer_size; 2485 req.enables = cpu_to_le32(start_addr + byte_offset ? 2486 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2487 mutex_lock(&bp->hwrm_cmd_lock); 2488 rc = _hwrm_send_message(bp, &req, sizeof(req), 2489 HWRM_CMD_TIMEOUT); 2490 if (!rc) 2491 memcpy(buf + byte_offset, output->data, xfer_size); 2492 mutex_unlock(&bp->hwrm_cmd_lock); 2493 byte_offset += xfer_size; 2494 } while (!rc && data_length > 0); 2495 2496 return rc; 2497 } 2498 2499 static int bnxt_get_module_info(struct net_device *dev, 2500 struct ethtool_modinfo *modinfo) 2501 { 2502 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2503 struct bnxt *bp = netdev_priv(dev); 2504 int rc; 2505 2506 /* No point in going further if phy status indicates 2507 * module is not inserted or if it is powered down or 2508 * if it is of type 10GBase-T 2509 */ 2510 if (bp->link_info.module_status > 2511 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2512 return -EOPNOTSUPP; 2513 2514 /* This feature is not supported in older firmware versions */ 2515 if (bp->hwrm_spec_code < 0x10202) 2516 return -EOPNOTSUPP; 2517 2518 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2519 SFF_DIAG_SUPPORT_OFFSET + 1, 2520 data); 2521 if (!rc) { 2522 u8 module_id = data[0]; 2523 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2524 2525 switch (module_id) { 2526 case SFF_MODULE_ID_SFP: 2527 modinfo->type = ETH_MODULE_SFF_8472; 2528 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2529 if (!diag_supported) 2530 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2531 break; 2532 case SFF_MODULE_ID_QSFP: 2533 case SFF_MODULE_ID_QSFP_PLUS: 2534 modinfo->type = ETH_MODULE_SFF_8436; 2535 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2536 break; 2537 case SFF_MODULE_ID_QSFP28: 2538 modinfo->type = ETH_MODULE_SFF_8636; 2539 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2540 break; 2541 default: 2542 rc = -EOPNOTSUPP; 2543 break; 2544 } 2545 } 2546 return rc; 2547 } 2548 2549 static int bnxt_get_module_eeprom(struct net_device *dev, 2550 struct ethtool_eeprom *eeprom, 2551 u8 *data) 2552 { 2553 struct bnxt *bp = netdev_priv(dev); 2554 u16 start = eeprom->offset, length = eeprom->len; 2555 int rc = 0; 2556 2557 memset(data, 0, eeprom->len); 2558 2559 /* Read A0 portion of the EEPROM */ 2560 if (start < ETH_MODULE_SFF_8436_LEN) { 2561 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 2562 length = ETH_MODULE_SFF_8436_LEN - start; 2563 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 2564 start, length, data); 2565 if (rc) 2566 return rc; 2567 start += length; 2568 data += length; 2569 length = eeprom->len - length; 2570 } 2571 2572 /* Read A2 portion of the EEPROM */ 2573 if (length) { 2574 start -= ETH_MODULE_SFF_8436_LEN; 2575 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, 2576 start, length, data); 2577 } 2578 return rc; 2579 } 2580 2581 static int bnxt_nway_reset(struct net_device *dev) 2582 { 2583 int rc = 0; 2584 2585 struct bnxt *bp = netdev_priv(dev); 2586 struct bnxt_link_info *link_info = &bp->link_info; 2587 2588 if (!BNXT_PHY_CFG_ABLE(bp)) 2589 return -EOPNOTSUPP; 2590 2591 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 2592 return -EINVAL; 2593 2594 if (netif_running(dev)) 2595 rc = bnxt_hwrm_set_link_setting(bp, true, false); 2596 2597 return rc; 2598 } 2599 2600 static int bnxt_set_phys_id(struct net_device *dev, 2601 enum ethtool_phys_id_state state) 2602 { 2603 struct hwrm_port_led_cfg_input req = {0}; 2604 struct bnxt *bp = netdev_priv(dev); 2605 struct bnxt_pf_info *pf = &bp->pf; 2606 struct bnxt_led_cfg *led_cfg; 2607 u8 led_state; 2608 __le16 duration; 2609 int i; 2610 2611 if (!bp->num_leds || BNXT_VF(bp)) 2612 return -EOPNOTSUPP; 2613 2614 if (state == ETHTOOL_ID_ACTIVE) { 2615 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 2616 duration = cpu_to_le16(500); 2617 } else if (state == ETHTOOL_ID_INACTIVE) { 2618 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 2619 duration = cpu_to_le16(0); 2620 } else { 2621 return -EINVAL; 2622 } 2623 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 2624 req.port_id = cpu_to_le16(pf->port_id); 2625 req.num_leds = bp->num_leds; 2626 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 2627 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 2628 req.enables |= BNXT_LED_DFLT_ENABLES(i); 2629 led_cfg->led_id = bp->leds[i].led_id; 2630 led_cfg->led_state = led_state; 2631 led_cfg->led_blink_on = duration; 2632 led_cfg->led_blink_off = duration; 2633 led_cfg->led_group_id = bp->leds[i].led_group_id; 2634 } 2635 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2636 } 2637 2638 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 2639 { 2640 struct hwrm_selftest_irq_input req = {0}; 2641 2642 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 2643 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2644 } 2645 2646 static int bnxt_test_irq(struct bnxt *bp) 2647 { 2648 int i; 2649 2650 for (i = 0; i < bp->cp_nr_rings; i++) { 2651 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 2652 int rc; 2653 2654 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 2655 if (rc) 2656 return rc; 2657 } 2658 return 0; 2659 } 2660 2661 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 2662 { 2663 struct hwrm_port_mac_cfg_input req = {0}; 2664 2665 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 2666 2667 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 2668 if (enable) 2669 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 2670 else 2671 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 2672 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2673 } 2674 2675 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 2676 { 2677 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 2678 struct hwrm_port_phy_qcaps_input req = {0}; 2679 int rc; 2680 2681 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 2682 mutex_lock(&bp->hwrm_cmd_lock); 2683 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2684 if (!rc) 2685 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 2686 2687 mutex_unlock(&bp->hwrm_cmd_lock); 2688 return rc; 2689 } 2690 2691 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 2692 struct hwrm_port_phy_cfg_input *req) 2693 { 2694 struct bnxt_link_info *link_info = &bp->link_info; 2695 u16 fw_advertising; 2696 u16 fw_speed; 2697 int rc; 2698 2699 if (!link_info->autoneg || 2700 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK)) 2701 return 0; 2702 2703 rc = bnxt_query_force_speeds(bp, &fw_advertising); 2704 if (rc) 2705 return rc; 2706 2707 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2708 if (bp->link_info.link_up) 2709 fw_speed = bp->link_info.link_speed; 2710 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 2711 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2712 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 2713 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2714 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 2715 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2716 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 2717 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2718 2719 req->force_link_speed = cpu_to_le16(fw_speed); 2720 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 2721 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2722 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 2723 req->flags = 0; 2724 req->force_link_speed = cpu_to_le16(0); 2725 return rc; 2726 } 2727 2728 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 2729 { 2730 struct hwrm_port_phy_cfg_input req = {0}; 2731 2732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 2733 2734 if (enable) { 2735 bnxt_disable_an_for_lpbk(bp, &req); 2736 if (ext) 2737 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 2738 else 2739 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 2740 } else { 2741 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 2742 } 2743 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 2744 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2745 } 2746 2747 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2748 u32 raw_cons, int pkt_size) 2749 { 2750 struct bnxt_napi *bnapi = cpr->bnapi; 2751 struct bnxt_rx_ring_info *rxr; 2752 struct bnxt_sw_rx_bd *rx_buf; 2753 struct rx_cmp *rxcmp; 2754 u16 cp_cons, cons; 2755 u8 *data; 2756 u32 len; 2757 int i; 2758 2759 rxr = bnapi->rx_ring; 2760 cp_cons = RING_CMP(raw_cons); 2761 rxcmp = (struct rx_cmp *) 2762 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2763 cons = rxcmp->rx_cmp_opaque; 2764 rx_buf = &rxr->rx_buf_ring[cons]; 2765 data = rx_buf->data_ptr; 2766 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 2767 if (len != pkt_size) 2768 return -EIO; 2769 i = ETH_ALEN; 2770 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 2771 return -EIO; 2772 i += ETH_ALEN; 2773 for ( ; i < pkt_size; i++) { 2774 if (data[i] != (u8)(i & 0xff)) 2775 return -EIO; 2776 } 2777 return 0; 2778 } 2779 2780 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2781 int pkt_size) 2782 { 2783 struct tx_cmp *txcmp; 2784 int rc = -EIO; 2785 u32 raw_cons; 2786 u32 cons; 2787 int i; 2788 2789 raw_cons = cpr->cp_raw_cons; 2790 for (i = 0; i < 200; i++) { 2791 cons = RING_CMP(raw_cons); 2792 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2793 2794 if (!TX_CMP_VALID(txcmp, raw_cons)) { 2795 udelay(5); 2796 continue; 2797 } 2798 2799 /* The valid test of the entry must be done first before 2800 * reading any further. 2801 */ 2802 dma_rmb(); 2803 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 2804 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 2805 raw_cons = NEXT_RAW_CMP(raw_cons); 2806 raw_cons = NEXT_RAW_CMP(raw_cons); 2807 break; 2808 } 2809 raw_cons = NEXT_RAW_CMP(raw_cons); 2810 } 2811 cpr->cp_raw_cons = raw_cons; 2812 return rc; 2813 } 2814 2815 static int bnxt_run_loopback(struct bnxt *bp) 2816 { 2817 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 2818 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 2819 struct bnxt_cp_ring_info *cpr; 2820 int pkt_size, i = 0; 2821 struct sk_buff *skb; 2822 dma_addr_t map; 2823 u8 *data; 2824 int rc; 2825 2826 cpr = &rxr->bnapi->cp_ring; 2827 if (bp->flags & BNXT_FLAG_CHIP_P5) 2828 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 2829 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 2830 skb = netdev_alloc_skb(bp->dev, pkt_size); 2831 if (!skb) 2832 return -ENOMEM; 2833 data = skb_put(skb, pkt_size); 2834 eth_broadcast_addr(data); 2835 i += ETH_ALEN; 2836 ether_addr_copy(&data[i], bp->dev->dev_addr); 2837 i += ETH_ALEN; 2838 for ( ; i < pkt_size; i++) 2839 data[i] = (u8)(i & 0xff); 2840 2841 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 2842 PCI_DMA_TODEVICE); 2843 if (dma_mapping_error(&bp->pdev->dev, map)) { 2844 dev_kfree_skb(skb); 2845 return -EIO; 2846 } 2847 bnxt_xmit_bd(bp, txr, map, pkt_size); 2848 2849 /* Sync BD data before updating doorbell */ 2850 wmb(); 2851 2852 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 2853 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 2854 2855 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 2856 dev_kfree_skb(skb); 2857 return rc; 2858 } 2859 2860 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 2861 { 2862 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 2863 struct hwrm_selftest_exec_input req = {0}; 2864 int rc; 2865 2866 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 2867 mutex_lock(&bp->hwrm_cmd_lock); 2868 resp->test_success = 0; 2869 req.flags = test_mask; 2870 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 2871 *test_results = resp->test_success; 2872 mutex_unlock(&bp->hwrm_cmd_lock); 2873 return rc; 2874 } 2875 2876 #define BNXT_DRV_TESTS 4 2877 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 2878 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 2879 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 2880 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 2881 2882 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 2883 u64 *buf) 2884 { 2885 struct bnxt *bp = netdev_priv(dev); 2886 bool do_ext_lpbk = false; 2887 bool offline = false; 2888 u8 test_results = 0; 2889 u8 test_mask = 0; 2890 int rc = 0, i; 2891 2892 if (!bp->num_tests || !BNXT_SINGLE_PF(bp)) 2893 return; 2894 memset(buf, 0, sizeof(u64) * bp->num_tests); 2895 if (!netif_running(dev)) { 2896 etest->flags |= ETH_TEST_FL_FAILED; 2897 return; 2898 } 2899 2900 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 2901 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 2902 do_ext_lpbk = true; 2903 2904 if (etest->flags & ETH_TEST_FL_OFFLINE) { 2905 if (bp->pf.active_vfs) { 2906 etest->flags |= ETH_TEST_FL_FAILED; 2907 netdev_warn(dev, "Offline tests cannot be run with active VFs\n"); 2908 return; 2909 } 2910 offline = true; 2911 } 2912 2913 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 2914 u8 bit_val = 1 << i; 2915 2916 if (!(bp->test_info->offline_mask & bit_val)) 2917 test_mask |= bit_val; 2918 else if (offline) 2919 test_mask |= bit_val; 2920 } 2921 if (!offline) { 2922 bnxt_run_fw_tests(bp, test_mask, &test_results); 2923 } else { 2924 rc = bnxt_close_nic(bp, false, false); 2925 if (rc) 2926 return; 2927 bnxt_run_fw_tests(bp, test_mask, &test_results); 2928 2929 buf[BNXT_MACLPBK_TEST_IDX] = 1; 2930 bnxt_hwrm_mac_loopback(bp, true); 2931 msleep(250); 2932 rc = bnxt_half_open_nic(bp); 2933 if (rc) { 2934 bnxt_hwrm_mac_loopback(bp, false); 2935 etest->flags |= ETH_TEST_FL_FAILED; 2936 return; 2937 } 2938 if (bnxt_run_loopback(bp)) 2939 etest->flags |= ETH_TEST_FL_FAILED; 2940 else 2941 buf[BNXT_MACLPBK_TEST_IDX] = 0; 2942 2943 bnxt_hwrm_mac_loopback(bp, false); 2944 bnxt_hwrm_phy_loopback(bp, true, false); 2945 msleep(1000); 2946 if (bnxt_run_loopback(bp)) { 2947 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 2948 etest->flags |= ETH_TEST_FL_FAILED; 2949 } 2950 if (do_ext_lpbk) { 2951 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 2952 bnxt_hwrm_phy_loopback(bp, true, true); 2953 msleep(1000); 2954 if (bnxt_run_loopback(bp)) { 2955 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 2956 etest->flags |= ETH_TEST_FL_FAILED; 2957 } 2958 } 2959 bnxt_hwrm_phy_loopback(bp, false, false); 2960 bnxt_half_close_nic(bp); 2961 rc = bnxt_open_nic(bp, false, true); 2962 } 2963 if (rc || bnxt_test_irq(bp)) { 2964 buf[BNXT_IRQ_TEST_IDX] = 1; 2965 etest->flags |= ETH_TEST_FL_FAILED; 2966 } 2967 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 2968 u8 bit_val = 1 << i; 2969 2970 if ((test_mask & bit_val) && !(test_results & bit_val)) { 2971 buf[i] = 1; 2972 etest->flags |= ETH_TEST_FL_FAILED; 2973 } 2974 } 2975 } 2976 2977 static int bnxt_reset(struct net_device *dev, u32 *flags) 2978 { 2979 struct bnxt *bp = netdev_priv(dev); 2980 int rc = 0; 2981 2982 if (!BNXT_PF(bp)) { 2983 netdev_err(dev, "Reset is not supported from a VF\n"); 2984 return -EOPNOTSUPP; 2985 } 2986 2987 if (pci_vfs_assigned(bp->pdev) && 2988 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 2989 netdev_err(dev, 2990 "Reset not allowed when VFs are assigned to VMs\n"); 2991 return -EBUSY; 2992 } 2993 2994 if (*flags == ETH_RESET_ALL) { 2995 /* This feature is not supported in older firmware versions */ 2996 if (bp->hwrm_spec_code < 0x10803) 2997 return -EOPNOTSUPP; 2998 2999 rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_CHIP); 3000 if (!rc) { 3001 netdev_info(dev, "Reset request successful.\n"); 3002 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3003 netdev_info(dev, "Reload driver to complete reset\n"); 3004 *flags = 0; 3005 } 3006 } else if (*flags == ETH_RESET_AP) { 3007 /* This feature is not supported in older firmware versions */ 3008 if (bp->hwrm_spec_code < 0x10803) 3009 return -EOPNOTSUPP; 3010 3011 rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_AP); 3012 if (!rc) { 3013 netdev_info(dev, "Reset Application Processor request successful.\n"); 3014 *flags = 0; 3015 } 3016 } else { 3017 rc = -EINVAL; 3018 } 3019 3020 return rc; 3021 } 3022 3023 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3024 struct bnxt_hwrm_dbg_dma_info *info) 3025 { 3026 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3027 struct hwrm_dbg_cmn_input *cmn_req = msg; 3028 __le16 *seq_ptr = msg + info->seq_off; 3029 u16 seq = 0, len, segs_off; 3030 void *resp = cmn_resp; 3031 dma_addr_t dma_handle; 3032 int rc, off = 0; 3033 void *dma_buf; 3034 3035 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3036 GFP_KERNEL); 3037 if (!dma_buf) 3038 return -ENOMEM; 3039 3040 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3041 total_segments); 3042 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3043 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3044 mutex_lock(&bp->hwrm_cmd_lock); 3045 while (1) { 3046 *seq_ptr = cpu_to_le16(seq); 3047 rc = _hwrm_send_message(bp, msg, msg_len, 3048 HWRM_COREDUMP_TIMEOUT); 3049 if (rc) 3050 break; 3051 3052 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3053 if (!seq && 3054 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3055 info->segs = le16_to_cpu(*((__le16 *)(resp + 3056 segs_off))); 3057 if (!info->segs) { 3058 rc = -EIO; 3059 break; 3060 } 3061 3062 info->dest_buf_size = info->segs * 3063 sizeof(struct coredump_segment_record); 3064 info->dest_buf = kmalloc(info->dest_buf_size, 3065 GFP_KERNEL); 3066 if (!info->dest_buf) { 3067 rc = -ENOMEM; 3068 break; 3069 } 3070 } 3071 3072 if (info->dest_buf) { 3073 if ((info->seg_start + off + len) <= 3074 BNXT_COREDUMP_BUF_LEN(info->buf_len)) { 3075 memcpy(info->dest_buf + off, dma_buf, len); 3076 } else { 3077 rc = -ENOBUFS; 3078 break; 3079 } 3080 } 3081 3082 if (cmn_req->req_type == 3083 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3084 info->dest_buf_size += len; 3085 3086 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3087 break; 3088 3089 seq++; 3090 off += len; 3091 } 3092 mutex_unlock(&bp->hwrm_cmd_lock); 3093 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3094 return rc; 3095 } 3096 3097 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3098 struct bnxt_coredump *coredump) 3099 { 3100 struct hwrm_dbg_coredump_list_input req = {0}; 3101 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3102 int rc; 3103 3104 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3105 3106 info.dma_len = COREDUMP_LIST_BUF_LEN; 3107 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3108 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3109 data_len); 3110 3111 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3112 if (!rc) { 3113 coredump->data = info.dest_buf; 3114 coredump->data_size = info.dest_buf_size; 3115 coredump->total_segs = info.segs; 3116 } 3117 return rc; 3118 } 3119 3120 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3121 u16 segment_id) 3122 { 3123 struct hwrm_dbg_coredump_initiate_input req = {0}; 3124 3125 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3126 req.component_id = cpu_to_le16(component_id); 3127 req.segment_id = cpu_to_le16(segment_id); 3128 3129 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3130 } 3131 3132 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3133 u16 segment_id, u32 *seg_len, 3134 void *buf, u32 buf_len, u32 offset) 3135 { 3136 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3137 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3138 int rc; 3139 3140 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3141 req.component_id = cpu_to_le16(component_id); 3142 req.segment_id = cpu_to_le16(segment_id); 3143 3144 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3145 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3146 seq_no); 3147 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3148 data_len); 3149 if (buf) { 3150 info.dest_buf = buf + offset; 3151 info.buf_len = buf_len; 3152 info.seg_start = offset; 3153 } 3154 3155 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3156 if (!rc) 3157 *seg_len = info.dest_buf_size; 3158 3159 return rc; 3160 } 3161 3162 static void 3163 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3164 struct bnxt_coredump_segment_hdr *seg_hdr, 3165 struct coredump_segment_record *seg_rec, u32 seg_len, 3166 int status, u32 duration, u32 instance) 3167 { 3168 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3169 memcpy(seg_hdr->signature, "sEgM", 4); 3170 if (seg_rec) { 3171 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3172 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3173 seg_hdr->low_version = seg_rec->version_low; 3174 seg_hdr->high_version = seg_rec->version_hi; 3175 } else { 3176 /* For hwrm_ver_get response Component id = 2 3177 * and Segment id = 0 3178 */ 3179 seg_hdr->component_id = cpu_to_le32(2); 3180 seg_hdr->segment_id = 0; 3181 } 3182 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3183 seg_hdr->length = cpu_to_le32(seg_len); 3184 seg_hdr->status = cpu_to_le32(status); 3185 seg_hdr->duration = cpu_to_le32(duration); 3186 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3187 seg_hdr->instance = cpu_to_le32(instance); 3188 } 3189 3190 static void 3191 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3192 time64_t start, s16 start_utc, u16 total_segs, 3193 int status) 3194 { 3195 time64_t end = ktime_get_real_seconds(); 3196 u32 os_ver_major = 0, os_ver_minor = 0; 3197 struct tm tm; 3198 3199 time64_to_tm(start, 0, &tm); 3200 memset(record, 0, sizeof(*record)); 3201 memcpy(record->signature, "cOrE", 4); 3202 record->flags = 0; 3203 record->low_version = 0; 3204 record->high_version = 1; 3205 record->asic_state = 0; 3206 strlcpy(record->system_name, utsname()->nodename, 3207 sizeof(record->system_name)); 3208 record->year = cpu_to_le16(tm.tm_year + 1900); 3209 record->month = cpu_to_le16(tm.tm_mon + 1); 3210 record->day = cpu_to_le16(tm.tm_mday); 3211 record->hour = cpu_to_le16(tm.tm_hour); 3212 record->minute = cpu_to_le16(tm.tm_min); 3213 record->second = cpu_to_le16(tm.tm_sec); 3214 record->utc_bias = cpu_to_le16(start_utc); 3215 strcpy(record->commandline, "ethtool -w"); 3216 record->total_segments = cpu_to_le32(total_segs); 3217 3218 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3219 record->os_ver_major = cpu_to_le32(os_ver_major); 3220 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3221 3222 strlcpy(record->os_name, utsname()->sysname, 32); 3223 time64_to_tm(end, 0, &tm); 3224 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3225 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3226 record->end_day = cpu_to_le16(tm.tm_mday); 3227 record->end_hour = cpu_to_le16(tm.tm_hour); 3228 record->end_minute = cpu_to_le16(tm.tm_min); 3229 record->end_second = cpu_to_le16(tm.tm_sec); 3230 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3231 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3232 bp->ver_resp.chip_rev << 8 | 3233 bp->ver_resp.chip_metal); 3234 record->asic_id2 = 0; 3235 record->coredump_status = cpu_to_le32(status); 3236 record->ioctl_low_version = 0; 3237 record->ioctl_high_version = 0; 3238 } 3239 3240 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3241 { 3242 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3243 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0; 3244 struct coredump_segment_record *seg_record = NULL; 3245 struct bnxt_coredump_segment_hdr seg_hdr; 3246 struct bnxt_coredump coredump = {NULL}; 3247 time64_t start_time; 3248 u16 start_utc; 3249 int rc = 0, i; 3250 3251 if (buf) 3252 buf_len = *dump_len; 3253 3254 start_time = ktime_get_real_seconds(); 3255 start_utc = sys_tz.tz_minuteswest * 60; 3256 seg_hdr_len = sizeof(seg_hdr); 3257 3258 /* First segment should be hwrm_ver_get response */ 3259 *dump_len = seg_hdr_len + ver_get_resp_len; 3260 if (buf) { 3261 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3262 0, 0, 0); 3263 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3264 offset += seg_hdr_len; 3265 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3266 offset += ver_get_resp_len; 3267 } 3268 3269 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3270 if (rc) { 3271 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3272 goto err; 3273 } 3274 3275 *dump_len += seg_hdr_len * coredump.total_segs; 3276 3277 seg_record = (struct coredump_segment_record *)coredump.data; 3278 seg_record_len = sizeof(*seg_record); 3279 3280 for (i = 0; i < coredump.total_segs; i++) { 3281 u16 comp_id = le16_to_cpu(seg_record->component_id); 3282 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3283 u32 duration = 0, seg_len = 0; 3284 unsigned long start, end; 3285 3286 if (buf && ((offset + seg_hdr_len) > 3287 BNXT_COREDUMP_BUF_LEN(buf_len))) { 3288 rc = -ENOBUFS; 3289 goto err; 3290 } 3291 3292 start = jiffies; 3293 3294 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3295 if (rc) { 3296 netdev_err(bp->dev, 3297 "Failed to initiate coredump for seg = %d\n", 3298 seg_record->segment_id); 3299 goto next_seg; 3300 } 3301 3302 /* Write segment data into the buffer */ 3303 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3304 &seg_len, buf, buf_len, 3305 offset + seg_hdr_len); 3306 if (rc && rc == -ENOBUFS) 3307 goto err; 3308 else if (rc) 3309 netdev_err(bp->dev, 3310 "Failed to retrieve coredump for seg = %d\n", 3311 seg_record->segment_id); 3312 3313 next_seg: 3314 end = jiffies; 3315 duration = jiffies_to_msecs(end - start); 3316 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3317 rc, duration, 0); 3318 3319 if (buf) { 3320 /* Write segment header into the buffer */ 3321 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3322 offset += seg_hdr_len + seg_len; 3323 } 3324 3325 *dump_len += seg_len; 3326 seg_record = 3327 (struct coredump_segment_record *)((u8 *)seg_record + 3328 seg_record_len); 3329 } 3330 3331 err: 3332 if (buf) 3333 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3334 start_utc, coredump.total_segs + 1, 3335 rc); 3336 kfree(coredump.data); 3337 *dump_len += sizeof(struct bnxt_coredump_record); 3338 if (rc == -ENOBUFS) 3339 netdev_err(bp->dev, "Firmware returned large coredump buffer\n"); 3340 return rc; 3341 } 3342 3343 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3344 { 3345 struct bnxt *bp = netdev_priv(dev); 3346 3347 if (dump->flag > BNXT_DUMP_CRASH) { 3348 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3349 return -EINVAL; 3350 } 3351 3352 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3353 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3354 return -EOPNOTSUPP; 3355 } 3356 3357 bp->dump_flag = dump->flag; 3358 return 0; 3359 } 3360 3361 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3362 { 3363 struct bnxt *bp = netdev_priv(dev); 3364 3365 if (bp->hwrm_spec_code < 0x10801) 3366 return -EOPNOTSUPP; 3367 3368 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3369 bp->ver_resp.hwrm_fw_min_8b << 16 | 3370 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3371 bp->ver_resp.hwrm_fw_rsvd_8b; 3372 3373 dump->flag = bp->dump_flag; 3374 if (bp->dump_flag == BNXT_DUMP_CRASH) 3375 dump->len = BNXT_CRASH_DUMP_LEN; 3376 else 3377 bnxt_get_coredump(bp, NULL, &dump->len); 3378 return 0; 3379 } 3380 3381 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3382 void *buf) 3383 { 3384 struct bnxt *bp = netdev_priv(dev); 3385 3386 if (bp->hwrm_spec_code < 0x10801) 3387 return -EOPNOTSUPP; 3388 3389 memset(buf, 0, dump->len); 3390 3391 dump->flag = bp->dump_flag; 3392 if (dump->flag == BNXT_DUMP_CRASH) { 3393 #ifdef CONFIG_TEE_BNXT_FW 3394 return tee_bnxt_copy_coredump(buf, 0, dump->len); 3395 #endif 3396 } else { 3397 return bnxt_get_coredump(bp, buf, &dump->len); 3398 } 3399 3400 return 0; 3401 } 3402 3403 void bnxt_ethtool_init(struct bnxt *bp) 3404 { 3405 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3406 struct hwrm_selftest_qlist_input req = {0}; 3407 struct bnxt_test_info *test_info; 3408 struct net_device *dev = bp->dev; 3409 int i, rc; 3410 3411 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3412 bnxt_get_pkgver(dev); 3413 3414 bp->num_tests = 0; 3415 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp)) 3416 return; 3417 3418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3419 mutex_lock(&bp->hwrm_cmd_lock); 3420 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3421 if (rc) 3422 goto ethtool_init_exit; 3423 3424 test_info = bp->test_info; 3425 if (!test_info) 3426 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3427 if (!test_info) 3428 goto ethtool_init_exit; 3429 3430 bp->test_info = test_info; 3431 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3432 if (bp->num_tests > BNXT_MAX_TEST) 3433 bp->num_tests = BNXT_MAX_TEST; 3434 3435 test_info->offline_mask = resp->offline_tests; 3436 test_info->timeout = le16_to_cpu(resp->test_timeout); 3437 if (!test_info->timeout) 3438 test_info->timeout = HWRM_CMD_TIMEOUT; 3439 for (i = 0; i < bp->num_tests; i++) { 3440 char *str = test_info->string[i]; 3441 char *fw_str = resp->test0_name + i * 32; 3442 3443 if (i == BNXT_MACLPBK_TEST_IDX) { 3444 strcpy(str, "Mac loopback test (offline)"); 3445 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3446 strcpy(str, "Phy loopback test (offline)"); 3447 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3448 strcpy(str, "Ext loopback test (offline)"); 3449 } else if (i == BNXT_IRQ_TEST_IDX) { 3450 strcpy(str, "Interrupt_test (offline)"); 3451 } else { 3452 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3453 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3454 if (test_info->offline_mask & (1 << i)) 3455 strncat(str, " (offline)", 3456 ETH_GSTRING_LEN - strlen(str)); 3457 else 3458 strncat(str, " (online)", 3459 ETH_GSTRING_LEN - strlen(str)); 3460 } 3461 } 3462 3463 ethtool_init_exit: 3464 mutex_unlock(&bp->hwrm_cmd_lock); 3465 } 3466 3467 void bnxt_ethtool_free(struct bnxt *bp) 3468 { 3469 kfree(bp->test_info); 3470 bp->test_info = NULL; 3471 } 3472 3473 const struct ethtool_ops bnxt_ethtool_ops = { 3474 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3475 ETHTOOL_COALESCE_MAX_FRAMES | 3476 ETHTOOL_COALESCE_USECS_IRQ | 3477 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3478 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3479 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3480 .get_link_ksettings = bnxt_get_link_ksettings, 3481 .set_link_ksettings = bnxt_set_link_ksettings, 3482 .get_pauseparam = bnxt_get_pauseparam, 3483 .set_pauseparam = bnxt_set_pauseparam, 3484 .get_drvinfo = bnxt_get_drvinfo, 3485 .get_wol = bnxt_get_wol, 3486 .set_wol = bnxt_set_wol, 3487 .get_coalesce = bnxt_get_coalesce, 3488 .set_coalesce = bnxt_set_coalesce, 3489 .get_msglevel = bnxt_get_msglevel, 3490 .set_msglevel = bnxt_set_msglevel, 3491 .get_sset_count = bnxt_get_sset_count, 3492 .get_strings = bnxt_get_strings, 3493 .get_ethtool_stats = bnxt_get_ethtool_stats, 3494 .set_ringparam = bnxt_set_ringparam, 3495 .get_ringparam = bnxt_get_ringparam, 3496 .get_channels = bnxt_get_channels, 3497 .set_channels = bnxt_set_channels, 3498 .get_rxnfc = bnxt_get_rxnfc, 3499 .set_rxnfc = bnxt_set_rxnfc, 3500 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3501 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3502 .get_rxfh = bnxt_get_rxfh, 3503 .flash_device = bnxt_flash_device, 3504 .get_eeprom_len = bnxt_get_eeprom_len, 3505 .get_eeprom = bnxt_get_eeprom, 3506 .set_eeprom = bnxt_set_eeprom, 3507 .get_link = bnxt_get_link, 3508 .get_eee = bnxt_get_eee, 3509 .set_eee = bnxt_set_eee, 3510 .get_module_info = bnxt_get_module_info, 3511 .get_module_eeprom = bnxt_get_module_eeprom, 3512 .nway_reset = bnxt_nway_reset, 3513 .set_phys_id = bnxt_set_phys_id, 3514 .self_test = bnxt_self_test, 3515 .reset = bnxt_reset, 3516 .set_dump = bnxt_set_dump, 3517 .get_dump_flag = bnxt_get_dump_flag, 3518 .get_dump_data = bnxt_get_dump_data, 3519 }; 3520