1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/linkmode.h> 15 #include <linux/interrupt.h> 16 #include <linux/pci.h> 17 #include <linux/etherdevice.h> 18 #include <linux/crc32.h> 19 #include <linux/firmware.h> 20 #include <linux/utsname.h> 21 #include <linux/time.h> 22 #include <linux/ptp_clock_kernel.h> 23 #include <linux/net_tstamp.h> 24 #include <linux/timecounter.h> 25 #include "bnxt_hsi.h" 26 #include "bnxt.h" 27 #include "bnxt_hwrm.h" 28 #include "bnxt_xdp.h" 29 #include "bnxt_ptp.h" 30 #include "bnxt_ethtool.h" 31 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 32 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 33 #include "bnxt_coredump.h" 34 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 35 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 36 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 37 38 static u32 bnxt_get_msglevel(struct net_device *dev) 39 { 40 struct bnxt *bp = netdev_priv(dev); 41 42 return bp->msg_enable; 43 } 44 45 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 46 { 47 struct bnxt *bp = netdev_priv(dev); 48 49 bp->msg_enable = value; 50 } 51 52 static int bnxt_get_coalesce(struct net_device *dev, 53 struct ethtool_coalesce *coal, 54 struct kernel_ethtool_coalesce *kernel_coal, 55 struct netlink_ext_ack *extack) 56 { 57 struct bnxt *bp = netdev_priv(dev); 58 struct bnxt_coal *hw_coal; 59 u16 mult; 60 61 memset(coal, 0, sizeof(*coal)); 62 63 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 64 65 hw_coal = &bp->rx_coal; 66 mult = hw_coal->bufs_per_record; 67 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 68 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 69 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 70 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 71 72 hw_coal = &bp->tx_coal; 73 mult = hw_coal->bufs_per_record; 74 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 75 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 76 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 77 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 78 79 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 80 81 return 0; 82 } 83 84 static int bnxt_set_coalesce(struct net_device *dev, 85 struct ethtool_coalesce *coal, 86 struct kernel_ethtool_coalesce *kernel_coal, 87 struct netlink_ext_ack *extack) 88 { 89 struct bnxt *bp = netdev_priv(dev); 90 bool update_stats = false; 91 struct bnxt_coal *hw_coal; 92 int rc = 0; 93 u16 mult; 94 95 if (coal->use_adaptive_rx_coalesce) { 96 bp->flags |= BNXT_FLAG_DIM; 97 } else { 98 if (bp->flags & BNXT_FLAG_DIM) { 99 bp->flags &= ~(BNXT_FLAG_DIM); 100 goto reset_coalesce; 101 } 102 } 103 104 hw_coal = &bp->rx_coal; 105 mult = hw_coal->bufs_per_record; 106 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 107 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 108 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 109 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 110 111 hw_coal = &bp->tx_coal; 112 mult = hw_coal->bufs_per_record; 113 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 114 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 115 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 116 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 117 118 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 119 u32 stats_ticks = coal->stats_block_coalesce_usecs; 120 121 /* Allow 0, which means disable. */ 122 if (stats_ticks) 123 stats_ticks = clamp_t(u32, stats_ticks, 124 BNXT_MIN_STATS_COAL_TICKS, 125 BNXT_MAX_STATS_COAL_TICKS); 126 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 127 bp->stats_coal_ticks = stats_ticks; 128 if (bp->stats_coal_ticks) 129 bp->current_interval = 130 bp->stats_coal_ticks * HZ / 1000000; 131 else 132 bp->current_interval = BNXT_TIMER_INTERVAL; 133 update_stats = true; 134 } 135 136 reset_coalesce: 137 if (netif_running(dev)) { 138 if (update_stats) { 139 rc = bnxt_close_nic(bp, true, false); 140 if (!rc) 141 rc = bnxt_open_nic(bp, true, false); 142 } else { 143 rc = bnxt_hwrm_set_coal(bp); 144 } 145 } 146 147 return rc; 148 } 149 150 static const char * const bnxt_ring_rx_stats_str[] = { 151 "rx_ucast_packets", 152 "rx_mcast_packets", 153 "rx_bcast_packets", 154 "rx_discards", 155 "rx_errors", 156 "rx_ucast_bytes", 157 "rx_mcast_bytes", 158 "rx_bcast_bytes", 159 }; 160 161 static const char * const bnxt_ring_tx_stats_str[] = { 162 "tx_ucast_packets", 163 "tx_mcast_packets", 164 "tx_bcast_packets", 165 "tx_errors", 166 "tx_discards", 167 "tx_ucast_bytes", 168 "tx_mcast_bytes", 169 "tx_bcast_bytes", 170 }; 171 172 static const char * const bnxt_ring_tpa_stats_str[] = { 173 "tpa_packets", 174 "tpa_bytes", 175 "tpa_events", 176 "tpa_aborts", 177 }; 178 179 static const char * const bnxt_ring_tpa2_stats_str[] = { 180 "rx_tpa_eligible_pkt", 181 "rx_tpa_eligible_bytes", 182 "rx_tpa_pkt", 183 "rx_tpa_bytes", 184 "rx_tpa_errors", 185 "rx_tpa_events", 186 }; 187 188 static const char * const bnxt_rx_sw_stats_str[] = { 189 "rx_l4_csum_errors", 190 "rx_resets", 191 "rx_buf_errors", 192 }; 193 194 static const char * const bnxt_cmn_sw_stats_str[] = { 195 "missed_irqs", 196 }; 197 198 #define BNXT_RX_STATS_ENTRY(counter) \ 199 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 200 201 #define BNXT_TX_STATS_ENTRY(counter) \ 202 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 203 204 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 205 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 206 207 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 208 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 209 210 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 211 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 212 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 213 214 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 215 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 216 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 217 218 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 219 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 220 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 221 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 222 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 223 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 224 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 225 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 226 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 227 228 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 229 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 230 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 231 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 232 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 233 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 234 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 235 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 236 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 237 238 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 239 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 240 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 241 242 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 243 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 244 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 245 246 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 247 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 248 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 249 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 250 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 251 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 252 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 253 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 254 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 255 256 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 257 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 258 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 259 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 260 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 261 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 262 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 263 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 264 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 265 266 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 267 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 269 270 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 271 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 272 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 273 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 274 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 275 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 276 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 277 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 278 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 279 280 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 281 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 282 __stringify(counter##_pri##n) } 283 284 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 285 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 286 __stringify(counter##_pri##n) } 287 288 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 289 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 290 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 291 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 292 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 293 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 294 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 295 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 296 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 297 298 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 299 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 300 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 301 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 302 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 303 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 304 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 305 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 306 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 307 308 enum { 309 RX_TOTAL_DISCARDS, 310 TX_TOTAL_DISCARDS, 311 RX_NETPOLL_DISCARDS, 312 }; 313 314 static struct { 315 u64 counter; 316 char string[ETH_GSTRING_LEN]; 317 } bnxt_sw_func_stats[] = { 318 {0, "rx_total_discard_pkts"}, 319 {0, "tx_total_discard_pkts"}, 320 {0, "rx_total_netpoll_discards"}, 321 }; 322 323 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 324 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 325 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 326 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 327 328 static const struct { 329 long offset; 330 char string[ETH_GSTRING_LEN]; 331 } bnxt_port_stats_arr[] = { 332 BNXT_RX_STATS_ENTRY(rx_64b_frames), 333 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 334 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 335 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 336 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 337 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 338 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 339 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 340 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 341 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 342 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 343 BNXT_RX_STATS_ENTRY(rx_total_frames), 344 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 345 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 346 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 347 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 348 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 349 BNXT_RX_STATS_ENTRY(rx_pause_frames), 350 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 351 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 352 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 353 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 354 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 355 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 356 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 357 BNXT_RX_STATS_ENTRY(rx_good_frames), 358 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 359 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 360 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 361 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 362 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 363 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 364 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 365 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 366 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 367 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 368 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 369 BNXT_RX_STATS_ENTRY(rx_bytes), 370 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 371 BNXT_RX_STATS_ENTRY(rx_runt_frames), 372 BNXT_RX_STATS_ENTRY(rx_stat_discard), 373 BNXT_RX_STATS_ENTRY(rx_stat_err), 374 375 BNXT_TX_STATS_ENTRY(tx_64b_frames), 376 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 377 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 378 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 379 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 380 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 381 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 382 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 383 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 384 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 385 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 386 BNXT_TX_STATS_ENTRY(tx_good_frames), 387 BNXT_TX_STATS_ENTRY(tx_total_frames), 388 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 389 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 390 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 391 BNXT_TX_STATS_ENTRY(tx_pause_frames), 392 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 393 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 394 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 395 BNXT_TX_STATS_ENTRY(tx_err), 396 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 397 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 398 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 399 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 400 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 401 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 402 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 403 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 404 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 405 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 406 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 407 BNXT_TX_STATS_ENTRY(tx_total_collisions), 408 BNXT_TX_STATS_ENTRY(tx_bytes), 409 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 410 BNXT_TX_STATS_ENTRY(tx_stat_discard), 411 BNXT_TX_STATS_ENTRY(tx_stat_error), 412 }; 413 414 static const struct { 415 long offset; 416 char string[ETH_GSTRING_LEN]; 417 } bnxt_port_stats_ext_arr[] = { 418 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 419 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 420 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 421 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 422 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 423 BNXT_RX_STATS_EXT_COS_ENTRIES, 424 BNXT_RX_STATS_EXT_PFC_ENTRIES, 425 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 426 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 427 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 428 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 429 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 430 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 431 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 432 }; 433 434 static const struct { 435 long offset; 436 char string[ETH_GSTRING_LEN]; 437 } bnxt_tx_port_stats_ext_arr[] = { 438 BNXT_TX_STATS_EXT_COS_ENTRIES, 439 BNXT_TX_STATS_EXT_PFC_ENTRIES, 440 }; 441 442 static const struct { 443 long base_off; 444 char string[ETH_GSTRING_LEN]; 445 } bnxt_rx_bytes_pri_arr[] = { 446 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 447 }; 448 449 static const struct { 450 long base_off; 451 char string[ETH_GSTRING_LEN]; 452 } bnxt_rx_pkts_pri_arr[] = { 453 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 454 }; 455 456 static const struct { 457 long base_off; 458 char string[ETH_GSTRING_LEN]; 459 } bnxt_tx_bytes_pri_arr[] = { 460 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 461 }; 462 463 static const struct { 464 long base_off; 465 char string[ETH_GSTRING_LEN]; 466 } bnxt_tx_pkts_pri_arr[] = { 467 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 468 }; 469 470 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 471 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 472 #define BNXT_NUM_STATS_PRI \ 473 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 474 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 475 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 476 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 477 478 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 479 { 480 if (BNXT_SUPPORTS_TPA(bp)) { 481 if (bp->max_tpa_v2) { 482 if (BNXT_CHIP_P5_THOR(bp)) 483 return BNXT_NUM_TPA_RING_STATS_P5; 484 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 485 } 486 return BNXT_NUM_TPA_RING_STATS; 487 } 488 return 0; 489 } 490 491 static int bnxt_get_num_ring_stats(struct bnxt *bp) 492 { 493 int rx, tx, cmn; 494 495 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 496 bnxt_get_num_tpa_ring_stats(bp); 497 tx = NUM_RING_TX_HW_STATS; 498 cmn = NUM_RING_CMN_SW_STATS; 499 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 500 cmn * bp->cp_nr_rings; 501 } 502 503 static int bnxt_get_num_stats(struct bnxt *bp) 504 { 505 int num_stats = bnxt_get_num_ring_stats(bp); 506 507 num_stats += BNXT_NUM_SW_FUNC_STATS; 508 509 if (bp->flags & BNXT_FLAG_PORT_STATS) 510 num_stats += BNXT_NUM_PORT_STATS; 511 512 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 513 num_stats += bp->fw_rx_stats_ext_size + 514 bp->fw_tx_stats_ext_size; 515 if (bp->pri2cos_valid) 516 num_stats += BNXT_NUM_STATS_PRI; 517 } 518 519 return num_stats; 520 } 521 522 static int bnxt_get_sset_count(struct net_device *dev, int sset) 523 { 524 struct bnxt *bp = netdev_priv(dev); 525 526 switch (sset) { 527 case ETH_SS_STATS: 528 return bnxt_get_num_stats(bp); 529 case ETH_SS_TEST: 530 if (!bp->num_tests) 531 return -EOPNOTSUPP; 532 return bp->num_tests; 533 default: 534 return -EOPNOTSUPP; 535 } 536 } 537 538 static bool is_rx_ring(struct bnxt *bp, int ring_num) 539 { 540 return ring_num < bp->rx_nr_rings; 541 } 542 543 static bool is_tx_ring(struct bnxt *bp, int ring_num) 544 { 545 int tx_base = 0; 546 547 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 548 tx_base = bp->rx_nr_rings; 549 550 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 551 return true; 552 return false; 553 } 554 555 static void bnxt_get_ethtool_stats(struct net_device *dev, 556 struct ethtool_stats *stats, u64 *buf) 557 { 558 u32 i, j = 0; 559 struct bnxt *bp = netdev_priv(dev); 560 u32 tpa_stats; 561 562 if (!bp->bnapi) { 563 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 564 goto skip_ring_stats; 565 } 566 567 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 568 bnxt_sw_func_stats[i].counter = 0; 569 570 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 571 for (i = 0; i < bp->cp_nr_rings; i++) { 572 struct bnxt_napi *bnapi = bp->bnapi[i]; 573 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 574 u64 *sw_stats = cpr->stats.sw_stats; 575 u64 *sw; 576 int k; 577 578 if (is_rx_ring(bp, i)) { 579 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 580 buf[j] = sw_stats[k]; 581 } 582 if (is_tx_ring(bp, i)) { 583 k = NUM_RING_RX_HW_STATS; 584 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 585 j++, k++) 586 buf[j] = sw_stats[k]; 587 } 588 if (!tpa_stats || !is_rx_ring(bp, i)) 589 goto skip_tpa_ring_stats; 590 591 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 592 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 593 tpa_stats; j++, k++) 594 buf[j] = sw_stats[k]; 595 596 skip_tpa_ring_stats: 597 sw = (u64 *)&cpr->sw_stats.rx; 598 if (is_rx_ring(bp, i)) { 599 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 600 buf[j] = sw[k]; 601 } 602 603 sw = (u64 *)&cpr->sw_stats.cmn; 604 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 605 buf[j] = sw[k]; 606 607 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 608 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts); 609 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 610 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts); 611 bnxt_sw_func_stats[RX_NETPOLL_DISCARDS].counter += 612 cpr->sw_stats.rx.rx_netpoll_discards; 613 } 614 615 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 616 buf[j] = bnxt_sw_func_stats[i].counter; 617 618 skip_ring_stats: 619 if (bp->flags & BNXT_FLAG_PORT_STATS) { 620 u64 *port_stats = bp->port_stats.sw_stats; 621 622 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 623 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 624 } 625 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 626 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 627 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 628 629 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 630 buf[j] = *(rx_port_stats_ext + 631 bnxt_port_stats_ext_arr[i].offset); 632 } 633 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 634 buf[j] = *(tx_port_stats_ext + 635 bnxt_tx_port_stats_ext_arr[i].offset); 636 } 637 if (bp->pri2cos_valid) { 638 for (i = 0; i < 8; i++, j++) { 639 long n = bnxt_rx_bytes_pri_arr[i].base_off + 640 bp->pri2cos_idx[i]; 641 642 buf[j] = *(rx_port_stats_ext + n); 643 } 644 for (i = 0; i < 8; i++, j++) { 645 long n = bnxt_rx_pkts_pri_arr[i].base_off + 646 bp->pri2cos_idx[i]; 647 648 buf[j] = *(rx_port_stats_ext + n); 649 } 650 for (i = 0; i < 8; i++, j++) { 651 long n = bnxt_tx_bytes_pri_arr[i].base_off + 652 bp->pri2cos_idx[i]; 653 654 buf[j] = *(tx_port_stats_ext + n); 655 } 656 for (i = 0; i < 8; i++, j++) { 657 long n = bnxt_tx_pkts_pri_arr[i].base_off + 658 bp->pri2cos_idx[i]; 659 660 buf[j] = *(tx_port_stats_ext + n); 661 } 662 } 663 } 664 } 665 666 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 667 { 668 struct bnxt *bp = netdev_priv(dev); 669 static const char * const *str; 670 u32 i, j, num_str; 671 672 switch (stringset) { 673 case ETH_SS_STATS: 674 for (i = 0; i < bp->cp_nr_rings; i++) { 675 if (is_rx_ring(bp, i)) { 676 num_str = NUM_RING_RX_HW_STATS; 677 for (j = 0; j < num_str; j++) { 678 sprintf(buf, "[%d]: %s", i, 679 bnxt_ring_rx_stats_str[j]); 680 buf += ETH_GSTRING_LEN; 681 } 682 } 683 if (is_tx_ring(bp, i)) { 684 num_str = NUM_RING_TX_HW_STATS; 685 for (j = 0; j < num_str; j++) { 686 sprintf(buf, "[%d]: %s", i, 687 bnxt_ring_tx_stats_str[j]); 688 buf += ETH_GSTRING_LEN; 689 } 690 } 691 num_str = bnxt_get_num_tpa_ring_stats(bp); 692 if (!num_str || !is_rx_ring(bp, i)) 693 goto skip_tpa_stats; 694 695 if (bp->max_tpa_v2) 696 str = bnxt_ring_tpa2_stats_str; 697 else 698 str = bnxt_ring_tpa_stats_str; 699 700 for (j = 0; j < num_str; j++) { 701 sprintf(buf, "[%d]: %s", i, str[j]); 702 buf += ETH_GSTRING_LEN; 703 } 704 skip_tpa_stats: 705 if (is_rx_ring(bp, i)) { 706 num_str = NUM_RING_RX_SW_STATS; 707 for (j = 0; j < num_str; j++) { 708 sprintf(buf, "[%d]: %s", i, 709 bnxt_rx_sw_stats_str[j]); 710 buf += ETH_GSTRING_LEN; 711 } 712 } 713 num_str = NUM_RING_CMN_SW_STATS; 714 for (j = 0; j < num_str; j++) { 715 sprintf(buf, "[%d]: %s", i, 716 bnxt_cmn_sw_stats_str[j]); 717 buf += ETH_GSTRING_LEN; 718 } 719 } 720 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 721 strcpy(buf, bnxt_sw_func_stats[i].string); 722 buf += ETH_GSTRING_LEN; 723 } 724 725 if (bp->flags & BNXT_FLAG_PORT_STATS) { 726 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 727 strcpy(buf, bnxt_port_stats_arr[i].string); 728 buf += ETH_GSTRING_LEN; 729 } 730 } 731 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 732 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 733 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 734 buf += ETH_GSTRING_LEN; 735 } 736 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 737 strcpy(buf, 738 bnxt_tx_port_stats_ext_arr[i].string); 739 buf += ETH_GSTRING_LEN; 740 } 741 if (bp->pri2cos_valid) { 742 for (i = 0; i < 8; i++) { 743 strcpy(buf, 744 bnxt_rx_bytes_pri_arr[i].string); 745 buf += ETH_GSTRING_LEN; 746 } 747 for (i = 0; i < 8; i++) { 748 strcpy(buf, 749 bnxt_rx_pkts_pri_arr[i].string); 750 buf += ETH_GSTRING_LEN; 751 } 752 for (i = 0; i < 8; i++) { 753 strcpy(buf, 754 bnxt_tx_bytes_pri_arr[i].string); 755 buf += ETH_GSTRING_LEN; 756 } 757 for (i = 0; i < 8; i++) { 758 strcpy(buf, 759 bnxt_tx_pkts_pri_arr[i].string); 760 buf += ETH_GSTRING_LEN; 761 } 762 } 763 } 764 break; 765 case ETH_SS_TEST: 766 if (bp->num_tests) 767 memcpy(buf, bp->test_info->string, 768 bp->num_tests * ETH_GSTRING_LEN); 769 break; 770 default: 771 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 772 stringset); 773 break; 774 } 775 } 776 777 static void bnxt_get_ringparam(struct net_device *dev, 778 struct ethtool_ringparam *ering) 779 { 780 struct bnxt *bp = netdev_priv(dev); 781 782 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 783 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 784 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 785 } else { 786 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 787 ering->rx_jumbo_max_pending = 0; 788 } 789 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 790 791 ering->rx_pending = bp->rx_ring_size; 792 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 793 ering->tx_pending = bp->tx_ring_size; 794 } 795 796 static int bnxt_set_ringparam(struct net_device *dev, 797 struct ethtool_ringparam *ering) 798 { 799 struct bnxt *bp = netdev_priv(dev); 800 801 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 802 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 803 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 804 return -EINVAL; 805 806 if (netif_running(dev)) 807 bnxt_close_nic(bp, false, false); 808 809 bp->rx_ring_size = ering->rx_pending; 810 bp->tx_ring_size = ering->tx_pending; 811 bnxt_set_ring_params(bp); 812 813 if (netif_running(dev)) 814 return bnxt_open_nic(bp, false, false); 815 816 return 0; 817 } 818 819 static void bnxt_get_channels(struct net_device *dev, 820 struct ethtool_channels *channel) 821 { 822 struct bnxt *bp = netdev_priv(dev); 823 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 824 int max_rx_rings, max_tx_rings, tcs; 825 int max_tx_sch_inputs, tx_grps; 826 827 /* Get the most up-to-date max_tx_sch_inputs. */ 828 if (netif_running(dev) && BNXT_NEW_RM(bp)) 829 bnxt_hwrm_func_resc_qcaps(bp, false); 830 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 831 832 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 833 if (max_tx_sch_inputs) 834 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 835 836 tcs = netdev_get_num_tc(dev); 837 tx_grps = max(tcs, 1); 838 if (bp->tx_nr_rings_xdp) 839 tx_grps++; 840 max_tx_rings /= tx_grps; 841 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 842 843 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 844 max_rx_rings = 0; 845 max_tx_rings = 0; 846 } 847 if (max_tx_sch_inputs) 848 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 849 850 if (tcs > 1) 851 max_tx_rings /= tcs; 852 853 channel->max_rx = max_rx_rings; 854 channel->max_tx = max_tx_rings; 855 channel->max_other = 0; 856 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 857 channel->combined_count = bp->rx_nr_rings; 858 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 859 channel->combined_count--; 860 } else { 861 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 862 channel->rx_count = bp->rx_nr_rings; 863 channel->tx_count = bp->tx_nr_rings_per_tc; 864 } 865 } 866 } 867 868 static int bnxt_set_channels(struct net_device *dev, 869 struct ethtool_channels *channel) 870 { 871 struct bnxt *bp = netdev_priv(dev); 872 int req_tx_rings, req_rx_rings, tcs; 873 bool sh = false; 874 int tx_xdp = 0; 875 int rc = 0; 876 877 if (channel->other_count) 878 return -EINVAL; 879 880 if (!channel->combined_count && 881 (!channel->rx_count || !channel->tx_count)) 882 return -EINVAL; 883 884 if (channel->combined_count && 885 (channel->rx_count || channel->tx_count)) 886 return -EINVAL; 887 888 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 889 channel->tx_count)) 890 return -EINVAL; 891 892 if (channel->combined_count) 893 sh = true; 894 895 tcs = netdev_get_num_tc(dev); 896 897 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 898 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 899 if (bp->tx_nr_rings_xdp) { 900 if (!sh) { 901 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 902 return -EINVAL; 903 } 904 tx_xdp = req_rx_rings; 905 } 906 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 907 if (rc) { 908 netdev_warn(dev, "Unable to allocate the requested rings\n"); 909 return rc; 910 } 911 912 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 913 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 914 netif_is_rxfh_configured(dev)) { 915 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 916 return -EINVAL; 917 } 918 919 if (netif_running(dev)) { 920 if (BNXT_PF(bp)) { 921 /* TODO CHIMP_FW: Send message to all VF's 922 * before PF unload 923 */ 924 } 925 rc = bnxt_close_nic(bp, true, false); 926 if (rc) { 927 netdev_err(bp->dev, "Set channel failure rc :%x\n", 928 rc); 929 return rc; 930 } 931 } 932 933 if (sh) { 934 bp->flags |= BNXT_FLAG_SHARED_RINGS; 935 bp->rx_nr_rings = channel->combined_count; 936 bp->tx_nr_rings_per_tc = channel->combined_count; 937 } else { 938 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 939 bp->rx_nr_rings = channel->rx_count; 940 bp->tx_nr_rings_per_tc = channel->tx_count; 941 } 942 bp->tx_nr_rings_xdp = tx_xdp; 943 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 944 if (tcs > 1) 945 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 946 947 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 948 bp->tx_nr_rings + bp->rx_nr_rings; 949 950 /* After changing number of rx channels, update NTUPLE feature. */ 951 netdev_update_features(dev); 952 if (netif_running(dev)) { 953 rc = bnxt_open_nic(bp, true, false); 954 if ((!rc) && BNXT_PF(bp)) { 955 /* TODO CHIMP_FW: Send message to all VF's 956 * to renable 957 */ 958 } 959 } else { 960 rc = bnxt_reserve_rings(bp, true); 961 } 962 963 return rc; 964 } 965 966 #ifdef CONFIG_RFS_ACCEL 967 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 968 u32 *rule_locs) 969 { 970 int i, j = 0; 971 972 cmd->data = bp->ntp_fltr_count; 973 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 974 struct hlist_head *head; 975 struct bnxt_ntuple_filter *fltr; 976 977 head = &bp->ntp_fltr_hash_tbl[i]; 978 rcu_read_lock(); 979 hlist_for_each_entry_rcu(fltr, head, hash) { 980 if (j == cmd->rule_cnt) 981 break; 982 rule_locs[j++] = fltr->sw_id; 983 } 984 rcu_read_unlock(); 985 if (j == cmd->rule_cnt) 986 break; 987 } 988 cmd->rule_cnt = j; 989 return 0; 990 } 991 992 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 993 { 994 struct ethtool_rx_flow_spec *fs = 995 (struct ethtool_rx_flow_spec *)&cmd->fs; 996 struct bnxt_ntuple_filter *fltr; 997 struct flow_keys *fkeys; 998 int i, rc = -EINVAL; 999 1000 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1001 return rc; 1002 1003 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1004 struct hlist_head *head; 1005 1006 head = &bp->ntp_fltr_hash_tbl[i]; 1007 rcu_read_lock(); 1008 hlist_for_each_entry_rcu(fltr, head, hash) { 1009 if (fltr->sw_id == fs->location) 1010 goto fltr_found; 1011 } 1012 rcu_read_unlock(); 1013 } 1014 return rc; 1015 1016 fltr_found: 1017 fkeys = &fltr->fkeys; 1018 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1019 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1020 fs->flow_type = TCP_V4_FLOW; 1021 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1022 fs->flow_type = UDP_V4_FLOW; 1023 else 1024 goto fltr_err; 1025 1026 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1027 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1028 1029 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1030 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1031 1032 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1033 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1034 1035 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1036 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1037 } else { 1038 int i; 1039 1040 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1041 fs->flow_type = TCP_V6_FLOW; 1042 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1043 fs->flow_type = UDP_V6_FLOW; 1044 else 1045 goto fltr_err; 1046 1047 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1048 fkeys->addrs.v6addrs.src; 1049 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1050 fkeys->addrs.v6addrs.dst; 1051 for (i = 0; i < 4; i++) { 1052 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1053 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1054 } 1055 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1056 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1057 1058 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1059 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1060 } 1061 1062 fs->ring_cookie = fltr->rxq; 1063 rc = 0; 1064 1065 fltr_err: 1066 rcu_read_unlock(); 1067 1068 return rc; 1069 } 1070 #endif 1071 1072 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1073 { 1074 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1075 return RXH_IP_SRC | RXH_IP_DST; 1076 return 0; 1077 } 1078 1079 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1080 { 1081 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1082 return RXH_IP_SRC | RXH_IP_DST; 1083 return 0; 1084 } 1085 1086 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1087 { 1088 cmd->data = 0; 1089 switch (cmd->flow_type) { 1090 case TCP_V4_FLOW: 1091 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1092 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1093 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1094 cmd->data |= get_ethtool_ipv4_rss(bp); 1095 break; 1096 case UDP_V4_FLOW: 1097 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1098 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1099 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1100 fallthrough; 1101 case SCTP_V4_FLOW: 1102 case AH_ESP_V4_FLOW: 1103 case AH_V4_FLOW: 1104 case ESP_V4_FLOW: 1105 case IPV4_FLOW: 1106 cmd->data |= get_ethtool_ipv4_rss(bp); 1107 break; 1108 1109 case TCP_V6_FLOW: 1110 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1111 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1112 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1113 cmd->data |= get_ethtool_ipv6_rss(bp); 1114 break; 1115 case UDP_V6_FLOW: 1116 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1117 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1118 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1119 fallthrough; 1120 case SCTP_V6_FLOW: 1121 case AH_ESP_V6_FLOW: 1122 case AH_V6_FLOW: 1123 case ESP_V6_FLOW: 1124 case IPV6_FLOW: 1125 cmd->data |= get_ethtool_ipv6_rss(bp); 1126 break; 1127 } 1128 return 0; 1129 } 1130 1131 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1132 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1133 1134 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1135 { 1136 u32 rss_hash_cfg = bp->rss_hash_cfg; 1137 int tuple, rc = 0; 1138 1139 if (cmd->data == RXH_4TUPLE) 1140 tuple = 4; 1141 else if (cmd->data == RXH_2TUPLE) 1142 tuple = 2; 1143 else if (!cmd->data) 1144 tuple = 0; 1145 else 1146 return -EINVAL; 1147 1148 if (cmd->flow_type == TCP_V4_FLOW) { 1149 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1150 if (tuple == 4) 1151 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1152 } else if (cmd->flow_type == UDP_V4_FLOW) { 1153 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1154 return -EINVAL; 1155 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1156 if (tuple == 4) 1157 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1158 } else if (cmd->flow_type == TCP_V6_FLOW) { 1159 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1160 if (tuple == 4) 1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1162 } else if (cmd->flow_type == UDP_V6_FLOW) { 1163 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1164 return -EINVAL; 1165 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1166 if (tuple == 4) 1167 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1168 } else if (tuple == 4) { 1169 return -EINVAL; 1170 } 1171 1172 switch (cmd->flow_type) { 1173 case TCP_V4_FLOW: 1174 case UDP_V4_FLOW: 1175 case SCTP_V4_FLOW: 1176 case AH_ESP_V4_FLOW: 1177 case AH_V4_FLOW: 1178 case ESP_V4_FLOW: 1179 case IPV4_FLOW: 1180 if (tuple == 2) 1181 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1182 else if (!tuple) 1183 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1184 break; 1185 1186 case TCP_V6_FLOW: 1187 case UDP_V6_FLOW: 1188 case SCTP_V6_FLOW: 1189 case AH_ESP_V6_FLOW: 1190 case AH_V6_FLOW: 1191 case ESP_V6_FLOW: 1192 case IPV6_FLOW: 1193 if (tuple == 2) 1194 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1195 else if (!tuple) 1196 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1197 break; 1198 } 1199 1200 if (bp->rss_hash_cfg == rss_hash_cfg) 1201 return 0; 1202 1203 bp->rss_hash_cfg = rss_hash_cfg; 1204 if (netif_running(bp->dev)) { 1205 bnxt_close_nic(bp, false, false); 1206 rc = bnxt_open_nic(bp, false, false); 1207 } 1208 return rc; 1209 } 1210 1211 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1212 u32 *rule_locs) 1213 { 1214 struct bnxt *bp = netdev_priv(dev); 1215 int rc = 0; 1216 1217 switch (cmd->cmd) { 1218 #ifdef CONFIG_RFS_ACCEL 1219 case ETHTOOL_GRXRINGS: 1220 cmd->data = bp->rx_nr_rings; 1221 break; 1222 1223 case ETHTOOL_GRXCLSRLCNT: 1224 cmd->rule_cnt = bp->ntp_fltr_count; 1225 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1226 break; 1227 1228 case ETHTOOL_GRXCLSRLALL: 1229 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1230 break; 1231 1232 case ETHTOOL_GRXCLSRULE: 1233 rc = bnxt_grxclsrule(bp, cmd); 1234 break; 1235 #endif 1236 1237 case ETHTOOL_GRXFH: 1238 rc = bnxt_grxfh(bp, cmd); 1239 break; 1240 1241 default: 1242 rc = -EOPNOTSUPP; 1243 break; 1244 } 1245 1246 return rc; 1247 } 1248 1249 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1250 { 1251 struct bnxt *bp = netdev_priv(dev); 1252 int rc; 1253 1254 switch (cmd->cmd) { 1255 case ETHTOOL_SRXFH: 1256 rc = bnxt_srxfh(bp, cmd); 1257 break; 1258 1259 default: 1260 rc = -EOPNOTSUPP; 1261 break; 1262 } 1263 return rc; 1264 } 1265 1266 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1267 { 1268 struct bnxt *bp = netdev_priv(dev); 1269 1270 if (bp->flags & BNXT_FLAG_CHIP_P5) 1271 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1272 return HW_HASH_INDEX_SIZE; 1273 } 1274 1275 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1276 { 1277 return HW_HASH_KEY_SIZE; 1278 } 1279 1280 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1281 u8 *hfunc) 1282 { 1283 struct bnxt *bp = netdev_priv(dev); 1284 struct bnxt_vnic_info *vnic; 1285 u32 i, tbl_size; 1286 1287 if (hfunc) 1288 *hfunc = ETH_RSS_HASH_TOP; 1289 1290 if (!bp->vnic_info) 1291 return 0; 1292 1293 vnic = &bp->vnic_info[0]; 1294 if (indir && bp->rss_indir_tbl) { 1295 tbl_size = bnxt_get_rxfh_indir_size(dev); 1296 for (i = 0; i < tbl_size; i++) 1297 indir[i] = bp->rss_indir_tbl[i]; 1298 } 1299 1300 if (key && vnic->rss_hash_key) 1301 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1302 1303 return 0; 1304 } 1305 1306 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1307 const u8 *key, const u8 hfunc) 1308 { 1309 struct bnxt *bp = netdev_priv(dev); 1310 int rc = 0; 1311 1312 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1313 return -EOPNOTSUPP; 1314 1315 if (key) 1316 return -EOPNOTSUPP; 1317 1318 if (indir) { 1319 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1320 1321 for (i = 0; i < tbl_size; i++) 1322 bp->rss_indir_tbl[i] = indir[i]; 1323 pad = bp->rss_indir_tbl_entries - tbl_size; 1324 if (pad) 1325 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1326 } 1327 1328 if (netif_running(bp->dev)) { 1329 bnxt_close_nic(bp, false, false); 1330 rc = bnxt_open_nic(bp, false, false); 1331 } 1332 return rc; 1333 } 1334 1335 static void bnxt_get_drvinfo(struct net_device *dev, 1336 struct ethtool_drvinfo *info) 1337 { 1338 struct bnxt *bp = netdev_priv(dev); 1339 1340 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1341 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1342 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1343 info->n_stats = bnxt_get_num_stats(bp); 1344 info->testinfo_len = bp->num_tests; 1345 /* TODO CHIMP_FW: eeprom dump details */ 1346 info->eedump_len = 0; 1347 /* TODO CHIMP FW: reg dump details */ 1348 info->regdump_len = 0; 1349 } 1350 1351 static int bnxt_get_regs_len(struct net_device *dev) 1352 { 1353 struct bnxt *bp = netdev_priv(dev); 1354 int reg_len; 1355 1356 if (!BNXT_PF(bp)) 1357 return -EOPNOTSUPP; 1358 1359 reg_len = BNXT_PXP_REG_LEN; 1360 1361 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1362 reg_len += sizeof(struct pcie_ctx_hw_stats); 1363 1364 return reg_len; 1365 } 1366 1367 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1368 void *_p) 1369 { 1370 struct pcie_ctx_hw_stats *hw_pcie_stats; 1371 struct hwrm_pcie_qstats_input *req; 1372 struct bnxt *bp = netdev_priv(dev); 1373 dma_addr_t hw_pcie_stats_addr; 1374 int rc; 1375 1376 regs->version = 0; 1377 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1378 1379 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1380 return; 1381 1382 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1383 return; 1384 1385 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1386 &hw_pcie_stats_addr); 1387 if (!hw_pcie_stats) { 1388 hwrm_req_drop(bp, req); 1389 return; 1390 } 1391 1392 regs->version = 1; 1393 hwrm_req_hold(bp, req); /* hold on to slice */ 1394 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1395 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1396 rc = hwrm_req_send(bp, req); 1397 if (!rc) { 1398 __le64 *src = (__le64 *)hw_pcie_stats; 1399 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1400 int i; 1401 1402 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1403 dst[i] = le64_to_cpu(src[i]); 1404 } 1405 hwrm_req_drop(bp, req); 1406 } 1407 1408 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1409 { 1410 struct bnxt *bp = netdev_priv(dev); 1411 1412 wol->supported = 0; 1413 wol->wolopts = 0; 1414 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1415 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1416 wol->supported = WAKE_MAGIC; 1417 if (bp->wol) 1418 wol->wolopts = WAKE_MAGIC; 1419 } 1420 } 1421 1422 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1423 { 1424 struct bnxt *bp = netdev_priv(dev); 1425 1426 if (wol->wolopts & ~WAKE_MAGIC) 1427 return -EINVAL; 1428 1429 if (wol->wolopts & WAKE_MAGIC) { 1430 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1431 return -EINVAL; 1432 if (!bp->wol) { 1433 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1434 return -EBUSY; 1435 bp->wol = 1; 1436 } 1437 } else { 1438 if (bp->wol) { 1439 if (bnxt_hwrm_free_wol_fltr(bp)) 1440 return -EBUSY; 1441 bp->wol = 0; 1442 } 1443 } 1444 return 0; 1445 } 1446 1447 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1448 { 1449 u32 speed_mask = 0; 1450 1451 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1452 /* set the advertised speeds */ 1453 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1454 speed_mask |= ADVERTISED_100baseT_Full; 1455 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1456 speed_mask |= ADVERTISED_1000baseT_Full; 1457 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1458 speed_mask |= ADVERTISED_2500baseX_Full; 1459 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1460 speed_mask |= ADVERTISED_10000baseT_Full; 1461 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1462 speed_mask |= ADVERTISED_40000baseCR4_Full; 1463 1464 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1465 speed_mask |= ADVERTISED_Pause; 1466 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1467 speed_mask |= ADVERTISED_Asym_Pause; 1468 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1469 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1470 1471 return speed_mask; 1472 } 1473 1474 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1475 { \ 1476 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1477 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1478 100baseT_Full); \ 1479 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1480 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1481 1000baseT_Full); \ 1482 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1483 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1484 10000baseT_Full); \ 1485 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1486 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1487 25000baseCR_Full); \ 1488 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1489 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1490 40000baseCR4_Full);\ 1491 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1492 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1493 50000baseCR2_Full);\ 1494 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1495 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1496 100000baseCR4_Full);\ 1497 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1498 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1499 Pause); \ 1500 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1501 ethtool_link_ksettings_add_link_mode( \ 1502 lk_ksettings, name, Asym_Pause);\ 1503 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1504 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1505 Asym_Pause); \ 1506 } \ 1507 } 1508 1509 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1510 { \ 1511 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1512 100baseT_Full) || \ 1513 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1514 100baseT_Half)) \ 1515 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1516 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1517 1000baseT_Full) || \ 1518 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1519 1000baseT_Half)) \ 1520 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1521 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1522 10000baseT_Full)) \ 1523 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1524 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1525 25000baseCR_Full)) \ 1526 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1527 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1528 40000baseCR4_Full)) \ 1529 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1530 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1531 50000baseCR2_Full)) \ 1532 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1533 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1534 100000baseCR4_Full)) \ 1535 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1536 } 1537 1538 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1539 { \ 1540 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \ 1541 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1542 50000baseCR_Full); \ 1543 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \ 1544 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1545 100000baseCR2_Full);\ 1546 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \ 1547 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1548 200000baseCR4_Full);\ 1549 } 1550 1551 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1552 { \ 1553 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1554 50000baseCR_Full)) \ 1555 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \ 1556 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1557 100000baseCR2_Full)) \ 1558 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \ 1559 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1560 200000baseCR4_Full)) \ 1561 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \ 1562 } 1563 1564 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1565 struct ethtool_link_ksettings *lk_ksettings) 1566 { 1567 u16 fec_cfg = link_info->fec_cfg; 1568 1569 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1570 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1571 lk_ksettings->link_modes.advertising); 1572 return; 1573 } 1574 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1575 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1576 lk_ksettings->link_modes.advertising); 1577 if (fec_cfg & BNXT_FEC_ENC_RS) 1578 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1579 lk_ksettings->link_modes.advertising); 1580 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1581 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1582 lk_ksettings->link_modes.advertising); 1583 } 1584 1585 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1586 struct ethtool_link_ksettings *lk_ksettings) 1587 { 1588 u16 fw_speeds = link_info->advertising; 1589 u8 fw_pause = 0; 1590 1591 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1592 fw_pause = link_info->auto_pause_setting; 1593 1594 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1595 fw_speeds = link_info->advertising_pam4; 1596 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising); 1597 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 1598 } 1599 1600 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1601 struct ethtool_link_ksettings *lk_ksettings) 1602 { 1603 u16 fw_speeds = link_info->lp_auto_link_speeds; 1604 u8 fw_pause = 0; 1605 1606 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1607 fw_pause = link_info->lp_pause; 1608 1609 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1610 lp_advertising); 1611 fw_speeds = link_info->lp_auto_pam4_link_speeds; 1612 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising); 1613 } 1614 1615 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1616 struct ethtool_link_ksettings *lk_ksettings) 1617 { 1618 u16 fec_cfg = link_info->fec_cfg; 1619 1620 if (fec_cfg & BNXT_FEC_NONE) { 1621 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1622 lk_ksettings->link_modes.supported); 1623 return; 1624 } 1625 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1626 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1627 lk_ksettings->link_modes.supported); 1628 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1629 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1630 lk_ksettings->link_modes.supported); 1631 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1632 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1633 lk_ksettings->link_modes.supported); 1634 } 1635 1636 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1637 struct ethtool_link_ksettings *lk_ksettings) 1638 { 1639 u16 fw_speeds = link_info->support_speeds; 1640 1641 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1642 fw_speeds = link_info->support_pam4_speeds; 1643 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported); 1644 1645 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1646 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1647 Asym_Pause); 1648 1649 if (link_info->support_auto_speeds || 1650 link_info->support_pam4_auto_speeds) 1651 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1652 Autoneg); 1653 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 1654 } 1655 1656 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1657 { 1658 switch (fw_link_speed) { 1659 case BNXT_LINK_SPEED_100MB: 1660 return SPEED_100; 1661 case BNXT_LINK_SPEED_1GB: 1662 return SPEED_1000; 1663 case BNXT_LINK_SPEED_2_5GB: 1664 return SPEED_2500; 1665 case BNXT_LINK_SPEED_10GB: 1666 return SPEED_10000; 1667 case BNXT_LINK_SPEED_20GB: 1668 return SPEED_20000; 1669 case BNXT_LINK_SPEED_25GB: 1670 return SPEED_25000; 1671 case BNXT_LINK_SPEED_40GB: 1672 return SPEED_40000; 1673 case BNXT_LINK_SPEED_50GB: 1674 return SPEED_50000; 1675 case BNXT_LINK_SPEED_100GB: 1676 return SPEED_100000; 1677 default: 1678 return SPEED_UNKNOWN; 1679 } 1680 } 1681 1682 static int bnxt_get_link_ksettings(struct net_device *dev, 1683 struct ethtool_link_ksettings *lk_ksettings) 1684 { 1685 struct bnxt *bp = netdev_priv(dev); 1686 struct bnxt_link_info *link_info = &bp->link_info; 1687 struct ethtool_link_settings *base = &lk_ksettings->base; 1688 u32 ethtool_speed; 1689 1690 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1691 mutex_lock(&bp->link_lock); 1692 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1693 1694 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1695 if (link_info->autoneg) { 1696 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1697 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1698 advertising, Autoneg); 1699 base->autoneg = AUTONEG_ENABLE; 1700 base->duplex = DUPLEX_UNKNOWN; 1701 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1702 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1703 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1704 base->duplex = DUPLEX_FULL; 1705 else 1706 base->duplex = DUPLEX_HALF; 1707 } 1708 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1709 } else { 1710 base->autoneg = AUTONEG_DISABLE; 1711 ethtool_speed = 1712 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1713 base->duplex = DUPLEX_HALF; 1714 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1715 base->duplex = DUPLEX_FULL; 1716 } 1717 base->speed = ethtool_speed; 1718 1719 base->port = PORT_NONE; 1720 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1721 base->port = PORT_TP; 1722 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1723 TP); 1724 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1725 TP); 1726 } else { 1727 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1728 FIBRE); 1729 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1730 FIBRE); 1731 1732 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1733 base->port = PORT_DA; 1734 else if (link_info->media_type == 1735 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1736 base->port = PORT_FIBRE; 1737 } 1738 base->phy_address = link_info->phy_addr; 1739 mutex_unlock(&bp->link_lock); 1740 1741 return 0; 1742 } 1743 1744 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed) 1745 { 1746 struct bnxt *bp = netdev_priv(dev); 1747 struct bnxt_link_info *link_info = &bp->link_info; 1748 u16 support_pam4_spds = link_info->support_pam4_speeds; 1749 u16 support_spds = link_info->support_speeds; 1750 u8 sig_mode = BNXT_SIG_MODE_NRZ; 1751 u16 fw_speed = 0; 1752 1753 switch (ethtool_speed) { 1754 case SPEED_100: 1755 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1756 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 1757 break; 1758 case SPEED_1000: 1759 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1760 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 1761 break; 1762 case SPEED_2500: 1763 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1764 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 1765 break; 1766 case SPEED_10000: 1767 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1768 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 1769 break; 1770 case SPEED_20000: 1771 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1772 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 1773 break; 1774 case SPEED_25000: 1775 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1776 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 1777 break; 1778 case SPEED_40000: 1779 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1780 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 1781 break; 1782 case SPEED_50000: 1783 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) { 1784 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 1785 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 1786 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 1787 sig_mode = BNXT_SIG_MODE_PAM4; 1788 } 1789 break; 1790 case SPEED_100000: 1791 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) { 1792 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 1793 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 1794 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 1795 sig_mode = BNXT_SIG_MODE_PAM4; 1796 } 1797 break; 1798 case SPEED_200000: 1799 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 1800 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 1801 sig_mode = BNXT_SIG_MODE_PAM4; 1802 } 1803 break; 1804 } 1805 1806 if (!fw_speed) { 1807 netdev_err(dev, "unsupported speed!\n"); 1808 return -EINVAL; 1809 } 1810 1811 if (link_info->req_link_speed == fw_speed && 1812 link_info->req_signal_mode == sig_mode && 1813 link_info->autoneg == 0) 1814 return -EALREADY; 1815 1816 link_info->req_link_speed = fw_speed; 1817 link_info->req_signal_mode = sig_mode; 1818 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1819 link_info->autoneg = 0; 1820 link_info->advertising = 0; 1821 link_info->advertising_pam4 = 0; 1822 1823 return 0; 1824 } 1825 1826 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1827 { 1828 u16 fw_speed_mask = 0; 1829 1830 /* only support autoneg at speed 100, 1000, and 10000 */ 1831 if (advertising & (ADVERTISED_100baseT_Full | 1832 ADVERTISED_100baseT_Half)) { 1833 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1834 } 1835 if (advertising & (ADVERTISED_1000baseT_Full | 1836 ADVERTISED_1000baseT_Half)) { 1837 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1838 } 1839 if (advertising & ADVERTISED_10000baseT_Full) 1840 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1841 1842 if (advertising & ADVERTISED_40000baseCR4_Full) 1843 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1844 1845 return fw_speed_mask; 1846 } 1847 1848 static int bnxt_set_link_ksettings(struct net_device *dev, 1849 const struct ethtool_link_ksettings *lk_ksettings) 1850 { 1851 struct bnxt *bp = netdev_priv(dev); 1852 struct bnxt_link_info *link_info = &bp->link_info; 1853 const struct ethtool_link_settings *base = &lk_ksettings->base; 1854 bool set_pause = false; 1855 u32 speed; 1856 int rc = 0; 1857 1858 if (!BNXT_PHY_CFG_ABLE(bp)) 1859 return -EOPNOTSUPP; 1860 1861 mutex_lock(&bp->link_lock); 1862 if (base->autoneg == AUTONEG_ENABLE) { 1863 link_info->advertising = 0; 1864 link_info->advertising_pam4 = 0; 1865 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings, 1866 advertising); 1867 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4, 1868 lk_ksettings, advertising); 1869 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1870 if (!link_info->advertising && !link_info->advertising_pam4) { 1871 link_info->advertising = link_info->support_auto_speeds; 1872 link_info->advertising_pam4 = 1873 link_info->support_pam4_auto_speeds; 1874 } 1875 /* any change to autoneg will cause link change, therefore the 1876 * driver should put back the original pause setting in autoneg 1877 */ 1878 set_pause = true; 1879 } else { 1880 u8 phy_type = link_info->phy_type; 1881 1882 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1883 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1884 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1885 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1886 rc = -EINVAL; 1887 goto set_setting_exit; 1888 } 1889 if (base->duplex == DUPLEX_HALF) { 1890 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1891 rc = -EINVAL; 1892 goto set_setting_exit; 1893 } 1894 speed = base->speed; 1895 rc = bnxt_force_link_speed(dev, speed); 1896 if (rc) { 1897 if (rc == -EALREADY) 1898 rc = 0; 1899 goto set_setting_exit; 1900 } 1901 } 1902 1903 if (netif_running(dev)) 1904 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1905 1906 set_setting_exit: 1907 mutex_unlock(&bp->link_lock); 1908 return rc; 1909 } 1910 1911 static int bnxt_get_fecparam(struct net_device *dev, 1912 struct ethtool_fecparam *fec) 1913 { 1914 struct bnxt *bp = netdev_priv(dev); 1915 struct bnxt_link_info *link_info; 1916 u8 active_fec; 1917 u16 fec_cfg; 1918 1919 link_info = &bp->link_info; 1920 fec_cfg = link_info->fec_cfg; 1921 active_fec = link_info->active_fec_sig_mode & 1922 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 1923 if (fec_cfg & BNXT_FEC_NONE) { 1924 fec->fec = ETHTOOL_FEC_NONE; 1925 fec->active_fec = ETHTOOL_FEC_NONE; 1926 return 0; 1927 } 1928 if (fec_cfg & BNXT_FEC_AUTONEG) 1929 fec->fec |= ETHTOOL_FEC_AUTO; 1930 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1931 fec->fec |= ETHTOOL_FEC_BASER; 1932 if (fec_cfg & BNXT_FEC_ENC_RS) 1933 fec->fec |= ETHTOOL_FEC_RS; 1934 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1935 fec->fec |= ETHTOOL_FEC_LLRS; 1936 1937 switch (active_fec) { 1938 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 1939 fec->active_fec |= ETHTOOL_FEC_BASER; 1940 break; 1941 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 1942 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 1943 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 1944 fec->active_fec |= ETHTOOL_FEC_RS; 1945 break; 1946 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 1947 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 1948 fec->active_fec |= ETHTOOL_FEC_LLRS; 1949 break; 1950 } 1951 return 0; 1952 } 1953 1954 static void bnxt_get_fec_stats(struct net_device *dev, 1955 struct ethtool_fec_stats *fec_stats) 1956 { 1957 struct bnxt *bp = netdev_priv(dev); 1958 u64 *rx; 1959 1960 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 1961 return; 1962 1963 rx = bp->rx_port_stats_ext.sw_stats; 1964 fec_stats->corrected_bits.total = 1965 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 1966 } 1967 1968 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 1969 u32 fec) 1970 { 1971 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 1972 1973 if (fec & ETHTOOL_FEC_BASER) 1974 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 1975 else if (fec & ETHTOOL_FEC_RS) 1976 fw_fec |= BNXT_FEC_RS_ON(link_info); 1977 else if (fec & ETHTOOL_FEC_LLRS) 1978 fw_fec |= BNXT_FEC_LLRS_ON; 1979 return fw_fec; 1980 } 1981 1982 static int bnxt_set_fecparam(struct net_device *dev, 1983 struct ethtool_fecparam *fecparam) 1984 { 1985 struct hwrm_port_phy_cfg_input *req; 1986 struct bnxt *bp = netdev_priv(dev); 1987 struct bnxt_link_info *link_info; 1988 u32 new_cfg, fec = fecparam->fec; 1989 u16 fec_cfg; 1990 int rc; 1991 1992 link_info = &bp->link_info; 1993 fec_cfg = link_info->fec_cfg; 1994 if (fec_cfg & BNXT_FEC_NONE) 1995 return -EOPNOTSUPP; 1996 1997 if (fec & ETHTOOL_FEC_OFF) { 1998 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 1999 BNXT_FEC_ALL_OFF(link_info); 2000 goto apply_fec; 2001 } 2002 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2003 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2004 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2005 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2006 return -EINVAL; 2007 2008 if (fec & ETHTOOL_FEC_AUTO) { 2009 if (!link_info->autoneg) 2010 return -EINVAL; 2011 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2012 } else { 2013 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2014 } 2015 2016 apply_fec: 2017 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2018 if (rc) 2019 return rc; 2020 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2021 rc = hwrm_req_send(bp, req); 2022 /* update current settings */ 2023 if (!rc) { 2024 mutex_lock(&bp->link_lock); 2025 bnxt_update_link(bp, false); 2026 mutex_unlock(&bp->link_lock); 2027 } 2028 return rc; 2029 } 2030 2031 static void bnxt_get_pauseparam(struct net_device *dev, 2032 struct ethtool_pauseparam *epause) 2033 { 2034 struct bnxt *bp = netdev_priv(dev); 2035 struct bnxt_link_info *link_info = &bp->link_info; 2036 2037 if (BNXT_VF(bp)) 2038 return; 2039 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2040 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2041 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2042 } 2043 2044 static void bnxt_get_pause_stats(struct net_device *dev, 2045 struct ethtool_pause_stats *epstat) 2046 { 2047 struct bnxt *bp = netdev_priv(dev); 2048 u64 *rx, *tx; 2049 2050 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2051 return; 2052 2053 rx = bp->port_stats.sw_stats; 2054 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2055 2056 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2057 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2058 } 2059 2060 static int bnxt_set_pauseparam(struct net_device *dev, 2061 struct ethtool_pauseparam *epause) 2062 { 2063 int rc = 0; 2064 struct bnxt *bp = netdev_priv(dev); 2065 struct bnxt_link_info *link_info = &bp->link_info; 2066 2067 if (!BNXT_PHY_CFG_ABLE(bp)) 2068 return -EOPNOTSUPP; 2069 2070 mutex_lock(&bp->link_lock); 2071 if (epause->autoneg) { 2072 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2073 rc = -EINVAL; 2074 goto pause_exit; 2075 } 2076 2077 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2078 if (bp->hwrm_spec_code >= 0x10201) 2079 link_info->req_flow_ctrl = 2080 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 2081 } else { 2082 /* when transition from auto pause to force pause, 2083 * force a link change 2084 */ 2085 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2086 link_info->force_link_chng = true; 2087 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2088 link_info->req_flow_ctrl = 0; 2089 } 2090 if (epause->rx_pause) 2091 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2092 2093 if (epause->tx_pause) 2094 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2095 2096 if (netif_running(dev)) 2097 rc = bnxt_hwrm_set_pause(bp); 2098 2099 pause_exit: 2100 mutex_unlock(&bp->link_lock); 2101 return rc; 2102 } 2103 2104 static u32 bnxt_get_link(struct net_device *dev) 2105 { 2106 struct bnxt *bp = netdev_priv(dev); 2107 2108 /* TODO: handle MF, VF, driver close case */ 2109 return bp->link_info.link_up; 2110 } 2111 2112 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2113 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2114 { 2115 struct hwrm_nvm_get_dev_info_output *resp; 2116 struct hwrm_nvm_get_dev_info_input *req; 2117 int rc; 2118 2119 if (BNXT_VF(bp)) 2120 return -EOPNOTSUPP; 2121 2122 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2123 if (rc) 2124 return rc; 2125 2126 resp = hwrm_req_hold(bp, req); 2127 rc = hwrm_req_send(bp, req); 2128 if (!rc) 2129 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2130 hwrm_req_drop(bp, req); 2131 return rc; 2132 } 2133 2134 static void bnxt_print_admin_err(struct bnxt *bp) 2135 { 2136 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2137 } 2138 2139 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2140 u16 ext, u16 *index, u32 *item_length, 2141 u32 *data_length); 2142 2143 static int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2144 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2145 u32 dir_item_len, const u8 *data, 2146 size_t data_len) 2147 { 2148 struct bnxt *bp = netdev_priv(dev); 2149 struct hwrm_nvm_write_input *req; 2150 int rc; 2151 2152 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2153 if (rc) 2154 return rc; 2155 2156 if (data_len && data) { 2157 dma_addr_t dma_handle; 2158 u8 *kmem; 2159 2160 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2161 if (!kmem) { 2162 hwrm_req_drop(bp, req); 2163 return -ENOMEM; 2164 } 2165 2166 req->dir_data_length = cpu_to_le32(data_len); 2167 2168 memcpy(kmem, data, data_len); 2169 req->host_src_addr = cpu_to_le64(dma_handle); 2170 } 2171 2172 hwrm_req_timeout(bp, req, FLASH_NVRAM_TIMEOUT); 2173 req->dir_type = cpu_to_le16(dir_type); 2174 req->dir_ordinal = cpu_to_le16(dir_ordinal); 2175 req->dir_ext = cpu_to_le16(dir_ext); 2176 req->dir_attr = cpu_to_le16(dir_attr); 2177 req->dir_item_length = cpu_to_le32(dir_item_len); 2178 rc = hwrm_req_send(bp, req); 2179 2180 if (rc == -EACCES) 2181 bnxt_print_admin_err(bp); 2182 return rc; 2183 } 2184 2185 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2186 u8 self_reset, u8 flags) 2187 { 2188 struct bnxt *bp = netdev_priv(dev); 2189 struct hwrm_fw_reset_input *req; 2190 int rc; 2191 2192 if (!bnxt_hwrm_reset_permitted(bp)) { 2193 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 2194 return -EPERM; 2195 } 2196 2197 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 2198 if (rc) 2199 return rc; 2200 2201 req->embedded_proc_type = proc_type; 2202 req->selfrst_status = self_reset; 2203 req->flags = flags; 2204 2205 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2206 rc = hwrm_req_send_silent(bp, req); 2207 } else { 2208 rc = hwrm_req_send(bp, req); 2209 if (rc == -EACCES) 2210 bnxt_print_admin_err(bp); 2211 } 2212 return rc; 2213 } 2214 2215 static int bnxt_firmware_reset(struct net_device *dev, 2216 enum bnxt_nvm_directory_type dir_type) 2217 { 2218 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2219 u8 proc_type, flags = 0; 2220 2221 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2222 /* (e.g. when firmware isn't already running) */ 2223 switch (dir_type) { 2224 case BNX_DIR_TYPE_CHIMP_PATCH: 2225 case BNX_DIR_TYPE_BOOTCODE: 2226 case BNX_DIR_TYPE_BOOTCODE_2: 2227 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2228 /* Self-reset ChiMP upon next PCIe reset: */ 2229 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2230 break; 2231 case BNX_DIR_TYPE_APE_FW: 2232 case BNX_DIR_TYPE_APE_PATCH: 2233 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2234 /* Self-reset APE upon next PCIe reset: */ 2235 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2236 break; 2237 case BNX_DIR_TYPE_KONG_FW: 2238 case BNX_DIR_TYPE_KONG_PATCH: 2239 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2240 break; 2241 case BNX_DIR_TYPE_BONO_FW: 2242 case BNX_DIR_TYPE_BONO_PATCH: 2243 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2244 break; 2245 default: 2246 return -EINVAL; 2247 } 2248 2249 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2250 } 2251 2252 static int bnxt_firmware_reset_chip(struct net_device *dev) 2253 { 2254 struct bnxt *bp = netdev_priv(dev); 2255 u8 flags = 0; 2256 2257 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2258 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2259 2260 return bnxt_hwrm_firmware_reset(dev, 2261 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2262 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2263 flags); 2264 } 2265 2266 static int bnxt_firmware_reset_ap(struct net_device *dev) 2267 { 2268 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2269 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2270 0); 2271 } 2272 2273 static int bnxt_flash_firmware(struct net_device *dev, 2274 u16 dir_type, 2275 const u8 *fw_data, 2276 size_t fw_size) 2277 { 2278 int rc = 0; 2279 u16 code_type; 2280 u32 stored_crc; 2281 u32 calculated_crc; 2282 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2283 2284 switch (dir_type) { 2285 case BNX_DIR_TYPE_BOOTCODE: 2286 case BNX_DIR_TYPE_BOOTCODE_2: 2287 code_type = CODE_BOOT; 2288 break; 2289 case BNX_DIR_TYPE_CHIMP_PATCH: 2290 code_type = CODE_CHIMP_PATCH; 2291 break; 2292 case BNX_DIR_TYPE_APE_FW: 2293 code_type = CODE_MCTP_PASSTHRU; 2294 break; 2295 case BNX_DIR_TYPE_APE_PATCH: 2296 code_type = CODE_APE_PATCH; 2297 break; 2298 case BNX_DIR_TYPE_KONG_FW: 2299 code_type = CODE_KONG_FW; 2300 break; 2301 case BNX_DIR_TYPE_KONG_PATCH: 2302 code_type = CODE_KONG_PATCH; 2303 break; 2304 case BNX_DIR_TYPE_BONO_FW: 2305 code_type = CODE_BONO_FW; 2306 break; 2307 case BNX_DIR_TYPE_BONO_PATCH: 2308 code_type = CODE_BONO_PATCH; 2309 break; 2310 default: 2311 netdev_err(dev, "Unsupported directory entry type: %u\n", 2312 dir_type); 2313 return -EINVAL; 2314 } 2315 if (fw_size < sizeof(struct bnxt_fw_header)) { 2316 netdev_err(dev, "Invalid firmware file size: %u\n", 2317 (unsigned int)fw_size); 2318 return -EINVAL; 2319 } 2320 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2321 netdev_err(dev, "Invalid firmware signature: %08X\n", 2322 le32_to_cpu(header->signature)); 2323 return -EINVAL; 2324 } 2325 if (header->code_type != code_type) { 2326 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2327 code_type, header->code_type); 2328 return -EINVAL; 2329 } 2330 if (header->device != DEVICE_CUMULUS_FAMILY) { 2331 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2332 DEVICE_CUMULUS_FAMILY, header->device); 2333 return -EINVAL; 2334 } 2335 /* Confirm the CRC32 checksum of the file: */ 2336 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2337 sizeof(stored_crc))); 2338 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2339 if (calculated_crc != stored_crc) { 2340 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2341 (unsigned long)stored_crc, 2342 (unsigned long)calculated_crc); 2343 return -EINVAL; 2344 } 2345 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2346 0, 0, 0, fw_data, fw_size); 2347 if (rc == 0) /* Firmware update successful */ 2348 rc = bnxt_firmware_reset(dev, dir_type); 2349 2350 return rc; 2351 } 2352 2353 static int bnxt_flash_microcode(struct net_device *dev, 2354 u16 dir_type, 2355 const u8 *fw_data, 2356 size_t fw_size) 2357 { 2358 struct bnxt_ucode_trailer *trailer; 2359 u32 calculated_crc; 2360 u32 stored_crc; 2361 int rc = 0; 2362 2363 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2364 netdev_err(dev, "Invalid microcode file size: %u\n", 2365 (unsigned int)fw_size); 2366 return -EINVAL; 2367 } 2368 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2369 sizeof(*trailer))); 2370 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2371 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2372 le32_to_cpu(trailer->sig)); 2373 return -EINVAL; 2374 } 2375 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2376 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2377 dir_type, le16_to_cpu(trailer->dir_type)); 2378 return -EINVAL; 2379 } 2380 if (le16_to_cpu(trailer->trailer_length) < 2381 sizeof(struct bnxt_ucode_trailer)) { 2382 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2383 le16_to_cpu(trailer->trailer_length)); 2384 return -EINVAL; 2385 } 2386 2387 /* Confirm the CRC32 checksum of the file: */ 2388 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2389 sizeof(stored_crc))); 2390 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2391 if (calculated_crc != stored_crc) { 2392 netdev_err(dev, 2393 "CRC32 (%08lX) does not match calculated: %08lX\n", 2394 (unsigned long)stored_crc, 2395 (unsigned long)calculated_crc); 2396 return -EINVAL; 2397 } 2398 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2399 0, 0, 0, fw_data, fw_size); 2400 2401 return rc; 2402 } 2403 2404 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2405 { 2406 switch (dir_type) { 2407 case BNX_DIR_TYPE_CHIMP_PATCH: 2408 case BNX_DIR_TYPE_BOOTCODE: 2409 case BNX_DIR_TYPE_BOOTCODE_2: 2410 case BNX_DIR_TYPE_APE_FW: 2411 case BNX_DIR_TYPE_APE_PATCH: 2412 case BNX_DIR_TYPE_KONG_FW: 2413 case BNX_DIR_TYPE_KONG_PATCH: 2414 case BNX_DIR_TYPE_BONO_FW: 2415 case BNX_DIR_TYPE_BONO_PATCH: 2416 return true; 2417 } 2418 2419 return false; 2420 } 2421 2422 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2423 { 2424 switch (dir_type) { 2425 case BNX_DIR_TYPE_AVS: 2426 case BNX_DIR_TYPE_EXP_ROM_MBA: 2427 case BNX_DIR_TYPE_PCIE: 2428 case BNX_DIR_TYPE_TSCF_UCODE: 2429 case BNX_DIR_TYPE_EXT_PHY: 2430 case BNX_DIR_TYPE_CCM: 2431 case BNX_DIR_TYPE_ISCSI_BOOT: 2432 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2433 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2434 return true; 2435 } 2436 2437 return false; 2438 } 2439 2440 static bool bnxt_dir_type_is_executable(u16 dir_type) 2441 { 2442 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2443 bnxt_dir_type_is_other_exec_format(dir_type); 2444 } 2445 2446 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2447 u16 dir_type, 2448 const char *filename) 2449 { 2450 const struct firmware *fw; 2451 int rc; 2452 2453 rc = request_firmware(&fw, filename, &dev->dev); 2454 if (rc != 0) { 2455 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2456 rc, filename); 2457 return rc; 2458 } 2459 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2460 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2461 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2462 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2463 else 2464 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2465 0, 0, 0, fw->data, fw->size); 2466 release_firmware(fw); 2467 return rc; 2468 } 2469 2470 #define BNXT_PKG_DMA_SIZE 0x40000 2471 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2472 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2473 2474 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2475 u32 install_type) 2476 { 2477 struct hwrm_nvm_install_update_input *install; 2478 struct hwrm_nvm_install_update_output *resp; 2479 struct hwrm_nvm_modify_input *modify; 2480 struct bnxt *bp = netdev_priv(dev); 2481 bool defrag_attempted = false; 2482 dma_addr_t dma_handle; 2483 u8 *kmem = NULL; 2484 u32 modify_len; 2485 u32 item_len; 2486 u16 index; 2487 int rc; 2488 2489 bnxt_hwrm_fw_set_time(bp); 2490 2491 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 2492 if (rc) 2493 return rc; 2494 2495 /* Try allocating a large DMA buffer first. Older fw will 2496 * cause excessive NVRAM erases when using small blocks. 2497 */ 2498 modify_len = roundup_pow_of_two(fw->size); 2499 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 2500 while (1) { 2501 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 2502 if (!kmem && modify_len > PAGE_SIZE) 2503 modify_len /= 2; 2504 else 2505 break; 2506 } 2507 if (!kmem) { 2508 hwrm_req_drop(bp, modify); 2509 return -ENOMEM; 2510 } 2511 2512 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 2513 if (rc) { 2514 hwrm_req_drop(bp, modify); 2515 return rc; 2516 } 2517 2518 hwrm_req_timeout(bp, modify, FLASH_PACKAGE_TIMEOUT); 2519 hwrm_req_timeout(bp, install, INSTALL_PACKAGE_TIMEOUT); 2520 2521 hwrm_req_hold(bp, modify); 2522 modify->host_src_addr = cpu_to_le64(dma_handle); 2523 2524 resp = hwrm_req_hold(bp, install); 2525 if ((install_type & 0xffff) == 0) 2526 install_type >>= 16; 2527 install->install_type = cpu_to_le32(install_type); 2528 2529 do { 2530 u32 copied = 0, len = modify_len; 2531 2532 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2533 BNX_DIR_ORDINAL_FIRST, 2534 BNX_DIR_EXT_NONE, 2535 &index, &item_len, NULL); 2536 if (rc) { 2537 netdev_err(dev, "PKG update area not created in nvram\n"); 2538 break; 2539 } 2540 if (fw->size > item_len) { 2541 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2542 (unsigned long)fw->size); 2543 rc = -EFBIG; 2544 break; 2545 } 2546 2547 modify->dir_idx = cpu_to_le16(index); 2548 2549 if (fw->size > modify_len) 2550 modify->flags = BNXT_NVM_MORE_FLAG; 2551 while (copied < fw->size) { 2552 u32 balance = fw->size - copied; 2553 2554 if (balance <= modify_len) { 2555 len = balance; 2556 if (copied) 2557 modify->flags |= BNXT_NVM_LAST_FLAG; 2558 } 2559 memcpy(kmem, fw->data + copied, len); 2560 modify->len = cpu_to_le32(len); 2561 modify->offset = cpu_to_le32(copied); 2562 rc = hwrm_req_send(bp, modify); 2563 if (rc) 2564 goto pkg_abort; 2565 copied += len; 2566 } 2567 2568 rc = hwrm_req_send_silent(bp, install); 2569 2570 if (defrag_attempted) { 2571 /* We have tried to defragment already in the previous 2572 * iteration. Return with the result for INSTALL_UPDATE 2573 */ 2574 break; 2575 } 2576 2577 if (rc && ((struct hwrm_err_output *)resp)->cmd_err == 2578 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2579 install->flags = 2580 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2581 2582 rc = hwrm_req_send_silent(bp, install); 2583 2584 if (rc && ((struct hwrm_err_output *)resp)->cmd_err == 2585 NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 2586 /* FW has cleared NVM area, driver will create 2587 * UPDATE directory and try the flash again 2588 */ 2589 defrag_attempted = true; 2590 install->flags = 0; 2591 rc = bnxt_flash_nvram(bp->dev, 2592 BNX_DIR_TYPE_UPDATE, 2593 BNX_DIR_ORDINAL_FIRST, 2594 0, 0, item_len, NULL, 0); 2595 } else if (rc) { 2596 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x\n", rc); 2597 } 2598 } else if (rc) { 2599 netdev_err(dev, "HWRM_NVM_INSTALL_UPDATE failure rc :%x\n", rc); 2600 } 2601 } while (defrag_attempted && !rc); 2602 2603 pkg_abort: 2604 hwrm_req_drop(bp, modify); 2605 hwrm_req_drop(bp, install); 2606 2607 if (resp->result) { 2608 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2609 (s8)resp->result, (int)resp->problem_item); 2610 rc = -ENOPKG; 2611 } 2612 if (rc == -EACCES) 2613 bnxt_print_admin_err(bp); 2614 return rc; 2615 } 2616 2617 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2618 u32 install_type) 2619 { 2620 const struct firmware *fw; 2621 int rc; 2622 2623 rc = request_firmware(&fw, filename, &dev->dev); 2624 if (rc != 0) { 2625 netdev_err(dev, "PKG error %d requesting file: %s\n", 2626 rc, filename); 2627 return rc; 2628 } 2629 2630 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type); 2631 2632 release_firmware(fw); 2633 2634 return rc; 2635 } 2636 2637 static int bnxt_flash_device(struct net_device *dev, 2638 struct ethtool_flash *flash) 2639 { 2640 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2641 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2642 return -EINVAL; 2643 } 2644 2645 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2646 flash->region > 0xffff) 2647 return bnxt_flash_package_from_file(dev, flash->data, 2648 flash->region); 2649 2650 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2651 } 2652 2653 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2654 { 2655 struct hwrm_nvm_get_dir_info_output *output; 2656 struct hwrm_nvm_get_dir_info_input *req; 2657 struct bnxt *bp = netdev_priv(dev); 2658 int rc; 2659 2660 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 2661 if (rc) 2662 return rc; 2663 2664 output = hwrm_req_hold(bp, req); 2665 rc = hwrm_req_send(bp, req); 2666 if (!rc) { 2667 *entries = le32_to_cpu(output->entries); 2668 *length = le32_to_cpu(output->entry_length); 2669 } 2670 hwrm_req_drop(bp, req); 2671 return rc; 2672 } 2673 2674 static int bnxt_get_eeprom_len(struct net_device *dev) 2675 { 2676 struct bnxt *bp = netdev_priv(dev); 2677 2678 if (BNXT_VF(bp)) 2679 return 0; 2680 2681 /* The -1 return value allows the entire 32-bit range of offsets to be 2682 * passed via the ethtool command-line utility. 2683 */ 2684 return -1; 2685 } 2686 2687 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2688 { 2689 struct bnxt *bp = netdev_priv(dev); 2690 int rc; 2691 u32 dir_entries; 2692 u32 entry_length; 2693 u8 *buf; 2694 size_t buflen; 2695 dma_addr_t dma_handle; 2696 struct hwrm_nvm_get_dir_entries_input *req; 2697 2698 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2699 if (rc != 0) 2700 return rc; 2701 2702 if (!dir_entries || !entry_length) 2703 return -EIO; 2704 2705 /* Insert 2 bytes of directory info (count and size of entries) */ 2706 if (len < 2) 2707 return -EINVAL; 2708 2709 *data++ = dir_entries; 2710 *data++ = entry_length; 2711 len -= 2; 2712 memset(data, 0xff, len); 2713 2714 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 2715 if (rc) 2716 return rc; 2717 2718 buflen = dir_entries * entry_length; 2719 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 2720 if (!buf) { 2721 hwrm_req_drop(bp, req); 2722 return -ENOMEM; 2723 } 2724 req->host_dest_addr = cpu_to_le64(dma_handle); 2725 2726 hwrm_req_hold(bp, req); /* hold the slice */ 2727 rc = hwrm_req_send(bp, req); 2728 if (rc == 0) 2729 memcpy(data, buf, len > buflen ? buflen : len); 2730 hwrm_req_drop(bp, req); 2731 return rc; 2732 } 2733 2734 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2735 u32 length, u8 *data) 2736 { 2737 struct bnxt *bp = netdev_priv(dev); 2738 int rc; 2739 u8 *buf; 2740 dma_addr_t dma_handle; 2741 struct hwrm_nvm_read_input *req; 2742 2743 if (!length) 2744 return -EINVAL; 2745 2746 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 2747 if (rc) 2748 return rc; 2749 2750 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 2751 if (!buf) { 2752 hwrm_req_drop(bp, req); 2753 return -ENOMEM; 2754 } 2755 2756 req->host_dest_addr = cpu_to_le64(dma_handle); 2757 req->dir_idx = cpu_to_le16(index); 2758 req->offset = cpu_to_le32(offset); 2759 req->len = cpu_to_le32(length); 2760 2761 hwrm_req_hold(bp, req); /* hold the slice */ 2762 rc = hwrm_req_send(bp, req); 2763 if (rc == 0) 2764 memcpy(data, buf, length); 2765 hwrm_req_drop(bp, req); 2766 return rc; 2767 } 2768 2769 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2770 u16 ext, u16 *index, u32 *item_length, 2771 u32 *data_length) 2772 { 2773 struct hwrm_nvm_find_dir_entry_output *output; 2774 struct hwrm_nvm_find_dir_entry_input *req; 2775 struct bnxt *bp = netdev_priv(dev); 2776 int rc; 2777 2778 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 2779 if (rc) 2780 return rc; 2781 2782 req->enables = 0; 2783 req->dir_idx = 0; 2784 req->dir_type = cpu_to_le16(type); 2785 req->dir_ordinal = cpu_to_le16(ordinal); 2786 req->dir_ext = cpu_to_le16(ext); 2787 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2788 output = hwrm_req_hold(bp, req); 2789 rc = hwrm_req_send_silent(bp, req); 2790 if (rc == 0) { 2791 if (index) 2792 *index = le16_to_cpu(output->dir_idx); 2793 if (item_length) 2794 *item_length = le32_to_cpu(output->dir_item_length); 2795 if (data_length) 2796 *data_length = le32_to_cpu(output->dir_data_length); 2797 } 2798 hwrm_req_drop(bp, req); 2799 return rc; 2800 } 2801 2802 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2803 { 2804 char *retval = NULL; 2805 char *p; 2806 char *value; 2807 int field = 0; 2808 2809 if (datalen < 1) 2810 return NULL; 2811 /* null-terminate the log data (removing last '\n'): */ 2812 data[datalen - 1] = 0; 2813 for (p = data; *p != 0; p++) { 2814 field = 0; 2815 retval = NULL; 2816 while (*p != 0 && *p != '\n') { 2817 value = p; 2818 while (*p != 0 && *p != '\t' && *p != '\n') 2819 p++; 2820 if (field == desired_field) 2821 retval = value; 2822 if (*p != '\t') 2823 break; 2824 *p = 0; 2825 field++; 2826 p++; 2827 } 2828 if (*p == 0) 2829 break; 2830 *p = 0; 2831 } 2832 return retval; 2833 } 2834 2835 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 2836 { 2837 struct bnxt *bp = netdev_priv(dev); 2838 u16 index = 0; 2839 char *pkgver; 2840 u32 pkglen; 2841 u8 *pkgbuf; 2842 int rc; 2843 2844 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2845 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2846 &index, NULL, &pkglen); 2847 if (rc) 2848 return rc; 2849 2850 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2851 if (!pkgbuf) { 2852 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2853 pkglen); 2854 return -ENOMEM; 2855 } 2856 2857 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 2858 if (rc) 2859 goto err; 2860 2861 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2862 pkglen); 2863 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 2864 strscpy(ver, pkgver, size); 2865 else 2866 rc = -ENOENT; 2867 2868 err: 2869 kfree(pkgbuf); 2870 2871 return rc; 2872 } 2873 2874 static void bnxt_get_pkgver(struct net_device *dev) 2875 { 2876 struct bnxt *bp = netdev_priv(dev); 2877 char buf[FW_VER_STR_LEN]; 2878 int len; 2879 2880 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 2881 len = strlen(bp->fw_ver_str); 2882 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2883 "/pkg %s", buf); 2884 } 2885 } 2886 2887 static int bnxt_get_eeprom(struct net_device *dev, 2888 struct ethtool_eeprom *eeprom, 2889 u8 *data) 2890 { 2891 u32 index; 2892 u32 offset; 2893 2894 if (eeprom->offset == 0) /* special offset value to get directory */ 2895 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2896 2897 index = eeprom->offset >> 24; 2898 offset = eeprom->offset & 0xffffff; 2899 2900 if (index == 0) { 2901 netdev_err(dev, "unsupported index value: %d\n", index); 2902 return -EINVAL; 2903 } 2904 2905 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2906 } 2907 2908 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2909 { 2910 struct hwrm_nvm_erase_dir_entry_input *req; 2911 struct bnxt *bp = netdev_priv(dev); 2912 int rc; 2913 2914 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 2915 if (rc) 2916 return rc; 2917 2918 req->dir_idx = cpu_to_le16(index); 2919 return hwrm_req_send(bp, req); 2920 } 2921 2922 static int bnxt_set_eeprom(struct net_device *dev, 2923 struct ethtool_eeprom *eeprom, 2924 u8 *data) 2925 { 2926 struct bnxt *bp = netdev_priv(dev); 2927 u8 index, dir_op; 2928 u16 type, ext, ordinal, attr; 2929 2930 if (!BNXT_PF(bp)) { 2931 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2932 return -EINVAL; 2933 } 2934 2935 type = eeprom->magic >> 16; 2936 2937 if (type == 0xffff) { /* special value for directory operations */ 2938 index = eeprom->magic & 0xff; 2939 dir_op = eeprom->magic >> 8; 2940 if (index == 0) 2941 return -EINVAL; 2942 switch (dir_op) { 2943 case 0x0e: /* erase */ 2944 if (eeprom->offset != ~eeprom->magic) 2945 return -EINVAL; 2946 return bnxt_erase_nvram_directory(dev, index - 1); 2947 default: 2948 return -EINVAL; 2949 } 2950 } 2951 2952 /* Create or re-write an NVM item: */ 2953 if (bnxt_dir_type_is_executable(type)) 2954 return -EOPNOTSUPP; 2955 ext = eeprom->magic & 0xffff; 2956 ordinal = eeprom->offset >> 16; 2957 attr = eeprom->offset & 0xffff; 2958 2959 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 2960 eeprom->len); 2961 } 2962 2963 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2964 { 2965 struct bnxt *bp = netdev_priv(dev); 2966 struct ethtool_eee *eee = &bp->eee; 2967 struct bnxt_link_info *link_info = &bp->link_info; 2968 u32 advertising; 2969 int rc = 0; 2970 2971 if (!BNXT_PHY_CFG_ABLE(bp)) 2972 return -EOPNOTSUPP; 2973 2974 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 2975 return -EOPNOTSUPP; 2976 2977 mutex_lock(&bp->link_lock); 2978 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2979 if (!edata->eee_enabled) 2980 goto eee_ok; 2981 2982 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2983 netdev_warn(dev, "EEE requires autoneg\n"); 2984 rc = -EINVAL; 2985 goto eee_exit; 2986 } 2987 if (edata->tx_lpi_enabled) { 2988 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2989 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2990 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2991 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2992 rc = -EINVAL; 2993 goto eee_exit; 2994 } else if (!bp->lpi_tmr_hi) { 2995 edata->tx_lpi_timer = eee->tx_lpi_timer; 2996 } 2997 } 2998 if (!edata->advertised) { 2999 edata->advertised = advertising & eee->supported; 3000 } else if (edata->advertised & ~advertising) { 3001 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3002 edata->advertised, advertising); 3003 rc = -EINVAL; 3004 goto eee_exit; 3005 } 3006 3007 eee->advertised = edata->advertised; 3008 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3009 eee->tx_lpi_timer = edata->tx_lpi_timer; 3010 eee_ok: 3011 eee->eee_enabled = edata->eee_enabled; 3012 3013 if (netif_running(dev)) 3014 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3015 3016 eee_exit: 3017 mutex_unlock(&bp->link_lock); 3018 return rc; 3019 } 3020 3021 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3022 { 3023 struct bnxt *bp = netdev_priv(dev); 3024 3025 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3026 return -EOPNOTSUPP; 3027 3028 *edata = bp->eee; 3029 if (!bp->eee.eee_enabled) { 3030 /* Preserve tx_lpi_timer so that the last value will be used 3031 * by default when it is re-enabled. 3032 */ 3033 edata->advertised = 0; 3034 edata->tx_lpi_enabled = 0; 3035 } 3036 3037 if (!bp->eee.eee_active) 3038 edata->lp_advertised = 0; 3039 3040 return 0; 3041 } 3042 3043 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3044 u16 page_number, u16 start_addr, 3045 u16 data_length, u8 *buf) 3046 { 3047 struct hwrm_port_phy_i2c_read_output *output; 3048 struct hwrm_port_phy_i2c_read_input *req; 3049 int rc, byte_offset = 0; 3050 3051 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3052 if (rc) 3053 return rc; 3054 3055 output = hwrm_req_hold(bp, req); 3056 req->i2c_slave_addr = i2c_addr; 3057 req->page_number = cpu_to_le16(page_number); 3058 req->port_id = cpu_to_le16(bp->pf.port_id); 3059 do { 3060 u16 xfer_size; 3061 3062 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3063 data_length -= xfer_size; 3064 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3065 req->data_length = xfer_size; 3066 req->enables = cpu_to_le32(start_addr + byte_offset ? 3067 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 3068 rc = hwrm_req_send(bp, req); 3069 if (!rc) 3070 memcpy(buf + byte_offset, output->data, xfer_size); 3071 byte_offset += xfer_size; 3072 } while (!rc && data_length > 0); 3073 hwrm_req_drop(bp, req); 3074 3075 return rc; 3076 } 3077 3078 static int bnxt_get_module_info(struct net_device *dev, 3079 struct ethtool_modinfo *modinfo) 3080 { 3081 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 3082 struct bnxt *bp = netdev_priv(dev); 3083 int rc; 3084 3085 /* No point in going further if phy status indicates 3086 * module is not inserted or if it is powered down or 3087 * if it is of type 10GBase-T 3088 */ 3089 if (bp->link_info.module_status > 3090 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3091 return -EOPNOTSUPP; 3092 3093 /* This feature is not supported in older firmware versions */ 3094 if (bp->hwrm_spec_code < 0x10202) 3095 return -EOPNOTSUPP; 3096 3097 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3098 SFF_DIAG_SUPPORT_OFFSET + 1, 3099 data); 3100 if (!rc) { 3101 u8 module_id = data[0]; 3102 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 3103 3104 switch (module_id) { 3105 case SFF_MODULE_ID_SFP: 3106 modinfo->type = ETH_MODULE_SFF_8472; 3107 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3108 if (!diag_supported) 3109 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3110 break; 3111 case SFF_MODULE_ID_QSFP: 3112 case SFF_MODULE_ID_QSFP_PLUS: 3113 modinfo->type = ETH_MODULE_SFF_8436; 3114 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3115 break; 3116 case SFF_MODULE_ID_QSFP28: 3117 modinfo->type = ETH_MODULE_SFF_8636; 3118 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 3119 break; 3120 default: 3121 rc = -EOPNOTSUPP; 3122 break; 3123 } 3124 } 3125 return rc; 3126 } 3127 3128 static int bnxt_get_module_eeprom(struct net_device *dev, 3129 struct ethtool_eeprom *eeprom, 3130 u8 *data) 3131 { 3132 struct bnxt *bp = netdev_priv(dev); 3133 u16 start = eeprom->offset, length = eeprom->len; 3134 int rc = 0; 3135 3136 memset(data, 0, eeprom->len); 3137 3138 /* Read A0 portion of the EEPROM */ 3139 if (start < ETH_MODULE_SFF_8436_LEN) { 3140 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3141 length = ETH_MODULE_SFF_8436_LEN - start; 3142 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3143 start, length, data); 3144 if (rc) 3145 return rc; 3146 start += length; 3147 data += length; 3148 length = eeprom->len - length; 3149 } 3150 3151 /* Read A2 portion of the EEPROM */ 3152 if (length) { 3153 start -= ETH_MODULE_SFF_8436_LEN; 3154 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 3155 start, length, data); 3156 } 3157 return rc; 3158 } 3159 3160 static int bnxt_nway_reset(struct net_device *dev) 3161 { 3162 int rc = 0; 3163 3164 struct bnxt *bp = netdev_priv(dev); 3165 struct bnxt_link_info *link_info = &bp->link_info; 3166 3167 if (!BNXT_PHY_CFG_ABLE(bp)) 3168 return -EOPNOTSUPP; 3169 3170 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3171 return -EINVAL; 3172 3173 if (netif_running(dev)) 3174 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3175 3176 return rc; 3177 } 3178 3179 static int bnxt_set_phys_id(struct net_device *dev, 3180 enum ethtool_phys_id_state state) 3181 { 3182 struct hwrm_port_led_cfg_input *req; 3183 struct bnxt *bp = netdev_priv(dev); 3184 struct bnxt_pf_info *pf = &bp->pf; 3185 struct bnxt_led_cfg *led_cfg; 3186 u8 led_state; 3187 __le16 duration; 3188 int rc, i; 3189 3190 if (!bp->num_leds || BNXT_VF(bp)) 3191 return -EOPNOTSUPP; 3192 3193 if (state == ETHTOOL_ID_ACTIVE) { 3194 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3195 duration = cpu_to_le16(500); 3196 } else if (state == ETHTOOL_ID_INACTIVE) { 3197 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3198 duration = cpu_to_le16(0); 3199 } else { 3200 return -EINVAL; 3201 } 3202 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 3203 if (rc) 3204 return rc; 3205 3206 req->port_id = cpu_to_le16(pf->port_id); 3207 req->num_leds = bp->num_leds; 3208 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 3209 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3210 req->enables |= BNXT_LED_DFLT_ENABLES(i); 3211 led_cfg->led_id = bp->leds[i].led_id; 3212 led_cfg->led_state = led_state; 3213 led_cfg->led_blink_on = duration; 3214 led_cfg->led_blink_off = duration; 3215 led_cfg->led_group_id = bp->leds[i].led_group_id; 3216 } 3217 return hwrm_req_send(bp, req); 3218 } 3219 3220 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3221 { 3222 struct hwrm_selftest_irq_input *req; 3223 int rc; 3224 3225 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 3226 if (rc) 3227 return rc; 3228 3229 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3230 return hwrm_req_send(bp, req); 3231 } 3232 3233 static int bnxt_test_irq(struct bnxt *bp) 3234 { 3235 int i; 3236 3237 for (i = 0; i < bp->cp_nr_rings; i++) { 3238 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3239 int rc; 3240 3241 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3242 if (rc) 3243 return rc; 3244 } 3245 return 0; 3246 } 3247 3248 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3249 { 3250 struct hwrm_port_mac_cfg_input *req; 3251 int rc; 3252 3253 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 3254 if (rc) 3255 return rc; 3256 3257 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3258 if (enable) 3259 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3260 else 3261 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3262 return hwrm_req_send(bp, req); 3263 } 3264 3265 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3266 { 3267 struct hwrm_port_phy_qcaps_output *resp; 3268 struct hwrm_port_phy_qcaps_input *req; 3269 int rc; 3270 3271 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 3272 if (rc) 3273 return rc; 3274 3275 resp = hwrm_req_hold(bp, req); 3276 rc = hwrm_req_send(bp, req); 3277 if (!rc) 3278 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3279 3280 hwrm_req_drop(bp, req); 3281 return rc; 3282 } 3283 3284 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3285 struct hwrm_port_phy_cfg_input *req) 3286 { 3287 struct bnxt_link_info *link_info = &bp->link_info; 3288 u16 fw_advertising; 3289 u16 fw_speed; 3290 int rc; 3291 3292 if (!link_info->autoneg || 3293 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 3294 return 0; 3295 3296 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3297 if (rc) 3298 return rc; 3299 3300 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3301 if (bp->link_info.link_up) 3302 fw_speed = bp->link_info.link_speed; 3303 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3304 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3305 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3306 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3307 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3308 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3309 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3310 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3311 3312 req->force_link_speed = cpu_to_le16(fw_speed); 3313 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3314 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3315 rc = hwrm_req_send(bp, req); 3316 req->flags = 0; 3317 req->force_link_speed = cpu_to_le16(0); 3318 return rc; 3319 } 3320 3321 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3322 { 3323 struct hwrm_port_phy_cfg_input *req; 3324 int rc; 3325 3326 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3327 if (rc) 3328 return rc; 3329 3330 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 3331 hwrm_req_hold(bp, req); 3332 3333 if (enable) { 3334 bnxt_disable_an_for_lpbk(bp, req); 3335 if (ext) 3336 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3337 else 3338 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3339 } else { 3340 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3341 } 3342 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3343 rc = hwrm_req_send(bp, req); 3344 hwrm_req_drop(bp, req); 3345 return rc; 3346 } 3347 3348 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3349 u32 raw_cons, int pkt_size) 3350 { 3351 struct bnxt_napi *bnapi = cpr->bnapi; 3352 struct bnxt_rx_ring_info *rxr; 3353 struct bnxt_sw_rx_bd *rx_buf; 3354 struct rx_cmp *rxcmp; 3355 u16 cp_cons, cons; 3356 u8 *data; 3357 u32 len; 3358 int i; 3359 3360 rxr = bnapi->rx_ring; 3361 cp_cons = RING_CMP(raw_cons); 3362 rxcmp = (struct rx_cmp *) 3363 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3364 cons = rxcmp->rx_cmp_opaque; 3365 rx_buf = &rxr->rx_buf_ring[cons]; 3366 data = rx_buf->data_ptr; 3367 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3368 if (len != pkt_size) 3369 return -EIO; 3370 i = ETH_ALEN; 3371 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3372 return -EIO; 3373 i += ETH_ALEN; 3374 for ( ; i < pkt_size; i++) { 3375 if (data[i] != (u8)(i & 0xff)) 3376 return -EIO; 3377 } 3378 return 0; 3379 } 3380 3381 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3382 int pkt_size) 3383 { 3384 struct tx_cmp *txcmp; 3385 int rc = -EIO; 3386 u32 raw_cons; 3387 u32 cons; 3388 int i; 3389 3390 raw_cons = cpr->cp_raw_cons; 3391 for (i = 0; i < 200; i++) { 3392 cons = RING_CMP(raw_cons); 3393 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3394 3395 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3396 udelay(5); 3397 continue; 3398 } 3399 3400 /* The valid test of the entry must be done first before 3401 * reading any further. 3402 */ 3403 dma_rmb(); 3404 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3405 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3406 raw_cons = NEXT_RAW_CMP(raw_cons); 3407 raw_cons = NEXT_RAW_CMP(raw_cons); 3408 break; 3409 } 3410 raw_cons = NEXT_RAW_CMP(raw_cons); 3411 } 3412 cpr->cp_raw_cons = raw_cons; 3413 return rc; 3414 } 3415 3416 static int bnxt_run_loopback(struct bnxt *bp) 3417 { 3418 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3419 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3420 struct bnxt_cp_ring_info *cpr; 3421 int pkt_size, i = 0; 3422 struct sk_buff *skb; 3423 dma_addr_t map; 3424 u8 *data; 3425 int rc; 3426 3427 cpr = &rxr->bnapi->cp_ring; 3428 if (bp->flags & BNXT_FLAG_CHIP_P5) 3429 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3430 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3431 skb = netdev_alloc_skb(bp->dev, pkt_size); 3432 if (!skb) 3433 return -ENOMEM; 3434 data = skb_put(skb, pkt_size); 3435 eth_broadcast_addr(data); 3436 i += ETH_ALEN; 3437 ether_addr_copy(&data[i], bp->dev->dev_addr); 3438 i += ETH_ALEN; 3439 for ( ; i < pkt_size; i++) 3440 data[i] = (u8)(i & 0xff); 3441 3442 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3443 DMA_TO_DEVICE); 3444 if (dma_mapping_error(&bp->pdev->dev, map)) { 3445 dev_kfree_skb(skb); 3446 return -EIO; 3447 } 3448 bnxt_xmit_bd(bp, txr, map, pkt_size); 3449 3450 /* Sync BD data before updating doorbell */ 3451 wmb(); 3452 3453 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3454 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3455 3456 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 3457 dev_kfree_skb(skb); 3458 return rc; 3459 } 3460 3461 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3462 { 3463 struct hwrm_selftest_exec_output *resp; 3464 struct hwrm_selftest_exec_input *req; 3465 int rc; 3466 3467 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 3468 if (rc) 3469 return rc; 3470 3471 hwrm_req_timeout(bp, req, bp->test_info->timeout); 3472 req->flags = test_mask; 3473 3474 resp = hwrm_req_hold(bp, req); 3475 rc = hwrm_req_send(bp, req); 3476 *test_results = resp->test_success; 3477 hwrm_req_drop(bp, req); 3478 return rc; 3479 } 3480 3481 #define BNXT_DRV_TESTS 4 3482 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3483 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3484 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3485 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3486 3487 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3488 u64 *buf) 3489 { 3490 struct bnxt *bp = netdev_priv(dev); 3491 bool do_ext_lpbk = false; 3492 bool offline = false; 3493 u8 test_results = 0; 3494 u8 test_mask = 0; 3495 int rc = 0, i; 3496 3497 if (!bp->num_tests || !BNXT_PF(bp)) 3498 return; 3499 memset(buf, 0, sizeof(u64) * bp->num_tests); 3500 if (!netif_running(dev)) { 3501 etest->flags |= ETH_TEST_FL_FAILED; 3502 return; 3503 } 3504 3505 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3506 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 3507 do_ext_lpbk = true; 3508 3509 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3510 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 3511 etest->flags |= ETH_TEST_FL_FAILED; 3512 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 3513 return; 3514 } 3515 offline = true; 3516 } 3517 3518 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3519 u8 bit_val = 1 << i; 3520 3521 if (!(bp->test_info->offline_mask & bit_val)) 3522 test_mask |= bit_val; 3523 else if (offline) 3524 test_mask |= bit_val; 3525 } 3526 if (!offline) { 3527 bnxt_run_fw_tests(bp, test_mask, &test_results); 3528 } else { 3529 rc = bnxt_close_nic(bp, false, false); 3530 if (rc) 3531 return; 3532 bnxt_run_fw_tests(bp, test_mask, &test_results); 3533 3534 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3535 bnxt_hwrm_mac_loopback(bp, true); 3536 msleep(250); 3537 rc = bnxt_half_open_nic(bp); 3538 if (rc) { 3539 bnxt_hwrm_mac_loopback(bp, false); 3540 etest->flags |= ETH_TEST_FL_FAILED; 3541 return; 3542 } 3543 if (bnxt_run_loopback(bp)) 3544 etest->flags |= ETH_TEST_FL_FAILED; 3545 else 3546 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3547 3548 bnxt_hwrm_mac_loopback(bp, false); 3549 bnxt_hwrm_phy_loopback(bp, true, false); 3550 msleep(1000); 3551 if (bnxt_run_loopback(bp)) { 3552 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3553 etest->flags |= ETH_TEST_FL_FAILED; 3554 } 3555 if (do_ext_lpbk) { 3556 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3557 bnxt_hwrm_phy_loopback(bp, true, true); 3558 msleep(1000); 3559 if (bnxt_run_loopback(bp)) { 3560 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3561 etest->flags |= ETH_TEST_FL_FAILED; 3562 } 3563 } 3564 bnxt_hwrm_phy_loopback(bp, false, false); 3565 bnxt_half_close_nic(bp); 3566 rc = bnxt_open_nic(bp, false, true); 3567 } 3568 if (rc || bnxt_test_irq(bp)) { 3569 buf[BNXT_IRQ_TEST_IDX] = 1; 3570 etest->flags |= ETH_TEST_FL_FAILED; 3571 } 3572 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3573 u8 bit_val = 1 << i; 3574 3575 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3576 buf[i] = 1; 3577 etest->flags |= ETH_TEST_FL_FAILED; 3578 } 3579 } 3580 } 3581 3582 static int bnxt_reset(struct net_device *dev, u32 *flags) 3583 { 3584 struct bnxt *bp = netdev_priv(dev); 3585 bool reload = false; 3586 u32 req = *flags; 3587 3588 if (!req) 3589 return -EINVAL; 3590 3591 if (!BNXT_PF(bp)) { 3592 netdev_err(dev, "Reset is not supported from a VF\n"); 3593 return -EOPNOTSUPP; 3594 } 3595 3596 if (pci_vfs_assigned(bp->pdev) && 3597 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3598 netdev_err(dev, 3599 "Reset not allowed when VFs are assigned to VMs\n"); 3600 return -EBUSY; 3601 } 3602 3603 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3604 /* This feature is not supported in older firmware versions */ 3605 if (bp->hwrm_spec_code >= 0x10803) { 3606 if (!bnxt_firmware_reset_chip(dev)) { 3607 netdev_info(dev, "Firmware reset request successful.\n"); 3608 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3609 reload = true; 3610 *flags &= ~BNXT_FW_RESET_CHIP; 3611 } 3612 } else if (req == BNXT_FW_RESET_CHIP) { 3613 return -EOPNOTSUPP; /* only request, fail hard */ 3614 } 3615 } 3616 3617 if (req & BNXT_FW_RESET_AP) { 3618 /* This feature is not supported in older firmware versions */ 3619 if (bp->hwrm_spec_code >= 0x10803) { 3620 if (!bnxt_firmware_reset_ap(dev)) { 3621 netdev_info(dev, "Reset application processor successful.\n"); 3622 reload = true; 3623 *flags &= ~BNXT_FW_RESET_AP; 3624 } 3625 } else if (req == BNXT_FW_RESET_AP) { 3626 return -EOPNOTSUPP; /* only request, fail hard */ 3627 } 3628 } 3629 3630 if (reload) 3631 netdev_info(dev, "Reload driver to complete reset\n"); 3632 3633 return 0; 3634 } 3635 3636 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3637 { 3638 struct bnxt *bp = netdev_priv(dev); 3639 3640 if (dump->flag > BNXT_DUMP_CRASH) { 3641 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3642 return -EINVAL; 3643 } 3644 3645 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3646 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3647 return -EOPNOTSUPP; 3648 } 3649 3650 bp->dump_flag = dump->flag; 3651 return 0; 3652 } 3653 3654 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3655 { 3656 struct bnxt *bp = netdev_priv(dev); 3657 3658 if (bp->hwrm_spec_code < 0x10801) 3659 return -EOPNOTSUPP; 3660 3661 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3662 bp->ver_resp.hwrm_fw_min_8b << 16 | 3663 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3664 bp->ver_resp.hwrm_fw_rsvd_8b; 3665 3666 dump->flag = bp->dump_flag; 3667 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 3668 return 0; 3669 } 3670 3671 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3672 void *buf) 3673 { 3674 struct bnxt *bp = netdev_priv(dev); 3675 3676 if (bp->hwrm_spec_code < 0x10801) 3677 return -EOPNOTSUPP; 3678 3679 memset(buf, 0, dump->len); 3680 3681 dump->flag = bp->dump_flag; 3682 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 3683 } 3684 3685 static int bnxt_get_ts_info(struct net_device *dev, 3686 struct ethtool_ts_info *info) 3687 { 3688 struct bnxt *bp = netdev_priv(dev); 3689 struct bnxt_ptp_cfg *ptp; 3690 3691 ptp = bp->ptp_cfg; 3692 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3693 SOF_TIMESTAMPING_RX_SOFTWARE | 3694 SOF_TIMESTAMPING_SOFTWARE; 3695 3696 info->phc_index = -1; 3697 if (!ptp) 3698 return 0; 3699 3700 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 3701 SOF_TIMESTAMPING_RX_HARDWARE | 3702 SOF_TIMESTAMPING_RAW_HARDWARE; 3703 if (ptp->ptp_clock) 3704 info->phc_index = ptp_clock_index(ptp->ptp_clock); 3705 3706 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 3707 3708 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3709 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 3710 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 3711 return 0; 3712 } 3713 3714 void bnxt_ethtool_init(struct bnxt *bp) 3715 { 3716 struct hwrm_selftest_qlist_output *resp; 3717 struct hwrm_selftest_qlist_input *req; 3718 struct bnxt_test_info *test_info; 3719 struct net_device *dev = bp->dev; 3720 int i, rc; 3721 3722 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3723 bnxt_get_pkgver(dev); 3724 3725 bp->num_tests = 0; 3726 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 3727 return; 3728 3729 test_info = bp->test_info; 3730 if (!test_info) { 3731 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3732 if (!test_info) 3733 return; 3734 bp->test_info = test_info; 3735 } 3736 3737 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 3738 return; 3739 3740 resp = hwrm_req_hold(bp, req); 3741 rc = hwrm_req_send_silent(bp, req); 3742 if (rc) 3743 goto ethtool_init_exit; 3744 3745 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3746 if (bp->num_tests > BNXT_MAX_TEST) 3747 bp->num_tests = BNXT_MAX_TEST; 3748 3749 test_info->offline_mask = resp->offline_tests; 3750 test_info->timeout = le16_to_cpu(resp->test_timeout); 3751 if (!test_info->timeout) 3752 test_info->timeout = HWRM_CMD_TIMEOUT; 3753 for (i = 0; i < bp->num_tests; i++) { 3754 char *str = test_info->string[i]; 3755 char *fw_str = resp->test0_name + i * 32; 3756 3757 if (i == BNXT_MACLPBK_TEST_IDX) { 3758 strcpy(str, "Mac loopback test (offline)"); 3759 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3760 strcpy(str, "Phy loopback test (offline)"); 3761 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3762 strcpy(str, "Ext loopback test (offline)"); 3763 } else if (i == BNXT_IRQ_TEST_IDX) { 3764 strcpy(str, "Interrupt_test (offline)"); 3765 } else { 3766 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3767 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3768 if (test_info->offline_mask & (1 << i)) 3769 strncat(str, " (offline)", 3770 ETH_GSTRING_LEN - strlen(str)); 3771 else 3772 strncat(str, " (online)", 3773 ETH_GSTRING_LEN - strlen(str)); 3774 } 3775 } 3776 3777 ethtool_init_exit: 3778 hwrm_req_drop(bp, req); 3779 } 3780 3781 static void bnxt_get_eth_phy_stats(struct net_device *dev, 3782 struct ethtool_eth_phy_stats *phy_stats) 3783 { 3784 struct bnxt *bp = netdev_priv(dev); 3785 u64 *rx; 3786 3787 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 3788 return; 3789 3790 rx = bp->rx_port_stats_ext.sw_stats; 3791 phy_stats->SymbolErrorDuringCarrier = 3792 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 3793 } 3794 3795 static void bnxt_get_eth_mac_stats(struct net_device *dev, 3796 struct ethtool_eth_mac_stats *mac_stats) 3797 { 3798 struct bnxt *bp = netdev_priv(dev); 3799 u64 *rx, *tx; 3800 3801 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3802 return; 3803 3804 rx = bp->port_stats.sw_stats; 3805 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3806 3807 mac_stats->FramesReceivedOK = 3808 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 3809 mac_stats->FramesTransmittedOK = 3810 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 3811 mac_stats->FrameCheckSequenceErrors = 3812 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 3813 mac_stats->AlignmentErrors = 3814 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 3815 mac_stats->OutOfRangeLengthField = 3816 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 3817 } 3818 3819 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 3820 struct ethtool_eth_ctrl_stats *ctrl_stats) 3821 { 3822 struct bnxt *bp = netdev_priv(dev); 3823 u64 *rx; 3824 3825 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3826 return; 3827 3828 rx = bp->port_stats.sw_stats; 3829 ctrl_stats->MACControlFramesReceived = 3830 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 3831 } 3832 3833 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 3834 { 0, 64 }, 3835 { 65, 127 }, 3836 { 128, 255 }, 3837 { 256, 511 }, 3838 { 512, 1023 }, 3839 { 1024, 1518 }, 3840 { 1519, 2047 }, 3841 { 2048, 4095 }, 3842 { 4096, 9216 }, 3843 { 9217, 16383 }, 3844 {} 3845 }; 3846 3847 static void bnxt_get_rmon_stats(struct net_device *dev, 3848 struct ethtool_rmon_stats *rmon_stats, 3849 const struct ethtool_rmon_hist_range **ranges) 3850 { 3851 struct bnxt *bp = netdev_priv(dev); 3852 u64 *rx, *tx; 3853 3854 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 3855 return; 3856 3857 rx = bp->port_stats.sw_stats; 3858 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 3859 3860 rmon_stats->jabbers = 3861 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 3862 rmon_stats->oversize_pkts = 3863 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 3864 rmon_stats->undersize_pkts = 3865 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 3866 3867 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 3868 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 3869 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 3870 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 3871 rmon_stats->hist[4] = 3872 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 3873 rmon_stats->hist[5] = 3874 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 3875 rmon_stats->hist[6] = 3876 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 3877 rmon_stats->hist[7] = 3878 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 3879 rmon_stats->hist[8] = 3880 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 3881 rmon_stats->hist[9] = 3882 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 3883 3884 rmon_stats->hist_tx[0] = 3885 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 3886 rmon_stats->hist_tx[1] = 3887 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 3888 rmon_stats->hist_tx[2] = 3889 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 3890 rmon_stats->hist_tx[3] = 3891 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 3892 rmon_stats->hist_tx[4] = 3893 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 3894 rmon_stats->hist_tx[5] = 3895 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 3896 rmon_stats->hist_tx[6] = 3897 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 3898 rmon_stats->hist_tx[7] = 3899 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 3900 rmon_stats->hist_tx[8] = 3901 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 3902 rmon_stats->hist_tx[9] = 3903 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 3904 3905 *ranges = bnxt_rmon_ranges; 3906 } 3907 3908 void bnxt_ethtool_free(struct bnxt *bp) 3909 { 3910 kfree(bp->test_info); 3911 bp->test_info = NULL; 3912 } 3913 3914 const struct ethtool_ops bnxt_ethtool_ops = { 3915 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3916 ETHTOOL_COALESCE_MAX_FRAMES | 3917 ETHTOOL_COALESCE_USECS_IRQ | 3918 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3919 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3920 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3921 .get_link_ksettings = bnxt_get_link_ksettings, 3922 .set_link_ksettings = bnxt_set_link_ksettings, 3923 .get_fec_stats = bnxt_get_fec_stats, 3924 .get_fecparam = bnxt_get_fecparam, 3925 .set_fecparam = bnxt_set_fecparam, 3926 .get_pause_stats = bnxt_get_pause_stats, 3927 .get_pauseparam = bnxt_get_pauseparam, 3928 .set_pauseparam = bnxt_set_pauseparam, 3929 .get_drvinfo = bnxt_get_drvinfo, 3930 .get_regs_len = bnxt_get_regs_len, 3931 .get_regs = bnxt_get_regs, 3932 .get_wol = bnxt_get_wol, 3933 .set_wol = bnxt_set_wol, 3934 .get_coalesce = bnxt_get_coalesce, 3935 .set_coalesce = bnxt_set_coalesce, 3936 .get_msglevel = bnxt_get_msglevel, 3937 .set_msglevel = bnxt_set_msglevel, 3938 .get_sset_count = bnxt_get_sset_count, 3939 .get_strings = bnxt_get_strings, 3940 .get_ethtool_stats = bnxt_get_ethtool_stats, 3941 .set_ringparam = bnxt_set_ringparam, 3942 .get_ringparam = bnxt_get_ringparam, 3943 .get_channels = bnxt_get_channels, 3944 .set_channels = bnxt_set_channels, 3945 .get_rxnfc = bnxt_get_rxnfc, 3946 .set_rxnfc = bnxt_set_rxnfc, 3947 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3948 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3949 .get_rxfh = bnxt_get_rxfh, 3950 .set_rxfh = bnxt_set_rxfh, 3951 .flash_device = bnxt_flash_device, 3952 .get_eeprom_len = bnxt_get_eeprom_len, 3953 .get_eeprom = bnxt_get_eeprom, 3954 .set_eeprom = bnxt_set_eeprom, 3955 .get_link = bnxt_get_link, 3956 .get_eee = bnxt_get_eee, 3957 .set_eee = bnxt_set_eee, 3958 .get_module_info = bnxt_get_module_info, 3959 .get_module_eeprom = bnxt_get_module_eeprom, 3960 .nway_reset = bnxt_nway_reset, 3961 .set_phys_id = bnxt_set_phys_id, 3962 .self_test = bnxt_self_test, 3963 .get_ts_info = bnxt_get_ts_info, 3964 .reset = bnxt_reset, 3965 .set_dump = bnxt_set_dump, 3966 .get_dump_flag = bnxt_get_dump_flag, 3967 .get_dump_data = bnxt_get_dump_data, 3968 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 3969 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 3970 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 3971 .get_rmon_stats = bnxt_get_rmon_stats, 3972 }; 3973