1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/etherdevice.h> 17 #include <linux/crc32.h> 18 #include <linux/firmware.h> 19 #include <linux/utsname.h> 20 #include <linux/time.h> 21 #include "bnxt_hsi.h" 22 #include "bnxt.h" 23 #include "bnxt_xdp.h" 24 #include "bnxt_ethtool.h" 25 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 26 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 27 #include "bnxt_coredump.h" 28 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 29 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 30 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 32 static u32 bnxt_get_msglevel(struct net_device *dev) 33 { 34 struct bnxt *bp = netdev_priv(dev); 35 36 return bp->msg_enable; 37 } 38 39 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 40 { 41 struct bnxt *bp = netdev_priv(dev); 42 43 bp->msg_enable = value; 44 } 45 46 static int bnxt_get_coalesce(struct net_device *dev, 47 struct ethtool_coalesce *coal) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 struct bnxt_coal *hw_coal; 51 u16 mult; 52 53 memset(coal, 0, sizeof(*coal)); 54 55 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 56 57 hw_coal = &bp->rx_coal; 58 mult = hw_coal->bufs_per_record; 59 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 60 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 61 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 62 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 63 64 hw_coal = &bp->tx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 71 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 72 73 return 0; 74 } 75 76 static int bnxt_set_coalesce(struct net_device *dev, 77 struct ethtool_coalesce *coal) 78 { 79 struct bnxt *bp = netdev_priv(dev); 80 bool update_stats = false; 81 struct bnxt_coal *hw_coal; 82 int rc = 0; 83 u16 mult; 84 85 if (coal->use_adaptive_rx_coalesce) { 86 bp->flags |= BNXT_FLAG_DIM; 87 } else { 88 if (bp->flags & BNXT_FLAG_DIM) { 89 bp->flags &= ~(BNXT_FLAG_DIM); 90 goto reset_coalesce; 91 } 92 } 93 94 hw_coal = &bp->rx_coal; 95 mult = hw_coal->bufs_per_record; 96 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 97 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 98 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 99 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 100 101 hw_coal = &bp->tx_coal; 102 mult = hw_coal->bufs_per_record; 103 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 104 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 105 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 106 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 107 108 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 109 u32 stats_ticks = coal->stats_block_coalesce_usecs; 110 111 /* Allow 0, which means disable. */ 112 if (stats_ticks) 113 stats_ticks = clamp_t(u32, stats_ticks, 114 BNXT_MIN_STATS_COAL_TICKS, 115 BNXT_MAX_STATS_COAL_TICKS); 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 117 bp->stats_coal_ticks = stats_ticks; 118 if (bp->stats_coal_ticks) 119 bp->current_interval = 120 bp->stats_coal_ticks * HZ / 1000000; 121 else 122 bp->current_interval = BNXT_TIMER_INTERVAL; 123 update_stats = true; 124 } 125 126 reset_coalesce: 127 if (netif_running(dev)) { 128 if (update_stats) { 129 rc = bnxt_close_nic(bp, true, false); 130 if (!rc) 131 rc = bnxt_open_nic(bp, true, false); 132 } else { 133 rc = bnxt_hwrm_set_coal(bp); 134 } 135 } 136 137 return rc; 138 } 139 140 static const char * const bnxt_ring_stats_str[] = { 141 "rx_ucast_packets", 142 "rx_mcast_packets", 143 "rx_bcast_packets", 144 "rx_discards", 145 "rx_drops", 146 "rx_ucast_bytes", 147 "rx_mcast_bytes", 148 "rx_bcast_bytes", 149 "tx_ucast_packets", 150 "tx_mcast_packets", 151 "tx_bcast_packets", 152 "tx_discards", 153 "tx_drops", 154 "tx_ucast_bytes", 155 "tx_mcast_bytes", 156 "tx_bcast_bytes", 157 }; 158 159 static const char * const bnxt_ring_tpa_stats_str[] = { 160 "tpa_packets", 161 "tpa_bytes", 162 "tpa_events", 163 "tpa_aborts", 164 }; 165 166 static const char * const bnxt_ring_tpa2_stats_str[] = { 167 "rx_tpa_eligible_pkt", 168 "rx_tpa_eligible_bytes", 169 "rx_tpa_pkt", 170 "rx_tpa_bytes", 171 "rx_tpa_errors", 172 }; 173 174 static const char * const bnxt_ring_sw_stats_str[] = { 175 "rx_l4_csum_errors", 176 "missed_irqs", 177 }; 178 179 #define BNXT_RX_STATS_ENTRY(counter) \ 180 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 181 182 #define BNXT_TX_STATS_ENTRY(counter) \ 183 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 184 185 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 186 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 187 188 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 189 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 190 191 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 192 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 193 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 194 195 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 196 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 197 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 198 199 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 200 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 201 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 202 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 203 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 204 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 205 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 206 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 207 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 208 209 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 210 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 211 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 212 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 213 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 214 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 215 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 216 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 217 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 218 219 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 220 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 221 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 222 223 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 224 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 225 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 226 227 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 228 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 229 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 230 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 231 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 232 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 233 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 234 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 235 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 236 237 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 238 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 239 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 240 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 241 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 242 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 243 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 244 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 245 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 246 247 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 248 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 249 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 250 251 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 252 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 253 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 254 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 255 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 256 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 257 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 258 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 259 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 260 261 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 262 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 263 __stringify(counter##_pri##n) } 264 265 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 266 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 267 __stringify(counter##_pri##n) } 268 269 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 270 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 271 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 272 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 273 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 274 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 275 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 276 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 277 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 278 279 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 280 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 281 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 282 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 283 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 284 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 285 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 286 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 287 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 288 289 #define BNXT_PCIE_STATS_ENTRY(counter) \ 290 { BNXT_PCIE_STATS_OFFSET(counter), __stringify(counter) } 291 292 enum { 293 RX_TOTAL_DISCARDS, 294 TX_TOTAL_DISCARDS, 295 }; 296 297 static struct { 298 u64 counter; 299 char string[ETH_GSTRING_LEN]; 300 } bnxt_sw_func_stats[] = { 301 {0, "rx_total_discard_pkts"}, 302 {0, "tx_total_discard_pkts"}, 303 }; 304 305 static const struct { 306 long offset; 307 char string[ETH_GSTRING_LEN]; 308 } bnxt_port_stats_arr[] = { 309 BNXT_RX_STATS_ENTRY(rx_64b_frames), 310 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 311 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 312 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 313 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 314 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 315 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 316 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 317 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 318 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 319 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 320 BNXT_RX_STATS_ENTRY(rx_total_frames), 321 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 322 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 323 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 324 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 325 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 326 BNXT_RX_STATS_ENTRY(rx_pause_frames), 327 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 328 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 329 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 330 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 331 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 332 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 333 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 334 BNXT_RX_STATS_ENTRY(rx_good_frames), 335 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 336 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 337 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 338 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 339 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 340 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 341 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 342 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 343 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 344 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 345 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 346 BNXT_RX_STATS_ENTRY(rx_bytes), 347 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 348 BNXT_RX_STATS_ENTRY(rx_runt_frames), 349 BNXT_RX_STATS_ENTRY(rx_stat_discard), 350 BNXT_RX_STATS_ENTRY(rx_stat_err), 351 352 BNXT_TX_STATS_ENTRY(tx_64b_frames), 353 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 354 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 355 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 356 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 357 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 358 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 359 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 360 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 361 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 362 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 363 BNXT_TX_STATS_ENTRY(tx_good_frames), 364 BNXT_TX_STATS_ENTRY(tx_total_frames), 365 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 366 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 367 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 368 BNXT_TX_STATS_ENTRY(tx_pause_frames), 369 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 370 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 371 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 372 BNXT_TX_STATS_ENTRY(tx_err), 373 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 374 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 375 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 376 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 377 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 378 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 379 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 380 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 381 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 382 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 383 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 384 BNXT_TX_STATS_ENTRY(tx_total_collisions), 385 BNXT_TX_STATS_ENTRY(tx_bytes), 386 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 387 BNXT_TX_STATS_ENTRY(tx_stat_discard), 388 BNXT_TX_STATS_ENTRY(tx_stat_error), 389 }; 390 391 static const struct { 392 long offset; 393 char string[ETH_GSTRING_LEN]; 394 } bnxt_port_stats_ext_arr[] = { 395 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 396 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 397 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 398 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 399 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 400 BNXT_RX_STATS_EXT_COS_ENTRIES, 401 BNXT_RX_STATS_EXT_PFC_ENTRIES, 402 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 403 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 404 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 405 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 406 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 407 }; 408 409 static const struct { 410 long offset; 411 char string[ETH_GSTRING_LEN]; 412 } bnxt_tx_port_stats_ext_arr[] = { 413 BNXT_TX_STATS_EXT_COS_ENTRIES, 414 BNXT_TX_STATS_EXT_PFC_ENTRIES, 415 }; 416 417 static const struct { 418 long base_off; 419 char string[ETH_GSTRING_LEN]; 420 } bnxt_rx_bytes_pri_arr[] = { 421 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 422 }; 423 424 static const struct { 425 long base_off; 426 char string[ETH_GSTRING_LEN]; 427 } bnxt_rx_pkts_pri_arr[] = { 428 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 429 }; 430 431 static const struct { 432 long base_off; 433 char string[ETH_GSTRING_LEN]; 434 } bnxt_tx_bytes_pri_arr[] = { 435 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 436 }; 437 438 static const struct { 439 long base_off; 440 char string[ETH_GSTRING_LEN]; 441 } bnxt_tx_pkts_pri_arr[] = { 442 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 443 }; 444 445 static const struct { 446 long offset; 447 char string[ETH_GSTRING_LEN]; 448 } bnxt_pcie_stats_arr[] = { 449 BNXT_PCIE_STATS_ENTRY(pcie_pl_signal_integrity), 450 BNXT_PCIE_STATS_ENTRY(pcie_dl_signal_integrity), 451 BNXT_PCIE_STATS_ENTRY(pcie_tl_signal_integrity), 452 BNXT_PCIE_STATS_ENTRY(pcie_link_integrity), 453 BNXT_PCIE_STATS_ENTRY(pcie_tx_traffic_rate), 454 BNXT_PCIE_STATS_ENTRY(pcie_rx_traffic_rate), 455 BNXT_PCIE_STATS_ENTRY(pcie_tx_dllp_statistics), 456 BNXT_PCIE_STATS_ENTRY(pcie_rx_dllp_statistics), 457 BNXT_PCIE_STATS_ENTRY(pcie_equalization_time), 458 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[0]), 459 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[2]), 460 BNXT_PCIE_STATS_ENTRY(pcie_recovery_histogram), 461 }; 462 463 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 464 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 465 #define BNXT_NUM_STATS_PRI \ 466 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 467 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 468 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 469 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 470 #define BNXT_NUM_PCIE_STATS ARRAY_SIZE(bnxt_pcie_stats_arr) 471 472 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 473 { 474 if (BNXT_SUPPORTS_TPA(bp)) { 475 if (bp->max_tpa_v2) 476 return ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 477 return ARRAY_SIZE(bnxt_ring_tpa_stats_str); 478 } 479 return 0; 480 } 481 482 static int bnxt_get_num_ring_stats(struct bnxt *bp) 483 { 484 int num_stats; 485 486 num_stats = ARRAY_SIZE(bnxt_ring_stats_str) + 487 ARRAY_SIZE(bnxt_ring_sw_stats_str) + 488 bnxt_get_num_tpa_ring_stats(bp); 489 return num_stats * bp->cp_nr_rings; 490 } 491 492 static int bnxt_get_num_stats(struct bnxt *bp) 493 { 494 int num_stats = bnxt_get_num_ring_stats(bp); 495 496 num_stats += BNXT_NUM_SW_FUNC_STATS; 497 498 if (bp->flags & BNXT_FLAG_PORT_STATS) 499 num_stats += BNXT_NUM_PORT_STATS; 500 501 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 502 num_stats += bp->fw_rx_stats_ext_size + 503 bp->fw_tx_stats_ext_size; 504 if (bp->pri2cos_valid) 505 num_stats += BNXT_NUM_STATS_PRI; 506 } 507 508 if (bp->flags & BNXT_FLAG_PCIE_STATS) 509 num_stats += BNXT_NUM_PCIE_STATS; 510 511 return num_stats; 512 } 513 514 static int bnxt_get_sset_count(struct net_device *dev, int sset) 515 { 516 struct bnxt *bp = netdev_priv(dev); 517 518 switch (sset) { 519 case ETH_SS_STATS: 520 return bnxt_get_num_stats(bp); 521 case ETH_SS_TEST: 522 if (!bp->num_tests) 523 return -EOPNOTSUPP; 524 return bp->num_tests; 525 default: 526 return -EOPNOTSUPP; 527 } 528 } 529 530 static void bnxt_get_ethtool_stats(struct net_device *dev, 531 struct ethtool_stats *stats, u64 *buf) 532 { 533 u32 i, j = 0; 534 struct bnxt *bp = netdev_priv(dev); 535 u32 stat_fields = ARRAY_SIZE(bnxt_ring_stats_str) + 536 bnxt_get_num_tpa_ring_stats(bp); 537 538 if (!bp->bnapi) { 539 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 540 goto skip_ring_stats; 541 } 542 543 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 544 bnxt_sw_func_stats[i].counter = 0; 545 546 for (i = 0; i < bp->cp_nr_rings; i++) { 547 struct bnxt_napi *bnapi = bp->bnapi[i]; 548 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 549 __le64 *hw_stats = (__le64 *)cpr->hw_stats; 550 int k; 551 552 for (k = 0; k < stat_fields; j++, k++) 553 buf[j] = le64_to_cpu(hw_stats[k]); 554 buf[j++] = cpr->rx_l4_csum_errors; 555 buf[j++] = cpr->missed_irqs; 556 557 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 558 le64_to_cpu(cpr->hw_stats->rx_discard_pkts); 559 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 560 le64_to_cpu(cpr->hw_stats->tx_discard_pkts); 561 } 562 563 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 564 buf[j] = bnxt_sw_func_stats[i].counter; 565 566 skip_ring_stats: 567 if (bp->flags & BNXT_FLAG_PORT_STATS) { 568 __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats; 569 570 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) { 571 buf[j] = le64_to_cpu(*(port_stats + 572 bnxt_port_stats_arr[i].offset)); 573 } 574 } 575 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 576 __le64 *rx_port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext; 577 __le64 *tx_port_stats_ext = (__le64 *)bp->hw_tx_port_stats_ext; 578 579 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 580 buf[j] = le64_to_cpu(*(rx_port_stats_ext + 581 bnxt_port_stats_ext_arr[i].offset)); 582 } 583 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 584 buf[j] = le64_to_cpu(*(tx_port_stats_ext + 585 bnxt_tx_port_stats_ext_arr[i].offset)); 586 } 587 if (bp->pri2cos_valid) { 588 for (i = 0; i < 8; i++, j++) { 589 long n = bnxt_rx_bytes_pri_arr[i].base_off + 590 bp->pri2cos[i]; 591 592 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 593 } 594 for (i = 0; i < 8; i++, j++) { 595 long n = bnxt_rx_pkts_pri_arr[i].base_off + 596 bp->pri2cos[i]; 597 598 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 599 } 600 for (i = 0; i < 8; i++, j++) { 601 long n = bnxt_tx_bytes_pri_arr[i].base_off + 602 bp->pri2cos[i]; 603 604 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 605 } 606 for (i = 0; i < 8; i++, j++) { 607 long n = bnxt_tx_pkts_pri_arr[i].base_off + 608 bp->pri2cos[i]; 609 610 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 611 } 612 } 613 } 614 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 615 __le64 *pcie_stats = (__le64 *)bp->hw_pcie_stats; 616 617 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++, j++) { 618 buf[j] = le64_to_cpu(*(pcie_stats + 619 bnxt_pcie_stats_arr[i].offset)); 620 } 621 } 622 } 623 624 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 625 { 626 struct bnxt *bp = netdev_priv(dev); 627 static const char * const *str; 628 u32 i, j, num_str; 629 630 switch (stringset) { 631 case ETH_SS_STATS: 632 for (i = 0; i < bp->cp_nr_rings; i++) { 633 num_str = ARRAY_SIZE(bnxt_ring_stats_str); 634 for (j = 0; j < num_str; j++) { 635 sprintf(buf, "[%d]: %s", i, 636 bnxt_ring_stats_str[j]); 637 buf += ETH_GSTRING_LEN; 638 } 639 if (!BNXT_SUPPORTS_TPA(bp)) 640 goto skip_tpa_stats; 641 642 if (bp->max_tpa_v2) { 643 num_str = ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 644 str = bnxt_ring_tpa2_stats_str; 645 } else { 646 num_str = ARRAY_SIZE(bnxt_ring_tpa_stats_str); 647 str = bnxt_ring_tpa_stats_str; 648 } 649 for (j = 0; j < num_str; j++) { 650 sprintf(buf, "[%d]: %s", i, str[j]); 651 buf += ETH_GSTRING_LEN; 652 } 653 skip_tpa_stats: 654 num_str = ARRAY_SIZE(bnxt_ring_sw_stats_str); 655 for (j = 0; j < num_str; j++) { 656 sprintf(buf, "[%d]: %s", i, 657 bnxt_ring_sw_stats_str[j]); 658 buf += ETH_GSTRING_LEN; 659 } 660 } 661 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 662 strcpy(buf, bnxt_sw_func_stats[i].string); 663 buf += ETH_GSTRING_LEN; 664 } 665 666 if (bp->flags & BNXT_FLAG_PORT_STATS) { 667 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 668 strcpy(buf, bnxt_port_stats_arr[i].string); 669 buf += ETH_GSTRING_LEN; 670 } 671 } 672 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 673 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 674 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 675 buf += ETH_GSTRING_LEN; 676 } 677 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 678 strcpy(buf, 679 bnxt_tx_port_stats_ext_arr[i].string); 680 buf += ETH_GSTRING_LEN; 681 } 682 if (bp->pri2cos_valid) { 683 for (i = 0; i < 8; i++) { 684 strcpy(buf, 685 bnxt_rx_bytes_pri_arr[i].string); 686 buf += ETH_GSTRING_LEN; 687 } 688 for (i = 0; i < 8; i++) { 689 strcpy(buf, 690 bnxt_rx_pkts_pri_arr[i].string); 691 buf += ETH_GSTRING_LEN; 692 } 693 for (i = 0; i < 8; i++) { 694 strcpy(buf, 695 bnxt_tx_bytes_pri_arr[i].string); 696 buf += ETH_GSTRING_LEN; 697 } 698 for (i = 0; i < 8; i++) { 699 strcpy(buf, 700 bnxt_tx_pkts_pri_arr[i].string); 701 buf += ETH_GSTRING_LEN; 702 } 703 } 704 } 705 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 706 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++) { 707 strcpy(buf, bnxt_pcie_stats_arr[i].string); 708 buf += ETH_GSTRING_LEN; 709 } 710 } 711 break; 712 case ETH_SS_TEST: 713 if (bp->num_tests) 714 memcpy(buf, bp->test_info->string, 715 bp->num_tests * ETH_GSTRING_LEN); 716 break; 717 default: 718 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 719 stringset); 720 break; 721 } 722 } 723 724 static void bnxt_get_ringparam(struct net_device *dev, 725 struct ethtool_ringparam *ering) 726 { 727 struct bnxt *bp = netdev_priv(dev); 728 729 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 730 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 731 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 732 733 ering->rx_pending = bp->rx_ring_size; 734 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 735 ering->tx_pending = bp->tx_ring_size; 736 } 737 738 static int bnxt_set_ringparam(struct net_device *dev, 739 struct ethtool_ringparam *ering) 740 { 741 struct bnxt *bp = netdev_priv(dev); 742 743 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 744 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 745 (ering->tx_pending <= MAX_SKB_FRAGS)) 746 return -EINVAL; 747 748 if (netif_running(dev)) 749 bnxt_close_nic(bp, false, false); 750 751 bp->rx_ring_size = ering->rx_pending; 752 bp->tx_ring_size = ering->tx_pending; 753 bnxt_set_ring_params(bp); 754 755 if (netif_running(dev)) 756 return bnxt_open_nic(bp, false, false); 757 758 return 0; 759 } 760 761 static void bnxt_get_channels(struct net_device *dev, 762 struct ethtool_channels *channel) 763 { 764 struct bnxt *bp = netdev_priv(dev); 765 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 766 int max_rx_rings, max_tx_rings, tcs; 767 int max_tx_sch_inputs; 768 769 /* Get the most up-to-date max_tx_sch_inputs. */ 770 if (BNXT_NEW_RM(bp)) 771 bnxt_hwrm_func_resc_qcaps(bp, false); 772 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 773 774 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 775 if (max_tx_sch_inputs) 776 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 777 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 778 779 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 780 max_rx_rings = 0; 781 max_tx_rings = 0; 782 } 783 if (max_tx_sch_inputs) 784 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 785 786 tcs = netdev_get_num_tc(dev); 787 if (tcs > 1) 788 max_tx_rings /= tcs; 789 790 channel->max_rx = max_rx_rings; 791 channel->max_tx = max_tx_rings; 792 channel->max_other = 0; 793 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 794 channel->combined_count = bp->rx_nr_rings; 795 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 796 channel->combined_count--; 797 } else { 798 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 799 channel->rx_count = bp->rx_nr_rings; 800 channel->tx_count = bp->tx_nr_rings_per_tc; 801 } 802 } 803 } 804 805 static int bnxt_set_channels(struct net_device *dev, 806 struct ethtool_channels *channel) 807 { 808 struct bnxt *bp = netdev_priv(dev); 809 int req_tx_rings, req_rx_rings, tcs; 810 bool sh = false; 811 int tx_xdp = 0; 812 int rc = 0; 813 814 if (channel->other_count) 815 return -EINVAL; 816 817 if (!channel->combined_count && 818 (!channel->rx_count || !channel->tx_count)) 819 return -EINVAL; 820 821 if (channel->combined_count && 822 (channel->rx_count || channel->tx_count)) 823 return -EINVAL; 824 825 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 826 channel->tx_count)) 827 return -EINVAL; 828 829 if (channel->combined_count) 830 sh = true; 831 832 tcs = netdev_get_num_tc(dev); 833 834 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 835 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 836 if (bp->tx_nr_rings_xdp) { 837 if (!sh) { 838 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 839 return -EINVAL; 840 } 841 tx_xdp = req_rx_rings; 842 } 843 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 844 if (rc) { 845 netdev_warn(dev, "Unable to allocate the requested rings\n"); 846 return rc; 847 } 848 849 if (netif_running(dev)) { 850 if (BNXT_PF(bp)) { 851 /* TODO CHIMP_FW: Send message to all VF's 852 * before PF unload 853 */ 854 } 855 rc = bnxt_close_nic(bp, true, false); 856 if (rc) { 857 netdev_err(bp->dev, "Set channel failure rc :%x\n", 858 rc); 859 return rc; 860 } 861 } 862 863 if (sh) { 864 bp->flags |= BNXT_FLAG_SHARED_RINGS; 865 bp->rx_nr_rings = channel->combined_count; 866 bp->tx_nr_rings_per_tc = channel->combined_count; 867 } else { 868 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 869 bp->rx_nr_rings = channel->rx_count; 870 bp->tx_nr_rings_per_tc = channel->tx_count; 871 } 872 bp->tx_nr_rings_xdp = tx_xdp; 873 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 874 if (tcs > 1) 875 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 876 877 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 878 bp->tx_nr_rings + bp->rx_nr_rings; 879 880 /* After changing number of rx channels, update NTUPLE feature. */ 881 netdev_update_features(dev); 882 if (netif_running(dev)) { 883 rc = bnxt_open_nic(bp, true, false); 884 if ((!rc) && BNXT_PF(bp)) { 885 /* TODO CHIMP_FW: Send message to all VF's 886 * to renable 887 */ 888 } 889 } else { 890 rc = bnxt_reserve_rings(bp, true); 891 } 892 893 return rc; 894 } 895 896 #ifdef CONFIG_RFS_ACCEL 897 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 898 u32 *rule_locs) 899 { 900 int i, j = 0; 901 902 cmd->data = bp->ntp_fltr_count; 903 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 904 struct hlist_head *head; 905 struct bnxt_ntuple_filter *fltr; 906 907 head = &bp->ntp_fltr_hash_tbl[i]; 908 rcu_read_lock(); 909 hlist_for_each_entry_rcu(fltr, head, hash) { 910 if (j == cmd->rule_cnt) 911 break; 912 rule_locs[j++] = fltr->sw_id; 913 } 914 rcu_read_unlock(); 915 if (j == cmd->rule_cnt) 916 break; 917 } 918 cmd->rule_cnt = j; 919 return 0; 920 } 921 922 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 923 { 924 struct ethtool_rx_flow_spec *fs = 925 (struct ethtool_rx_flow_spec *)&cmd->fs; 926 struct bnxt_ntuple_filter *fltr; 927 struct flow_keys *fkeys; 928 int i, rc = -EINVAL; 929 930 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 931 return rc; 932 933 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 934 struct hlist_head *head; 935 936 head = &bp->ntp_fltr_hash_tbl[i]; 937 rcu_read_lock(); 938 hlist_for_each_entry_rcu(fltr, head, hash) { 939 if (fltr->sw_id == fs->location) 940 goto fltr_found; 941 } 942 rcu_read_unlock(); 943 } 944 return rc; 945 946 fltr_found: 947 fkeys = &fltr->fkeys; 948 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 949 if (fkeys->basic.ip_proto == IPPROTO_TCP) 950 fs->flow_type = TCP_V4_FLOW; 951 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 952 fs->flow_type = UDP_V4_FLOW; 953 else 954 goto fltr_err; 955 956 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 957 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 958 959 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 960 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 961 962 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 963 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 964 965 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 966 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 967 } else { 968 int i; 969 970 if (fkeys->basic.ip_proto == IPPROTO_TCP) 971 fs->flow_type = TCP_V6_FLOW; 972 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 973 fs->flow_type = UDP_V6_FLOW; 974 else 975 goto fltr_err; 976 977 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 978 fkeys->addrs.v6addrs.src; 979 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 980 fkeys->addrs.v6addrs.dst; 981 for (i = 0; i < 4; i++) { 982 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 983 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 984 } 985 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 986 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 987 988 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 989 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 990 } 991 992 fs->ring_cookie = fltr->rxq; 993 rc = 0; 994 995 fltr_err: 996 rcu_read_unlock(); 997 998 return rc; 999 } 1000 #endif 1001 1002 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1003 { 1004 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1005 return RXH_IP_SRC | RXH_IP_DST; 1006 return 0; 1007 } 1008 1009 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1010 { 1011 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1012 return RXH_IP_SRC | RXH_IP_DST; 1013 return 0; 1014 } 1015 1016 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1017 { 1018 cmd->data = 0; 1019 switch (cmd->flow_type) { 1020 case TCP_V4_FLOW: 1021 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1022 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1023 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1024 cmd->data |= get_ethtool_ipv4_rss(bp); 1025 break; 1026 case UDP_V4_FLOW: 1027 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1028 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1029 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1030 /* fall through */ 1031 case SCTP_V4_FLOW: 1032 case AH_ESP_V4_FLOW: 1033 case AH_V4_FLOW: 1034 case ESP_V4_FLOW: 1035 case IPV4_FLOW: 1036 cmd->data |= get_ethtool_ipv4_rss(bp); 1037 break; 1038 1039 case TCP_V6_FLOW: 1040 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1041 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1042 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1043 cmd->data |= get_ethtool_ipv6_rss(bp); 1044 break; 1045 case UDP_V6_FLOW: 1046 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1047 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1048 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1049 /* fall through */ 1050 case SCTP_V6_FLOW: 1051 case AH_ESP_V6_FLOW: 1052 case AH_V6_FLOW: 1053 case ESP_V6_FLOW: 1054 case IPV6_FLOW: 1055 cmd->data |= get_ethtool_ipv6_rss(bp); 1056 break; 1057 } 1058 return 0; 1059 } 1060 1061 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1062 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1063 1064 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1065 { 1066 u32 rss_hash_cfg = bp->rss_hash_cfg; 1067 int tuple, rc = 0; 1068 1069 if (cmd->data == RXH_4TUPLE) 1070 tuple = 4; 1071 else if (cmd->data == RXH_2TUPLE) 1072 tuple = 2; 1073 else if (!cmd->data) 1074 tuple = 0; 1075 else 1076 return -EINVAL; 1077 1078 if (cmd->flow_type == TCP_V4_FLOW) { 1079 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1080 if (tuple == 4) 1081 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1082 } else if (cmd->flow_type == UDP_V4_FLOW) { 1083 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1084 return -EINVAL; 1085 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1086 if (tuple == 4) 1087 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1088 } else if (cmd->flow_type == TCP_V6_FLOW) { 1089 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1090 if (tuple == 4) 1091 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1092 } else if (cmd->flow_type == UDP_V6_FLOW) { 1093 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1094 return -EINVAL; 1095 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1096 if (tuple == 4) 1097 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1098 } else if (tuple == 4) { 1099 return -EINVAL; 1100 } 1101 1102 switch (cmd->flow_type) { 1103 case TCP_V4_FLOW: 1104 case UDP_V4_FLOW: 1105 case SCTP_V4_FLOW: 1106 case AH_ESP_V4_FLOW: 1107 case AH_V4_FLOW: 1108 case ESP_V4_FLOW: 1109 case IPV4_FLOW: 1110 if (tuple == 2) 1111 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1112 else if (!tuple) 1113 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1114 break; 1115 1116 case TCP_V6_FLOW: 1117 case UDP_V6_FLOW: 1118 case SCTP_V6_FLOW: 1119 case AH_ESP_V6_FLOW: 1120 case AH_V6_FLOW: 1121 case ESP_V6_FLOW: 1122 case IPV6_FLOW: 1123 if (tuple == 2) 1124 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1125 else if (!tuple) 1126 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1127 break; 1128 } 1129 1130 if (bp->rss_hash_cfg == rss_hash_cfg) 1131 return 0; 1132 1133 bp->rss_hash_cfg = rss_hash_cfg; 1134 if (netif_running(bp->dev)) { 1135 bnxt_close_nic(bp, false, false); 1136 rc = bnxt_open_nic(bp, false, false); 1137 } 1138 return rc; 1139 } 1140 1141 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1142 u32 *rule_locs) 1143 { 1144 struct bnxt *bp = netdev_priv(dev); 1145 int rc = 0; 1146 1147 switch (cmd->cmd) { 1148 #ifdef CONFIG_RFS_ACCEL 1149 case ETHTOOL_GRXRINGS: 1150 cmd->data = bp->rx_nr_rings; 1151 break; 1152 1153 case ETHTOOL_GRXCLSRLCNT: 1154 cmd->rule_cnt = bp->ntp_fltr_count; 1155 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1156 break; 1157 1158 case ETHTOOL_GRXCLSRLALL: 1159 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1160 break; 1161 1162 case ETHTOOL_GRXCLSRULE: 1163 rc = bnxt_grxclsrule(bp, cmd); 1164 break; 1165 #endif 1166 1167 case ETHTOOL_GRXFH: 1168 rc = bnxt_grxfh(bp, cmd); 1169 break; 1170 1171 default: 1172 rc = -EOPNOTSUPP; 1173 break; 1174 } 1175 1176 return rc; 1177 } 1178 1179 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1180 { 1181 struct bnxt *bp = netdev_priv(dev); 1182 int rc; 1183 1184 switch (cmd->cmd) { 1185 case ETHTOOL_SRXFH: 1186 rc = bnxt_srxfh(bp, cmd); 1187 break; 1188 1189 default: 1190 rc = -EOPNOTSUPP; 1191 break; 1192 } 1193 return rc; 1194 } 1195 1196 static u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1197 { 1198 return HW_HASH_INDEX_SIZE; 1199 } 1200 1201 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1202 { 1203 return HW_HASH_KEY_SIZE; 1204 } 1205 1206 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1207 u8 *hfunc) 1208 { 1209 struct bnxt *bp = netdev_priv(dev); 1210 struct bnxt_vnic_info *vnic; 1211 int i = 0; 1212 1213 if (hfunc) 1214 *hfunc = ETH_RSS_HASH_TOP; 1215 1216 if (!bp->vnic_info) 1217 return 0; 1218 1219 vnic = &bp->vnic_info[0]; 1220 if (indir && vnic->rss_table) { 1221 for (i = 0; i < HW_HASH_INDEX_SIZE; i++) 1222 indir[i] = le16_to_cpu(vnic->rss_table[i]); 1223 } 1224 1225 if (key && vnic->rss_hash_key) 1226 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1227 1228 return 0; 1229 } 1230 1231 static void bnxt_get_drvinfo(struct net_device *dev, 1232 struct ethtool_drvinfo *info) 1233 { 1234 struct bnxt *bp = netdev_priv(dev); 1235 1236 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1237 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1238 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1239 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1240 info->n_stats = bnxt_get_num_stats(bp); 1241 info->testinfo_len = bp->num_tests; 1242 /* TODO CHIMP_FW: eeprom dump details */ 1243 info->eedump_len = 0; 1244 /* TODO CHIMP FW: reg dump details */ 1245 info->regdump_len = 0; 1246 } 1247 1248 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1249 { 1250 struct bnxt *bp = netdev_priv(dev); 1251 1252 wol->supported = 0; 1253 wol->wolopts = 0; 1254 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1255 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1256 wol->supported = WAKE_MAGIC; 1257 if (bp->wol) 1258 wol->wolopts = WAKE_MAGIC; 1259 } 1260 } 1261 1262 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1263 { 1264 struct bnxt *bp = netdev_priv(dev); 1265 1266 if (wol->wolopts & ~WAKE_MAGIC) 1267 return -EINVAL; 1268 1269 if (wol->wolopts & WAKE_MAGIC) { 1270 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1271 return -EINVAL; 1272 if (!bp->wol) { 1273 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1274 return -EBUSY; 1275 bp->wol = 1; 1276 } 1277 } else { 1278 if (bp->wol) { 1279 if (bnxt_hwrm_free_wol_fltr(bp)) 1280 return -EBUSY; 1281 bp->wol = 0; 1282 } 1283 } 1284 return 0; 1285 } 1286 1287 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1288 { 1289 u32 speed_mask = 0; 1290 1291 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1292 /* set the advertised speeds */ 1293 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1294 speed_mask |= ADVERTISED_100baseT_Full; 1295 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1296 speed_mask |= ADVERTISED_1000baseT_Full; 1297 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1298 speed_mask |= ADVERTISED_2500baseX_Full; 1299 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1300 speed_mask |= ADVERTISED_10000baseT_Full; 1301 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1302 speed_mask |= ADVERTISED_40000baseCR4_Full; 1303 1304 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1305 speed_mask |= ADVERTISED_Pause; 1306 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1307 speed_mask |= ADVERTISED_Asym_Pause; 1308 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1309 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1310 1311 return speed_mask; 1312 } 1313 1314 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1315 { \ 1316 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1317 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1318 100baseT_Full); \ 1319 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1320 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1321 1000baseT_Full); \ 1322 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1323 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1324 10000baseT_Full); \ 1325 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1326 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1327 25000baseCR_Full); \ 1328 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1329 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1330 40000baseCR4_Full);\ 1331 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1332 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1333 50000baseCR2_Full);\ 1334 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1335 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1336 100000baseCR4_Full);\ 1337 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1338 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1339 Pause); \ 1340 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1341 ethtool_link_ksettings_add_link_mode( \ 1342 lk_ksettings, name, Asym_Pause);\ 1343 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1344 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1345 Asym_Pause); \ 1346 } \ 1347 } 1348 1349 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1350 { \ 1351 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1352 100baseT_Full) || \ 1353 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1354 100baseT_Half)) \ 1355 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1356 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1357 1000baseT_Full) || \ 1358 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1359 1000baseT_Half)) \ 1360 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1361 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1362 10000baseT_Full)) \ 1363 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1364 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1365 25000baseCR_Full)) \ 1366 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1367 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1368 40000baseCR4_Full)) \ 1369 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1370 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1371 50000baseCR2_Full)) \ 1372 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1373 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1374 100000baseCR4_Full)) \ 1375 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1376 } 1377 1378 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1379 struct ethtool_link_ksettings *lk_ksettings) 1380 { 1381 u16 fw_speeds = link_info->advertising; 1382 u8 fw_pause = 0; 1383 1384 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1385 fw_pause = link_info->auto_pause_setting; 1386 1387 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1388 } 1389 1390 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1391 struct ethtool_link_ksettings *lk_ksettings) 1392 { 1393 u16 fw_speeds = link_info->lp_auto_link_speeds; 1394 u8 fw_pause = 0; 1395 1396 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1397 fw_pause = link_info->lp_pause; 1398 1399 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1400 lp_advertising); 1401 } 1402 1403 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1404 struct ethtool_link_ksettings *lk_ksettings) 1405 { 1406 u16 fw_speeds = link_info->support_speeds; 1407 1408 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1409 1410 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1411 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1412 Asym_Pause); 1413 1414 if (link_info->support_auto_speeds) 1415 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1416 Autoneg); 1417 } 1418 1419 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1420 { 1421 switch (fw_link_speed) { 1422 case BNXT_LINK_SPEED_100MB: 1423 return SPEED_100; 1424 case BNXT_LINK_SPEED_1GB: 1425 return SPEED_1000; 1426 case BNXT_LINK_SPEED_2_5GB: 1427 return SPEED_2500; 1428 case BNXT_LINK_SPEED_10GB: 1429 return SPEED_10000; 1430 case BNXT_LINK_SPEED_20GB: 1431 return SPEED_20000; 1432 case BNXT_LINK_SPEED_25GB: 1433 return SPEED_25000; 1434 case BNXT_LINK_SPEED_40GB: 1435 return SPEED_40000; 1436 case BNXT_LINK_SPEED_50GB: 1437 return SPEED_50000; 1438 case BNXT_LINK_SPEED_100GB: 1439 return SPEED_100000; 1440 default: 1441 return SPEED_UNKNOWN; 1442 } 1443 } 1444 1445 static int bnxt_get_link_ksettings(struct net_device *dev, 1446 struct ethtool_link_ksettings *lk_ksettings) 1447 { 1448 struct bnxt *bp = netdev_priv(dev); 1449 struct bnxt_link_info *link_info = &bp->link_info; 1450 struct ethtool_link_settings *base = &lk_ksettings->base; 1451 u32 ethtool_speed; 1452 1453 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1454 mutex_lock(&bp->link_lock); 1455 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1456 1457 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1458 if (link_info->autoneg) { 1459 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1460 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1461 advertising, Autoneg); 1462 base->autoneg = AUTONEG_ENABLE; 1463 if (link_info->phy_link_status == BNXT_LINK_LINK) 1464 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1465 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1466 if (!netif_carrier_ok(dev)) 1467 base->duplex = DUPLEX_UNKNOWN; 1468 else if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1469 base->duplex = DUPLEX_FULL; 1470 else 1471 base->duplex = DUPLEX_HALF; 1472 } else { 1473 base->autoneg = AUTONEG_DISABLE; 1474 ethtool_speed = 1475 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1476 base->duplex = DUPLEX_HALF; 1477 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1478 base->duplex = DUPLEX_FULL; 1479 } 1480 base->speed = ethtool_speed; 1481 1482 base->port = PORT_NONE; 1483 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1484 base->port = PORT_TP; 1485 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1486 TP); 1487 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1488 TP); 1489 } else { 1490 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1491 FIBRE); 1492 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1493 FIBRE); 1494 1495 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1496 base->port = PORT_DA; 1497 else if (link_info->media_type == 1498 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1499 base->port = PORT_FIBRE; 1500 } 1501 base->phy_address = link_info->phy_addr; 1502 mutex_unlock(&bp->link_lock); 1503 1504 return 0; 1505 } 1506 1507 static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed) 1508 { 1509 struct bnxt *bp = netdev_priv(dev); 1510 struct bnxt_link_info *link_info = &bp->link_info; 1511 u16 support_spds = link_info->support_speeds; 1512 u32 fw_speed = 0; 1513 1514 switch (ethtool_speed) { 1515 case SPEED_100: 1516 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1517 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB; 1518 break; 1519 case SPEED_1000: 1520 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1521 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB; 1522 break; 1523 case SPEED_2500: 1524 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1525 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB; 1526 break; 1527 case SPEED_10000: 1528 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1529 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB; 1530 break; 1531 case SPEED_20000: 1532 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1533 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB; 1534 break; 1535 case SPEED_25000: 1536 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1537 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB; 1538 break; 1539 case SPEED_40000: 1540 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1541 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB; 1542 break; 1543 case SPEED_50000: 1544 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) 1545 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB; 1546 break; 1547 case SPEED_100000: 1548 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) 1549 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB; 1550 break; 1551 default: 1552 netdev_err(dev, "unsupported speed!\n"); 1553 break; 1554 } 1555 return fw_speed; 1556 } 1557 1558 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1559 { 1560 u16 fw_speed_mask = 0; 1561 1562 /* only support autoneg at speed 100, 1000, and 10000 */ 1563 if (advertising & (ADVERTISED_100baseT_Full | 1564 ADVERTISED_100baseT_Half)) { 1565 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1566 } 1567 if (advertising & (ADVERTISED_1000baseT_Full | 1568 ADVERTISED_1000baseT_Half)) { 1569 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1570 } 1571 if (advertising & ADVERTISED_10000baseT_Full) 1572 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1573 1574 if (advertising & ADVERTISED_40000baseCR4_Full) 1575 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1576 1577 return fw_speed_mask; 1578 } 1579 1580 static int bnxt_set_link_ksettings(struct net_device *dev, 1581 const struct ethtool_link_ksettings *lk_ksettings) 1582 { 1583 struct bnxt *bp = netdev_priv(dev); 1584 struct bnxt_link_info *link_info = &bp->link_info; 1585 const struct ethtool_link_settings *base = &lk_ksettings->base; 1586 bool set_pause = false; 1587 u16 fw_advertising = 0; 1588 u32 speed; 1589 int rc = 0; 1590 1591 if (!BNXT_SINGLE_PF(bp)) 1592 return -EOPNOTSUPP; 1593 1594 mutex_lock(&bp->link_lock); 1595 if (base->autoneg == AUTONEG_ENABLE) { 1596 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings, 1597 advertising); 1598 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1599 if (!fw_advertising) 1600 link_info->advertising = link_info->support_auto_speeds; 1601 else 1602 link_info->advertising = fw_advertising; 1603 /* any change to autoneg will cause link change, therefore the 1604 * driver should put back the original pause setting in autoneg 1605 */ 1606 set_pause = true; 1607 } else { 1608 u16 fw_speed; 1609 u8 phy_type = link_info->phy_type; 1610 1611 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1612 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1613 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1614 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1615 rc = -EINVAL; 1616 goto set_setting_exit; 1617 } 1618 if (base->duplex == DUPLEX_HALF) { 1619 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1620 rc = -EINVAL; 1621 goto set_setting_exit; 1622 } 1623 speed = base->speed; 1624 fw_speed = bnxt_get_fw_speed(dev, speed); 1625 if (!fw_speed) { 1626 rc = -EINVAL; 1627 goto set_setting_exit; 1628 } 1629 link_info->req_link_speed = fw_speed; 1630 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1631 link_info->autoneg = 0; 1632 link_info->advertising = 0; 1633 } 1634 1635 if (netif_running(dev)) 1636 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1637 1638 set_setting_exit: 1639 mutex_unlock(&bp->link_lock); 1640 return rc; 1641 } 1642 1643 static void bnxt_get_pauseparam(struct net_device *dev, 1644 struct ethtool_pauseparam *epause) 1645 { 1646 struct bnxt *bp = netdev_priv(dev); 1647 struct bnxt_link_info *link_info = &bp->link_info; 1648 1649 if (BNXT_VF(bp)) 1650 return; 1651 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 1652 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 1653 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 1654 } 1655 1656 static int bnxt_set_pauseparam(struct net_device *dev, 1657 struct ethtool_pauseparam *epause) 1658 { 1659 int rc = 0; 1660 struct bnxt *bp = netdev_priv(dev); 1661 struct bnxt_link_info *link_info = &bp->link_info; 1662 1663 if (!BNXT_SINGLE_PF(bp)) 1664 return -EOPNOTSUPP; 1665 1666 if (epause->autoneg) { 1667 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 1668 return -EINVAL; 1669 1670 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 1671 if (bp->hwrm_spec_code >= 0x10201) 1672 link_info->req_flow_ctrl = 1673 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 1674 } else { 1675 /* when transition from auto pause to force pause, 1676 * force a link change 1677 */ 1678 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1679 link_info->force_link_chng = true; 1680 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 1681 link_info->req_flow_ctrl = 0; 1682 } 1683 if (epause->rx_pause) 1684 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 1685 1686 if (epause->tx_pause) 1687 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 1688 1689 if (netif_running(dev)) 1690 rc = bnxt_hwrm_set_pause(bp); 1691 return rc; 1692 } 1693 1694 static u32 bnxt_get_link(struct net_device *dev) 1695 { 1696 struct bnxt *bp = netdev_priv(dev); 1697 1698 /* TODO: handle MF, VF, driver close case */ 1699 return bp->link_info.link_up; 1700 } 1701 1702 static void bnxt_print_admin_err(struct bnxt *bp) 1703 { 1704 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 1705 } 1706 1707 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 1708 u16 ext, u16 *index, u32 *item_length, 1709 u32 *data_length); 1710 1711 static int bnxt_flash_nvram(struct net_device *dev, 1712 u16 dir_type, 1713 u16 dir_ordinal, 1714 u16 dir_ext, 1715 u16 dir_attr, 1716 const u8 *data, 1717 size_t data_len) 1718 { 1719 struct bnxt *bp = netdev_priv(dev); 1720 int rc; 1721 struct hwrm_nvm_write_input req = {0}; 1722 dma_addr_t dma_handle; 1723 u8 *kmem; 1724 1725 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 1726 1727 req.dir_type = cpu_to_le16(dir_type); 1728 req.dir_ordinal = cpu_to_le16(dir_ordinal); 1729 req.dir_ext = cpu_to_le16(dir_ext); 1730 req.dir_attr = cpu_to_le16(dir_attr); 1731 req.dir_data_length = cpu_to_le32(data_len); 1732 1733 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 1734 GFP_KERNEL); 1735 if (!kmem) { 1736 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 1737 (unsigned)data_len); 1738 return -ENOMEM; 1739 } 1740 memcpy(kmem, data, data_len); 1741 req.host_src_addr = cpu_to_le64(dma_handle); 1742 1743 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 1744 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 1745 1746 if (rc == -EACCES) 1747 bnxt_print_admin_err(bp); 1748 return rc; 1749 } 1750 1751 static int bnxt_firmware_reset(struct net_device *dev, 1752 u16 dir_type) 1753 { 1754 struct hwrm_fw_reset_input req = {0}; 1755 struct bnxt *bp = netdev_priv(dev); 1756 int rc; 1757 1758 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 1759 1760 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 1761 /* (e.g. when firmware isn't already running) */ 1762 switch (dir_type) { 1763 case BNX_DIR_TYPE_CHIMP_PATCH: 1764 case BNX_DIR_TYPE_BOOTCODE: 1765 case BNX_DIR_TYPE_BOOTCODE_2: 1766 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 1767 /* Self-reset ChiMP upon next PCIe reset: */ 1768 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1769 break; 1770 case BNX_DIR_TYPE_APE_FW: 1771 case BNX_DIR_TYPE_APE_PATCH: 1772 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 1773 /* Self-reset APE upon next PCIe reset: */ 1774 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1775 break; 1776 case BNX_DIR_TYPE_KONG_FW: 1777 case BNX_DIR_TYPE_KONG_PATCH: 1778 req.embedded_proc_type = 1779 FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 1780 break; 1781 case BNX_DIR_TYPE_BONO_FW: 1782 case BNX_DIR_TYPE_BONO_PATCH: 1783 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 1784 break; 1785 case BNXT_FW_RESET_CHIP: 1786 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP; 1787 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP; 1788 break; 1789 case BNXT_FW_RESET_AP: 1790 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP; 1791 break; 1792 default: 1793 return -EINVAL; 1794 } 1795 1796 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1797 if (rc == -EACCES) 1798 bnxt_print_admin_err(bp); 1799 return rc; 1800 } 1801 1802 static int bnxt_flash_firmware(struct net_device *dev, 1803 u16 dir_type, 1804 const u8 *fw_data, 1805 size_t fw_size) 1806 { 1807 int rc = 0; 1808 u16 code_type; 1809 u32 stored_crc; 1810 u32 calculated_crc; 1811 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 1812 1813 switch (dir_type) { 1814 case BNX_DIR_TYPE_BOOTCODE: 1815 case BNX_DIR_TYPE_BOOTCODE_2: 1816 code_type = CODE_BOOT; 1817 break; 1818 case BNX_DIR_TYPE_CHIMP_PATCH: 1819 code_type = CODE_CHIMP_PATCH; 1820 break; 1821 case BNX_DIR_TYPE_APE_FW: 1822 code_type = CODE_MCTP_PASSTHRU; 1823 break; 1824 case BNX_DIR_TYPE_APE_PATCH: 1825 code_type = CODE_APE_PATCH; 1826 break; 1827 case BNX_DIR_TYPE_KONG_FW: 1828 code_type = CODE_KONG_FW; 1829 break; 1830 case BNX_DIR_TYPE_KONG_PATCH: 1831 code_type = CODE_KONG_PATCH; 1832 break; 1833 case BNX_DIR_TYPE_BONO_FW: 1834 code_type = CODE_BONO_FW; 1835 break; 1836 case BNX_DIR_TYPE_BONO_PATCH: 1837 code_type = CODE_BONO_PATCH; 1838 break; 1839 default: 1840 netdev_err(dev, "Unsupported directory entry type: %u\n", 1841 dir_type); 1842 return -EINVAL; 1843 } 1844 if (fw_size < sizeof(struct bnxt_fw_header)) { 1845 netdev_err(dev, "Invalid firmware file size: %u\n", 1846 (unsigned int)fw_size); 1847 return -EINVAL; 1848 } 1849 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 1850 netdev_err(dev, "Invalid firmware signature: %08X\n", 1851 le32_to_cpu(header->signature)); 1852 return -EINVAL; 1853 } 1854 if (header->code_type != code_type) { 1855 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 1856 code_type, header->code_type); 1857 return -EINVAL; 1858 } 1859 if (header->device != DEVICE_CUMULUS_FAMILY) { 1860 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 1861 DEVICE_CUMULUS_FAMILY, header->device); 1862 return -EINVAL; 1863 } 1864 /* Confirm the CRC32 checksum of the file: */ 1865 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 1866 sizeof(stored_crc))); 1867 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 1868 if (calculated_crc != stored_crc) { 1869 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 1870 (unsigned long)stored_crc, 1871 (unsigned long)calculated_crc); 1872 return -EINVAL; 1873 } 1874 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1875 0, 0, fw_data, fw_size); 1876 if (rc == 0) /* Firmware update successful */ 1877 rc = bnxt_firmware_reset(dev, dir_type); 1878 1879 return rc; 1880 } 1881 1882 static int bnxt_flash_microcode(struct net_device *dev, 1883 u16 dir_type, 1884 const u8 *fw_data, 1885 size_t fw_size) 1886 { 1887 struct bnxt_ucode_trailer *trailer; 1888 u32 calculated_crc; 1889 u32 stored_crc; 1890 int rc = 0; 1891 1892 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 1893 netdev_err(dev, "Invalid microcode file size: %u\n", 1894 (unsigned int)fw_size); 1895 return -EINVAL; 1896 } 1897 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 1898 sizeof(*trailer))); 1899 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 1900 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 1901 le32_to_cpu(trailer->sig)); 1902 return -EINVAL; 1903 } 1904 if (le16_to_cpu(trailer->dir_type) != dir_type) { 1905 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 1906 dir_type, le16_to_cpu(trailer->dir_type)); 1907 return -EINVAL; 1908 } 1909 if (le16_to_cpu(trailer->trailer_length) < 1910 sizeof(struct bnxt_ucode_trailer)) { 1911 netdev_err(dev, "Invalid microcode trailer length: %d\n", 1912 le16_to_cpu(trailer->trailer_length)); 1913 return -EINVAL; 1914 } 1915 1916 /* Confirm the CRC32 checksum of the file: */ 1917 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 1918 sizeof(stored_crc))); 1919 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 1920 if (calculated_crc != stored_crc) { 1921 netdev_err(dev, 1922 "CRC32 (%08lX) does not match calculated: %08lX\n", 1923 (unsigned long)stored_crc, 1924 (unsigned long)calculated_crc); 1925 return -EINVAL; 1926 } 1927 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1928 0, 0, fw_data, fw_size); 1929 1930 return rc; 1931 } 1932 1933 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 1934 { 1935 switch (dir_type) { 1936 case BNX_DIR_TYPE_CHIMP_PATCH: 1937 case BNX_DIR_TYPE_BOOTCODE: 1938 case BNX_DIR_TYPE_BOOTCODE_2: 1939 case BNX_DIR_TYPE_APE_FW: 1940 case BNX_DIR_TYPE_APE_PATCH: 1941 case BNX_DIR_TYPE_KONG_FW: 1942 case BNX_DIR_TYPE_KONG_PATCH: 1943 case BNX_DIR_TYPE_BONO_FW: 1944 case BNX_DIR_TYPE_BONO_PATCH: 1945 return true; 1946 } 1947 1948 return false; 1949 } 1950 1951 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 1952 { 1953 switch (dir_type) { 1954 case BNX_DIR_TYPE_AVS: 1955 case BNX_DIR_TYPE_EXP_ROM_MBA: 1956 case BNX_DIR_TYPE_PCIE: 1957 case BNX_DIR_TYPE_TSCF_UCODE: 1958 case BNX_DIR_TYPE_EXT_PHY: 1959 case BNX_DIR_TYPE_CCM: 1960 case BNX_DIR_TYPE_ISCSI_BOOT: 1961 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 1962 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 1963 return true; 1964 } 1965 1966 return false; 1967 } 1968 1969 static bool bnxt_dir_type_is_executable(u16 dir_type) 1970 { 1971 return bnxt_dir_type_is_ape_bin_format(dir_type) || 1972 bnxt_dir_type_is_other_exec_format(dir_type); 1973 } 1974 1975 static int bnxt_flash_firmware_from_file(struct net_device *dev, 1976 u16 dir_type, 1977 const char *filename) 1978 { 1979 const struct firmware *fw; 1980 int rc; 1981 1982 rc = request_firmware(&fw, filename, &dev->dev); 1983 if (rc != 0) { 1984 netdev_err(dev, "Error %d requesting firmware file: %s\n", 1985 rc, filename); 1986 return rc; 1987 } 1988 if (bnxt_dir_type_is_ape_bin_format(dir_type) == true) 1989 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 1990 else if (bnxt_dir_type_is_other_exec_format(dir_type) == true) 1991 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 1992 else 1993 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1994 0, 0, fw->data, fw->size); 1995 release_firmware(fw); 1996 return rc; 1997 } 1998 1999 static int bnxt_flash_package_from_file(struct net_device *dev, 2000 char *filename, u32 install_type) 2001 { 2002 struct bnxt *bp = netdev_priv(dev); 2003 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2004 struct hwrm_nvm_install_update_input install = {0}; 2005 const struct firmware *fw; 2006 int rc, hwrm_err = 0; 2007 u32 item_len; 2008 u16 index; 2009 2010 bnxt_hwrm_fw_set_time(bp); 2011 2012 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2013 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2014 &index, &item_len, NULL) != 0) { 2015 netdev_err(dev, "PKG update area not created in nvram\n"); 2016 return -ENOBUFS; 2017 } 2018 2019 rc = request_firmware(&fw, filename, &dev->dev); 2020 if (rc != 0) { 2021 netdev_err(dev, "PKG error %d requesting file: %s\n", 2022 rc, filename); 2023 return rc; 2024 } 2025 2026 if (fw->size > item_len) { 2027 netdev_err(dev, "PKG insufficient update area in nvram: %lu", 2028 (unsigned long)fw->size); 2029 rc = -EFBIG; 2030 } else { 2031 dma_addr_t dma_handle; 2032 u8 *kmem; 2033 struct hwrm_nvm_modify_input modify = {0}; 2034 2035 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2036 2037 modify.dir_idx = cpu_to_le16(index); 2038 modify.len = cpu_to_le32(fw->size); 2039 2040 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2041 &dma_handle, GFP_KERNEL); 2042 if (!kmem) { 2043 netdev_err(dev, 2044 "dma_alloc_coherent failure, length = %u\n", 2045 (unsigned int)fw->size); 2046 rc = -ENOMEM; 2047 } else { 2048 memcpy(kmem, fw->data, fw->size); 2049 modify.host_src_addr = cpu_to_le64(dma_handle); 2050 2051 hwrm_err = hwrm_send_message(bp, &modify, 2052 sizeof(modify), 2053 FLASH_PACKAGE_TIMEOUT); 2054 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2055 dma_handle); 2056 } 2057 } 2058 release_firmware(fw); 2059 if (rc || hwrm_err) 2060 goto err_exit; 2061 2062 if ((install_type & 0xffff) == 0) 2063 install_type >>= 16; 2064 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2065 install.install_type = cpu_to_le32(install_type); 2066 2067 mutex_lock(&bp->hwrm_cmd_lock); 2068 hwrm_err = _hwrm_send_message(bp, &install, sizeof(install), 2069 INSTALL_PACKAGE_TIMEOUT); 2070 if (hwrm_err) { 2071 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2072 2073 if (resp->error_code && error_code == 2074 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2075 install.flags |= cpu_to_le16( 2076 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2077 hwrm_err = _hwrm_send_message(bp, &install, 2078 sizeof(install), 2079 INSTALL_PACKAGE_TIMEOUT); 2080 } 2081 if (hwrm_err) 2082 goto flash_pkg_exit; 2083 } 2084 2085 if (resp->result) { 2086 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2087 (s8)resp->result, (int)resp->problem_item); 2088 rc = -ENOPKG; 2089 } 2090 flash_pkg_exit: 2091 mutex_unlock(&bp->hwrm_cmd_lock); 2092 err_exit: 2093 if (hwrm_err == -EACCES) 2094 bnxt_print_admin_err(bp); 2095 return rc; 2096 } 2097 2098 static int bnxt_flash_device(struct net_device *dev, 2099 struct ethtool_flash *flash) 2100 { 2101 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2102 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2103 return -EINVAL; 2104 } 2105 2106 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2107 flash->region > 0xffff) 2108 return bnxt_flash_package_from_file(dev, flash->data, 2109 flash->region); 2110 2111 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2112 } 2113 2114 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2115 { 2116 struct bnxt *bp = netdev_priv(dev); 2117 int rc; 2118 struct hwrm_nvm_get_dir_info_input req = {0}; 2119 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2120 2121 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2122 2123 mutex_lock(&bp->hwrm_cmd_lock); 2124 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2125 if (!rc) { 2126 *entries = le32_to_cpu(output->entries); 2127 *length = le32_to_cpu(output->entry_length); 2128 } 2129 mutex_unlock(&bp->hwrm_cmd_lock); 2130 return rc; 2131 } 2132 2133 static int bnxt_get_eeprom_len(struct net_device *dev) 2134 { 2135 struct bnxt *bp = netdev_priv(dev); 2136 2137 if (BNXT_VF(bp)) 2138 return 0; 2139 2140 /* The -1 return value allows the entire 32-bit range of offsets to be 2141 * passed via the ethtool command-line utility. 2142 */ 2143 return -1; 2144 } 2145 2146 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2147 { 2148 struct bnxt *bp = netdev_priv(dev); 2149 int rc; 2150 u32 dir_entries; 2151 u32 entry_length; 2152 u8 *buf; 2153 size_t buflen; 2154 dma_addr_t dma_handle; 2155 struct hwrm_nvm_get_dir_entries_input req = {0}; 2156 2157 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2158 if (rc != 0) 2159 return rc; 2160 2161 /* Insert 2 bytes of directory info (count and size of entries) */ 2162 if (len < 2) 2163 return -EINVAL; 2164 2165 *data++ = dir_entries; 2166 *data++ = entry_length; 2167 len -= 2; 2168 memset(data, 0xff, len); 2169 2170 buflen = dir_entries * entry_length; 2171 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2172 GFP_KERNEL); 2173 if (!buf) { 2174 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2175 (unsigned)buflen); 2176 return -ENOMEM; 2177 } 2178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2179 req.host_dest_addr = cpu_to_le64(dma_handle); 2180 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2181 if (rc == 0) 2182 memcpy(data, buf, len > buflen ? buflen : len); 2183 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2184 return rc; 2185 } 2186 2187 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2188 u32 length, u8 *data) 2189 { 2190 struct bnxt *bp = netdev_priv(dev); 2191 int rc; 2192 u8 *buf; 2193 dma_addr_t dma_handle; 2194 struct hwrm_nvm_read_input req = {0}; 2195 2196 if (!length) 2197 return -EINVAL; 2198 2199 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2200 GFP_KERNEL); 2201 if (!buf) { 2202 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2203 (unsigned)length); 2204 return -ENOMEM; 2205 } 2206 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2207 req.host_dest_addr = cpu_to_le64(dma_handle); 2208 req.dir_idx = cpu_to_le16(index); 2209 req.offset = cpu_to_le32(offset); 2210 req.len = cpu_to_le32(length); 2211 2212 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2213 if (rc == 0) 2214 memcpy(data, buf, length); 2215 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2216 return rc; 2217 } 2218 2219 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2220 u16 ext, u16 *index, u32 *item_length, 2221 u32 *data_length) 2222 { 2223 struct bnxt *bp = netdev_priv(dev); 2224 int rc; 2225 struct hwrm_nvm_find_dir_entry_input req = {0}; 2226 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2227 2228 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2229 req.enables = 0; 2230 req.dir_idx = 0; 2231 req.dir_type = cpu_to_le16(type); 2232 req.dir_ordinal = cpu_to_le16(ordinal); 2233 req.dir_ext = cpu_to_le16(ext); 2234 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2235 mutex_lock(&bp->hwrm_cmd_lock); 2236 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2237 if (rc == 0) { 2238 if (index) 2239 *index = le16_to_cpu(output->dir_idx); 2240 if (item_length) 2241 *item_length = le32_to_cpu(output->dir_item_length); 2242 if (data_length) 2243 *data_length = le32_to_cpu(output->dir_data_length); 2244 } 2245 mutex_unlock(&bp->hwrm_cmd_lock); 2246 return rc; 2247 } 2248 2249 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2250 { 2251 char *retval = NULL; 2252 char *p; 2253 char *value; 2254 int field = 0; 2255 2256 if (datalen < 1) 2257 return NULL; 2258 /* null-terminate the log data (removing last '\n'): */ 2259 data[datalen - 1] = 0; 2260 for (p = data; *p != 0; p++) { 2261 field = 0; 2262 retval = NULL; 2263 while (*p != 0 && *p != '\n') { 2264 value = p; 2265 while (*p != 0 && *p != '\t' && *p != '\n') 2266 p++; 2267 if (field == desired_field) 2268 retval = value; 2269 if (*p != '\t') 2270 break; 2271 *p = 0; 2272 field++; 2273 p++; 2274 } 2275 if (*p == 0) 2276 break; 2277 *p = 0; 2278 } 2279 return retval; 2280 } 2281 2282 static void bnxt_get_pkgver(struct net_device *dev) 2283 { 2284 struct bnxt *bp = netdev_priv(dev); 2285 u16 index = 0; 2286 char *pkgver; 2287 u32 pkglen; 2288 u8 *pkgbuf; 2289 int len; 2290 2291 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2292 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2293 &index, NULL, &pkglen) != 0) 2294 return; 2295 2296 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2297 if (!pkgbuf) { 2298 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2299 pkglen); 2300 return; 2301 } 2302 2303 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2304 goto err; 2305 2306 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2307 pkglen); 2308 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2309 len = strlen(bp->fw_ver_str); 2310 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2311 "/pkg %s", pkgver); 2312 } 2313 err: 2314 kfree(pkgbuf); 2315 } 2316 2317 static int bnxt_get_eeprom(struct net_device *dev, 2318 struct ethtool_eeprom *eeprom, 2319 u8 *data) 2320 { 2321 u32 index; 2322 u32 offset; 2323 2324 if (eeprom->offset == 0) /* special offset value to get directory */ 2325 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2326 2327 index = eeprom->offset >> 24; 2328 offset = eeprom->offset & 0xffffff; 2329 2330 if (index == 0) { 2331 netdev_err(dev, "unsupported index value: %d\n", index); 2332 return -EINVAL; 2333 } 2334 2335 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2336 } 2337 2338 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2339 { 2340 struct bnxt *bp = netdev_priv(dev); 2341 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2342 2343 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2344 req.dir_idx = cpu_to_le16(index); 2345 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2346 } 2347 2348 static int bnxt_set_eeprom(struct net_device *dev, 2349 struct ethtool_eeprom *eeprom, 2350 u8 *data) 2351 { 2352 struct bnxt *bp = netdev_priv(dev); 2353 u8 index, dir_op; 2354 u16 type, ext, ordinal, attr; 2355 2356 if (!BNXT_PF(bp)) { 2357 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2358 return -EINVAL; 2359 } 2360 2361 type = eeprom->magic >> 16; 2362 2363 if (type == 0xffff) { /* special value for directory operations */ 2364 index = eeprom->magic & 0xff; 2365 dir_op = eeprom->magic >> 8; 2366 if (index == 0) 2367 return -EINVAL; 2368 switch (dir_op) { 2369 case 0x0e: /* erase */ 2370 if (eeprom->offset != ~eeprom->magic) 2371 return -EINVAL; 2372 return bnxt_erase_nvram_directory(dev, index - 1); 2373 default: 2374 return -EINVAL; 2375 } 2376 } 2377 2378 /* Create or re-write an NVM item: */ 2379 if (bnxt_dir_type_is_executable(type) == true) 2380 return -EOPNOTSUPP; 2381 ext = eeprom->magic & 0xffff; 2382 ordinal = eeprom->offset >> 16; 2383 attr = eeprom->offset & 0xffff; 2384 2385 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2386 eeprom->len); 2387 } 2388 2389 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2390 { 2391 struct bnxt *bp = netdev_priv(dev); 2392 struct ethtool_eee *eee = &bp->eee; 2393 struct bnxt_link_info *link_info = &bp->link_info; 2394 u32 advertising = 2395 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2396 int rc = 0; 2397 2398 if (!BNXT_SINGLE_PF(bp)) 2399 return -EOPNOTSUPP; 2400 2401 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2402 return -EOPNOTSUPP; 2403 2404 if (!edata->eee_enabled) 2405 goto eee_ok; 2406 2407 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2408 netdev_warn(dev, "EEE requires autoneg\n"); 2409 return -EINVAL; 2410 } 2411 if (edata->tx_lpi_enabled) { 2412 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2413 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2414 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2415 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2416 return -EINVAL; 2417 } else if (!bp->lpi_tmr_hi) { 2418 edata->tx_lpi_timer = eee->tx_lpi_timer; 2419 } 2420 } 2421 if (!edata->advertised) { 2422 edata->advertised = advertising & eee->supported; 2423 } else if (edata->advertised & ~advertising) { 2424 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2425 edata->advertised, advertising); 2426 return -EINVAL; 2427 } 2428 2429 eee->advertised = edata->advertised; 2430 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2431 eee->tx_lpi_timer = edata->tx_lpi_timer; 2432 eee_ok: 2433 eee->eee_enabled = edata->eee_enabled; 2434 2435 if (netif_running(dev)) 2436 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2437 2438 return rc; 2439 } 2440 2441 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2442 { 2443 struct bnxt *bp = netdev_priv(dev); 2444 2445 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2446 return -EOPNOTSUPP; 2447 2448 *edata = bp->eee; 2449 if (!bp->eee.eee_enabled) { 2450 /* Preserve tx_lpi_timer so that the last value will be used 2451 * by default when it is re-enabled. 2452 */ 2453 edata->advertised = 0; 2454 edata->tx_lpi_enabled = 0; 2455 } 2456 2457 if (!bp->eee.eee_active) 2458 edata->lp_advertised = 0; 2459 2460 return 0; 2461 } 2462 2463 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2464 u16 page_number, u16 start_addr, 2465 u16 data_length, u8 *buf) 2466 { 2467 struct hwrm_port_phy_i2c_read_input req = {0}; 2468 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2469 int rc, byte_offset = 0; 2470 2471 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2472 req.i2c_slave_addr = i2c_addr; 2473 req.page_number = cpu_to_le16(page_number); 2474 req.port_id = cpu_to_le16(bp->pf.port_id); 2475 do { 2476 u16 xfer_size; 2477 2478 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2479 data_length -= xfer_size; 2480 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2481 req.data_length = xfer_size; 2482 req.enables = cpu_to_le32(start_addr + byte_offset ? 2483 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2484 mutex_lock(&bp->hwrm_cmd_lock); 2485 rc = _hwrm_send_message(bp, &req, sizeof(req), 2486 HWRM_CMD_TIMEOUT); 2487 if (!rc) 2488 memcpy(buf + byte_offset, output->data, xfer_size); 2489 mutex_unlock(&bp->hwrm_cmd_lock); 2490 byte_offset += xfer_size; 2491 } while (!rc && data_length > 0); 2492 2493 return rc; 2494 } 2495 2496 static int bnxt_get_module_info(struct net_device *dev, 2497 struct ethtool_modinfo *modinfo) 2498 { 2499 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2500 struct bnxt *bp = netdev_priv(dev); 2501 int rc; 2502 2503 /* No point in going further if phy status indicates 2504 * module is not inserted or if it is powered down or 2505 * if it is of type 10GBase-T 2506 */ 2507 if (bp->link_info.module_status > 2508 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2509 return -EOPNOTSUPP; 2510 2511 /* This feature is not supported in older firmware versions */ 2512 if (bp->hwrm_spec_code < 0x10202) 2513 return -EOPNOTSUPP; 2514 2515 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2516 SFF_DIAG_SUPPORT_OFFSET + 1, 2517 data); 2518 if (!rc) { 2519 u8 module_id = data[0]; 2520 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2521 2522 switch (module_id) { 2523 case SFF_MODULE_ID_SFP: 2524 modinfo->type = ETH_MODULE_SFF_8472; 2525 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2526 if (!diag_supported) 2527 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2528 break; 2529 case SFF_MODULE_ID_QSFP: 2530 case SFF_MODULE_ID_QSFP_PLUS: 2531 modinfo->type = ETH_MODULE_SFF_8436; 2532 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2533 break; 2534 case SFF_MODULE_ID_QSFP28: 2535 modinfo->type = ETH_MODULE_SFF_8636; 2536 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2537 break; 2538 default: 2539 rc = -EOPNOTSUPP; 2540 break; 2541 } 2542 } 2543 return rc; 2544 } 2545 2546 static int bnxt_get_module_eeprom(struct net_device *dev, 2547 struct ethtool_eeprom *eeprom, 2548 u8 *data) 2549 { 2550 struct bnxt *bp = netdev_priv(dev); 2551 u16 start = eeprom->offset, length = eeprom->len; 2552 int rc = 0; 2553 2554 memset(data, 0, eeprom->len); 2555 2556 /* Read A0 portion of the EEPROM */ 2557 if (start < ETH_MODULE_SFF_8436_LEN) { 2558 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 2559 length = ETH_MODULE_SFF_8436_LEN - start; 2560 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 2561 start, length, data); 2562 if (rc) 2563 return rc; 2564 start += length; 2565 data += length; 2566 length = eeprom->len - length; 2567 } 2568 2569 /* Read A2 portion of the EEPROM */ 2570 if (length) { 2571 start -= ETH_MODULE_SFF_8436_LEN; 2572 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, 2573 start, length, data); 2574 } 2575 return rc; 2576 } 2577 2578 static int bnxt_nway_reset(struct net_device *dev) 2579 { 2580 int rc = 0; 2581 2582 struct bnxt *bp = netdev_priv(dev); 2583 struct bnxt_link_info *link_info = &bp->link_info; 2584 2585 if (!BNXT_SINGLE_PF(bp)) 2586 return -EOPNOTSUPP; 2587 2588 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 2589 return -EINVAL; 2590 2591 if (netif_running(dev)) 2592 rc = bnxt_hwrm_set_link_setting(bp, true, false); 2593 2594 return rc; 2595 } 2596 2597 static int bnxt_set_phys_id(struct net_device *dev, 2598 enum ethtool_phys_id_state state) 2599 { 2600 struct hwrm_port_led_cfg_input req = {0}; 2601 struct bnxt *bp = netdev_priv(dev); 2602 struct bnxt_pf_info *pf = &bp->pf; 2603 struct bnxt_led_cfg *led_cfg; 2604 u8 led_state; 2605 __le16 duration; 2606 int i, rc; 2607 2608 if (!bp->num_leds || BNXT_VF(bp)) 2609 return -EOPNOTSUPP; 2610 2611 if (state == ETHTOOL_ID_ACTIVE) { 2612 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 2613 duration = cpu_to_le16(500); 2614 } else if (state == ETHTOOL_ID_INACTIVE) { 2615 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 2616 duration = cpu_to_le16(0); 2617 } else { 2618 return -EINVAL; 2619 } 2620 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 2621 req.port_id = cpu_to_le16(pf->port_id); 2622 req.num_leds = bp->num_leds; 2623 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 2624 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 2625 req.enables |= BNXT_LED_DFLT_ENABLES(i); 2626 led_cfg->led_id = bp->leds[i].led_id; 2627 led_cfg->led_state = led_state; 2628 led_cfg->led_blink_on = duration; 2629 led_cfg->led_blink_off = duration; 2630 led_cfg->led_group_id = bp->leds[i].led_group_id; 2631 } 2632 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2633 return rc; 2634 } 2635 2636 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 2637 { 2638 struct hwrm_selftest_irq_input req = {0}; 2639 2640 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 2641 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2642 } 2643 2644 static int bnxt_test_irq(struct bnxt *bp) 2645 { 2646 int i; 2647 2648 for (i = 0; i < bp->cp_nr_rings; i++) { 2649 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 2650 int rc; 2651 2652 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 2653 if (rc) 2654 return rc; 2655 } 2656 return 0; 2657 } 2658 2659 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 2660 { 2661 struct hwrm_port_mac_cfg_input req = {0}; 2662 2663 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 2664 2665 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 2666 if (enable) 2667 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 2668 else 2669 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 2670 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2671 } 2672 2673 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 2674 { 2675 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 2676 struct hwrm_port_phy_qcaps_input req = {0}; 2677 int rc; 2678 2679 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 2680 mutex_lock(&bp->hwrm_cmd_lock); 2681 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2682 if (!rc) 2683 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 2684 2685 mutex_unlock(&bp->hwrm_cmd_lock); 2686 return rc; 2687 } 2688 2689 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 2690 struct hwrm_port_phy_cfg_input *req) 2691 { 2692 struct bnxt_link_info *link_info = &bp->link_info; 2693 u16 fw_advertising; 2694 u16 fw_speed; 2695 int rc; 2696 2697 if (!link_info->autoneg) 2698 return 0; 2699 2700 rc = bnxt_query_force_speeds(bp, &fw_advertising); 2701 if (rc) 2702 return rc; 2703 2704 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2705 if (netif_carrier_ok(bp->dev)) 2706 fw_speed = bp->link_info.link_speed; 2707 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 2708 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2709 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 2710 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2711 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 2712 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2713 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 2714 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2715 2716 req->force_link_speed = cpu_to_le16(fw_speed); 2717 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 2718 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2719 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 2720 req->flags = 0; 2721 req->force_link_speed = cpu_to_le16(0); 2722 return rc; 2723 } 2724 2725 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 2726 { 2727 struct hwrm_port_phy_cfg_input req = {0}; 2728 2729 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 2730 2731 if (enable) { 2732 bnxt_disable_an_for_lpbk(bp, &req); 2733 if (ext) 2734 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 2735 else 2736 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 2737 } else { 2738 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 2739 } 2740 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 2741 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2742 } 2743 2744 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2745 u32 raw_cons, int pkt_size) 2746 { 2747 struct bnxt_napi *bnapi = cpr->bnapi; 2748 struct bnxt_rx_ring_info *rxr; 2749 struct bnxt_sw_rx_bd *rx_buf; 2750 struct rx_cmp *rxcmp; 2751 u16 cp_cons, cons; 2752 u8 *data; 2753 u32 len; 2754 int i; 2755 2756 rxr = bnapi->rx_ring; 2757 cp_cons = RING_CMP(raw_cons); 2758 rxcmp = (struct rx_cmp *) 2759 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2760 cons = rxcmp->rx_cmp_opaque; 2761 rx_buf = &rxr->rx_buf_ring[cons]; 2762 data = rx_buf->data_ptr; 2763 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 2764 if (len != pkt_size) 2765 return -EIO; 2766 i = ETH_ALEN; 2767 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 2768 return -EIO; 2769 i += ETH_ALEN; 2770 for ( ; i < pkt_size; i++) { 2771 if (data[i] != (u8)(i & 0xff)) 2772 return -EIO; 2773 } 2774 return 0; 2775 } 2776 2777 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2778 int pkt_size) 2779 { 2780 struct tx_cmp *txcmp; 2781 int rc = -EIO; 2782 u32 raw_cons; 2783 u32 cons; 2784 int i; 2785 2786 raw_cons = cpr->cp_raw_cons; 2787 for (i = 0; i < 200; i++) { 2788 cons = RING_CMP(raw_cons); 2789 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2790 2791 if (!TX_CMP_VALID(txcmp, raw_cons)) { 2792 udelay(5); 2793 continue; 2794 } 2795 2796 /* The valid test of the entry must be done first before 2797 * reading any further. 2798 */ 2799 dma_rmb(); 2800 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 2801 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 2802 raw_cons = NEXT_RAW_CMP(raw_cons); 2803 raw_cons = NEXT_RAW_CMP(raw_cons); 2804 break; 2805 } 2806 raw_cons = NEXT_RAW_CMP(raw_cons); 2807 } 2808 cpr->cp_raw_cons = raw_cons; 2809 return rc; 2810 } 2811 2812 static int bnxt_run_loopback(struct bnxt *bp) 2813 { 2814 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 2815 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 2816 struct bnxt_cp_ring_info *cpr; 2817 int pkt_size, i = 0; 2818 struct sk_buff *skb; 2819 dma_addr_t map; 2820 u8 *data; 2821 int rc; 2822 2823 cpr = &rxr->bnapi->cp_ring; 2824 if (bp->flags & BNXT_FLAG_CHIP_P5) 2825 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 2826 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 2827 skb = netdev_alloc_skb(bp->dev, pkt_size); 2828 if (!skb) 2829 return -ENOMEM; 2830 data = skb_put(skb, pkt_size); 2831 eth_broadcast_addr(data); 2832 i += ETH_ALEN; 2833 ether_addr_copy(&data[i], bp->dev->dev_addr); 2834 i += ETH_ALEN; 2835 for ( ; i < pkt_size; i++) 2836 data[i] = (u8)(i & 0xff); 2837 2838 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 2839 PCI_DMA_TODEVICE); 2840 if (dma_mapping_error(&bp->pdev->dev, map)) { 2841 dev_kfree_skb(skb); 2842 return -EIO; 2843 } 2844 bnxt_xmit_bd(bp, txr, map, pkt_size); 2845 2846 /* Sync BD data before updating doorbell */ 2847 wmb(); 2848 2849 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 2850 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 2851 2852 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 2853 dev_kfree_skb(skb); 2854 return rc; 2855 } 2856 2857 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 2858 { 2859 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 2860 struct hwrm_selftest_exec_input req = {0}; 2861 int rc; 2862 2863 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 2864 mutex_lock(&bp->hwrm_cmd_lock); 2865 resp->test_success = 0; 2866 req.flags = test_mask; 2867 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 2868 *test_results = resp->test_success; 2869 mutex_unlock(&bp->hwrm_cmd_lock); 2870 return rc; 2871 } 2872 2873 #define BNXT_DRV_TESTS 4 2874 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 2875 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 2876 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 2877 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 2878 2879 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 2880 u64 *buf) 2881 { 2882 struct bnxt *bp = netdev_priv(dev); 2883 bool do_ext_lpbk = false; 2884 bool offline = false; 2885 u8 test_results = 0; 2886 u8 test_mask = 0; 2887 int rc = 0, i; 2888 2889 if (!bp->num_tests || !BNXT_SINGLE_PF(bp)) 2890 return; 2891 memset(buf, 0, sizeof(u64) * bp->num_tests); 2892 if (!netif_running(dev)) { 2893 etest->flags |= ETH_TEST_FL_FAILED; 2894 return; 2895 } 2896 2897 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 2898 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 2899 do_ext_lpbk = true; 2900 2901 if (etest->flags & ETH_TEST_FL_OFFLINE) { 2902 if (bp->pf.active_vfs) { 2903 etest->flags |= ETH_TEST_FL_FAILED; 2904 netdev_warn(dev, "Offline tests cannot be run with active VFs\n"); 2905 return; 2906 } 2907 offline = true; 2908 } 2909 2910 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 2911 u8 bit_val = 1 << i; 2912 2913 if (!(bp->test_info->offline_mask & bit_val)) 2914 test_mask |= bit_val; 2915 else if (offline) 2916 test_mask |= bit_val; 2917 } 2918 if (!offline) { 2919 bnxt_run_fw_tests(bp, test_mask, &test_results); 2920 } else { 2921 rc = bnxt_close_nic(bp, false, false); 2922 if (rc) 2923 return; 2924 bnxt_run_fw_tests(bp, test_mask, &test_results); 2925 2926 buf[BNXT_MACLPBK_TEST_IDX] = 1; 2927 bnxt_hwrm_mac_loopback(bp, true); 2928 msleep(250); 2929 rc = bnxt_half_open_nic(bp); 2930 if (rc) { 2931 bnxt_hwrm_mac_loopback(bp, false); 2932 etest->flags |= ETH_TEST_FL_FAILED; 2933 return; 2934 } 2935 if (bnxt_run_loopback(bp)) 2936 etest->flags |= ETH_TEST_FL_FAILED; 2937 else 2938 buf[BNXT_MACLPBK_TEST_IDX] = 0; 2939 2940 bnxt_hwrm_mac_loopback(bp, false); 2941 bnxt_hwrm_phy_loopback(bp, true, false); 2942 msleep(1000); 2943 if (bnxt_run_loopback(bp)) { 2944 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 2945 etest->flags |= ETH_TEST_FL_FAILED; 2946 } 2947 if (do_ext_lpbk) { 2948 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 2949 bnxt_hwrm_phy_loopback(bp, true, true); 2950 msleep(1000); 2951 if (bnxt_run_loopback(bp)) { 2952 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 2953 etest->flags |= ETH_TEST_FL_FAILED; 2954 } 2955 } 2956 bnxt_hwrm_phy_loopback(bp, false, false); 2957 bnxt_half_close_nic(bp); 2958 rc = bnxt_open_nic(bp, false, true); 2959 } 2960 if (rc || bnxt_test_irq(bp)) { 2961 buf[BNXT_IRQ_TEST_IDX] = 1; 2962 etest->flags |= ETH_TEST_FL_FAILED; 2963 } 2964 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 2965 u8 bit_val = 1 << i; 2966 2967 if ((test_mask & bit_val) && !(test_results & bit_val)) { 2968 buf[i] = 1; 2969 etest->flags |= ETH_TEST_FL_FAILED; 2970 } 2971 } 2972 } 2973 2974 static int bnxt_reset(struct net_device *dev, u32 *flags) 2975 { 2976 struct bnxt *bp = netdev_priv(dev); 2977 int rc = 0; 2978 2979 if (!BNXT_PF(bp)) { 2980 netdev_err(dev, "Reset is not supported from a VF\n"); 2981 return -EOPNOTSUPP; 2982 } 2983 2984 if (pci_vfs_assigned(bp->pdev)) { 2985 netdev_err(dev, 2986 "Reset not allowed when VFs are assigned to VMs\n"); 2987 return -EBUSY; 2988 } 2989 2990 if (*flags == ETH_RESET_ALL) { 2991 /* This feature is not supported in older firmware versions */ 2992 if (bp->hwrm_spec_code < 0x10803) 2993 return -EOPNOTSUPP; 2994 2995 rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_CHIP); 2996 if (!rc) { 2997 netdev_info(dev, "Reset request successful. Reload driver to complete reset\n"); 2998 *flags = 0; 2999 } 3000 } else if (*flags == ETH_RESET_AP) { 3001 /* This feature is not supported in older firmware versions */ 3002 if (bp->hwrm_spec_code < 0x10803) 3003 return -EOPNOTSUPP; 3004 3005 rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_AP); 3006 if (!rc) { 3007 netdev_info(dev, "Reset Application Processor request successful.\n"); 3008 *flags = 0; 3009 } 3010 } else { 3011 rc = -EINVAL; 3012 } 3013 3014 return rc; 3015 } 3016 3017 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3018 struct bnxt_hwrm_dbg_dma_info *info) 3019 { 3020 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3021 struct hwrm_dbg_cmn_input *cmn_req = msg; 3022 __le16 *seq_ptr = msg + info->seq_off; 3023 u16 seq = 0, len, segs_off; 3024 void *resp = cmn_resp; 3025 dma_addr_t dma_handle; 3026 int rc, off = 0; 3027 void *dma_buf; 3028 3029 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3030 GFP_KERNEL); 3031 if (!dma_buf) 3032 return -ENOMEM; 3033 3034 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3035 total_segments); 3036 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3037 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3038 mutex_lock(&bp->hwrm_cmd_lock); 3039 while (1) { 3040 *seq_ptr = cpu_to_le16(seq); 3041 rc = _hwrm_send_message(bp, msg, msg_len, HWRM_CMD_TIMEOUT); 3042 if (rc) 3043 break; 3044 3045 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3046 if (!seq && 3047 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3048 info->segs = le16_to_cpu(*((__le16 *)(resp + 3049 segs_off))); 3050 if (!info->segs) { 3051 rc = -EIO; 3052 break; 3053 } 3054 3055 info->dest_buf_size = info->segs * 3056 sizeof(struct coredump_segment_record); 3057 info->dest_buf = kmalloc(info->dest_buf_size, 3058 GFP_KERNEL); 3059 if (!info->dest_buf) { 3060 rc = -ENOMEM; 3061 break; 3062 } 3063 } 3064 3065 if (info->dest_buf) 3066 memcpy(info->dest_buf + off, dma_buf, len); 3067 3068 if (cmn_req->req_type == 3069 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3070 info->dest_buf_size += len; 3071 3072 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3073 break; 3074 3075 seq++; 3076 off += len; 3077 } 3078 mutex_unlock(&bp->hwrm_cmd_lock); 3079 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3080 return rc; 3081 } 3082 3083 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3084 struct bnxt_coredump *coredump) 3085 { 3086 struct hwrm_dbg_coredump_list_input req = {0}; 3087 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3088 int rc; 3089 3090 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3091 3092 info.dma_len = COREDUMP_LIST_BUF_LEN; 3093 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3094 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3095 data_len); 3096 3097 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3098 if (!rc) { 3099 coredump->data = info.dest_buf; 3100 coredump->data_size = info.dest_buf_size; 3101 coredump->total_segs = info.segs; 3102 } 3103 return rc; 3104 } 3105 3106 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3107 u16 segment_id) 3108 { 3109 struct hwrm_dbg_coredump_initiate_input req = {0}; 3110 3111 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3112 req.component_id = cpu_to_le16(component_id); 3113 req.segment_id = cpu_to_le16(segment_id); 3114 3115 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3116 } 3117 3118 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3119 u16 segment_id, u32 *seg_len, 3120 void *buf, u32 offset) 3121 { 3122 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3123 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3124 int rc; 3125 3126 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3127 req.component_id = cpu_to_le16(component_id); 3128 req.segment_id = cpu_to_le16(segment_id); 3129 3130 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3131 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3132 seq_no); 3133 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3134 data_len); 3135 if (buf) 3136 info.dest_buf = buf + offset; 3137 3138 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3139 if (!rc) 3140 *seg_len = info.dest_buf_size; 3141 3142 return rc; 3143 } 3144 3145 static void 3146 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3147 struct bnxt_coredump_segment_hdr *seg_hdr, 3148 struct coredump_segment_record *seg_rec, u32 seg_len, 3149 int status, u32 duration, u32 instance) 3150 { 3151 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3152 memcpy(seg_hdr->signature, "sEgM", 4); 3153 if (seg_rec) { 3154 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3155 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3156 seg_hdr->low_version = seg_rec->version_low; 3157 seg_hdr->high_version = seg_rec->version_hi; 3158 } else { 3159 /* For hwrm_ver_get response Component id = 2 3160 * and Segment id = 0 3161 */ 3162 seg_hdr->component_id = cpu_to_le32(2); 3163 seg_hdr->segment_id = 0; 3164 } 3165 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3166 seg_hdr->length = cpu_to_le32(seg_len); 3167 seg_hdr->status = cpu_to_le32(status); 3168 seg_hdr->duration = cpu_to_le32(duration); 3169 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3170 seg_hdr->instance = cpu_to_le32(instance); 3171 } 3172 3173 static void 3174 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3175 time64_t start, s16 start_utc, u16 total_segs, 3176 int status) 3177 { 3178 time64_t end = ktime_get_real_seconds(); 3179 u32 os_ver_major = 0, os_ver_minor = 0; 3180 struct tm tm; 3181 3182 time64_to_tm(start, 0, &tm); 3183 memset(record, 0, sizeof(*record)); 3184 memcpy(record->signature, "cOrE", 4); 3185 record->flags = 0; 3186 record->low_version = 0; 3187 record->high_version = 1; 3188 record->asic_state = 0; 3189 strlcpy(record->system_name, utsname()->nodename, 3190 sizeof(record->system_name)); 3191 record->year = cpu_to_le16(tm.tm_year + 1900); 3192 record->month = cpu_to_le16(tm.tm_mon + 1); 3193 record->day = cpu_to_le16(tm.tm_mday); 3194 record->hour = cpu_to_le16(tm.tm_hour); 3195 record->minute = cpu_to_le16(tm.tm_min); 3196 record->second = cpu_to_le16(tm.tm_sec); 3197 record->utc_bias = cpu_to_le16(start_utc); 3198 strcpy(record->commandline, "ethtool -w"); 3199 record->total_segments = cpu_to_le32(total_segs); 3200 3201 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3202 record->os_ver_major = cpu_to_le32(os_ver_major); 3203 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3204 3205 strlcpy(record->os_name, utsname()->sysname, 32); 3206 time64_to_tm(end, 0, &tm); 3207 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3208 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3209 record->end_day = cpu_to_le16(tm.tm_mday); 3210 record->end_hour = cpu_to_le16(tm.tm_hour); 3211 record->end_minute = cpu_to_le16(tm.tm_min); 3212 record->end_second = cpu_to_le16(tm.tm_sec); 3213 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3214 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3215 bp->ver_resp.chip_rev << 8 | 3216 bp->ver_resp.chip_metal); 3217 record->asic_id2 = 0; 3218 record->coredump_status = cpu_to_le32(status); 3219 record->ioctl_low_version = 0; 3220 record->ioctl_high_version = 0; 3221 } 3222 3223 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3224 { 3225 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3226 struct coredump_segment_record *seg_record = NULL; 3227 u32 offset = 0, seg_hdr_len, seg_record_len; 3228 struct bnxt_coredump_segment_hdr seg_hdr; 3229 struct bnxt_coredump coredump = {NULL}; 3230 time64_t start_time; 3231 u16 start_utc; 3232 int rc = 0, i; 3233 3234 start_time = ktime_get_real_seconds(); 3235 start_utc = sys_tz.tz_minuteswest * 60; 3236 seg_hdr_len = sizeof(seg_hdr); 3237 3238 /* First segment should be hwrm_ver_get response */ 3239 *dump_len = seg_hdr_len + ver_get_resp_len; 3240 if (buf) { 3241 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3242 0, 0, 0); 3243 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3244 offset += seg_hdr_len; 3245 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3246 offset += ver_get_resp_len; 3247 } 3248 3249 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3250 if (rc) { 3251 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3252 goto err; 3253 } 3254 3255 *dump_len += seg_hdr_len * coredump.total_segs; 3256 3257 seg_record = (struct coredump_segment_record *)coredump.data; 3258 seg_record_len = sizeof(*seg_record); 3259 3260 for (i = 0; i < coredump.total_segs; i++) { 3261 u16 comp_id = le16_to_cpu(seg_record->component_id); 3262 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3263 u32 duration = 0, seg_len = 0; 3264 unsigned long start, end; 3265 3266 start = jiffies; 3267 3268 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3269 if (rc) { 3270 netdev_err(bp->dev, 3271 "Failed to initiate coredump for seg = %d\n", 3272 seg_record->segment_id); 3273 goto next_seg; 3274 } 3275 3276 /* Write segment data into the buffer */ 3277 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3278 &seg_len, buf, 3279 offset + seg_hdr_len); 3280 if (rc) 3281 netdev_err(bp->dev, 3282 "Failed to retrieve coredump for seg = %d\n", 3283 seg_record->segment_id); 3284 3285 next_seg: 3286 end = jiffies; 3287 duration = jiffies_to_msecs(end - start); 3288 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3289 rc, duration, 0); 3290 3291 if (buf) { 3292 /* Write segment header into the buffer */ 3293 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3294 offset += seg_hdr_len + seg_len; 3295 } 3296 3297 *dump_len += seg_len; 3298 seg_record = 3299 (struct coredump_segment_record *)((u8 *)seg_record + 3300 seg_record_len); 3301 } 3302 3303 err: 3304 if (buf) 3305 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3306 start_utc, coredump.total_segs + 1, 3307 rc); 3308 kfree(coredump.data); 3309 *dump_len += sizeof(struct bnxt_coredump_record); 3310 3311 return rc; 3312 } 3313 3314 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3315 { 3316 struct bnxt *bp = netdev_priv(dev); 3317 3318 if (bp->hwrm_spec_code < 0x10801) 3319 return -EOPNOTSUPP; 3320 3321 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3322 bp->ver_resp.hwrm_fw_min_8b << 16 | 3323 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3324 bp->ver_resp.hwrm_fw_rsvd_8b; 3325 3326 return bnxt_get_coredump(bp, NULL, &dump->len); 3327 } 3328 3329 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3330 void *buf) 3331 { 3332 struct bnxt *bp = netdev_priv(dev); 3333 3334 if (bp->hwrm_spec_code < 0x10801) 3335 return -EOPNOTSUPP; 3336 3337 memset(buf, 0, dump->len); 3338 3339 return bnxt_get_coredump(bp, buf, &dump->len); 3340 } 3341 3342 void bnxt_ethtool_init(struct bnxt *bp) 3343 { 3344 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3345 struct hwrm_selftest_qlist_input req = {0}; 3346 struct bnxt_test_info *test_info; 3347 struct net_device *dev = bp->dev; 3348 int i, rc; 3349 3350 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3351 bnxt_get_pkgver(dev); 3352 3353 bp->num_tests = 0; 3354 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp)) 3355 return; 3356 3357 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3358 mutex_lock(&bp->hwrm_cmd_lock); 3359 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3360 if (rc) 3361 goto ethtool_init_exit; 3362 3363 test_info = bp->test_info; 3364 if (!test_info) 3365 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3366 if (!test_info) 3367 goto ethtool_init_exit; 3368 3369 bp->test_info = test_info; 3370 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3371 if (bp->num_tests > BNXT_MAX_TEST) 3372 bp->num_tests = BNXT_MAX_TEST; 3373 3374 test_info->offline_mask = resp->offline_tests; 3375 test_info->timeout = le16_to_cpu(resp->test_timeout); 3376 if (!test_info->timeout) 3377 test_info->timeout = HWRM_CMD_TIMEOUT; 3378 for (i = 0; i < bp->num_tests; i++) { 3379 char *str = test_info->string[i]; 3380 char *fw_str = resp->test0_name + i * 32; 3381 3382 if (i == BNXT_MACLPBK_TEST_IDX) { 3383 strcpy(str, "Mac loopback test (offline)"); 3384 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3385 strcpy(str, "Phy loopback test (offline)"); 3386 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3387 strcpy(str, "Ext loopback test (offline)"); 3388 } else if (i == BNXT_IRQ_TEST_IDX) { 3389 strcpy(str, "Interrupt_test (offline)"); 3390 } else { 3391 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3392 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3393 if (test_info->offline_mask & (1 << i)) 3394 strncat(str, " (offline)", 3395 ETH_GSTRING_LEN - strlen(str)); 3396 else 3397 strncat(str, " (online)", 3398 ETH_GSTRING_LEN - strlen(str)); 3399 } 3400 } 3401 3402 ethtool_init_exit: 3403 mutex_unlock(&bp->hwrm_cmd_lock); 3404 } 3405 3406 void bnxt_ethtool_free(struct bnxt *bp) 3407 { 3408 kfree(bp->test_info); 3409 bp->test_info = NULL; 3410 } 3411 3412 const struct ethtool_ops bnxt_ethtool_ops = { 3413 .get_link_ksettings = bnxt_get_link_ksettings, 3414 .set_link_ksettings = bnxt_set_link_ksettings, 3415 .get_pauseparam = bnxt_get_pauseparam, 3416 .set_pauseparam = bnxt_set_pauseparam, 3417 .get_drvinfo = bnxt_get_drvinfo, 3418 .get_wol = bnxt_get_wol, 3419 .set_wol = bnxt_set_wol, 3420 .get_coalesce = bnxt_get_coalesce, 3421 .set_coalesce = bnxt_set_coalesce, 3422 .get_msglevel = bnxt_get_msglevel, 3423 .set_msglevel = bnxt_set_msglevel, 3424 .get_sset_count = bnxt_get_sset_count, 3425 .get_strings = bnxt_get_strings, 3426 .get_ethtool_stats = bnxt_get_ethtool_stats, 3427 .set_ringparam = bnxt_set_ringparam, 3428 .get_ringparam = bnxt_get_ringparam, 3429 .get_channels = bnxt_get_channels, 3430 .set_channels = bnxt_set_channels, 3431 .get_rxnfc = bnxt_get_rxnfc, 3432 .set_rxnfc = bnxt_set_rxnfc, 3433 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3434 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3435 .get_rxfh = bnxt_get_rxfh, 3436 .flash_device = bnxt_flash_device, 3437 .get_eeprom_len = bnxt_get_eeprom_len, 3438 .get_eeprom = bnxt_get_eeprom, 3439 .set_eeprom = bnxt_set_eeprom, 3440 .get_link = bnxt_get_link, 3441 .get_eee = bnxt_get_eee, 3442 .set_eee = bnxt_set_eee, 3443 .get_module_info = bnxt_get_module_info, 3444 .get_module_eeprom = bnxt_get_module_eeprom, 3445 .nway_reset = bnxt_nway_reset, 3446 .set_phys_id = bnxt_set_phys_id, 3447 .self_test = bnxt_self_test, 3448 .reset = bnxt_reset, 3449 .get_dump_flag = bnxt_get_dump_flag, 3450 .get_dump_data = bnxt_get_dump_data, 3451 }; 3452