1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/etherdevice.h> 17 #include <linux/crc32.h> 18 #include <linux/firmware.h> 19 #include <linux/utsname.h> 20 #include <linux/time.h> 21 #include "bnxt_hsi.h" 22 #include "bnxt.h" 23 #include "bnxt_xdp.h" 24 #include "bnxt_ethtool.h" 25 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 26 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 27 #include "bnxt_coredump.h" 28 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 29 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 30 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 32 static u32 bnxt_get_msglevel(struct net_device *dev) 33 { 34 struct bnxt *bp = netdev_priv(dev); 35 36 return bp->msg_enable; 37 } 38 39 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 40 { 41 struct bnxt *bp = netdev_priv(dev); 42 43 bp->msg_enable = value; 44 } 45 46 static int bnxt_get_coalesce(struct net_device *dev, 47 struct ethtool_coalesce *coal) 48 { 49 struct bnxt *bp = netdev_priv(dev); 50 struct bnxt_coal *hw_coal; 51 u16 mult; 52 53 memset(coal, 0, sizeof(*coal)); 54 55 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 56 57 hw_coal = &bp->rx_coal; 58 mult = hw_coal->bufs_per_record; 59 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 60 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 61 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 62 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 63 64 hw_coal = &bp->tx_coal; 65 mult = hw_coal->bufs_per_record; 66 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 67 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 68 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 69 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 70 71 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 72 73 return 0; 74 } 75 76 static int bnxt_set_coalesce(struct net_device *dev, 77 struct ethtool_coalesce *coal) 78 { 79 struct bnxt *bp = netdev_priv(dev); 80 bool update_stats = false; 81 struct bnxt_coal *hw_coal; 82 int rc = 0; 83 u16 mult; 84 85 if (coal->use_adaptive_rx_coalesce) { 86 bp->flags |= BNXT_FLAG_DIM; 87 } else { 88 if (bp->flags & BNXT_FLAG_DIM) { 89 bp->flags &= ~(BNXT_FLAG_DIM); 90 goto reset_coalesce; 91 } 92 } 93 94 hw_coal = &bp->rx_coal; 95 mult = hw_coal->bufs_per_record; 96 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 97 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 98 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 99 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 100 101 hw_coal = &bp->tx_coal; 102 mult = hw_coal->bufs_per_record; 103 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 104 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 105 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 106 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 107 108 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 109 u32 stats_ticks = coal->stats_block_coalesce_usecs; 110 111 /* Allow 0, which means disable. */ 112 if (stats_ticks) 113 stats_ticks = clamp_t(u32, stats_ticks, 114 BNXT_MIN_STATS_COAL_TICKS, 115 BNXT_MAX_STATS_COAL_TICKS); 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 117 bp->stats_coal_ticks = stats_ticks; 118 if (bp->stats_coal_ticks) 119 bp->current_interval = 120 bp->stats_coal_ticks * HZ / 1000000; 121 else 122 bp->current_interval = BNXT_TIMER_INTERVAL; 123 update_stats = true; 124 } 125 126 reset_coalesce: 127 if (netif_running(dev)) { 128 if (update_stats) { 129 rc = bnxt_close_nic(bp, true, false); 130 if (!rc) 131 rc = bnxt_open_nic(bp, true, false); 132 } else { 133 rc = bnxt_hwrm_set_coal(bp); 134 } 135 } 136 137 return rc; 138 } 139 140 static const char * const bnxt_ring_rx_stats_str[] = { 141 "rx_ucast_packets", 142 "rx_mcast_packets", 143 "rx_bcast_packets", 144 "rx_discards", 145 "rx_drops", 146 "rx_ucast_bytes", 147 "rx_mcast_bytes", 148 "rx_bcast_bytes", 149 }; 150 151 static const char * const bnxt_ring_tx_stats_str[] = { 152 "tx_ucast_packets", 153 "tx_mcast_packets", 154 "tx_bcast_packets", 155 "tx_discards", 156 "tx_drops", 157 "tx_ucast_bytes", 158 "tx_mcast_bytes", 159 "tx_bcast_bytes", 160 }; 161 162 static const char * const bnxt_ring_tpa_stats_str[] = { 163 "tpa_packets", 164 "tpa_bytes", 165 "tpa_events", 166 "tpa_aborts", 167 }; 168 169 static const char * const bnxt_ring_tpa2_stats_str[] = { 170 "rx_tpa_eligible_pkt", 171 "rx_tpa_eligible_bytes", 172 "rx_tpa_pkt", 173 "rx_tpa_bytes", 174 "rx_tpa_errors", 175 }; 176 177 static const char * const bnxt_rx_sw_stats_str[] = { 178 "rx_l4_csum_errors", 179 "rx_buf_errors", 180 }; 181 182 static const char * const bnxt_cmn_sw_stats_str[] = { 183 "missed_irqs", 184 }; 185 186 #define BNXT_RX_STATS_ENTRY(counter) \ 187 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 188 189 #define BNXT_TX_STATS_ENTRY(counter) \ 190 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 191 192 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 193 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 194 195 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 196 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 197 198 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 199 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 200 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 201 202 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 203 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 204 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 205 206 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 207 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 208 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 209 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 210 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 211 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 212 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 213 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 214 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 215 216 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 217 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 218 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 219 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 220 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 221 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 222 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 223 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 224 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 225 226 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 227 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 228 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 229 230 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 231 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 232 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 233 234 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 235 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 236 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 237 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 238 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 239 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 240 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 241 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 242 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 243 244 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 245 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 246 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 247 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 248 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 249 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 250 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 251 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 252 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 253 254 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 255 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 256 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 257 258 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 259 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 260 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 261 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 267 268 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 269 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 270 __stringify(counter##_pri##n) } 271 272 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 273 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 274 __stringify(counter##_pri##n) } 275 276 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 277 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 278 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 279 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 280 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 281 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 282 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 283 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 284 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 285 286 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 287 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 288 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 289 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 290 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 291 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 292 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 293 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 294 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 295 296 #define BNXT_PCIE_STATS_ENTRY(counter) \ 297 { BNXT_PCIE_STATS_OFFSET(counter), __stringify(counter) } 298 299 enum { 300 RX_TOTAL_DISCARDS, 301 TX_TOTAL_DISCARDS, 302 }; 303 304 static struct { 305 u64 counter; 306 char string[ETH_GSTRING_LEN]; 307 } bnxt_sw_func_stats[] = { 308 {0, "rx_total_discard_pkts"}, 309 {0, "tx_total_discard_pkts"}, 310 }; 311 312 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 313 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 314 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 315 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 316 317 static const struct { 318 long offset; 319 char string[ETH_GSTRING_LEN]; 320 } bnxt_port_stats_arr[] = { 321 BNXT_RX_STATS_ENTRY(rx_64b_frames), 322 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 323 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 324 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 325 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 326 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 327 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 328 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 329 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 330 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 331 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 332 BNXT_RX_STATS_ENTRY(rx_total_frames), 333 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 334 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 335 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 336 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 337 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 338 BNXT_RX_STATS_ENTRY(rx_pause_frames), 339 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 340 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 341 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 342 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 343 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 344 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 345 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 346 BNXT_RX_STATS_ENTRY(rx_good_frames), 347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 354 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 355 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 357 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 358 BNXT_RX_STATS_ENTRY(rx_bytes), 359 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 360 BNXT_RX_STATS_ENTRY(rx_runt_frames), 361 BNXT_RX_STATS_ENTRY(rx_stat_discard), 362 BNXT_RX_STATS_ENTRY(rx_stat_err), 363 364 BNXT_TX_STATS_ENTRY(tx_64b_frames), 365 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 366 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 367 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 368 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 369 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 370 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 371 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 372 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 373 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 374 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 375 BNXT_TX_STATS_ENTRY(tx_good_frames), 376 BNXT_TX_STATS_ENTRY(tx_total_frames), 377 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 378 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 379 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 380 BNXT_TX_STATS_ENTRY(tx_pause_frames), 381 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 382 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 383 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 384 BNXT_TX_STATS_ENTRY(tx_err), 385 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 393 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 395 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 396 BNXT_TX_STATS_ENTRY(tx_total_collisions), 397 BNXT_TX_STATS_ENTRY(tx_bytes), 398 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 399 BNXT_TX_STATS_ENTRY(tx_stat_discard), 400 BNXT_TX_STATS_ENTRY(tx_stat_error), 401 }; 402 403 static const struct { 404 long offset; 405 char string[ETH_GSTRING_LEN]; 406 } bnxt_port_stats_ext_arr[] = { 407 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 408 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 409 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 410 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 411 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 412 BNXT_RX_STATS_EXT_COS_ENTRIES, 413 BNXT_RX_STATS_EXT_PFC_ENTRIES, 414 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 415 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 416 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 417 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 418 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 419 }; 420 421 static const struct { 422 long offset; 423 char string[ETH_GSTRING_LEN]; 424 } bnxt_tx_port_stats_ext_arr[] = { 425 BNXT_TX_STATS_EXT_COS_ENTRIES, 426 BNXT_TX_STATS_EXT_PFC_ENTRIES, 427 }; 428 429 static const struct { 430 long base_off; 431 char string[ETH_GSTRING_LEN]; 432 } bnxt_rx_bytes_pri_arr[] = { 433 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 434 }; 435 436 static const struct { 437 long base_off; 438 char string[ETH_GSTRING_LEN]; 439 } bnxt_rx_pkts_pri_arr[] = { 440 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 441 }; 442 443 static const struct { 444 long base_off; 445 char string[ETH_GSTRING_LEN]; 446 } bnxt_tx_bytes_pri_arr[] = { 447 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 448 }; 449 450 static const struct { 451 long base_off; 452 char string[ETH_GSTRING_LEN]; 453 } bnxt_tx_pkts_pri_arr[] = { 454 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 455 }; 456 457 static const struct { 458 long offset; 459 char string[ETH_GSTRING_LEN]; 460 } bnxt_pcie_stats_arr[] = { 461 BNXT_PCIE_STATS_ENTRY(pcie_pl_signal_integrity), 462 BNXT_PCIE_STATS_ENTRY(pcie_dl_signal_integrity), 463 BNXT_PCIE_STATS_ENTRY(pcie_tl_signal_integrity), 464 BNXT_PCIE_STATS_ENTRY(pcie_link_integrity), 465 BNXT_PCIE_STATS_ENTRY(pcie_tx_traffic_rate), 466 BNXT_PCIE_STATS_ENTRY(pcie_rx_traffic_rate), 467 BNXT_PCIE_STATS_ENTRY(pcie_tx_dllp_statistics), 468 BNXT_PCIE_STATS_ENTRY(pcie_rx_dllp_statistics), 469 BNXT_PCIE_STATS_ENTRY(pcie_equalization_time), 470 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[0]), 471 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[2]), 472 BNXT_PCIE_STATS_ENTRY(pcie_recovery_histogram), 473 }; 474 475 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 476 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 477 #define BNXT_NUM_STATS_PRI \ 478 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 479 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 480 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 481 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 482 #define BNXT_NUM_PCIE_STATS ARRAY_SIZE(bnxt_pcie_stats_arr) 483 484 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 485 { 486 if (BNXT_SUPPORTS_TPA(bp)) { 487 if (bp->max_tpa_v2) 488 return ARRAY_SIZE(bnxt_ring_tpa2_stats_str); 489 return ARRAY_SIZE(bnxt_ring_tpa_stats_str); 490 } 491 return 0; 492 } 493 494 static int bnxt_get_num_ring_stats(struct bnxt *bp) 495 { 496 int rx, tx, cmn; 497 bool sh = false; 498 499 if (bp->flags & BNXT_FLAG_SHARED_RINGS) 500 sh = true; 501 502 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 503 bnxt_get_num_tpa_ring_stats(bp); 504 tx = NUM_RING_TX_HW_STATS; 505 cmn = NUM_RING_CMN_SW_STATS; 506 if (sh) 507 return (rx + tx + cmn) * bp->cp_nr_rings; 508 else 509 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 510 cmn * bp->cp_nr_rings; 511 } 512 513 static int bnxt_get_num_stats(struct bnxt *bp) 514 { 515 int num_stats = bnxt_get_num_ring_stats(bp); 516 517 num_stats += BNXT_NUM_SW_FUNC_STATS; 518 519 if (bp->flags & BNXT_FLAG_PORT_STATS) 520 num_stats += BNXT_NUM_PORT_STATS; 521 522 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 523 num_stats += bp->fw_rx_stats_ext_size + 524 bp->fw_tx_stats_ext_size; 525 if (bp->pri2cos_valid) 526 num_stats += BNXT_NUM_STATS_PRI; 527 } 528 529 if (bp->flags & BNXT_FLAG_PCIE_STATS) 530 num_stats += BNXT_NUM_PCIE_STATS; 531 532 return num_stats; 533 } 534 535 static int bnxt_get_sset_count(struct net_device *dev, int sset) 536 { 537 struct bnxt *bp = netdev_priv(dev); 538 539 switch (sset) { 540 case ETH_SS_STATS: 541 return bnxt_get_num_stats(bp); 542 case ETH_SS_TEST: 543 if (!bp->num_tests) 544 return -EOPNOTSUPP; 545 return bp->num_tests; 546 default: 547 return -EOPNOTSUPP; 548 } 549 } 550 551 static bool is_rx_ring(struct bnxt *bp, int ring_num) 552 { 553 return ring_num < bp->rx_nr_rings; 554 } 555 556 static bool is_tx_ring(struct bnxt *bp, int ring_num) 557 { 558 int tx_base = 0; 559 560 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 561 tx_base = bp->rx_nr_rings; 562 563 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 564 return true; 565 return false; 566 } 567 568 static void bnxt_get_ethtool_stats(struct net_device *dev, 569 struct ethtool_stats *stats, u64 *buf) 570 { 571 u32 i, j = 0; 572 struct bnxt *bp = netdev_priv(dev); 573 u32 tpa_stats; 574 575 if (!bp->bnapi) { 576 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 577 goto skip_ring_stats; 578 } 579 580 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 581 bnxt_sw_func_stats[i].counter = 0; 582 583 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 584 for (i = 0; i < bp->cp_nr_rings; i++) { 585 struct bnxt_napi *bnapi = bp->bnapi[i]; 586 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 587 __le64 *hw_stats = (__le64 *)cpr->hw_stats; 588 u64 *sw; 589 int k; 590 591 if (is_rx_ring(bp, i)) { 592 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 593 buf[j] = le64_to_cpu(hw_stats[k]); 594 } 595 if (is_tx_ring(bp, i)) { 596 k = NUM_RING_RX_HW_STATS; 597 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 598 j++, k++) 599 buf[j] = le64_to_cpu(hw_stats[k]); 600 } 601 if (!tpa_stats || !is_rx_ring(bp, i)) 602 goto skip_tpa_ring_stats; 603 604 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 605 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 606 tpa_stats; j++, k++) 607 buf[j] = le64_to_cpu(hw_stats[k]); 608 609 skip_tpa_ring_stats: 610 sw = (u64 *)&cpr->sw_stats.rx; 611 if (is_rx_ring(bp, i)) { 612 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 613 buf[j] = sw[k]; 614 } 615 616 sw = (u64 *)&cpr->sw_stats.cmn; 617 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 618 buf[j] = sw[k]; 619 620 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 621 le64_to_cpu(cpr->hw_stats->rx_discard_pkts); 622 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 623 le64_to_cpu(cpr->hw_stats->tx_discard_pkts); 624 } 625 626 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 627 buf[j] = bnxt_sw_func_stats[i].counter; 628 629 skip_ring_stats: 630 if (bp->flags & BNXT_FLAG_PORT_STATS) { 631 __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats; 632 633 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) { 634 buf[j] = le64_to_cpu(*(port_stats + 635 bnxt_port_stats_arr[i].offset)); 636 } 637 } 638 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 639 __le64 *rx_port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext; 640 __le64 *tx_port_stats_ext = (__le64 *)bp->hw_tx_port_stats_ext; 641 642 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 643 buf[j] = le64_to_cpu(*(rx_port_stats_ext + 644 bnxt_port_stats_ext_arr[i].offset)); 645 } 646 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 647 buf[j] = le64_to_cpu(*(tx_port_stats_ext + 648 bnxt_tx_port_stats_ext_arr[i].offset)); 649 } 650 if (bp->pri2cos_valid) { 651 for (i = 0; i < 8; i++, j++) { 652 long n = bnxt_rx_bytes_pri_arr[i].base_off + 653 bp->pri2cos_idx[i]; 654 655 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 656 } 657 for (i = 0; i < 8; i++, j++) { 658 long n = bnxt_rx_pkts_pri_arr[i].base_off + 659 bp->pri2cos_idx[i]; 660 661 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n)); 662 } 663 for (i = 0; i < 8; i++, j++) { 664 long n = bnxt_tx_bytes_pri_arr[i].base_off + 665 bp->pri2cos_idx[i]; 666 667 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 668 } 669 for (i = 0; i < 8; i++, j++) { 670 long n = bnxt_tx_pkts_pri_arr[i].base_off + 671 bp->pri2cos_idx[i]; 672 673 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n)); 674 } 675 } 676 } 677 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 678 __le64 *pcie_stats = (__le64 *)bp->hw_pcie_stats; 679 680 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++, j++) { 681 buf[j] = le64_to_cpu(*(pcie_stats + 682 bnxt_pcie_stats_arr[i].offset)); 683 } 684 } 685 } 686 687 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 688 { 689 struct bnxt *bp = netdev_priv(dev); 690 static const char * const *str; 691 u32 i, j, num_str; 692 693 switch (stringset) { 694 case ETH_SS_STATS: 695 for (i = 0; i < bp->cp_nr_rings; i++) { 696 if (is_rx_ring(bp, i)) { 697 num_str = NUM_RING_RX_HW_STATS; 698 for (j = 0; j < num_str; j++) { 699 sprintf(buf, "[%d]: %s", i, 700 bnxt_ring_rx_stats_str[j]); 701 buf += ETH_GSTRING_LEN; 702 } 703 } 704 if (is_tx_ring(bp, i)) { 705 num_str = NUM_RING_TX_HW_STATS; 706 for (j = 0; j < num_str; j++) { 707 sprintf(buf, "[%d]: %s", i, 708 bnxt_ring_tx_stats_str[j]); 709 buf += ETH_GSTRING_LEN; 710 } 711 } 712 num_str = bnxt_get_num_tpa_ring_stats(bp); 713 if (!num_str || !is_rx_ring(bp, i)) 714 goto skip_tpa_stats; 715 716 if (bp->max_tpa_v2) 717 str = bnxt_ring_tpa2_stats_str; 718 else 719 str = bnxt_ring_tpa_stats_str; 720 721 for (j = 0; j < num_str; j++) { 722 sprintf(buf, "[%d]: %s", i, str[j]); 723 buf += ETH_GSTRING_LEN; 724 } 725 skip_tpa_stats: 726 if (is_rx_ring(bp, i)) { 727 num_str = NUM_RING_RX_SW_STATS; 728 for (j = 0; j < num_str; j++) { 729 sprintf(buf, "[%d]: %s", i, 730 bnxt_rx_sw_stats_str[j]); 731 buf += ETH_GSTRING_LEN; 732 } 733 } 734 num_str = NUM_RING_CMN_SW_STATS; 735 for (j = 0; j < num_str; j++) { 736 sprintf(buf, "[%d]: %s", i, 737 bnxt_cmn_sw_stats_str[j]); 738 buf += ETH_GSTRING_LEN; 739 } 740 } 741 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 742 strcpy(buf, bnxt_sw_func_stats[i].string); 743 buf += ETH_GSTRING_LEN; 744 } 745 746 if (bp->flags & BNXT_FLAG_PORT_STATS) { 747 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 748 strcpy(buf, bnxt_port_stats_arr[i].string); 749 buf += ETH_GSTRING_LEN; 750 } 751 } 752 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 753 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 754 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 755 buf += ETH_GSTRING_LEN; 756 } 757 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 758 strcpy(buf, 759 bnxt_tx_port_stats_ext_arr[i].string); 760 buf += ETH_GSTRING_LEN; 761 } 762 if (bp->pri2cos_valid) { 763 for (i = 0; i < 8; i++) { 764 strcpy(buf, 765 bnxt_rx_bytes_pri_arr[i].string); 766 buf += ETH_GSTRING_LEN; 767 } 768 for (i = 0; i < 8; i++) { 769 strcpy(buf, 770 bnxt_rx_pkts_pri_arr[i].string); 771 buf += ETH_GSTRING_LEN; 772 } 773 for (i = 0; i < 8; i++) { 774 strcpy(buf, 775 bnxt_tx_bytes_pri_arr[i].string); 776 buf += ETH_GSTRING_LEN; 777 } 778 for (i = 0; i < 8; i++) { 779 strcpy(buf, 780 bnxt_tx_pkts_pri_arr[i].string); 781 buf += ETH_GSTRING_LEN; 782 } 783 } 784 } 785 if (bp->flags & BNXT_FLAG_PCIE_STATS) { 786 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++) { 787 strcpy(buf, bnxt_pcie_stats_arr[i].string); 788 buf += ETH_GSTRING_LEN; 789 } 790 } 791 break; 792 case ETH_SS_TEST: 793 if (bp->num_tests) 794 memcpy(buf, bp->test_info->string, 795 bp->num_tests * ETH_GSTRING_LEN); 796 break; 797 default: 798 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 799 stringset); 800 break; 801 } 802 } 803 804 static void bnxt_get_ringparam(struct net_device *dev, 805 struct ethtool_ringparam *ering) 806 { 807 struct bnxt *bp = netdev_priv(dev); 808 809 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 810 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 811 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 812 813 ering->rx_pending = bp->rx_ring_size; 814 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 815 ering->tx_pending = bp->tx_ring_size; 816 } 817 818 static int bnxt_set_ringparam(struct net_device *dev, 819 struct ethtool_ringparam *ering) 820 { 821 struct bnxt *bp = netdev_priv(dev); 822 823 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 824 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 825 (ering->tx_pending <= MAX_SKB_FRAGS)) 826 return -EINVAL; 827 828 if (netif_running(dev)) 829 bnxt_close_nic(bp, false, false); 830 831 bp->rx_ring_size = ering->rx_pending; 832 bp->tx_ring_size = ering->tx_pending; 833 bnxt_set_ring_params(bp); 834 835 if (netif_running(dev)) 836 return bnxt_open_nic(bp, false, false); 837 838 return 0; 839 } 840 841 static void bnxt_get_channels(struct net_device *dev, 842 struct ethtool_channels *channel) 843 { 844 struct bnxt *bp = netdev_priv(dev); 845 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 846 int max_rx_rings, max_tx_rings, tcs; 847 int max_tx_sch_inputs; 848 849 /* Get the most up-to-date max_tx_sch_inputs. */ 850 if (BNXT_NEW_RM(bp)) 851 bnxt_hwrm_func_resc_qcaps(bp, false); 852 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 853 854 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 855 if (max_tx_sch_inputs) 856 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 857 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 858 859 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 860 max_rx_rings = 0; 861 max_tx_rings = 0; 862 } 863 if (max_tx_sch_inputs) 864 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 865 866 tcs = netdev_get_num_tc(dev); 867 if (tcs > 1) 868 max_tx_rings /= tcs; 869 870 channel->max_rx = max_rx_rings; 871 channel->max_tx = max_tx_rings; 872 channel->max_other = 0; 873 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 874 channel->combined_count = bp->rx_nr_rings; 875 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 876 channel->combined_count--; 877 } else { 878 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 879 channel->rx_count = bp->rx_nr_rings; 880 channel->tx_count = bp->tx_nr_rings_per_tc; 881 } 882 } 883 } 884 885 static int bnxt_set_channels(struct net_device *dev, 886 struct ethtool_channels *channel) 887 { 888 struct bnxt *bp = netdev_priv(dev); 889 int req_tx_rings, req_rx_rings, tcs; 890 bool sh = false; 891 int tx_xdp = 0; 892 int rc = 0; 893 894 if (channel->other_count) 895 return -EINVAL; 896 897 if (!channel->combined_count && 898 (!channel->rx_count || !channel->tx_count)) 899 return -EINVAL; 900 901 if (channel->combined_count && 902 (channel->rx_count || channel->tx_count)) 903 return -EINVAL; 904 905 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 906 channel->tx_count)) 907 return -EINVAL; 908 909 if (channel->combined_count) 910 sh = true; 911 912 tcs = netdev_get_num_tc(dev); 913 914 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 915 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 916 if (bp->tx_nr_rings_xdp) { 917 if (!sh) { 918 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 919 return -EINVAL; 920 } 921 tx_xdp = req_rx_rings; 922 } 923 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 924 if (rc) { 925 netdev_warn(dev, "Unable to allocate the requested rings\n"); 926 return rc; 927 } 928 929 if (netif_running(dev)) { 930 if (BNXT_PF(bp)) { 931 /* TODO CHIMP_FW: Send message to all VF's 932 * before PF unload 933 */ 934 } 935 rc = bnxt_close_nic(bp, true, false); 936 if (rc) { 937 netdev_err(bp->dev, "Set channel failure rc :%x\n", 938 rc); 939 return rc; 940 } 941 } 942 943 if (sh) { 944 bp->flags |= BNXT_FLAG_SHARED_RINGS; 945 bp->rx_nr_rings = channel->combined_count; 946 bp->tx_nr_rings_per_tc = channel->combined_count; 947 } else { 948 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 949 bp->rx_nr_rings = channel->rx_count; 950 bp->tx_nr_rings_per_tc = channel->tx_count; 951 } 952 bp->tx_nr_rings_xdp = tx_xdp; 953 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 954 if (tcs > 1) 955 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 956 957 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 958 bp->tx_nr_rings + bp->rx_nr_rings; 959 960 /* After changing number of rx channels, update NTUPLE feature. */ 961 netdev_update_features(dev); 962 if (netif_running(dev)) { 963 rc = bnxt_open_nic(bp, true, false); 964 if ((!rc) && BNXT_PF(bp)) { 965 /* TODO CHIMP_FW: Send message to all VF's 966 * to renable 967 */ 968 } 969 } else { 970 rc = bnxt_reserve_rings(bp, true); 971 } 972 973 return rc; 974 } 975 976 #ifdef CONFIG_RFS_ACCEL 977 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 978 u32 *rule_locs) 979 { 980 int i, j = 0; 981 982 cmd->data = bp->ntp_fltr_count; 983 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 984 struct hlist_head *head; 985 struct bnxt_ntuple_filter *fltr; 986 987 head = &bp->ntp_fltr_hash_tbl[i]; 988 rcu_read_lock(); 989 hlist_for_each_entry_rcu(fltr, head, hash) { 990 if (j == cmd->rule_cnt) 991 break; 992 rule_locs[j++] = fltr->sw_id; 993 } 994 rcu_read_unlock(); 995 if (j == cmd->rule_cnt) 996 break; 997 } 998 cmd->rule_cnt = j; 999 return 0; 1000 } 1001 1002 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1003 { 1004 struct ethtool_rx_flow_spec *fs = 1005 (struct ethtool_rx_flow_spec *)&cmd->fs; 1006 struct bnxt_ntuple_filter *fltr; 1007 struct flow_keys *fkeys; 1008 int i, rc = -EINVAL; 1009 1010 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1011 return rc; 1012 1013 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1014 struct hlist_head *head; 1015 1016 head = &bp->ntp_fltr_hash_tbl[i]; 1017 rcu_read_lock(); 1018 hlist_for_each_entry_rcu(fltr, head, hash) { 1019 if (fltr->sw_id == fs->location) 1020 goto fltr_found; 1021 } 1022 rcu_read_unlock(); 1023 } 1024 return rc; 1025 1026 fltr_found: 1027 fkeys = &fltr->fkeys; 1028 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1029 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1030 fs->flow_type = TCP_V4_FLOW; 1031 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1032 fs->flow_type = UDP_V4_FLOW; 1033 else 1034 goto fltr_err; 1035 1036 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1037 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1038 1039 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1040 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1041 1042 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1043 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1044 1045 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1046 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1047 } else { 1048 int i; 1049 1050 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1051 fs->flow_type = TCP_V6_FLOW; 1052 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1053 fs->flow_type = UDP_V6_FLOW; 1054 else 1055 goto fltr_err; 1056 1057 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1058 fkeys->addrs.v6addrs.src; 1059 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1060 fkeys->addrs.v6addrs.dst; 1061 for (i = 0; i < 4; i++) { 1062 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1063 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1064 } 1065 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1066 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1067 1068 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1069 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1070 } 1071 1072 fs->ring_cookie = fltr->rxq; 1073 rc = 0; 1074 1075 fltr_err: 1076 rcu_read_unlock(); 1077 1078 return rc; 1079 } 1080 #endif 1081 1082 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1083 { 1084 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1085 return RXH_IP_SRC | RXH_IP_DST; 1086 return 0; 1087 } 1088 1089 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1090 { 1091 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1092 return RXH_IP_SRC | RXH_IP_DST; 1093 return 0; 1094 } 1095 1096 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1097 { 1098 cmd->data = 0; 1099 switch (cmd->flow_type) { 1100 case TCP_V4_FLOW: 1101 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1102 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1103 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1104 cmd->data |= get_ethtool_ipv4_rss(bp); 1105 break; 1106 case UDP_V4_FLOW: 1107 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1108 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1109 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1110 /* fall through */ 1111 case SCTP_V4_FLOW: 1112 case AH_ESP_V4_FLOW: 1113 case AH_V4_FLOW: 1114 case ESP_V4_FLOW: 1115 case IPV4_FLOW: 1116 cmd->data |= get_ethtool_ipv4_rss(bp); 1117 break; 1118 1119 case TCP_V6_FLOW: 1120 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1121 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1122 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1123 cmd->data |= get_ethtool_ipv6_rss(bp); 1124 break; 1125 case UDP_V6_FLOW: 1126 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1127 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1128 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1129 /* fall through */ 1130 case SCTP_V6_FLOW: 1131 case AH_ESP_V6_FLOW: 1132 case AH_V6_FLOW: 1133 case ESP_V6_FLOW: 1134 case IPV6_FLOW: 1135 cmd->data |= get_ethtool_ipv6_rss(bp); 1136 break; 1137 } 1138 return 0; 1139 } 1140 1141 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1142 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1143 1144 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1145 { 1146 u32 rss_hash_cfg = bp->rss_hash_cfg; 1147 int tuple, rc = 0; 1148 1149 if (cmd->data == RXH_4TUPLE) 1150 tuple = 4; 1151 else if (cmd->data == RXH_2TUPLE) 1152 tuple = 2; 1153 else if (!cmd->data) 1154 tuple = 0; 1155 else 1156 return -EINVAL; 1157 1158 if (cmd->flow_type == TCP_V4_FLOW) { 1159 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1160 if (tuple == 4) 1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1162 } else if (cmd->flow_type == UDP_V4_FLOW) { 1163 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1164 return -EINVAL; 1165 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1166 if (tuple == 4) 1167 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1168 } else if (cmd->flow_type == TCP_V6_FLOW) { 1169 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1170 if (tuple == 4) 1171 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1172 } else if (cmd->flow_type == UDP_V6_FLOW) { 1173 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1174 return -EINVAL; 1175 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1176 if (tuple == 4) 1177 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1178 } else if (tuple == 4) { 1179 return -EINVAL; 1180 } 1181 1182 switch (cmd->flow_type) { 1183 case TCP_V4_FLOW: 1184 case UDP_V4_FLOW: 1185 case SCTP_V4_FLOW: 1186 case AH_ESP_V4_FLOW: 1187 case AH_V4_FLOW: 1188 case ESP_V4_FLOW: 1189 case IPV4_FLOW: 1190 if (tuple == 2) 1191 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1192 else if (!tuple) 1193 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1194 break; 1195 1196 case TCP_V6_FLOW: 1197 case UDP_V6_FLOW: 1198 case SCTP_V6_FLOW: 1199 case AH_ESP_V6_FLOW: 1200 case AH_V6_FLOW: 1201 case ESP_V6_FLOW: 1202 case IPV6_FLOW: 1203 if (tuple == 2) 1204 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1205 else if (!tuple) 1206 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1207 break; 1208 } 1209 1210 if (bp->rss_hash_cfg == rss_hash_cfg) 1211 return 0; 1212 1213 bp->rss_hash_cfg = rss_hash_cfg; 1214 if (netif_running(bp->dev)) { 1215 bnxt_close_nic(bp, false, false); 1216 rc = bnxt_open_nic(bp, false, false); 1217 } 1218 return rc; 1219 } 1220 1221 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1222 u32 *rule_locs) 1223 { 1224 struct bnxt *bp = netdev_priv(dev); 1225 int rc = 0; 1226 1227 switch (cmd->cmd) { 1228 #ifdef CONFIG_RFS_ACCEL 1229 case ETHTOOL_GRXRINGS: 1230 cmd->data = bp->rx_nr_rings; 1231 break; 1232 1233 case ETHTOOL_GRXCLSRLCNT: 1234 cmd->rule_cnt = bp->ntp_fltr_count; 1235 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1236 break; 1237 1238 case ETHTOOL_GRXCLSRLALL: 1239 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1240 break; 1241 1242 case ETHTOOL_GRXCLSRULE: 1243 rc = bnxt_grxclsrule(bp, cmd); 1244 break; 1245 #endif 1246 1247 case ETHTOOL_GRXFH: 1248 rc = bnxt_grxfh(bp, cmd); 1249 break; 1250 1251 default: 1252 rc = -EOPNOTSUPP; 1253 break; 1254 } 1255 1256 return rc; 1257 } 1258 1259 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1260 { 1261 struct bnxt *bp = netdev_priv(dev); 1262 int rc; 1263 1264 switch (cmd->cmd) { 1265 case ETHTOOL_SRXFH: 1266 rc = bnxt_srxfh(bp, cmd); 1267 break; 1268 1269 default: 1270 rc = -EOPNOTSUPP; 1271 break; 1272 } 1273 return rc; 1274 } 1275 1276 static u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1277 { 1278 return HW_HASH_INDEX_SIZE; 1279 } 1280 1281 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1282 { 1283 return HW_HASH_KEY_SIZE; 1284 } 1285 1286 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1287 u8 *hfunc) 1288 { 1289 struct bnxt *bp = netdev_priv(dev); 1290 struct bnxt_vnic_info *vnic; 1291 int i = 0; 1292 1293 if (hfunc) 1294 *hfunc = ETH_RSS_HASH_TOP; 1295 1296 if (!bp->vnic_info) 1297 return 0; 1298 1299 vnic = &bp->vnic_info[0]; 1300 if (indir && vnic->rss_table) { 1301 for (i = 0; i < HW_HASH_INDEX_SIZE; i++) 1302 indir[i] = le16_to_cpu(vnic->rss_table[i]); 1303 } 1304 1305 if (key && vnic->rss_hash_key) 1306 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1307 1308 return 0; 1309 } 1310 1311 static void bnxt_get_drvinfo(struct net_device *dev, 1312 struct ethtool_drvinfo *info) 1313 { 1314 struct bnxt *bp = netdev_priv(dev); 1315 1316 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1317 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1318 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1319 info->n_stats = bnxt_get_num_stats(bp); 1320 info->testinfo_len = bp->num_tests; 1321 /* TODO CHIMP_FW: eeprom dump details */ 1322 info->eedump_len = 0; 1323 /* TODO CHIMP FW: reg dump details */ 1324 info->regdump_len = 0; 1325 } 1326 1327 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1328 { 1329 struct bnxt *bp = netdev_priv(dev); 1330 1331 wol->supported = 0; 1332 wol->wolopts = 0; 1333 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1334 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1335 wol->supported = WAKE_MAGIC; 1336 if (bp->wol) 1337 wol->wolopts = WAKE_MAGIC; 1338 } 1339 } 1340 1341 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1342 { 1343 struct bnxt *bp = netdev_priv(dev); 1344 1345 if (wol->wolopts & ~WAKE_MAGIC) 1346 return -EINVAL; 1347 1348 if (wol->wolopts & WAKE_MAGIC) { 1349 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1350 return -EINVAL; 1351 if (!bp->wol) { 1352 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1353 return -EBUSY; 1354 bp->wol = 1; 1355 } 1356 } else { 1357 if (bp->wol) { 1358 if (bnxt_hwrm_free_wol_fltr(bp)) 1359 return -EBUSY; 1360 bp->wol = 0; 1361 } 1362 } 1363 return 0; 1364 } 1365 1366 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1367 { 1368 u32 speed_mask = 0; 1369 1370 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1371 /* set the advertised speeds */ 1372 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1373 speed_mask |= ADVERTISED_100baseT_Full; 1374 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1375 speed_mask |= ADVERTISED_1000baseT_Full; 1376 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1377 speed_mask |= ADVERTISED_2500baseX_Full; 1378 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1379 speed_mask |= ADVERTISED_10000baseT_Full; 1380 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1381 speed_mask |= ADVERTISED_40000baseCR4_Full; 1382 1383 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1384 speed_mask |= ADVERTISED_Pause; 1385 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1386 speed_mask |= ADVERTISED_Asym_Pause; 1387 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1388 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1389 1390 return speed_mask; 1391 } 1392 1393 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1394 { \ 1395 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1396 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1397 100baseT_Full); \ 1398 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1399 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1400 1000baseT_Full); \ 1401 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1402 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1403 10000baseT_Full); \ 1404 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1405 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1406 25000baseCR_Full); \ 1407 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1408 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1409 40000baseCR4_Full);\ 1410 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1411 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1412 50000baseCR2_Full);\ 1413 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1414 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1415 100000baseCR4_Full);\ 1416 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1417 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1418 Pause); \ 1419 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1420 ethtool_link_ksettings_add_link_mode( \ 1421 lk_ksettings, name, Asym_Pause);\ 1422 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1423 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1424 Asym_Pause); \ 1425 } \ 1426 } 1427 1428 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1429 { \ 1430 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1431 100baseT_Full) || \ 1432 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1433 100baseT_Half)) \ 1434 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1435 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1436 1000baseT_Full) || \ 1437 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1438 1000baseT_Half)) \ 1439 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1440 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1441 10000baseT_Full)) \ 1442 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1443 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1444 25000baseCR_Full)) \ 1445 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1446 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1447 40000baseCR4_Full)) \ 1448 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1449 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1450 50000baseCR2_Full)) \ 1451 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1452 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1453 100000baseCR4_Full)) \ 1454 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1455 } 1456 1457 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1458 struct ethtool_link_ksettings *lk_ksettings) 1459 { 1460 u16 fw_speeds = link_info->advertising; 1461 u8 fw_pause = 0; 1462 1463 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1464 fw_pause = link_info->auto_pause_setting; 1465 1466 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1467 } 1468 1469 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1470 struct ethtool_link_ksettings *lk_ksettings) 1471 { 1472 u16 fw_speeds = link_info->lp_auto_link_speeds; 1473 u8 fw_pause = 0; 1474 1475 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1476 fw_pause = link_info->lp_pause; 1477 1478 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1479 lp_advertising); 1480 } 1481 1482 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1483 struct ethtool_link_ksettings *lk_ksettings) 1484 { 1485 u16 fw_speeds = link_info->support_speeds; 1486 1487 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1488 1489 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1490 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1491 Asym_Pause); 1492 1493 if (link_info->support_auto_speeds) 1494 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1495 Autoneg); 1496 } 1497 1498 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1499 { 1500 switch (fw_link_speed) { 1501 case BNXT_LINK_SPEED_100MB: 1502 return SPEED_100; 1503 case BNXT_LINK_SPEED_1GB: 1504 return SPEED_1000; 1505 case BNXT_LINK_SPEED_2_5GB: 1506 return SPEED_2500; 1507 case BNXT_LINK_SPEED_10GB: 1508 return SPEED_10000; 1509 case BNXT_LINK_SPEED_20GB: 1510 return SPEED_20000; 1511 case BNXT_LINK_SPEED_25GB: 1512 return SPEED_25000; 1513 case BNXT_LINK_SPEED_40GB: 1514 return SPEED_40000; 1515 case BNXT_LINK_SPEED_50GB: 1516 return SPEED_50000; 1517 case BNXT_LINK_SPEED_100GB: 1518 return SPEED_100000; 1519 default: 1520 return SPEED_UNKNOWN; 1521 } 1522 } 1523 1524 static int bnxt_get_link_ksettings(struct net_device *dev, 1525 struct ethtool_link_ksettings *lk_ksettings) 1526 { 1527 struct bnxt *bp = netdev_priv(dev); 1528 struct bnxt_link_info *link_info = &bp->link_info; 1529 struct ethtool_link_settings *base = &lk_ksettings->base; 1530 u32 ethtool_speed; 1531 1532 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1533 mutex_lock(&bp->link_lock); 1534 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1535 1536 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1537 if (link_info->autoneg) { 1538 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1539 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1540 advertising, Autoneg); 1541 base->autoneg = AUTONEG_ENABLE; 1542 base->duplex = DUPLEX_UNKNOWN; 1543 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1544 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1545 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1546 base->duplex = DUPLEX_FULL; 1547 else 1548 base->duplex = DUPLEX_HALF; 1549 } 1550 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1551 } else { 1552 base->autoneg = AUTONEG_DISABLE; 1553 ethtool_speed = 1554 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1555 base->duplex = DUPLEX_HALF; 1556 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1557 base->duplex = DUPLEX_FULL; 1558 } 1559 base->speed = ethtool_speed; 1560 1561 base->port = PORT_NONE; 1562 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1563 base->port = PORT_TP; 1564 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1565 TP); 1566 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1567 TP); 1568 } else { 1569 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1570 FIBRE); 1571 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1572 FIBRE); 1573 1574 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1575 base->port = PORT_DA; 1576 else if (link_info->media_type == 1577 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1578 base->port = PORT_FIBRE; 1579 } 1580 base->phy_address = link_info->phy_addr; 1581 mutex_unlock(&bp->link_lock); 1582 1583 return 0; 1584 } 1585 1586 static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed) 1587 { 1588 struct bnxt *bp = netdev_priv(dev); 1589 struct bnxt_link_info *link_info = &bp->link_info; 1590 u16 support_spds = link_info->support_speeds; 1591 u32 fw_speed = 0; 1592 1593 switch (ethtool_speed) { 1594 case SPEED_100: 1595 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1596 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB; 1597 break; 1598 case SPEED_1000: 1599 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1600 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB; 1601 break; 1602 case SPEED_2500: 1603 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1604 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB; 1605 break; 1606 case SPEED_10000: 1607 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1608 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB; 1609 break; 1610 case SPEED_20000: 1611 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1612 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB; 1613 break; 1614 case SPEED_25000: 1615 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1616 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB; 1617 break; 1618 case SPEED_40000: 1619 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1620 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB; 1621 break; 1622 case SPEED_50000: 1623 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) 1624 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB; 1625 break; 1626 case SPEED_100000: 1627 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) 1628 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB; 1629 break; 1630 default: 1631 netdev_err(dev, "unsupported speed!\n"); 1632 break; 1633 } 1634 return fw_speed; 1635 } 1636 1637 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1638 { 1639 u16 fw_speed_mask = 0; 1640 1641 /* only support autoneg at speed 100, 1000, and 10000 */ 1642 if (advertising & (ADVERTISED_100baseT_Full | 1643 ADVERTISED_100baseT_Half)) { 1644 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1645 } 1646 if (advertising & (ADVERTISED_1000baseT_Full | 1647 ADVERTISED_1000baseT_Half)) { 1648 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1649 } 1650 if (advertising & ADVERTISED_10000baseT_Full) 1651 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1652 1653 if (advertising & ADVERTISED_40000baseCR4_Full) 1654 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1655 1656 return fw_speed_mask; 1657 } 1658 1659 static int bnxt_set_link_ksettings(struct net_device *dev, 1660 const struct ethtool_link_ksettings *lk_ksettings) 1661 { 1662 struct bnxt *bp = netdev_priv(dev); 1663 struct bnxt_link_info *link_info = &bp->link_info; 1664 const struct ethtool_link_settings *base = &lk_ksettings->base; 1665 bool set_pause = false; 1666 u16 fw_advertising = 0; 1667 u32 speed; 1668 int rc = 0; 1669 1670 if (!BNXT_PHY_CFG_ABLE(bp)) 1671 return -EOPNOTSUPP; 1672 1673 mutex_lock(&bp->link_lock); 1674 if (base->autoneg == AUTONEG_ENABLE) { 1675 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings, 1676 advertising); 1677 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1678 if (!fw_advertising) 1679 link_info->advertising = link_info->support_auto_speeds; 1680 else 1681 link_info->advertising = fw_advertising; 1682 /* any change to autoneg will cause link change, therefore the 1683 * driver should put back the original pause setting in autoneg 1684 */ 1685 set_pause = true; 1686 } else { 1687 u16 fw_speed; 1688 u8 phy_type = link_info->phy_type; 1689 1690 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1691 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1692 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1693 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1694 rc = -EINVAL; 1695 goto set_setting_exit; 1696 } 1697 if (base->duplex == DUPLEX_HALF) { 1698 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1699 rc = -EINVAL; 1700 goto set_setting_exit; 1701 } 1702 speed = base->speed; 1703 fw_speed = bnxt_get_fw_speed(dev, speed); 1704 if (!fw_speed) { 1705 rc = -EINVAL; 1706 goto set_setting_exit; 1707 } 1708 link_info->req_link_speed = fw_speed; 1709 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1710 link_info->autoneg = 0; 1711 link_info->advertising = 0; 1712 } 1713 1714 if (netif_running(dev)) 1715 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1716 1717 set_setting_exit: 1718 mutex_unlock(&bp->link_lock); 1719 return rc; 1720 } 1721 1722 static void bnxt_get_pauseparam(struct net_device *dev, 1723 struct ethtool_pauseparam *epause) 1724 { 1725 struct bnxt *bp = netdev_priv(dev); 1726 struct bnxt_link_info *link_info = &bp->link_info; 1727 1728 if (BNXT_VF(bp)) 1729 return; 1730 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 1731 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 1732 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 1733 } 1734 1735 static int bnxt_set_pauseparam(struct net_device *dev, 1736 struct ethtool_pauseparam *epause) 1737 { 1738 int rc = 0; 1739 struct bnxt *bp = netdev_priv(dev); 1740 struct bnxt_link_info *link_info = &bp->link_info; 1741 1742 if (!BNXT_PHY_CFG_ABLE(bp)) 1743 return -EOPNOTSUPP; 1744 1745 if (epause->autoneg) { 1746 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 1747 return -EINVAL; 1748 1749 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 1750 if (bp->hwrm_spec_code >= 0x10201) 1751 link_info->req_flow_ctrl = 1752 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 1753 } else { 1754 /* when transition from auto pause to force pause, 1755 * force a link change 1756 */ 1757 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1758 link_info->force_link_chng = true; 1759 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 1760 link_info->req_flow_ctrl = 0; 1761 } 1762 if (epause->rx_pause) 1763 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 1764 1765 if (epause->tx_pause) 1766 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 1767 1768 if (netif_running(dev)) { 1769 mutex_lock(&bp->link_lock); 1770 rc = bnxt_hwrm_set_pause(bp); 1771 mutex_unlock(&bp->link_lock); 1772 } 1773 return rc; 1774 } 1775 1776 static u32 bnxt_get_link(struct net_device *dev) 1777 { 1778 struct bnxt *bp = netdev_priv(dev); 1779 1780 /* TODO: handle MF, VF, driver close case */ 1781 return bp->link_info.link_up; 1782 } 1783 1784 static void bnxt_print_admin_err(struct bnxt *bp) 1785 { 1786 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 1787 } 1788 1789 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 1790 u16 ext, u16 *index, u32 *item_length, 1791 u32 *data_length); 1792 1793 static int bnxt_flash_nvram(struct net_device *dev, 1794 u16 dir_type, 1795 u16 dir_ordinal, 1796 u16 dir_ext, 1797 u16 dir_attr, 1798 const u8 *data, 1799 size_t data_len) 1800 { 1801 struct bnxt *bp = netdev_priv(dev); 1802 int rc; 1803 struct hwrm_nvm_write_input req = {0}; 1804 dma_addr_t dma_handle; 1805 u8 *kmem; 1806 1807 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 1808 1809 req.dir_type = cpu_to_le16(dir_type); 1810 req.dir_ordinal = cpu_to_le16(dir_ordinal); 1811 req.dir_ext = cpu_to_le16(dir_ext); 1812 req.dir_attr = cpu_to_le16(dir_attr); 1813 req.dir_data_length = cpu_to_le32(data_len); 1814 1815 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 1816 GFP_KERNEL); 1817 if (!kmem) { 1818 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 1819 (unsigned)data_len); 1820 return -ENOMEM; 1821 } 1822 memcpy(kmem, data, data_len); 1823 req.host_src_addr = cpu_to_le64(dma_handle); 1824 1825 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 1826 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 1827 1828 if (rc == -EACCES) 1829 bnxt_print_admin_err(bp); 1830 return rc; 1831 } 1832 1833 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 1834 u8 self_reset, u8 flags) 1835 { 1836 struct hwrm_fw_reset_input req = {0}; 1837 struct bnxt *bp = netdev_priv(dev); 1838 int rc; 1839 1840 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 1841 1842 req.embedded_proc_type = proc_type; 1843 req.selfrst_status = self_reset; 1844 req.flags = flags; 1845 1846 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 1847 rc = hwrm_send_message_silent(bp, &req, sizeof(req), 1848 HWRM_CMD_TIMEOUT); 1849 } else { 1850 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1851 if (rc == -EACCES) 1852 bnxt_print_admin_err(bp); 1853 } 1854 return rc; 1855 } 1856 1857 static int bnxt_firmware_reset(struct net_device *dev, 1858 enum bnxt_nvm_directory_type dir_type) 1859 { 1860 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 1861 u8 proc_type, flags = 0; 1862 1863 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 1864 /* (e.g. when firmware isn't already running) */ 1865 switch (dir_type) { 1866 case BNX_DIR_TYPE_CHIMP_PATCH: 1867 case BNX_DIR_TYPE_BOOTCODE: 1868 case BNX_DIR_TYPE_BOOTCODE_2: 1869 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 1870 /* Self-reset ChiMP upon next PCIe reset: */ 1871 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1872 break; 1873 case BNX_DIR_TYPE_APE_FW: 1874 case BNX_DIR_TYPE_APE_PATCH: 1875 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 1876 /* Self-reset APE upon next PCIe reset: */ 1877 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 1878 break; 1879 case BNX_DIR_TYPE_KONG_FW: 1880 case BNX_DIR_TYPE_KONG_PATCH: 1881 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 1882 break; 1883 case BNX_DIR_TYPE_BONO_FW: 1884 case BNX_DIR_TYPE_BONO_PATCH: 1885 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 1886 break; 1887 default: 1888 return -EINVAL; 1889 } 1890 1891 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 1892 } 1893 1894 static int bnxt_firmware_reset_chip(struct net_device *dev) 1895 { 1896 struct bnxt *bp = netdev_priv(dev); 1897 u8 flags = 0; 1898 1899 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 1900 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 1901 1902 return bnxt_hwrm_firmware_reset(dev, 1903 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 1904 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 1905 flags); 1906 } 1907 1908 static int bnxt_firmware_reset_ap(struct net_device *dev) 1909 { 1910 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 1911 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 1912 0); 1913 } 1914 1915 static int bnxt_flash_firmware(struct net_device *dev, 1916 u16 dir_type, 1917 const u8 *fw_data, 1918 size_t fw_size) 1919 { 1920 int rc = 0; 1921 u16 code_type; 1922 u32 stored_crc; 1923 u32 calculated_crc; 1924 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 1925 1926 switch (dir_type) { 1927 case BNX_DIR_TYPE_BOOTCODE: 1928 case BNX_DIR_TYPE_BOOTCODE_2: 1929 code_type = CODE_BOOT; 1930 break; 1931 case BNX_DIR_TYPE_CHIMP_PATCH: 1932 code_type = CODE_CHIMP_PATCH; 1933 break; 1934 case BNX_DIR_TYPE_APE_FW: 1935 code_type = CODE_MCTP_PASSTHRU; 1936 break; 1937 case BNX_DIR_TYPE_APE_PATCH: 1938 code_type = CODE_APE_PATCH; 1939 break; 1940 case BNX_DIR_TYPE_KONG_FW: 1941 code_type = CODE_KONG_FW; 1942 break; 1943 case BNX_DIR_TYPE_KONG_PATCH: 1944 code_type = CODE_KONG_PATCH; 1945 break; 1946 case BNX_DIR_TYPE_BONO_FW: 1947 code_type = CODE_BONO_FW; 1948 break; 1949 case BNX_DIR_TYPE_BONO_PATCH: 1950 code_type = CODE_BONO_PATCH; 1951 break; 1952 default: 1953 netdev_err(dev, "Unsupported directory entry type: %u\n", 1954 dir_type); 1955 return -EINVAL; 1956 } 1957 if (fw_size < sizeof(struct bnxt_fw_header)) { 1958 netdev_err(dev, "Invalid firmware file size: %u\n", 1959 (unsigned int)fw_size); 1960 return -EINVAL; 1961 } 1962 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 1963 netdev_err(dev, "Invalid firmware signature: %08X\n", 1964 le32_to_cpu(header->signature)); 1965 return -EINVAL; 1966 } 1967 if (header->code_type != code_type) { 1968 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 1969 code_type, header->code_type); 1970 return -EINVAL; 1971 } 1972 if (header->device != DEVICE_CUMULUS_FAMILY) { 1973 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 1974 DEVICE_CUMULUS_FAMILY, header->device); 1975 return -EINVAL; 1976 } 1977 /* Confirm the CRC32 checksum of the file: */ 1978 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 1979 sizeof(stored_crc))); 1980 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 1981 if (calculated_crc != stored_crc) { 1982 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 1983 (unsigned long)stored_crc, 1984 (unsigned long)calculated_crc); 1985 return -EINVAL; 1986 } 1987 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 1988 0, 0, fw_data, fw_size); 1989 if (rc == 0) /* Firmware update successful */ 1990 rc = bnxt_firmware_reset(dev, dir_type); 1991 1992 return rc; 1993 } 1994 1995 static int bnxt_flash_microcode(struct net_device *dev, 1996 u16 dir_type, 1997 const u8 *fw_data, 1998 size_t fw_size) 1999 { 2000 struct bnxt_ucode_trailer *trailer; 2001 u32 calculated_crc; 2002 u32 stored_crc; 2003 int rc = 0; 2004 2005 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2006 netdev_err(dev, "Invalid microcode file size: %u\n", 2007 (unsigned int)fw_size); 2008 return -EINVAL; 2009 } 2010 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2011 sizeof(*trailer))); 2012 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2013 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2014 le32_to_cpu(trailer->sig)); 2015 return -EINVAL; 2016 } 2017 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2018 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2019 dir_type, le16_to_cpu(trailer->dir_type)); 2020 return -EINVAL; 2021 } 2022 if (le16_to_cpu(trailer->trailer_length) < 2023 sizeof(struct bnxt_ucode_trailer)) { 2024 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2025 le16_to_cpu(trailer->trailer_length)); 2026 return -EINVAL; 2027 } 2028 2029 /* Confirm the CRC32 checksum of the file: */ 2030 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2031 sizeof(stored_crc))); 2032 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2033 if (calculated_crc != stored_crc) { 2034 netdev_err(dev, 2035 "CRC32 (%08lX) does not match calculated: %08lX\n", 2036 (unsigned long)stored_crc, 2037 (unsigned long)calculated_crc); 2038 return -EINVAL; 2039 } 2040 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2041 0, 0, fw_data, fw_size); 2042 2043 return rc; 2044 } 2045 2046 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2047 { 2048 switch (dir_type) { 2049 case BNX_DIR_TYPE_CHIMP_PATCH: 2050 case BNX_DIR_TYPE_BOOTCODE: 2051 case BNX_DIR_TYPE_BOOTCODE_2: 2052 case BNX_DIR_TYPE_APE_FW: 2053 case BNX_DIR_TYPE_APE_PATCH: 2054 case BNX_DIR_TYPE_KONG_FW: 2055 case BNX_DIR_TYPE_KONG_PATCH: 2056 case BNX_DIR_TYPE_BONO_FW: 2057 case BNX_DIR_TYPE_BONO_PATCH: 2058 return true; 2059 } 2060 2061 return false; 2062 } 2063 2064 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2065 { 2066 switch (dir_type) { 2067 case BNX_DIR_TYPE_AVS: 2068 case BNX_DIR_TYPE_EXP_ROM_MBA: 2069 case BNX_DIR_TYPE_PCIE: 2070 case BNX_DIR_TYPE_TSCF_UCODE: 2071 case BNX_DIR_TYPE_EXT_PHY: 2072 case BNX_DIR_TYPE_CCM: 2073 case BNX_DIR_TYPE_ISCSI_BOOT: 2074 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2075 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2076 return true; 2077 } 2078 2079 return false; 2080 } 2081 2082 static bool bnxt_dir_type_is_executable(u16 dir_type) 2083 { 2084 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2085 bnxt_dir_type_is_other_exec_format(dir_type); 2086 } 2087 2088 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2089 u16 dir_type, 2090 const char *filename) 2091 { 2092 const struct firmware *fw; 2093 int rc; 2094 2095 rc = request_firmware(&fw, filename, &dev->dev); 2096 if (rc != 0) { 2097 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2098 rc, filename); 2099 return rc; 2100 } 2101 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2102 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2103 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2104 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2105 else 2106 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2107 0, 0, fw->data, fw->size); 2108 release_firmware(fw); 2109 return rc; 2110 } 2111 2112 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2113 u32 install_type) 2114 { 2115 struct bnxt *bp = netdev_priv(dev); 2116 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2117 struct hwrm_nvm_install_update_input install = {0}; 2118 const struct firmware *fw; 2119 u32 item_len; 2120 int rc = 0; 2121 u16 index; 2122 2123 bnxt_hwrm_fw_set_time(bp); 2124 2125 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2126 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2127 &index, &item_len, NULL); 2128 if (rc) { 2129 netdev_err(dev, "PKG update area not created in nvram\n"); 2130 return rc; 2131 } 2132 2133 rc = request_firmware(&fw, filename, &dev->dev); 2134 if (rc != 0) { 2135 netdev_err(dev, "PKG error %d requesting file: %s\n", 2136 rc, filename); 2137 return rc; 2138 } 2139 2140 if (fw->size > item_len) { 2141 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2142 (unsigned long)fw->size); 2143 rc = -EFBIG; 2144 } else { 2145 dma_addr_t dma_handle; 2146 u8 *kmem; 2147 struct hwrm_nvm_modify_input modify = {0}; 2148 2149 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2150 2151 modify.dir_idx = cpu_to_le16(index); 2152 modify.len = cpu_to_le32(fw->size); 2153 2154 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2155 &dma_handle, GFP_KERNEL); 2156 if (!kmem) { 2157 netdev_err(dev, 2158 "dma_alloc_coherent failure, length = %u\n", 2159 (unsigned int)fw->size); 2160 rc = -ENOMEM; 2161 } else { 2162 memcpy(kmem, fw->data, fw->size); 2163 modify.host_src_addr = cpu_to_le64(dma_handle); 2164 2165 rc = hwrm_send_message(bp, &modify, sizeof(modify), 2166 FLASH_PACKAGE_TIMEOUT); 2167 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2168 dma_handle); 2169 } 2170 } 2171 release_firmware(fw); 2172 if (rc) 2173 goto err_exit; 2174 2175 if ((install_type & 0xffff) == 0) 2176 install_type >>= 16; 2177 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2178 install.install_type = cpu_to_le32(install_type); 2179 2180 mutex_lock(&bp->hwrm_cmd_lock); 2181 rc = _hwrm_send_message(bp, &install, sizeof(install), 2182 INSTALL_PACKAGE_TIMEOUT); 2183 if (rc) { 2184 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2185 2186 if (resp->error_code && error_code == 2187 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2188 install.flags |= cpu_to_le16( 2189 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2190 rc = _hwrm_send_message(bp, &install, sizeof(install), 2191 INSTALL_PACKAGE_TIMEOUT); 2192 } 2193 if (rc) 2194 goto flash_pkg_exit; 2195 } 2196 2197 if (resp->result) { 2198 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2199 (s8)resp->result, (int)resp->problem_item); 2200 rc = -ENOPKG; 2201 } 2202 flash_pkg_exit: 2203 mutex_unlock(&bp->hwrm_cmd_lock); 2204 err_exit: 2205 if (rc == -EACCES) 2206 bnxt_print_admin_err(bp); 2207 return rc; 2208 } 2209 2210 static int bnxt_flash_device(struct net_device *dev, 2211 struct ethtool_flash *flash) 2212 { 2213 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2214 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2215 return -EINVAL; 2216 } 2217 2218 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2219 flash->region > 0xffff) 2220 return bnxt_flash_package_from_file(dev, flash->data, 2221 flash->region); 2222 2223 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2224 } 2225 2226 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2227 { 2228 struct bnxt *bp = netdev_priv(dev); 2229 int rc; 2230 struct hwrm_nvm_get_dir_info_input req = {0}; 2231 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2232 2233 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2234 2235 mutex_lock(&bp->hwrm_cmd_lock); 2236 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2237 if (!rc) { 2238 *entries = le32_to_cpu(output->entries); 2239 *length = le32_to_cpu(output->entry_length); 2240 } 2241 mutex_unlock(&bp->hwrm_cmd_lock); 2242 return rc; 2243 } 2244 2245 static int bnxt_get_eeprom_len(struct net_device *dev) 2246 { 2247 struct bnxt *bp = netdev_priv(dev); 2248 2249 if (BNXT_VF(bp)) 2250 return 0; 2251 2252 /* The -1 return value allows the entire 32-bit range of offsets to be 2253 * passed via the ethtool command-line utility. 2254 */ 2255 return -1; 2256 } 2257 2258 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2259 { 2260 struct bnxt *bp = netdev_priv(dev); 2261 int rc; 2262 u32 dir_entries; 2263 u32 entry_length; 2264 u8 *buf; 2265 size_t buflen; 2266 dma_addr_t dma_handle; 2267 struct hwrm_nvm_get_dir_entries_input req = {0}; 2268 2269 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2270 if (rc != 0) 2271 return rc; 2272 2273 /* Insert 2 bytes of directory info (count and size of entries) */ 2274 if (len < 2) 2275 return -EINVAL; 2276 2277 *data++ = dir_entries; 2278 *data++ = entry_length; 2279 len -= 2; 2280 memset(data, 0xff, len); 2281 2282 buflen = dir_entries * entry_length; 2283 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2284 GFP_KERNEL); 2285 if (!buf) { 2286 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2287 (unsigned)buflen); 2288 return -ENOMEM; 2289 } 2290 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2291 req.host_dest_addr = cpu_to_le64(dma_handle); 2292 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2293 if (rc == 0) 2294 memcpy(data, buf, len > buflen ? buflen : len); 2295 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2296 return rc; 2297 } 2298 2299 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2300 u32 length, u8 *data) 2301 { 2302 struct bnxt *bp = netdev_priv(dev); 2303 int rc; 2304 u8 *buf; 2305 dma_addr_t dma_handle; 2306 struct hwrm_nvm_read_input req = {0}; 2307 2308 if (!length) 2309 return -EINVAL; 2310 2311 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2312 GFP_KERNEL); 2313 if (!buf) { 2314 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2315 (unsigned)length); 2316 return -ENOMEM; 2317 } 2318 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2319 req.host_dest_addr = cpu_to_le64(dma_handle); 2320 req.dir_idx = cpu_to_le16(index); 2321 req.offset = cpu_to_le32(offset); 2322 req.len = cpu_to_le32(length); 2323 2324 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2325 if (rc == 0) 2326 memcpy(data, buf, length); 2327 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2328 return rc; 2329 } 2330 2331 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2332 u16 ext, u16 *index, u32 *item_length, 2333 u32 *data_length) 2334 { 2335 struct bnxt *bp = netdev_priv(dev); 2336 int rc; 2337 struct hwrm_nvm_find_dir_entry_input req = {0}; 2338 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2339 2340 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2341 req.enables = 0; 2342 req.dir_idx = 0; 2343 req.dir_type = cpu_to_le16(type); 2344 req.dir_ordinal = cpu_to_le16(ordinal); 2345 req.dir_ext = cpu_to_le16(ext); 2346 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2347 mutex_lock(&bp->hwrm_cmd_lock); 2348 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2349 if (rc == 0) { 2350 if (index) 2351 *index = le16_to_cpu(output->dir_idx); 2352 if (item_length) 2353 *item_length = le32_to_cpu(output->dir_item_length); 2354 if (data_length) 2355 *data_length = le32_to_cpu(output->dir_data_length); 2356 } 2357 mutex_unlock(&bp->hwrm_cmd_lock); 2358 return rc; 2359 } 2360 2361 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2362 { 2363 char *retval = NULL; 2364 char *p; 2365 char *value; 2366 int field = 0; 2367 2368 if (datalen < 1) 2369 return NULL; 2370 /* null-terminate the log data (removing last '\n'): */ 2371 data[datalen - 1] = 0; 2372 for (p = data; *p != 0; p++) { 2373 field = 0; 2374 retval = NULL; 2375 while (*p != 0 && *p != '\n') { 2376 value = p; 2377 while (*p != 0 && *p != '\t' && *p != '\n') 2378 p++; 2379 if (field == desired_field) 2380 retval = value; 2381 if (*p != '\t') 2382 break; 2383 *p = 0; 2384 field++; 2385 p++; 2386 } 2387 if (*p == 0) 2388 break; 2389 *p = 0; 2390 } 2391 return retval; 2392 } 2393 2394 static void bnxt_get_pkgver(struct net_device *dev) 2395 { 2396 struct bnxt *bp = netdev_priv(dev); 2397 u16 index = 0; 2398 char *pkgver; 2399 u32 pkglen; 2400 u8 *pkgbuf; 2401 int len; 2402 2403 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2404 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2405 &index, NULL, &pkglen) != 0) 2406 return; 2407 2408 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2409 if (!pkgbuf) { 2410 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2411 pkglen); 2412 return; 2413 } 2414 2415 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2416 goto err; 2417 2418 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2419 pkglen); 2420 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2421 len = strlen(bp->fw_ver_str); 2422 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2423 "/pkg %s", pkgver); 2424 } 2425 err: 2426 kfree(pkgbuf); 2427 } 2428 2429 static int bnxt_get_eeprom(struct net_device *dev, 2430 struct ethtool_eeprom *eeprom, 2431 u8 *data) 2432 { 2433 u32 index; 2434 u32 offset; 2435 2436 if (eeprom->offset == 0) /* special offset value to get directory */ 2437 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2438 2439 index = eeprom->offset >> 24; 2440 offset = eeprom->offset & 0xffffff; 2441 2442 if (index == 0) { 2443 netdev_err(dev, "unsupported index value: %d\n", index); 2444 return -EINVAL; 2445 } 2446 2447 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2448 } 2449 2450 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2451 { 2452 struct bnxt *bp = netdev_priv(dev); 2453 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2454 2455 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2456 req.dir_idx = cpu_to_le16(index); 2457 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2458 } 2459 2460 static int bnxt_set_eeprom(struct net_device *dev, 2461 struct ethtool_eeprom *eeprom, 2462 u8 *data) 2463 { 2464 struct bnxt *bp = netdev_priv(dev); 2465 u8 index, dir_op; 2466 u16 type, ext, ordinal, attr; 2467 2468 if (!BNXT_PF(bp)) { 2469 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2470 return -EINVAL; 2471 } 2472 2473 type = eeprom->magic >> 16; 2474 2475 if (type == 0xffff) { /* special value for directory operations */ 2476 index = eeprom->magic & 0xff; 2477 dir_op = eeprom->magic >> 8; 2478 if (index == 0) 2479 return -EINVAL; 2480 switch (dir_op) { 2481 case 0x0e: /* erase */ 2482 if (eeprom->offset != ~eeprom->magic) 2483 return -EINVAL; 2484 return bnxt_erase_nvram_directory(dev, index - 1); 2485 default: 2486 return -EINVAL; 2487 } 2488 } 2489 2490 /* Create or re-write an NVM item: */ 2491 if (bnxt_dir_type_is_executable(type)) 2492 return -EOPNOTSUPP; 2493 ext = eeprom->magic & 0xffff; 2494 ordinal = eeprom->offset >> 16; 2495 attr = eeprom->offset & 0xffff; 2496 2497 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2498 eeprom->len); 2499 } 2500 2501 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2502 { 2503 struct bnxt *bp = netdev_priv(dev); 2504 struct ethtool_eee *eee = &bp->eee; 2505 struct bnxt_link_info *link_info = &bp->link_info; 2506 u32 advertising = 2507 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2508 int rc = 0; 2509 2510 if (!BNXT_PHY_CFG_ABLE(bp)) 2511 return -EOPNOTSUPP; 2512 2513 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2514 return -EOPNOTSUPP; 2515 2516 if (!edata->eee_enabled) 2517 goto eee_ok; 2518 2519 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2520 netdev_warn(dev, "EEE requires autoneg\n"); 2521 return -EINVAL; 2522 } 2523 if (edata->tx_lpi_enabled) { 2524 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2525 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2526 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2527 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2528 return -EINVAL; 2529 } else if (!bp->lpi_tmr_hi) { 2530 edata->tx_lpi_timer = eee->tx_lpi_timer; 2531 } 2532 } 2533 if (!edata->advertised) { 2534 edata->advertised = advertising & eee->supported; 2535 } else if (edata->advertised & ~advertising) { 2536 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2537 edata->advertised, advertising); 2538 return -EINVAL; 2539 } 2540 2541 eee->advertised = edata->advertised; 2542 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2543 eee->tx_lpi_timer = edata->tx_lpi_timer; 2544 eee_ok: 2545 eee->eee_enabled = edata->eee_enabled; 2546 2547 if (netif_running(dev)) 2548 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2549 2550 return rc; 2551 } 2552 2553 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2554 { 2555 struct bnxt *bp = netdev_priv(dev); 2556 2557 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2558 return -EOPNOTSUPP; 2559 2560 *edata = bp->eee; 2561 if (!bp->eee.eee_enabled) { 2562 /* Preserve tx_lpi_timer so that the last value will be used 2563 * by default when it is re-enabled. 2564 */ 2565 edata->advertised = 0; 2566 edata->tx_lpi_enabled = 0; 2567 } 2568 2569 if (!bp->eee.eee_active) 2570 edata->lp_advertised = 0; 2571 2572 return 0; 2573 } 2574 2575 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2576 u16 page_number, u16 start_addr, 2577 u16 data_length, u8 *buf) 2578 { 2579 struct hwrm_port_phy_i2c_read_input req = {0}; 2580 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2581 int rc, byte_offset = 0; 2582 2583 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2584 req.i2c_slave_addr = i2c_addr; 2585 req.page_number = cpu_to_le16(page_number); 2586 req.port_id = cpu_to_le16(bp->pf.port_id); 2587 do { 2588 u16 xfer_size; 2589 2590 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2591 data_length -= xfer_size; 2592 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2593 req.data_length = xfer_size; 2594 req.enables = cpu_to_le32(start_addr + byte_offset ? 2595 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2596 mutex_lock(&bp->hwrm_cmd_lock); 2597 rc = _hwrm_send_message(bp, &req, sizeof(req), 2598 HWRM_CMD_TIMEOUT); 2599 if (!rc) 2600 memcpy(buf + byte_offset, output->data, xfer_size); 2601 mutex_unlock(&bp->hwrm_cmd_lock); 2602 byte_offset += xfer_size; 2603 } while (!rc && data_length > 0); 2604 2605 return rc; 2606 } 2607 2608 static int bnxt_get_module_info(struct net_device *dev, 2609 struct ethtool_modinfo *modinfo) 2610 { 2611 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2612 struct bnxt *bp = netdev_priv(dev); 2613 int rc; 2614 2615 /* No point in going further if phy status indicates 2616 * module is not inserted or if it is powered down or 2617 * if it is of type 10GBase-T 2618 */ 2619 if (bp->link_info.module_status > 2620 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2621 return -EOPNOTSUPP; 2622 2623 /* This feature is not supported in older firmware versions */ 2624 if (bp->hwrm_spec_code < 0x10202) 2625 return -EOPNOTSUPP; 2626 2627 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2628 SFF_DIAG_SUPPORT_OFFSET + 1, 2629 data); 2630 if (!rc) { 2631 u8 module_id = data[0]; 2632 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2633 2634 switch (module_id) { 2635 case SFF_MODULE_ID_SFP: 2636 modinfo->type = ETH_MODULE_SFF_8472; 2637 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2638 if (!diag_supported) 2639 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2640 break; 2641 case SFF_MODULE_ID_QSFP: 2642 case SFF_MODULE_ID_QSFP_PLUS: 2643 modinfo->type = ETH_MODULE_SFF_8436; 2644 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2645 break; 2646 case SFF_MODULE_ID_QSFP28: 2647 modinfo->type = ETH_MODULE_SFF_8636; 2648 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2649 break; 2650 default: 2651 rc = -EOPNOTSUPP; 2652 break; 2653 } 2654 } 2655 return rc; 2656 } 2657 2658 static int bnxt_get_module_eeprom(struct net_device *dev, 2659 struct ethtool_eeprom *eeprom, 2660 u8 *data) 2661 { 2662 struct bnxt *bp = netdev_priv(dev); 2663 u16 start = eeprom->offset, length = eeprom->len; 2664 int rc = 0; 2665 2666 memset(data, 0, eeprom->len); 2667 2668 /* Read A0 portion of the EEPROM */ 2669 if (start < ETH_MODULE_SFF_8436_LEN) { 2670 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 2671 length = ETH_MODULE_SFF_8436_LEN - start; 2672 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 2673 start, length, data); 2674 if (rc) 2675 return rc; 2676 start += length; 2677 data += length; 2678 length = eeprom->len - length; 2679 } 2680 2681 /* Read A2 portion of the EEPROM */ 2682 if (length) { 2683 start -= ETH_MODULE_SFF_8436_LEN; 2684 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, 2685 start, length, data); 2686 } 2687 return rc; 2688 } 2689 2690 static int bnxt_nway_reset(struct net_device *dev) 2691 { 2692 int rc = 0; 2693 2694 struct bnxt *bp = netdev_priv(dev); 2695 struct bnxt_link_info *link_info = &bp->link_info; 2696 2697 if (!BNXT_PHY_CFG_ABLE(bp)) 2698 return -EOPNOTSUPP; 2699 2700 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 2701 return -EINVAL; 2702 2703 if (netif_running(dev)) 2704 rc = bnxt_hwrm_set_link_setting(bp, true, false); 2705 2706 return rc; 2707 } 2708 2709 static int bnxt_set_phys_id(struct net_device *dev, 2710 enum ethtool_phys_id_state state) 2711 { 2712 struct hwrm_port_led_cfg_input req = {0}; 2713 struct bnxt *bp = netdev_priv(dev); 2714 struct bnxt_pf_info *pf = &bp->pf; 2715 struct bnxt_led_cfg *led_cfg; 2716 u8 led_state; 2717 __le16 duration; 2718 int i; 2719 2720 if (!bp->num_leds || BNXT_VF(bp)) 2721 return -EOPNOTSUPP; 2722 2723 if (state == ETHTOOL_ID_ACTIVE) { 2724 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 2725 duration = cpu_to_le16(500); 2726 } else if (state == ETHTOOL_ID_INACTIVE) { 2727 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 2728 duration = cpu_to_le16(0); 2729 } else { 2730 return -EINVAL; 2731 } 2732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 2733 req.port_id = cpu_to_le16(pf->port_id); 2734 req.num_leds = bp->num_leds; 2735 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 2736 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 2737 req.enables |= BNXT_LED_DFLT_ENABLES(i); 2738 led_cfg->led_id = bp->leds[i].led_id; 2739 led_cfg->led_state = led_state; 2740 led_cfg->led_blink_on = duration; 2741 led_cfg->led_blink_off = duration; 2742 led_cfg->led_group_id = bp->leds[i].led_group_id; 2743 } 2744 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2745 } 2746 2747 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 2748 { 2749 struct hwrm_selftest_irq_input req = {0}; 2750 2751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 2752 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2753 } 2754 2755 static int bnxt_test_irq(struct bnxt *bp) 2756 { 2757 int i; 2758 2759 for (i = 0; i < bp->cp_nr_rings; i++) { 2760 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 2761 int rc; 2762 2763 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 2764 if (rc) 2765 return rc; 2766 } 2767 return 0; 2768 } 2769 2770 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 2771 { 2772 struct hwrm_port_mac_cfg_input req = {0}; 2773 2774 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 2775 2776 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 2777 if (enable) 2778 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 2779 else 2780 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 2781 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2782 } 2783 2784 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 2785 { 2786 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 2787 struct hwrm_port_phy_qcaps_input req = {0}; 2788 int rc; 2789 2790 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 2791 mutex_lock(&bp->hwrm_cmd_lock); 2792 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2793 if (!rc) 2794 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 2795 2796 mutex_unlock(&bp->hwrm_cmd_lock); 2797 return rc; 2798 } 2799 2800 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 2801 struct hwrm_port_phy_cfg_input *req) 2802 { 2803 struct bnxt_link_info *link_info = &bp->link_info; 2804 u16 fw_advertising; 2805 u16 fw_speed; 2806 int rc; 2807 2808 if (!link_info->autoneg || 2809 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK)) 2810 return 0; 2811 2812 rc = bnxt_query_force_speeds(bp, &fw_advertising); 2813 if (rc) 2814 return rc; 2815 2816 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2817 if (bp->link_info.link_up) 2818 fw_speed = bp->link_info.link_speed; 2819 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 2820 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2821 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 2822 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2823 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 2824 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2825 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 2826 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2827 2828 req->force_link_speed = cpu_to_le16(fw_speed); 2829 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 2830 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2831 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 2832 req->flags = 0; 2833 req->force_link_speed = cpu_to_le16(0); 2834 return rc; 2835 } 2836 2837 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 2838 { 2839 struct hwrm_port_phy_cfg_input req = {0}; 2840 2841 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 2842 2843 if (enable) { 2844 bnxt_disable_an_for_lpbk(bp, &req); 2845 if (ext) 2846 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 2847 else 2848 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 2849 } else { 2850 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 2851 } 2852 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 2853 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2854 } 2855 2856 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2857 u32 raw_cons, int pkt_size) 2858 { 2859 struct bnxt_napi *bnapi = cpr->bnapi; 2860 struct bnxt_rx_ring_info *rxr; 2861 struct bnxt_sw_rx_bd *rx_buf; 2862 struct rx_cmp *rxcmp; 2863 u16 cp_cons, cons; 2864 u8 *data; 2865 u32 len; 2866 int i; 2867 2868 rxr = bnapi->rx_ring; 2869 cp_cons = RING_CMP(raw_cons); 2870 rxcmp = (struct rx_cmp *) 2871 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 2872 cons = rxcmp->rx_cmp_opaque; 2873 rx_buf = &rxr->rx_buf_ring[cons]; 2874 data = rx_buf->data_ptr; 2875 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 2876 if (len != pkt_size) 2877 return -EIO; 2878 i = ETH_ALEN; 2879 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 2880 return -EIO; 2881 i += ETH_ALEN; 2882 for ( ; i < pkt_size; i++) { 2883 if (data[i] != (u8)(i & 0xff)) 2884 return -EIO; 2885 } 2886 return 0; 2887 } 2888 2889 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 2890 int pkt_size) 2891 { 2892 struct tx_cmp *txcmp; 2893 int rc = -EIO; 2894 u32 raw_cons; 2895 u32 cons; 2896 int i; 2897 2898 raw_cons = cpr->cp_raw_cons; 2899 for (i = 0; i < 200; i++) { 2900 cons = RING_CMP(raw_cons); 2901 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 2902 2903 if (!TX_CMP_VALID(txcmp, raw_cons)) { 2904 udelay(5); 2905 continue; 2906 } 2907 2908 /* The valid test of the entry must be done first before 2909 * reading any further. 2910 */ 2911 dma_rmb(); 2912 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 2913 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 2914 raw_cons = NEXT_RAW_CMP(raw_cons); 2915 raw_cons = NEXT_RAW_CMP(raw_cons); 2916 break; 2917 } 2918 raw_cons = NEXT_RAW_CMP(raw_cons); 2919 } 2920 cpr->cp_raw_cons = raw_cons; 2921 return rc; 2922 } 2923 2924 static int bnxt_run_loopback(struct bnxt *bp) 2925 { 2926 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 2927 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 2928 struct bnxt_cp_ring_info *cpr; 2929 int pkt_size, i = 0; 2930 struct sk_buff *skb; 2931 dma_addr_t map; 2932 u8 *data; 2933 int rc; 2934 2935 cpr = &rxr->bnapi->cp_ring; 2936 if (bp->flags & BNXT_FLAG_CHIP_P5) 2937 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 2938 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 2939 skb = netdev_alloc_skb(bp->dev, pkt_size); 2940 if (!skb) 2941 return -ENOMEM; 2942 data = skb_put(skb, pkt_size); 2943 eth_broadcast_addr(data); 2944 i += ETH_ALEN; 2945 ether_addr_copy(&data[i], bp->dev->dev_addr); 2946 i += ETH_ALEN; 2947 for ( ; i < pkt_size; i++) 2948 data[i] = (u8)(i & 0xff); 2949 2950 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 2951 PCI_DMA_TODEVICE); 2952 if (dma_mapping_error(&bp->pdev->dev, map)) { 2953 dev_kfree_skb(skb); 2954 return -EIO; 2955 } 2956 bnxt_xmit_bd(bp, txr, map, pkt_size); 2957 2958 /* Sync BD data before updating doorbell */ 2959 wmb(); 2960 2961 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 2962 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 2963 2964 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 2965 dev_kfree_skb(skb); 2966 return rc; 2967 } 2968 2969 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 2970 { 2971 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 2972 struct hwrm_selftest_exec_input req = {0}; 2973 int rc; 2974 2975 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 2976 mutex_lock(&bp->hwrm_cmd_lock); 2977 resp->test_success = 0; 2978 req.flags = test_mask; 2979 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 2980 *test_results = resp->test_success; 2981 mutex_unlock(&bp->hwrm_cmd_lock); 2982 return rc; 2983 } 2984 2985 #define BNXT_DRV_TESTS 4 2986 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 2987 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 2988 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 2989 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 2990 2991 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 2992 u64 *buf) 2993 { 2994 struct bnxt *bp = netdev_priv(dev); 2995 bool do_ext_lpbk = false; 2996 bool offline = false; 2997 u8 test_results = 0; 2998 u8 test_mask = 0; 2999 int rc = 0, i; 3000 3001 if (!bp->num_tests || !BNXT_SINGLE_PF(bp)) 3002 return; 3003 memset(buf, 0, sizeof(u64) * bp->num_tests); 3004 if (!netif_running(dev)) { 3005 etest->flags |= ETH_TEST_FL_FAILED; 3006 return; 3007 } 3008 3009 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3010 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 3011 do_ext_lpbk = true; 3012 3013 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3014 if (bp->pf.active_vfs) { 3015 etest->flags |= ETH_TEST_FL_FAILED; 3016 netdev_warn(dev, "Offline tests cannot be run with active VFs\n"); 3017 return; 3018 } 3019 offline = true; 3020 } 3021 3022 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3023 u8 bit_val = 1 << i; 3024 3025 if (!(bp->test_info->offline_mask & bit_val)) 3026 test_mask |= bit_val; 3027 else if (offline) 3028 test_mask |= bit_val; 3029 } 3030 if (!offline) { 3031 bnxt_run_fw_tests(bp, test_mask, &test_results); 3032 } else { 3033 rc = bnxt_close_nic(bp, false, false); 3034 if (rc) 3035 return; 3036 bnxt_run_fw_tests(bp, test_mask, &test_results); 3037 3038 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3039 bnxt_hwrm_mac_loopback(bp, true); 3040 msleep(250); 3041 rc = bnxt_half_open_nic(bp); 3042 if (rc) { 3043 bnxt_hwrm_mac_loopback(bp, false); 3044 etest->flags |= ETH_TEST_FL_FAILED; 3045 return; 3046 } 3047 if (bnxt_run_loopback(bp)) 3048 etest->flags |= ETH_TEST_FL_FAILED; 3049 else 3050 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3051 3052 bnxt_hwrm_mac_loopback(bp, false); 3053 bnxt_hwrm_phy_loopback(bp, true, false); 3054 msleep(1000); 3055 if (bnxt_run_loopback(bp)) { 3056 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3057 etest->flags |= ETH_TEST_FL_FAILED; 3058 } 3059 if (do_ext_lpbk) { 3060 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3061 bnxt_hwrm_phy_loopback(bp, true, true); 3062 msleep(1000); 3063 if (bnxt_run_loopback(bp)) { 3064 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3065 etest->flags |= ETH_TEST_FL_FAILED; 3066 } 3067 } 3068 bnxt_hwrm_phy_loopback(bp, false, false); 3069 bnxt_half_close_nic(bp); 3070 rc = bnxt_open_nic(bp, false, true); 3071 } 3072 if (rc || bnxt_test_irq(bp)) { 3073 buf[BNXT_IRQ_TEST_IDX] = 1; 3074 etest->flags |= ETH_TEST_FL_FAILED; 3075 } 3076 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3077 u8 bit_val = 1 << i; 3078 3079 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3080 buf[i] = 1; 3081 etest->flags |= ETH_TEST_FL_FAILED; 3082 } 3083 } 3084 } 3085 3086 static int bnxt_reset(struct net_device *dev, u32 *flags) 3087 { 3088 struct bnxt *bp = netdev_priv(dev); 3089 bool reload = false; 3090 u32 req = *flags; 3091 3092 if (!req) 3093 return -EINVAL; 3094 3095 if (!BNXT_PF(bp)) { 3096 netdev_err(dev, "Reset is not supported from a VF\n"); 3097 return -EOPNOTSUPP; 3098 } 3099 3100 if (pci_vfs_assigned(bp->pdev) && 3101 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3102 netdev_err(dev, 3103 "Reset not allowed when VFs are assigned to VMs\n"); 3104 return -EBUSY; 3105 } 3106 3107 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3108 /* This feature is not supported in older firmware versions */ 3109 if (bp->hwrm_spec_code >= 0x10803) { 3110 if (!bnxt_firmware_reset_chip(dev)) { 3111 netdev_info(dev, "Firmware reset request successful.\n"); 3112 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3113 reload = true; 3114 *flags &= ~BNXT_FW_RESET_CHIP; 3115 } 3116 } else if (req == BNXT_FW_RESET_CHIP) { 3117 return -EOPNOTSUPP; /* only request, fail hard */ 3118 } 3119 } 3120 3121 if (req & BNXT_FW_RESET_AP) { 3122 /* This feature is not supported in older firmware versions */ 3123 if (bp->hwrm_spec_code >= 0x10803) { 3124 if (!bnxt_firmware_reset_ap(dev)) { 3125 netdev_info(dev, "Reset application processor successful.\n"); 3126 reload = true; 3127 *flags &= ~BNXT_FW_RESET_AP; 3128 } 3129 } else if (req == BNXT_FW_RESET_AP) { 3130 return -EOPNOTSUPP; /* only request, fail hard */ 3131 } 3132 } 3133 3134 if (reload) 3135 netdev_info(dev, "Reload driver to complete reset\n"); 3136 3137 return 0; 3138 } 3139 3140 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3141 struct bnxt_hwrm_dbg_dma_info *info) 3142 { 3143 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3144 struct hwrm_dbg_cmn_input *cmn_req = msg; 3145 __le16 *seq_ptr = msg + info->seq_off; 3146 u16 seq = 0, len, segs_off; 3147 void *resp = cmn_resp; 3148 dma_addr_t dma_handle; 3149 int rc, off = 0; 3150 void *dma_buf; 3151 3152 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3153 GFP_KERNEL); 3154 if (!dma_buf) 3155 return -ENOMEM; 3156 3157 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3158 total_segments); 3159 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3160 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3161 mutex_lock(&bp->hwrm_cmd_lock); 3162 while (1) { 3163 *seq_ptr = cpu_to_le16(seq); 3164 rc = _hwrm_send_message(bp, msg, msg_len, 3165 HWRM_COREDUMP_TIMEOUT); 3166 if (rc) 3167 break; 3168 3169 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3170 if (!seq && 3171 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3172 info->segs = le16_to_cpu(*((__le16 *)(resp + 3173 segs_off))); 3174 if (!info->segs) { 3175 rc = -EIO; 3176 break; 3177 } 3178 3179 info->dest_buf_size = info->segs * 3180 sizeof(struct coredump_segment_record); 3181 info->dest_buf = kmalloc(info->dest_buf_size, 3182 GFP_KERNEL); 3183 if (!info->dest_buf) { 3184 rc = -ENOMEM; 3185 break; 3186 } 3187 } 3188 3189 if (info->dest_buf) { 3190 if ((info->seg_start + off + len) <= 3191 BNXT_COREDUMP_BUF_LEN(info->buf_len)) { 3192 memcpy(info->dest_buf + off, dma_buf, len); 3193 } else { 3194 rc = -ENOBUFS; 3195 break; 3196 } 3197 } 3198 3199 if (cmn_req->req_type == 3200 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3201 info->dest_buf_size += len; 3202 3203 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3204 break; 3205 3206 seq++; 3207 off += len; 3208 } 3209 mutex_unlock(&bp->hwrm_cmd_lock); 3210 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3211 return rc; 3212 } 3213 3214 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3215 struct bnxt_coredump *coredump) 3216 { 3217 struct hwrm_dbg_coredump_list_input req = {0}; 3218 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3219 int rc; 3220 3221 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3222 3223 info.dma_len = COREDUMP_LIST_BUF_LEN; 3224 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3225 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3226 data_len); 3227 3228 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3229 if (!rc) { 3230 coredump->data = info.dest_buf; 3231 coredump->data_size = info.dest_buf_size; 3232 coredump->total_segs = info.segs; 3233 } 3234 return rc; 3235 } 3236 3237 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3238 u16 segment_id) 3239 { 3240 struct hwrm_dbg_coredump_initiate_input req = {0}; 3241 3242 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3243 req.component_id = cpu_to_le16(component_id); 3244 req.segment_id = cpu_to_le16(segment_id); 3245 3246 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3247 } 3248 3249 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3250 u16 segment_id, u32 *seg_len, 3251 void *buf, u32 buf_len, u32 offset) 3252 { 3253 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3254 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3255 int rc; 3256 3257 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3258 req.component_id = cpu_to_le16(component_id); 3259 req.segment_id = cpu_to_le16(segment_id); 3260 3261 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3262 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3263 seq_no); 3264 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3265 data_len); 3266 if (buf) { 3267 info.dest_buf = buf + offset; 3268 info.buf_len = buf_len; 3269 info.seg_start = offset; 3270 } 3271 3272 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3273 if (!rc) 3274 *seg_len = info.dest_buf_size; 3275 3276 return rc; 3277 } 3278 3279 static void 3280 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3281 struct bnxt_coredump_segment_hdr *seg_hdr, 3282 struct coredump_segment_record *seg_rec, u32 seg_len, 3283 int status, u32 duration, u32 instance) 3284 { 3285 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3286 memcpy(seg_hdr->signature, "sEgM", 4); 3287 if (seg_rec) { 3288 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3289 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3290 seg_hdr->low_version = seg_rec->version_low; 3291 seg_hdr->high_version = seg_rec->version_hi; 3292 } else { 3293 /* For hwrm_ver_get response Component id = 2 3294 * and Segment id = 0 3295 */ 3296 seg_hdr->component_id = cpu_to_le32(2); 3297 seg_hdr->segment_id = 0; 3298 } 3299 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3300 seg_hdr->length = cpu_to_le32(seg_len); 3301 seg_hdr->status = cpu_to_le32(status); 3302 seg_hdr->duration = cpu_to_le32(duration); 3303 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3304 seg_hdr->instance = cpu_to_le32(instance); 3305 } 3306 3307 static void 3308 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3309 time64_t start, s16 start_utc, u16 total_segs, 3310 int status) 3311 { 3312 time64_t end = ktime_get_real_seconds(); 3313 u32 os_ver_major = 0, os_ver_minor = 0; 3314 struct tm tm; 3315 3316 time64_to_tm(start, 0, &tm); 3317 memset(record, 0, sizeof(*record)); 3318 memcpy(record->signature, "cOrE", 4); 3319 record->flags = 0; 3320 record->low_version = 0; 3321 record->high_version = 1; 3322 record->asic_state = 0; 3323 strlcpy(record->system_name, utsname()->nodename, 3324 sizeof(record->system_name)); 3325 record->year = cpu_to_le16(tm.tm_year + 1900); 3326 record->month = cpu_to_le16(tm.tm_mon + 1); 3327 record->day = cpu_to_le16(tm.tm_mday); 3328 record->hour = cpu_to_le16(tm.tm_hour); 3329 record->minute = cpu_to_le16(tm.tm_min); 3330 record->second = cpu_to_le16(tm.tm_sec); 3331 record->utc_bias = cpu_to_le16(start_utc); 3332 strcpy(record->commandline, "ethtool -w"); 3333 record->total_segments = cpu_to_le32(total_segs); 3334 3335 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3336 record->os_ver_major = cpu_to_le32(os_ver_major); 3337 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3338 3339 strlcpy(record->os_name, utsname()->sysname, 32); 3340 time64_to_tm(end, 0, &tm); 3341 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3342 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3343 record->end_day = cpu_to_le16(tm.tm_mday); 3344 record->end_hour = cpu_to_le16(tm.tm_hour); 3345 record->end_minute = cpu_to_le16(tm.tm_min); 3346 record->end_second = cpu_to_le16(tm.tm_sec); 3347 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3348 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3349 bp->ver_resp.chip_rev << 8 | 3350 bp->ver_resp.chip_metal); 3351 record->asic_id2 = 0; 3352 record->coredump_status = cpu_to_le32(status); 3353 record->ioctl_low_version = 0; 3354 record->ioctl_high_version = 0; 3355 } 3356 3357 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3358 { 3359 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3360 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0; 3361 struct coredump_segment_record *seg_record = NULL; 3362 struct bnxt_coredump_segment_hdr seg_hdr; 3363 struct bnxt_coredump coredump = {NULL}; 3364 time64_t start_time; 3365 u16 start_utc; 3366 int rc = 0, i; 3367 3368 if (buf) 3369 buf_len = *dump_len; 3370 3371 start_time = ktime_get_real_seconds(); 3372 start_utc = sys_tz.tz_minuteswest * 60; 3373 seg_hdr_len = sizeof(seg_hdr); 3374 3375 /* First segment should be hwrm_ver_get response */ 3376 *dump_len = seg_hdr_len + ver_get_resp_len; 3377 if (buf) { 3378 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3379 0, 0, 0); 3380 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3381 offset += seg_hdr_len; 3382 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3383 offset += ver_get_resp_len; 3384 } 3385 3386 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3387 if (rc) { 3388 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3389 goto err; 3390 } 3391 3392 *dump_len += seg_hdr_len * coredump.total_segs; 3393 3394 seg_record = (struct coredump_segment_record *)coredump.data; 3395 seg_record_len = sizeof(*seg_record); 3396 3397 for (i = 0; i < coredump.total_segs; i++) { 3398 u16 comp_id = le16_to_cpu(seg_record->component_id); 3399 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3400 u32 duration = 0, seg_len = 0; 3401 unsigned long start, end; 3402 3403 if (buf && ((offset + seg_hdr_len) > 3404 BNXT_COREDUMP_BUF_LEN(buf_len))) { 3405 rc = -ENOBUFS; 3406 goto err; 3407 } 3408 3409 start = jiffies; 3410 3411 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3412 if (rc) { 3413 netdev_err(bp->dev, 3414 "Failed to initiate coredump for seg = %d\n", 3415 seg_record->segment_id); 3416 goto next_seg; 3417 } 3418 3419 /* Write segment data into the buffer */ 3420 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3421 &seg_len, buf, buf_len, 3422 offset + seg_hdr_len); 3423 if (rc && rc == -ENOBUFS) 3424 goto err; 3425 else if (rc) 3426 netdev_err(bp->dev, 3427 "Failed to retrieve coredump for seg = %d\n", 3428 seg_record->segment_id); 3429 3430 next_seg: 3431 end = jiffies; 3432 duration = jiffies_to_msecs(end - start); 3433 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3434 rc, duration, 0); 3435 3436 if (buf) { 3437 /* Write segment header into the buffer */ 3438 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3439 offset += seg_hdr_len + seg_len; 3440 } 3441 3442 *dump_len += seg_len; 3443 seg_record = 3444 (struct coredump_segment_record *)((u8 *)seg_record + 3445 seg_record_len); 3446 } 3447 3448 err: 3449 if (buf) 3450 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3451 start_utc, coredump.total_segs + 1, 3452 rc); 3453 kfree(coredump.data); 3454 *dump_len += sizeof(struct bnxt_coredump_record); 3455 if (rc == -ENOBUFS) 3456 netdev_err(bp->dev, "Firmware returned large coredump buffer\n"); 3457 return rc; 3458 } 3459 3460 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3461 { 3462 struct bnxt *bp = netdev_priv(dev); 3463 3464 if (dump->flag > BNXT_DUMP_CRASH) { 3465 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3466 return -EINVAL; 3467 } 3468 3469 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3470 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3471 return -EOPNOTSUPP; 3472 } 3473 3474 bp->dump_flag = dump->flag; 3475 return 0; 3476 } 3477 3478 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3479 { 3480 struct bnxt *bp = netdev_priv(dev); 3481 3482 if (bp->hwrm_spec_code < 0x10801) 3483 return -EOPNOTSUPP; 3484 3485 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3486 bp->ver_resp.hwrm_fw_min_8b << 16 | 3487 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3488 bp->ver_resp.hwrm_fw_rsvd_8b; 3489 3490 dump->flag = bp->dump_flag; 3491 if (bp->dump_flag == BNXT_DUMP_CRASH) 3492 dump->len = BNXT_CRASH_DUMP_LEN; 3493 else 3494 bnxt_get_coredump(bp, NULL, &dump->len); 3495 return 0; 3496 } 3497 3498 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3499 void *buf) 3500 { 3501 struct bnxt *bp = netdev_priv(dev); 3502 3503 if (bp->hwrm_spec_code < 0x10801) 3504 return -EOPNOTSUPP; 3505 3506 memset(buf, 0, dump->len); 3507 3508 dump->flag = bp->dump_flag; 3509 if (dump->flag == BNXT_DUMP_CRASH) { 3510 #ifdef CONFIG_TEE_BNXT_FW 3511 return tee_bnxt_copy_coredump(buf, 0, dump->len); 3512 #endif 3513 } else { 3514 return bnxt_get_coredump(bp, buf, &dump->len); 3515 } 3516 3517 return 0; 3518 } 3519 3520 void bnxt_ethtool_init(struct bnxt *bp) 3521 { 3522 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3523 struct hwrm_selftest_qlist_input req = {0}; 3524 struct bnxt_test_info *test_info; 3525 struct net_device *dev = bp->dev; 3526 int i, rc; 3527 3528 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3529 bnxt_get_pkgver(dev); 3530 3531 bp->num_tests = 0; 3532 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp)) 3533 return; 3534 3535 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3536 mutex_lock(&bp->hwrm_cmd_lock); 3537 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3538 if (rc) 3539 goto ethtool_init_exit; 3540 3541 test_info = bp->test_info; 3542 if (!test_info) 3543 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3544 if (!test_info) 3545 goto ethtool_init_exit; 3546 3547 bp->test_info = test_info; 3548 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3549 if (bp->num_tests > BNXT_MAX_TEST) 3550 bp->num_tests = BNXT_MAX_TEST; 3551 3552 test_info->offline_mask = resp->offline_tests; 3553 test_info->timeout = le16_to_cpu(resp->test_timeout); 3554 if (!test_info->timeout) 3555 test_info->timeout = HWRM_CMD_TIMEOUT; 3556 for (i = 0; i < bp->num_tests; i++) { 3557 char *str = test_info->string[i]; 3558 char *fw_str = resp->test0_name + i * 32; 3559 3560 if (i == BNXT_MACLPBK_TEST_IDX) { 3561 strcpy(str, "Mac loopback test (offline)"); 3562 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3563 strcpy(str, "Phy loopback test (offline)"); 3564 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3565 strcpy(str, "Ext loopback test (offline)"); 3566 } else if (i == BNXT_IRQ_TEST_IDX) { 3567 strcpy(str, "Interrupt_test (offline)"); 3568 } else { 3569 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3570 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3571 if (test_info->offline_mask & (1 << i)) 3572 strncat(str, " (offline)", 3573 ETH_GSTRING_LEN - strlen(str)); 3574 else 3575 strncat(str, " (online)", 3576 ETH_GSTRING_LEN - strlen(str)); 3577 } 3578 } 3579 3580 ethtool_init_exit: 3581 mutex_unlock(&bp->hwrm_cmd_lock); 3582 } 3583 3584 void bnxt_ethtool_free(struct bnxt *bp) 3585 { 3586 kfree(bp->test_info); 3587 bp->test_info = NULL; 3588 } 3589 3590 const struct ethtool_ops bnxt_ethtool_ops = { 3591 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3592 ETHTOOL_COALESCE_MAX_FRAMES | 3593 ETHTOOL_COALESCE_USECS_IRQ | 3594 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3595 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3596 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3597 .get_link_ksettings = bnxt_get_link_ksettings, 3598 .set_link_ksettings = bnxt_set_link_ksettings, 3599 .get_pauseparam = bnxt_get_pauseparam, 3600 .set_pauseparam = bnxt_set_pauseparam, 3601 .get_drvinfo = bnxt_get_drvinfo, 3602 .get_wol = bnxt_get_wol, 3603 .set_wol = bnxt_set_wol, 3604 .get_coalesce = bnxt_get_coalesce, 3605 .set_coalesce = bnxt_set_coalesce, 3606 .get_msglevel = bnxt_get_msglevel, 3607 .set_msglevel = bnxt_set_msglevel, 3608 .get_sset_count = bnxt_get_sset_count, 3609 .get_strings = bnxt_get_strings, 3610 .get_ethtool_stats = bnxt_get_ethtool_stats, 3611 .set_ringparam = bnxt_set_ringparam, 3612 .get_ringparam = bnxt_get_ringparam, 3613 .get_channels = bnxt_get_channels, 3614 .set_channels = bnxt_set_channels, 3615 .get_rxnfc = bnxt_get_rxnfc, 3616 .set_rxnfc = bnxt_set_rxnfc, 3617 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3618 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3619 .get_rxfh = bnxt_get_rxfh, 3620 .flash_device = bnxt_flash_device, 3621 .get_eeprom_len = bnxt_get_eeprom_len, 3622 .get_eeprom = bnxt_get_eeprom, 3623 .set_eeprom = bnxt_set_eeprom, 3624 .get_link = bnxt_get_link, 3625 .get_eee = bnxt_get_eee, 3626 .set_eee = bnxt_set_eee, 3627 .get_module_info = bnxt_get_module_info, 3628 .get_module_eeprom = bnxt_get_module_eeprom, 3629 .nway_reset = bnxt_nway_reset, 3630 .set_phys_id = bnxt_set_phys_id, 3631 .self_test = bnxt_self_test, 3632 .reset = bnxt_reset, 3633 .set_dump = bnxt_set_dump, 3634 .get_dump_flag = bnxt_get_dump_flag, 3635 .get_dump_data = bnxt_get_dump_data, 3636 }; 3637