1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/stringify.h> 13 #include <linux/ethtool.h> 14 #include <linux/linkmode.h> 15 #include <linux/interrupt.h> 16 #include <linux/pci.h> 17 #include <linux/etherdevice.h> 18 #include <linux/crc32.h> 19 #include <linux/firmware.h> 20 #include <linux/utsname.h> 21 #include <linux/time.h> 22 #include "bnxt_hsi.h" 23 #include "bnxt.h" 24 #include "bnxt_xdp.h" 25 #include "bnxt_ethtool.h" 26 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 27 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 28 #include "bnxt_coredump.h" 29 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 30 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 31 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 32 33 static u32 bnxt_get_msglevel(struct net_device *dev) 34 { 35 struct bnxt *bp = netdev_priv(dev); 36 37 return bp->msg_enable; 38 } 39 40 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 41 { 42 struct bnxt *bp = netdev_priv(dev); 43 44 bp->msg_enable = value; 45 } 46 47 static int bnxt_get_coalesce(struct net_device *dev, 48 struct ethtool_coalesce *coal) 49 { 50 struct bnxt *bp = netdev_priv(dev); 51 struct bnxt_coal *hw_coal; 52 u16 mult; 53 54 memset(coal, 0, sizeof(*coal)); 55 56 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 57 58 hw_coal = &bp->rx_coal; 59 mult = hw_coal->bufs_per_record; 60 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 61 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 62 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 63 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 64 65 hw_coal = &bp->tx_coal; 66 mult = hw_coal->bufs_per_record; 67 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 68 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 69 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 70 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 71 72 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 73 74 return 0; 75 } 76 77 static int bnxt_set_coalesce(struct net_device *dev, 78 struct ethtool_coalesce *coal) 79 { 80 struct bnxt *bp = netdev_priv(dev); 81 bool update_stats = false; 82 struct bnxt_coal *hw_coal; 83 int rc = 0; 84 u16 mult; 85 86 if (coal->use_adaptive_rx_coalesce) { 87 bp->flags |= BNXT_FLAG_DIM; 88 } else { 89 if (bp->flags & BNXT_FLAG_DIM) { 90 bp->flags &= ~(BNXT_FLAG_DIM); 91 goto reset_coalesce; 92 } 93 } 94 95 hw_coal = &bp->rx_coal; 96 mult = hw_coal->bufs_per_record; 97 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 98 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 99 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 100 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 101 102 hw_coal = &bp->tx_coal; 103 mult = hw_coal->bufs_per_record; 104 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 105 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 106 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 107 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 108 109 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 110 u32 stats_ticks = coal->stats_block_coalesce_usecs; 111 112 /* Allow 0, which means disable. */ 113 if (stats_ticks) 114 stats_ticks = clamp_t(u32, stats_ticks, 115 BNXT_MIN_STATS_COAL_TICKS, 116 BNXT_MAX_STATS_COAL_TICKS); 117 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 118 bp->stats_coal_ticks = stats_ticks; 119 if (bp->stats_coal_ticks) 120 bp->current_interval = 121 bp->stats_coal_ticks * HZ / 1000000; 122 else 123 bp->current_interval = BNXT_TIMER_INTERVAL; 124 update_stats = true; 125 } 126 127 reset_coalesce: 128 if (netif_running(dev)) { 129 if (update_stats) { 130 rc = bnxt_close_nic(bp, true, false); 131 if (!rc) 132 rc = bnxt_open_nic(bp, true, false); 133 } else { 134 rc = bnxt_hwrm_set_coal(bp); 135 } 136 } 137 138 return rc; 139 } 140 141 static const char * const bnxt_ring_rx_stats_str[] = { 142 "rx_ucast_packets", 143 "rx_mcast_packets", 144 "rx_bcast_packets", 145 "rx_discards", 146 "rx_errors", 147 "rx_ucast_bytes", 148 "rx_mcast_bytes", 149 "rx_bcast_bytes", 150 }; 151 152 static const char * const bnxt_ring_tx_stats_str[] = { 153 "tx_ucast_packets", 154 "tx_mcast_packets", 155 "tx_bcast_packets", 156 "tx_errors", 157 "tx_discards", 158 "tx_ucast_bytes", 159 "tx_mcast_bytes", 160 "tx_bcast_bytes", 161 }; 162 163 static const char * const bnxt_ring_tpa_stats_str[] = { 164 "tpa_packets", 165 "tpa_bytes", 166 "tpa_events", 167 "tpa_aborts", 168 }; 169 170 static const char * const bnxt_ring_tpa2_stats_str[] = { 171 "rx_tpa_eligible_pkt", 172 "rx_tpa_eligible_bytes", 173 "rx_tpa_pkt", 174 "rx_tpa_bytes", 175 "rx_tpa_errors", 176 "rx_tpa_events", 177 }; 178 179 static const char * const bnxt_rx_sw_stats_str[] = { 180 "rx_l4_csum_errors", 181 "rx_resets", 182 "rx_buf_errors", 183 }; 184 185 static const char * const bnxt_cmn_sw_stats_str[] = { 186 "missed_irqs", 187 }; 188 189 #define BNXT_RX_STATS_ENTRY(counter) \ 190 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 191 192 #define BNXT_TX_STATS_ENTRY(counter) \ 193 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 194 195 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 196 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 197 198 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 199 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 200 201 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 202 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 203 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 204 205 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 206 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 207 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 208 209 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 210 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 211 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 212 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 213 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 214 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 215 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 216 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 217 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 218 219 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 220 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 221 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 222 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 223 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 224 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 225 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 226 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 227 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 228 229 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 230 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 231 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 232 233 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 234 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 235 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 236 237 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 238 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 239 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 240 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 241 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 242 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 243 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 244 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 245 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 246 247 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 248 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 249 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 250 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 251 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 252 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 253 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 254 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 255 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 256 257 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 258 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 259 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 260 261 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 267 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 268 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 269 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 270 271 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 272 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 273 __stringify(counter##_pri##n) } 274 275 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 276 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 277 __stringify(counter##_pri##n) } 278 279 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 280 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 281 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 282 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 283 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 284 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 285 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 286 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 287 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 288 289 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 290 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 291 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 292 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 293 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 294 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 295 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 296 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 297 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 298 299 enum { 300 RX_TOTAL_DISCARDS, 301 TX_TOTAL_DISCARDS, 302 }; 303 304 static struct { 305 u64 counter; 306 char string[ETH_GSTRING_LEN]; 307 } bnxt_sw_func_stats[] = { 308 {0, "rx_total_discard_pkts"}, 309 {0, "tx_total_discard_pkts"}, 310 }; 311 312 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 313 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 314 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 315 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 316 317 static const struct { 318 long offset; 319 char string[ETH_GSTRING_LEN]; 320 } bnxt_port_stats_arr[] = { 321 BNXT_RX_STATS_ENTRY(rx_64b_frames), 322 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 323 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 324 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 325 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 326 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 327 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 328 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 329 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 330 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 331 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 332 BNXT_RX_STATS_ENTRY(rx_total_frames), 333 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 334 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 335 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 336 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 337 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 338 BNXT_RX_STATS_ENTRY(rx_pause_frames), 339 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 340 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 341 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 342 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 343 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 344 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 345 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 346 BNXT_RX_STATS_ENTRY(rx_good_frames), 347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 354 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 355 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 357 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 358 BNXT_RX_STATS_ENTRY(rx_bytes), 359 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 360 BNXT_RX_STATS_ENTRY(rx_runt_frames), 361 BNXT_RX_STATS_ENTRY(rx_stat_discard), 362 BNXT_RX_STATS_ENTRY(rx_stat_err), 363 364 BNXT_TX_STATS_ENTRY(tx_64b_frames), 365 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 366 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 367 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 368 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 369 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 370 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 371 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 372 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 373 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 374 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 375 BNXT_TX_STATS_ENTRY(tx_good_frames), 376 BNXT_TX_STATS_ENTRY(tx_total_frames), 377 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 378 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 379 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 380 BNXT_TX_STATS_ENTRY(tx_pause_frames), 381 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 382 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 383 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 384 BNXT_TX_STATS_ENTRY(tx_err), 385 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 393 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 395 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 396 BNXT_TX_STATS_ENTRY(tx_total_collisions), 397 BNXT_TX_STATS_ENTRY(tx_bytes), 398 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 399 BNXT_TX_STATS_ENTRY(tx_stat_discard), 400 BNXT_TX_STATS_ENTRY(tx_stat_error), 401 }; 402 403 static const struct { 404 long offset; 405 char string[ETH_GSTRING_LEN]; 406 } bnxt_port_stats_ext_arr[] = { 407 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 408 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 409 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 410 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 411 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 412 BNXT_RX_STATS_EXT_COS_ENTRIES, 413 BNXT_RX_STATS_EXT_PFC_ENTRIES, 414 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 415 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 416 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 417 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 418 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 419 }; 420 421 static const struct { 422 long offset; 423 char string[ETH_GSTRING_LEN]; 424 } bnxt_tx_port_stats_ext_arr[] = { 425 BNXT_TX_STATS_EXT_COS_ENTRIES, 426 BNXT_TX_STATS_EXT_PFC_ENTRIES, 427 }; 428 429 static const struct { 430 long base_off; 431 char string[ETH_GSTRING_LEN]; 432 } bnxt_rx_bytes_pri_arr[] = { 433 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 434 }; 435 436 static const struct { 437 long base_off; 438 char string[ETH_GSTRING_LEN]; 439 } bnxt_rx_pkts_pri_arr[] = { 440 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 441 }; 442 443 static const struct { 444 long base_off; 445 char string[ETH_GSTRING_LEN]; 446 } bnxt_tx_bytes_pri_arr[] = { 447 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 448 }; 449 450 static const struct { 451 long base_off; 452 char string[ETH_GSTRING_LEN]; 453 } bnxt_tx_pkts_pri_arr[] = { 454 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 455 }; 456 457 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats) 458 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 459 #define BNXT_NUM_STATS_PRI \ 460 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 461 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 462 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 463 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 464 465 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 466 { 467 if (BNXT_SUPPORTS_TPA(bp)) { 468 if (bp->max_tpa_v2) { 469 if (BNXT_CHIP_P5_THOR(bp)) 470 return BNXT_NUM_TPA_RING_STATS_P5; 471 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 472 } 473 return BNXT_NUM_TPA_RING_STATS; 474 } 475 return 0; 476 } 477 478 static int bnxt_get_num_ring_stats(struct bnxt *bp) 479 { 480 int rx, tx, cmn; 481 482 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 483 bnxt_get_num_tpa_ring_stats(bp); 484 tx = NUM_RING_TX_HW_STATS; 485 cmn = NUM_RING_CMN_SW_STATS; 486 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 487 cmn * bp->cp_nr_rings; 488 } 489 490 static int bnxt_get_num_stats(struct bnxt *bp) 491 { 492 int num_stats = bnxt_get_num_ring_stats(bp); 493 494 num_stats += BNXT_NUM_SW_FUNC_STATS; 495 496 if (bp->flags & BNXT_FLAG_PORT_STATS) 497 num_stats += BNXT_NUM_PORT_STATS; 498 499 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 500 num_stats += bp->fw_rx_stats_ext_size + 501 bp->fw_tx_stats_ext_size; 502 if (bp->pri2cos_valid) 503 num_stats += BNXT_NUM_STATS_PRI; 504 } 505 506 return num_stats; 507 } 508 509 static int bnxt_get_sset_count(struct net_device *dev, int sset) 510 { 511 struct bnxt *bp = netdev_priv(dev); 512 513 switch (sset) { 514 case ETH_SS_STATS: 515 return bnxt_get_num_stats(bp); 516 case ETH_SS_TEST: 517 if (!bp->num_tests) 518 return -EOPNOTSUPP; 519 return bp->num_tests; 520 default: 521 return -EOPNOTSUPP; 522 } 523 } 524 525 static bool is_rx_ring(struct bnxt *bp, int ring_num) 526 { 527 return ring_num < bp->rx_nr_rings; 528 } 529 530 static bool is_tx_ring(struct bnxt *bp, int ring_num) 531 { 532 int tx_base = 0; 533 534 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 535 tx_base = bp->rx_nr_rings; 536 537 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 538 return true; 539 return false; 540 } 541 542 static void bnxt_get_ethtool_stats(struct net_device *dev, 543 struct ethtool_stats *stats, u64 *buf) 544 { 545 u32 i, j = 0; 546 struct bnxt *bp = netdev_priv(dev); 547 u32 tpa_stats; 548 549 if (!bp->bnapi) { 550 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS; 551 goto skip_ring_stats; 552 } 553 554 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) 555 bnxt_sw_func_stats[i].counter = 0; 556 557 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 558 for (i = 0; i < bp->cp_nr_rings; i++) { 559 struct bnxt_napi *bnapi = bp->bnapi[i]; 560 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 561 u64 *sw_stats = cpr->stats.sw_stats; 562 u64 *sw; 563 int k; 564 565 if (is_rx_ring(bp, i)) { 566 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 567 buf[j] = sw_stats[k]; 568 } 569 if (is_tx_ring(bp, i)) { 570 k = NUM_RING_RX_HW_STATS; 571 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 572 j++, k++) 573 buf[j] = sw_stats[k]; 574 } 575 if (!tpa_stats || !is_rx_ring(bp, i)) 576 goto skip_tpa_ring_stats; 577 578 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 579 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 580 tpa_stats; j++, k++) 581 buf[j] = sw_stats[k]; 582 583 skip_tpa_ring_stats: 584 sw = (u64 *)&cpr->sw_stats.rx; 585 if (is_rx_ring(bp, i)) { 586 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 587 buf[j] = sw[k]; 588 } 589 590 sw = (u64 *)&cpr->sw_stats.cmn; 591 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 592 buf[j] = sw[k]; 593 594 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter += 595 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts); 596 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter += 597 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts); 598 } 599 600 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++) 601 buf[j] = bnxt_sw_func_stats[i].counter; 602 603 skip_ring_stats: 604 if (bp->flags & BNXT_FLAG_PORT_STATS) { 605 u64 *port_stats = bp->port_stats.sw_stats; 606 607 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 608 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 609 } 610 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 611 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 612 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 613 614 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) { 615 buf[j] = *(rx_port_stats_ext + 616 bnxt_port_stats_ext_arr[i].offset); 617 } 618 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) { 619 buf[j] = *(tx_port_stats_ext + 620 bnxt_tx_port_stats_ext_arr[i].offset); 621 } 622 if (bp->pri2cos_valid) { 623 for (i = 0; i < 8; i++, j++) { 624 long n = bnxt_rx_bytes_pri_arr[i].base_off + 625 bp->pri2cos_idx[i]; 626 627 buf[j] = *(rx_port_stats_ext + n); 628 } 629 for (i = 0; i < 8; i++, j++) { 630 long n = bnxt_rx_pkts_pri_arr[i].base_off + 631 bp->pri2cos_idx[i]; 632 633 buf[j] = *(rx_port_stats_ext + n); 634 } 635 for (i = 0; i < 8; i++, j++) { 636 long n = bnxt_tx_bytes_pri_arr[i].base_off + 637 bp->pri2cos_idx[i]; 638 639 buf[j] = *(tx_port_stats_ext + n); 640 } 641 for (i = 0; i < 8; i++, j++) { 642 long n = bnxt_tx_pkts_pri_arr[i].base_off + 643 bp->pri2cos_idx[i]; 644 645 buf[j] = *(tx_port_stats_ext + n); 646 } 647 } 648 } 649 } 650 651 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 652 { 653 struct bnxt *bp = netdev_priv(dev); 654 static const char * const *str; 655 u32 i, j, num_str; 656 657 switch (stringset) { 658 case ETH_SS_STATS: 659 for (i = 0; i < bp->cp_nr_rings; i++) { 660 if (is_rx_ring(bp, i)) { 661 num_str = NUM_RING_RX_HW_STATS; 662 for (j = 0; j < num_str; j++) { 663 sprintf(buf, "[%d]: %s", i, 664 bnxt_ring_rx_stats_str[j]); 665 buf += ETH_GSTRING_LEN; 666 } 667 } 668 if (is_tx_ring(bp, i)) { 669 num_str = NUM_RING_TX_HW_STATS; 670 for (j = 0; j < num_str; j++) { 671 sprintf(buf, "[%d]: %s", i, 672 bnxt_ring_tx_stats_str[j]); 673 buf += ETH_GSTRING_LEN; 674 } 675 } 676 num_str = bnxt_get_num_tpa_ring_stats(bp); 677 if (!num_str || !is_rx_ring(bp, i)) 678 goto skip_tpa_stats; 679 680 if (bp->max_tpa_v2) 681 str = bnxt_ring_tpa2_stats_str; 682 else 683 str = bnxt_ring_tpa_stats_str; 684 685 for (j = 0; j < num_str; j++) { 686 sprintf(buf, "[%d]: %s", i, str[j]); 687 buf += ETH_GSTRING_LEN; 688 } 689 skip_tpa_stats: 690 if (is_rx_ring(bp, i)) { 691 num_str = NUM_RING_RX_SW_STATS; 692 for (j = 0; j < num_str; j++) { 693 sprintf(buf, "[%d]: %s", i, 694 bnxt_rx_sw_stats_str[j]); 695 buf += ETH_GSTRING_LEN; 696 } 697 } 698 num_str = NUM_RING_CMN_SW_STATS; 699 for (j = 0; j < num_str; j++) { 700 sprintf(buf, "[%d]: %s", i, 701 bnxt_cmn_sw_stats_str[j]); 702 buf += ETH_GSTRING_LEN; 703 } 704 } 705 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) { 706 strcpy(buf, bnxt_sw_func_stats[i].string); 707 buf += ETH_GSTRING_LEN; 708 } 709 710 if (bp->flags & BNXT_FLAG_PORT_STATS) { 711 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 712 strcpy(buf, bnxt_port_stats_arr[i].string); 713 buf += ETH_GSTRING_LEN; 714 } 715 } 716 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 717 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) { 718 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 719 buf += ETH_GSTRING_LEN; 720 } 721 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) { 722 strcpy(buf, 723 bnxt_tx_port_stats_ext_arr[i].string); 724 buf += ETH_GSTRING_LEN; 725 } 726 if (bp->pri2cos_valid) { 727 for (i = 0; i < 8; i++) { 728 strcpy(buf, 729 bnxt_rx_bytes_pri_arr[i].string); 730 buf += ETH_GSTRING_LEN; 731 } 732 for (i = 0; i < 8; i++) { 733 strcpy(buf, 734 bnxt_rx_pkts_pri_arr[i].string); 735 buf += ETH_GSTRING_LEN; 736 } 737 for (i = 0; i < 8; i++) { 738 strcpy(buf, 739 bnxt_tx_bytes_pri_arr[i].string); 740 buf += ETH_GSTRING_LEN; 741 } 742 for (i = 0; i < 8; i++) { 743 strcpy(buf, 744 bnxt_tx_pkts_pri_arr[i].string); 745 buf += ETH_GSTRING_LEN; 746 } 747 } 748 } 749 break; 750 case ETH_SS_TEST: 751 if (bp->num_tests) 752 memcpy(buf, bp->test_info->string, 753 bp->num_tests * ETH_GSTRING_LEN); 754 break; 755 default: 756 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 757 stringset); 758 break; 759 } 760 } 761 762 static void bnxt_get_ringparam(struct net_device *dev, 763 struct ethtool_ringparam *ering) 764 { 765 struct bnxt *bp = netdev_priv(dev); 766 767 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 768 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 769 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 770 771 ering->rx_pending = bp->rx_ring_size; 772 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 773 ering->tx_pending = bp->tx_ring_size; 774 } 775 776 static int bnxt_set_ringparam(struct net_device *dev, 777 struct ethtool_ringparam *ering) 778 { 779 struct bnxt *bp = netdev_priv(dev); 780 781 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 782 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 783 (ering->tx_pending <= MAX_SKB_FRAGS)) 784 return -EINVAL; 785 786 if (netif_running(dev)) 787 bnxt_close_nic(bp, false, false); 788 789 bp->rx_ring_size = ering->rx_pending; 790 bp->tx_ring_size = ering->tx_pending; 791 bnxt_set_ring_params(bp); 792 793 if (netif_running(dev)) 794 return bnxt_open_nic(bp, false, false); 795 796 return 0; 797 } 798 799 static void bnxt_get_channels(struct net_device *dev, 800 struct ethtool_channels *channel) 801 { 802 struct bnxt *bp = netdev_priv(dev); 803 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 804 int max_rx_rings, max_tx_rings, tcs; 805 int max_tx_sch_inputs, tx_grps; 806 807 /* Get the most up-to-date max_tx_sch_inputs. */ 808 if (netif_running(dev) && BNXT_NEW_RM(bp)) 809 bnxt_hwrm_func_resc_qcaps(bp, false); 810 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 811 812 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 813 if (max_tx_sch_inputs) 814 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 815 816 tcs = netdev_get_num_tc(dev); 817 tx_grps = max(tcs, 1); 818 if (bp->tx_nr_rings_xdp) 819 tx_grps++; 820 max_tx_rings /= tx_grps; 821 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 822 823 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 824 max_rx_rings = 0; 825 max_tx_rings = 0; 826 } 827 if (max_tx_sch_inputs) 828 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 829 830 if (tcs > 1) 831 max_tx_rings /= tcs; 832 833 channel->max_rx = max_rx_rings; 834 channel->max_tx = max_tx_rings; 835 channel->max_other = 0; 836 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 837 channel->combined_count = bp->rx_nr_rings; 838 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 839 channel->combined_count--; 840 } else { 841 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 842 channel->rx_count = bp->rx_nr_rings; 843 channel->tx_count = bp->tx_nr_rings_per_tc; 844 } 845 } 846 } 847 848 static int bnxt_set_channels(struct net_device *dev, 849 struct ethtool_channels *channel) 850 { 851 struct bnxt *bp = netdev_priv(dev); 852 int req_tx_rings, req_rx_rings, tcs; 853 bool sh = false; 854 int tx_xdp = 0; 855 int rc = 0; 856 857 if (channel->other_count) 858 return -EINVAL; 859 860 if (!channel->combined_count && 861 (!channel->rx_count || !channel->tx_count)) 862 return -EINVAL; 863 864 if (channel->combined_count && 865 (channel->rx_count || channel->tx_count)) 866 return -EINVAL; 867 868 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 869 channel->tx_count)) 870 return -EINVAL; 871 872 if (channel->combined_count) 873 sh = true; 874 875 tcs = netdev_get_num_tc(dev); 876 877 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 878 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 879 if (bp->tx_nr_rings_xdp) { 880 if (!sh) { 881 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 882 return -EINVAL; 883 } 884 tx_xdp = req_rx_rings; 885 } 886 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 887 if (rc) { 888 netdev_warn(dev, "Unable to allocate the requested rings\n"); 889 return rc; 890 } 891 892 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 893 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 894 (dev->priv_flags & IFF_RXFH_CONFIGURED)) { 895 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 896 return -EINVAL; 897 } 898 899 if (netif_running(dev)) { 900 if (BNXT_PF(bp)) { 901 /* TODO CHIMP_FW: Send message to all VF's 902 * before PF unload 903 */ 904 } 905 rc = bnxt_close_nic(bp, true, false); 906 if (rc) { 907 netdev_err(bp->dev, "Set channel failure rc :%x\n", 908 rc); 909 return rc; 910 } 911 } 912 913 if (sh) { 914 bp->flags |= BNXT_FLAG_SHARED_RINGS; 915 bp->rx_nr_rings = channel->combined_count; 916 bp->tx_nr_rings_per_tc = channel->combined_count; 917 } else { 918 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 919 bp->rx_nr_rings = channel->rx_count; 920 bp->tx_nr_rings_per_tc = channel->tx_count; 921 } 922 bp->tx_nr_rings_xdp = tx_xdp; 923 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 924 if (tcs > 1) 925 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 926 927 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 928 bp->tx_nr_rings + bp->rx_nr_rings; 929 930 /* After changing number of rx channels, update NTUPLE feature. */ 931 netdev_update_features(dev); 932 if (netif_running(dev)) { 933 rc = bnxt_open_nic(bp, true, false); 934 if ((!rc) && BNXT_PF(bp)) { 935 /* TODO CHIMP_FW: Send message to all VF's 936 * to renable 937 */ 938 } 939 } else { 940 rc = bnxt_reserve_rings(bp, true); 941 } 942 943 return rc; 944 } 945 946 #ifdef CONFIG_RFS_ACCEL 947 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 948 u32 *rule_locs) 949 { 950 int i, j = 0; 951 952 cmd->data = bp->ntp_fltr_count; 953 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 954 struct hlist_head *head; 955 struct bnxt_ntuple_filter *fltr; 956 957 head = &bp->ntp_fltr_hash_tbl[i]; 958 rcu_read_lock(); 959 hlist_for_each_entry_rcu(fltr, head, hash) { 960 if (j == cmd->rule_cnt) 961 break; 962 rule_locs[j++] = fltr->sw_id; 963 } 964 rcu_read_unlock(); 965 if (j == cmd->rule_cnt) 966 break; 967 } 968 cmd->rule_cnt = j; 969 return 0; 970 } 971 972 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 973 { 974 struct ethtool_rx_flow_spec *fs = 975 (struct ethtool_rx_flow_spec *)&cmd->fs; 976 struct bnxt_ntuple_filter *fltr; 977 struct flow_keys *fkeys; 978 int i, rc = -EINVAL; 979 980 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 981 return rc; 982 983 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 984 struct hlist_head *head; 985 986 head = &bp->ntp_fltr_hash_tbl[i]; 987 rcu_read_lock(); 988 hlist_for_each_entry_rcu(fltr, head, hash) { 989 if (fltr->sw_id == fs->location) 990 goto fltr_found; 991 } 992 rcu_read_unlock(); 993 } 994 return rc; 995 996 fltr_found: 997 fkeys = &fltr->fkeys; 998 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 999 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1000 fs->flow_type = TCP_V4_FLOW; 1001 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1002 fs->flow_type = UDP_V4_FLOW; 1003 else 1004 goto fltr_err; 1005 1006 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1007 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1008 1009 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1010 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1011 1012 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1013 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1014 1015 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1016 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1017 } else { 1018 int i; 1019 1020 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1021 fs->flow_type = TCP_V6_FLOW; 1022 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1023 fs->flow_type = UDP_V6_FLOW; 1024 else 1025 goto fltr_err; 1026 1027 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1028 fkeys->addrs.v6addrs.src; 1029 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1030 fkeys->addrs.v6addrs.dst; 1031 for (i = 0; i < 4; i++) { 1032 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1033 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1034 } 1035 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1036 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1037 1038 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1039 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1040 } 1041 1042 fs->ring_cookie = fltr->rxq; 1043 rc = 0; 1044 1045 fltr_err: 1046 rcu_read_unlock(); 1047 1048 return rc; 1049 } 1050 #endif 1051 1052 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1053 { 1054 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1055 return RXH_IP_SRC | RXH_IP_DST; 1056 return 0; 1057 } 1058 1059 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1060 { 1061 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1062 return RXH_IP_SRC | RXH_IP_DST; 1063 return 0; 1064 } 1065 1066 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1067 { 1068 cmd->data = 0; 1069 switch (cmd->flow_type) { 1070 case TCP_V4_FLOW: 1071 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1072 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1073 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1074 cmd->data |= get_ethtool_ipv4_rss(bp); 1075 break; 1076 case UDP_V4_FLOW: 1077 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1078 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1079 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1080 fallthrough; 1081 case SCTP_V4_FLOW: 1082 case AH_ESP_V4_FLOW: 1083 case AH_V4_FLOW: 1084 case ESP_V4_FLOW: 1085 case IPV4_FLOW: 1086 cmd->data |= get_ethtool_ipv4_rss(bp); 1087 break; 1088 1089 case TCP_V6_FLOW: 1090 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1091 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1092 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1093 cmd->data |= get_ethtool_ipv6_rss(bp); 1094 break; 1095 case UDP_V6_FLOW: 1096 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1097 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1098 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1099 fallthrough; 1100 case SCTP_V6_FLOW: 1101 case AH_ESP_V6_FLOW: 1102 case AH_V6_FLOW: 1103 case ESP_V6_FLOW: 1104 case IPV6_FLOW: 1105 cmd->data |= get_ethtool_ipv6_rss(bp); 1106 break; 1107 } 1108 return 0; 1109 } 1110 1111 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1112 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1113 1114 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1115 { 1116 u32 rss_hash_cfg = bp->rss_hash_cfg; 1117 int tuple, rc = 0; 1118 1119 if (cmd->data == RXH_4TUPLE) 1120 tuple = 4; 1121 else if (cmd->data == RXH_2TUPLE) 1122 tuple = 2; 1123 else if (!cmd->data) 1124 tuple = 0; 1125 else 1126 return -EINVAL; 1127 1128 if (cmd->flow_type == TCP_V4_FLOW) { 1129 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1130 if (tuple == 4) 1131 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1132 } else if (cmd->flow_type == UDP_V4_FLOW) { 1133 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1134 return -EINVAL; 1135 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1136 if (tuple == 4) 1137 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1138 } else if (cmd->flow_type == TCP_V6_FLOW) { 1139 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1140 if (tuple == 4) 1141 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1142 } else if (cmd->flow_type == UDP_V6_FLOW) { 1143 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1144 return -EINVAL; 1145 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1146 if (tuple == 4) 1147 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1148 } else if (tuple == 4) { 1149 return -EINVAL; 1150 } 1151 1152 switch (cmd->flow_type) { 1153 case TCP_V4_FLOW: 1154 case UDP_V4_FLOW: 1155 case SCTP_V4_FLOW: 1156 case AH_ESP_V4_FLOW: 1157 case AH_V4_FLOW: 1158 case ESP_V4_FLOW: 1159 case IPV4_FLOW: 1160 if (tuple == 2) 1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1162 else if (!tuple) 1163 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1164 break; 1165 1166 case TCP_V6_FLOW: 1167 case UDP_V6_FLOW: 1168 case SCTP_V6_FLOW: 1169 case AH_ESP_V6_FLOW: 1170 case AH_V6_FLOW: 1171 case ESP_V6_FLOW: 1172 case IPV6_FLOW: 1173 if (tuple == 2) 1174 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1175 else if (!tuple) 1176 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1177 break; 1178 } 1179 1180 if (bp->rss_hash_cfg == rss_hash_cfg) 1181 return 0; 1182 1183 bp->rss_hash_cfg = rss_hash_cfg; 1184 if (netif_running(bp->dev)) { 1185 bnxt_close_nic(bp, false, false); 1186 rc = bnxt_open_nic(bp, false, false); 1187 } 1188 return rc; 1189 } 1190 1191 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1192 u32 *rule_locs) 1193 { 1194 struct bnxt *bp = netdev_priv(dev); 1195 int rc = 0; 1196 1197 switch (cmd->cmd) { 1198 #ifdef CONFIG_RFS_ACCEL 1199 case ETHTOOL_GRXRINGS: 1200 cmd->data = bp->rx_nr_rings; 1201 break; 1202 1203 case ETHTOOL_GRXCLSRLCNT: 1204 cmd->rule_cnt = bp->ntp_fltr_count; 1205 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1206 break; 1207 1208 case ETHTOOL_GRXCLSRLALL: 1209 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1210 break; 1211 1212 case ETHTOOL_GRXCLSRULE: 1213 rc = bnxt_grxclsrule(bp, cmd); 1214 break; 1215 #endif 1216 1217 case ETHTOOL_GRXFH: 1218 rc = bnxt_grxfh(bp, cmd); 1219 break; 1220 1221 default: 1222 rc = -EOPNOTSUPP; 1223 break; 1224 } 1225 1226 return rc; 1227 } 1228 1229 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1230 { 1231 struct bnxt *bp = netdev_priv(dev); 1232 int rc; 1233 1234 switch (cmd->cmd) { 1235 case ETHTOOL_SRXFH: 1236 rc = bnxt_srxfh(bp, cmd); 1237 break; 1238 1239 default: 1240 rc = -EOPNOTSUPP; 1241 break; 1242 } 1243 return rc; 1244 } 1245 1246 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1247 { 1248 struct bnxt *bp = netdev_priv(dev); 1249 1250 if (bp->flags & BNXT_FLAG_CHIP_P5) 1251 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1252 return HW_HASH_INDEX_SIZE; 1253 } 1254 1255 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1256 { 1257 return HW_HASH_KEY_SIZE; 1258 } 1259 1260 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1261 u8 *hfunc) 1262 { 1263 struct bnxt *bp = netdev_priv(dev); 1264 struct bnxt_vnic_info *vnic; 1265 u32 i, tbl_size; 1266 1267 if (hfunc) 1268 *hfunc = ETH_RSS_HASH_TOP; 1269 1270 if (!bp->vnic_info) 1271 return 0; 1272 1273 vnic = &bp->vnic_info[0]; 1274 if (indir && bp->rss_indir_tbl) { 1275 tbl_size = bnxt_get_rxfh_indir_size(dev); 1276 for (i = 0; i < tbl_size; i++) 1277 indir[i] = bp->rss_indir_tbl[i]; 1278 } 1279 1280 if (key && vnic->rss_hash_key) 1281 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1282 1283 return 0; 1284 } 1285 1286 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1287 const u8 *key, const u8 hfunc) 1288 { 1289 struct bnxt *bp = netdev_priv(dev); 1290 int rc = 0; 1291 1292 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1293 return -EOPNOTSUPP; 1294 1295 if (key) 1296 return -EOPNOTSUPP; 1297 1298 if (indir) { 1299 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1300 1301 for (i = 0; i < tbl_size; i++) 1302 bp->rss_indir_tbl[i] = indir[i]; 1303 pad = bp->rss_indir_tbl_entries - tbl_size; 1304 if (pad) 1305 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1306 } 1307 1308 if (netif_running(bp->dev)) { 1309 bnxt_close_nic(bp, false, false); 1310 rc = bnxt_open_nic(bp, false, false); 1311 } 1312 return rc; 1313 } 1314 1315 static void bnxt_get_drvinfo(struct net_device *dev, 1316 struct ethtool_drvinfo *info) 1317 { 1318 struct bnxt *bp = netdev_priv(dev); 1319 1320 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1321 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1322 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1323 info->n_stats = bnxt_get_num_stats(bp); 1324 info->testinfo_len = bp->num_tests; 1325 /* TODO CHIMP_FW: eeprom dump details */ 1326 info->eedump_len = 0; 1327 /* TODO CHIMP FW: reg dump details */ 1328 info->regdump_len = 0; 1329 } 1330 1331 static int bnxt_get_regs_len(struct net_device *dev) 1332 { 1333 struct bnxt *bp = netdev_priv(dev); 1334 int reg_len; 1335 1336 if (!BNXT_PF(bp)) 1337 return -EOPNOTSUPP; 1338 1339 reg_len = BNXT_PXP_REG_LEN; 1340 1341 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1342 reg_len += sizeof(struct pcie_ctx_hw_stats); 1343 1344 return reg_len; 1345 } 1346 1347 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1348 void *_p) 1349 { 1350 struct pcie_ctx_hw_stats *hw_pcie_stats; 1351 struct hwrm_pcie_qstats_input req = {0}; 1352 struct bnxt *bp = netdev_priv(dev); 1353 dma_addr_t hw_pcie_stats_addr; 1354 int rc; 1355 1356 regs->version = 0; 1357 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1358 1359 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1360 return; 1361 1362 hw_pcie_stats = dma_alloc_coherent(&bp->pdev->dev, 1363 sizeof(*hw_pcie_stats), 1364 &hw_pcie_stats_addr, GFP_KERNEL); 1365 if (!hw_pcie_stats) 1366 return; 1367 1368 regs->version = 1; 1369 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1); 1370 req.pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1371 req.pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1372 mutex_lock(&bp->hwrm_cmd_lock); 1373 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1374 if (!rc) { 1375 __le64 *src = (__le64 *)hw_pcie_stats; 1376 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1377 int i; 1378 1379 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1380 dst[i] = le64_to_cpu(src[i]); 1381 } 1382 mutex_unlock(&bp->hwrm_cmd_lock); 1383 dma_free_coherent(&bp->pdev->dev, sizeof(*hw_pcie_stats), hw_pcie_stats, 1384 hw_pcie_stats_addr); 1385 } 1386 1387 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1388 { 1389 struct bnxt *bp = netdev_priv(dev); 1390 1391 wol->supported = 0; 1392 wol->wolopts = 0; 1393 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1394 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1395 wol->supported = WAKE_MAGIC; 1396 if (bp->wol) 1397 wol->wolopts = WAKE_MAGIC; 1398 } 1399 } 1400 1401 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1402 { 1403 struct bnxt *bp = netdev_priv(dev); 1404 1405 if (wol->wolopts & ~WAKE_MAGIC) 1406 return -EINVAL; 1407 1408 if (wol->wolopts & WAKE_MAGIC) { 1409 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1410 return -EINVAL; 1411 if (!bp->wol) { 1412 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1413 return -EBUSY; 1414 bp->wol = 1; 1415 } 1416 } else { 1417 if (bp->wol) { 1418 if (bnxt_hwrm_free_wol_fltr(bp)) 1419 return -EBUSY; 1420 bp->wol = 0; 1421 } 1422 } 1423 return 0; 1424 } 1425 1426 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1427 { 1428 u32 speed_mask = 0; 1429 1430 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1431 /* set the advertised speeds */ 1432 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1433 speed_mask |= ADVERTISED_100baseT_Full; 1434 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1435 speed_mask |= ADVERTISED_1000baseT_Full; 1436 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1437 speed_mask |= ADVERTISED_2500baseX_Full; 1438 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1439 speed_mask |= ADVERTISED_10000baseT_Full; 1440 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1441 speed_mask |= ADVERTISED_40000baseCR4_Full; 1442 1443 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1444 speed_mask |= ADVERTISED_Pause; 1445 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1446 speed_mask |= ADVERTISED_Asym_Pause; 1447 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1448 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1449 1450 return speed_mask; 1451 } 1452 1453 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\ 1454 { \ 1455 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \ 1456 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1457 100baseT_Full); \ 1458 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \ 1459 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1460 1000baseT_Full); \ 1461 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \ 1462 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1463 10000baseT_Full); \ 1464 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \ 1465 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1466 25000baseCR_Full); \ 1467 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \ 1468 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1469 40000baseCR4_Full);\ 1470 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \ 1471 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1472 50000baseCR2_Full);\ 1473 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \ 1474 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1475 100000baseCR4_Full);\ 1476 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \ 1477 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1478 Pause); \ 1479 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \ 1480 ethtool_link_ksettings_add_link_mode( \ 1481 lk_ksettings, name, Asym_Pause);\ 1482 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \ 1483 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1484 Asym_Pause); \ 1485 } \ 1486 } 1487 1488 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \ 1489 { \ 1490 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1491 100baseT_Full) || \ 1492 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1493 100baseT_Half)) \ 1494 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \ 1495 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1496 1000baseT_Full) || \ 1497 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1498 1000baseT_Half)) \ 1499 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \ 1500 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1501 10000baseT_Full)) \ 1502 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \ 1503 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1504 25000baseCR_Full)) \ 1505 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \ 1506 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1507 40000baseCR4_Full)) \ 1508 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \ 1509 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1510 50000baseCR2_Full)) \ 1511 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \ 1512 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1513 100000baseCR4_Full)) \ 1514 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \ 1515 } 1516 1517 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1518 { \ 1519 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \ 1520 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1521 50000baseCR_Full); \ 1522 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \ 1523 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1524 100000baseCR2_Full);\ 1525 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \ 1526 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\ 1527 200000baseCR4_Full);\ 1528 } 1529 1530 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \ 1531 { \ 1532 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1533 50000baseCR_Full)) \ 1534 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \ 1535 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1536 100000baseCR2_Full)) \ 1537 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \ 1538 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \ 1539 200000baseCR4_Full)) \ 1540 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \ 1541 } 1542 1543 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1544 struct ethtool_link_ksettings *lk_ksettings) 1545 { 1546 u16 fec_cfg = link_info->fec_cfg; 1547 1548 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1549 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1550 lk_ksettings->link_modes.advertising); 1551 return; 1552 } 1553 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1554 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1555 lk_ksettings->link_modes.advertising); 1556 if (fec_cfg & BNXT_FEC_ENC_RS) 1557 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1558 lk_ksettings->link_modes.advertising); 1559 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1560 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1561 lk_ksettings->link_modes.advertising); 1562 } 1563 1564 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info, 1565 struct ethtool_link_ksettings *lk_ksettings) 1566 { 1567 u16 fw_speeds = link_info->advertising; 1568 u8 fw_pause = 0; 1569 1570 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1571 fw_pause = link_info->auto_pause_setting; 1572 1573 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising); 1574 fw_speeds = link_info->advertising_pam4; 1575 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising); 1576 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 1577 } 1578 1579 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info, 1580 struct ethtool_link_ksettings *lk_ksettings) 1581 { 1582 u16 fw_speeds = link_info->lp_auto_link_speeds; 1583 u8 fw_pause = 0; 1584 1585 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1586 fw_pause = link_info->lp_pause; 1587 1588 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, 1589 lp_advertising); 1590 fw_speeds = link_info->lp_auto_pam4_link_speeds; 1591 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising); 1592 } 1593 1594 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1595 struct ethtool_link_ksettings *lk_ksettings) 1596 { 1597 u16 fec_cfg = link_info->fec_cfg; 1598 1599 if (fec_cfg & BNXT_FEC_NONE) { 1600 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1601 lk_ksettings->link_modes.supported); 1602 return; 1603 } 1604 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1605 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1606 lk_ksettings->link_modes.supported); 1607 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1608 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1609 lk_ksettings->link_modes.supported); 1610 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1611 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1612 lk_ksettings->link_modes.supported); 1613 } 1614 1615 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info, 1616 struct ethtool_link_ksettings *lk_ksettings) 1617 { 1618 u16 fw_speeds = link_info->support_speeds; 1619 1620 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported); 1621 fw_speeds = link_info->support_pam4_speeds; 1622 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported); 1623 1624 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause); 1625 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1626 Asym_Pause); 1627 1628 if (link_info->support_auto_speeds || 1629 link_info->support_pam4_auto_speeds) 1630 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1631 Autoneg); 1632 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 1633 } 1634 1635 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1636 { 1637 switch (fw_link_speed) { 1638 case BNXT_LINK_SPEED_100MB: 1639 return SPEED_100; 1640 case BNXT_LINK_SPEED_1GB: 1641 return SPEED_1000; 1642 case BNXT_LINK_SPEED_2_5GB: 1643 return SPEED_2500; 1644 case BNXT_LINK_SPEED_10GB: 1645 return SPEED_10000; 1646 case BNXT_LINK_SPEED_20GB: 1647 return SPEED_20000; 1648 case BNXT_LINK_SPEED_25GB: 1649 return SPEED_25000; 1650 case BNXT_LINK_SPEED_40GB: 1651 return SPEED_40000; 1652 case BNXT_LINK_SPEED_50GB: 1653 return SPEED_50000; 1654 case BNXT_LINK_SPEED_100GB: 1655 return SPEED_100000; 1656 default: 1657 return SPEED_UNKNOWN; 1658 } 1659 } 1660 1661 static int bnxt_get_link_ksettings(struct net_device *dev, 1662 struct ethtool_link_ksettings *lk_ksettings) 1663 { 1664 struct bnxt *bp = netdev_priv(dev); 1665 struct bnxt_link_info *link_info = &bp->link_info; 1666 struct ethtool_link_settings *base = &lk_ksettings->base; 1667 u32 ethtool_speed; 1668 1669 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 1670 mutex_lock(&bp->link_lock); 1671 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings); 1672 1673 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 1674 if (link_info->autoneg) { 1675 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings); 1676 ethtool_link_ksettings_add_link_mode(lk_ksettings, 1677 advertising, Autoneg); 1678 base->autoneg = AUTONEG_ENABLE; 1679 base->duplex = DUPLEX_UNKNOWN; 1680 if (link_info->phy_link_status == BNXT_LINK_LINK) { 1681 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings); 1682 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1683 base->duplex = DUPLEX_FULL; 1684 else 1685 base->duplex = DUPLEX_HALF; 1686 } 1687 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1688 } else { 1689 base->autoneg = AUTONEG_DISABLE; 1690 ethtool_speed = 1691 bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1692 base->duplex = DUPLEX_HALF; 1693 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1694 base->duplex = DUPLEX_FULL; 1695 } 1696 base->speed = ethtool_speed; 1697 1698 base->port = PORT_NONE; 1699 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1700 base->port = PORT_TP; 1701 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1702 TP); 1703 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1704 TP); 1705 } else { 1706 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, 1707 FIBRE); 1708 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising, 1709 FIBRE); 1710 1711 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 1712 base->port = PORT_DA; 1713 else if (link_info->media_type == 1714 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE) 1715 base->port = PORT_FIBRE; 1716 } 1717 base->phy_address = link_info->phy_addr; 1718 mutex_unlock(&bp->link_lock); 1719 1720 return 0; 1721 } 1722 1723 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed) 1724 { 1725 struct bnxt *bp = netdev_priv(dev); 1726 struct bnxt_link_info *link_info = &bp->link_info; 1727 u16 support_pam4_spds = link_info->support_pam4_speeds; 1728 u16 support_spds = link_info->support_speeds; 1729 u8 sig_mode = BNXT_SIG_MODE_NRZ; 1730 u16 fw_speed = 0; 1731 1732 switch (ethtool_speed) { 1733 case SPEED_100: 1734 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 1735 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 1736 break; 1737 case SPEED_1000: 1738 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 1739 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 1740 break; 1741 case SPEED_2500: 1742 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 1743 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 1744 break; 1745 case SPEED_10000: 1746 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 1747 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 1748 break; 1749 case SPEED_20000: 1750 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) 1751 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 1752 break; 1753 case SPEED_25000: 1754 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 1755 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 1756 break; 1757 case SPEED_40000: 1758 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) 1759 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 1760 break; 1761 case SPEED_50000: 1762 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) { 1763 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 1764 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 1765 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 1766 sig_mode = BNXT_SIG_MODE_PAM4; 1767 } 1768 break; 1769 case SPEED_100000: 1770 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) { 1771 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 1772 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 1773 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 1774 sig_mode = BNXT_SIG_MODE_PAM4; 1775 } 1776 break; 1777 case SPEED_200000: 1778 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 1779 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 1780 sig_mode = BNXT_SIG_MODE_PAM4; 1781 } 1782 break; 1783 } 1784 1785 if (!fw_speed) { 1786 netdev_err(dev, "unsupported speed!\n"); 1787 return -EINVAL; 1788 } 1789 1790 if (link_info->req_link_speed == fw_speed && 1791 link_info->req_signal_mode == sig_mode && 1792 link_info->autoneg == 0) 1793 return -EALREADY; 1794 1795 link_info->req_link_speed = fw_speed; 1796 link_info->req_signal_mode = sig_mode; 1797 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 1798 link_info->autoneg = 0; 1799 link_info->advertising = 0; 1800 link_info->advertising_pam4 = 0; 1801 1802 return 0; 1803 } 1804 1805 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 1806 { 1807 u16 fw_speed_mask = 0; 1808 1809 /* only support autoneg at speed 100, 1000, and 10000 */ 1810 if (advertising & (ADVERTISED_100baseT_Full | 1811 ADVERTISED_100baseT_Half)) { 1812 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 1813 } 1814 if (advertising & (ADVERTISED_1000baseT_Full | 1815 ADVERTISED_1000baseT_Half)) { 1816 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 1817 } 1818 if (advertising & ADVERTISED_10000baseT_Full) 1819 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 1820 1821 if (advertising & ADVERTISED_40000baseCR4_Full) 1822 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 1823 1824 return fw_speed_mask; 1825 } 1826 1827 static int bnxt_set_link_ksettings(struct net_device *dev, 1828 const struct ethtool_link_ksettings *lk_ksettings) 1829 { 1830 struct bnxt *bp = netdev_priv(dev); 1831 struct bnxt_link_info *link_info = &bp->link_info; 1832 const struct ethtool_link_settings *base = &lk_ksettings->base; 1833 bool set_pause = false; 1834 u32 speed; 1835 int rc = 0; 1836 1837 if (!BNXT_PHY_CFG_ABLE(bp)) 1838 return -EOPNOTSUPP; 1839 1840 mutex_lock(&bp->link_lock); 1841 if (base->autoneg == AUTONEG_ENABLE) { 1842 link_info->advertising = 0; 1843 link_info->advertising_pam4 = 0; 1844 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings, 1845 advertising); 1846 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4, 1847 lk_ksettings, advertising); 1848 link_info->autoneg |= BNXT_AUTONEG_SPEED; 1849 if (!link_info->advertising && !link_info->advertising_pam4) { 1850 link_info->advertising = link_info->support_auto_speeds; 1851 link_info->advertising_pam4 = 1852 link_info->support_pam4_auto_speeds; 1853 } 1854 /* any change to autoneg will cause link change, therefore the 1855 * driver should put back the original pause setting in autoneg 1856 */ 1857 set_pause = true; 1858 } else { 1859 u8 phy_type = link_info->phy_type; 1860 1861 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 1862 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 1863 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 1864 netdev_err(dev, "10GBase-T devices must autoneg\n"); 1865 rc = -EINVAL; 1866 goto set_setting_exit; 1867 } 1868 if (base->duplex == DUPLEX_HALF) { 1869 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 1870 rc = -EINVAL; 1871 goto set_setting_exit; 1872 } 1873 speed = base->speed; 1874 rc = bnxt_force_link_speed(dev, speed); 1875 if (rc) { 1876 if (rc == -EALREADY) 1877 rc = 0; 1878 goto set_setting_exit; 1879 } 1880 } 1881 1882 if (netif_running(dev)) 1883 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 1884 1885 set_setting_exit: 1886 mutex_unlock(&bp->link_lock); 1887 return rc; 1888 } 1889 1890 static int bnxt_get_fecparam(struct net_device *dev, 1891 struct ethtool_fecparam *fec) 1892 { 1893 struct bnxt *bp = netdev_priv(dev); 1894 struct bnxt_link_info *link_info; 1895 u8 active_fec; 1896 u16 fec_cfg; 1897 1898 link_info = &bp->link_info; 1899 fec_cfg = link_info->fec_cfg; 1900 active_fec = link_info->active_fec_sig_mode & 1901 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 1902 if (fec_cfg & BNXT_FEC_NONE) { 1903 fec->fec = ETHTOOL_FEC_NONE; 1904 fec->active_fec = ETHTOOL_FEC_NONE; 1905 return 0; 1906 } 1907 if (fec_cfg & BNXT_FEC_AUTONEG) 1908 fec->fec |= ETHTOOL_FEC_AUTO; 1909 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1910 fec->fec |= ETHTOOL_FEC_BASER; 1911 if (fec_cfg & BNXT_FEC_ENC_RS) 1912 fec->fec |= ETHTOOL_FEC_RS; 1913 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1914 fec->fec |= ETHTOOL_FEC_LLRS; 1915 1916 switch (active_fec) { 1917 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 1918 fec->active_fec |= ETHTOOL_FEC_BASER; 1919 break; 1920 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 1921 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 1922 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 1923 fec->active_fec |= ETHTOOL_FEC_RS; 1924 break; 1925 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 1926 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 1927 fec->active_fec |= ETHTOOL_FEC_LLRS; 1928 break; 1929 } 1930 return 0; 1931 } 1932 1933 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 1934 u32 fec) 1935 { 1936 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 1937 1938 if (fec & ETHTOOL_FEC_BASER) 1939 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 1940 else if (fec & ETHTOOL_FEC_RS) 1941 fw_fec |= BNXT_FEC_RS_ON(link_info); 1942 else if (fec & ETHTOOL_FEC_LLRS) 1943 fw_fec |= BNXT_FEC_LLRS_ON; 1944 return fw_fec; 1945 } 1946 1947 static int bnxt_set_fecparam(struct net_device *dev, 1948 struct ethtool_fecparam *fecparam) 1949 { 1950 struct hwrm_port_phy_cfg_input req = {0}; 1951 struct bnxt *bp = netdev_priv(dev); 1952 struct bnxt_link_info *link_info; 1953 u32 new_cfg, fec = fecparam->fec; 1954 u16 fec_cfg; 1955 int rc; 1956 1957 link_info = &bp->link_info; 1958 fec_cfg = link_info->fec_cfg; 1959 if (fec_cfg & BNXT_FEC_NONE) 1960 return -EOPNOTSUPP; 1961 1962 if (fec & ETHTOOL_FEC_OFF) { 1963 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 1964 BNXT_FEC_ALL_OFF(link_info); 1965 goto apply_fec; 1966 } 1967 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 1968 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 1969 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 1970 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 1971 return -EINVAL; 1972 1973 if (fec & ETHTOOL_FEC_AUTO) { 1974 if (!link_info->autoneg) 1975 return -EINVAL; 1976 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 1977 } else { 1978 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 1979 } 1980 1981 apply_fec: 1982 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 1983 req.flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 1984 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 1985 /* update current settings */ 1986 if (!rc) { 1987 mutex_lock(&bp->link_lock); 1988 bnxt_update_link(bp, false); 1989 mutex_unlock(&bp->link_lock); 1990 } 1991 return rc; 1992 } 1993 1994 static void bnxt_get_pauseparam(struct net_device *dev, 1995 struct ethtool_pauseparam *epause) 1996 { 1997 struct bnxt *bp = netdev_priv(dev); 1998 struct bnxt_link_info *link_info = &bp->link_info; 1999 2000 if (BNXT_VF(bp)) 2001 return; 2002 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2003 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2004 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2005 } 2006 2007 static void bnxt_get_pause_stats(struct net_device *dev, 2008 struct ethtool_pause_stats *epstat) 2009 { 2010 struct bnxt *bp = netdev_priv(dev); 2011 u64 *rx, *tx; 2012 2013 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2014 return; 2015 2016 rx = bp->port_stats.sw_stats; 2017 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2018 2019 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2020 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2021 } 2022 2023 static int bnxt_set_pauseparam(struct net_device *dev, 2024 struct ethtool_pauseparam *epause) 2025 { 2026 int rc = 0; 2027 struct bnxt *bp = netdev_priv(dev); 2028 struct bnxt_link_info *link_info = &bp->link_info; 2029 2030 if (!BNXT_PHY_CFG_ABLE(bp)) 2031 return -EOPNOTSUPP; 2032 2033 mutex_lock(&bp->link_lock); 2034 if (epause->autoneg) { 2035 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2036 rc = -EINVAL; 2037 goto pause_exit; 2038 } 2039 2040 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2041 if (bp->hwrm_spec_code >= 0x10201) 2042 link_info->req_flow_ctrl = 2043 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE; 2044 } else { 2045 /* when transition from auto pause to force pause, 2046 * force a link change 2047 */ 2048 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2049 link_info->force_link_chng = true; 2050 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2051 link_info->req_flow_ctrl = 0; 2052 } 2053 if (epause->rx_pause) 2054 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2055 2056 if (epause->tx_pause) 2057 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2058 2059 if (netif_running(dev)) 2060 rc = bnxt_hwrm_set_pause(bp); 2061 2062 pause_exit: 2063 mutex_unlock(&bp->link_lock); 2064 return rc; 2065 } 2066 2067 static u32 bnxt_get_link(struct net_device *dev) 2068 { 2069 struct bnxt *bp = netdev_priv(dev); 2070 2071 /* TODO: handle MF, VF, driver close case */ 2072 return bp->link_info.link_up; 2073 } 2074 2075 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2076 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2077 { 2078 struct hwrm_nvm_get_dev_info_output *resp = bp->hwrm_cmd_resp_addr; 2079 struct hwrm_nvm_get_dev_info_input req = {0}; 2080 int rc; 2081 2082 if (BNXT_VF(bp)) 2083 return -EOPNOTSUPP; 2084 2085 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DEV_INFO, -1, -1); 2086 mutex_lock(&bp->hwrm_cmd_lock); 2087 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2088 if (!rc) 2089 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2090 mutex_unlock(&bp->hwrm_cmd_lock); 2091 return rc; 2092 } 2093 2094 static void bnxt_print_admin_err(struct bnxt *bp) 2095 { 2096 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2097 } 2098 2099 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2100 u16 ext, u16 *index, u32 *item_length, 2101 u32 *data_length); 2102 2103 static int bnxt_flash_nvram(struct net_device *dev, 2104 u16 dir_type, 2105 u16 dir_ordinal, 2106 u16 dir_ext, 2107 u16 dir_attr, 2108 const u8 *data, 2109 size_t data_len) 2110 { 2111 struct bnxt *bp = netdev_priv(dev); 2112 int rc; 2113 struct hwrm_nvm_write_input req = {0}; 2114 dma_addr_t dma_handle; 2115 u8 *kmem; 2116 2117 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1); 2118 2119 req.dir_type = cpu_to_le16(dir_type); 2120 req.dir_ordinal = cpu_to_le16(dir_ordinal); 2121 req.dir_ext = cpu_to_le16(dir_ext); 2122 req.dir_attr = cpu_to_le16(dir_attr); 2123 req.dir_data_length = cpu_to_le32(data_len); 2124 2125 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle, 2126 GFP_KERNEL); 2127 if (!kmem) { 2128 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2129 (unsigned)data_len); 2130 return -ENOMEM; 2131 } 2132 memcpy(kmem, data, data_len); 2133 req.host_src_addr = cpu_to_le64(dma_handle); 2134 2135 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT); 2136 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle); 2137 2138 if (rc == -EACCES) 2139 bnxt_print_admin_err(bp); 2140 return rc; 2141 } 2142 2143 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2144 u8 self_reset, u8 flags) 2145 { 2146 struct hwrm_fw_reset_input req = {0}; 2147 struct bnxt *bp = netdev_priv(dev); 2148 int rc; 2149 2150 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1); 2151 2152 req.embedded_proc_type = proc_type; 2153 req.selfrst_status = self_reset; 2154 req.flags = flags; 2155 2156 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2157 rc = hwrm_send_message_silent(bp, &req, sizeof(req), 2158 HWRM_CMD_TIMEOUT); 2159 } else { 2160 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2161 if (rc == -EACCES) 2162 bnxt_print_admin_err(bp); 2163 } 2164 return rc; 2165 } 2166 2167 static int bnxt_firmware_reset(struct net_device *dev, 2168 enum bnxt_nvm_directory_type dir_type) 2169 { 2170 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2171 u8 proc_type, flags = 0; 2172 2173 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2174 /* (e.g. when firmware isn't already running) */ 2175 switch (dir_type) { 2176 case BNX_DIR_TYPE_CHIMP_PATCH: 2177 case BNX_DIR_TYPE_BOOTCODE: 2178 case BNX_DIR_TYPE_BOOTCODE_2: 2179 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2180 /* Self-reset ChiMP upon next PCIe reset: */ 2181 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2182 break; 2183 case BNX_DIR_TYPE_APE_FW: 2184 case BNX_DIR_TYPE_APE_PATCH: 2185 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2186 /* Self-reset APE upon next PCIe reset: */ 2187 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2188 break; 2189 case BNX_DIR_TYPE_KONG_FW: 2190 case BNX_DIR_TYPE_KONG_PATCH: 2191 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2192 break; 2193 case BNX_DIR_TYPE_BONO_FW: 2194 case BNX_DIR_TYPE_BONO_PATCH: 2195 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2196 break; 2197 default: 2198 return -EINVAL; 2199 } 2200 2201 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2202 } 2203 2204 static int bnxt_firmware_reset_chip(struct net_device *dev) 2205 { 2206 struct bnxt *bp = netdev_priv(dev); 2207 u8 flags = 0; 2208 2209 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2210 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2211 2212 return bnxt_hwrm_firmware_reset(dev, 2213 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2214 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2215 flags); 2216 } 2217 2218 static int bnxt_firmware_reset_ap(struct net_device *dev) 2219 { 2220 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2221 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2222 0); 2223 } 2224 2225 static int bnxt_flash_firmware(struct net_device *dev, 2226 u16 dir_type, 2227 const u8 *fw_data, 2228 size_t fw_size) 2229 { 2230 int rc = 0; 2231 u16 code_type; 2232 u32 stored_crc; 2233 u32 calculated_crc; 2234 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2235 2236 switch (dir_type) { 2237 case BNX_DIR_TYPE_BOOTCODE: 2238 case BNX_DIR_TYPE_BOOTCODE_2: 2239 code_type = CODE_BOOT; 2240 break; 2241 case BNX_DIR_TYPE_CHIMP_PATCH: 2242 code_type = CODE_CHIMP_PATCH; 2243 break; 2244 case BNX_DIR_TYPE_APE_FW: 2245 code_type = CODE_MCTP_PASSTHRU; 2246 break; 2247 case BNX_DIR_TYPE_APE_PATCH: 2248 code_type = CODE_APE_PATCH; 2249 break; 2250 case BNX_DIR_TYPE_KONG_FW: 2251 code_type = CODE_KONG_FW; 2252 break; 2253 case BNX_DIR_TYPE_KONG_PATCH: 2254 code_type = CODE_KONG_PATCH; 2255 break; 2256 case BNX_DIR_TYPE_BONO_FW: 2257 code_type = CODE_BONO_FW; 2258 break; 2259 case BNX_DIR_TYPE_BONO_PATCH: 2260 code_type = CODE_BONO_PATCH; 2261 break; 2262 default: 2263 netdev_err(dev, "Unsupported directory entry type: %u\n", 2264 dir_type); 2265 return -EINVAL; 2266 } 2267 if (fw_size < sizeof(struct bnxt_fw_header)) { 2268 netdev_err(dev, "Invalid firmware file size: %u\n", 2269 (unsigned int)fw_size); 2270 return -EINVAL; 2271 } 2272 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2273 netdev_err(dev, "Invalid firmware signature: %08X\n", 2274 le32_to_cpu(header->signature)); 2275 return -EINVAL; 2276 } 2277 if (header->code_type != code_type) { 2278 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2279 code_type, header->code_type); 2280 return -EINVAL; 2281 } 2282 if (header->device != DEVICE_CUMULUS_FAMILY) { 2283 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2284 DEVICE_CUMULUS_FAMILY, header->device); 2285 return -EINVAL; 2286 } 2287 /* Confirm the CRC32 checksum of the file: */ 2288 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2289 sizeof(stored_crc))); 2290 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2291 if (calculated_crc != stored_crc) { 2292 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2293 (unsigned long)stored_crc, 2294 (unsigned long)calculated_crc); 2295 return -EINVAL; 2296 } 2297 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2298 0, 0, fw_data, fw_size); 2299 if (rc == 0) /* Firmware update successful */ 2300 rc = bnxt_firmware_reset(dev, dir_type); 2301 2302 return rc; 2303 } 2304 2305 static int bnxt_flash_microcode(struct net_device *dev, 2306 u16 dir_type, 2307 const u8 *fw_data, 2308 size_t fw_size) 2309 { 2310 struct bnxt_ucode_trailer *trailer; 2311 u32 calculated_crc; 2312 u32 stored_crc; 2313 int rc = 0; 2314 2315 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2316 netdev_err(dev, "Invalid microcode file size: %u\n", 2317 (unsigned int)fw_size); 2318 return -EINVAL; 2319 } 2320 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2321 sizeof(*trailer))); 2322 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2323 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2324 le32_to_cpu(trailer->sig)); 2325 return -EINVAL; 2326 } 2327 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2328 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2329 dir_type, le16_to_cpu(trailer->dir_type)); 2330 return -EINVAL; 2331 } 2332 if (le16_to_cpu(trailer->trailer_length) < 2333 sizeof(struct bnxt_ucode_trailer)) { 2334 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2335 le16_to_cpu(trailer->trailer_length)); 2336 return -EINVAL; 2337 } 2338 2339 /* Confirm the CRC32 checksum of the file: */ 2340 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2341 sizeof(stored_crc))); 2342 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2343 if (calculated_crc != stored_crc) { 2344 netdev_err(dev, 2345 "CRC32 (%08lX) does not match calculated: %08lX\n", 2346 (unsigned long)stored_crc, 2347 (unsigned long)calculated_crc); 2348 return -EINVAL; 2349 } 2350 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2351 0, 0, fw_data, fw_size); 2352 2353 return rc; 2354 } 2355 2356 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2357 { 2358 switch (dir_type) { 2359 case BNX_DIR_TYPE_CHIMP_PATCH: 2360 case BNX_DIR_TYPE_BOOTCODE: 2361 case BNX_DIR_TYPE_BOOTCODE_2: 2362 case BNX_DIR_TYPE_APE_FW: 2363 case BNX_DIR_TYPE_APE_PATCH: 2364 case BNX_DIR_TYPE_KONG_FW: 2365 case BNX_DIR_TYPE_KONG_PATCH: 2366 case BNX_DIR_TYPE_BONO_FW: 2367 case BNX_DIR_TYPE_BONO_PATCH: 2368 return true; 2369 } 2370 2371 return false; 2372 } 2373 2374 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2375 { 2376 switch (dir_type) { 2377 case BNX_DIR_TYPE_AVS: 2378 case BNX_DIR_TYPE_EXP_ROM_MBA: 2379 case BNX_DIR_TYPE_PCIE: 2380 case BNX_DIR_TYPE_TSCF_UCODE: 2381 case BNX_DIR_TYPE_EXT_PHY: 2382 case BNX_DIR_TYPE_CCM: 2383 case BNX_DIR_TYPE_ISCSI_BOOT: 2384 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2385 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2386 return true; 2387 } 2388 2389 return false; 2390 } 2391 2392 static bool bnxt_dir_type_is_executable(u16 dir_type) 2393 { 2394 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2395 bnxt_dir_type_is_other_exec_format(dir_type); 2396 } 2397 2398 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2399 u16 dir_type, 2400 const char *filename) 2401 { 2402 const struct firmware *fw; 2403 int rc; 2404 2405 rc = request_firmware(&fw, filename, &dev->dev); 2406 if (rc != 0) { 2407 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2408 rc, filename); 2409 return rc; 2410 } 2411 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2412 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2413 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2414 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2415 else 2416 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2417 0, 0, fw->data, fw->size); 2418 release_firmware(fw); 2419 return rc; 2420 } 2421 2422 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2423 u32 install_type) 2424 { 2425 struct bnxt *bp = netdev_priv(dev); 2426 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr; 2427 struct hwrm_nvm_install_update_input install = {0}; 2428 u32 item_len; 2429 int rc = 0; 2430 u16 index; 2431 2432 bnxt_hwrm_fw_set_time(bp); 2433 2434 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2435 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2436 &index, &item_len, NULL); 2437 if (rc) { 2438 netdev_err(dev, "PKG update area not created in nvram\n"); 2439 return rc; 2440 } 2441 2442 if (fw->size > item_len) { 2443 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n", 2444 (unsigned long)fw->size); 2445 rc = -EFBIG; 2446 } else { 2447 dma_addr_t dma_handle; 2448 u8 *kmem; 2449 struct hwrm_nvm_modify_input modify = {0}; 2450 2451 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1); 2452 2453 modify.dir_idx = cpu_to_le16(index); 2454 modify.len = cpu_to_le32(fw->size); 2455 2456 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size, 2457 &dma_handle, GFP_KERNEL); 2458 if (!kmem) { 2459 netdev_err(dev, 2460 "dma_alloc_coherent failure, length = %u\n", 2461 (unsigned int)fw->size); 2462 rc = -ENOMEM; 2463 } else { 2464 memcpy(kmem, fw->data, fw->size); 2465 modify.host_src_addr = cpu_to_le64(dma_handle); 2466 2467 rc = hwrm_send_message(bp, &modify, sizeof(modify), 2468 FLASH_PACKAGE_TIMEOUT); 2469 dma_free_coherent(&bp->pdev->dev, fw->size, kmem, 2470 dma_handle); 2471 } 2472 } 2473 if (rc) 2474 goto err_exit; 2475 2476 if ((install_type & 0xffff) == 0) 2477 install_type >>= 16; 2478 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1); 2479 install.install_type = cpu_to_le32(install_type); 2480 2481 mutex_lock(&bp->hwrm_cmd_lock); 2482 rc = _hwrm_send_message(bp, &install, sizeof(install), 2483 INSTALL_PACKAGE_TIMEOUT); 2484 if (rc) { 2485 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err; 2486 2487 if (resp->error_code && error_code == 2488 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) { 2489 install.flags |= cpu_to_le16( 2490 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 2491 rc = _hwrm_send_message(bp, &install, sizeof(install), 2492 INSTALL_PACKAGE_TIMEOUT); 2493 } 2494 if (rc) 2495 goto flash_pkg_exit; 2496 } 2497 2498 if (resp->result) { 2499 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 2500 (s8)resp->result, (int)resp->problem_item); 2501 rc = -ENOPKG; 2502 } 2503 flash_pkg_exit: 2504 mutex_unlock(&bp->hwrm_cmd_lock); 2505 err_exit: 2506 if (rc == -EACCES) 2507 bnxt_print_admin_err(bp); 2508 return rc; 2509 } 2510 2511 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 2512 u32 install_type) 2513 { 2514 const struct firmware *fw; 2515 int rc; 2516 2517 rc = request_firmware(&fw, filename, &dev->dev); 2518 if (rc != 0) { 2519 netdev_err(dev, "PKG error %d requesting file: %s\n", 2520 rc, filename); 2521 return rc; 2522 } 2523 2524 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type); 2525 2526 release_firmware(fw); 2527 2528 return rc; 2529 } 2530 2531 static int bnxt_flash_device(struct net_device *dev, 2532 struct ethtool_flash *flash) 2533 { 2534 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 2535 netdev_err(dev, "flashdev not supported from a virtual function\n"); 2536 return -EINVAL; 2537 } 2538 2539 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 2540 flash->region > 0xffff) 2541 return bnxt_flash_package_from_file(dev, flash->data, 2542 flash->region); 2543 2544 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 2545 } 2546 2547 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 2548 { 2549 struct bnxt *bp = netdev_priv(dev); 2550 int rc; 2551 struct hwrm_nvm_get_dir_info_input req = {0}; 2552 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr; 2553 2554 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1); 2555 2556 mutex_lock(&bp->hwrm_cmd_lock); 2557 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2558 if (!rc) { 2559 *entries = le32_to_cpu(output->entries); 2560 *length = le32_to_cpu(output->entry_length); 2561 } 2562 mutex_unlock(&bp->hwrm_cmd_lock); 2563 return rc; 2564 } 2565 2566 static int bnxt_get_eeprom_len(struct net_device *dev) 2567 { 2568 struct bnxt *bp = netdev_priv(dev); 2569 2570 if (BNXT_VF(bp)) 2571 return 0; 2572 2573 /* The -1 return value allows the entire 32-bit range of offsets to be 2574 * passed via the ethtool command-line utility. 2575 */ 2576 return -1; 2577 } 2578 2579 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 2580 { 2581 struct bnxt *bp = netdev_priv(dev); 2582 int rc; 2583 u32 dir_entries; 2584 u32 entry_length; 2585 u8 *buf; 2586 size_t buflen; 2587 dma_addr_t dma_handle; 2588 struct hwrm_nvm_get_dir_entries_input req = {0}; 2589 2590 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 2591 if (rc != 0) 2592 return rc; 2593 2594 if (!dir_entries || !entry_length) 2595 return -EIO; 2596 2597 /* Insert 2 bytes of directory info (count and size of entries) */ 2598 if (len < 2) 2599 return -EINVAL; 2600 2601 *data++ = dir_entries; 2602 *data++ = entry_length; 2603 len -= 2; 2604 memset(data, 0xff, len); 2605 2606 buflen = dir_entries * entry_length; 2607 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle, 2608 GFP_KERNEL); 2609 if (!buf) { 2610 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2611 (unsigned)buflen); 2612 return -ENOMEM; 2613 } 2614 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1); 2615 req.host_dest_addr = cpu_to_le64(dma_handle); 2616 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2617 if (rc == 0) 2618 memcpy(data, buf, len > buflen ? buflen : len); 2619 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle); 2620 return rc; 2621 } 2622 2623 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 2624 u32 length, u8 *data) 2625 { 2626 struct bnxt *bp = netdev_priv(dev); 2627 int rc; 2628 u8 *buf; 2629 dma_addr_t dma_handle; 2630 struct hwrm_nvm_read_input req = {0}; 2631 2632 if (!length) 2633 return -EINVAL; 2634 2635 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle, 2636 GFP_KERNEL); 2637 if (!buf) { 2638 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n", 2639 (unsigned)length); 2640 return -ENOMEM; 2641 } 2642 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1); 2643 req.host_dest_addr = cpu_to_le64(dma_handle); 2644 req.dir_idx = cpu_to_le16(index); 2645 req.offset = cpu_to_le32(offset); 2646 req.len = cpu_to_le32(length); 2647 2648 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2649 if (rc == 0) 2650 memcpy(data, buf, length); 2651 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle); 2652 return rc; 2653 } 2654 2655 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2656 u16 ext, u16 *index, u32 *item_length, 2657 u32 *data_length) 2658 { 2659 struct bnxt *bp = netdev_priv(dev); 2660 int rc; 2661 struct hwrm_nvm_find_dir_entry_input req = {0}; 2662 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr; 2663 2664 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1); 2665 req.enables = 0; 2666 req.dir_idx = 0; 2667 req.dir_type = cpu_to_le16(type); 2668 req.dir_ordinal = cpu_to_le16(ordinal); 2669 req.dir_ext = cpu_to_le16(ext); 2670 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 2671 mutex_lock(&bp->hwrm_cmd_lock); 2672 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2673 if (rc == 0) { 2674 if (index) 2675 *index = le16_to_cpu(output->dir_idx); 2676 if (item_length) 2677 *item_length = le32_to_cpu(output->dir_item_length); 2678 if (data_length) 2679 *data_length = le32_to_cpu(output->dir_data_length); 2680 } 2681 mutex_unlock(&bp->hwrm_cmd_lock); 2682 return rc; 2683 } 2684 2685 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 2686 { 2687 char *retval = NULL; 2688 char *p; 2689 char *value; 2690 int field = 0; 2691 2692 if (datalen < 1) 2693 return NULL; 2694 /* null-terminate the log data (removing last '\n'): */ 2695 data[datalen - 1] = 0; 2696 for (p = data; *p != 0; p++) { 2697 field = 0; 2698 retval = NULL; 2699 while (*p != 0 && *p != '\n') { 2700 value = p; 2701 while (*p != 0 && *p != '\t' && *p != '\n') 2702 p++; 2703 if (field == desired_field) 2704 retval = value; 2705 if (*p != '\t') 2706 break; 2707 *p = 0; 2708 field++; 2709 p++; 2710 } 2711 if (*p == 0) 2712 break; 2713 *p = 0; 2714 } 2715 return retval; 2716 } 2717 2718 static void bnxt_get_pkgver(struct net_device *dev) 2719 { 2720 struct bnxt *bp = netdev_priv(dev); 2721 u16 index = 0; 2722 char *pkgver; 2723 u32 pkglen; 2724 u8 *pkgbuf; 2725 int len; 2726 2727 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 2728 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 2729 &index, NULL, &pkglen) != 0) 2730 return; 2731 2732 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 2733 if (!pkgbuf) { 2734 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 2735 pkglen); 2736 return; 2737 } 2738 2739 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf)) 2740 goto err; 2741 2742 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 2743 pkglen); 2744 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) { 2745 len = strlen(bp->fw_ver_str); 2746 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 2747 "/pkg %s", pkgver); 2748 } 2749 err: 2750 kfree(pkgbuf); 2751 } 2752 2753 static int bnxt_get_eeprom(struct net_device *dev, 2754 struct ethtool_eeprom *eeprom, 2755 u8 *data) 2756 { 2757 u32 index; 2758 u32 offset; 2759 2760 if (eeprom->offset == 0) /* special offset value to get directory */ 2761 return bnxt_get_nvram_directory(dev, eeprom->len, data); 2762 2763 index = eeprom->offset >> 24; 2764 offset = eeprom->offset & 0xffffff; 2765 2766 if (index == 0) { 2767 netdev_err(dev, "unsupported index value: %d\n", index); 2768 return -EINVAL; 2769 } 2770 2771 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 2772 } 2773 2774 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 2775 { 2776 struct bnxt *bp = netdev_priv(dev); 2777 struct hwrm_nvm_erase_dir_entry_input req = {0}; 2778 2779 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1); 2780 req.dir_idx = cpu_to_le16(index); 2781 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 2782 } 2783 2784 static int bnxt_set_eeprom(struct net_device *dev, 2785 struct ethtool_eeprom *eeprom, 2786 u8 *data) 2787 { 2788 struct bnxt *bp = netdev_priv(dev); 2789 u8 index, dir_op; 2790 u16 type, ext, ordinal, attr; 2791 2792 if (!BNXT_PF(bp)) { 2793 netdev_err(dev, "NVM write not supported from a virtual function\n"); 2794 return -EINVAL; 2795 } 2796 2797 type = eeprom->magic >> 16; 2798 2799 if (type == 0xffff) { /* special value for directory operations */ 2800 index = eeprom->magic & 0xff; 2801 dir_op = eeprom->magic >> 8; 2802 if (index == 0) 2803 return -EINVAL; 2804 switch (dir_op) { 2805 case 0x0e: /* erase */ 2806 if (eeprom->offset != ~eeprom->magic) 2807 return -EINVAL; 2808 return bnxt_erase_nvram_directory(dev, index - 1); 2809 default: 2810 return -EINVAL; 2811 } 2812 } 2813 2814 /* Create or re-write an NVM item: */ 2815 if (bnxt_dir_type_is_executable(type)) 2816 return -EOPNOTSUPP; 2817 ext = eeprom->magic & 0xffff; 2818 ordinal = eeprom->offset >> 16; 2819 attr = eeprom->offset & 0xffff; 2820 2821 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data, 2822 eeprom->len); 2823 } 2824 2825 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2826 { 2827 struct bnxt *bp = netdev_priv(dev); 2828 struct ethtool_eee *eee = &bp->eee; 2829 struct bnxt_link_info *link_info = &bp->link_info; 2830 u32 advertising; 2831 int rc = 0; 2832 2833 if (!BNXT_PHY_CFG_ABLE(bp)) 2834 return -EOPNOTSUPP; 2835 2836 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2837 return -EOPNOTSUPP; 2838 2839 mutex_lock(&bp->link_lock); 2840 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 2841 if (!edata->eee_enabled) 2842 goto eee_ok; 2843 2844 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2845 netdev_warn(dev, "EEE requires autoneg\n"); 2846 rc = -EINVAL; 2847 goto eee_exit; 2848 } 2849 if (edata->tx_lpi_enabled) { 2850 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 2851 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 2852 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 2853 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 2854 rc = -EINVAL; 2855 goto eee_exit; 2856 } else if (!bp->lpi_tmr_hi) { 2857 edata->tx_lpi_timer = eee->tx_lpi_timer; 2858 } 2859 } 2860 if (!edata->advertised) { 2861 edata->advertised = advertising & eee->supported; 2862 } else if (edata->advertised & ~advertising) { 2863 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 2864 edata->advertised, advertising); 2865 rc = -EINVAL; 2866 goto eee_exit; 2867 } 2868 2869 eee->advertised = edata->advertised; 2870 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 2871 eee->tx_lpi_timer = edata->tx_lpi_timer; 2872 eee_ok: 2873 eee->eee_enabled = edata->eee_enabled; 2874 2875 if (netif_running(dev)) 2876 rc = bnxt_hwrm_set_link_setting(bp, false, true); 2877 2878 eee_exit: 2879 mutex_unlock(&bp->link_lock); 2880 return rc; 2881 } 2882 2883 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2884 { 2885 struct bnxt *bp = netdev_priv(dev); 2886 2887 if (!(bp->flags & BNXT_FLAG_EEE_CAP)) 2888 return -EOPNOTSUPP; 2889 2890 *edata = bp->eee; 2891 if (!bp->eee.eee_enabled) { 2892 /* Preserve tx_lpi_timer so that the last value will be used 2893 * by default when it is re-enabled. 2894 */ 2895 edata->advertised = 0; 2896 edata->tx_lpi_enabled = 0; 2897 } 2898 2899 if (!bp->eee.eee_active) 2900 edata->lp_advertised = 0; 2901 2902 return 0; 2903 } 2904 2905 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 2906 u16 page_number, u16 start_addr, 2907 u16 data_length, u8 *buf) 2908 { 2909 struct hwrm_port_phy_i2c_read_input req = {0}; 2910 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr; 2911 int rc, byte_offset = 0; 2912 2913 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1); 2914 req.i2c_slave_addr = i2c_addr; 2915 req.page_number = cpu_to_le16(page_number); 2916 req.port_id = cpu_to_le16(bp->pf.port_id); 2917 do { 2918 u16 xfer_size; 2919 2920 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 2921 data_length -= xfer_size; 2922 req.page_offset = cpu_to_le16(start_addr + byte_offset); 2923 req.data_length = xfer_size; 2924 req.enables = cpu_to_le32(start_addr + byte_offset ? 2925 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 2926 mutex_lock(&bp->hwrm_cmd_lock); 2927 rc = _hwrm_send_message(bp, &req, sizeof(req), 2928 HWRM_CMD_TIMEOUT); 2929 if (!rc) 2930 memcpy(buf + byte_offset, output->data, xfer_size); 2931 mutex_unlock(&bp->hwrm_cmd_lock); 2932 byte_offset += xfer_size; 2933 } while (!rc && data_length > 0); 2934 2935 return rc; 2936 } 2937 2938 static int bnxt_get_module_info(struct net_device *dev, 2939 struct ethtool_modinfo *modinfo) 2940 { 2941 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 2942 struct bnxt *bp = netdev_priv(dev); 2943 int rc; 2944 2945 /* No point in going further if phy status indicates 2946 * module is not inserted or if it is powered down or 2947 * if it is of type 10GBase-T 2948 */ 2949 if (bp->link_info.module_status > 2950 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 2951 return -EOPNOTSUPP; 2952 2953 /* This feature is not supported in older firmware versions */ 2954 if (bp->hwrm_spec_code < 0x10202) 2955 return -EOPNOTSUPP; 2956 2957 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 2958 SFF_DIAG_SUPPORT_OFFSET + 1, 2959 data); 2960 if (!rc) { 2961 u8 module_id = data[0]; 2962 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 2963 2964 switch (module_id) { 2965 case SFF_MODULE_ID_SFP: 2966 modinfo->type = ETH_MODULE_SFF_8472; 2967 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2968 if (!diag_supported) 2969 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2970 break; 2971 case SFF_MODULE_ID_QSFP: 2972 case SFF_MODULE_ID_QSFP_PLUS: 2973 modinfo->type = ETH_MODULE_SFF_8436; 2974 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2975 break; 2976 case SFF_MODULE_ID_QSFP28: 2977 modinfo->type = ETH_MODULE_SFF_8636; 2978 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2979 break; 2980 default: 2981 rc = -EOPNOTSUPP; 2982 break; 2983 } 2984 } 2985 return rc; 2986 } 2987 2988 static int bnxt_get_module_eeprom(struct net_device *dev, 2989 struct ethtool_eeprom *eeprom, 2990 u8 *data) 2991 { 2992 struct bnxt *bp = netdev_priv(dev); 2993 u16 start = eeprom->offset, length = eeprom->len; 2994 int rc = 0; 2995 2996 memset(data, 0, eeprom->len); 2997 2998 /* Read A0 portion of the EEPROM */ 2999 if (start < ETH_MODULE_SFF_8436_LEN) { 3000 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3001 length = ETH_MODULE_SFF_8436_LEN - start; 3002 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3003 start, length, data); 3004 if (rc) 3005 return rc; 3006 start += length; 3007 data += length; 3008 length = eeprom->len - length; 3009 } 3010 3011 /* Read A2 portion of the EEPROM */ 3012 if (length) { 3013 start -= ETH_MODULE_SFF_8436_LEN; 3014 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 3015 start, length, data); 3016 } 3017 return rc; 3018 } 3019 3020 static int bnxt_nway_reset(struct net_device *dev) 3021 { 3022 int rc = 0; 3023 3024 struct bnxt *bp = netdev_priv(dev); 3025 struct bnxt_link_info *link_info = &bp->link_info; 3026 3027 if (!BNXT_PHY_CFG_ABLE(bp)) 3028 return -EOPNOTSUPP; 3029 3030 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3031 return -EINVAL; 3032 3033 if (netif_running(dev)) 3034 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3035 3036 return rc; 3037 } 3038 3039 static int bnxt_set_phys_id(struct net_device *dev, 3040 enum ethtool_phys_id_state state) 3041 { 3042 struct hwrm_port_led_cfg_input req = {0}; 3043 struct bnxt *bp = netdev_priv(dev); 3044 struct bnxt_pf_info *pf = &bp->pf; 3045 struct bnxt_led_cfg *led_cfg; 3046 u8 led_state; 3047 __le16 duration; 3048 int i; 3049 3050 if (!bp->num_leds || BNXT_VF(bp)) 3051 return -EOPNOTSUPP; 3052 3053 if (state == ETHTOOL_ID_ACTIVE) { 3054 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3055 duration = cpu_to_le16(500); 3056 } else if (state == ETHTOOL_ID_INACTIVE) { 3057 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3058 duration = cpu_to_le16(0); 3059 } else { 3060 return -EINVAL; 3061 } 3062 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1); 3063 req.port_id = cpu_to_le16(pf->port_id); 3064 req.num_leds = bp->num_leds; 3065 led_cfg = (struct bnxt_led_cfg *)&req.led0_id; 3066 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3067 req.enables |= BNXT_LED_DFLT_ENABLES(i); 3068 led_cfg->led_id = bp->leds[i].led_id; 3069 led_cfg->led_state = led_state; 3070 led_cfg->led_blink_on = duration; 3071 led_cfg->led_blink_off = duration; 3072 led_cfg->led_group_id = bp->leds[i].led_group_id; 3073 } 3074 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3075 } 3076 3077 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3078 { 3079 struct hwrm_selftest_irq_input req = {0}; 3080 3081 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1); 3082 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3083 } 3084 3085 static int bnxt_test_irq(struct bnxt *bp) 3086 { 3087 int i; 3088 3089 for (i = 0; i < bp->cp_nr_rings; i++) { 3090 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3091 int rc; 3092 3093 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3094 if (rc) 3095 return rc; 3096 } 3097 return 0; 3098 } 3099 3100 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3101 { 3102 struct hwrm_port_mac_cfg_input req = {0}; 3103 3104 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); 3105 3106 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3107 if (enable) 3108 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3109 else 3110 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3111 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3112 } 3113 3114 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3115 { 3116 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 3117 struct hwrm_port_phy_qcaps_input req = {0}; 3118 int rc; 3119 3120 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1); 3121 mutex_lock(&bp->hwrm_cmd_lock); 3122 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3123 if (!rc) 3124 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3125 3126 mutex_unlock(&bp->hwrm_cmd_lock); 3127 return rc; 3128 } 3129 3130 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3131 struct hwrm_port_phy_cfg_input *req) 3132 { 3133 struct bnxt_link_info *link_info = &bp->link_info; 3134 u16 fw_advertising; 3135 u16 fw_speed; 3136 int rc; 3137 3138 if (!link_info->autoneg || 3139 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK)) 3140 return 0; 3141 3142 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3143 if (rc) 3144 return rc; 3145 3146 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3147 if (bp->link_info.link_up) 3148 fw_speed = bp->link_info.link_speed; 3149 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3150 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3151 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3152 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3153 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3154 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3155 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3156 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3157 3158 req->force_link_speed = cpu_to_le16(fw_speed); 3159 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3160 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3161 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT); 3162 req->flags = 0; 3163 req->force_link_speed = cpu_to_le16(0); 3164 return rc; 3165 } 3166 3167 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3168 { 3169 struct hwrm_port_phy_cfg_input req = {0}; 3170 3171 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); 3172 3173 if (enable) { 3174 bnxt_disable_an_for_lpbk(bp, &req); 3175 if (ext) 3176 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3177 else 3178 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3179 } else { 3180 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3181 } 3182 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3183 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3184 } 3185 3186 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3187 u32 raw_cons, int pkt_size) 3188 { 3189 struct bnxt_napi *bnapi = cpr->bnapi; 3190 struct bnxt_rx_ring_info *rxr; 3191 struct bnxt_sw_rx_bd *rx_buf; 3192 struct rx_cmp *rxcmp; 3193 u16 cp_cons, cons; 3194 u8 *data; 3195 u32 len; 3196 int i; 3197 3198 rxr = bnapi->rx_ring; 3199 cp_cons = RING_CMP(raw_cons); 3200 rxcmp = (struct rx_cmp *) 3201 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3202 cons = rxcmp->rx_cmp_opaque; 3203 rx_buf = &rxr->rx_buf_ring[cons]; 3204 data = rx_buf->data_ptr; 3205 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3206 if (len != pkt_size) 3207 return -EIO; 3208 i = ETH_ALEN; 3209 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3210 return -EIO; 3211 i += ETH_ALEN; 3212 for ( ; i < pkt_size; i++) { 3213 if (data[i] != (u8)(i & 0xff)) 3214 return -EIO; 3215 } 3216 return 0; 3217 } 3218 3219 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3220 int pkt_size) 3221 { 3222 struct tx_cmp *txcmp; 3223 int rc = -EIO; 3224 u32 raw_cons; 3225 u32 cons; 3226 int i; 3227 3228 raw_cons = cpr->cp_raw_cons; 3229 for (i = 0; i < 200; i++) { 3230 cons = RING_CMP(raw_cons); 3231 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3232 3233 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3234 udelay(5); 3235 continue; 3236 } 3237 3238 /* The valid test of the entry must be done first before 3239 * reading any further. 3240 */ 3241 dma_rmb(); 3242 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3243 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3244 raw_cons = NEXT_RAW_CMP(raw_cons); 3245 raw_cons = NEXT_RAW_CMP(raw_cons); 3246 break; 3247 } 3248 raw_cons = NEXT_RAW_CMP(raw_cons); 3249 } 3250 cpr->cp_raw_cons = raw_cons; 3251 return rc; 3252 } 3253 3254 static int bnxt_run_loopback(struct bnxt *bp) 3255 { 3256 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3257 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3258 struct bnxt_cp_ring_info *cpr; 3259 int pkt_size, i = 0; 3260 struct sk_buff *skb; 3261 dma_addr_t map; 3262 u8 *data; 3263 int rc; 3264 3265 cpr = &rxr->bnapi->cp_ring; 3266 if (bp->flags & BNXT_FLAG_CHIP_P5) 3267 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3268 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3269 skb = netdev_alloc_skb(bp->dev, pkt_size); 3270 if (!skb) 3271 return -ENOMEM; 3272 data = skb_put(skb, pkt_size); 3273 eth_broadcast_addr(data); 3274 i += ETH_ALEN; 3275 ether_addr_copy(&data[i], bp->dev->dev_addr); 3276 i += ETH_ALEN; 3277 for ( ; i < pkt_size; i++) 3278 data[i] = (u8)(i & 0xff); 3279 3280 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3281 PCI_DMA_TODEVICE); 3282 if (dma_mapping_error(&bp->pdev->dev, map)) { 3283 dev_kfree_skb(skb); 3284 return -EIO; 3285 } 3286 bnxt_xmit_bd(bp, txr, map, pkt_size); 3287 3288 /* Sync BD data before updating doorbell */ 3289 wmb(); 3290 3291 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3292 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3293 3294 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 3295 dev_kfree_skb(skb); 3296 return rc; 3297 } 3298 3299 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3300 { 3301 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr; 3302 struct hwrm_selftest_exec_input req = {0}; 3303 int rc; 3304 3305 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1); 3306 mutex_lock(&bp->hwrm_cmd_lock); 3307 resp->test_success = 0; 3308 req.flags = test_mask; 3309 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout); 3310 *test_results = resp->test_success; 3311 mutex_unlock(&bp->hwrm_cmd_lock); 3312 return rc; 3313 } 3314 3315 #define BNXT_DRV_TESTS 4 3316 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3317 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3318 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 3319 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 3320 3321 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 3322 u64 *buf) 3323 { 3324 struct bnxt *bp = netdev_priv(dev); 3325 bool do_ext_lpbk = false; 3326 bool offline = false; 3327 u8 test_results = 0; 3328 u8 test_mask = 0; 3329 int rc = 0, i; 3330 3331 if (!bp->num_tests || !BNXT_PF(bp)) 3332 return; 3333 memset(buf, 0, sizeof(u64) * bp->num_tests); 3334 if (!netif_running(dev)) { 3335 etest->flags |= ETH_TEST_FL_FAILED; 3336 return; 3337 } 3338 3339 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 3340 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK)) 3341 do_ext_lpbk = true; 3342 3343 if (etest->flags & ETH_TEST_FL_OFFLINE) { 3344 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 3345 etest->flags |= ETH_TEST_FL_FAILED; 3346 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 3347 return; 3348 } 3349 offline = true; 3350 } 3351 3352 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3353 u8 bit_val = 1 << i; 3354 3355 if (!(bp->test_info->offline_mask & bit_val)) 3356 test_mask |= bit_val; 3357 else if (offline) 3358 test_mask |= bit_val; 3359 } 3360 if (!offline) { 3361 bnxt_run_fw_tests(bp, test_mask, &test_results); 3362 } else { 3363 rc = bnxt_close_nic(bp, false, false); 3364 if (rc) 3365 return; 3366 bnxt_run_fw_tests(bp, test_mask, &test_results); 3367 3368 buf[BNXT_MACLPBK_TEST_IDX] = 1; 3369 bnxt_hwrm_mac_loopback(bp, true); 3370 msleep(250); 3371 rc = bnxt_half_open_nic(bp); 3372 if (rc) { 3373 bnxt_hwrm_mac_loopback(bp, false); 3374 etest->flags |= ETH_TEST_FL_FAILED; 3375 return; 3376 } 3377 if (bnxt_run_loopback(bp)) 3378 etest->flags |= ETH_TEST_FL_FAILED; 3379 else 3380 buf[BNXT_MACLPBK_TEST_IDX] = 0; 3381 3382 bnxt_hwrm_mac_loopback(bp, false); 3383 bnxt_hwrm_phy_loopback(bp, true, false); 3384 msleep(1000); 3385 if (bnxt_run_loopback(bp)) { 3386 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 3387 etest->flags |= ETH_TEST_FL_FAILED; 3388 } 3389 if (do_ext_lpbk) { 3390 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3391 bnxt_hwrm_phy_loopback(bp, true, true); 3392 msleep(1000); 3393 if (bnxt_run_loopback(bp)) { 3394 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 3395 etest->flags |= ETH_TEST_FL_FAILED; 3396 } 3397 } 3398 bnxt_hwrm_phy_loopback(bp, false, false); 3399 bnxt_half_close_nic(bp); 3400 rc = bnxt_open_nic(bp, false, true); 3401 } 3402 if (rc || bnxt_test_irq(bp)) { 3403 buf[BNXT_IRQ_TEST_IDX] = 1; 3404 etest->flags |= ETH_TEST_FL_FAILED; 3405 } 3406 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 3407 u8 bit_val = 1 << i; 3408 3409 if ((test_mask & bit_val) && !(test_results & bit_val)) { 3410 buf[i] = 1; 3411 etest->flags |= ETH_TEST_FL_FAILED; 3412 } 3413 } 3414 } 3415 3416 static int bnxt_reset(struct net_device *dev, u32 *flags) 3417 { 3418 struct bnxt *bp = netdev_priv(dev); 3419 bool reload = false; 3420 u32 req = *flags; 3421 3422 if (!req) 3423 return -EINVAL; 3424 3425 if (!BNXT_PF(bp)) { 3426 netdev_err(dev, "Reset is not supported from a VF\n"); 3427 return -EOPNOTSUPP; 3428 } 3429 3430 if (pci_vfs_assigned(bp->pdev) && 3431 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 3432 netdev_err(dev, 3433 "Reset not allowed when VFs are assigned to VMs\n"); 3434 return -EBUSY; 3435 } 3436 3437 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 3438 /* This feature is not supported in older firmware versions */ 3439 if (bp->hwrm_spec_code >= 0x10803) { 3440 if (!bnxt_firmware_reset_chip(dev)) { 3441 netdev_info(dev, "Firmware reset request successful.\n"); 3442 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 3443 reload = true; 3444 *flags &= ~BNXT_FW_RESET_CHIP; 3445 } 3446 } else if (req == BNXT_FW_RESET_CHIP) { 3447 return -EOPNOTSUPP; /* only request, fail hard */ 3448 } 3449 } 3450 3451 if (req & BNXT_FW_RESET_AP) { 3452 /* This feature is not supported in older firmware versions */ 3453 if (bp->hwrm_spec_code >= 0x10803) { 3454 if (!bnxt_firmware_reset_ap(dev)) { 3455 netdev_info(dev, "Reset application processor successful.\n"); 3456 reload = true; 3457 *flags &= ~BNXT_FW_RESET_AP; 3458 } 3459 } else if (req == BNXT_FW_RESET_AP) { 3460 return -EOPNOTSUPP; /* only request, fail hard */ 3461 } 3462 } 3463 3464 if (reload) 3465 netdev_info(dev, "Reload driver to complete reset\n"); 3466 3467 return 0; 3468 } 3469 3470 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len, 3471 struct bnxt_hwrm_dbg_dma_info *info) 3472 { 3473 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr; 3474 struct hwrm_dbg_cmn_input *cmn_req = msg; 3475 __le16 *seq_ptr = msg + info->seq_off; 3476 u16 seq = 0, len, segs_off; 3477 void *resp = cmn_resp; 3478 dma_addr_t dma_handle; 3479 int rc, off = 0; 3480 void *dma_buf; 3481 3482 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle, 3483 GFP_KERNEL); 3484 if (!dma_buf) 3485 return -ENOMEM; 3486 3487 segs_off = offsetof(struct hwrm_dbg_coredump_list_output, 3488 total_segments); 3489 cmn_req->host_dest_addr = cpu_to_le64(dma_handle); 3490 cmn_req->host_buf_len = cpu_to_le32(info->dma_len); 3491 mutex_lock(&bp->hwrm_cmd_lock); 3492 while (1) { 3493 *seq_ptr = cpu_to_le16(seq); 3494 rc = _hwrm_send_message(bp, msg, msg_len, 3495 HWRM_COREDUMP_TIMEOUT); 3496 if (rc) 3497 break; 3498 3499 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off))); 3500 if (!seq && 3501 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) { 3502 info->segs = le16_to_cpu(*((__le16 *)(resp + 3503 segs_off))); 3504 if (!info->segs) { 3505 rc = -EIO; 3506 break; 3507 } 3508 3509 info->dest_buf_size = info->segs * 3510 sizeof(struct coredump_segment_record); 3511 info->dest_buf = kmalloc(info->dest_buf_size, 3512 GFP_KERNEL); 3513 if (!info->dest_buf) { 3514 rc = -ENOMEM; 3515 break; 3516 } 3517 } 3518 3519 if (info->dest_buf) { 3520 if ((info->seg_start + off + len) <= 3521 BNXT_COREDUMP_BUF_LEN(info->buf_len)) { 3522 memcpy(info->dest_buf + off, dma_buf, len); 3523 } else { 3524 rc = -ENOBUFS; 3525 break; 3526 } 3527 } 3528 3529 if (cmn_req->req_type == 3530 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE)) 3531 info->dest_buf_size += len; 3532 3533 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE)) 3534 break; 3535 3536 seq++; 3537 off += len; 3538 } 3539 mutex_unlock(&bp->hwrm_cmd_lock); 3540 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle); 3541 return rc; 3542 } 3543 3544 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp, 3545 struct bnxt_coredump *coredump) 3546 { 3547 struct hwrm_dbg_coredump_list_input req = {0}; 3548 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3549 int rc; 3550 3551 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1); 3552 3553 info.dma_len = COREDUMP_LIST_BUF_LEN; 3554 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no); 3555 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output, 3556 data_len); 3557 3558 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3559 if (!rc) { 3560 coredump->data = info.dest_buf; 3561 coredump->data_size = info.dest_buf_size; 3562 coredump->total_segs = info.segs; 3563 } 3564 return rc; 3565 } 3566 3567 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id, 3568 u16 segment_id) 3569 { 3570 struct hwrm_dbg_coredump_initiate_input req = {0}; 3571 3572 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1); 3573 req.component_id = cpu_to_le16(component_id); 3574 req.segment_id = cpu_to_le16(segment_id); 3575 3576 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT); 3577 } 3578 3579 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id, 3580 u16 segment_id, u32 *seg_len, 3581 void *buf, u32 buf_len, u32 offset) 3582 { 3583 struct hwrm_dbg_coredump_retrieve_input req = {0}; 3584 struct bnxt_hwrm_dbg_dma_info info = {NULL}; 3585 int rc; 3586 3587 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1); 3588 req.component_id = cpu_to_le16(component_id); 3589 req.segment_id = cpu_to_le16(segment_id); 3590 3591 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN; 3592 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input, 3593 seq_no); 3594 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output, 3595 data_len); 3596 if (buf) { 3597 info.dest_buf = buf + offset; 3598 info.buf_len = buf_len; 3599 info.seg_start = offset; 3600 } 3601 3602 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info); 3603 if (!rc) 3604 *seg_len = info.dest_buf_size; 3605 3606 return rc; 3607 } 3608 3609 static void 3610 bnxt_fill_coredump_seg_hdr(struct bnxt *bp, 3611 struct bnxt_coredump_segment_hdr *seg_hdr, 3612 struct coredump_segment_record *seg_rec, u32 seg_len, 3613 int status, u32 duration, u32 instance) 3614 { 3615 memset(seg_hdr, 0, sizeof(*seg_hdr)); 3616 memcpy(seg_hdr->signature, "sEgM", 4); 3617 if (seg_rec) { 3618 seg_hdr->component_id = (__force __le32)seg_rec->component_id; 3619 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id; 3620 seg_hdr->low_version = seg_rec->version_low; 3621 seg_hdr->high_version = seg_rec->version_hi; 3622 } else { 3623 /* For hwrm_ver_get response Component id = 2 3624 * and Segment id = 0 3625 */ 3626 seg_hdr->component_id = cpu_to_le32(2); 3627 seg_hdr->segment_id = 0; 3628 } 3629 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn); 3630 seg_hdr->length = cpu_to_le32(seg_len); 3631 seg_hdr->status = cpu_to_le32(status); 3632 seg_hdr->duration = cpu_to_le32(duration); 3633 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr)); 3634 seg_hdr->instance = cpu_to_le32(instance); 3635 } 3636 3637 static void 3638 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record, 3639 time64_t start, s16 start_utc, u16 total_segs, 3640 int status) 3641 { 3642 time64_t end = ktime_get_real_seconds(); 3643 u32 os_ver_major = 0, os_ver_minor = 0; 3644 struct tm tm; 3645 3646 time64_to_tm(start, 0, &tm); 3647 memset(record, 0, sizeof(*record)); 3648 memcpy(record->signature, "cOrE", 4); 3649 record->flags = 0; 3650 record->low_version = 0; 3651 record->high_version = 1; 3652 record->asic_state = 0; 3653 strlcpy(record->system_name, utsname()->nodename, 3654 sizeof(record->system_name)); 3655 record->year = cpu_to_le16(tm.tm_year + 1900); 3656 record->month = cpu_to_le16(tm.tm_mon + 1); 3657 record->day = cpu_to_le16(tm.tm_mday); 3658 record->hour = cpu_to_le16(tm.tm_hour); 3659 record->minute = cpu_to_le16(tm.tm_min); 3660 record->second = cpu_to_le16(tm.tm_sec); 3661 record->utc_bias = cpu_to_le16(start_utc); 3662 strcpy(record->commandline, "ethtool -w"); 3663 record->total_segments = cpu_to_le32(total_segs); 3664 3665 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor); 3666 record->os_ver_major = cpu_to_le32(os_ver_major); 3667 record->os_ver_minor = cpu_to_le32(os_ver_minor); 3668 3669 strlcpy(record->os_name, utsname()->sysname, 32); 3670 time64_to_tm(end, 0, &tm); 3671 record->end_year = cpu_to_le16(tm.tm_year + 1900); 3672 record->end_month = cpu_to_le16(tm.tm_mon + 1); 3673 record->end_day = cpu_to_le16(tm.tm_mday); 3674 record->end_hour = cpu_to_le16(tm.tm_hour); 3675 record->end_minute = cpu_to_le16(tm.tm_min); 3676 record->end_second = cpu_to_le16(tm.tm_sec); 3677 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60); 3678 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 | 3679 bp->ver_resp.chip_rev << 8 | 3680 bp->ver_resp.chip_metal); 3681 record->asic_id2 = 0; 3682 record->coredump_status = cpu_to_le32(status); 3683 record->ioctl_low_version = 0; 3684 record->ioctl_high_version = 0; 3685 } 3686 3687 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len) 3688 { 3689 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output); 3690 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0; 3691 struct coredump_segment_record *seg_record = NULL; 3692 struct bnxt_coredump_segment_hdr seg_hdr; 3693 struct bnxt_coredump coredump = {NULL}; 3694 time64_t start_time; 3695 u16 start_utc; 3696 int rc = 0, i; 3697 3698 if (buf) 3699 buf_len = *dump_len; 3700 3701 start_time = ktime_get_real_seconds(); 3702 start_utc = sys_tz.tz_minuteswest * 60; 3703 seg_hdr_len = sizeof(seg_hdr); 3704 3705 /* First segment should be hwrm_ver_get response */ 3706 *dump_len = seg_hdr_len + ver_get_resp_len; 3707 if (buf) { 3708 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len, 3709 0, 0, 0); 3710 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3711 offset += seg_hdr_len; 3712 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len); 3713 offset += ver_get_resp_len; 3714 } 3715 3716 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump); 3717 if (rc) { 3718 netdev_err(bp->dev, "Failed to get coredump segment list\n"); 3719 goto err; 3720 } 3721 3722 *dump_len += seg_hdr_len * coredump.total_segs; 3723 3724 seg_record = (struct coredump_segment_record *)coredump.data; 3725 seg_record_len = sizeof(*seg_record); 3726 3727 for (i = 0; i < coredump.total_segs; i++) { 3728 u16 comp_id = le16_to_cpu(seg_record->component_id); 3729 u16 seg_id = le16_to_cpu(seg_record->segment_id); 3730 u32 duration = 0, seg_len = 0; 3731 unsigned long start, end; 3732 3733 if (buf && ((offset + seg_hdr_len) > 3734 BNXT_COREDUMP_BUF_LEN(buf_len))) { 3735 rc = -ENOBUFS; 3736 goto err; 3737 } 3738 3739 start = jiffies; 3740 3741 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id); 3742 if (rc) { 3743 netdev_err(bp->dev, 3744 "Failed to initiate coredump for seg = %d\n", 3745 seg_record->segment_id); 3746 goto next_seg; 3747 } 3748 3749 /* Write segment data into the buffer */ 3750 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id, 3751 &seg_len, buf, buf_len, 3752 offset + seg_hdr_len); 3753 if (rc && rc == -ENOBUFS) 3754 goto err; 3755 else if (rc) 3756 netdev_err(bp->dev, 3757 "Failed to retrieve coredump for seg = %d\n", 3758 seg_record->segment_id); 3759 3760 next_seg: 3761 end = jiffies; 3762 duration = jiffies_to_msecs(end - start); 3763 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len, 3764 rc, duration, 0); 3765 3766 if (buf) { 3767 /* Write segment header into the buffer */ 3768 memcpy(buf + offset, &seg_hdr, seg_hdr_len); 3769 offset += seg_hdr_len + seg_len; 3770 } 3771 3772 *dump_len += seg_len; 3773 seg_record = 3774 (struct coredump_segment_record *)((u8 *)seg_record + 3775 seg_record_len); 3776 } 3777 3778 err: 3779 if (buf) 3780 bnxt_fill_coredump_record(bp, buf + offset, start_time, 3781 start_utc, coredump.total_segs + 1, 3782 rc); 3783 kfree(coredump.data); 3784 *dump_len += sizeof(struct bnxt_coredump_record); 3785 if (rc == -ENOBUFS) 3786 netdev_err(bp->dev, "Firmware returned large coredump buffer\n"); 3787 return rc; 3788 } 3789 3790 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 3791 { 3792 struct bnxt *bp = netdev_priv(dev); 3793 3794 if (dump->flag > BNXT_DUMP_CRASH) { 3795 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 3796 return -EINVAL; 3797 } 3798 3799 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 3800 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 3801 return -EOPNOTSUPP; 3802 } 3803 3804 bp->dump_flag = dump->flag; 3805 return 0; 3806 } 3807 3808 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 3809 { 3810 struct bnxt *bp = netdev_priv(dev); 3811 3812 if (bp->hwrm_spec_code < 0x10801) 3813 return -EOPNOTSUPP; 3814 3815 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 3816 bp->ver_resp.hwrm_fw_min_8b << 16 | 3817 bp->ver_resp.hwrm_fw_bld_8b << 8 | 3818 bp->ver_resp.hwrm_fw_rsvd_8b; 3819 3820 dump->flag = bp->dump_flag; 3821 if (bp->dump_flag == BNXT_DUMP_CRASH) 3822 dump->len = BNXT_CRASH_DUMP_LEN; 3823 else 3824 bnxt_get_coredump(bp, NULL, &dump->len); 3825 return 0; 3826 } 3827 3828 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 3829 void *buf) 3830 { 3831 struct bnxt *bp = netdev_priv(dev); 3832 3833 if (bp->hwrm_spec_code < 0x10801) 3834 return -EOPNOTSUPP; 3835 3836 memset(buf, 0, dump->len); 3837 3838 dump->flag = bp->dump_flag; 3839 if (dump->flag == BNXT_DUMP_CRASH) { 3840 #ifdef CONFIG_TEE_BNXT_FW 3841 return tee_bnxt_copy_coredump(buf, 0, dump->len); 3842 #endif 3843 } else { 3844 return bnxt_get_coredump(bp, buf, &dump->len); 3845 } 3846 3847 return 0; 3848 } 3849 3850 void bnxt_ethtool_init(struct bnxt *bp) 3851 { 3852 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3853 struct hwrm_selftest_qlist_input req = {0}; 3854 struct bnxt_test_info *test_info; 3855 struct net_device *dev = bp->dev; 3856 int i, rc; 3857 3858 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 3859 bnxt_get_pkgver(dev); 3860 3861 bp->num_tests = 0; 3862 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 3863 return; 3864 3865 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1); 3866 mutex_lock(&bp->hwrm_cmd_lock); 3867 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3868 if (rc) 3869 goto ethtool_init_exit; 3870 3871 test_info = bp->test_info; 3872 if (!test_info) 3873 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 3874 if (!test_info) 3875 goto ethtool_init_exit; 3876 3877 bp->test_info = test_info; 3878 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 3879 if (bp->num_tests > BNXT_MAX_TEST) 3880 bp->num_tests = BNXT_MAX_TEST; 3881 3882 test_info->offline_mask = resp->offline_tests; 3883 test_info->timeout = le16_to_cpu(resp->test_timeout); 3884 if (!test_info->timeout) 3885 test_info->timeout = HWRM_CMD_TIMEOUT; 3886 for (i = 0; i < bp->num_tests; i++) { 3887 char *str = test_info->string[i]; 3888 char *fw_str = resp->test0_name + i * 32; 3889 3890 if (i == BNXT_MACLPBK_TEST_IDX) { 3891 strcpy(str, "Mac loopback test (offline)"); 3892 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3893 strcpy(str, "Phy loopback test (offline)"); 3894 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 3895 strcpy(str, "Ext loopback test (offline)"); 3896 } else if (i == BNXT_IRQ_TEST_IDX) { 3897 strcpy(str, "Interrupt_test (offline)"); 3898 } else { 3899 strlcpy(str, fw_str, ETH_GSTRING_LEN); 3900 strncat(str, " test", ETH_GSTRING_LEN - strlen(str)); 3901 if (test_info->offline_mask & (1 << i)) 3902 strncat(str, " (offline)", 3903 ETH_GSTRING_LEN - strlen(str)); 3904 else 3905 strncat(str, " (online)", 3906 ETH_GSTRING_LEN - strlen(str)); 3907 } 3908 } 3909 3910 ethtool_init_exit: 3911 mutex_unlock(&bp->hwrm_cmd_lock); 3912 } 3913 3914 void bnxt_ethtool_free(struct bnxt *bp) 3915 { 3916 kfree(bp->test_info); 3917 bp->test_info = NULL; 3918 } 3919 3920 const struct ethtool_ops bnxt_ethtool_ops = { 3921 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 3922 ETHTOOL_COALESCE_MAX_FRAMES | 3923 ETHTOOL_COALESCE_USECS_IRQ | 3924 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 3925 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 3926 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 3927 .get_link_ksettings = bnxt_get_link_ksettings, 3928 .set_link_ksettings = bnxt_set_link_ksettings, 3929 .get_fecparam = bnxt_get_fecparam, 3930 .set_fecparam = bnxt_set_fecparam, 3931 .get_pause_stats = bnxt_get_pause_stats, 3932 .get_pauseparam = bnxt_get_pauseparam, 3933 .set_pauseparam = bnxt_set_pauseparam, 3934 .get_drvinfo = bnxt_get_drvinfo, 3935 .get_regs_len = bnxt_get_regs_len, 3936 .get_regs = bnxt_get_regs, 3937 .get_wol = bnxt_get_wol, 3938 .set_wol = bnxt_set_wol, 3939 .get_coalesce = bnxt_get_coalesce, 3940 .set_coalesce = bnxt_set_coalesce, 3941 .get_msglevel = bnxt_get_msglevel, 3942 .set_msglevel = bnxt_set_msglevel, 3943 .get_sset_count = bnxt_get_sset_count, 3944 .get_strings = bnxt_get_strings, 3945 .get_ethtool_stats = bnxt_get_ethtool_stats, 3946 .set_ringparam = bnxt_set_ringparam, 3947 .get_ringparam = bnxt_get_ringparam, 3948 .get_channels = bnxt_get_channels, 3949 .set_channels = bnxt_set_channels, 3950 .get_rxnfc = bnxt_get_rxnfc, 3951 .set_rxnfc = bnxt_set_rxnfc, 3952 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 3953 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 3954 .get_rxfh = bnxt_get_rxfh, 3955 .set_rxfh = bnxt_set_rxfh, 3956 .flash_device = bnxt_flash_device, 3957 .get_eeprom_len = bnxt_get_eeprom_len, 3958 .get_eeprom = bnxt_get_eeprom, 3959 .set_eeprom = bnxt_set_eeprom, 3960 .get_link = bnxt_get_link, 3961 .get_eee = bnxt_get_eee, 3962 .set_eee = bnxt_set_eee, 3963 .get_module_info = bnxt_get_module_info, 3964 .get_module_eeprom = bnxt_get_module_eeprom, 3965 .nway_reset = bnxt_nway_reset, 3966 .set_phys_id = bnxt_set_phys_id, 3967 .self_test = bnxt_self_test, 3968 .reset = bnxt_reset, 3969 .set_dump = bnxt_set_dump, 3970 .get_dump_flag = bnxt_get_dump_flag, 3971 .get_dump_data = bnxt_get_dump_data, 3972 }; 3973