1 /* bnx2x_sriov.c: QLogic Everest network driver.
2  *
3  * Copyright 2009-2013 Broadcom Corporation
4  * Copyright 2014 QLogic Corporation
5  * All rights reserved
6  *
7  * Unless you and QLogic execute a separate written software license
8  * agreement governing use of this software, this software is licensed to you
9  * under the terms of the GNU General Public License version 2, available
10  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
11  *
12  * Notwithstanding the above, under no circumstances may you combine this
13  * software in any way with any other QLogic software provided under a
14  * license other than the GPL, without QLogic's express prior written
15  * consent.
16  *
17  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
18  * Written by: Shmulik Ravid
19  *	       Ariel Elior <ariel.elior@qlogic.com>
20  *
21  */
22 #include "bnx2x.h"
23 #include "bnx2x_init.h"
24 #include "bnx2x_cmn.h"
25 #include "bnx2x_sp.h"
26 #include <linux/crc32.h>
27 #include <linux/if_vlan.h>
28 
29 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx,
30 			    struct bnx2x_virtf **vf,
31 			    struct pf_vf_bulletin_content **bulletin,
32 			    bool test_queue);
33 
34 /* General service functions */
35 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
36 					 u16 pf_id)
37 {
38 	REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
39 		pf_id);
40 	REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
41 		pf_id);
42 	REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
43 		pf_id);
44 	REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
45 		pf_id);
46 }
47 
48 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
49 					u8 enable)
50 {
51 	REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
52 		enable);
53 	REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
54 		enable);
55 	REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
56 		enable);
57 	REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
58 		enable);
59 }
60 
61 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
62 {
63 	int idx;
64 
65 	for_each_vf(bp, idx)
66 		if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid)
67 			break;
68 	return idx;
69 }
70 
71 static
72 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
73 {
74 	u16 idx =  (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid);
75 	return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL;
76 }
77 
78 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf,
79 				u8 igu_sb_id, u8 segment, u16 index, u8 op,
80 				u8 update)
81 {
82 	/* acking a VF sb through the PF - use the GRC */
83 	u32 ctl;
84 	u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
85 	u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
86 	u32 func_encode = vf->abs_vfid;
87 	u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id;
88 	struct igu_regular cmd_data = {0};
89 
90 	cmd_data.sb_id_and_flags =
91 			((index << IGU_REGULAR_SB_INDEX_SHIFT) |
92 			 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
93 			 (update << IGU_REGULAR_BUPDATE_SHIFT) |
94 			 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
95 
96 	ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT		|
97 	      func_encode << IGU_CTRL_REG_FID_SHIFT		|
98 	      IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
99 
100 	DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
101 	   cmd_data.sb_id_and_flags, igu_addr_data);
102 	REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags);
103 	mmiowb();
104 	barrier();
105 
106 	DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
107 	   ctl, igu_addr_ctl);
108 	REG_WR(bp, igu_addr_ctl, ctl);
109 	mmiowb();
110 	barrier();
111 }
112 
113 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp,
114 				       struct bnx2x_virtf *vf,
115 				       bool print_err)
116 {
117 	if (!bnx2x_leading_vfq(vf, sp_initialized)) {
118 		if (print_err)
119 			BNX2X_ERR("Slowpath objects not yet initialized!\n");
120 		else
121 			DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n");
122 		return false;
123 	}
124 	return true;
125 }
126 
127 /* VFOP operations states */
128 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf,
129 			      struct bnx2x_queue_init_params *init_params,
130 			      struct bnx2x_queue_setup_params *setup_params,
131 			      u16 q_idx, u16 sb_idx)
132 {
133 	DP(BNX2X_MSG_IOV,
134 	   "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d",
135 	   vf->abs_vfid,
136 	   q_idx,
137 	   sb_idx,
138 	   init_params->tx.sb_cq_index,
139 	   init_params->tx.hc_rate,
140 	   setup_params->flags,
141 	   setup_params->txq_params.traffic_type);
142 }
143 
144 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf,
145 			    struct bnx2x_queue_init_params *init_params,
146 			    struct bnx2x_queue_setup_params *setup_params,
147 			    u16 q_idx, u16 sb_idx)
148 {
149 	struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params;
150 
151 	DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n"
152 	   "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n",
153 	   vf->abs_vfid,
154 	   q_idx,
155 	   sb_idx,
156 	   init_params->rx.sb_cq_index,
157 	   init_params->rx.hc_rate,
158 	   setup_params->gen_params.mtu,
159 	   rxq_params->buf_sz,
160 	   rxq_params->sge_buf_sz,
161 	   rxq_params->max_sges_pkt,
162 	   rxq_params->tpa_agg_sz,
163 	   setup_params->flags,
164 	   rxq_params->drop_flags,
165 	   rxq_params->cache_line_log);
166 }
167 
168 void bnx2x_vfop_qctor_prep(struct bnx2x *bp,
169 			   struct bnx2x_virtf *vf,
170 			   struct bnx2x_vf_queue *q,
171 			   struct bnx2x_vf_queue_construct_params *p,
172 			   unsigned long q_type)
173 {
174 	struct bnx2x_queue_init_params *init_p = &p->qstate.params.init;
175 	struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup;
176 
177 	/* INIT */
178 
179 	/* Enable host coalescing in the transition to INIT state */
180 	if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags))
181 		__set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags);
182 
183 	if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags))
184 		__set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags);
185 
186 	/* FW SB ID */
187 	init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
188 	init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
189 
190 	/* context */
191 	init_p->cxts[0] = q->cxt;
192 
193 	/* SETUP */
194 
195 	/* Setup-op general parameters */
196 	setup_p->gen_params.spcl_id = vf->sp_cl_id;
197 	setup_p->gen_params.stat_id = vfq_stat_id(vf, q);
198 	setup_p->gen_params.fp_hsi = vf->fp_hsi;
199 
200 	/* Setup-op flags:
201 	 * collect statistics, zero statistics, local-switching, security,
202 	 * OV for Flex10, RSS and MCAST for leading
203 	 */
204 	if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags))
205 		__set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags);
206 
207 	/* for VFs, enable tx switching, bd coherency, and mac address
208 	 * anti-spoofing
209 	 */
210 	__set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags);
211 	__set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags);
212 	if (vf->spoofchk)
213 		__set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags);
214 	else
215 		__clear_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags);
216 
217 	/* Setup-op rx parameters */
218 	if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) {
219 		struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params;
220 
221 		rxq_p->cl_qzone_id = vfq_qzone_id(vf, q);
222 		rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx);
223 		rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid);
224 
225 		if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags))
226 			rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES;
227 	}
228 
229 	/* Setup-op tx parameters */
230 	if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) {
231 		setup_p->txq_params.tss_leading_cl_id = vf->leading_rss;
232 		setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
233 	}
234 }
235 
236 static int bnx2x_vf_queue_create(struct bnx2x *bp,
237 				 struct bnx2x_virtf *vf, int qid,
238 				 struct bnx2x_vf_queue_construct_params *qctor)
239 {
240 	struct bnx2x_queue_state_params *q_params;
241 	int rc = 0;
242 
243 	DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
244 
245 	/* Prepare ramrod information */
246 	q_params = &qctor->qstate;
247 	q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj);
248 	set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags);
249 
250 	if (bnx2x_get_q_logical_state(bp, q_params->q_obj) ==
251 	    BNX2X_Q_LOGICAL_STATE_ACTIVE) {
252 		DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n");
253 		goto out;
254 	}
255 
256 	/* Run Queue 'construction' ramrods */
257 	q_params->cmd = BNX2X_Q_CMD_INIT;
258 	rc = bnx2x_queue_state_change(bp, q_params);
259 	if (rc)
260 		goto out;
261 
262 	memcpy(&q_params->params.setup, &qctor->prep_qsetup,
263 	       sizeof(struct bnx2x_queue_setup_params));
264 	q_params->cmd = BNX2X_Q_CMD_SETUP;
265 	rc = bnx2x_queue_state_change(bp, q_params);
266 	if (rc)
267 		goto out;
268 
269 	/* enable interrupts */
270 	bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)),
271 			    USTORM_ID, 0, IGU_INT_ENABLE, 0);
272 out:
273 	return rc;
274 }
275 
276 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf,
277 				  int qid)
278 {
279 	enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT,
280 				       BNX2X_Q_CMD_TERMINATE,
281 				       BNX2X_Q_CMD_CFC_DEL};
282 	struct bnx2x_queue_state_params q_params;
283 	int rc, i;
284 
285 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
286 
287 	/* Prepare ramrod information */
288 	memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params));
289 	q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
290 	set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
291 
292 	if (bnx2x_get_q_logical_state(bp, q_params.q_obj) ==
293 	    BNX2X_Q_LOGICAL_STATE_STOPPED) {
294 		DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n");
295 		goto out;
296 	}
297 
298 	/* Run Queue 'destruction' ramrods */
299 	for (i = 0; i < ARRAY_SIZE(cmds); i++) {
300 		q_params.cmd = cmds[i];
301 		rc = bnx2x_queue_state_change(bp, &q_params);
302 		if (rc) {
303 			BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]);
304 			return rc;
305 		}
306 	}
307 out:
308 	/* Clean Context */
309 	if (bnx2x_vfq(vf, qid, cxt)) {
310 		bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0;
311 		bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0;
312 	}
313 
314 	return 0;
315 }
316 
317 static void
318 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid)
319 {
320 	struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
321 	if (vf) {
322 		/* the first igu entry belonging to VFs of this PF */
323 		if (!BP_VFDB(bp)->first_vf_igu_entry)
324 			BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id;
325 
326 		/* the first igu entry belonging to this VF */
327 		if (!vf_sb_count(vf))
328 			vf->igu_base_id = igu_sb_id;
329 
330 		++vf_sb_count(vf);
331 		++vf->sb_count;
332 	}
333 	BP_VFDB(bp)->vf_sbs_pool++;
334 }
335 
336 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp,
337 					struct bnx2x_vlan_mac_obj *obj,
338 					atomic_t *counter)
339 {
340 	struct list_head *pos;
341 	int read_lock;
342 	int cnt = 0;
343 
344 	read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj);
345 	if (read_lock)
346 		DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n");
347 
348 	list_for_each(pos, &obj->head)
349 		cnt++;
350 
351 	if (!read_lock)
352 		bnx2x_vlan_mac_h_read_unlock(bp, obj);
353 
354 	atomic_set(counter, cnt);
355 }
356 
357 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf,
358 				   int qid, bool drv_only, int type)
359 {
360 	struct bnx2x_vlan_mac_ramrod_params ramrod;
361 	int rc;
362 
363 	DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid,
364 			  (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" :
365 			  (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs");
366 
367 	/* Prepare ramrod params */
368 	memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params));
369 	if (type == BNX2X_VF_FILTER_VLAN_MAC) {
370 		set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
371 		ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj);
372 	} else if (type == BNX2X_VF_FILTER_MAC) {
373 		set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
374 		ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
375 	} else {
376 		ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
377 	}
378 	ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL;
379 
380 	set_bit(RAMROD_EXEC, &ramrod.ramrod_flags);
381 	if (drv_only)
382 		set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags);
383 	else
384 		set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
385 
386 	/* Start deleting */
387 	rc = ramrod.vlan_mac_obj->delete_all(bp,
388 					     ramrod.vlan_mac_obj,
389 					     &ramrod.user_req.vlan_mac_flags,
390 					     &ramrod.ramrod_flags);
391 	if (rc) {
392 		BNX2X_ERR("Failed to delete all %s\n",
393 			  (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" :
394 			  (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs");
395 		return rc;
396 	}
397 
398 	return 0;
399 }
400 
401 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp,
402 				    struct bnx2x_virtf *vf, int qid,
403 				    struct bnx2x_vf_mac_vlan_filter *filter,
404 				    bool drv_only)
405 {
406 	struct bnx2x_vlan_mac_ramrod_params ramrod;
407 	int rc;
408 
409 	DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n",
410 	   vf->abs_vfid, filter->add ? "Adding" : "Deleting",
411 	   (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MAC" :
412 	   (filter->type == BNX2X_VF_FILTER_MAC) ? "MAC" : "VLAN");
413 
414 	/* Prepare ramrod params */
415 	memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params));
416 	if (filter->type == BNX2X_VF_FILTER_VLAN_MAC) {
417 		ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj);
418 		ramrod.user_req.u.vlan.vlan = filter->vid;
419 		memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN);
420 		set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
421 	} else if (filter->type == BNX2X_VF_FILTER_VLAN) {
422 		ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
423 		ramrod.user_req.u.vlan.vlan = filter->vid;
424 	} else {
425 		set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
426 		ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
427 		memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN);
428 	}
429 	ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD :
430 					    BNX2X_VLAN_MAC_DEL;
431 
432 	set_bit(RAMROD_EXEC, &ramrod.ramrod_flags);
433 	if (drv_only)
434 		set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags);
435 	else
436 		set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
437 
438 	/* Add/Remove the filter */
439 	rc = bnx2x_config_vlan_mac(bp, &ramrod);
440 	if (rc == -EEXIST)
441 		return 0;
442 	if (rc) {
443 		BNX2X_ERR("Failed to %s %s\n",
444 			  filter->add ? "add" : "delete",
445 			  (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ?
446 				"VLAN-MAC" :
447 			  (filter->type == BNX2X_VF_FILTER_MAC) ?
448 				"MAC" : "VLAN");
449 		return rc;
450 	}
451 
452 	filter->applied = true;
453 
454 	return 0;
455 }
456 
457 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf,
458 				  struct bnx2x_vf_mac_vlan_filters *filters,
459 				  int qid, bool drv_only)
460 {
461 	int rc = 0, i;
462 
463 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
464 
465 	if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
466 		return -EINVAL;
467 
468 	/* Prepare ramrod params */
469 	for (i = 0; i < filters->count; i++) {
470 		rc = bnx2x_vf_mac_vlan_config(bp, vf, qid,
471 					      &filters->filters[i], drv_only);
472 		if (rc)
473 			break;
474 	}
475 
476 	/* Rollback if needed */
477 	if (i != filters->count) {
478 		BNX2X_ERR("Managed only %d/%d filters - rolling back\n",
479 			  i, filters->count);
480 		while (--i >= 0) {
481 			if (!filters->filters[i].applied)
482 				continue;
483 			filters->filters[i].add = !filters->filters[i].add;
484 			bnx2x_vf_mac_vlan_config(bp, vf, qid,
485 						 &filters->filters[i],
486 						 drv_only);
487 		}
488 	}
489 
490 	/* It's our responsibility to free the filters */
491 	kfree(filters);
492 
493 	return rc;
494 }
495 
496 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid,
497 			 struct bnx2x_vf_queue_construct_params *qctor)
498 {
499 	int rc;
500 
501 	DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
502 
503 	rc = bnx2x_vf_queue_create(bp, vf, qid, qctor);
504 	if (rc)
505 		goto op_err;
506 
507 	/* Schedule the configuration of any pending vlan filters */
508 	bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN,
509 			       BNX2X_MSG_IOV);
510 	return 0;
511 op_err:
512 	BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc);
513 	return rc;
514 }
515 
516 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf,
517 			       int qid)
518 {
519 	int rc;
520 
521 	DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
522 
523 	/* If needed, clean the filtering data base */
524 	if ((qid == LEADING_IDX) &&
525 	    bnx2x_validate_vf_sp_objs(bp, vf, false)) {
526 		rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
527 					     BNX2X_VF_FILTER_VLAN_MAC);
528 		if (rc)
529 			goto op_err;
530 		rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
531 					     BNX2X_VF_FILTER_VLAN);
532 		if (rc)
533 			goto op_err;
534 		rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
535 					     BNX2X_VF_FILTER_MAC);
536 		if (rc)
537 			goto op_err;
538 	}
539 
540 	/* Terminate queue */
541 	if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) {
542 		struct bnx2x_queue_state_params qstate;
543 
544 		memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params));
545 		qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
546 		qstate.q_obj->state = BNX2X_Q_STATE_STOPPED;
547 		qstate.cmd = BNX2X_Q_CMD_TERMINATE;
548 		set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags);
549 		rc = bnx2x_queue_state_change(bp, &qstate);
550 		if (rc)
551 			goto op_err;
552 	}
553 
554 	return 0;
555 op_err:
556 	BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc);
557 	return rc;
558 }
559 
560 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf,
561 		   bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only)
562 {
563 	struct bnx2x_mcast_list_elem *mc = NULL;
564 	struct bnx2x_mcast_ramrod_params mcast;
565 	int rc, i;
566 
567 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
568 
569 	/* Prepare Multicast command */
570 	memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params));
571 	mcast.mcast_obj = &vf->mcast_obj;
572 	if (drv_only)
573 		set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags);
574 	else
575 		set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags);
576 	if (mc_num) {
577 		mc = kcalloc(mc_num, sizeof(struct bnx2x_mcast_list_elem),
578 			     GFP_KERNEL);
579 		if (!mc) {
580 			BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n");
581 			return -ENOMEM;
582 		}
583 	}
584 
585 	if (mc_num) {
586 		INIT_LIST_HEAD(&mcast.mcast_list);
587 		for (i = 0; i < mc_num; i++) {
588 			mc[i].mac = mcasts[i];
589 			list_add_tail(&mc[i].link,
590 				      &mcast.mcast_list);
591 		}
592 
593 		/* add new mcasts */
594 		mcast.mcast_list_len = mc_num;
595 		rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_SET);
596 		if (rc)
597 			BNX2X_ERR("Failed to set multicasts\n");
598 	} else {
599 		/* clear existing mcasts */
600 		rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL);
601 		if (rc)
602 			BNX2X_ERR("Failed to remove multicasts\n");
603 	}
604 
605 	kfree(mc);
606 
607 	return rc;
608 }
609 
610 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid,
611 				  struct bnx2x_rx_mode_ramrod_params *ramrod,
612 				  struct bnx2x_virtf *vf,
613 				  unsigned long accept_flags)
614 {
615 	struct bnx2x_vf_queue *vfq = vfq_get(vf, qid);
616 
617 	memset(ramrod, 0, sizeof(*ramrod));
618 	ramrod->cid = vfq->cid;
619 	ramrod->cl_id = vfq_cl_id(vf, vfq);
620 	ramrod->rx_mode_obj = &bp->rx_mode_obj;
621 	ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid);
622 	ramrod->rx_accept_flags = accept_flags;
623 	ramrod->tx_accept_flags = accept_flags;
624 	ramrod->pstate = &vf->filter_state;
625 	ramrod->state = BNX2X_FILTER_RX_MODE_PENDING;
626 
627 	set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
628 	set_bit(RAMROD_RX, &ramrod->ramrod_flags);
629 	set_bit(RAMROD_TX, &ramrod->ramrod_flags);
630 
631 	ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2);
632 	ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2);
633 }
634 
635 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf,
636 		    int qid, unsigned long accept_flags)
637 {
638 	struct bnx2x_rx_mode_ramrod_params ramrod;
639 
640 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
641 
642 	bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags);
643 	set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
644 	vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags;
645 	return bnx2x_config_rx_mode(bp, &ramrod);
646 }
647 
648 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid)
649 {
650 	int rc;
651 
652 	DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
653 
654 	/* Remove all classification configuration for leading queue */
655 	if (qid == LEADING_IDX) {
656 		rc = bnx2x_vf_rxmode(bp, vf, qid, 0);
657 		if (rc)
658 			goto op_err;
659 
660 		/* Remove filtering if feasible */
661 		if (bnx2x_validate_vf_sp_objs(bp, vf, true)) {
662 			rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
663 						     false,
664 						     BNX2X_VF_FILTER_VLAN_MAC);
665 			if (rc)
666 				goto op_err;
667 			rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
668 						     false,
669 						     BNX2X_VF_FILTER_VLAN);
670 			if (rc)
671 				goto op_err;
672 			rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
673 						     false,
674 						     BNX2X_VF_FILTER_MAC);
675 			if (rc)
676 				goto op_err;
677 			rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false);
678 			if (rc)
679 				goto op_err;
680 		}
681 	}
682 
683 	/* Destroy queue */
684 	rc = bnx2x_vf_queue_destroy(bp, vf, qid);
685 	if (rc)
686 		goto op_err;
687 	return rc;
688 op_err:
689 	BNX2X_ERR("vf[%d:%d] error: rc %d\n",
690 		  vf->abs_vfid, qid, rc);
691 	return rc;
692 }
693 
694 /* VF enable primitives
695  * when pretend is required the caller is responsible
696  * for calling pretend prior to calling these routines
697  */
698 
699 /* internal vf enable - until vf is enabled internally all transactions
700  * are blocked. This routine should always be called last with pretend.
701  */
702 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable)
703 {
704 	REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);
705 }
706 
707 /* clears vf error in all semi blocks */
708 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid)
709 {
710 	REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);
711 	REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);
712 	REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);
713 	REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);
714 }
715 
716 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid)
717 {
718 	u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5;
719 	u32 was_err_reg = 0;
720 
721 	switch (was_err_group) {
722 	case 0:
723 	    was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR;
724 	    break;
725 	case 1:
726 	    was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR;
727 	    break;
728 	case 2:
729 	    was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR;
730 	    break;
731 	case 3:
732 	    was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR;
733 	    break;
734 	}
735 	REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));
736 }
737 
738 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf)
739 {
740 	int i;
741 	u32 val;
742 
743 	/* Set VF masks and configuration - pretend */
744 	bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
745 
746 	REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
747 	REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
748 	REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
749 	REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
750 	REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
751 	REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
752 
753 	val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
754 	val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN);
755 	val &= ~IGU_VF_CONF_PARENT_MASK;
756 	val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT;
757 	REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
758 
759 	DP(BNX2X_MSG_IOV,
760 	   "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n",
761 	   vf->abs_vfid, val);
762 
763 	bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
764 
765 	/* iterate over all queues, clear sb consumer */
766 	for (i = 0; i < vf_sb_count(vf); i++) {
767 		u8 igu_sb_id = vf_igu_sb(vf, i);
768 
769 		/* zero prod memory */
770 		REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0);
771 
772 		/* clear sb state machine */
773 		bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id,
774 				       false /* VF */);
775 
776 		/* disable + update */
777 		bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0,
778 				    IGU_INT_DISABLE, 1);
779 	}
780 }
781 
782 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid)
783 {
784 	/* set the VF-PF association in the FW */
785 	storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp));
786 	storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1);
787 
788 	/* clear vf errors*/
789 	bnx2x_vf_semi_clear_err(bp, abs_vfid);
790 	bnx2x_vf_pglue_clear_err(bp, abs_vfid);
791 
792 	/* internal vf-enable - pretend */
793 	bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid));
794 	DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid);
795 	bnx2x_vf_enable_internal(bp, true);
796 	bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
797 }
798 
799 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf)
800 {
801 	/* Reset vf in IGU  interrupts are still disabled */
802 	bnx2x_vf_igu_reset(bp, vf);
803 
804 	/* pretend to enable the vf with the PBF */
805 	bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
806 	REG_WR(bp, PBF_REG_DISABLE_VF, 0);
807 	bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
808 }
809 
810 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid)
811 {
812 	struct pci_dev *dev;
813 	struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
814 
815 	if (!vf)
816 		return false;
817 
818 	dev = pci_get_domain_bus_and_slot(vf->domain, vf->bus, vf->devfn);
819 	if (dev)
820 		return bnx2x_is_pcie_pending(dev);
821 	return false;
822 }
823 
824 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid)
825 {
826 	/* Verify no pending pci transactions */
827 	if (bnx2x_vf_is_pcie_pending(bp, abs_vfid))
828 		BNX2X_ERR("PCIE Transactions still pending\n");
829 
830 	return 0;
831 }
832 
833 /* must be called after the number of PF queues and the number of VFs are
834  * both known
835  */
836 static void
837 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
838 {
839 	struct vf_pf_resc_request *resc = &vf->alloc_resc;
840 
841 	/* will be set only during VF-ACQUIRE */
842 	resc->num_rxqs = 0;
843 	resc->num_txqs = 0;
844 
845 	resc->num_mac_filters = VF_MAC_CREDIT_CNT;
846 	resc->num_vlan_filters = VF_VLAN_CREDIT_CNT;
847 
848 	/* no real limitation */
849 	resc->num_mc_filters = 0;
850 
851 	/* num_sbs already set */
852 	resc->num_sbs = vf->sb_count;
853 }
854 
855 /* FLR routines: */
856 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
857 {
858 	/* reset the state variables */
859 	bnx2x_iov_static_resc(bp, vf);
860 	vf->state = VF_FREE;
861 }
862 
863 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf)
864 {
865 	u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
866 
867 	/* DQ usage counter */
868 	bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
869 	bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT,
870 					"DQ VF usage counter timed out",
871 					poll_cnt);
872 	bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
873 
874 	/* FW cleanup command - poll for the results */
875 	if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid),
876 				   poll_cnt))
877 		BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid);
878 
879 	/* verify TX hw is flushed */
880 	bnx2x_tx_hw_flushed(bp, poll_cnt);
881 }
882 
883 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf)
884 {
885 	int rc, i;
886 
887 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
888 
889 	/* the cleanup operations are valid if and only if the VF
890 	 * was first acquired.
891 	 */
892 	for (i = 0; i < vf_rxq_count(vf); i++) {
893 		rc = bnx2x_vf_queue_flr(bp, vf, i);
894 		if (rc)
895 			goto out;
896 	}
897 
898 	/* remove multicasts */
899 	bnx2x_vf_mcast(bp, vf, NULL, 0, true);
900 
901 	/* dispatch final cleanup and wait for HW queues to flush */
902 	bnx2x_vf_flr_clnup_hw(bp, vf);
903 
904 	/* release VF resources */
905 	bnx2x_vf_free_resc(bp, vf);
906 
907 	vf->malicious = false;
908 
909 	/* re-open the mailbox */
910 	bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
911 	return;
912 out:
913 	BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n",
914 		  vf->abs_vfid, i, rc);
915 }
916 
917 static void bnx2x_vf_flr_clnup(struct bnx2x *bp)
918 {
919 	struct bnx2x_virtf *vf;
920 	int i;
921 
922 	for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) {
923 		/* VF should be RESET & in FLR cleanup states */
924 		if (bnx2x_vf(bp, i, state) != VF_RESET ||
925 		    !bnx2x_vf(bp, i, flr_clnup_stage))
926 			continue;
927 
928 		DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n",
929 		   i, BNX2X_NR_VIRTFN(bp));
930 
931 		vf = BP_VF(bp, i);
932 
933 		/* lock the vf pf channel */
934 		bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
935 
936 		/* invoke the VF FLR SM */
937 		bnx2x_vf_flr(bp, vf);
938 
939 		/* mark the VF to be ACKED and continue */
940 		vf->flr_clnup_stage = false;
941 		bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
942 	}
943 
944 	/* Acknowledge the handled VFs.
945 	 * we are acknowledge all the vfs which an flr was requested for, even
946 	 * if amongst them there are such that we never opened, since the mcp
947 	 * will interrupt us immediately again if we only ack some of the bits,
948 	 * resulting in an endless loop. This can happen for example in KVM
949 	 * where an 'all ones' flr request is sometimes given by hyper visor
950 	 */
951 	DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n",
952 	   bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
953 	for (i = 0; i < FLRD_VFS_DWORDS; i++)
954 		SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i],
955 			  bp->vfdb->flrd_vfs[i]);
956 
957 	bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0);
958 
959 	/* clear the acked bits - better yet if the MCP implemented
960 	 * write to clear semantics
961 	 */
962 	for (i = 0; i < FLRD_VFS_DWORDS; i++)
963 		SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0);
964 }
965 
966 void bnx2x_vf_handle_flr_event(struct bnx2x *bp)
967 {
968 	int i;
969 
970 	/* Read FLR'd VFs */
971 	for (i = 0; i < FLRD_VFS_DWORDS; i++)
972 		bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]);
973 
974 	DP(BNX2X_MSG_MCP,
975 	   "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n",
976 	   bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
977 
978 	for_each_vf(bp, i) {
979 		struct bnx2x_virtf *vf = BP_VF(bp, i);
980 		u32 reset = 0;
981 
982 		if (vf->abs_vfid < 32)
983 			reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid);
984 		else
985 			reset = bp->vfdb->flrd_vfs[1] &
986 				(1 << (vf->abs_vfid - 32));
987 
988 		if (reset) {
989 			/* set as reset and ready for cleanup */
990 			vf->state = VF_RESET;
991 			vf->flr_clnup_stage = true;
992 
993 			DP(BNX2X_MSG_IOV,
994 			   "Initiating Final cleanup for VF %d\n",
995 			   vf->abs_vfid);
996 		}
997 	}
998 
999 	/* do the FLR cleanup for all marked VFs*/
1000 	bnx2x_vf_flr_clnup(bp);
1001 }
1002 
1003 /* IOV global initialization routines  */
1004 void bnx2x_iov_init_dq(struct bnx2x *bp)
1005 {
1006 	if (!IS_SRIOV(bp))
1007 		return;
1008 
1009 	/* Set the DQ such that the CID reflect the abs_vfid */
1010 	REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);
1011 	REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
1012 
1013 	/* Set VFs starting CID. If its > 0 the preceding CIDs are belong to
1014 	 * the PF L2 queues
1015 	 */
1016 	REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
1017 
1018 	/* The VF window size is the log2 of the max number of CIDs per VF */
1019 	REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
1020 
1021 	/* The VF doorbell size  0 - *B, 4 - 128B. We set it here to match
1022 	 * the Pf doorbell size although the 2 are independent.
1023 	 */
1024 	REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3);
1025 
1026 	/* No security checks for now -
1027 	 * configure single rule (out of 16) mask = 0x1, value = 0x0,
1028 	 * CID range 0 - 0x1ffff
1029 	 */
1030 	REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);
1031 	REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);
1032 	REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
1033 	REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
1034 
1035 	/* set the VF doorbell threshold. This threshold represents the amount
1036 	 * of doorbells allowed in the main DORQ fifo for a specific VF.
1037 	 */
1038 	REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64);
1039 }
1040 
1041 void bnx2x_iov_init_dmae(struct bnx2x *bp)
1042 {
1043 	if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV))
1044 		REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
1045 }
1046 
1047 static int bnx2x_vf_domain(struct bnx2x *bp, int vfid)
1048 {
1049 	struct pci_dev *dev = bp->pdev;
1050 
1051 	return pci_domain_nr(dev->bus);
1052 }
1053 
1054 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
1055 {
1056 	struct pci_dev *dev = bp->pdev;
1057 	struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1058 
1059 	return dev->bus->number + ((dev->devfn + iov->offset +
1060 				    iov->stride * vfid) >> 8);
1061 }
1062 
1063 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid)
1064 {
1065 	struct pci_dev *dev = bp->pdev;
1066 	struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1067 
1068 	return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff;
1069 }
1070 
1071 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf)
1072 {
1073 	int i, n;
1074 	struct pci_dev *dev = bp->pdev;
1075 	struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1076 
1077 	for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) {
1078 		u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i);
1079 		u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i);
1080 
1081 		size /= iov->total;
1082 		vf->bars[n].bar = start + size * vf->abs_vfid;
1083 		vf->bars[n].size = size;
1084 	}
1085 }
1086 
1087 static int
1088 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
1089 {
1090 	int sb_id;
1091 	u32 val;
1092 	u8 fid, current_pf = 0;
1093 
1094 	/* IGU in normal mode - read CAM */
1095 	for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) {
1096 		val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4);
1097 		if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
1098 			continue;
1099 		fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
1100 		if (fid & IGU_FID_ENCODE_IS_PF)
1101 			current_pf = fid & IGU_FID_PF_NUM_MASK;
1102 		else if (current_pf == BP_FUNC(bp))
1103 			bnx2x_vf_set_igu_info(bp, sb_id,
1104 					      (fid & IGU_FID_VF_NUM_MASK));
1105 		DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
1106 		   ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"),
1107 		   ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) :
1108 		   (fid & IGU_FID_VF_NUM_MASK)), sb_id,
1109 		   GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR));
1110 	}
1111 	DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool);
1112 	return BP_VFDB(bp)->vf_sbs_pool;
1113 }
1114 
1115 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp)
1116 {
1117 	if (bp->vfdb) {
1118 		kfree(bp->vfdb->vfqs);
1119 		kfree(bp->vfdb->vfs);
1120 		kfree(bp->vfdb);
1121 	}
1122 	bp->vfdb = NULL;
1123 }
1124 
1125 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
1126 {
1127 	int pos;
1128 	struct pci_dev *dev = bp->pdev;
1129 
1130 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
1131 	if (!pos) {
1132 		BNX2X_ERR("failed to find SRIOV capability in device\n");
1133 		return -ENODEV;
1134 	}
1135 
1136 	iov->pos = pos;
1137 	DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos);
1138 	pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
1139 	pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total);
1140 	pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial);
1141 	pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
1142 	pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
1143 	pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
1144 	pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
1145 	pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
1146 
1147 	return 0;
1148 }
1149 
1150 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
1151 {
1152 	u32 val;
1153 
1154 	/* read the SRIOV capability structure
1155 	 * The fields can be read via configuration read or
1156 	 * directly from the device (starting at offset PCICFG_OFFSET)
1157 	 */
1158 	if (bnx2x_sriov_pci_cfg_info(bp, iov))
1159 		return -ENODEV;
1160 
1161 	/* get the number of SRIOV bars */
1162 	iov->nres = 0;
1163 
1164 	/* read the first_vfid */
1165 	val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF);
1166 	iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK)
1167 			       * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp));
1168 
1169 	DP(BNX2X_MSG_IOV,
1170 	   "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
1171 	   BP_FUNC(bp),
1172 	   iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total,
1173 	   iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
1174 
1175 	return 0;
1176 }
1177 
1178 /* must be called after PF bars are mapped */
1179 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
1180 		       int num_vfs_param)
1181 {
1182 	int err, i;
1183 	struct bnx2x_sriov *iov;
1184 	struct pci_dev *dev = bp->pdev;
1185 
1186 	bp->vfdb = NULL;
1187 
1188 	/* verify is pf */
1189 	if (IS_VF(bp))
1190 		return 0;
1191 
1192 	/* verify sriov capability is present in configuration space */
1193 	if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV))
1194 		return 0;
1195 
1196 	/* verify chip revision */
1197 	if (CHIP_IS_E1x(bp))
1198 		return 0;
1199 
1200 	/* check if SRIOV support is turned off */
1201 	if (!num_vfs_param)
1202 		return 0;
1203 
1204 	/* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */
1205 	if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) {
1206 		BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n",
1207 			  BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID);
1208 		return 0;
1209 	}
1210 
1211 	/* SRIOV can be enabled only with MSIX */
1212 	if (int_mode_param == BNX2X_INT_MODE_MSI ||
1213 	    int_mode_param == BNX2X_INT_MODE_INTX) {
1214 		BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n");
1215 		return 0;
1216 	}
1217 
1218 	err = -EIO;
1219 	/* verify ari is enabled */
1220 	if (!pci_ari_enabled(bp->pdev->bus)) {
1221 		BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n");
1222 		return 0;
1223 	}
1224 
1225 	/* verify igu is in normal mode */
1226 	if (CHIP_INT_MODE_IS_BC(bp)) {
1227 		BNX2X_ERR("IGU not normal mode,  SRIOV can not be enabled\n");
1228 		return 0;
1229 	}
1230 
1231 	/* allocate the vfs database */
1232 	bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL);
1233 	if (!bp->vfdb) {
1234 		BNX2X_ERR("failed to allocate vf database\n");
1235 		err = -ENOMEM;
1236 		goto failed;
1237 	}
1238 
1239 	/* get the sriov info - Linux already collected all the pertinent
1240 	 * information, however the sriov structure is for the private use
1241 	 * of the pci module. Also we want this information regardless
1242 	 * of the hyper-visor.
1243 	 */
1244 	iov = &(bp->vfdb->sriov);
1245 	err = bnx2x_sriov_info(bp, iov);
1246 	if (err)
1247 		goto failed;
1248 
1249 	/* SR-IOV capability was enabled but there are no VFs*/
1250 	if (iov->total == 0)
1251 		goto failed;
1252 
1253 	iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param);
1254 
1255 	DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n",
1256 	   num_vfs_param, iov->nr_virtfn);
1257 
1258 	/* allocate the vf array */
1259 	bp->vfdb->vfs = kcalloc(BNX2X_NR_VIRTFN(bp),
1260 				sizeof(struct bnx2x_virtf),
1261 				GFP_KERNEL);
1262 	if (!bp->vfdb->vfs) {
1263 		BNX2X_ERR("failed to allocate vf array\n");
1264 		err = -ENOMEM;
1265 		goto failed;
1266 	}
1267 
1268 	/* Initial VF init - index and abs_vfid - nr_virtfn must be set */
1269 	for_each_vf(bp, i) {
1270 		bnx2x_vf(bp, i, index) = i;
1271 		bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i;
1272 		bnx2x_vf(bp, i, state) = VF_FREE;
1273 		mutex_init(&bnx2x_vf(bp, i, op_mutex));
1274 		bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE;
1275 		/* enable spoofchk by default */
1276 		bnx2x_vf(bp, i, spoofchk) = 1;
1277 	}
1278 
1279 	/* re-read the IGU CAM for VFs - index and abs_vfid must be set */
1280 	if (!bnx2x_get_vf_igu_cam_info(bp)) {
1281 		BNX2X_ERR("No entries in IGU CAM for vfs\n");
1282 		err = -EINVAL;
1283 		goto failed;
1284 	}
1285 
1286 	/* allocate the queue arrays for all VFs */
1287 	bp->vfdb->vfqs = kcalloc(BNX2X_MAX_NUM_VF_QUEUES,
1288 				 sizeof(struct bnx2x_vf_queue),
1289 				 GFP_KERNEL);
1290 
1291 	if (!bp->vfdb->vfqs) {
1292 		BNX2X_ERR("failed to allocate vf queue array\n");
1293 		err = -ENOMEM;
1294 		goto failed;
1295 	}
1296 
1297 	/* Prepare the VFs event synchronization mechanism */
1298 	mutex_init(&bp->vfdb->event_mutex);
1299 
1300 	mutex_init(&bp->vfdb->bulletin_mutex);
1301 
1302 	if (SHMEM2_HAS(bp, sriov_switch_mode))
1303 		SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB);
1304 
1305 	return 0;
1306 failed:
1307 	DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
1308 	__bnx2x_iov_free_vfdb(bp);
1309 	return err;
1310 }
1311 
1312 void bnx2x_iov_remove_one(struct bnx2x *bp)
1313 {
1314 	int vf_idx;
1315 
1316 	/* if SRIOV is not enabled there's nothing to do */
1317 	if (!IS_SRIOV(bp))
1318 		return;
1319 
1320 	bnx2x_disable_sriov(bp);
1321 
1322 	/* disable access to all VFs */
1323 	for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) {
1324 		bnx2x_pretend_func(bp,
1325 				   HW_VF_HANDLE(bp,
1326 						bp->vfdb->sriov.first_vf_in_pf +
1327 						vf_idx));
1328 		DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n",
1329 		   bp->vfdb->sriov.first_vf_in_pf + vf_idx);
1330 		bnx2x_vf_enable_internal(bp, 0);
1331 		bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1332 	}
1333 
1334 	/* free vf database */
1335 	__bnx2x_iov_free_vfdb(bp);
1336 }
1337 
1338 void bnx2x_iov_free_mem(struct bnx2x *bp)
1339 {
1340 	int i;
1341 
1342 	if (!IS_SRIOV(bp))
1343 		return;
1344 
1345 	/* free vfs hw contexts */
1346 	for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1347 		struct hw_dma *cxt = &bp->vfdb->context[i];
1348 		BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size);
1349 	}
1350 
1351 	BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr,
1352 		       BP_VFDB(bp)->sp_dma.mapping,
1353 		       BP_VFDB(bp)->sp_dma.size);
1354 
1355 	BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr,
1356 		       BP_VF_MBX_DMA(bp)->mapping,
1357 		       BP_VF_MBX_DMA(bp)->size);
1358 
1359 	BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr,
1360 		       BP_VF_BULLETIN_DMA(bp)->mapping,
1361 		       BP_VF_BULLETIN_DMA(bp)->size);
1362 }
1363 
1364 int bnx2x_iov_alloc_mem(struct bnx2x *bp)
1365 {
1366 	size_t tot_size;
1367 	int i, rc = 0;
1368 
1369 	if (!IS_SRIOV(bp))
1370 		return rc;
1371 
1372 	/* allocate vfs hw contexts */
1373 	tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) *
1374 		BNX2X_CIDS_PER_VF * sizeof(union cdu_context);
1375 
1376 	for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1377 		struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i);
1378 		cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ);
1379 
1380 		if (cxt->size) {
1381 			cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size);
1382 			if (!cxt->addr)
1383 				goto alloc_mem_err;
1384 		} else {
1385 			cxt->addr = NULL;
1386 			cxt->mapping = 0;
1387 		}
1388 		tot_size -= cxt->size;
1389 	}
1390 
1391 	/* allocate vfs ramrods dma memory - client_init and set_mac */
1392 	tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp);
1393 	BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping,
1394 						   tot_size);
1395 	if (!BP_VFDB(bp)->sp_dma.addr)
1396 		goto alloc_mem_err;
1397 	BP_VFDB(bp)->sp_dma.size = tot_size;
1398 
1399 	/* allocate mailboxes */
1400 	tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE;
1401 	BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping,
1402 						  tot_size);
1403 	if (!BP_VF_MBX_DMA(bp)->addr)
1404 		goto alloc_mem_err;
1405 
1406 	BP_VF_MBX_DMA(bp)->size = tot_size;
1407 
1408 	/* allocate local bulletin boards */
1409 	tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE;
1410 	BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping,
1411 						       tot_size);
1412 	if (!BP_VF_BULLETIN_DMA(bp)->addr)
1413 		goto alloc_mem_err;
1414 
1415 	BP_VF_BULLETIN_DMA(bp)->size = tot_size;
1416 
1417 	return 0;
1418 
1419 alloc_mem_err:
1420 	return -ENOMEM;
1421 }
1422 
1423 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf,
1424 			   struct bnx2x_vf_queue *q)
1425 {
1426 	u8 cl_id = vfq_cl_id(vf, q);
1427 	u8 func_id = FW_VF_HANDLE(vf->abs_vfid);
1428 	unsigned long q_type = 0;
1429 
1430 	set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
1431 	set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
1432 
1433 	/* Queue State object */
1434 	bnx2x_init_queue_obj(bp, &q->sp_obj,
1435 			     cl_id, &q->cid, 1, func_id,
1436 			     bnx2x_vf_sp(bp, vf, q_data),
1437 			     bnx2x_vf_sp_map(bp, vf, q_data),
1438 			     q_type);
1439 
1440 	/* sp indication is set only when vlan/mac/etc. are initialized */
1441 	q->sp_initialized = false;
1442 
1443 	DP(BNX2X_MSG_IOV,
1444 	   "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n",
1445 	   vf->abs_vfid, q->sp_obj.func_id, q->cid);
1446 }
1447 
1448 static int bnx2x_max_speed_cap(struct bnx2x *bp)
1449 {
1450 	u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)];
1451 
1452 	if (supported &
1453 	    (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full))
1454 		return 20000;
1455 
1456 	return 10000; /* assume lowest supported speed is 10G */
1457 }
1458 
1459 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx)
1460 {
1461 	struct bnx2x_link_report_data *state = &bp->last_reported_link;
1462 	struct pf_vf_bulletin_content *bulletin;
1463 	struct bnx2x_virtf *vf;
1464 	bool update = true;
1465 	int rc = 0;
1466 
1467 	/* sanity and init */
1468 	rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false);
1469 	if (rc)
1470 		return rc;
1471 
1472 	mutex_lock(&bp->vfdb->bulletin_mutex);
1473 
1474 	if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) {
1475 		bulletin->valid_bitmap |= 1 << LINK_VALID;
1476 
1477 		bulletin->link_speed = state->line_speed;
1478 		bulletin->link_flags = 0;
1479 		if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1480 			     &state->link_report_flags))
1481 			bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN;
1482 		if (test_bit(BNX2X_LINK_REPORT_FD,
1483 			     &state->link_report_flags))
1484 			bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX;
1485 		if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1486 			     &state->link_report_flags))
1487 			bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON;
1488 		if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1489 			     &state->link_report_flags))
1490 			bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON;
1491 	} else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE &&
1492 		   !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) {
1493 		bulletin->valid_bitmap |= 1 << LINK_VALID;
1494 		bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN;
1495 	} else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE &&
1496 		   (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) {
1497 		bulletin->valid_bitmap |= 1 << LINK_VALID;
1498 		bulletin->link_speed = bnx2x_max_speed_cap(bp);
1499 		bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN;
1500 	} else {
1501 		update = false;
1502 	}
1503 
1504 	if (update) {
1505 		DP(NETIF_MSG_LINK | BNX2X_MSG_IOV,
1506 		   "vf %d mode %u speed %d flags %x\n", idx,
1507 		   vf->link_cfg, bulletin->link_speed, bulletin->link_flags);
1508 
1509 		/* Post update on VF's bulletin board */
1510 		rc = bnx2x_post_vf_bulletin(bp, idx);
1511 		if (rc) {
1512 			BNX2X_ERR("failed to update VF[%d] bulletin\n", idx);
1513 			goto out;
1514 		}
1515 	}
1516 
1517 out:
1518 	mutex_unlock(&bp->vfdb->bulletin_mutex);
1519 	return rc;
1520 }
1521 
1522 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state)
1523 {
1524 	struct bnx2x *bp = netdev_priv(dev);
1525 	struct bnx2x_virtf *vf = BP_VF(bp, idx);
1526 
1527 	if (!vf)
1528 		return -EINVAL;
1529 
1530 	if (vf->link_cfg == link_state)
1531 		return 0; /* nothing todo */
1532 
1533 	vf->link_cfg = link_state;
1534 
1535 	return bnx2x_iov_link_update_vf(bp, idx);
1536 }
1537 
1538 void bnx2x_iov_link_update(struct bnx2x *bp)
1539 {
1540 	int vfid;
1541 
1542 	if (!IS_SRIOV(bp))
1543 		return;
1544 
1545 	for_each_vf(bp, vfid)
1546 		bnx2x_iov_link_update_vf(bp, vfid);
1547 }
1548 
1549 /* called by bnx2x_nic_load */
1550 int bnx2x_iov_nic_init(struct bnx2x *bp)
1551 {
1552 	int vfid;
1553 
1554 	if (!IS_SRIOV(bp)) {
1555 		DP(BNX2X_MSG_IOV, "vfdb was not allocated\n");
1556 		return 0;
1557 	}
1558 
1559 	DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn);
1560 
1561 	/* let FLR complete ... */
1562 	msleep(100);
1563 
1564 	/* initialize vf database */
1565 	for_each_vf(bp, vfid) {
1566 		struct bnx2x_virtf *vf = BP_VF(bp, vfid);
1567 
1568 		int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) *
1569 			BNX2X_CIDS_PER_VF;
1570 
1571 		union cdu_context *base_cxt = (union cdu_context *)
1572 			BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
1573 			(base_vf_cid & (ILT_PAGE_CIDS-1));
1574 
1575 		DP(BNX2X_MSG_IOV,
1576 		   "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n",
1577 		   vf->abs_vfid, vf_sb_count(vf), base_vf_cid,
1578 		   BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt);
1579 
1580 		/* init statically provisioned resources */
1581 		bnx2x_iov_static_resc(bp, vf);
1582 
1583 		/* queues are initialized during VF-ACQUIRE */
1584 		vf->filter_state = 0;
1585 		vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id);
1586 
1587 		bnx2x_init_credit_pool(&vf->vf_vlans_pool, 0,
1588 				       vf_vlan_rules_cnt(vf));
1589 		bnx2x_init_credit_pool(&vf->vf_macs_pool, 0,
1590 				       vf_mac_rules_cnt(vf));
1591 
1592 		/*  init mcast object - This object will be re-initialized
1593 		 *  during VF-ACQUIRE with the proper cl_id and cid.
1594 		 *  It needs to be initialized here so that it can be safely
1595 		 *  handled by a subsequent FLR flow.
1596 		 */
1597 		bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF,
1598 				     0xFF, 0xFF, 0xFF,
1599 				     bnx2x_vf_sp(bp, vf, mcast_rdata),
1600 				     bnx2x_vf_sp_map(bp, vf, mcast_rdata),
1601 				     BNX2X_FILTER_MCAST_PENDING,
1602 				     &vf->filter_state,
1603 				     BNX2X_OBJ_TYPE_RX_TX);
1604 
1605 		/* set the mailbox message addresses */
1606 		BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *)
1607 			(((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid *
1608 			MBX_MSG_ALIGNED_SIZE);
1609 
1610 		BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping +
1611 			vfid * MBX_MSG_ALIGNED_SIZE;
1612 
1613 		/* Enable vf mailbox */
1614 		bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
1615 	}
1616 
1617 	/* Final VF init */
1618 	for_each_vf(bp, vfid) {
1619 		struct bnx2x_virtf *vf = BP_VF(bp, vfid);
1620 
1621 		/* fill in the BDF and bars */
1622 		vf->domain = bnx2x_vf_domain(bp, vfid);
1623 		vf->bus = bnx2x_vf_bus(bp, vfid);
1624 		vf->devfn = bnx2x_vf_devfn(bp, vfid);
1625 		bnx2x_vf_set_bars(bp, vf);
1626 
1627 		DP(BNX2X_MSG_IOV,
1628 		   "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n",
1629 		   vf->abs_vfid, vf->bus, vf->devfn,
1630 		   (unsigned)vf->bars[0].bar, vf->bars[0].size,
1631 		   (unsigned)vf->bars[1].bar, vf->bars[1].size,
1632 		   (unsigned)vf->bars[2].bar, vf->bars[2].size);
1633 	}
1634 
1635 	return 0;
1636 }
1637 
1638 /* called by bnx2x_chip_cleanup */
1639 int bnx2x_iov_chip_cleanup(struct bnx2x *bp)
1640 {
1641 	int i;
1642 
1643 	if (!IS_SRIOV(bp))
1644 		return 0;
1645 
1646 	/* release all the VFs */
1647 	for_each_vf(bp, i)
1648 		bnx2x_vf_release(bp, BP_VF(bp, i));
1649 
1650 	return 0;
1651 }
1652 
1653 /* called by bnx2x_init_hw_func, returns the next ilt line */
1654 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line)
1655 {
1656 	int i;
1657 	struct bnx2x_ilt *ilt = BP_ILT(bp);
1658 
1659 	if (!IS_SRIOV(bp))
1660 		return line;
1661 
1662 	/* set vfs ilt lines */
1663 	for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1664 		struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i);
1665 
1666 		ilt->lines[line+i].page = hw_cxt->addr;
1667 		ilt->lines[line+i].page_mapping = hw_cxt->mapping;
1668 		ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */
1669 	}
1670 	return line + i;
1671 }
1672 
1673 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid)
1674 {
1675 	return ((cid >= BNX2X_FIRST_VF_CID) &&
1676 		((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS));
1677 }
1678 
1679 static
1680 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp,
1681 					struct bnx2x_vf_queue *vfq,
1682 					union event_ring_elem *elem)
1683 {
1684 	unsigned long ramrod_flags = 0;
1685 	int rc = 0;
1686 	u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
1687 
1688 	/* Always push next commands out, don't wait here */
1689 	set_bit(RAMROD_CONT, &ramrod_flags);
1690 
1691 	switch (echo >> BNX2X_SWCID_SHIFT) {
1692 	case BNX2X_FILTER_MAC_PENDING:
1693 		rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem,
1694 					   &ramrod_flags);
1695 		break;
1696 	case BNX2X_FILTER_VLAN_PENDING:
1697 		rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem,
1698 					    &ramrod_flags);
1699 		break;
1700 	default:
1701 		BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
1702 		return;
1703 	}
1704 	if (rc < 0)
1705 		BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
1706 	else if (rc > 0)
1707 		DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n");
1708 }
1709 
1710 static
1711 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp,
1712 			       struct bnx2x_virtf *vf)
1713 {
1714 	struct bnx2x_mcast_ramrod_params rparam = {NULL};
1715 	int rc;
1716 
1717 	rparam.mcast_obj = &vf->mcast_obj;
1718 	vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw);
1719 
1720 	/* If there are pending mcast commands - send them */
1721 	if (vf->mcast_obj.check_pending(&vf->mcast_obj)) {
1722 		rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
1723 		if (rc < 0)
1724 			BNX2X_ERR("Failed to send pending mcast commands: %d\n",
1725 				  rc);
1726 	}
1727 }
1728 
1729 static
1730 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp,
1731 				 struct bnx2x_virtf *vf)
1732 {
1733 	smp_mb__before_atomic();
1734 	clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
1735 	smp_mb__after_atomic();
1736 }
1737 
1738 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp,
1739 					   struct bnx2x_virtf *vf)
1740 {
1741 	vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw);
1742 }
1743 
1744 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem)
1745 {
1746 	struct bnx2x_virtf *vf;
1747 	int qidx = 0, abs_vfid;
1748 	u8 opcode;
1749 	u16 cid = 0xffff;
1750 
1751 	if (!IS_SRIOV(bp))
1752 		return 1;
1753 
1754 	/* first get the cid - the only events we handle here are cfc-delete
1755 	 * and set-mac completion
1756 	 */
1757 	opcode = elem->message.opcode;
1758 
1759 	switch (opcode) {
1760 	case EVENT_RING_OPCODE_CFC_DEL:
1761 		cid = SW_CID(elem->message.data.cfc_del_event.cid);
1762 		DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid);
1763 		break;
1764 	case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
1765 	case EVENT_RING_OPCODE_MULTICAST_RULES:
1766 	case EVENT_RING_OPCODE_FILTERS_RULES:
1767 	case EVENT_RING_OPCODE_RSS_UPDATE_RULES:
1768 		cid = SW_CID(elem->message.data.eth_event.echo);
1769 		DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid);
1770 		break;
1771 	case EVENT_RING_OPCODE_VF_FLR:
1772 		abs_vfid = elem->message.data.vf_flr_event.vf_id;
1773 		DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n",
1774 		   abs_vfid);
1775 		goto get_vf;
1776 	case EVENT_RING_OPCODE_MALICIOUS_VF:
1777 		abs_vfid = elem->message.data.malicious_vf_event.vf_id;
1778 		BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n",
1779 			  abs_vfid,
1780 			  elem->message.data.malicious_vf_event.err_id);
1781 		goto get_vf;
1782 	default:
1783 		return 1;
1784 	}
1785 
1786 	/* check if the cid is the VF range */
1787 	if (!bnx2x_iov_is_vf_cid(bp, cid)) {
1788 		DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid);
1789 		return 1;
1790 	}
1791 
1792 	/* extract vf and rxq index from vf_cid - relies on the following:
1793 	 * 1. vfid on cid reflects the true abs_vfid
1794 	 * 2. The max number of VFs (per path) is 64
1795 	 */
1796 	qidx = cid & ((1 << BNX2X_VF_CID_WND)-1);
1797 	abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
1798 get_vf:
1799 	vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
1800 
1801 	if (!vf) {
1802 		BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n",
1803 			  cid, abs_vfid);
1804 		return 0;
1805 	}
1806 
1807 	switch (opcode) {
1808 	case EVENT_RING_OPCODE_CFC_DEL:
1809 		DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n",
1810 		   vf->abs_vfid, qidx);
1811 		vfq_get(vf, qidx)->sp_obj.complete_cmd(bp,
1812 						       &vfq_get(vf,
1813 								qidx)->sp_obj,
1814 						       BNX2X_Q_CMD_CFC_DEL);
1815 		break;
1816 	case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
1817 		DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n",
1818 		   vf->abs_vfid, qidx);
1819 		bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem);
1820 		break;
1821 	case EVENT_RING_OPCODE_MULTICAST_RULES:
1822 		DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n",
1823 		   vf->abs_vfid, qidx);
1824 		bnx2x_vf_handle_mcast_eqe(bp, vf);
1825 		break;
1826 	case EVENT_RING_OPCODE_FILTERS_RULES:
1827 		DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n",
1828 		   vf->abs_vfid, qidx);
1829 		bnx2x_vf_handle_filters_eqe(bp, vf);
1830 		break;
1831 	case EVENT_RING_OPCODE_RSS_UPDATE_RULES:
1832 		DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n",
1833 		   vf->abs_vfid, qidx);
1834 		bnx2x_vf_handle_rss_update_eqe(bp, vf);
1835 		/* fall through */
1836 	case EVENT_RING_OPCODE_VF_FLR:
1837 		/* Do nothing for now */
1838 		return 0;
1839 	case EVENT_RING_OPCODE_MALICIOUS_VF:
1840 		vf->malicious = true;
1841 		return 0;
1842 	}
1843 
1844 	return 0;
1845 }
1846 
1847 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid)
1848 {
1849 	/* extract the vf from vf_cid - relies on the following:
1850 	 * 1. vfid on cid reflects the true abs_vfid
1851 	 * 2. The max number of VFs (per path) is 64
1852 	 */
1853 	int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
1854 	return bnx2x_vf_by_abs_fid(bp, abs_vfid);
1855 }
1856 
1857 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid,
1858 				struct bnx2x_queue_sp_obj **q_obj)
1859 {
1860 	struct bnx2x_virtf *vf;
1861 
1862 	if (!IS_SRIOV(bp))
1863 		return;
1864 
1865 	vf = bnx2x_vf_by_cid(bp, vf_cid);
1866 
1867 	if (vf) {
1868 		/* extract queue index from vf_cid - relies on the following:
1869 		 * 1. vfid on cid reflects the true abs_vfid
1870 		 * 2. The max number of VFs (per path) is 64
1871 		 */
1872 		int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1);
1873 		*q_obj = &bnx2x_vfq(vf, q_index, sp_obj);
1874 	} else {
1875 		BNX2X_ERR("No vf matching cid %d\n", vf_cid);
1876 	}
1877 }
1878 
1879 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp)
1880 {
1881 	int i;
1882 	int first_queue_query_index, num_queues_req;
1883 	dma_addr_t cur_data_offset;
1884 	struct stats_query_entry *cur_query_entry;
1885 	u8 stats_count = 0;
1886 	bool is_fcoe = false;
1887 
1888 	if (!IS_SRIOV(bp))
1889 		return;
1890 
1891 	if (!NO_FCOE(bp))
1892 		is_fcoe = true;
1893 
1894 	/* fcoe adds one global request and one queue request */
1895 	num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe;
1896 	first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX -
1897 		(is_fcoe ? 0 : 1);
1898 
1899 	DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1900 	       "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n",
1901 	       BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index,
1902 	       first_queue_query_index + num_queues_req);
1903 
1904 	cur_data_offset = bp->fw_stats_data_mapping +
1905 		offsetof(struct bnx2x_fw_stats_data, queue_stats) +
1906 		num_queues_req * sizeof(struct per_queue_stats);
1907 
1908 	cur_query_entry = &bp->fw_stats_req->
1909 		query[first_queue_query_index + num_queues_req];
1910 
1911 	for_each_vf(bp, i) {
1912 		int j;
1913 		struct bnx2x_virtf *vf = BP_VF(bp, i);
1914 
1915 		if (vf->state != VF_ENABLED) {
1916 			DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1917 			       "vf %d not enabled so no stats for it\n",
1918 			       vf->abs_vfid);
1919 			continue;
1920 		}
1921 
1922 		if (vf->malicious) {
1923 			DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1924 			       "vf %d malicious so no stats for it\n",
1925 			       vf->abs_vfid);
1926 			continue;
1927 		}
1928 
1929 		DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1930 		       "add addresses for vf %d\n", vf->abs_vfid);
1931 		for_each_vfq(vf, j) {
1932 			struct bnx2x_vf_queue *rxq = vfq_get(vf, j);
1933 
1934 			dma_addr_t q_stats_addr =
1935 				vf->fw_stat_map + j * vf->stats_stride;
1936 
1937 			/* collect stats fro active queues only */
1938 			if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) ==
1939 			    BNX2X_Q_LOGICAL_STATE_STOPPED)
1940 				continue;
1941 
1942 			/* create stats query entry for this queue */
1943 			cur_query_entry->kind = STATS_TYPE_QUEUE;
1944 			cur_query_entry->index = vfq_stat_id(vf, rxq);
1945 			cur_query_entry->funcID =
1946 				cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid));
1947 			cur_query_entry->address.hi =
1948 				cpu_to_le32(U64_HI(q_stats_addr));
1949 			cur_query_entry->address.lo =
1950 				cpu_to_le32(U64_LO(q_stats_addr));
1951 			DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1952 			       "added address %x %x for vf %d queue %d client %d\n",
1953 			       cur_query_entry->address.hi,
1954 			       cur_query_entry->address.lo,
1955 			       cur_query_entry->funcID,
1956 			       j, cur_query_entry->index);
1957 			cur_query_entry++;
1958 			cur_data_offset += sizeof(struct per_queue_stats);
1959 			stats_count++;
1960 
1961 			/* all stats are coalesced to the leading queue */
1962 			if (vf->cfg_flags & VF_CFG_STATS_COALESCE)
1963 				break;
1964 		}
1965 	}
1966 	bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count;
1967 }
1968 
1969 /* VF API helpers */
1970 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid,
1971 				u8 enable)
1972 {
1973 	u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4;
1974 	u32 val = enable ? (abs_vfid | (1 << 6)) : 0;
1975 
1976 	REG_WR(bp, reg, val);
1977 }
1978 
1979 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf)
1980 {
1981 	int i;
1982 
1983 	for_each_vfq(vf, i)
1984 		bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
1985 				    vfq_qzone_id(vf, vfq_get(vf, i)), false);
1986 }
1987 
1988 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf)
1989 {
1990 	u32 val;
1991 
1992 	/* clear the VF configuration - pretend */
1993 	bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
1994 	val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
1995 	val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN |
1996 		 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK);
1997 	REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
1998 	bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1999 }
2000 
2001 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf)
2002 {
2003 	return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF),
2004 		     BNX2X_VF_MAX_QUEUES);
2005 }
2006 
2007 static
2008 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf,
2009 			    struct vf_pf_resc_request *req_resc)
2010 {
2011 	u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
2012 	u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
2013 
2014 	return ((req_resc->num_rxqs <= rxq_cnt) &&
2015 		(req_resc->num_txqs <= txq_cnt) &&
2016 		(req_resc->num_sbs <= vf_sb_count(vf))   &&
2017 		(req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) &&
2018 		(req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf)));
2019 }
2020 
2021 /* CORE VF API */
2022 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf,
2023 		     struct vf_pf_resc_request *resc)
2024 {
2025 	int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) *
2026 		BNX2X_CIDS_PER_VF;
2027 
2028 	union cdu_context *base_cxt = (union cdu_context *)
2029 		BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
2030 		(base_vf_cid & (ILT_PAGE_CIDS-1));
2031 	int i;
2032 
2033 	/* if state is 'acquired' the VF was not released or FLR'd, in
2034 	 * this case the returned resources match the acquired already
2035 	 * acquired resources. Verify that the requested numbers do
2036 	 * not exceed the already acquired numbers.
2037 	 */
2038 	if (vf->state == VF_ACQUIRED) {
2039 		DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n",
2040 		   vf->abs_vfid);
2041 
2042 		if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
2043 			BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n",
2044 				  vf->abs_vfid);
2045 			return -EINVAL;
2046 		}
2047 		return 0;
2048 	}
2049 
2050 	/* Otherwise vf state must be 'free' or 'reset' */
2051 	if (vf->state != VF_FREE && vf->state != VF_RESET) {
2052 		BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n",
2053 			  vf->abs_vfid, vf->state);
2054 		return -EINVAL;
2055 	}
2056 
2057 	/* static allocation:
2058 	 * the global maximum number are fixed per VF. Fail the request if
2059 	 * requested number exceed these globals
2060 	 */
2061 	if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
2062 		DP(BNX2X_MSG_IOV,
2063 		   "cannot fulfill vf resource request. Placing maximal available values in response\n");
2064 		/* set the max resource in the vf */
2065 		return -ENOMEM;
2066 	}
2067 
2068 	/* Set resources counters - 0 request means max available */
2069 	vf_sb_count(vf) = resc->num_sbs;
2070 	vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
2071 	vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
2072 
2073 	DP(BNX2X_MSG_IOV,
2074 	   "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n",
2075 	   vf_sb_count(vf), vf_rxq_count(vf),
2076 	   vf_txq_count(vf), vf_mac_rules_cnt(vf),
2077 	   vf_vlan_rules_cnt(vf));
2078 
2079 	/* Initialize the queues */
2080 	if (!vf->vfqs) {
2081 		DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n");
2082 		return -EINVAL;
2083 	}
2084 
2085 	for_each_vfq(vf, i) {
2086 		struct bnx2x_vf_queue *q = vfq_get(vf, i);
2087 
2088 		if (!q) {
2089 			BNX2X_ERR("q number %d was not allocated\n", i);
2090 			return -EINVAL;
2091 		}
2092 
2093 		q->index = i;
2094 		q->cxt = &((base_cxt + i)->eth);
2095 		q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i;
2096 
2097 		DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n",
2098 		   vf->abs_vfid, i, q->index, q->cid, q->cxt);
2099 
2100 		/* init SP objects */
2101 		bnx2x_vfq_init(bp, vf, q);
2102 	}
2103 	vf->state = VF_ACQUIRED;
2104 	return 0;
2105 }
2106 
2107 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map)
2108 {
2109 	struct bnx2x_func_init_params func_init = {0};
2110 	int i;
2111 
2112 	/* the sb resources are initialized at this point, do the
2113 	 * FW/HW initializations
2114 	 */
2115 	for_each_vf_sb(vf, i)
2116 		bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true,
2117 			      vf_igu_sb(vf, i), vf_igu_sb(vf, i));
2118 
2119 	/* Sanity checks */
2120 	if (vf->state != VF_ACQUIRED) {
2121 		DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n",
2122 		   vf->abs_vfid, vf->state);
2123 		return -EINVAL;
2124 	}
2125 
2126 	/* let FLR complete ... */
2127 	msleep(100);
2128 
2129 	/* FLR cleanup epilogue */
2130 	if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid))
2131 		return -EBUSY;
2132 
2133 	/* reset IGU VF statistics: MSIX */
2134 	REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);
2135 
2136 	/* function setup */
2137 	func_init.pf_id = BP_FUNC(bp);
2138 	func_init.func_id = FW_VF_HANDLE(vf->abs_vfid);
2139 	bnx2x_func_init(bp, &func_init);
2140 
2141 	/* Enable the vf */
2142 	bnx2x_vf_enable_access(bp, vf->abs_vfid);
2143 	bnx2x_vf_enable_traffic(bp, vf);
2144 
2145 	/* queue protection table */
2146 	for_each_vfq(vf, i)
2147 		bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
2148 				    vfq_qzone_id(vf, vfq_get(vf, i)), true);
2149 
2150 	vf->state = VF_ENABLED;
2151 
2152 	/* update vf bulletin board */
2153 	bnx2x_post_vf_bulletin(bp, vf->index);
2154 
2155 	return 0;
2156 }
2157 
2158 struct set_vf_state_cookie {
2159 	struct bnx2x_virtf *vf;
2160 	u8 state;
2161 };
2162 
2163 static void bnx2x_set_vf_state(void *cookie)
2164 {
2165 	struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie;
2166 
2167 	p->vf->state = p->state;
2168 }
2169 
2170 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf)
2171 {
2172 	int rc = 0, i;
2173 
2174 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2175 
2176 	/* Close all queues */
2177 	for (i = 0; i < vf_rxq_count(vf); i++) {
2178 		rc = bnx2x_vf_queue_teardown(bp, vf, i);
2179 		if (rc)
2180 			goto op_err;
2181 	}
2182 
2183 	/* disable the interrupts */
2184 	DP(BNX2X_MSG_IOV, "disabling igu\n");
2185 	bnx2x_vf_igu_disable(bp, vf);
2186 
2187 	/* disable the VF */
2188 	DP(BNX2X_MSG_IOV, "clearing qtbl\n");
2189 	bnx2x_vf_clr_qtbl(bp, vf);
2190 
2191 	/* need to make sure there are no outstanding stats ramrods which may
2192 	 * cause the device to access the VF's stats buffer which it will free
2193 	 * as soon as we return from the close flow.
2194 	 */
2195 	{
2196 		struct set_vf_state_cookie cookie;
2197 
2198 		cookie.vf = vf;
2199 		cookie.state = VF_ACQUIRED;
2200 		rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie);
2201 		if (rc)
2202 			goto op_err;
2203 	}
2204 
2205 	DP(BNX2X_MSG_IOV, "set state to acquired\n");
2206 
2207 	return 0;
2208 op_err:
2209 	BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc);
2210 	return rc;
2211 }
2212 
2213 /* VF release can be called either: 1. The VF was acquired but
2214  * not enabled 2. the vf was enabled or in the process of being
2215  * enabled
2216  */
2217 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf)
2218 {
2219 	int rc;
2220 
2221 	DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid,
2222 	   vf->state == VF_FREE ? "Free" :
2223 	   vf->state == VF_ACQUIRED ? "Acquired" :
2224 	   vf->state == VF_ENABLED ? "Enabled" :
2225 	   vf->state == VF_RESET ? "Reset" :
2226 	   "Unknown");
2227 
2228 	switch (vf->state) {
2229 	case VF_ENABLED:
2230 		rc = bnx2x_vf_close(bp, vf);
2231 		if (rc)
2232 			goto op_err;
2233 		/* Fallthrough to release resources */
2234 	case VF_ACQUIRED:
2235 		DP(BNX2X_MSG_IOV, "about to free resources\n");
2236 		bnx2x_vf_free_resc(bp, vf);
2237 		break;
2238 
2239 	case VF_FREE:
2240 	case VF_RESET:
2241 	default:
2242 		break;
2243 	}
2244 	return 0;
2245 op_err:
2246 	BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc);
2247 	return rc;
2248 }
2249 
2250 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
2251 			struct bnx2x_config_rss_params *rss)
2252 {
2253 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2254 	set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags);
2255 	return bnx2x_config_rss(bp, rss);
2256 }
2257 
2258 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
2259 			struct vfpf_tpa_tlv *tlv,
2260 			struct bnx2x_queue_update_tpa_params *params)
2261 {
2262 	aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr;
2263 	struct bnx2x_queue_state_params qstate;
2264 	int qid, rc = 0;
2265 
2266 	DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2267 
2268 	/* Set ramrod params */
2269 	memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params));
2270 	memcpy(&qstate.params.update_tpa, params,
2271 	       sizeof(struct bnx2x_queue_update_tpa_params));
2272 	qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA;
2273 	set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags);
2274 
2275 	for (qid = 0; qid < vf_rxq_count(vf); qid++) {
2276 		qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
2277 		qstate.params.update_tpa.sge_map = sge_addr[qid];
2278 		DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n",
2279 		   vf->abs_vfid, qid, U64_HI(sge_addr[qid]),
2280 		   U64_LO(sge_addr[qid]));
2281 		rc = bnx2x_queue_state_change(bp, &qstate);
2282 		if (rc) {
2283 			BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n",
2284 				  U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]),
2285 				  vf->abs_vfid, qid);
2286 			return rc;
2287 		}
2288 	}
2289 
2290 	return rc;
2291 }
2292 
2293 /* VF release ~ VF close + VF release-resources
2294  * Release is the ultimate SW shutdown and is called whenever an
2295  * irrecoverable error is encountered.
2296  */
2297 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf)
2298 {
2299 	int rc;
2300 
2301 	DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid);
2302 	bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF);
2303 
2304 	rc = bnx2x_vf_free(bp, vf);
2305 	if (rc)
2306 		WARN(rc,
2307 		     "VF[%d] Failed to allocate resources for release op- rc=%d\n",
2308 		     vf->abs_vfid, rc);
2309 	bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF);
2310 	return rc;
2311 }
2312 
2313 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
2314 			      enum channel_tlvs tlv)
2315 {
2316 	/* we don't lock the channel for unsupported tlvs */
2317 	if (!bnx2x_tlv_supported(tlv)) {
2318 		BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n");
2319 		return;
2320 	}
2321 
2322 	/* lock the channel */
2323 	mutex_lock(&vf->op_mutex);
2324 
2325 	/* record the locking op */
2326 	vf->op_current = tlv;
2327 
2328 	/* log the lock */
2329 	DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n",
2330 	   vf->abs_vfid, tlv);
2331 }
2332 
2333 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
2334 				enum channel_tlvs expected_tlv)
2335 {
2336 	enum channel_tlvs current_tlv;
2337 
2338 	if (!vf) {
2339 		BNX2X_ERR("VF was %p\n", vf);
2340 		return;
2341 	}
2342 
2343 	current_tlv = vf->op_current;
2344 
2345 	/* we don't unlock the channel for unsupported tlvs */
2346 	if (!bnx2x_tlv_supported(expected_tlv))
2347 		return;
2348 
2349 	WARN(expected_tlv != vf->op_current,
2350 	     "lock mismatch: expected %d found %d", expected_tlv,
2351 	     vf->op_current);
2352 
2353 	/* record the locking op */
2354 	vf->op_current = CHANNEL_TLV_NONE;
2355 
2356 	/* lock the channel */
2357 	mutex_unlock(&vf->op_mutex);
2358 
2359 	/* log the unlock */
2360 	DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n",
2361 	   vf->abs_vfid, current_tlv);
2362 }
2363 
2364 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable)
2365 {
2366 	struct bnx2x_queue_state_params q_params;
2367 	u32 prev_flags;
2368 	int i, rc;
2369 
2370 	/* Verify changes are needed and record current Tx switching state */
2371 	prev_flags = bp->flags;
2372 	if (enable)
2373 		bp->flags |= TX_SWITCHING;
2374 	else
2375 		bp->flags &= ~TX_SWITCHING;
2376 	if (prev_flags == bp->flags)
2377 		return 0;
2378 
2379 	/* Verify state enables the sending of queue ramrods */
2380 	if ((bp->state != BNX2X_STATE_OPEN) ||
2381 	    (bnx2x_get_q_logical_state(bp,
2382 				      &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) !=
2383 	     BNX2X_Q_LOGICAL_STATE_ACTIVE))
2384 		return 0;
2385 
2386 	/* send q. update ramrod to configure Tx switching */
2387 	memset(&q_params, 0, sizeof(q_params));
2388 	__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
2389 	q_params.cmd = BNX2X_Q_CMD_UPDATE;
2390 	__set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
2391 		  &q_params.params.update.update_flags);
2392 	if (enable)
2393 		__set_bit(BNX2X_Q_UPDATE_TX_SWITCHING,
2394 			  &q_params.params.update.update_flags);
2395 	else
2396 		__clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING,
2397 			    &q_params.params.update.update_flags);
2398 
2399 	/* send the ramrod on all the queues of the PF */
2400 	for_each_eth_queue(bp, i) {
2401 		struct bnx2x_fastpath *fp = &bp->fp[i];
2402 
2403 		/* Set the appropriate Queue object */
2404 		q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
2405 
2406 		/* Update the Queue state */
2407 		rc = bnx2x_queue_state_change(bp, &q_params);
2408 		if (rc) {
2409 			BNX2X_ERR("Failed to configure Tx switching\n");
2410 			return rc;
2411 		}
2412 	}
2413 
2414 	DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled");
2415 	return 0;
2416 }
2417 
2418 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param)
2419 {
2420 	struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev));
2421 
2422 	if (!IS_SRIOV(bp)) {
2423 		BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n");
2424 		return -EINVAL;
2425 	}
2426 
2427 	DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n",
2428 	   num_vfs_param, BNX2X_NR_VIRTFN(bp));
2429 
2430 	/* HW channel is only operational when PF is up */
2431 	if (bp->state != BNX2X_STATE_OPEN) {
2432 		BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n");
2433 		return -EINVAL;
2434 	}
2435 
2436 	/* we are always bound by the total_vfs in the configuration space */
2437 	if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) {
2438 		BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n",
2439 			  num_vfs_param, BNX2X_NR_VIRTFN(bp));
2440 		num_vfs_param = BNX2X_NR_VIRTFN(bp);
2441 	}
2442 
2443 	bp->requested_nr_virtfn = num_vfs_param;
2444 	if (num_vfs_param == 0) {
2445 		bnx2x_set_pf_tx_switching(bp, false);
2446 		bnx2x_disable_sriov(bp);
2447 		return 0;
2448 	} else {
2449 		return bnx2x_enable_sriov(bp);
2450 	}
2451 }
2452 
2453 #define IGU_ENTRY_SIZE 4
2454 
2455 int bnx2x_enable_sriov(struct bnx2x *bp)
2456 {
2457 	int rc = 0, req_vfs = bp->requested_nr_virtfn;
2458 	int vf_idx, sb_idx, vfq_idx, qcount, first_vf;
2459 	u32 igu_entry, address;
2460 	u16 num_vf_queues;
2461 
2462 	if (req_vfs == 0)
2463 		return 0;
2464 
2465 	first_vf = bp->vfdb->sriov.first_vf_in_pf;
2466 
2467 	/* statically distribute vf sb pool between VFs */
2468 	num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES,
2469 			      BP_VFDB(bp)->vf_sbs_pool / req_vfs);
2470 
2471 	/* zero previous values learned from igu cam */
2472 	for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) {
2473 		struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
2474 
2475 		vf->sb_count = 0;
2476 		vf_sb_count(BP_VF(bp, vf_idx)) = 0;
2477 	}
2478 	bp->vfdb->vf_sbs_pool = 0;
2479 
2480 	/* prepare IGU cam */
2481 	sb_idx = BP_VFDB(bp)->first_vf_igu_entry;
2482 	address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE;
2483 	for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
2484 		for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) {
2485 			igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT |
2486 				vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT |
2487 				IGU_REG_MAPPING_MEMORY_VALID;
2488 			DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n",
2489 			   sb_idx, vf_idx);
2490 			REG_WR(bp, address, igu_entry);
2491 			sb_idx++;
2492 			address += IGU_ENTRY_SIZE;
2493 		}
2494 	}
2495 
2496 	/* Reinitialize vf database according to igu cam */
2497 	bnx2x_get_vf_igu_cam_info(bp);
2498 
2499 	DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n",
2500 	   BP_VFDB(bp)->vf_sbs_pool, num_vf_queues);
2501 
2502 	qcount = 0;
2503 	for_each_vf(bp, vf_idx) {
2504 		struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
2505 
2506 		/* set local queue arrays */
2507 		vf->vfqs = &bp->vfdb->vfqs[qcount];
2508 		qcount += vf_sb_count(vf);
2509 		bnx2x_iov_static_resc(bp, vf);
2510 	}
2511 
2512 	/* prepare msix vectors in VF configuration space - the value in the
2513 	 * PCI configuration space should be the index of the last entry,
2514 	 * namely one less than the actual size of the table
2515 	 */
2516 	for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
2517 		bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
2518 		REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
2519 		       num_vf_queues - 1);
2520 		DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n",
2521 		   vf_idx, num_vf_queues - 1);
2522 	}
2523 	bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
2524 
2525 	/* enable sriov. This will probe all the VFs, and consequentially cause
2526 	 * the "acquire" messages to appear on the VF PF channel.
2527 	 */
2528 	DP(BNX2X_MSG_IOV, "about to call enable sriov\n");
2529 	bnx2x_disable_sriov(bp);
2530 
2531 	rc = bnx2x_set_pf_tx_switching(bp, true);
2532 	if (rc)
2533 		return rc;
2534 
2535 	rc = pci_enable_sriov(bp->pdev, req_vfs);
2536 	if (rc) {
2537 		BNX2X_ERR("pci_enable_sriov failed with %d\n", rc);
2538 		return rc;
2539 	}
2540 	DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs);
2541 	return req_vfs;
2542 }
2543 
2544 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp)
2545 {
2546 	int vfidx;
2547 	struct pf_vf_bulletin_content *bulletin;
2548 
2549 	DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n");
2550 	for_each_vf(bp, vfidx) {
2551 		bulletin = BP_VF_BULLETIN(bp, vfidx);
2552 		if (bulletin->valid_bitmap & (1 << VLAN_VALID))
2553 			bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0,
2554 					  htons(ETH_P_8021Q));
2555 	}
2556 }
2557 
2558 void bnx2x_disable_sriov(struct bnx2x *bp)
2559 {
2560 	if (pci_vfs_assigned(bp->pdev)) {
2561 		DP(BNX2X_MSG_IOV,
2562 		   "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2563 		return;
2564 	}
2565 
2566 	pci_disable_sriov(bp->pdev);
2567 }
2568 
2569 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx,
2570 			    struct bnx2x_virtf **vf,
2571 			    struct pf_vf_bulletin_content **bulletin,
2572 			    bool test_queue)
2573 {
2574 	if (bp->state != BNX2X_STATE_OPEN) {
2575 		BNX2X_ERR("PF is down - can't utilize iov-related functionality\n");
2576 		return -EINVAL;
2577 	}
2578 
2579 	if (!IS_SRIOV(bp)) {
2580 		BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n");
2581 		return -EINVAL;
2582 	}
2583 
2584 	if (vfidx >= BNX2X_NR_VIRTFN(bp)) {
2585 		BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n",
2586 			  vfidx, BNX2X_NR_VIRTFN(bp));
2587 		return -EINVAL;
2588 	}
2589 
2590 	/* init members */
2591 	*vf = BP_VF(bp, vfidx);
2592 	*bulletin = BP_VF_BULLETIN(bp, vfidx);
2593 
2594 	if (!*vf) {
2595 		BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx);
2596 		return -EINVAL;
2597 	}
2598 
2599 	if (test_queue && !(*vf)->vfqs) {
2600 		BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n",
2601 			  vfidx);
2602 		return -EINVAL;
2603 	}
2604 
2605 	if (!*bulletin) {
2606 		BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n",
2607 			  vfidx);
2608 		return -EINVAL;
2609 	}
2610 
2611 	return 0;
2612 }
2613 
2614 int bnx2x_get_vf_config(struct net_device *dev, int vfidx,
2615 			struct ifla_vf_info *ivi)
2616 {
2617 	struct bnx2x *bp = netdev_priv(dev);
2618 	struct bnx2x_virtf *vf = NULL;
2619 	struct pf_vf_bulletin_content *bulletin = NULL;
2620 	struct bnx2x_vlan_mac_obj *mac_obj;
2621 	struct bnx2x_vlan_mac_obj *vlan_obj;
2622 	int rc;
2623 
2624 	/* sanity and init */
2625 	rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2626 	if (rc)
2627 		return rc;
2628 
2629 	mac_obj = &bnx2x_leading_vfq(vf, mac_obj);
2630 	vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2631 	if (!mac_obj || !vlan_obj) {
2632 		BNX2X_ERR("VF partially initialized\n");
2633 		return -EINVAL;
2634 	}
2635 
2636 	ivi->vf = vfidx;
2637 	ivi->qos = 0;
2638 	ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */
2639 	ivi->min_tx_rate = 0;
2640 	ivi->spoofchk = vf->spoofchk ? 1 : 0;
2641 	ivi->linkstate = vf->link_cfg;
2642 	if (vf->state == VF_ENABLED) {
2643 		/* mac and vlan are in vlan_mac objects */
2644 		if (bnx2x_validate_vf_sp_objs(bp, vf, false)) {
2645 			mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac,
2646 						0, ETH_ALEN);
2647 			vlan_obj->get_n_elements(bp, vlan_obj, 1,
2648 						 (u8 *)&ivi->vlan, 0,
2649 						 VLAN_HLEN);
2650 		}
2651 	} else {
2652 		mutex_lock(&bp->vfdb->bulletin_mutex);
2653 		/* mac */
2654 		if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID))
2655 			/* mac configured by ndo so its in bulletin board */
2656 			memcpy(&ivi->mac, bulletin->mac, ETH_ALEN);
2657 		else
2658 			/* function has not been loaded yet. Show mac as 0s */
2659 			eth_zero_addr(ivi->mac);
2660 
2661 		/* vlan */
2662 		if (bulletin->valid_bitmap & (1 << VLAN_VALID))
2663 			/* vlan configured by ndo so its in bulletin board */
2664 			memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN);
2665 		else
2666 			/* function has not been loaded yet. Show vlans as 0s */
2667 			memset(&ivi->vlan, 0, VLAN_HLEN);
2668 
2669 		mutex_unlock(&bp->vfdb->bulletin_mutex);
2670 	}
2671 
2672 	return 0;
2673 }
2674 
2675 /* New mac for VF. Consider these cases:
2676  * 1. VF hasn't been acquired yet - save the mac in local bulletin board and
2677  *    supply at acquire.
2678  * 2. VF has already been acquired but has not yet initialized - store in local
2679  *    bulletin board. mac will be posted on VF bulletin board after VF init. VF
2680  *    will configure this mac when it is ready.
2681  * 3. VF has already initialized but has not yet setup a queue - post the new
2682  *    mac on VF's bulletin board right now. VF will configure this mac when it
2683  *    is ready.
2684  * 4. VF has already set a queue - delete any macs already configured for this
2685  *    queue and manually config the new mac.
2686  * In any event, once this function has been called refuse any attempts by the
2687  * VF to configure any mac for itself except for this mac. In case of a race
2688  * where the VF fails to see the new post on its bulletin board before sending a
2689  * mac configuration request, the PF will simply fail the request and VF can try
2690  * again after consulting its bulletin board.
2691  */
2692 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
2693 {
2694 	struct bnx2x *bp = netdev_priv(dev);
2695 	int rc, q_logical_state;
2696 	struct bnx2x_virtf *vf = NULL;
2697 	struct pf_vf_bulletin_content *bulletin = NULL;
2698 
2699 	if (!is_valid_ether_addr(mac)) {
2700 		BNX2X_ERR("mac address invalid\n");
2701 		return -EINVAL;
2702 	}
2703 
2704 	/* sanity and init */
2705 	rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2706 	if (rc)
2707 		return rc;
2708 
2709 	mutex_lock(&bp->vfdb->bulletin_mutex);
2710 
2711 	/* update PF's copy of the VF's bulletin. Will no longer accept mac
2712 	 * configuration requests from vf unless match this mac
2713 	 */
2714 	bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID;
2715 	memcpy(bulletin->mac, mac, ETH_ALEN);
2716 
2717 	/* Post update on VF's bulletin board */
2718 	rc = bnx2x_post_vf_bulletin(bp, vfidx);
2719 
2720 	/* release lock before checking return code */
2721 	mutex_unlock(&bp->vfdb->bulletin_mutex);
2722 
2723 	if (rc) {
2724 		BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx);
2725 		return rc;
2726 	}
2727 
2728 	q_logical_state =
2729 		bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj));
2730 	if (vf->state == VF_ENABLED &&
2731 	    q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) {
2732 		/* configure the mac in device on this vf's queue */
2733 		unsigned long ramrod_flags = 0;
2734 		struct bnx2x_vlan_mac_obj *mac_obj;
2735 
2736 		/* User should be able to see failure reason in system logs */
2737 		if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
2738 			return -EINVAL;
2739 
2740 		/* must lock vfpf channel to protect against vf flows */
2741 		bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
2742 
2743 		/* remove existing eth macs */
2744 		mac_obj = &bnx2x_leading_vfq(vf, mac_obj);
2745 		rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true);
2746 		if (rc) {
2747 			BNX2X_ERR("failed to delete eth macs\n");
2748 			rc = -EINVAL;
2749 			goto out;
2750 		}
2751 
2752 		/* remove existing uc list macs */
2753 		rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true);
2754 		if (rc) {
2755 			BNX2X_ERR("failed to delete uc_list macs\n");
2756 			rc = -EINVAL;
2757 			goto out;
2758 		}
2759 
2760 		/* configure the new mac to device */
2761 		__set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2762 		bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true,
2763 				  BNX2X_ETH_MAC, &ramrod_flags);
2764 
2765 out:
2766 		bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
2767 	}
2768 
2769 	return rc;
2770 }
2771 
2772 static void bnx2x_set_vf_vlan_acceptance(struct bnx2x *bp,
2773 					 struct bnx2x_virtf *vf, bool accept)
2774 {
2775 	struct bnx2x_rx_mode_ramrod_params rx_ramrod;
2776 	unsigned long accept_flags;
2777 
2778 	/* need to remove/add the VF's accept_any_vlan bit */
2779 	accept_flags = bnx2x_leading_vfq(vf, accept_flags);
2780 	if (accept)
2781 		set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
2782 	else
2783 		clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
2784 
2785 	bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf,
2786 			      accept_flags);
2787 	bnx2x_leading_vfq(vf, accept_flags) = accept_flags;
2788 	bnx2x_config_rx_mode(bp, &rx_ramrod);
2789 }
2790 
2791 static int bnx2x_set_vf_vlan_filter(struct bnx2x *bp, struct bnx2x_virtf *vf,
2792 				    u16 vlan, bool add)
2793 {
2794 	struct bnx2x_vlan_mac_ramrod_params ramrod_param;
2795 	unsigned long ramrod_flags = 0;
2796 	int rc = 0;
2797 
2798 	/* configure the new vlan to device */
2799 	memset(&ramrod_param, 0, sizeof(ramrod_param));
2800 	__set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2801 	ramrod_param.vlan_mac_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2802 	ramrod_param.ramrod_flags = ramrod_flags;
2803 	ramrod_param.user_req.u.vlan.vlan = vlan;
2804 	ramrod_param.user_req.cmd = add ? BNX2X_VLAN_MAC_ADD
2805 					: BNX2X_VLAN_MAC_DEL;
2806 	rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
2807 	if (rc) {
2808 		BNX2X_ERR("failed to configure vlan\n");
2809 		return -EINVAL;
2810 	}
2811 
2812 	return 0;
2813 }
2814 
2815 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos,
2816 		      __be16 vlan_proto)
2817 {
2818 	struct pf_vf_bulletin_content *bulletin = NULL;
2819 	struct bnx2x *bp = netdev_priv(dev);
2820 	struct bnx2x_vlan_mac_obj *vlan_obj;
2821 	unsigned long vlan_mac_flags = 0;
2822 	unsigned long ramrod_flags = 0;
2823 	struct bnx2x_virtf *vf = NULL;
2824 	int i, rc;
2825 
2826 	if (vlan > 4095) {
2827 		BNX2X_ERR("illegal vlan value %d\n", vlan);
2828 		return -EINVAL;
2829 	}
2830 
2831 	if (vlan_proto != htons(ETH_P_8021Q))
2832 		return -EPROTONOSUPPORT;
2833 
2834 	DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n",
2835 	   vfidx, vlan, 0);
2836 
2837 	/* sanity and init */
2838 	rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2839 	if (rc)
2840 		return rc;
2841 
2842 	/* update PF's copy of the VF's bulletin. No point in posting the vlan
2843 	 * to the VF since it doesn't have anything to do with it. But it useful
2844 	 * to store it here in case the VF is not up yet and we can only
2845 	 * configure the vlan later when it does. Treat vlan id 0 as remove the
2846 	 * Host tag.
2847 	 */
2848 	mutex_lock(&bp->vfdb->bulletin_mutex);
2849 
2850 	if (vlan > 0)
2851 		bulletin->valid_bitmap |= 1 << VLAN_VALID;
2852 	else
2853 		bulletin->valid_bitmap &= ~(1 << VLAN_VALID);
2854 	bulletin->vlan = vlan;
2855 
2856 	/* Post update on VF's bulletin board */
2857 	rc = bnx2x_post_vf_bulletin(bp, vfidx);
2858 	if (rc)
2859 		BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx);
2860 	mutex_unlock(&bp->vfdb->bulletin_mutex);
2861 
2862 	/* is vf initialized and queue set up? */
2863 	if (vf->state != VF_ENABLED ||
2864 	    bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) !=
2865 	    BNX2X_Q_LOGICAL_STATE_ACTIVE)
2866 		return rc;
2867 
2868 	/* User should be able to see error in system logs */
2869 	if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
2870 		return -EINVAL;
2871 
2872 	/* must lock vfpf channel to protect against vf flows */
2873 	bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
2874 
2875 	/* remove existing vlans */
2876 	__set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2877 	vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2878 	rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags,
2879 				  &ramrod_flags);
2880 	if (rc) {
2881 		BNX2X_ERR("failed to delete vlans\n");
2882 		rc = -EINVAL;
2883 		goto out;
2884 	}
2885 
2886 	/* clear accept_any_vlan when HV forces vlan, otherwise
2887 	 * according to VF capabilities
2888 	 */
2889 	if (vlan || !(vf->cfg_flags & VF_CFG_VLAN_FILTER))
2890 		bnx2x_set_vf_vlan_acceptance(bp, vf, !vlan);
2891 
2892 	rc = bnx2x_set_vf_vlan_filter(bp, vf, vlan, true);
2893 	if (rc)
2894 		goto out;
2895 
2896 	/* send queue update ramrods to configure default vlan and
2897 	 * silent vlan removal
2898 	 */
2899 	for_each_vfq(vf, i) {
2900 		struct bnx2x_queue_state_params q_params = {NULL};
2901 		struct bnx2x_queue_update_params *update_params;
2902 
2903 		q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj);
2904 
2905 		/* validate the Q is UP */
2906 		if (bnx2x_get_q_logical_state(bp, q_params.q_obj) !=
2907 		    BNX2X_Q_LOGICAL_STATE_ACTIVE)
2908 			continue;
2909 
2910 		__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
2911 		q_params.cmd = BNX2X_Q_CMD_UPDATE;
2912 		update_params = &q_params.params.update;
2913 		__set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
2914 			  &update_params->update_flags);
2915 		__set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
2916 			  &update_params->update_flags);
2917 		if (vlan == 0) {
2918 			/* if vlan is 0 then we want to leave the VF traffic
2919 			 * untagged, and leave the incoming traffic untouched
2920 			 * (i.e. do not remove any vlan tags).
2921 			 */
2922 			__clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
2923 				    &update_params->update_flags);
2924 			__clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
2925 				    &update_params->update_flags);
2926 		} else {
2927 			/* configure default vlan to vf queue and set silent
2928 			 * vlan removal (the vf remains unaware of this vlan).
2929 			 */
2930 			__set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
2931 				  &update_params->update_flags);
2932 			__set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
2933 				  &update_params->update_flags);
2934 			update_params->def_vlan = vlan;
2935 			update_params->silent_removal_value =
2936 				vlan & VLAN_VID_MASK;
2937 			update_params->silent_removal_mask = VLAN_VID_MASK;
2938 		}
2939 
2940 		/* Update the Queue state */
2941 		rc = bnx2x_queue_state_change(bp, &q_params);
2942 		if (rc) {
2943 			BNX2X_ERR("Failed to configure default VLAN queue %d\n",
2944 				  i);
2945 			goto out;
2946 		}
2947 	}
2948 out:
2949 	bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
2950 
2951 	if (rc)
2952 		DP(BNX2X_MSG_IOV,
2953 		   "updated VF[%d] vlan configuration (vlan = %d)\n",
2954 		   vfidx, vlan);
2955 
2956 	return rc;
2957 }
2958 
2959 int bnx2x_set_vf_spoofchk(struct net_device *dev, int idx, bool val)
2960 {
2961 	struct bnx2x *bp = netdev_priv(dev);
2962 	struct bnx2x_virtf *vf;
2963 	int i, rc = 0;
2964 
2965 	vf = BP_VF(bp, idx);
2966 	if (!vf)
2967 		return -EINVAL;
2968 
2969 	/* nothing to do */
2970 	if (vf->spoofchk == val)
2971 		return 0;
2972 
2973 	vf->spoofchk = val ? 1 : 0;
2974 
2975 	DP(BNX2X_MSG_IOV, "%s spoofchk for VF %d\n",
2976 	   val ? "enabling" : "disabling", idx);
2977 
2978 	/* is vf initialized and queue set up? */
2979 	if (vf->state != VF_ENABLED ||
2980 	    bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) !=
2981 	    BNX2X_Q_LOGICAL_STATE_ACTIVE)
2982 		return rc;
2983 
2984 	/* User should be able to see error in system logs */
2985 	if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
2986 		return -EINVAL;
2987 
2988 	/* send queue update ramrods to configure spoofchk */
2989 	for_each_vfq(vf, i) {
2990 		struct bnx2x_queue_state_params q_params = {NULL};
2991 		struct bnx2x_queue_update_params *update_params;
2992 
2993 		q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj);
2994 
2995 		/* validate the Q is UP */
2996 		if (bnx2x_get_q_logical_state(bp, q_params.q_obj) !=
2997 		    BNX2X_Q_LOGICAL_STATE_ACTIVE)
2998 			continue;
2999 
3000 		__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
3001 		q_params.cmd = BNX2X_Q_CMD_UPDATE;
3002 		update_params = &q_params.params.update;
3003 		__set_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
3004 			  &update_params->update_flags);
3005 		if (val) {
3006 			__set_bit(BNX2X_Q_UPDATE_ANTI_SPOOF,
3007 				  &update_params->update_flags);
3008 		} else {
3009 			__clear_bit(BNX2X_Q_UPDATE_ANTI_SPOOF,
3010 				    &update_params->update_flags);
3011 		}
3012 
3013 		/* Update the Queue state */
3014 		rc = bnx2x_queue_state_change(bp, &q_params);
3015 		if (rc) {
3016 			BNX2X_ERR("Failed to %s spoofchk on VF %d - vfq %d\n",
3017 				  val ? "enable" : "disable", idx, i);
3018 			goto out;
3019 		}
3020 	}
3021 out:
3022 	if (!rc)
3023 		DP(BNX2X_MSG_IOV,
3024 		   "%s spoofchk for VF[%d]\n", val ? "Enabled" : "Disabled",
3025 		   idx);
3026 
3027 	return rc;
3028 }
3029 
3030 /* crc is the first field in the bulletin board. Compute the crc over the
3031  * entire bulletin board excluding the crc field itself. Use the length field
3032  * as the Bulletin Board was posted by a PF with possibly a different version
3033  * from the vf which will sample it. Therefore, the length is computed by the
3034  * PF and then used blindly by the VF.
3035  */
3036 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin)
3037 {
3038 	return crc32(BULLETIN_CRC_SEED,
3039 		 ((u8 *)bulletin) + sizeof(bulletin->crc),
3040 		 bulletin->length - sizeof(bulletin->crc));
3041 }
3042 
3043 /* Check for new posts on the bulletin board */
3044 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp)
3045 {
3046 	struct pf_vf_bulletin_content *bulletin;
3047 	int attempts;
3048 
3049 	/* sampling structure in mid post may result with corrupted data
3050 	 * validate crc to ensure coherency.
3051 	 */
3052 	for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) {
3053 		u32 crc;
3054 
3055 		/* sample the bulletin board */
3056 		memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin,
3057 		       sizeof(union pf_vf_bulletin));
3058 
3059 		crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content);
3060 
3061 		if (bp->shadow_bulletin.content.crc == crc)
3062 			break;
3063 
3064 		BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n",
3065 			  bp->shadow_bulletin.content.crc, crc);
3066 	}
3067 
3068 	if (attempts >= BULLETIN_ATTEMPTS) {
3069 		BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n",
3070 			  attempts);
3071 		return PFVF_BULLETIN_CRC_ERR;
3072 	}
3073 	bulletin = &bp->shadow_bulletin.content;
3074 
3075 	/* bulletin board hasn't changed since last sample */
3076 	if (bp->old_bulletin.version == bulletin->version)
3077 		return PFVF_BULLETIN_UNCHANGED;
3078 
3079 	/* the mac address in bulletin board is valid and is new */
3080 	if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID &&
3081 	    !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) {
3082 		/* update new mac to net device */
3083 		memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN);
3084 	}
3085 
3086 	if (bulletin->valid_bitmap & (1 << LINK_VALID)) {
3087 		DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n",
3088 		   bulletin->link_speed, bulletin->link_flags);
3089 
3090 		bp->vf_link_vars.line_speed = bulletin->link_speed;
3091 		bp->vf_link_vars.link_report_flags = 0;
3092 		/* Link is down */
3093 		if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)
3094 			__set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
3095 				  &bp->vf_link_vars.link_report_flags);
3096 		/* Full DUPLEX */
3097 		if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX)
3098 			__set_bit(BNX2X_LINK_REPORT_FD,
3099 				  &bp->vf_link_vars.link_report_flags);
3100 		/* Rx Flow Control is ON */
3101 		if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON)
3102 			__set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
3103 				  &bp->vf_link_vars.link_report_flags);
3104 		/* Tx Flow Control is ON */
3105 		if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON)
3106 			__set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
3107 				  &bp->vf_link_vars.link_report_flags);
3108 		__bnx2x_link_report(bp);
3109 	}
3110 
3111 	/* copy new bulletin board to bp */
3112 	memcpy(&bp->old_bulletin, bulletin,
3113 	       sizeof(struct pf_vf_bulletin_content));
3114 
3115 	return PFVF_BULLETIN_UPDATED;
3116 }
3117 
3118 void bnx2x_timer_sriov(struct bnx2x *bp)
3119 {
3120 	bnx2x_sample_bulletin(bp);
3121 
3122 	/* if channel is down we need to self destruct */
3123 	if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN)
3124 		bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
3125 				       BNX2X_MSG_IOV);
3126 }
3127 
3128 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp)
3129 {
3130 	/* vf doorbells are embedded within the regview */
3131 	return bp->regview + PXP_VF_ADDR_DB_START;
3132 }
3133 
3134 void bnx2x_vf_pci_dealloc(struct bnx2x *bp)
3135 {
3136 	BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
3137 		       sizeof(struct bnx2x_vf_mbx_msg));
3138 	BNX2X_PCI_FREE(bp->pf2vf_bulletin, bp->pf2vf_bulletin_mapping,
3139 		       sizeof(union pf_vf_bulletin));
3140 }
3141 
3142 int bnx2x_vf_pci_alloc(struct bnx2x *bp)
3143 {
3144 	mutex_init(&bp->vf2pf_mutex);
3145 
3146 	/* allocate vf2pf mailbox for vf to pf channel */
3147 	bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping,
3148 					 sizeof(struct bnx2x_vf_mbx_msg));
3149 	if (!bp->vf2pf_mbox)
3150 		goto alloc_mem_err;
3151 
3152 	/* allocate pf 2 vf bulletin board */
3153 	bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping,
3154 					     sizeof(union pf_vf_bulletin));
3155 	if (!bp->pf2vf_bulletin)
3156 		goto alloc_mem_err;
3157 
3158 	bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true);
3159 
3160 	return 0;
3161 
3162 alloc_mem_err:
3163 	bnx2x_vf_pci_dealloc(bp);
3164 	return -ENOMEM;
3165 }
3166 
3167 void bnx2x_iov_channel_down(struct bnx2x *bp)
3168 {
3169 	int vf_idx;
3170 	struct pf_vf_bulletin_content *bulletin;
3171 
3172 	if (!IS_SRIOV(bp))
3173 		return;
3174 
3175 	for_each_vf(bp, vf_idx) {
3176 		/* locate this VFs bulletin board and update the channel down
3177 		 * bit
3178 		 */
3179 		bulletin = BP_VF_BULLETIN(bp, vf_idx);
3180 		bulletin->valid_bitmap |= 1 << CHANNEL_DOWN;
3181 
3182 		/* update vf bulletin board */
3183 		bnx2x_post_vf_bulletin(bp, vf_idx);
3184 	}
3185 }
3186 
3187 void bnx2x_iov_task(struct work_struct *work)
3188 {
3189 	struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work);
3190 
3191 	if (!netif_running(bp->dev))
3192 		return;
3193 
3194 	if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR,
3195 			       &bp->iov_task_state))
3196 		bnx2x_vf_handle_flr_event(bp);
3197 
3198 	if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG,
3199 			       &bp->iov_task_state))
3200 		bnx2x_vf_mbx(bp);
3201 }
3202 
3203 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag)
3204 {
3205 	smp_mb__before_atomic();
3206 	set_bit(flag, &bp->iov_task_state);
3207 	smp_mb__after_atomic();
3208 	DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag);
3209 	queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0);
3210 }
3211