1 /* bnx2x_sriov.c: QLogic Everest network driver. 2 * 3 * Copyright 2009-2013 Broadcom Corporation 4 * Copyright 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * Unless you and QLogic execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2, available 10 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 11 * 12 * Notwithstanding the above, under no circumstances may you combine this 13 * software in any way with any other QLogic software provided under a 14 * license other than the GPL, without QLogic's express prior written 15 * consent. 16 * 17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 18 * Written by: Shmulik Ravid 19 * Ariel Elior <ariel.elior@qlogic.com> 20 * 21 */ 22 #include "bnx2x.h" 23 #include "bnx2x_init.h" 24 #include "bnx2x_cmn.h" 25 #include "bnx2x_sp.h" 26 #include <linux/crc32.h> 27 #include <linux/if_vlan.h> 28 29 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 30 struct bnx2x_virtf **vf, 31 struct pf_vf_bulletin_content **bulletin, 32 bool test_queue); 33 34 /* General service functions */ 35 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 36 u16 pf_id) 37 { 38 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 39 pf_id); 40 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 41 pf_id); 42 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 43 pf_id); 44 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 45 pf_id); 46 } 47 48 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 49 u8 enable) 50 { 51 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 52 enable); 53 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 54 enable); 55 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 56 enable); 57 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 58 enable); 59 } 60 61 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 62 { 63 int idx; 64 65 for_each_vf(bp, idx) 66 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid) 67 break; 68 return idx; 69 } 70 71 static 72 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 73 { 74 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid); 75 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL; 76 } 77 78 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf, 79 u8 igu_sb_id, u8 segment, u16 index, u8 op, 80 u8 update) 81 { 82 /* acking a VF sb through the PF - use the GRC */ 83 u32 ctl; 84 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 85 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 86 u32 func_encode = vf->abs_vfid; 87 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id; 88 struct igu_regular cmd_data = {0}; 89 90 cmd_data.sb_id_and_flags = 91 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 92 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 93 (update << IGU_REGULAR_BUPDATE_SHIFT) | 94 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 95 96 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 97 func_encode << IGU_CTRL_REG_FID_SHIFT | 98 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 99 100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 101 cmd_data.sb_id_and_flags, igu_addr_data); 102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); 103 mmiowb(); 104 barrier(); 105 106 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 107 ctl, igu_addr_ctl); 108 REG_WR(bp, igu_addr_ctl, ctl); 109 mmiowb(); 110 barrier(); 111 } 112 113 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp, 114 struct bnx2x_virtf *vf, 115 bool print_err) 116 { 117 if (!bnx2x_leading_vfq(vf, sp_initialized)) { 118 if (print_err) 119 BNX2X_ERR("Slowpath objects not yet initialized!\n"); 120 else 121 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); 122 return false; 123 } 124 return true; 125 } 126 127 /* VFOP operations states */ 128 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf, 129 struct bnx2x_queue_init_params *init_params, 130 struct bnx2x_queue_setup_params *setup_params, 131 u16 q_idx, u16 sb_idx) 132 { 133 DP(BNX2X_MSG_IOV, 134 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", 135 vf->abs_vfid, 136 q_idx, 137 sb_idx, 138 init_params->tx.sb_cq_index, 139 init_params->tx.hc_rate, 140 setup_params->flags, 141 setup_params->txq_params.traffic_type); 142 } 143 144 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf, 145 struct bnx2x_queue_init_params *init_params, 146 struct bnx2x_queue_setup_params *setup_params, 147 u16 q_idx, u16 sb_idx) 148 { 149 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params; 150 151 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" 152 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n", 153 vf->abs_vfid, 154 q_idx, 155 sb_idx, 156 init_params->rx.sb_cq_index, 157 init_params->rx.hc_rate, 158 setup_params->gen_params.mtu, 159 rxq_params->buf_sz, 160 rxq_params->sge_buf_sz, 161 rxq_params->max_sges_pkt, 162 rxq_params->tpa_agg_sz, 163 setup_params->flags, 164 rxq_params->drop_flags, 165 rxq_params->cache_line_log); 166 } 167 168 void bnx2x_vfop_qctor_prep(struct bnx2x *bp, 169 struct bnx2x_virtf *vf, 170 struct bnx2x_vf_queue *q, 171 struct bnx2x_vf_queue_construct_params *p, 172 unsigned long q_type) 173 { 174 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init; 175 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup; 176 177 /* INIT */ 178 179 /* Enable host coalescing in the transition to INIT state */ 180 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags)) 181 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags); 182 183 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags)) 184 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags); 185 186 /* FW SB ID */ 187 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 188 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 189 190 /* context */ 191 init_p->cxts[0] = q->cxt; 192 193 /* SETUP */ 194 195 /* Setup-op general parameters */ 196 setup_p->gen_params.spcl_id = vf->sp_cl_id; 197 setup_p->gen_params.stat_id = vfq_stat_id(vf, q); 198 setup_p->gen_params.fp_hsi = vf->fp_hsi; 199 200 /* Setup-op flags: 201 * collect statistics, zero statistics, local-switching, security, 202 * OV for Flex10, RSS and MCAST for leading 203 */ 204 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags)) 205 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags); 206 207 /* for VFs, enable tx switching, bd coherency, and mac address 208 * anti-spoofing 209 */ 210 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags); 211 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags); 212 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags); 213 214 /* Setup-op rx parameters */ 215 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) { 216 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params; 217 218 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q); 219 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx); 220 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid); 221 222 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags)) 223 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES; 224 } 225 226 /* Setup-op tx parameters */ 227 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) { 228 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss; 229 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 230 } 231 } 232 233 static int bnx2x_vf_queue_create(struct bnx2x *bp, 234 struct bnx2x_virtf *vf, int qid, 235 struct bnx2x_vf_queue_construct_params *qctor) 236 { 237 struct bnx2x_queue_state_params *q_params; 238 int rc = 0; 239 240 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 241 242 /* Prepare ramrod information */ 243 q_params = &qctor->qstate; 244 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj); 245 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags); 246 247 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) == 248 BNX2X_Q_LOGICAL_STATE_ACTIVE) { 249 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); 250 goto out; 251 } 252 253 /* Run Queue 'construction' ramrods */ 254 q_params->cmd = BNX2X_Q_CMD_INIT; 255 rc = bnx2x_queue_state_change(bp, q_params); 256 if (rc) 257 goto out; 258 259 memcpy(&q_params->params.setup, &qctor->prep_qsetup, 260 sizeof(struct bnx2x_queue_setup_params)); 261 q_params->cmd = BNX2X_Q_CMD_SETUP; 262 rc = bnx2x_queue_state_change(bp, q_params); 263 if (rc) 264 goto out; 265 266 /* enable interrupts */ 267 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)), 268 USTORM_ID, 0, IGU_INT_ENABLE, 0); 269 out: 270 return rc; 271 } 272 273 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf, 274 int qid) 275 { 276 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT, 277 BNX2X_Q_CMD_TERMINATE, 278 BNX2X_Q_CMD_CFC_DEL}; 279 struct bnx2x_queue_state_params q_params; 280 int rc, i; 281 282 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 283 284 /* Prepare ramrod information */ 285 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params)); 286 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 287 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 288 289 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) == 290 BNX2X_Q_LOGICAL_STATE_STOPPED) { 291 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); 292 goto out; 293 } 294 295 /* Run Queue 'destruction' ramrods */ 296 for (i = 0; i < ARRAY_SIZE(cmds); i++) { 297 q_params.cmd = cmds[i]; 298 rc = bnx2x_queue_state_change(bp, &q_params); 299 if (rc) { 300 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]); 301 return rc; 302 } 303 } 304 out: 305 /* Clean Context */ 306 if (bnx2x_vfq(vf, qid, cxt)) { 307 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0; 308 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0; 309 } 310 311 return 0; 312 } 313 314 static void 315 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid) 316 { 317 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 318 if (vf) { 319 /* the first igu entry belonging to VFs of this PF */ 320 if (!BP_VFDB(bp)->first_vf_igu_entry) 321 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id; 322 323 /* the first igu entry belonging to this VF */ 324 if (!vf_sb_count(vf)) 325 vf->igu_base_id = igu_sb_id; 326 327 ++vf_sb_count(vf); 328 ++vf->sb_count; 329 } 330 BP_VFDB(bp)->vf_sbs_pool++; 331 } 332 333 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp, 334 struct bnx2x_vlan_mac_obj *obj, 335 atomic_t *counter) 336 { 337 struct list_head *pos; 338 int read_lock; 339 int cnt = 0; 340 341 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj); 342 if (read_lock) 343 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); 344 345 list_for_each(pos, &obj->head) 346 cnt++; 347 348 if (!read_lock) 349 bnx2x_vlan_mac_h_read_unlock(bp, obj); 350 351 atomic_set(counter, cnt); 352 } 353 354 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf, 355 int qid, bool drv_only, int type) 356 { 357 struct bnx2x_vlan_mac_ramrod_params ramrod; 358 int rc; 359 360 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, 361 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : 362 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); 363 364 /* Prepare ramrod params */ 365 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 366 if (type == BNX2X_VF_FILTER_VLAN_MAC) { 367 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 368 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); 369 } else if (type == BNX2X_VF_FILTER_MAC) { 370 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 371 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 372 } else { 373 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 374 } 375 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL; 376 377 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 378 if (drv_only) 379 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 380 else 381 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 382 383 /* Start deleting */ 384 rc = ramrod.vlan_mac_obj->delete_all(bp, 385 ramrod.vlan_mac_obj, 386 &ramrod.user_req.vlan_mac_flags, 387 &ramrod.ramrod_flags); 388 if (rc) { 389 BNX2X_ERR("Failed to delete all %s\n", 390 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : 391 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); 392 return rc; 393 } 394 395 return 0; 396 } 397 398 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp, 399 struct bnx2x_virtf *vf, int qid, 400 struct bnx2x_vf_mac_vlan_filter *filter, 401 bool drv_only) 402 { 403 struct bnx2x_vlan_mac_ramrod_params ramrod; 404 int rc; 405 406 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", 407 vf->abs_vfid, filter->add ? "Adding" : "Deleting", 408 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MAC" : 409 (filter->type == BNX2X_VF_FILTER_MAC) ? "MAC" : "VLAN"); 410 411 /* Prepare ramrod params */ 412 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 413 if (filter->type == BNX2X_VF_FILTER_VLAN_MAC) { 414 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); 415 ramrod.user_req.u.vlan.vlan = filter->vid; 416 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 417 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 418 } else if (filter->type == BNX2X_VF_FILTER_VLAN) { 419 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 420 ramrod.user_req.u.vlan.vlan = filter->vid; 421 } else { 422 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 423 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 424 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 425 } 426 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD : 427 BNX2X_VLAN_MAC_DEL; 428 429 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 430 if (drv_only) 431 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 432 else 433 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 434 435 /* Add/Remove the filter */ 436 rc = bnx2x_config_vlan_mac(bp, &ramrod); 437 if (rc == -EEXIST) 438 return 0; 439 if (rc) { 440 BNX2X_ERR("Failed to %s %s\n", 441 filter->add ? "add" : "delete", 442 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? 443 "VLAN-MAC" : 444 (filter->type == BNX2X_VF_FILTER_MAC) ? 445 "MAC" : "VLAN"); 446 return rc; 447 } 448 449 filter->applied = true; 450 451 return 0; 452 } 453 454 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf, 455 struct bnx2x_vf_mac_vlan_filters *filters, 456 int qid, bool drv_only) 457 { 458 int rc = 0, i; 459 460 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 461 462 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 463 return -EINVAL; 464 465 /* Prepare ramrod params */ 466 for (i = 0; i < filters->count; i++) { 467 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, 468 &filters->filters[i], drv_only); 469 if (rc) 470 break; 471 } 472 473 /* Rollback if needed */ 474 if (i != filters->count) { 475 BNX2X_ERR("Managed only %d/%d filters - rolling back\n", 476 i, filters->count); 477 while (--i >= 0) { 478 if (!filters->filters[i].applied) 479 continue; 480 filters->filters[i].add = !filters->filters[i].add; 481 bnx2x_vf_mac_vlan_config(bp, vf, qid, 482 &filters->filters[i], 483 drv_only); 484 } 485 } 486 487 /* It's our responsibility to free the filters */ 488 kfree(filters); 489 490 return rc; 491 } 492 493 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid, 494 struct bnx2x_vf_queue_construct_params *qctor) 495 { 496 int rc; 497 498 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 499 500 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor); 501 if (rc) 502 goto op_err; 503 504 /* Schedule the configuration of any pending vlan filters */ 505 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN, 506 BNX2X_MSG_IOV); 507 return 0; 508 op_err: 509 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 510 return rc; 511 } 512 513 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf, 514 int qid) 515 { 516 int rc; 517 518 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 519 520 /* If needed, clean the filtering data base */ 521 if ((qid == LEADING_IDX) && 522 bnx2x_validate_vf_sp_objs(bp, vf, false)) { 523 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 524 BNX2X_VF_FILTER_VLAN_MAC); 525 if (rc) 526 goto op_err; 527 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 528 BNX2X_VF_FILTER_VLAN); 529 if (rc) 530 goto op_err; 531 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 532 BNX2X_VF_FILTER_MAC); 533 if (rc) 534 goto op_err; 535 } 536 537 /* Terminate queue */ 538 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) { 539 struct bnx2x_queue_state_params qstate; 540 541 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 542 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 543 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED; 544 qstate.cmd = BNX2X_Q_CMD_TERMINATE; 545 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 546 rc = bnx2x_queue_state_change(bp, &qstate); 547 if (rc) 548 goto op_err; 549 } 550 551 return 0; 552 op_err: 553 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 554 return rc; 555 } 556 557 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf, 558 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only) 559 { 560 struct bnx2x_mcast_list_elem *mc = NULL; 561 struct bnx2x_mcast_ramrod_params mcast; 562 int rc, i; 563 564 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 565 566 /* Prepare Multicast command */ 567 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params)); 568 mcast.mcast_obj = &vf->mcast_obj; 569 if (drv_only) 570 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags); 571 else 572 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags); 573 if (mc_num) { 574 mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem), 575 GFP_KERNEL); 576 if (!mc) { 577 BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n"); 578 return -ENOMEM; 579 } 580 } 581 582 if (mc_num) { 583 INIT_LIST_HEAD(&mcast.mcast_list); 584 for (i = 0; i < mc_num; i++) { 585 mc[i].mac = mcasts[i]; 586 list_add_tail(&mc[i].link, 587 &mcast.mcast_list); 588 } 589 590 /* add new mcasts */ 591 mcast.mcast_list_len = mc_num; 592 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_SET); 593 if (rc) 594 BNX2X_ERR("Failed to set multicasts\n"); 595 } else { 596 /* clear existing mcasts */ 597 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL); 598 if (rc) 599 BNX2X_ERR("Failed to remove multicasts\n"); 600 } 601 602 kfree(mc); 603 604 return rc; 605 } 606 607 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid, 608 struct bnx2x_rx_mode_ramrod_params *ramrod, 609 struct bnx2x_virtf *vf, 610 unsigned long accept_flags) 611 { 612 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid); 613 614 memset(ramrod, 0, sizeof(*ramrod)); 615 ramrod->cid = vfq->cid; 616 ramrod->cl_id = vfq_cl_id(vf, vfq); 617 ramrod->rx_mode_obj = &bp->rx_mode_obj; 618 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid); 619 ramrod->rx_accept_flags = accept_flags; 620 ramrod->tx_accept_flags = accept_flags; 621 ramrod->pstate = &vf->filter_state; 622 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING; 623 624 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 625 set_bit(RAMROD_RX, &ramrod->ramrod_flags); 626 set_bit(RAMROD_TX, &ramrod->ramrod_flags); 627 628 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2); 629 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2); 630 } 631 632 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf, 633 int qid, unsigned long accept_flags) 634 { 635 struct bnx2x_rx_mode_ramrod_params ramrod; 636 637 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 638 639 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags); 640 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 641 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags; 642 return bnx2x_config_rx_mode(bp, &ramrod); 643 } 644 645 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid) 646 { 647 int rc; 648 649 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 650 651 /* Remove all classification configuration for leading queue */ 652 if (qid == LEADING_IDX) { 653 rc = bnx2x_vf_rxmode(bp, vf, qid, 0); 654 if (rc) 655 goto op_err; 656 657 /* Remove filtering if feasible */ 658 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) { 659 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 660 false, 661 BNX2X_VF_FILTER_VLAN_MAC); 662 if (rc) 663 goto op_err; 664 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 665 false, 666 BNX2X_VF_FILTER_VLAN); 667 if (rc) 668 goto op_err; 669 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 670 false, 671 BNX2X_VF_FILTER_MAC); 672 if (rc) 673 goto op_err; 674 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false); 675 if (rc) 676 goto op_err; 677 } 678 } 679 680 /* Destroy queue */ 681 rc = bnx2x_vf_queue_destroy(bp, vf, qid); 682 if (rc) 683 goto op_err; 684 return rc; 685 op_err: 686 BNX2X_ERR("vf[%d:%d] error: rc %d\n", 687 vf->abs_vfid, qid, rc); 688 return rc; 689 } 690 691 /* VF enable primitives 692 * when pretend is required the caller is responsible 693 * for calling pretend prior to calling these routines 694 */ 695 696 /* internal vf enable - until vf is enabled internally all transactions 697 * are blocked. This routine should always be called last with pretend. 698 */ 699 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable) 700 { 701 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); 702 } 703 704 /* clears vf error in all semi blocks */ 705 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid) 706 { 707 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); 708 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); 709 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); 710 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); 711 } 712 713 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid) 714 { 715 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5; 716 u32 was_err_reg = 0; 717 718 switch (was_err_group) { 719 case 0: 720 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR; 721 break; 722 case 1: 723 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR; 724 break; 725 case 2: 726 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR; 727 break; 728 case 3: 729 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR; 730 break; 731 } 732 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); 733 } 734 735 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf) 736 { 737 int i; 738 u32 val; 739 740 /* Set VF masks and configuration - pretend */ 741 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 742 743 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 744 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 745 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 746 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 747 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 748 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 749 750 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 751 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); 752 val &= ~IGU_VF_CONF_PARENT_MASK; 753 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; 754 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 755 756 DP(BNX2X_MSG_IOV, 757 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n", 758 vf->abs_vfid, val); 759 760 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 761 762 /* iterate over all queues, clear sb consumer */ 763 for (i = 0; i < vf_sb_count(vf); i++) { 764 u8 igu_sb_id = vf_igu_sb(vf, i); 765 766 /* zero prod memory */ 767 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); 768 769 /* clear sb state machine */ 770 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id, 771 false /* VF */); 772 773 /* disable + update */ 774 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0, 775 IGU_INT_DISABLE, 1); 776 } 777 } 778 779 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid) 780 { 781 /* set the VF-PF association in the FW */ 782 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp)); 783 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1); 784 785 /* clear vf errors*/ 786 bnx2x_vf_semi_clear_err(bp, abs_vfid); 787 bnx2x_vf_pglue_clear_err(bp, abs_vfid); 788 789 /* internal vf-enable - pretend */ 790 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid)); 791 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); 792 bnx2x_vf_enable_internal(bp, true); 793 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 794 } 795 796 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf) 797 { 798 /* Reset vf in IGU interrupts are still disabled */ 799 bnx2x_vf_igu_reset(bp, vf); 800 801 /* pretend to enable the vf with the PBF */ 802 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 803 REG_WR(bp, PBF_REG_DISABLE_VF, 0); 804 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 805 } 806 807 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) 808 { 809 struct pci_dev *dev; 810 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 811 812 if (!vf) 813 return false; 814 815 dev = pci_get_bus_and_slot(vf->bus, vf->devfn); 816 if (dev) 817 return bnx2x_is_pcie_pending(dev); 818 return false; 819 } 820 821 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid) 822 { 823 /* Verify no pending pci transactions */ 824 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid)) 825 BNX2X_ERR("PCIE Transactions still pending\n"); 826 827 return 0; 828 } 829 830 /* must be called after the number of PF queues and the number of VFs are 831 * both known 832 */ 833 static void 834 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 835 { 836 struct vf_pf_resc_request *resc = &vf->alloc_resc; 837 838 /* will be set only during VF-ACQUIRE */ 839 resc->num_rxqs = 0; 840 resc->num_txqs = 0; 841 842 resc->num_mac_filters = VF_MAC_CREDIT_CNT; 843 resc->num_vlan_filters = VF_VLAN_CREDIT_CNT; 844 845 /* no real limitation */ 846 resc->num_mc_filters = 0; 847 848 /* num_sbs already set */ 849 resc->num_sbs = vf->sb_count; 850 } 851 852 /* FLR routines: */ 853 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 854 { 855 /* reset the state variables */ 856 bnx2x_iov_static_resc(bp, vf); 857 vf->state = VF_FREE; 858 } 859 860 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf) 861 { 862 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 863 864 /* DQ usage counter */ 865 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 866 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT, 867 "DQ VF usage counter timed out", 868 poll_cnt); 869 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 870 871 /* FW cleanup command - poll for the results */ 872 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid), 873 poll_cnt)) 874 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid); 875 876 /* verify TX hw is flushed */ 877 bnx2x_tx_hw_flushed(bp, poll_cnt); 878 } 879 880 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf) 881 { 882 int rc, i; 883 884 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 885 886 /* the cleanup operations are valid if and only if the VF 887 * was first acquired. 888 */ 889 for (i = 0; i < vf_rxq_count(vf); i++) { 890 rc = bnx2x_vf_queue_flr(bp, vf, i); 891 if (rc) 892 goto out; 893 } 894 895 /* remove multicasts */ 896 bnx2x_vf_mcast(bp, vf, NULL, 0, true); 897 898 /* dispatch final cleanup and wait for HW queues to flush */ 899 bnx2x_vf_flr_clnup_hw(bp, vf); 900 901 /* release VF resources */ 902 bnx2x_vf_free_resc(bp, vf); 903 904 vf->malicious = false; 905 906 /* re-open the mailbox */ 907 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 908 return; 909 out: 910 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n", 911 vf->abs_vfid, i, rc); 912 } 913 914 static void bnx2x_vf_flr_clnup(struct bnx2x *bp) 915 { 916 struct bnx2x_virtf *vf; 917 int i; 918 919 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) { 920 /* VF should be RESET & in FLR cleanup states */ 921 if (bnx2x_vf(bp, i, state) != VF_RESET || 922 !bnx2x_vf(bp, i, flr_clnup_stage)) 923 continue; 924 925 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", 926 i, BNX2X_NR_VIRTFN(bp)); 927 928 vf = BP_VF(bp, i); 929 930 /* lock the vf pf channel */ 931 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 932 933 /* invoke the VF FLR SM */ 934 bnx2x_vf_flr(bp, vf); 935 936 /* mark the VF to be ACKED and continue */ 937 vf->flr_clnup_stage = false; 938 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 939 } 940 941 /* Acknowledge the handled VFs. 942 * we are acknowledge all the vfs which an flr was requested for, even 943 * if amongst them there are such that we never opened, since the mcp 944 * will interrupt us immediately again if we only ack some of the bits, 945 * resulting in an endless loop. This can happen for example in KVM 946 * where an 'all ones' flr request is sometimes given by hyper visor 947 */ 948 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", 949 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 950 for (i = 0; i < FLRD_VFS_DWORDS; i++) 951 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 952 bp->vfdb->flrd_vfs[i]); 953 954 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0); 955 956 /* clear the acked bits - better yet if the MCP implemented 957 * write to clear semantics 958 */ 959 for (i = 0; i < FLRD_VFS_DWORDS; i++) 960 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0); 961 } 962 963 void bnx2x_vf_handle_flr_event(struct bnx2x *bp) 964 { 965 int i; 966 967 /* Read FLR'd VFs */ 968 for (i = 0; i < FLRD_VFS_DWORDS; i++) 969 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]); 970 971 DP(BNX2X_MSG_MCP, 972 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n", 973 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 974 975 for_each_vf(bp, i) { 976 struct bnx2x_virtf *vf = BP_VF(bp, i); 977 u32 reset = 0; 978 979 if (vf->abs_vfid < 32) 980 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid); 981 else 982 reset = bp->vfdb->flrd_vfs[1] & 983 (1 << (vf->abs_vfid - 32)); 984 985 if (reset) { 986 /* set as reset and ready for cleanup */ 987 vf->state = VF_RESET; 988 vf->flr_clnup_stage = true; 989 990 DP(BNX2X_MSG_IOV, 991 "Initiating Final cleanup for VF %d\n", 992 vf->abs_vfid); 993 } 994 } 995 996 /* do the FLR cleanup for all marked VFs*/ 997 bnx2x_vf_flr_clnup(bp); 998 } 999 1000 /* IOV global initialization routines */ 1001 void bnx2x_iov_init_dq(struct bnx2x *bp) 1002 { 1003 if (!IS_SRIOV(bp)) 1004 return; 1005 1006 /* Set the DQ such that the CID reflect the abs_vfid */ 1007 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); 1008 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 1009 1010 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to 1011 * the PF L2 queues 1012 */ 1013 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 1014 1015 /* The VF window size is the log2 of the max number of CIDs per VF */ 1016 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 1017 1018 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 1019 * the Pf doorbell size although the 2 are independent. 1020 */ 1021 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); 1022 1023 /* No security checks for now - 1024 * configure single rule (out of 16) mask = 0x1, value = 0x0, 1025 * CID range 0 - 0x1ffff 1026 */ 1027 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); 1028 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); 1029 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 1030 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 1031 1032 /* set the VF doorbell threshold. This threshold represents the amount 1033 * of doorbells allowed in the main DORQ fifo for a specific VF. 1034 */ 1035 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64); 1036 } 1037 1038 void bnx2x_iov_init_dmae(struct bnx2x *bp) 1039 { 1040 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV)) 1041 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); 1042 } 1043 1044 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid) 1045 { 1046 struct pci_dev *dev = bp->pdev; 1047 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1048 1049 return dev->bus->number + ((dev->devfn + iov->offset + 1050 iov->stride * vfid) >> 8); 1051 } 1052 1053 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid) 1054 { 1055 struct pci_dev *dev = bp->pdev; 1056 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1057 1058 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff; 1059 } 1060 1061 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf) 1062 { 1063 int i, n; 1064 struct pci_dev *dev = bp->pdev; 1065 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1066 1067 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) { 1068 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i); 1069 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i); 1070 1071 size /= iov->total; 1072 vf->bars[n].bar = start + size * vf->abs_vfid; 1073 vf->bars[n].size = size; 1074 } 1075 } 1076 1077 static int 1078 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp) 1079 { 1080 int sb_id; 1081 u32 val; 1082 u8 fid, current_pf = 0; 1083 1084 /* IGU in normal mode - read CAM */ 1085 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) { 1086 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); 1087 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 1088 continue; 1089 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); 1090 if (fid & IGU_FID_ENCODE_IS_PF) 1091 current_pf = fid & IGU_FID_PF_NUM_MASK; 1092 else if (current_pf == BP_FUNC(bp)) 1093 bnx2x_vf_set_igu_info(bp, sb_id, 1094 (fid & IGU_FID_VF_NUM_MASK)); 1095 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", 1096 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"), 1097 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) : 1098 (fid & IGU_FID_VF_NUM_MASK)), sb_id, 1099 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); 1100 } 1101 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); 1102 return BP_VFDB(bp)->vf_sbs_pool; 1103 } 1104 1105 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp) 1106 { 1107 if (bp->vfdb) { 1108 kfree(bp->vfdb->vfqs); 1109 kfree(bp->vfdb->vfs); 1110 kfree(bp->vfdb); 1111 } 1112 bp->vfdb = NULL; 1113 } 1114 1115 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1116 { 1117 int pos; 1118 struct pci_dev *dev = bp->pdev; 1119 1120 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 1121 if (!pos) { 1122 BNX2X_ERR("failed to find SRIOV capability in device\n"); 1123 return -ENODEV; 1124 } 1125 1126 iov->pos = pos; 1127 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); 1128 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); 1129 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total); 1130 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial); 1131 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset); 1132 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride); 1133 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); 1134 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); 1135 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); 1136 1137 return 0; 1138 } 1139 1140 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1141 { 1142 u32 val; 1143 1144 /* read the SRIOV capability structure 1145 * The fields can be read via configuration read or 1146 * directly from the device (starting at offset PCICFG_OFFSET) 1147 */ 1148 if (bnx2x_sriov_pci_cfg_info(bp, iov)) 1149 return -ENODEV; 1150 1151 /* get the number of SRIOV bars */ 1152 iov->nres = 0; 1153 1154 /* read the first_vfid */ 1155 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 1156 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) 1157 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp)); 1158 1159 DP(BNX2X_MSG_IOV, 1160 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n", 1161 BP_FUNC(bp), 1162 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total, 1163 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz); 1164 1165 return 0; 1166 } 1167 1168 /* must be called after PF bars are mapped */ 1169 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, 1170 int num_vfs_param) 1171 { 1172 int err, i; 1173 struct bnx2x_sriov *iov; 1174 struct pci_dev *dev = bp->pdev; 1175 1176 bp->vfdb = NULL; 1177 1178 /* verify is pf */ 1179 if (IS_VF(bp)) 1180 return 0; 1181 1182 /* verify sriov capability is present in configuration space */ 1183 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV)) 1184 return 0; 1185 1186 /* verify chip revision */ 1187 if (CHIP_IS_E1x(bp)) 1188 return 0; 1189 1190 /* check if SRIOV support is turned off */ 1191 if (!num_vfs_param) 1192 return 0; 1193 1194 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */ 1195 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) { 1196 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n", 1197 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID); 1198 return 0; 1199 } 1200 1201 /* SRIOV can be enabled only with MSIX */ 1202 if (int_mode_param == BNX2X_INT_MODE_MSI || 1203 int_mode_param == BNX2X_INT_MODE_INTX) { 1204 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); 1205 return 0; 1206 } 1207 1208 err = -EIO; 1209 /* verify ari is enabled */ 1210 if (!pci_ari_enabled(bp->pdev->bus)) { 1211 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); 1212 return 0; 1213 } 1214 1215 /* verify igu is in normal mode */ 1216 if (CHIP_INT_MODE_IS_BC(bp)) { 1217 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); 1218 return 0; 1219 } 1220 1221 /* allocate the vfs database */ 1222 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL); 1223 if (!bp->vfdb) { 1224 BNX2X_ERR("failed to allocate vf database\n"); 1225 err = -ENOMEM; 1226 goto failed; 1227 } 1228 1229 /* get the sriov info - Linux already collected all the pertinent 1230 * information, however the sriov structure is for the private use 1231 * of the pci module. Also we want this information regardless 1232 * of the hyper-visor. 1233 */ 1234 iov = &(bp->vfdb->sriov); 1235 err = bnx2x_sriov_info(bp, iov); 1236 if (err) 1237 goto failed; 1238 1239 /* SR-IOV capability was enabled but there are no VFs*/ 1240 if (iov->total == 0) 1241 goto failed; 1242 1243 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); 1244 1245 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", 1246 num_vfs_param, iov->nr_virtfn); 1247 1248 /* allocate the vf array */ 1249 bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * 1250 BNX2X_NR_VIRTFN(bp), GFP_KERNEL); 1251 if (!bp->vfdb->vfs) { 1252 BNX2X_ERR("failed to allocate vf array\n"); 1253 err = -ENOMEM; 1254 goto failed; 1255 } 1256 1257 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */ 1258 for_each_vf(bp, i) { 1259 bnx2x_vf(bp, i, index) = i; 1260 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i; 1261 bnx2x_vf(bp, i, state) = VF_FREE; 1262 mutex_init(&bnx2x_vf(bp, i, op_mutex)); 1263 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE; 1264 } 1265 1266 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */ 1267 if (!bnx2x_get_vf_igu_cam_info(bp)) { 1268 BNX2X_ERR("No entries in IGU CAM for vfs\n"); 1269 err = -EINVAL; 1270 goto failed; 1271 } 1272 1273 /* allocate the queue arrays for all VFs */ 1274 bp->vfdb->vfqs = kzalloc( 1275 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue), 1276 GFP_KERNEL); 1277 1278 if (!bp->vfdb->vfqs) { 1279 BNX2X_ERR("failed to allocate vf queue array\n"); 1280 err = -ENOMEM; 1281 goto failed; 1282 } 1283 1284 /* Prepare the VFs event synchronization mechanism */ 1285 mutex_init(&bp->vfdb->event_mutex); 1286 1287 mutex_init(&bp->vfdb->bulletin_mutex); 1288 1289 if (SHMEM2_HAS(bp, sriov_switch_mode)) 1290 SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB); 1291 1292 return 0; 1293 failed: 1294 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err); 1295 __bnx2x_iov_free_vfdb(bp); 1296 return err; 1297 } 1298 1299 void bnx2x_iov_remove_one(struct bnx2x *bp) 1300 { 1301 int vf_idx; 1302 1303 /* if SRIOV is not enabled there's nothing to do */ 1304 if (!IS_SRIOV(bp)) 1305 return; 1306 1307 bnx2x_disable_sriov(bp); 1308 1309 /* disable access to all VFs */ 1310 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) { 1311 bnx2x_pretend_func(bp, 1312 HW_VF_HANDLE(bp, 1313 bp->vfdb->sriov.first_vf_in_pf + 1314 vf_idx)); 1315 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", 1316 bp->vfdb->sriov.first_vf_in_pf + vf_idx); 1317 bnx2x_vf_enable_internal(bp, 0); 1318 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1319 } 1320 1321 /* free vf database */ 1322 __bnx2x_iov_free_vfdb(bp); 1323 } 1324 1325 void bnx2x_iov_free_mem(struct bnx2x *bp) 1326 { 1327 int i; 1328 1329 if (!IS_SRIOV(bp)) 1330 return; 1331 1332 /* free vfs hw contexts */ 1333 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1334 struct hw_dma *cxt = &bp->vfdb->context[i]; 1335 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size); 1336 } 1337 1338 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr, 1339 BP_VFDB(bp)->sp_dma.mapping, 1340 BP_VFDB(bp)->sp_dma.size); 1341 1342 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr, 1343 BP_VF_MBX_DMA(bp)->mapping, 1344 BP_VF_MBX_DMA(bp)->size); 1345 1346 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr, 1347 BP_VF_BULLETIN_DMA(bp)->mapping, 1348 BP_VF_BULLETIN_DMA(bp)->size); 1349 } 1350 1351 int bnx2x_iov_alloc_mem(struct bnx2x *bp) 1352 { 1353 size_t tot_size; 1354 int i, rc = 0; 1355 1356 if (!IS_SRIOV(bp)) 1357 return rc; 1358 1359 /* allocate vfs hw contexts */ 1360 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) * 1361 BNX2X_CIDS_PER_VF * sizeof(union cdu_context); 1362 1363 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1364 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i); 1365 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ); 1366 1367 if (cxt->size) { 1368 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size); 1369 if (!cxt->addr) 1370 goto alloc_mem_err; 1371 } else { 1372 cxt->addr = NULL; 1373 cxt->mapping = 0; 1374 } 1375 tot_size -= cxt->size; 1376 } 1377 1378 /* allocate vfs ramrods dma memory - client_init and set_mac */ 1379 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp); 1380 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping, 1381 tot_size); 1382 if (!BP_VFDB(bp)->sp_dma.addr) 1383 goto alloc_mem_err; 1384 BP_VFDB(bp)->sp_dma.size = tot_size; 1385 1386 /* allocate mailboxes */ 1387 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE; 1388 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping, 1389 tot_size); 1390 if (!BP_VF_MBX_DMA(bp)->addr) 1391 goto alloc_mem_err; 1392 1393 BP_VF_MBX_DMA(bp)->size = tot_size; 1394 1395 /* allocate local bulletin boards */ 1396 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE; 1397 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping, 1398 tot_size); 1399 if (!BP_VF_BULLETIN_DMA(bp)->addr) 1400 goto alloc_mem_err; 1401 1402 BP_VF_BULLETIN_DMA(bp)->size = tot_size; 1403 1404 return 0; 1405 1406 alloc_mem_err: 1407 return -ENOMEM; 1408 } 1409 1410 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf, 1411 struct bnx2x_vf_queue *q) 1412 { 1413 u8 cl_id = vfq_cl_id(vf, q); 1414 u8 func_id = FW_VF_HANDLE(vf->abs_vfid); 1415 unsigned long q_type = 0; 1416 1417 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1418 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1419 1420 /* Queue State object */ 1421 bnx2x_init_queue_obj(bp, &q->sp_obj, 1422 cl_id, &q->cid, 1, func_id, 1423 bnx2x_vf_sp(bp, vf, q_data), 1424 bnx2x_vf_sp_map(bp, vf, q_data), 1425 q_type); 1426 1427 /* sp indication is set only when vlan/mac/etc. are initialized */ 1428 q->sp_initialized = false; 1429 1430 DP(BNX2X_MSG_IOV, 1431 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n", 1432 vf->abs_vfid, q->sp_obj.func_id, q->cid); 1433 } 1434 1435 static int bnx2x_max_speed_cap(struct bnx2x *bp) 1436 { 1437 u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)]; 1438 1439 if (supported & 1440 (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full)) 1441 return 20000; 1442 1443 return 10000; /* assume lowest supported speed is 10G */ 1444 } 1445 1446 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx) 1447 { 1448 struct bnx2x_link_report_data *state = &bp->last_reported_link; 1449 struct pf_vf_bulletin_content *bulletin; 1450 struct bnx2x_virtf *vf; 1451 bool update = true; 1452 int rc = 0; 1453 1454 /* sanity and init */ 1455 rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false); 1456 if (rc) 1457 return rc; 1458 1459 mutex_lock(&bp->vfdb->bulletin_mutex); 1460 1461 if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) { 1462 bulletin->valid_bitmap |= 1 << LINK_VALID; 1463 1464 bulletin->link_speed = state->line_speed; 1465 bulletin->link_flags = 0; 1466 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1467 &state->link_report_flags)) 1468 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1469 if (test_bit(BNX2X_LINK_REPORT_FD, 1470 &state->link_report_flags)) 1471 bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX; 1472 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON, 1473 &state->link_report_flags)) 1474 bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON; 1475 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON, 1476 &state->link_report_flags)) 1477 bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON; 1478 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE && 1479 !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1480 bulletin->valid_bitmap |= 1 << LINK_VALID; 1481 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1482 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE && 1483 (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1484 bulletin->valid_bitmap |= 1 << LINK_VALID; 1485 bulletin->link_speed = bnx2x_max_speed_cap(bp); 1486 bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN; 1487 } else { 1488 update = false; 1489 } 1490 1491 if (update) { 1492 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV, 1493 "vf %d mode %u speed %d flags %x\n", idx, 1494 vf->link_cfg, bulletin->link_speed, bulletin->link_flags); 1495 1496 /* Post update on VF's bulletin board */ 1497 rc = bnx2x_post_vf_bulletin(bp, idx); 1498 if (rc) { 1499 BNX2X_ERR("failed to update VF[%d] bulletin\n", idx); 1500 goto out; 1501 } 1502 } 1503 1504 out: 1505 mutex_unlock(&bp->vfdb->bulletin_mutex); 1506 return rc; 1507 } 1508 1509 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state) 1510 { 1511 struct bnx2x *bp = netdev_priv(dev); 1512 struct bnx2x_virtf *vf = BP_VF(bp, idx); 1513 1514 if (!vf) 1515 return -EINVAL; 1516 1517 if (vf->link_cfg == link_state) 1518 return 0; /* nothing todo */ 1519 1520 vf->link_cfg = link_state; 1521 1522 return bnx2x_iov_link_update_vf(bp, idx); 1523 } 1524 1525 void bnx2x_iov_link_update(struct bnx2x *bp) 1526 { 1527 int vfid; 1528 1529 if (!IS_SRIOV(bp)) 1530 return; 1531 1532 for_each_vf(bp, vfid) 1533 bnx2x_iov_link_update_vf(bp, vfid); 1534 } 1535 1536 /* called by bnx2x_nic_load */ 1537 int bnx2x_iov_nic_init(struct bnx2x *bp) 1538 { 1539 int vfid; 1540 1541 if (!IS_SRIOV(bp)) { 1542 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); 1543 return 0; 1544 } 1545 1546 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); 1547 1548 /* let FLR complete ... */ 1549 msleep(100); 1550 1551 /* initialize vf database */ 1552 for_each_vf(bp, vfid) { 1553 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1554 1555 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) * 1556 BNX2X_CIDS_PER_VF; 1557 1558 union cdu_context *base_cxt = (union cdu_context *) 1559 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 1560 (base_vf_cid & (ILT_PAGE_CIDS-1)); 1561 1562 DP(BNX2X_MSG_IOV, 1563 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n", 1564 vf->abs_vfid, vf_sb_count(vf), base_vf_cid, 1565 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt); 1566 1567 /* init statically provisioned resources */ 1568 bnx2x_iov_static_resc(bp, vf); 1569 1570 /* queues are initialized during VF-ACQUIRE */ 1571 vf->filter_state = 0; 1572 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id); 1573 1574 bnx2x_init_credit_pool(&vf->vf_vlans_pool, 0, 1575 vf_vlan_rules_cnt(vf)); 1576 bnx2x_init_credit_pool(&vf->vf_macs_pool, 0, 1577 vf_mac_rules_cnt(vf)); 1578 1579 /* init mcast object - This object will be re-initialized 1580 * during VF-ACQUIRE with the proper cl_id and cid. 1581 * It needs to be initialized here so that it can be safely 1582 * handled by a subsequent FLR flow. 1583 */ 1584 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF, 1585 0xFF, 0xFF, 0xFF, 1586 bnx2x_vf_sp(bp, vf, mcast_rdata), 1587 bnx2x_vf_sp_map(bp, vf, mcast_rdata), 1588 BNX2X_FILTER_MCAST_PENDING, 1589 &vf->filter_state, 1590 BNX2X_OBJ_TYPE_RX_TX); 1591 1592 /* set the mailbox message addresses */ 1593 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *) 1594 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid * 1595 MBX_MSG_ALIGNED_SIZE); 1596 1597 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping + 1598 vfid * MBX_MSG_ALIGNED_SIZE; 1599 1600 /* Enable vf mailbox */ 1601 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 1602 } 1603 1604 /* Final VF init */ 1605 for_each_vf(bp, vfid) { 1606 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1607 1608 /* fill in the BDF and bars */ 1609 vf->bus = bnx2x_vf_bus(bp, vfid); 1610 vf->devfn = bnx2x_vf_devfn(bp, vfid); 1611 bnx2x_vf_set_bars(bp, vf); 1612 1613 DP(BNX2X_MSG_IOV, 1614 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n", 1615 vf->abs_vfid, vf->bus, vf->devfn, 1616 (unsigned)vf->bars[0].bar, vf->bars[0].size, 1617 (unsigned)vf->bars[1].bar, vf->bars[1].size, 1618 (unsigned)vf->bars[2].bar, vf->bars[2].size); 1619 } 1620 1621 return 0; 1622 } 1623 1624 /* called by bnx2x_chip_cleanup */ 1625 int bnx2x_iov_chip_cleanup(struct bnx2x *bp) 1626 { 1627 int i; 1628 1629 if (!IS_SRIOV(bp)) 1630 return 0; 1631 1632 /* release all the VFs */ 1633 for_each_vf(bp, i) 1634 bnx2x_vf_release(bp, BP_VF(bp, i)); 1635 1636 return 0; 1637 } 1638 1639 /* called by bnx2x_init_hw_func, returns the next ilt line */ 1640 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) 1641 { 1642 int i; 1643 struct bnx2x_ilt *ilt = BP_ILT(bp); 1644 1645 if (!IS_SRIOV(bp)) 1646 return line; 1647 1648 /* set vfs ilt lines */ 1649 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1650 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i); 1651 1652 ilt->lines[line+i].page = hw_cxt->addr; 1653 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 1654 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 1655 } 1656 return line + i; 1657 } 1658 1659 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid) 1660 { 1661 return ((cid >= BNX2X_FIRST_VF_CID) && 1662 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS)); 1663 } 1664 1665 static 1666 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp, 1667 struct bnx2x_vf_queue *vfq, 1668 union event_ring_elem *elem) 1669 { 1670 unsigned long ramrod_flags = 0; 1671 int rc = 0; 1672 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); 1673 1674 /* Always push next commands out, don't wait here */ 1675 set_bit(RAMROD_CONT, &ramrod_flags); 1676 1677 switch (echo >> BNX2X_SWCID_SHIFT) { 1678 case BNX2X_FILTER_MAC_PENDING: 1679 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem, 1680 &ramrod_flags); 1681 break; 1682 case BNX2X_FILTER_VLAN_PENDING: 1683 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem, 1684 &ramrod_flags); 1685 break; 1686 default: 1687 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); 1688 return; 1689 } 1690 if (rc < 0) 1691 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 1692 else if (rc > 0) 1693 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); 1694 } 1695 1696 static 1697 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp, 1698 struct bnx2x_virtf *vf) 1699 { 1700 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 1701 int rc; 1702 1703 rparam.mcast_obj = &vf->mcast_obj; 1704 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw); 1705 1706 /* If there are pending mcast commands - send them */ 1707 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) { 1708 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 1709 if (rc < 0) 1710 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 1711 rc); 1712 } 1713 } 1714 1715 static 1716 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp, 1717 struct bnx2x_virtf *vf) 1718 { 1719 smp_mb__before_atomic(); 1720 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 1721 smp_mb__after_atomic(); 1722 } 1723 1724 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp, 1725 struct bnx2x_virtf *vf) 1726 { 1727 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw); 1728 } 1729 1730 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) 1731 { 1732 struct bnx2x_virtf *vf; 1733 int qidx = 0, abs_vfid; 1734 u8 opcode; 1735 u16 cid = 0xffff; 1736 1737 if (!IS_SRIOV(bp)) 1738 return 1; 1739 1740 /* first get the cid - the only events we handle here are cfc-delete 1741 * and set-mac completion 1742 */ 1743 opcode = elem->message.opcode; 1744 1745 switch (opcode) { 1746 case EVENT_RING_OPCODE_CFC_DEL: 1747 cid = SW_CID(elem->message.data.cfc_del_event.cid); 1748 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); 1749 break; 1750 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1751 case EVENT_RING_OPCODE_MULTICAST_RULES: 1752 case EVENT_RING_OPCODE_FILTERS_RULES: 1753 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1754 cid = SW_CID(elem->message.data.eth_event.echo); 1755 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); 1756 break; 1757 case EVENT_RING_OPCODE_VF_FLR: 1758 abs_vfid = elem->message.data.vf_flr_event.vf_id; 1759 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", 1760 abs_vfid); 1761 goto get_vf; 1762 case EVENT_RING_OPCODE_MALICIOUS_VF: 1763 abs_vfid = elem->message.data.malicious_vf_event.vf_id; 1764 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", 1765 abs_vfid, 1766 elem->message.data.malicious_vf_event.err_id); 1767 goto get_vf; 1768 default: 1769 return 1; 1770 } 1771 1772 /* check if the cid is the VF range */ 1773 if (!bnx2x_iov_is_vf_cid(bp, cid)) { 1774 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); 1775 return 1; 1776 } 1777 1778 /* extract vf and rxq index from vf_cid - relies on the following: 1779 * 1. vfid on cid reflects the true abs_vfid 1780 * 2. The max number of VFs (per path) is 64 1781 */ 1782 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1); 1783 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1784 get_vf: 1785 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 1786 1787 if (!vf) { 1788 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n", 1789 cid, abs_vfid); 1790 return 0; 1791 } 1792 1793 switch (opcode) { 1794 case EVENT_RING_OPCODE_CFC_DEL: 1795 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", 1796 vf->abs_vfid, qidx); 1797 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp, 1798 &vfq_get(vf, 1799 qidx)->sp_obj, 1800 BNX2X_Q_CMD_CFC_DEL); 1801 break; 1802 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1803 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", 1804 vf->abs_vfid, qidx); 1805 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem); 1806 break; 1807 case EVENT_RING_OPCODE_MULTICAST_RULES: 1808 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", 1809 vf->abs_vfid, qidx); 1810 bnx2x_vf_handle_mcast_eqe(bp, vf); 1811 break; 1812 case EVENT_RING_OPCODE_FILTERS_RULES: 1813 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", 1814 vf->abs_vfid, qidx); 1815 bnx2x_vf_handle_filters_eqe(bp, vf); 1816 break; 1817 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1818 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", 1819 vf->abs_vfid, qidx); 1820 bnx2x_vf_handle_rss_update_eqe(bp, vf); 1821 case EVENT_RING_OPCODE_VF_FLR: 1822 /* Do nothing for now */ 1823 return 0; 1824 case EVENT_RING_OPCODE_MALICIOUS_VF: 1825 vf->malicious = true; 1826 return 0; 1827 } 1828 1829 return 0; 1830 } 1831 1832 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid) 1833 { 1834 /* extract the vf from vf_cid - relies on the following: 1835 * 1. vfid on cid reflects the true abs_vfid 1836 * 2. The max number of VFs (per path) is 64 1837 */ 1838 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1839 return bnx2x_vf_by_abs_fid(bp, abs_vfid); 1840 } 1841 1842 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid, 1843 struct bnx2x_queue_sp_obj **q_obj) 1844 { 1845 struct bnx2x_virtf *vf; 1846 1847 if (!IS_SRIOV(bp)) 1848 return; 1849 1850 vf = bnx2x_vf_by_cid(bp, vf_cid); 1851 1852 if (vf) { 1853 /* extract queue index from vf_cid - relies on the following: 1854 * 1. vfid on cid reflects the true abs_vfid 1855 * 2. The max number of VFs (per path) is 64 1856 */ 1857 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1); 1858 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj); 1859 } else { 1860 BNX2X_ERR("No vf matching cid %d\n", vf_cid); 1861 } 1862 } 1863 1864 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) 1865 { 1866 int i; 1867 int first_queue_query_index, num_queues_req; 1868 dma_addr_t cur_data_offset; 1869 struct stats_query_entry *cur_query_entry; 1870 u8 stats_count = 0; 1871 bool is_fcoe = false; 1872 1873 if (!IS_SRIOV(bp)) 1874 return; 1875 1876 if (!NO_FCOE(bp)) 1877 is_fcoe = true; 1878 1879 /* fcoe adds one global request and one queue request */ 1880 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe; 1881 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1882 (is_fcoe ? 0 : 1); 1883 1884 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1885 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n", 1886 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index, 1887 first_queue_query_index + num_queues_req); 1888 1889 cur_data_offset = bp->fw_stats_data_mapping + 1890 offsetof(struct bnx2x_fw_stats_data, queue_stats) + 1891 num_queues_req * sizeof(struct per_queue_stats); 1892 1893 cur_query_entry = &bp->fw_stats_req-> 1894 query[first_queue_query_index + num_queues_req]; 1895 1896 for_each_vf(bp, i) { 1897 int j; 1898 struct bnx2x_virtf *vf = BP_VF(bp, i); 1899 1900 if (vf->state != VF_ENABLED) { 1901 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1902 "vf %d not enabled so no stats for it\n", 1903 vf->abs_vfid); 1904 continue; 1905 } 1906 1907 if (vf->malicious) { 1908 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1909 "vf %d malicious so no stats for it\n", 1910 vf->abs_vfid); 1911 continue; 1912 } 1913 1914 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1915 "add addresses for vf %d\n", vf->abs_vfid); 1916 for_each_vfq(vf, j) { 1917 struct bnx2x_vf_queue *rxq = vfq_get(vf, j); 1918 1919 dma_addr_t q_stats_addr = 1920 vf->fw_stat_map + j * vf->stats_stride; 1921 1922 /* collect stats fro active queues only */ 1923 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) == 1924 BNX2X_Q_LOGICAL_STATE_STOPPED) 1925 continue; 1926 1927 /* create stats query entry for this queue */ 1928 cur_query_entry->kind = STATS_TYPE_QUEUE; 1929 cur_query_entry->index = vfq_stat_id(vf, rxq); 1930 cur_query_entry->funcID = 1931 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid)); 1932 cur_query_entry->address.hi = 1933 cpu_to_le32(U64_HI(q_stats_addr)); 1934 cur_query_entry->address.lo = 1935 cpu_to_le32(U64_LO(q_stats_addr)); 1936 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1937 "added address %x %x for vf %d queue %d client %d\n", 1938 cur_query_entry->address.hi, 1939 cur_query_entry->address.lo, 1940 cur_query_entry->funcID, 1941 j, cur_query_entry->index); 1942 cur_query_entry++; 1943 cur_data_offset += sizeof(struct per_queue_stats); 1944 stats_count++; 1945 1946 /* all stats are coalesced to the leading queue */ 1947 if (vf->cfg_flags & VF_CFG_STATS_COALESCE) 1948 break; 1949 } 1950 } 1951 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count; 1952 } 1953 1954 /* VF API helpers */ 1955 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid, 1956 u8 enable) 1957 { 1958 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; 1959 u32 val = enable ? (abs_vfid | (1 << 6)) : 0; 1960 1961 REG_WR(bp, reg, val); 1962 } 1963 1964 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf) 1965 { 1966 int i; 1967 1968 for_each_vfq(vf, i) 1969 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 1970 vfq_qzone_id(vf, vfq_get(vf, i)), false); 1971 } 1972 1973 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf) 1974 { 1975 u32 val; 1976 1977 /* clear the VF configuration - pretend */ 1978 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 1979 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 1980 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | 1981 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK); 1982 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 1983 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1984 } 1985 1986 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf) 1987 { 1988 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF), 1989 BNX2X_VF_MAX_QUEUES); 1990 } 1991 1992 static 1993 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf, 1994 struct vf_pf_resc_request *req_resc) 1995 { 1996 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 1997 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 1998 1999 return ((req_resc->num_rxqs <= rxq_cnt) && 2000 (req_resc->num_txqs <= txq_cnt) && 2001 (req_resc->num_sbs <= vf_sb_count(vf)) && 2002 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) && 2003 (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf))); 2004 } 2005 2006 /* CORE VF API */ 2007 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf, 2008 struct vf_pf_resc_request *resc) 2009 { 2010 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) * 2011 BNX2X_CIDS_PER_VF; 2012 2013 union cdu_context *base_cxt = (union cdu_context *) 2014 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 2015 (base_vf_cid & (ILT_PAGE_CIDS-1)); 2016 int i; 2017 2018 /* if state is 'acquired' the VF was not released or FLR'd, in 2019 * this case the returned resources match the acquired already 2020 * acquired resources. Verify that the requested numbers do 2021 * not exceed the already acquired numbers. 2022 */ 2023 if (vf->state == VF_ACQUIRED) { 2024 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", 2025 vf->abs_vfid); 2026 2027 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2028 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n", 2029 vf->abs_vfid); 2030 return -EINVAL; 2031 } 2032 return 0; 2033 } 2034 2035 /* Otherwise vf state must be 'free' or 'reset' */ 2036 if (vf->state != VF_FREE && vf->state != VF_RESET) { 2037 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n", 2038 vf->abs_vfid, vf->state); 2039 return -EINVAL; 2040 } 2041 2042 /* static allocation: 2043 * the global maximum number are fixed per VF. Fail the request if 2044 * requested number exceed these globals 2045 */ 2046 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2047 DP(BNX2X_MSG_IOV, 2048 "cannot fulfill vf resource request. Placing maximal available values in response\n"); 2049 /* set the max resource in the vf */ 2050 return -ENOMEM; 2051 } 2052 2053 /* Set resources counters - 0 request means max available */ 2054 vf_sb_count(vf) = resc->num_sbs; 2055 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2056 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2057 2058 DP(BNX2X_MSG_IOV, 2059 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n", 2060 vf_sb_count(vf), vf_rxq_count(vf), 2061 vf_txq_count(vf), vf_mac_rules_cnt(vf), 2062 vf_vlan_rules_cnt(vf)); 2063 2064 /* Initialize the queues */ 2065 if (!vf->vfqs) { 2066 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); 2067 return -EINVAL; 2068 } 2069 2070 for_each_vfq(vf, i) { 2071 struct bnx2x_vf_queue *q = vfq_get(vf, i); 2072 2073 if (!q) { 2074 BNX2X_ERR("q number %d was not allocated\n", i); 2075 return -EINVAL; 2076 } 2077 2078 q->index = i; 2079 q->cxt = &((base_cxt + i)->eth); 2080 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i; 2081 2082 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", 2083 vf->abs_vfid, i, q->index, q->cid, q->cxt); 2084 2085 /* init SP objects */ 2086 bnx2x_vfq_init(bp, vf, q); 2087 } 2088 vf->state = VF_ACQUIRED; 2089 return 0; 2090 } 2091 2092 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map) 2093 { 2094 struct bnx2x_func_init_params func_init = {0}; 2095 int i; 2096 2097 /* the sb resources are initialized at this point, do the 2098 * FW/HW initializations 2099 */ 2100 for_each_vf_sb(vf, i) 2101 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true, 2102 vf_igu_sb(vf, i), vf_igu_sb(vf, i)); 2103 2104 /* Sanity checks */ 2105 if (vf->state != VF_ACQUIRED) { 2106 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", 2107 vf->abs_vfid, vf->state); 2108 return -EINVAL; 2109 } 2110 2111 /* let FLR complete ... */ 2112 msleep(100); 2113 2114 /* FLR cleanup epilogue */ 2115 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid)) 2116 return -EBUSY; 2117 2118 /* reset IGU VF statistics: MSIX */ 2119 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0); 2120 2121 /* function setup */ 2122 func_init.pf_id = BP_FUNC(bp); 2123 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid); 2124 bnx2x_func_init(bp, &func_init); 2125 2126 /* Enable the vf */ 2127 bnx2x_vf_enable_access(bp, vf->abs_vfid); 2128 bnx2x_vf_enable_traffic(bp, vf); 2129 2130 /* queue protection table */ 2131 for_each_vfq(vf, i) 2132 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2133 vfq_qzone_id(vf, vfq_get(vf, i)), true); 2134 2135 vf->state = VF_ENABLED; 2136 2137 /* update vf bulletin board */ 2138 bnx2x_post_vf_bulletin(bp, vf->index); 2139 2140 return 0; 2141 } 2142 2143 struct set_vf_state_cookie { 2144 struct bnx2x_virtf *vf; 2145 u8 state; 2146 }; 2147 2148 static void bnx2x_set_vf_state(void *cookie) 2149 { 2150 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie; 2151 2152 p->vf->state = p->state; 2153 } 2154 2155 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf) 2156 { 2157 int rc = 0, i; 2158 2159 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2160 2161 /* Close all queues */ 2162 for (i = 0; i < vf_rxq_count(vf); i++) { 2163 rc = bnx2x_vf_queue_teardown(bp, vf, i); 2164 if (rc) 2165 goto op_err; 2166 } 2167 2168 /* disable the interrupts */ 2169 DP(BNX2X_MSG_IOV, "disabling igu\n"); 2170 bnx2x_vf_igu_disable(bp, vf); 2171 2172 /* disable the VF */ 2173 DP(BNX2X_MSG_IOV, "clearing qtbl\n"); 2174 bnx2x_vf_clr_qtbl(bp, vf); 2175 2176 /* need to make sure there are no outstanding stats ramrods which may 2177 * cause the device to access the VF's stats buffer which it will free 2178 * as soon as we return from the close flow. 2179 */ 2180 { 2181 struct set_vf_state_cookie cookie; 2182 2183 cookie.vf = vf; 2184 cookie.state = VF_ACQUIRED; 2185 rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie); 2186 if (rc) 2187 goto op_err; 2188 } 2189 2190 DP(BNX2X_MSG_IOV, "set state to acquired\n"); 2191 2192 return 0; 2193 op_err: 2194 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc); 2195 return rc; 2196 } 2197 2198 /* VF release can be called either: 1. The VF was acquired but 2199 * not enabled 2. the vf was enabled or in the process of being 2200 * enabled 2201 */ 2202 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf) 2203 { 2204 int rc; 2205 2206 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, 2207 vf->state == VF_FREE ? "Free" : 2208 vf->state == VF_ACQUIRED ? "Acquired" : 2209 vf->state == VF_ENABLED ? "Enabled" : 2210 vf->state == VF_RESET ? "Reset" : 2211 "Unknown"); 2212 2213 switch (vf->state) { 2214 case VF_ENABLED: 2215 rc = bnx2x_vf_close(bp, vf); 2216 if (rc) 2217 goto op_err; 2218 /* Fallthrough to release resources */ 2219 case VF_ACQUIRED: 2220 DP(BNX2X_MSG_IOV, "about to free resources\n"); 2221 bnx2x_vf_free_resc(bp, vf); 2222 break; 2223 2224 case VF_FREE: 2225 case VF_RESET: 2226 default: 2227 break; 2228 } 2229 return 0; 2230 op_err: 2231 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc); 2232 return rc; 2233 } 2234 2235 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2236 struct bnx2x_config_rss_params *rss) 2237 { 2238 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2239 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags); 2240 return bnx2x_config_rss(bp, rss); 2241 } 2242 2243 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2244 struct vfpf_tpa_tlv *tlv, 2245 struct bnx2x_queue_update_tpa_params *params) 2246 { 2247 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr; 2248 struct bnx2x_queue_state_params qstate; 2249 int qid, rc = 0; 2250 2251 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2252 2253 /* Set ramrod params */ 2254 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 2255 memcpy(&qstate.params.update_tpa, params, 2256 sizeof(struct bnx2x_queue_update_tpa_params)); 2257 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA; 2258 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 2259 2260 for (qid = 0; qid < vf_rxq_count(vf); qid++) { 2261 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 2262 qstate.params.update_tpa.sge_map = sge_addr[qid]; 2263 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", 2264 vf->abs_vfid, qid, U64_HI(sge_addr[qid]), 2265 U64_LO(sge_addr[qid])); 2266 rc = bnx2x_queue_state_change(bp, &qstate); 2267 if (rc) { 2268 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n", 2269 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]), 2270 vf->abs_vfid, qid); 2271 return rc; 2272 } 2273 } 2274 2275 return rc; 2276 } 2277 2278 /* VF release ~ VF close + VF release-resources 2279 * Release is the ultimate SW shutdown and is called whenever an 2280 * irrecoverable error is encountered. 2281 */ 2282 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf) 2283 { 2284 int rc; 2285 2286 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); 2287 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2288 2289 rc = bnx2x_vf_free(bp, vf); 2290 if (rc) 2291 WARN(rc, 2292 "VF[%d] Failed to allocate resources for release op- rc=%d\n", 2293 vf->abs_vfid, rc); 2294 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2295 return rc; 2296 } 2297 2298 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2299 enum channel_tlvs tlv) 2300 { 2301 /* we don't lock the channel for unsupported tlvs */ 2302 if (!bnx2x_tlv_supported(tlv)) { 2303 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n"); 2304 return; 2305 } 2306 2307 /* lock the channel */ 2308 mutex_lock(&vf->op_mutex); 2309 2310 /* record the locking op */ 2311 vf->op_current = tlv; 2312 2313 /* log the lock */ 2314 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", 2315 vf->abs_vfid, tlv); 2316 } 2317 2318 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2319 enum channel_tlvs expected_tlv) 2320 { 2321 enum channel_tlvs current_tlv; 2322 2323 if (!vf) { 2324 BNX2X_ERR("VF was %p\n", vf); 2325 return; 2326 } 2327 2328 current_tlv = vf->op_current; 2329 2330 /* we don't unlock the channel for unsupported tlvs */ 2331 if (!bnx2x_tlv_supported(expected_tlv)) 2332 return; 2333 2334 WARN(expected_tlv != vf->op_current, 2335 "lock mismatch: expected %d found %d", expected_tlv, 2336 vf->op_current); 2337 2338 /* record the locking op */ 2339 vf->op_current = CHANNEL_TLV_NONE; 2340 2341 /* lock the channel */ 2342 mutex_unlock(&vf->op_mutex); 2343 2344 /* log the unlock */ 2345 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", 2346 vf->abs_vfid, current_tlv); 2347 } 2348 2349 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable) 2350 { 2351 struct bnx2x_queue_state_params q_params; 2352 u32 prev_flags; 2353 int i, rc; 2354 2355 /* Verify changes are needed and record current Tx switching state */ 2356 prev_flags = bp->flags; 2357 if (enable) 2358 bp->flags |= TX_SWITCHING; 2359 else 2360 bp->flags &= ~TX_SWITCHING; 2361 if (prev_flags == bp->flags) 2362 return 0; 2363 2364 /* Verify state enables the sending of queue ramrods */ 2365 if ((bp->state != BNX2X_STATE_OPEN) || 2366 (bnx2x_get_q_logical_state(bp, 2367 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) != 2368 BNX2X_Q_LOGICAL_STATE_ACTIVE)) 2369 return 0; 2370 2371 /* send q. update ramrod to configure Tx switching */ 2372 memset(&q_params, 0, sizeof(q_params)); 2373 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2374 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2375 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 2376 &q_params.params.update.update_flags); 2377 if (enable) 2378 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2379 &q_params.params.update.update_flags); 2380 else 2381 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2382 &q_params.params.update.update_flags); 2383 2384 /* send the ramrod on all the queues of the PF */ 2385 for_each_eth_queue(bp, i) { 2386 struct bnx2x_fastpath *fp = &bp->fp[i]; 2387 2388 /* Set the appropriate Queue object */ 2389 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 2390 2391 /* Update the Queue state */ 2392 rc = bnx2x_queue_state_change(bp, &q_params); 2393 if (rc) { 2394 BNX2X_ERR("Failed to configure Tx switching\n"); 2395 return rc; 2396 } 2397 } 2398 2399 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled"); 2400 return 0; 2401 } 2402 2403 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) 2404 { 2405 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); 2406 2407 if (!IS_SRIOV(bp)) { 2408 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); 2409 return -EINVAL; 2410 } 2411 2412 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", 2413 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2414 2415 /* HW channel is only operational when PF is up */ 2416 if (bp->state != BNX2X_STATE_OPEN) { 2417 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n"); 2418 return -EINVAL; 2419 } 2420 2421 /* we are always bound by the total_vfs in the configuration space */ 2422 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { 2423 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", 2424 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2425 num_vfs_param = BNX2X_NR_VIRTFN(bp); 2426 } 2427 2428 bp->requested_nr_virtfn = num_vfs_param; 2429 if (num_vfs_param == 0) { 2430 bnx2x_set_pf_tx_switching(bp, false); 2431 bnx2x_disable_sriov(bp); 2432 return 0; 2433 } else { 2434 return bnx2x_enable_sriov(bp); 2435 } 2436 } 2437 2438 #define IGU_ENTRY_SIZE 4 2439 2440 int bnx2x_enable_sriov(struct bnx2x *bp) 2441 { 2442 int rc = 0, req_vfs = bp->requested_nr_virtfn; 2443 int vf_idx, sb_idx, vfq_idx, qcount, first_vf; 2444 u32 igu_entry, address; 2445 u16 num_vf_queues; 2446 2447 if (req_vfs == 0) 2448 return 0; 2449 2450 first_vf = bp->vfdb->sriov.first_vf_in_pf; 2451 2452 /* statically distribute vf sb pool between VFs */ 2453 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES, 2454 BP_VFDB(bp)->vf_sbs_pool / req_vfs); 2455 2456 /* zero previous values learned from igu cam */ 2457 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) { 2458 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2459 2460 vf->sb_count = 0; 2461 vf_sb_count(BP_VF(bp, vf_idx)) = 0; 2462 } 2463 bp->vfdb->vf_sbs_pool = 0; 2464 2465 /* prepare IGU cam */ 2466 sb_idx = BP_VFDB(bp)->first_vf_igu_entry; 2467 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE; 2468 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2469 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) { 2470 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT | 2471 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT | 2472 IGU_REG_MAPPING_MEMORY_VALID; 2473 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", 2474 sb_idx, vf_idx); 2475 REG_WR(bp, address, igu_entry); 2476 sb_idx++; 2477 address += IGU_ENTRY_SIZE; 2478 } 2479 } 2480 2481 /* Reinitialize vf database according to igu cam */ 2482 bnx2x_get_vf_igu_cam_info(bp); 2483 2484 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", 2485 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues); 2486 2487 qcount = 0; 2488 for_each_vf(bp, vf_idx) { 2489 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2490 2491 /* set local queue arrays */ 2492 vf->vfqs = &bp->vfdb->vfqs[qcount]; 2493 qcount += vf_sb_count(vf); 2494 bnx2x_iov_static_resc(bp, vf); 2495 } 2496 2497 /* prepare msix vectors in VF configuration space - the value in the 2498 * PCI configuration space should be the index of the last entry, 2499 * namely one less than the actual size of the table 2500 */ 2501 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2502 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); 2503 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, 2504 num_vf_queues - 1); 2505 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n", 2506 vf_idx, num_vf_queues - 1); 2507 } 2508 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2509 2510 /* enable sriov. This will probe all the VFs, and consequentially cause 2511 * the "acquire" messages to appear on the VF PF channel. 2512 */ 2513 DP(BNX2X_MSG_IOV, "about to call enable sriov\n"); 2514 bnx2x_disable_sriov(bp); 2515 2516 rc = bnx2x_set_pf_tx_switching(bp, true); 2517 if (rc) 2518 return rc; 2519 2520 rc = pci_enable_sriov(bp->pdev, req_vfs); 2521 if (rc) { 2522 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); 2523 return rc; 2524 } 2525 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); 2526 return req_vfs; 2527 } 2528 2529 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) 2530 { 2531 int vfidx; 2532 struct pf_vf_bulletin_content *bulletin; 2533 2534 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); 2535 for_each_vf(bp, vfidx) { 2536 bulletin = BP_VF_BULLETIN(bp, vfidx); 2537 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2538 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0, 2539 htons(ETH_P_8021Q)); 2540 } 2541 } 2542 2543 void bnx2x_disable_sriov(struct bnx2x *bp) 2544 { 2545 if (pci_vfs_assigned(bp->pdev)) { 2546 DP(BNX2X_MSG_IOV, 2547 "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2548 return; 2549 } 2550 2551 pci_disable_sriov(bp->pdev); 2552 } 2553 2554 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 2555 struct bnx2x_virtf **vf, 2556 struct pf_vf_bulletin_content **bulletin, 2557 bool test_queue) 2558 { 2559 if (bp->state != BNX2X_STATE_OPEN) { 2560 BNX2X_ERR("PF is down - can't utilize iov-related functionality\n"); 2561 return -EINVAL; 2562 } 2563 2564 if (!IS_SRIOV(bp)) { 2565 BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n"); 2566 return -EINVAL; 2567 } 2568 2569 if (vfidx >= BNX2X_NR_VIRTFN(bp)) { 2570 BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n", 2571 vfidx, BNX2X_NR_VIRTFN(bp)); 2572 return -EINVAL; 2573 } 2574 2575 /* init members */ 2576 *vf = BP_VF(bp, vfidx); 2577 *bulletin = BP_VF_BULLETIN(bp, vfidx); 2578 2579 if (!*vf) { 2580 BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx); 2581 return -EINVAL; 2582 } 2583 2584 if (test_queue && !(*vf)->vfqs) { 2585 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n", 2586 vfidx); 2587 return -EINVAL; 2588 } 2589 2590 if (!*bulletin) { 2591 BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n", 2592 vfidx); 2593 return -EINVAL; 2594 } 2595 2596 return 0; 2597 } 2598 2599 int bnx2x_get_vf_config(struct net_device *dev, int vfidx, 2600 struct ifla_vf_info *ivi) 2601 { 2602 struct bnx2x *bp = netdev_priv(dev); 2603 struct bnx2x_virtf *vf = NULL; 2604 struct pf_vf_bulletin_content *bulletin = NULL; 2605 struct bnx2x_vlan_mac_obj *mac_obj; 2606 struct bnx2x_vlan_mac_obj *vlan_obj; 2607 int rc; 2608 2609 /* sanity and init */ 2610 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2611 if (rc) 2612 return rc; 2613 2614 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2615 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2616 if (!mac_obj || !vlan_obj) { 2617 BNX2X_ERR("VF partially initialized\n"); 2618 return -EINVAL; 2619 } 2620 2621 ivi->vf = vfidx; 2622 ivi->qos = 0; 2623 ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */ 2624 ivi->min_tx_rate = 0; 2625 ivi->spoofchk = 1; /*always enabled */ 2626 if (vf->state == VF_ENABLED) { 2627 /* mac and vlan are in vlan_mac objects */ 2628 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) { 2629 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, 2630 0, ETH_ALEN); 2631 vlan_obj->get_n_elements(bp, vlan_obj, 1, 2632 (u8 *)&ivi->vlan, 0, 2633 VLAN_HLEN); 2634 } 2635 } else { 2636 mutex_lock(&bp->vfdb->bulletin_mutex); 2637 /* mac */ 2638 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) 2639 /* mac configured by ndo so its in bulletin board */ 2640 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); 2641 else 2642 /* function has not been loaded yet. Show mac as 0s */ 2643 eth_zero_addr(ivi->mac); 2644 2645 /* vlan */ 2646 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2647 /* vlan configured by ndo so its in bulletin board */ 2648 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); 2649 else 2650 /* function has not been loaded yet. Show vlans as 0s */ 2651 memset(&ivi->vlan, 0, VLAN_HLEN); 2652 2653 mutex_unlock(&bp->vfdb->bulletin_mutex); 2654 } 2655 2656 return 0; 2657 } 2658 2659 /* New mac for VF. Consider these cases: 2660 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and 2661 * supply at acquire. 2662 * 2. VF has already been acquired but has not yet initialized - store in local 2663 * bulletin board. mac will be posted on VF bulletin board after VF init. VF 2664 * will configure this mac when it is ready. 2665 * 3. VF has already initialized but has not yet setup a queue - post the new 2666 * mac on VF's bulletin board right now. VF will configure this mac when it 2667 * is ready. 2668 * 4. VF has already set a queue - delete any macs already configured for this 2669 * queue and manually config the new mac. 2670 * In any event, once this function has been called refuse any attempts by the 2671 * VF to configure any mac for itself except for this mac. In case of a race 2672 * where the VF fails to see the new post on its bulletin board before sending a 2673 * mac configuration request, the PF will simply fail the request and VF can try 2674 * again after consulting its bulletin board. 2675 */ 2676 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) 2677 { 2678 struct bnx2x *bp = netdev_priv(dev); 2679 int rc, q_logical_state; 2680 struct bnx2x_virtf *vf = NULL; 2681 struct pf_vf_bulletin_content *bulletin = NULL; 2682 2683 if (!is_valid_ether_addr(mac)) { 2684 BNX2X_ERR("mac address invalid\n"); 2685 return -EINVAL; 2686 } 2687 2688 /* sanity and init */ 2689 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2690 if (rc) 2691 return rc; 2692 2693 mutex_lock(&bp->vfdb->bulletin_mutex); 2694 2695 /* update PF's copy of the VF's bulletin. Will no longer accept mac 2696 * configuration requests from vf unless match this mac 2697 */ 2698 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID; 2699 memcpy(bulletin->mac, mac, ETH_ALEN); 2700 2701 /* Post update on VF's bulletin board */ 2702 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2703 2704 /* release lock before checking return code */ 2705 mutex_unlock(&bp->vfdb->bulletin_mutex); 2706 2707 if (rc) { 2708 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2709 return rc; 2710 } 2711 2712 q_logical_state = 2713 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)); 2714 if (vf->state == VF_ENABLED && 2715 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { 2716 /* configure the mac in device on this vf's queue */ 2717 unsigned long ramrod_flags = 0; 2718 struct bnx2x_vlan_mac_obj *mac_obj; 2719 2720 /* User should be able to see failure reason in system logs */ 2721 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2722 return -EINVAL; 2723 2724 /* must lock vfpf channel to protect against vf flows */ 2725 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2726 2727 /* remove existing eth macs */ 2728 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2729 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true); 2730 if (rc) { 2731 BNX2X_ERR("failed to delete eth macs\n"); 2732 rc = -EINVAL; 2733 goto out; 2734 } 2735 2736 /* remove existing uc list macs */ 2737 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true); 2738 if (rc) { 2739 BNX2X_ERR("failed to delete uc_list macs\n"); 2740 rc = -EINVAL; 2741 goto out; 2742 } 2743 2744 /* configure the new mac to device */ 2745 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2746 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, 2747 BNX2X_ETH_MAC, &ramrod_flags); 2748 2749 out: 2750 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2751 } 2752 2753 return rc; 2754 } 2755 2756 static void bnx2x_set_vf_vlan_acceptance(struct bnx2x *bp, 2757 struct bnx2x_virtf *vf, bool accept) 2758 { 2759 struct bnx2x_rx_mode_ramrod_params rx_ramrod; 2760 unsigned long accept_flags; 2761 2762 /* need to remove/add the VF's accept_any_vlan bit */ 2763 accept_flags = bnx2x_leading_vfq(vf, accept_flags); 2764 if (accept) 2765 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2766 else 2767 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2768 2769 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf, 2770 accept_flags); 2771 bnx2x_leading_vfq(vf, accept_flags) = accept_flags; 2772 bnx2x_config_rx_mode(bp, &rx_ramrod); 2773 } 2774 2775 static int bnx2x_set_vf_vlan_filter(struct bnx2x *bp, struct bnx2x_virtf *vf, 2776 u16 vlan, bool add) 2777 { 2778 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 2779 unsigned long ramrod_flags = 0; 2780 int rc = 0; 2781 2782 /* configure the new vlan to device */ 2783 memset(&ramrod_param, 0, sizeof(ramrod_param)); 2784 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2785 ramrod_param.vlan_mac_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2786 ramrod_param.ramrod_flags = ramrod_flags; 2787 ramrod_param.user_req.u.vlan.vlan = vlan; 2788 ramrod_param.user_req.cmd = add ? BNX2X_VLAN_MAC_ADD 2789 : BNX2X_VLAN_MAC_DEL; 2790 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 2791 if (rc) { 2792 BNX2X_ERR("failed to configure vlan\n"); 2793 return -EINVAL; 2794 } 2795 2796 return 0; 2797 } 2798 2799 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos, 2800 __be16 vlan_proto) 2801 { 2802 struct pf_vf_bulletin_content *bulletin = NULL; 2803 struct bnx2x *bp = netdev_priv(dev); 2804 struct bnx2x_vlan_mac_obj *vlan_obj; 2805 unsigned long vlan_mac_flags = 0; 2806 unsigned long ramrod_flags = 0; 2807 struct bnx2x_virtf *vf = NULL; 2808 int i, rc; 2809 2810 if (vlan > 4095) { 2811 BNX2X_ERR("illegal vlan value %d\n", vlan); 2812 return -EINVAL; 2813 } 2814 2815 if (vlan_proto != htons(ETH_P_8021Q)) 2816 return -EPROTONOSUPPORT; 2817 2818 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", 2819 vfidx, vlan, 0); 2820 2821 /* sanity and init */ 2822 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2823 if (rc) 2824 return rc; 2825 2826 /* update PF's copy of the VF's bulletin. No point in posting the vlan 2827 * to the VF since it doesn't have anything to do with it. But it useful 2828 * to store it here in case the VF is not up yet and we can only 2829 * configure the vlan later when it does. Treat vlan id 0 as remove the 2830 * Host tag. 2831 */ 2832 mutex_lock(&bp->vfdb->bulletin_mutex); 2833 2834 if (vlan > 0) 2835 bulletin->valid_bitmap |= 1 << VLAN_VALID; 2836 else 2837 bulletin->valid_bitmap &= ~(1 << VLAN_VALID); 2838 bulletin->vlan = vlan; 2839 2840 /* Post update on VF's bulletin board */ 2841 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2842 if (rc) 2843 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2844 mutex_unlock(&bp->vfdb->bulletin_mutex); 2845 2846 /* is vf initialized and queue set up? */ 2847 if (vf->state != VF_ENABLED || 2848 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) != 2849 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2850 return rc; 2851 2852 /* User should be able to see error in system logs */ 2853 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2854 return -EINVAL; 2855 2856 /* must lock vfpf channel to protect against vf flows */ 2857 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2858 2859 /* remove existing vlans */ 2860 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2861 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2862 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, 2863 &ramrod_flags); 2864 if (rc) { 2865 BNX2X_ERR("failed to delete vlans\n"); 2866 rc = -EINVAL; 2867 goto out; 2868 } 2869 2870 /* clear accept_any_vlan when HV forces vlan, otherwise 2871 * according to VF capabilities 2872 */ 2873 if (vlan || !(vf->cfg_flags & VF_CFG_VLAN_FILTER)) 2874 bnx2x_set_vf_vlan_acceptance(bp, vf, !vlan); 2875 2876 rc = bnx2x_set_vf_vlan_filter(bp, vf, vlan, true); 2877 if (rc) 2878 goto out; 2879 2880 /* send queue update ramrods to configure default vlan and 2881 * silent vlan removal 2882 */ 2883 for_each_vfq(vf, i) { 2884 struct bnx2x_queue_state_params q_params = {NULL}; 2885 struct bnx2x_queue_update_params *update_params; 2886 2887 q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj); 2888 2889 /* validate the Q is UP */ 2890 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) != 2891 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2892 continue; 2893 2894 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2895 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2896 update_params = &q_params.params.update; 2897 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 2898 &update_params->update_flags); 2899 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 2900 &update_params->update_flags); 2901 if (vlan == 0) { 2902 /* if vlan is 0 then we want to leave the VF traffic 2903 * untagged, and leave the incoming traffic untouched 2904 * (i.e. do not remove any vlan tags). 2905 */ 2906 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2907 &update_params->update_flags); 2908 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2909 &update_params->update_flags); 2910 } else { 2911 /* configure default vlan to vf queue and set silent 2912 * vlan removal (the vf remains unaware of this vlan). 2913 */ 2914 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2915 &update_params->update_flags); 2916 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2917 &update_params->update_flags); 2918 update_params->def_vlan = vlan; 2919 update_params->silent_removal_value = 2920 vlan & VLAN_VID_MASK; 2921 update_params->silent_removal_mask = VLAN_VID_MASK; 2922 } 2923 2924 /* Update the Queue state */ 2925 rc = bnx2x_queue_state_change(bp, &q_params); 2926 if (rc) { 2927 BNX2X_ERR("Failed to configure default VLAN queue %d\n", 2928 i); 2929 goto out; 2930 } 2931 } 2932 out: 2933 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2934 2935 if (rc) 2936 DP(BNX2X_MSG_IOV, 2937 "updated VF[%d] vlan configuration (vlan = %d)\n", 2938 vfidx, vlan); 2939 2940 return rc; 2941 } 2942 2943 /* crc is the first field in the bulletin board. Compute the crc over the 2944 * entire bulletin board excluding the crc field itself. Use the length field 2945 * as the Bulletin Board was posted by a PF with possibly a different version 2946 * from the vf which will sample it. Therefore, the length is computed by the 2947 * PF and then used blindly by the VF. 2948 */ 2949 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin) 2950 { 2951 return crc32(BULLETIN_CRC_SEED, 2952 ((u8 *)bulletin) + sizeof(bulletin->crc), 2953 bulletin->length - sizeof(bulletin->crc)); 2954 } 2955 2956 /* Check for new posts on the bulletin board */ 2957 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) 2958 { 2959 struct pf_vf_bulletin_content *bulletin; 2960 int attempts; 2961 2962 /* sampling structure in mid post may result with corrupted data 2963 * validate crc to ensure coherency. 2964 */ 2965 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) { 2966 u32 crc; 2967 2968 /* sample the bulletin board */ 2969 memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin, 2970 sizeof(union pf_vf_bulletin)); 2971 2972 crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content); 2973 2974 if (bp->shadow_bulletin.content.crc == crc) 2975 break; 2976 2977 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n", 2978 bp->shadow_bulletin.content.crc, crc); 2979 } 2980 2981 if (attempts >= BULLETIN_ATTEMPTS) { 2982 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n", 2983 attempts); 2984 return PFVF_BULLETIN_CRC_ERR; 2985 } 2986 bulletin = &bp->shadow_bulletin.content; 2987 2988 /* bulletin board hasn't changed since last sample */ 2989 if (bp->old_bulletin.version == bulletin->version) 2990 return PFVF_BULLETIN_UNCHANGED; 2991 2992 /* the mac address in bulletin board is valid and is new */ 2993 if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID && 2994 !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) { 2995 /* update new mac to net device */ 2996 memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN); 2997 } 2998 2999 if (bulletin->valid_bitmap & (1 << LINK_VALID)) { 3000 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n", 3001 bulletin->link_speed, bulletin->link_flags); 3002 3003 bp->vf_link_vars.line_speed = bulletin->link_speed; 3004 bp->vf_link_vars.link_report_flags = 0; 3005 /* Link is down */ 3006 if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN) 3007 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, 3008 &bp->vf_link_vars.link_report_flags); 3009 /* Full DUPLEX */ 3010 if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX) 3011 __set_bit(BNX2X_LINK_REPORT_FD, 3012 &bp->vf_link_vars.link_report_flags); 3013 /* Rx Flow Control is ON */ 3014 if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON) 3015 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, 3016 &bp->vf_link_vars.link_report_flags); 3017 /* Tx Flow Control is ON */ 3018 if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON) 3019 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, 3020 &bp->vf_link_vars.link_report_flags); 3021 __bnx2x_link_report(bp); 3022 } 3023 3024 /* copy new bulletin board to bp */ 3025 memcpy(&bp->old_bulletin, bulletin, 3026 sizeof(struct pf_vf_bulletin_content)); 3027 3028 return PFVF_BULLETIN_UPDATED; 3029 } 3030 3031 void bnx2x_timer_sriov(struct bnx2x *bp) 3032 { 3033 bnx2x_sample_bulletin(bp); 3034 3035 /* if channel is down we need to self destruct */ 3036 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) 3037 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 3038 BNX2X_MSG_IOV); 3039 } 3040 3041 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) 3042 { 3043 /* vf doorbells are embedded within the regview */ 3044 return bp->regview + PXP_VF_ADDR_DB_START; 3045 } 3046 3047 void bnx2x_vf_pci_dealloc(struct bnx2x *bp) 3048 { 3049 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, 3050 sizeof(struct bnx2x_vf_mbx_msg)); 3051 BNX2X_PCI_FREE(bp->pf2vf_bulletin, bp->pf2vf_bulletin_mapping, 3052 sizeof(union pf_vf_bulletin)); 3053 } 3054 3055 int bnx2x_vf_pci_alloc(struct bnx2x *bp) 3056 { 3057 mutex_init(&bp->vf2pf_mutex); 3058 3059 /* allocate vf2pf mailbox for vf to pf channel */ 3060 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping, 3061 sizeof(struct bnx2x_vf_mbx_msg)); 3062 if (!bp->vf2pf_mbox) 3063 goto alloc_mem_err; 3064 3065 /* allocate pf 2 vf bulletin board */ 3066 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping, 3067 sizeof(union pf_vf_bulletin)); 3068 if (!bp->pf2vf_bulletin) 3069 goto alloc_mem_err; 3070 3071 bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true); 3072 3073 return 0; 3074 3075 alloc_mem_err: 3076 bnx2x_vf_pci_dealloc(bp); 3077 return -ENOMEM; 3078 } 3079 3080 void bnx2x_iov_channel_down(struct bnx2x *bp) 3081 { 3082 int vf_idx; 3083 struct pf_vf_bulletin_content *bulletin; 3084 3085 if (!IS_SRIOV(bp)) 3086 return; 3087 3088 for_each_vf(bp, vf_idx) { 3089 /* locate this VFs bulletin board and update the channel down 3090 * bit 3091 */ 3092 bulletin = BP_VF_BULLETIN(bp, vf_idx); 3093 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN; 3094 3095 /* update vf bulletin board */ 3096 bnx2x_post_vf_bulletin(bp, vf_idx); 3097 } 3098 } 3099 3100 void bnx2x_iov_task(struct work_struct *work) 3101 { 3102 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work); 3103 3104 if (!netif_running(bp->dev)) 3105 return; 3106 3107 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR, 3108 &bp->iov_task_state)) 3109 bnx2x_vf_handle_flr_event(bp); 3110 3111 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG, 3112 &bp->iov_task_state)) 3113 bnx2x_vf_mbx(bp); 3114 } 3115 3116 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) 3117 { 3118 smp_mb__before_atomic(); 3119 set_bit(flag, &bp->iov_task_state); 3120 smp_mb__after_atomic(); 3121 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); 3122 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0); 3123 } 3124