1 /* bnx2x_sriov.c: QLogic Everest network driver. 2 * 3 * Copyright 2009-2013 Broadcom Corporation 4 * Copyright 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * Unless you and QLogic execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2, available 10 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 11 * 12 * Notwithstanding the above, under no circumstances may you combine this 13 * software in any way with any other QLogic software provided under a 14 * license other than the GPL, without QLogic's express prior written 15 * consent. 16 * 17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 18 * Written by: Shmulik Ravid 19 * Ariel Elior <ariel.elior@qlogic.com> 20 * 21 */ 22 #include "bnx2x.h" 23 #include "bnx2x_init.h" 24 #include "bnx2x_cmn.h" 25 #include "bnx2x_sp.h" 26 #include <linux/crc32.h> 27 #include <linux/if_vlan.h> 28 29 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 30 struct bnx2x_virtf **vf, 31 struct pf_vf_bulletin_content **bulletin, 32 bool test_queue); 33 34 /* General service functions */ 35 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 36 u16 pf_id) 37 { 38 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 39 pf_id); 40 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 41 pf_id); 42 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 43 pf_id); 44 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 45 pf_id); 46 } 47 48 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 49 u8 enable) 50 { 51 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 52 enable); 53 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 54 enable); 55 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 56 enable); 57 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 58 enable); 59 } 60 61 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 62 { 63 int idx; 64 65 for_each_vf(bp, idx) 66 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid) 67 break; 68 return idx; 69 } 70 71 static 72 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 73 { 74 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid); 75 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL; 76 } 77 78 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf, 79 u8 igu_sb_id, u8 segment, u16 index, u8 op, 80 u8 update) 81 { 82 /* acking a VF sb through the PF - use the GRC */ 83 u32 ctl; 84 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 85 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 86 u32 func_encode = vf->abs_vfid; 87 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id; 88 struct igu_regular cmd_data = {0}; 89 90 cmd_data.sb_id_and_flags = 91 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 92 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 93 (update << IGU_REGULAR_BUPDATE_SHIFT) | 94 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 95 96 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 97 func_encode << IGU_CTRL_REG_FID_SHIFT | 98 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 99 100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 101 cmd_data.sb_id_and_flags, igu_addr_data); 102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); 103 mmiowb(); 104 barrier(); 105 106 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 107 ctl, igu_addr_ctl); 108 REG_WR(bp, igu_addr_ctl, ctl); 109 mmiowb(); 110 barrier(); 111 } 112 113 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp, 114 struct bnx2x_virtf *vf, 115 bool print_err) 116 { 117 if (!bnx2x_leading_vfq(vf, sp_initialized)) { 118 if (print_err) 119 BNX2X_ERR("Slowpath objects not yet initialized!\n"); 120 else 121 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); 122 return false; 123 } 124 return true; 125 } 126 127 /* VFOP operations states */ 128 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf, 129 struct bnx2x_queue_init_params *init_params, 130 struct bnx2x_queue_setup_params *setup_params, 131 u16 q_idx, u16 sb_idx) 132 { 133 DP(BNX2X_MSG_IOV, 134 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", 135 vf->abs_vfid, 136 q_idx, 137 sb_idx, 138 init_params->tx.sb_cq_index, 139 init_params->tx.hc_rate, 140 setup_params->flags, 141 setup_params->txq_params.traffic_type); 142 } 143 144 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf, 145 struct bnx2x_queue_init_params *init_params, 146 struct bnx2x_queue_setup_params *setup_params, 147 u16 q_idx, u16 sb_idx) 148 { 149 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params; 150 151 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" 152 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n", 153 vf->abs_vfid, 154 q_idx, 155 sb_idx, 156 init_params->rx.sb_cq_index, 157 init_params->rx.hc_rate, 158 setup_params->gen_params.mtu, 159 rxq_params->buf_sz, 160 rxq_params->sge_buf_sz, 161 rxq_params->max_sges_pkt, 162 rxq_params->tpa_agg_sz, 163 setup_params->flags, 164 rxq_params->drop_flags, 165 rxq_params->cache_line_log); 166 } 167 168 void bnx2x_vfop_qctor_prep(struct bnx2x *bp, 169 struct bnx2x_virtf *vf, 170 struct bnx2x_vf_queue *q, 171 struct bnx2x_vf_queue_construct_params *p, 172 unsigned long q_type) 173 { 174 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init; 175 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup; 176 177 /* INIT */ 178 179 /* Enable host coalescing in the transition to INIT state */ 180 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags)) 181 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags); 182 183 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags)) 184 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags); 185 186 /* FW SB ID */ 187 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 188 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 189 190 /* context */ 191 init_p->cxts[0] = q->cxt; 192 193 /* SETUP */ 194 195 /* Setup-op general parameters */ 196 setup_p->gen_params.spcl_id = vf->sp_cl_id; 197 setup_p->gen_params.stat_id = vfq_stat_id(vf, q); 198 setup_p->gen_params.fp_hsi = vf->fp_hsi; 199 200 /* Setup-op flags: 201 * collect statistics, zero statistics, local-switching, security, 202 * OV for Flex10, RSS and MCAST for leading 203 */ 204 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags)) 205 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags); 206 207 /* for VFs, enable tx switching, bd coherency, and mac address 208 * anti-spoofing 209 */ 210 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags); 211 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags); 212 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags); 213 214 /* Setup-op rx parameters */ 215 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) { 216 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params; 217 218 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q); 219 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx); 220 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid); 221 222 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags)) 223 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES; 224 } 225 226 /* Setup-op tx parameters */ 227 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) { 228 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss; 229 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 230 } 231 } 232 233 static int bnx2x_vf_queue_create(struct bnx2x *bp, 234 struct bnx2x_virtf *vf, int qid, 235 struct bnx2x_vf_queue_construct_params *qctor) 236 { 237 struct bnx2x_queue_state_params *q_params; 238 int rc = 0; 239 240 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 241 242 /* Prepare ramrod information */ 243 q_params = &qctor->qstate; 244 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj); 245 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags); 246 247 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) == 248 BNX2X_Q_LOGICAL_STATE_ACTIVE) { 249 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); 250 goto out; 251 } 252 253 /* Run Queue 'construction' ramrods */ 254 q_params->cmd = BNX2X_Q_CMD_INIT; 255 rc = bnx2x_queue_state_change(bp, q_params); 256 if (rc) 257 goto out; 258 259 memcpy(&q_params->params.setup, &qctor->prep_qsetup, 260 sizeof(struct bnx2x_queue_setup_params)); 261 q_params->cmd = BNX2X_Q_CMD_SETUP; 262 rc = bnx2x_queue_state_change(bp, q_params); 263 if (rc) 264 goto out; 265 266 /* enable interrupts */ 267 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)), 268 USTORM_ID, 0, IGU_INT_ENABLE, 0); 269 out: 270 return rc; 271 } 272 273 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf, 274 int qid) 275 { 276 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT, 277 BNX2X_Q_CMD_TERMINATE, 278 BNX2X_Q_CMD_CFC_DEL}; 279 struct bnx2x_queue_state_params q_params; 280 int rc, i; 281 282 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 283 284 /* Prepare ramrod information */ 285 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params)); 286 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 287 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 288 289 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) == 290 BNX2X_Q_LOGICAL_STATE_STOPPED) { 291 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); 292 goto out; 293 } 294 295 /* Run Queue 'destruction' ramrods */ 296 for (i = 0; i < ARRAY_SIZE(cmds); i++) { 297 q_params.cmd = cmds[i]; 298 rc = bnx2x_queue_state_change(bp, &q_params); 299 if (rc) { 300 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]); 301 return rc; 302 } 303 } 304 out: 305 /* Clean Context */ 306 if (bnx2x_vfq(vf, qid, cxt)) { 307 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0; 308 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0; 309 } 310 311 return 0; 312 } 313 314 static void 315 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid) 316 { 317 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 318 if (vf) { 319 /* the first igu entry belonging to VFs of this PF */ 320 if (!BP_VFDB(bp)->first_vf_igu_entry) 321 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id; 322 323 /* the first igu entry belonging to this VF */ 324 if (!vf_sb_count(vf)) 325 vf->igu_base_id = igu_sb_id; 326 327 ++vf_sb_count(vf); 328 ++vf->sb_count; 329 } 330 BP_VFDB(bp)->vf_sbs_pool++; 331 } 332 333 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp, 334 struct bnx2x_vlan_mac_obj *obj, 335 atomic_t *counter) 336 { 337 struct list_head *pos; 338 int read_lock; 339 int cnt = 0; 340 341 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj); 342 if (read_lock) 343 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); 344 345 list_for_each(pos, &obj->head) 346 cnt++; 347 348 if (!read_lock) 349 bnx2x_vlan_mac_h_read_unlock(bp, obj); 350 351 atomic_set(counter, cnt); 352 } 353 354 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf, 355 int qid, bool drv_only, int type) 356 { 357 struct bnx2x_vlan_mac_ramrod_params ramrod; 358 int rc; 359 360 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, 361 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : 362 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); 363 364 /* Prepare ramrod params */ 365 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 366 if (type == BNX2X_VF_FILTER_VLAN_MAC) { 367 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 368 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); 369 } else if (type == BNX2X_VF_FILTER_MAC) { 370 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 371 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 372 } else { 373 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 374 } 375 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL; 376 377 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 378 if (drv_only) 379 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 380 else 381 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 382 383 /* Start deleting */ 384 rc = ramrod.vlan_mac_obj->delete_all(bp, 385 ramrod.vlan_mac_obj, 386 &ramrod.user_req.vlan_mac_flags, 387 &ramrod.ramrod_flags); 388 if (rc) { 389 BNX2X_ERR("Failed to delete all %s\n", 390 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" : 391 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs"); 392 return rc; 393 } 394 395 return 0; 396 } 397 398 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp, 399 struct bnx2x_virtf *vf, int qid, 400 struct bnx2x_vf_mac_vlan_filter *filter, 401 bool drv_only) 402 { 403 struct bnx2x_vlan_mac_ramrod_params ramrod; 404 int rc; 405 406 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", 407 vf->abs_vfid, filter->add ? "Adding" : "Deleting", 408 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MAC" : 409 (filter->type == BNX2X_VF_FILTER_MAC) ? "MAC" : "VLAN"); 410 411 /* Prepare ramrod params */ 412 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 413 if (filter->type == BNX2X_VF_FILTER_VLAN_MAC) { 414 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj); 415 ramrod.user_req.u.vlan.vlan = filter->vid; 416 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 417 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 418 } else if (filter->type == BNX2X_VF_FILTER_VLAN) { 419 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 420 ramrod.user_req.u.vlan.vlan = filter->vid; 421 } else { 422 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 423 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 424 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 425 } 426 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD : 427 BNX2X_VLAN_MAC_DEL; 428 429 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 430 if (drv_only) 431 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 432 else 433 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 434 435 /* Add/Remove the filter */ 436 rc = bnx2x_config_vlan_mac(bp, &ramrod); 437 if (rc == -EEXIST) 438 return 0; 439 if (rc) { 440 BNX2X_ERR("Failed to %s %s\n", 441 filter->add ? "add" : "delete", 442 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? 443 "VLAN-MAC" : 444 (filter->type == BNX2X_VF_FILTER_MAC) ? 445 "MAC" : "VLAN"); 446 return rc; 447 } 448 449 filter->applied = true; 450 451 return 0; 452 } 453 454 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf, 455 struct bnx2x_vf_mac_vlan_filters *filters, 456 int qid, bool drv_only) 457 { 458 int rc = 0, i; 459 460 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 461 462 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 463 return -EINVAL; 464 465 /* Prepare ramrod params */ 466 for (i = 0; i < filters->count; i++) { 467 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, 468 &filters->filters[i], drv_only); 469 if (rc) 470 break; 471 } 472 473 /* Rollback if needed */ 474 if (i != filters->count) { 475 BNX2X_ERR("Managed only %d/%d filters - rolling back\n", 476 i, filters->count); 477 while (--i >= 0) { 478 if (!filters->filters[i].applied) 479 continue; 480 filters->filters[i].add = !filters->filters[i].add; 481 bnx2x_vf_mac_vlan_config(bp, vf, qid, 482 &filters->filters[i], 483 drv_only); 484 } 485 } 486 487 /* It's our responsibility to free the filters */ 488 kfree(filters); 489 490 return rc; 491 } 492 493 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid, 494 struct bnx2x_vf_queue_construct_params *qctor) 495 { 496 int rc; 497 498 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 499 500 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor); 501 if (rc) 502 goto op_err; 503 504 /* Schedule the configuration of any pending vlan filters */ 505 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN, 506 BNX2X_MSG_IOV); 507 return 0; 508 op_err: 509 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 510 return rc; 511 } 512 513 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf, 514 int qid) 515 { 516 int rc; 517 518 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 519 520 /* If needed, clean the filtering data base */ 521 if ((qid == LEADING_IDX) && 522 bnx2x_validate_vf_sp_objs(bp, vf, false)) { 523 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 524 BNX2X_VF_FILTER_VLAN_MAC); 525 if (rc) 526 goto op_err; 527 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 528 BNX2X_VF_FILTER_VLAN); 529 if (rc) 530 goto op_err; 531 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, 532 BNX2X_VF_FILTER_MAC); 533 if (rc) 534 goto op_err; 535 } 536 537 /* Terminate queue */ 538 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) { 539 struct bnx2x_queue_state_params qstate; 540 541 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 542 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 543 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED; 544 qstate.cmd = BNX2X_Q_CMD_TERMINATE; 545 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 546 rc = bnx2x_queue_state_change(bp, &qstate); 547 if (rc) 548 goto op_err; 549 } 550 551 return 0; 552 op_err: 553 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 554 return rc; 555 } 556 557 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf, 558 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only) 559 { 560 struct bnx2x_mcast_list_elem *mc = NULL; 561 struct bnx2x_mcast_ramrod_params mcast; 562 int rc, i; 563 564 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 565 566 /* Prepare Multicast command */ 567 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params)); 568 mcast.mcast_obj = &vf->mcast_obj; 569 if (drv_only) 570 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags); 571 else 572 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags); 573 if (mc_num) { 574 mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem), 575 GFP_KERNEL); 576 if (!mc) { 577 BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n"); 578 return -ENOMEM; 579 } 580 } 581 582 if (mc_num) { 583 INIT_LIST_HEAD(&mcast.mcast_list); 584 for (i = 0; i < mc_num; i++) { 585 mc[i].mac = mcasts[i]; 586 list_add_tail(&mc[i].link, 587 &mcast.mcast_list); 588 } 589 590 /* add new mcasts */ 591 mcast.mcast_list_len = mc_num; 592 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_SET); 593 if (rc) 594 BNX2X_ERR("Failed to set multicasts\n"); 595 } else { 596 /* clear existing mcasts */ 597 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL); 598 if (rc) 599 BNX2X_ERR("Failed to remove multicasts\n"); 600 } 601 602 kfree(mc); 603 604 return rc; 605 } 606 607 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid, 608 struct bnx2x_rx_mode_ramrod_params *ramrod, 609 struct bnx2x_virtf *vf, 610 unsigned long accept_flags) 611 { 612 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid); 613 614 memset(ramrod, 0, sizeof(*ramrod)); 615 ramrod->cid = vfq->cid; 616 ramrod->cl_id = vfq_cl_id(vf, vfq); 617 ramrod->rx_mode_obj = &bp->rx_mode_obj; 618 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid); 619 ramrod->rx_accept_flags = accept_flags; 620 ramrod->tx_accept_flags = accept_flags; 621 ramrod->pstate = &vf->filter_state; 622 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING; 623 624 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 625 set_bit(RAMROD_RX, &ramrod->ramrod_flags); 626 set_bit(RAMROD_TX, &ramrod->ramrod_flags); 627 628 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2); 629 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2); 630 } 631 632 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf, 633 int qid, unsigned long accept_flags) 634 { 635 struct bnx2x_rx_mode_ramrod_params ramrod; 636 637 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 638 639 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags); 640 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 641 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags; 642 return bnx2x_config_rx_mode(bp, &ramrod); 643 } 644 645 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid) 646 { 647 int rc; 648 649 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 650 651 /* Remove all classification configuration for leading queue */ 652 if (qid == LEADING_IDX) { 653 rc = bnx2x_vf_rxmode(bp, vf, qid, 0); 654 if (rc) 655 goto op_err; 656 657 /* Remove filtering if feasible */ 658 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) { 659 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 660 false, 661 BNX2X_VF_FILTER_VLAN_MAC); 662 if (rc) 663 goto op_err; 664 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 665 false, 666 BNX2X_VF_FILTER_VLAN); 667 if (rc) 668 goto op_err; 669 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 670 false, 671 BNX2X_VF_FILTER_MAC); 672 if (rc) 673 goto op_err; 674 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false); 675 if (rc) 676 goto op_err; 677 } 678 } 679 680 /* Destroy queue */ 681 rc = bnx2x_vf_queue_destroy(bp, vf, qid); 682 if (rc) 683 goto op_err; 684 return rc; 685 op_err: 686 BNX2X_ERR("vf[%d:%d] error: rc %d\n", 687 vf->abs_vfid, qid, rc); 688 return rc; 689 } 690 691 /* VF enable primitives 692 * when pretend is required the caller is responsible 693 * for calling pretend prior to calling these routines 694 */ 695 696 /* internal vf enable - until vf is enabled internally all transactions 697 * are blocked. This routine should always be called last with pretend. 698 */ 699 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable) 700 { 701 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); 702 } 703 704 /* clears vf error in all semi blocks */ 705 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid) 706 { 707 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); 708 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); 709 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); 710 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); 711 } 712 713 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid) 714 { 715 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5; 716 u32 was_err_reg = 0; 717 718 switch (was_err_group) { 719 case 0: 720 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR; 721 break; 722 case 1: 723 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR; 724 break; 725 case 2: 726 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR; 727 break; 728 case 3: 729 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR; 730 break; 731 } 732 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); 733 } 734 735 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf) 736 { 737 int i; 738 u32 val; 739 740 /* Set VF masks and configuration - pretend */ 741 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 742 743 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 744 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 745 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 746 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 747 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 748 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 749 750 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 751 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); 752 val &= ~IGU_VF_CONF_PARENT_MASK; 753 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; 754 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 755 756 DP(BNX2X_MSG_IOV, 757 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n", 758 vf->abs_vfid, val); 759 760 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 761 762 /* iterate over all queues, clear sb consumer */ 763 for (i = 0; i < vf_sb_count(vf); i++) { 764 u8 igu_sb_id = vf_igu_sb(vf, i); 765 766 /* zero prod memory */ 767 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); 768 769 /* clear sb state machine */ 770 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id, 771 false /* VF */); 772 773 /* disable + update */ 774 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0, 775 IGU_INT_DISABLE, 1); 776 } 777 } 778 779 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid) 780 { 781 /* set the VF-PF association in the FW */ 782 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp)); 783 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1); 784 785 /* clear vf errors*/ 786 bnx2x_vf_semi_clear_err(bp, abs_vfid); 787 bnx2x_vf_pglue_clear_err(bp, abs_vfid); 788 789 /* internal vf-enable - pretend */ 790 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid)); 791 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); 792 bnx2x_vf_enable_internal(bp, true); 793 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 794 } 795 796 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf) 797 { 798 /* Reset vf in IGU interrupts are still disabled */ 799 bnx2x_vf_igu_reset(bp, vf); 800 801 /* pretend to enable the vf with the PBF */ 802 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 803 REG_WR(bp, PBF_REG_DISABLE_VF, 0); 804 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 805 } 806 807 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) 808 { 809 struct pci_dev *dev; 810 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 811 812 if (!vf) 813 return false; 814 815 dev = pci_get_domain_bus_and_slot(vf->domain, vf->bus, vf->devfn); 816 if (dev) 817 return bnx2x_is_pcie_pending(dev); 818 return false; 819 } 820 821 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid) 822 { 823 /* Verify no pending pci transactions */ 824 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid)) 825 BNX2X_ERR("PCIE Transactions still pending\n"); 826 827 return 0; 828 } 829 830 /* must be called after the number of PF queues and the number of VFs are 831 * both known 832 */ 833 static void 834 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 835 { 836 struct vf_pf_resc_request *resc = &vf->alloc_resc; 837 838 /* will be set only during VF-ACQUIRE */ 839 resc->num_rxqs = 0; 840 resc->num_txqs = 0; 841 842 resc->num_mac_filters = VF_MAC_CREDIT_CNT; 843 resc->num_vlan_filters = VF_VLAN_CREDIT_CNT; 844 845 /* no real limitation */ 846 resc->num_mc_filters = 0; 847 848 /* num_sbs already set */ 849 resc->num_sbs = vf->sb_count; 850 } 851 852 /* FLR routines: */ 853 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 854 { 855 /* reset the state variables */ 856 bnx2x_iov_static_resc(bp, vf); 857 vf->state = VF_FREE; 858 } 859 860 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf) 861 { 862 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 863 864 /* DQ usage counter */ 865 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 866 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT, 867 "DQ VF usage counter timed out", 868 poll_cnt); 869 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 870 871 /* FW cleanup command - poll for the results */ 872 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid), 873 poll_cnt)) 874 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid); 875 876 /* verify TX hw is flushed */ 877 bnx2x_tx_hw_flushed(bp, poll_cnt); 878 } 879 880 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf) 881 { 882 int rc, i; 883 884 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 885 886 /* the cleanup operations are valid if and only if the VF 887 * was first acquired. 888 */ 889 for (i = 0; i < vf_rxq_count(vf); i++) { 890 rc = bnx2x_vf_queue_flr(bp, vf, i); 891 if (rc) 892 goto out; 893 } 894 895 /* remove multicasts */ 896 bnx2x_vf_mcast(bp, vf, NULL, 0, true); 897 898 /* dispatch final cleanup and wait for HW queues to flush */ 899 bnx2x_vf_flr_clnup_hw(bp, vf); 900 901 /* release VF resources */ 902 bnx2x_vf_free_resc(bp, vf); 903 904 vf->malicious = false; 905 906 /* re-open the mailbox */ 907 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 908 return; 909 out: 910 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n", 911 vf->abs_vfid, i, rc); 912 } 913 914 static void bnx2x_vf_flr_clnup(struct bnx2x *bp) 915 { 916 struct bnx2x_virtf *vf; 917 int i; 918 919 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) { 920 /* VF should be RESET & in FLR cleanup states */ 921 if (bnx2x_vf(bp, i, state) != VF_RESET || 922 !bnx2x_vf(bp, i, flr_clnup_stage)) 923 continue; 924 925 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", 926 i, BNX2X_NR_VIRTFN(bp)); 927 928 vf = BP_VF(bp, i); 929 930 /* lock the vf pf channel */ 931 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 932 933 /* invoke the VF FLR SM */ 934 bnx2x_vf_flr(bp, vf); 935 936 /* mark the VF to be ACKED and continue */ 937 vf->flr_clnup_stage = false; 938 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 939 } 940 941 /* Acknowledge the handled VFs. 942 * we are acknowledge all the vfs which an flr was requested for, even 943 * if amongst them there are such that we never opened, since the mcp 944 * will interrupt us immediately again if we only ack some of the bits, 945 * resulting in an endless loop. This can happen for example in KVM 946 * where an 'all ones' flr request is sometimes given by hyper visor 947 */ 948 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", 949 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 950 for (i = 0; i < FLRD_VFS_DWORDS; i++) 951 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 952 bp->vfdb->flrd_vfs[i]); 953 954 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0); 955 956 /* clear the acked bits - better yet if the MCP implemented 957 * write to clear semantics 958 */ 959 for (i = 0; i < FLRD_VFS_DWORDS; i++) 960 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0); 961 } 962 963 void bnx2x_vf_handle_flr_event(struct bnx2x *bp) 964 { 965 int i; 966 967 /* Read FLR'd VFs */ 968 for (i = 0; i < FLRD_VFS_DWORDS; i++) 969 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]); 970 971 DP(BNX2X_MSG_MCP, 972 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n", 973 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 974 975 for_each_vf(bp, i) { 976 struct bnx2x_virtf *vf = BP_VF(bp, i); 977 u32 reset = 0; 978 979 if (vf->abs_vfid < 32) 980 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid); 981 else 982 reset = bp->vfdb->flrd_vfs[1] & 983 (1 << (vf->abs_vfid - 32)); 984 985 if (reset) { 986 /* set as reset and ready for cleanup */ 987 vf->state = VF_RESET; 988 vf->flr_clnup_stage = true; 989 990 DP(BNX2X_MSG_IOV, 991 "Initiating Final cleanup for VF %d\n", 992 vf->abs_vfid); 993 } 994 } 995 996 /* do the FLR cleanup for all marked VFs*/ 997 bnx2x_vf_flr_clnup(bp); 998 } 999 1000 /* IOV global initialization routines */ 1001 void bnx2x_iov_init_dq(struct bnx2x *bp) 1002 { 1003 if (!IS_SRIOV(bp)) 1004 return; 1005 1006 /* Set the DQ such that the CID reflect the abs_vfid */ 1007 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); 1008 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 1009 1010 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to 1011 * the PF L2 queues 1012 */ 1013 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 1014 1015 /* The VF window size is the log2 of the max number of CIDs per VF */ 1016 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 1017 1018 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 1019 * the Pf doorbell size although the 2 are independent. 1020 */ 1021 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); 1022 1023 /* No security checks for now - 1024 * configure single rule (out of 16) mask = 0x1, value = 0x0, 1025 * CID range 0 - 0x1ffff 1026 */ 1027 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); 1028 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); 1029 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 1030 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 1031 1032 /* set the VF doorbell threshold. This threshold represents the amount 1033 * of doorbells allowed in the main DORQ fifo for a specific VF. 1034 */ 1035 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64); 1036 } 1037 1038 void bnx2x_iov_init_dmae(struct bnx2x *bp) 1039 { 1040 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV)) 1041 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); 1042 } 1043 1044 static int bnx2x_vf_domain(struct bnx2x *bp, int vfid) 1045 { 1046 struct pci_dev *dev = bp->pdev; 1047 1048 return pci_domain_nr(dev->bus); 1049 } 1050 1051 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid) 1052 { 1053 struct pci_dev *dev = bp->pdev; 1054 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1055 1056 return dev->bus->number + ((dev->devfn + iov->offset + 1057 iov->stride * vfid) >> 8); 1058 } 1059 1060 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid) 1061 { 1062 struct pci_dev *dev = bp->pdev; 1063 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1064 1065 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff; 1066 } 1067 1068 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf) 1069 { 1070 int i, n; 1071 struct pci_dev *dev = bp->pdev; 1072 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1073 1074 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) { 1075 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i); 1076 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i); 1077 1078 size /= iov->total; 1079 vf->bars[n].bar = start + size * vf->abs_vfid; 1080 vf->bars[n].size = size; 1081 } 1082 } 1083 1084 static int 1085 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp) 1086 { 1087 int sb_id; 1088 u32 val; 1089 u8 fid, current_pf = 0; 1090 1091 /* IGU in normal mode - read CAM */ 1092 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) { 1093 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); 1094 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 1095 continue; 1096 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); 1097 if (fid & IGU_FID_ENCODE_IS_PF) 1098 current_pf = fid & IGU_FID_PF_NUM_MASK; 1099 else if (current_pf == BP_FUNC(bp)) 1100 bnx2x_vf_set_igu_info(bp, sb_id, 1101 (fid & IGU_FID_VF_NUM_MASK)); 1102 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", 1103 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"), 1104 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) : 1105 (fid & IGU_FID_VF_NUM_MASK)), sb_id, 1106 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); 1107 } 1108 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); 1109 return BP_VFDB(bp)->vf_sbs_pool; 1110 } 1111 1112 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp) 1113 { 1114 if (bp->vfdb) { 1115 kfree(bp->vfdb->vfqs); 1116 kfree(bp->vfdb->vfs); 1117 kfree(bp->vfdb); 1118 } 1119 bp->vfdb = NULL; 1120 } 1121 1122 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1123 { 1124 int pos; 1125 struct pci_dev *dev = bp->pdev; 1126 1127 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 1128 if (!pos) { 1129 BNX2X_ERR("failed to find SRIOV capability in device\n"); 1130 return -ENODEV; 1131 } 1132 1133 iov->pos = pos; 1134 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); 1135 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); 1136 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total); 1137 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial); 1138 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset); 1139 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride); 1140 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); 1141 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); 1142 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); 1143 1144 return 0; 1145 } 1146 1147 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1148 { 1149 u32 val; 1150 1151 /* read the SRIOV capability structure 1152 * The fields can be read via configuration read or 1153 * directly from the device (starting at offset PCICFG_OFFSET) 1154 */ 1155 if (bnx2x_sriov_pci_cfg_info(bp, iov)) 1156 return -ENODEV; 1157 1158 /* get the number of SRIOV bars */ 1159 iov->nres = 0; 1160 1161 /* read the first_vfid */ 1162 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 1163 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) 1164 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp)); 1165 1166 DP(BNX2X_MSG_IOV, 1167 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n", 1168 BP_FUNC(bp), 1169 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total, 1170 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz); 1171 1172 return 0; 1173 } 1174 1175 /* must be called after PF bars are mapped */ 1176 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, 1177 int num_vfs_param) 1178 { 1179 int err, i; 1180 struct bnx2x_sriov *iov; 1181 struct pci_dev *dev = bp->pdev; 1182 1183 bp->vfdb = NULL; 1184 1185 /* verify is pf */ 1186 if (IS_VF(bp)) 1187 return 0; 1188 1189 /* verify sriov capability is present in configuration space */ 1190 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV)) 1191 return 0; 1192 1193 /* verify chip revision */ 1194 if (CHIP_IS_E1x(bp)) 1195 return 0; 1196 1197 /* check if SRIOV support is turned off */ 1198 if (!num_vfs_param) 1199 return 0; 1200 1201 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */ 1202 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) { 1203 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n", 1204 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID); 1205 return 0; 1206 } 1207 1208 /* SRIOV can be enabled only with MSIX */ 1209 if (int_mode_param == BNX2X_INT_MODE_MSI || 1210 int_mode_param == BNX2X_INT_MODE_INTX) { 1211 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); 1212 return 0; 1213 } 1214 1215 err = -EIO; 1216 /* verify ari is enabled */ 1217 if (!pci_ari_enabled(bp->pdev->bus)) { 1218 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); 1219 return 0; 1220 } 1221 1222 /* verify igu is in normal mode */ 1223 if (CHIP_INT_MODE_IS_BC(bp)) { 1224 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); 1225 return 0; 1226 } 1227 1228 /* allocate the vfs database */ 1229 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL); 1230 if (!bp->vfdb) { 1231 BNX2X_ERR("failed to allocate vf database\n"); 1232 err = -ENOMEM; 1233 goto failed; 1234 } 1235 1236 /* get the sriov info - Linux already collected all the pertinent 1237 * information, however the sriov structure is for the private use 1238 * of the pci module. Also we want this information regardless 1239 * of the hyper-visor. 1240 */ 1241 iov = &(bp->vfdb->sriov); 1242 err = bnx2x_sriov_info(bp, iov); 1243 if (err) 1244 goto failed; 1245 1246 /* SR-IOV capability was enabled but there are no VFs*/ 1247 if (iov->total == 0) 1248 goto failed; 1249 1250 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); 1251 1252 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", 1253 num_vfs_param, iov->nr_virtfn); 1254 1255 /* allocate the vf array */ 1256 bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * 1257 BNX2X_NR_VIRTFN(bp), GFP_KERNEL); 1258 if (!bp->vfdb->vfs) { 1259 BNX2X_ERR("failed to allocate vf array\n"); 1260 err = -ENOMEM; 1261 goto failed; 1262 } 1263 1264 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */ 1265 for_each_vf(bp, i) { 1266 bnx2x_vf(bp, i, index) = i; 1267 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i; 1268 bnx2x_vf(bp, i, state) = VF_FREE; 1269 mutex_init(&bnx2x_vf(bp, i, op_mutex)); 1270 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE; 1271 } 1272 1273 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */ 1274 if (!bnx2x_get_vf_igu_cam_info(bp)) { 1275 BNX2X_ERR("No entries in IGU CAM for vfs\n"); 1276 err = -EINVAL; 1277 goto failed; 1278 } 1279 1280 /* allocate the queue arrays for all VFs */ 1281 bp->vfdb->vfqs = kzalloc( 1282 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue), 1283 GFP_KERNEL); 1284 1285 if (!bp->vfdb->vfqs) { 1286 BNX2X_ERR("failed to allocate vf queue array\n"); 1287 err = -ENOMEM; 1288 goto failed; 1289 } 1290 1291 /* Prepare the VFs event synchronization mechanism */ 1292 mutex_init(&bp->vfdb->event_mutex); 1293 1294 mutex_init(&bp->vfdb->bulletin_mutex); 1295 1296 if (SHMEM2_HAS(bp, sriov_switch_mode)) 1297 SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB); 1298 1299 return 0; 1300 failed: 1301 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err); 1302 __bnx2x_iov_free_vfdb(bp); 1303 return err; 1304 } 1305 1306 void bnx2x_iov_remove_one(struct bnx2x *bp) 1307 { 1308 int vf_idx; 1309 1310 /* if SRIOV is not enabled there's nothing to do */ 1311 if (!IS_SRIOV(bp)) 1312 return; 1313 1314 bnx2x_disable_sriov(bp); 1315 1316 /* disable access to all VFs */ 1317 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) { 1318 bnx2x_pretend_func(bp, 1319 HW_VF_HANDLE(bp, 1320 bp->vfdb->sriov.first_vf_in_pf + 1321 vf_idx)); 1322 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", 1323 bp->vfdb->sriov.first_vf_in_pf + vf_idx); 1324 bnx2x_vf_enable_internal(bp, 0); 1325 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1326 } 1327 1328 /* free vf database */ 1329 __bnx2x_iov_free_vfdb(bp); 1330 } 1331 1332 void bnx2x_iov_free_mem(struct bnx2x *bp) 1333 { 1334 int i; 1335 1336 if (!IS_SRIOV(bp)) 1337 return; 1338 1339 /* free vfs hw contexts */ 1340 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1341 struct hw_dma *cxt = &bp->vfdb->context[i]; 1342 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size); 1343 } 1344 1345 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr, 1346 BP_VFDB(bp)->sp_dma.mapping, 1347 BP_VFDB(bp)->sp_dma.size); 1348 1349 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr, 1350 BP_VF_MBX_DMA(bp)->mapping, 1351 BP_VF_MBX_DMA(bp)->size); 1352 1353 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr, 1354 BP_VF_BULLETIN_DMA(bp)->mapping, 1355 BP_VF_BULLETIN_DMA(bp)->size); 1356 } 1357 1358 int bnx2x_iov_alloc_mem(struct bnx2x *bp) 1359 { 1360 size_t tot_size; 1361 int i, rc = 0; 1362 1363 if (!IS_SRIOV(bp)) 1364 return rc; 1365 1366 /* allocate vfs hw contexts */ 1367 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) * 1368 BNX2X_CIDS_PER_VF * sizeof(union cdu_context); 1369 1370 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1371 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i); 1372 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ); 1373 1374 if (cxt->size) { 1375 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size); 1376 if (!cxt->addr) 1377 goto alloc_mem_err; 1378 } else { 1379 cxt->addr = NULL; 1380 cxt->mapping = 0; 1381 } 1382 tot_size -= cxt->size; 1383 } 1384 1385 /* allocate vfs ramrods dma memory - client_init and set_mac */ 1386 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp); 1387 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping, 1388 tot_size); 1389 if (!BP_VFDB(bp)->sp_dma.addr) 1390 goto alloc_mem_err; 1391 BP_VFDB(bp)->sp_dma.size = tot_size; 1392 1393 /* allocate mailboxes */ 1394 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE; 1395 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping, 1396 tot_size); 1397 if (!BP_VF_MBX_DMA(bp)->addr) 1398 goto alloc_mem_err; 1399 1400 BP_VF_MBX_DMA(bp)->size = tot_size; 1401 1402 /* allocate local bulletin boards */ 1403 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE; 1404 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping, 1405 tot_size); 1406 if (!BP_VF_BULLETIN_DMA(bp)->addr) 1407 goto alloc_mem_err; 1408 1409 BP_VF_BULLETIN_DMA(bp)->size = tot_size; 1410 1411 return 0; 1412 1413 alloc_mem_err: 1414 return -ENOMEM; 1415 } 1416 1417 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf, 1418 struct bnx2x_vf_queue *q) 1419 { 1420 u8 cl_id = vfq_cl_id(vf, q); 1421 u8 func_id = FW_VF_HANDLE(vf->abs_vfid); 1422 unsigned long q_type = 0; 1423 1424 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1425 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1426 1427 /* Queue State object */ 1428 bnx2x_init_queue_obj(bp, &q->sp_obj, 1429 cl_id, &q->cid, 1, func_id, 1430 bnx2x_vf_sp(bp, vf, q_data), 1431 bnx2x_vf_sp_map(bp, vf, q_data), 1432 q_type); 1433 1434 /* sp indication is set only when vlan/mac/etc. are initialized */ 1435 q->sp_initialized = false; 1436 1437 DP(BNX2X_MSG_IOV, 1438 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n", 1439 vf->abs_vfid, q->sp_obj.func_id, q->cid); 1440 } 1441 1442 static int bnx2x_max_speed_cap(struct bnx2x *bp) 1443 { 1444 u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)]; 1445 1446 if (supported & 1447 (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full)) 1448 return 20000; 1449 1450 return 10000; /* assume lowest supported speed is 10G */ 1451 } 1452 1453 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx) 1454 { 1455 struct bnx2x_link_report_data *state = &bp->last_reported_link; 1456 struct pf_vf_bulletin_content *bulletin; 1457 struct bnx2x_virtf *vf; 1458 bool update = true; 1459 int rc = 0; 1460 1461 /* sanity and init */ 1462 rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false); 1463 if (rc) 1464 return rc; 1465 1466 mutex_lock(&bp->vfdb->bulletin_mutex); 1467 1468 if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) { 1469 bulletin->valid_bitmap |= 1 << LINK_VALID; 1470 1471 bulletin->link_speed = state->line_speed; 1472 bulletin->link_flags = 0; 1473 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1474 &state->link_report_flags)) 1475 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1476 if (test_bit(BNX2X_LINK_REPORT_FD, 1477 &state->link_report_flags)) 1478 bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX; 1479 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON, 1480 &state->link_report_flags)) 1481 bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON; 1482 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON, 1483 &state->link_report_flags)) 1484 bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON; 1485 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE && 1486 !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1487 bulletin->valid_bitmap |= 1 << LINK_VALID; 1488 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1489 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE && 1490 (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1491 bulletin->valid_bitmap |= 1 << LINK_VALID; 1492 bulletin->link_speed = bnx2x_max_speed_cap(bp); 1493 bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN; 1494 } else { 1495 update = false; 1496 } 1497 1498 if (update) { 1499 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV, 1500 "vf %d mode %u speed %d flags %x\n", idx, 1501 vf->link_cfg, bulletin->link_speed, bulletin->link_flags); 1502 1503 /* Post update on VF's bulletin board */ 1504 rc = bnx2x_post_vf_bulletin(bp, idx); 1505 if (rc) { 1506 BNX2X_ERR("failed to update VF[%d] bulletin\n", idx); 1507 goto out; 1508 } 1509 } 1510 1511 out: 1512 mutex_unlock(&bp->vfdb->bulletin_mutex); 1513 return rc; 1514 } 1515 1516 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state) 1517 { 1518 struct bnx2x *bp = netdev_priv(dev); 1519 struct bnx2x_virtf *vf = BP_VF(bp, idx); 1520 1521 if (!vf) 1522 return -EINVAL; 1523 1524 if (vf->link_cfg == link_state) 1525 return 0; /* nothing todo */ 1526 1527 vf->link_cfg = link_state; 1528 1529 return bnx2x_iov_link_update_vf(bp, idx); 1530 } 1531 1532 void bnx2x_iov_link_update(struct bnx2x *bp) 1533 { 1534 int vfid; 1535 1536 if (!IS_SRIOV(bp)) 1537 return; 1538 1539 for_each_vf(bp, vfid) 1540 bnx2x_iov_link_update_vf(bp, vfid); 1541 } 1542 1543 /* called by bnx2x_nic_load */ 1544 int bnx2x_iov_nic_init(struct bnx2x *bp) 1545 { 1546 int vfid; 1547 1548 if (!IS_SRIOV(bp)) { 1549 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); 1550 return 0; 1551 } 1552 1553 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); 1554 1555 /* let FLR complete ... */ 1556 msleep(100); 1557 1558 /* initialize vf database */ 1559 for_each_vf(bp, vfid) { 1560 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1561 1562 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) * 1563 BNX2X_CIDS_PER_VF; 1564 1565 union cdu_context *base_cxt = (union cdu_context *) 1566 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 1567 (base_vf_cid & (ILT_PAGE_CIDS-1)); 1568 1569 DP(BNX2X_MSG_IOV, 1570 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n", 1571 vf->abs_vfid, vf_sb_count(vf), base_vf_cid, 1572 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt); 1573 1574 /* init statically provisioned resources */ 1575 bnx2x_iov_static_resc(bp, vf); 1576 1577 /* queues are initialized during VF-ACQUIRE */ 1578 vf->filter_state = 0; 1579 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id); 1580 1581 bnx2x_init_credit_pool(&vf->vf_vlans_pool, 0, 1582 vf_vlan_rules_cnt(vf)); 1583 bnx2x_init_credit_pool(&vf->vf_macs_pool, 0, 1584 vf_mac_rules_cnt(vf)); 1585 1586 /* init mcast object - This object will be re-initialized 1587 * during VF-ACQUIRE with the proper cl_id and cid. 1588 * It needs to be initialized here so that it can be safely 1589 * handled by a subsequent FLR flow. 1590 */ 1591 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF, 1592 0xFF, 0xFF, 0xFF, 1593 bnx2x_vf_sp(bp, vf, mcast_rdata), 1594 bnx2x_vf_sp_map(bp, vf, mcast_rdata), 1595 BNX2X_FILTER_MCAST_PENDING, 1596 &vf->filter_state, 1597 BNX2X_OBJ_TYPE_RX_TX); 1598 1599 /* set the mailbox message addresses */ 1600 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *) 1601 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid * 1602 MBX_MSG_ALIGNED_SIZE); 1603 1604 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping + 1605 vfid * MBX_MSG_ALIGNED_SIZE; 1606 1607 /* Enable vf mailbox */ 1608 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 1609 } 1610 1611 /* Final VF init */ 1612 for_each_vf(bp, vfid) { 1613 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1614 1615 /* fill in the BDF and bars */ 1616 vf->domain = bnx2x_vf_domain(bp, vfid); 1617 vf->bus = bnx2x_vf_bus(bp, vfid); 1618 vf->devfn = bnx2x_vf_devfn(bp, vfid); 1619 bnx2x_vf_set_bars(bp, vf); 1620 1621 DP(BNX2X_MSG_IOV, 1622 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n", 1623 vf->abs_vfid, vf->bus, vf->devfn, 1624 (unsigned)vf->bars[0].bar, vf->bars[0].size, 1625 (unsigned)vf->bars[1].bar, vf->bars[1].size, 1626 (unsigned)vf->bars[2].bar, vf->bars[2].size); 1627 } 1628 1629 return 0; 1630 } 1631 1632 /* called by bnx2x_chip_cleanup */ 1633 int bnx2x_iov_chip_cleanup(struct bnx2x *bp) 1634 { 1635 int i; 1636 1637 if (!IS_SRIOV(bp)) 1638 return 0; 1639 1640 /* release all the VFs */ 1641 for_each_vf(bp, i) 1642 bnx2x_vf_release(bp, BP_VF(bp, i)); 1643 1644 return 0; 1645 } 1646 1647 /* called by bnx2x_init_hw_func, returns the next ilt line */ 1648 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) 1649 { 1650 int i; 1651 struct bnx2x_ilt *ilt = BP_ILT(bp); 1652 1653 if (!IS_SRIOV(bp)) 1654 return line; 1655 1656 /* set vfs ilt lines */ 1657 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1658 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i); 1659 1660 ilt->lines[line+i].page = hw_cxt->addr; 1661 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 1662 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 1663 } 1664 return line + i; 1665 } 1666 1667 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid) 1668 { 1669 return ((cid >= BNX2X_FIRST_VF_CID) && 1670 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS)); 1671 } 1672 1673 static 1674 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp, 1675 struct bnx2x_vf_queue *vfq, 1676 union event_ring_elem *elem) 1677 { 1678 unsigned long ramrod_flags = 0; 1679 int rc = 0; 1680 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); 1681 1682 /* Always push next commands out, don't wait here */ 1683 set_bit(RAMROD_CONT, &ramrod_flags); 1684 1685 switch (echo >> BNX2X_SWCID_SHIFT) { 1686 case BNX2X_FILTER_MAC_PENDING: 1687 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem, 1688 &ramrod_flags); 1689 break; 1690 case BNX2X_FILTER_VLAN_PENDING: 1691 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem, 1692 &ramrod_flags); 1693 break; 1694 default: 1695 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); 1696 return; 1697 } 1698 if (rc < 0) 1699 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 1700 else if (rc > 0) 1701 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); 1702 } 1703 1704 static 1705 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp, 1706 struct bnx2x_virtf *vf) 1707 { 1708 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 1709 int rc; 1710 1711 rparam.mcast_obj = &vf->mcast_obj; 1712 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw); 1713 1714 /* If there are pending mcast commands - send them */ 1715 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) { 1716 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 1717 if (rc < 0) 1718 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 1719 rc); 1720 } 1721 } 1722 1723 static 1724 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp, 1725 struct bnx2x_virtf *vf) 1726 { 1727 smp_mb__before_atomic(); 1728 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 1729 smp_mb__after_atomic(); 1730 } 1731 1732 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp, 1733 struct bnx2x_virtf *vf) 1734 { 1735 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw); 1736 } 1737 1738 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) 1739 { 1740 struct bnx2x_virtf *vf; 1741 int qidx = 0, abs_vfid; 1742 u8 opcode; 1743 u16 cid = 0xffff; 1744 1745 if (!IS_SRIOV(bp)) 1746 return 1; 1747 1748 /* first get the cid - the only events we handle here are cfc-delete 1749 * and set-mac completion 1750 */ 1751 opcode = elem->message.opcode; 1752 1753 switch (opcode) { 1754 case EVENT_RING_OPCODE_CFC_DEL: 1755 cid = SW_CID(elem->message.data.cfc_del_event.cid); 1756 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); 1757 break; 1758 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1759 case EVENT_RING_OPCODE_MULTICAST_RULES: 1760 case EVENT_RING_OPCODE_FILTERS_RULES: 1761 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1762 cid = SW_CID(elem->message.data.eth_event.echo); 1763 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); 1764 break; 1765 case EVENT_RING_OPCODE_VF_FLR: 1766 abs_vfid = elem->message.data.vf_flr_event.vf_id; 1767 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", 1768 abs_vfid); 1769 goto get_vf; 1770 case EVENT_RING_OPCODE_MALICIOUS_VF: 1771 abs_vfid = elem->message.data.malicious_vf_event.vf_id; 1772 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", 1773 abs_vfid, 1774 elem->message.data.malicious_vf_event.err_id); 1775 goto get_vf; 1776 default: 1777 return 1; 1778 } 1779 1780 /* check if the cid is the VF range */ 1781 if (!bnx2x_iov_is_vf_cid(bp, cid)) { 1782 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); 1783 return 1; 1784 } 1785 1786 /* extract vf and rxq index from vf_cid - relies on the following: 1787 * 1. vfid on cid reflects the true abs_vfid 1788 * 2. The max number of VFs (per path) is 64 1789 */ 1790 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1); 1791 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1792 get_vf: 1793 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 1794 1795 if (!vf) { 1796 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n", 1797 cid, abs_vfid); 1798 return 0; 1799 } 1800 1801 switch (opcode) { 1802 case EVENT_RING_OPCODE_CFC_DEL: 1803 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", 1804 vf->abs_vfid, qidx); 1805 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp, 1806 &vfq_get(vf, 1807 qidx)->sp_obj, 1808 BNX2X_Q_CMD_CFC_DEL); 1809 break; 1810 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1811 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", 1812 vf->abs_vfid, qidx); 1813 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem); 1814 break; 1815 case EVENT_RING_OPCODE_MULTICAST_RULES: 1816 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", 1817 vf->abs_vfid, qidx); 1818 bnx2x_vf_handle_mcast_eqe(bp, vf); 1819 break; 1820 case EVENT_RING_OPCODE_FILTERS_RULES: 1821 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", 1822 vf->abs_vfid, qidx); 1823 bnx2x_vf_handle_filters_eqe(bp, vf); 1824 break; 1825 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1826 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", 1827 vf->abs_vfid, qidx); 1828 bnx2x_vf_handle_rss_update_eqe(bp, vf); 1829 case EVENT_RING_OPCODE_VF_FLR: 1830 /* Do nothing for now */ 1831 return 0; 1832 case EVENT_RING_OPCODE_MALICIOUS_VF: 1833 vf->malicious = true; 1834 return 0; 1835 } 1836 1837 return 0; 1838 } 1839 1840 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid) 1841 { 1842 /* extract the vf from vf_cid - relies on the following: 1843 * 1. vfid on cid reflects the true abs_vfid 1844 * 2. The max number of VFs (per path) is 64 1845 */ 1846 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1847 return bnx2x_vf_by_abs_fid(bp, abs_vfid); 1848 } 1849 1850 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid, 1851 struct bnx2x_queue_sp_obj **q_obj) 1852 { 1853 struct bnx2x_virtf *vf; 1854 1855 if (!IS_SRIOV(bp)) 1856 return; 1857 1858 vf = bnx2x_vf_by_cid(bp, vf_cid); 1859 1860 if (vf) { 1861 /* extract queue index from vf_cid - relies on the following: 1862 * 1. vfid on cid reflects the true abs_vfid 1863 * 2. The max number of VFs (per path) is 64 1864 */ 1865 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1); 1866 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj); 1867 } else { 1868 BNX2X_ERR("No vf matching cid %d\n", vf_cid); 1869 } 1870 } 1871 1872 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) 1873 { 1874 int i; 1875 int first_queue_query_index, num_queues_req; 1876 dma_addr_t cur_data_offset; 1877 struct stats_query_entry *cur_query_entry; 1878 u8 stats_count = 0; 1879 bool is_fcoe = false; 1880 1881 if (!IS_SRIOV(bp)) 1882 return; 1883 1884 if (!NO_FCOE(bp)) 1885 is_fcoe = true; 1886 1887 /* fcoe adds one global request and one queue request */ 1888 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe; 1889 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1890 (is_fcoe ? 0 : 1); 1891 1892 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1893 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n", 1894 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index, 1895 first_queue_query_index + num_queues_req); 1896 1897 cur_data_offset = bp->fw_stats_data_mapping + 1898 offsetof(struct bnx2x_fw_stats_data, queue_stats) + 1899 num_queues_req * sizeof(struct per_queue_stats); 1900 1901 cur_query_entry = &bp->fw_stats_req-> 1902 query[first_queue_query_index + num_queues_req]; 1903 1904 for_each_vf(bp, i) { 1905 int j; 1906 struct bnx2x_virtf *vf = BP_VF(bp, i); 1907 1908 if (vf->state != VF_ENABLED) { 1909 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1910 "vf %d not enabled so no stats for it\n", 1911 vf->abs_vfid); 1912 continue; 1913 } 1914 1915 if (vf->malicious) { 1916 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1917 "vf %d malicious so no stats for it\n", 1918 vf->abs_vfid); 1919 continue; 1920 } 1921 1922 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1923 "add addresses for vf %d\n", vf->abs_vfid); 1924 for_each_vfq(vf, j) { 1925 struct bnx2x_vf_queue *rxq = vfq_get(vf, j); 1926 1927 dma_addr_t q_stats_addr = 1928 vf->fw_stat_map + j * vf->stats_stride; 1929 1930 /* collect stats fro active queues only */ 1931 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) == 1932 BNX2X_Q_LOGICAL_STATE_STOPPED) 1933 continue; 1934 1935 /* create stats query entry for this queue */ 1936 cur_query_entry->kind = STATS_TYPE_QUEUE; 1937 cur_query_entry->index = vfq_stat_id(vf, rxq); 1938 cur_query_entry->funcID = 1939 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid)); 1940 cur_query_entry->address.hi = 1941 cpu_to_le32(U64_HI(q_stats_addr)); 1942 cur_query_entry->address.lo = 1943 cpu_to_le32(U64_LO(q_stats_addr)); 1944 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1945 "added address %x %x for vf %d queue %d client %d\n", 1946 cur_query_entry->address.hi, 1947 cur_query_entry->address.lo, 1948 cur_query_entry->funcID, 1949 j, cur_query_entry->index); 1950 cur_query_entry++; 1951 cur_data_offset += sizeof(struct per_queue_stats); 1952 stats_count++; 1953 1954 /* all stats are coalesced to the leading queue */ 1955 if (vf->cfg_flags & VF_CFG_STATS_COALESCE) 1956 break; 1957 } 1958 } 1959 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count; 1960 } 1961 1962 /* VF API helpers */ 1963 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid, 1964 u8 enable) 1965 { 1966 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; 1967 u32 val = enable ? (abs_vfid | (1 << 6)) : 0; 1968 1969 REG_WR(bp, reg, val); 1970 } 1971 1972 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf) 1973 { 1974 int i; 1975 1976 for_each_vfq(vf, i) 1977 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 1978 vfq_qzone_id(vf, vfq_get(vf, i)), false); 1979 } 1980 1981 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf) 1982 { 1983 u32 val; 1984 1985 /* clear the VF configuration - pretend */ 1986 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 1987 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 1988 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | 1989 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK); 1990 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 1991 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1992 } 1993 1994 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf) 1995 { 1996 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF), 1997 BNX2X_VF_MAX_QUEUES); 1998 } 1999 2000 static 2001 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf, 2002 struct vf_pf_resc_request *req_resc) 2003 { 2004 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 2005 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 2006 2007 return ((req_resc->num_rxqs <= rxq_cnt) && 2008 (req_resc->num_txqs <= txq_cnt) && 2009 (req_resc->num_sbs <= vf_sb_count(vf)) && 2010 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) && 2011 (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf))); 2012 } 2013 2014 /* CORE VF API */ 2015 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf, 2016 struct vf_pf_resc_request *resc) 2017 { 2018 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) * 2019 BNX2X_CIDS_PER_VF; 2020 2021 union cdu_context *base_cxt = (union cdu_context *) 2022 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 2023 (base_vf_cid & (ILT_PAGE_CIDS-1)); 2024 int i; 2025 2026 /* if state is 'acquired' the VF was not released or FLR'd, in 2027 * this case the returned resources match the acquired already 2028 * acquired resources. Verify that the requested numbers do 2029 * not exceed the already acquired numbers. 2030 */ 2031 if (vf->state == VF_ACQUIRED) { 2032 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", 2033 vf->abs_vfid); 2034 2035 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2036 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n", 2037 vf->abs_vfid); 2038 return -EINVAL; 2039 } 2040 return 0; 2041 } 2042 2043 /* Otherwise vf state must be 'free' or 'reset' */ 2044 if (vf->state != VF_FREE && vf->state != VF_RESET) { 2045 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n", 2046 vf->abs_vfid, vf->state); 2047 return -EINVAL; 2048 } 2049 2050 /* static allocation: 2051 * the global maximum number are fixed per VF. Fail the request if 2052 * requested number exceed these globals 2053 */ 2054 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2055 DP(BNX2X_MSG_IOV, 2056 "cannot fulfill vf resource request. Placing maximal available values in response\n"); 2057 /* set the max resource in the vf */ 2058 return -ENOMEM; 2059 } 2060 2061 /* Set resources counters - 0 request means max available */ 2062 vf_sb_count(vf) = resc->num_sbs; 2063 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2064 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2065 2066 DP(BNX2X_MSG_IOV, 2067 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n", 2068 vf_sb_count(vf), vf_rxq_count(vf), 2069 vf_txq_count(vf), vf_mac_rules_cnt(vf), 2070 vf_vlan_rules_cnt(vf)); 2071 2072 /* Initialize the queues */ 2073 if (!vf->vfqs) { 2074 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); 2075 return -EINVAL; 2076 } 2077 2078 for_each_vfq(vf, i) { 2079 struct bnx2x_vf_queue *q = vfq_get(vf, i); 2080 2081 if (!q) { 2082 BNX2X_ERR("q number %d was not allocated\n", i); 2083 return -EINVAL; 2084 } 2085 2086 q->index = i; 2087 q->cxt = &((base_cxt + i)->eth); 2088 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i; 2089 2090 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", 2091 vf->abs_vfid, i, q->index, q->cid, q->cxt); 2092 2093 /* init SP objects */ 2094 bnx2x_vfq_init(bp, vf, q); 2095 } 2096 vf->state = VF_ACQUIRED; 2097 return 0; 2098 } 2099 2100 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map) 2101 { 2102 struct bnx2x_func_init_params func_init = {0}; 2103 int i; 2104 2105 /* the sb resources are initialized at this point, do the 2106 * FW/HW initializations 2107 */ 2108 for_each_vf_sb(vf, i) 2109 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true, 2110 vf_igu_sb(vf, i), vf_igu_sb(vf, i)); 2111 2112 /* Sanity checks */ 2113 if (vf->state != VF_ACQUIRED) { 2114 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", 2115 vf->abs_vfid, vf->state); 2116 return -EINVAL; 2117 } 2118 2119 /* let FLR complete ... */ 2120 msleep(100); 2121 2122 /* FLR cleanup epilogue */ 2123 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid)) 2124 return -EBUSY; 2125 2126 /* reset IGU VF statistics: MSIX */ 2127 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0); 2128 2129 /* function setup */ 2130 func_init.pf_id = BP_FUNC(bp); 2131 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid); 2132 bnx2x_func_init(bp, &func_init); 2133 2134 /* Enable the vf */ 2135 bnx2x_vf_enable_access(bp, vf->abs_vfid); 2136 bnx2x_vf_enable_traffic(bp, vf); 2137 2138 /* queue protection table */ 2139 for_each_vfq(vf, i) 2140 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2141 vfq_qzone_id(vf, vfq_get(vf, i)), true); 2142 2143 vf->state = VF_ENABLED; 2144 2145 /* update vf bulletin board */ 2146 bnx2x_post_vf_bulletin(bp, vf->index); 2147 2148 return 0; 2149 } 2150 2151 struct set_vf_state_cookie { 2152 struct bnx2x_virtf *vf; 2153 u8 state; 2154 }; 2155 2156 static void bnx2x_set_vf_state(void *cookie) 2157 { 2158 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie; 2159 2160 p->vf->state = p->state; 2161 } 2162 2163 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf) 2164 { 2165 int rc = 0, i; 2166 2167 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2168 2169 /* Close all queues */ 2170 for (i = 0; i < vf_rxq_count(vf); i++) { 2171 rc = bnx2x_vf_queue_teardown(bp, vf, i); 2172 if (rc) 2173 goto op_err; 2174 } 2175 2176 /* disable the interrupts */ 2177 DP(BNX2X_MSG_IOV, "disabling igu\n"); 2178 bnx2x_vf_igu_disable(bp, vf); 2179 2180 /* disable the VF */ 2181 DP(BNX2X_MSG_IOV, "clearing qtbl\n"); 2182 bnx2x_vf_clr_qtbl(bp, vf); 2183 2184 /* need to make sure there are no outstanding stats ramrods which may 2185 * cause the device to access the VF's stats buffer which it will free 2186 * as soon as we return from the close flow. 2187 */ 2188 { 2189 struct set_vf_state_cookie cookie; 2190 2191 cookie.vf = vf; 2192 cookie.state = VF_ACQUIRED; 2193 rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie); 2194 if (rc) 2195 goto op_err; 2196 } 2197 2198 DP(BNX2X_MSG_IOV, "set state to acquired\n"); 2199 2200 return 0; 2201 op_err: 2202 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc); 2203 return rc; 2204 } 2205 2206 /* VF release can be called either: 1. The VF was acquired but 2207 * not enabled 2. the vf was enabled or in the process of being 2208 * enabled 2209 */ 2210 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf) 2211 { 2212 int rc; 2213 2214 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, 2215 vf->state == VF_FREE ? "Free" : 2216 vf->state == VF_ACQUIRED ? "Acquired" : 2217 vf->state == VF_ENABLED ? "Enabled" : 2218 vf->state == VF_RESET ? "Reset" : 2219 "Unknown"); 2220 2221 switch (vf->state) { 2222 case VF_ENABLED: 2223 rc = bnx2x_vf_close(bp, vf); 2224 if (rc) 2225 goto op_err; 2226 /* Fallthrough to release resources */ 2227 case VF_ACQUIRED: 2228 DP(BNX2X_MSG_IOV, "about to free resources\n"); 2229 bnx2x_vf_free_resc(bp, vf); 2230 break; 2231 2232 case VF_FREE: 2233 case VF_RESET: 2234 default: 2235 break; 2236 } 2237 return 0; 2238 op_err: 2239 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc); 2240 return rc; 2241 } 2242 2243 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2244 struct bnx2x_config_rss_params *rss) 2245 { 2246 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2247 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags); 2248 return bnx2x_config_rss(bp, rss); 2249 } 2250 2251 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2252 struct vfpf_tpa_tlv *tlv, 2253 struct bnx2x_queue_update_tpa_params *params) 2254 { 2255 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr; 2256 struct bnx2x_queue_state_params qstate; 2257 int qid, rc = 0; 2258 2259 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2260 2261 /* Set ramrod params */ 2262 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 2263 memcpy(&qstate.params.update_tpa, params, 2264 sizeof(struct bnx2x_queue_update_tpa_params)); 2265 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA; 2266 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 2267 2268 for (qid = 0; qid < vf_rxq_count(vf); qid++) { 2269 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 2270 qstate.params.update_tpa.sge_map = sge_addr[qid]; 2271 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", 2272 vf->abs_vfid, qid, U64_HI(sge_addr[qid]), 2273 U64_LO(sge_addr[qid])); 2274 rc = bnx2x_queue_state_change(bp, &qstate); 2275 if (rc) { 2276 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n", 2277 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]), 2278 vf->abs_vfid, qid); 2279 return rc; 2280 } 2281 } 2282 2283 return rc; 2284 } 2285 2286 /* VF release ~ VF close + VF release-resources 2287 * Release is the ultimate SW shutdown and is called whenever an 2288 * irrecoverable error is encountered. 2289 */ 2290 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf) 2291 { 2292 int rc; 2293 2294 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); 2295 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2296 2297 rc = bnx2x_vf_free(bp, vf); 2298 if (rc) 2299 WARN(rc, 2300 "VF[%d] Failed to allocate resources for release op- rc=%d\n", 2301 vf->abs_vfid, rc); 2302 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2303 return rc; 2304 } 2305 2306 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2307 enum channel_tlvs tlv) 2308 { 2309 /* we don't lock the channel for unsupported tlvs */ 2310 if (!bnx2x_tlv_supported(tlv)) { 2311 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n"); 2312 return; 2313 } 2314 2315 /* lock the channel */ 2316 mutex_lock(&vf->op_mutex); 2317 2318 /* record the locking op */ 2319 vf->op_current = tlv; 2320 2321 /* log the lock */ 2322 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", 2323 vf->abs_vfid, tlv); 2324 } 2325 2326 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2327 enum channel_tlvs expected_tlv) 2328 { 2329 enum channel_tlvs current_tlv; 2330 2331 if (!vf) { 2332 BNX2X_ERR("VF was %p\n", vf); 2333 return; 2334 } 2335 2336 current_tlv = vf->op_current; 2337 2338 /* we don't unlock the channel for unsupported tlvs */ 2339 if (!bnx2x_tlv_supported(expected_tlv)) 2340 return; 2341 2342 WARN(expected_tlv != vf->op_current, 2343 "lock mismatch: expected %d found %d", expected_tlv, 2344 vf->op_current); 2345 2346 /* record the locking op */ 2347 vf->op_current = CHANNEL_TLV_NONE; 2348 2349 /* lock the channel */ 2350 mutex_unlock(&vf->op_mutex); 2351 2352 /* log the unlock */ 2353 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", 2354 vf->abs_vfid, current_tlv); 2355 } 2356 2357 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable) 2358 { 2359 struct bnx2x_queue_state_params q_params; 2360 u32 prev_flags; 2361 int i, rc; 2362 2363 /* Verify changes are needed and record current Tx switching state */ 2364 prev_flags = bp->flags; 2365 if (enable) 2366 bp->flags |= TX_SWITCHING; 2367 else 2368 bp->flags &= ~TX_SWITCHING; 2369 if (prev_flags == bp->flags) 2370 return 0; 2371 2372 /* Verify state enables the sending of queue ramrods */ 2373 if ((bp->state != BNX2X_STATE_OPEN) || 2374 (bnx2x_get_q_logical_state(bp, 2375 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) != 2376 BNX2X_Q_LOGICAL_STATE_ACTIVE)) 2377 return 0; 2378 2379 /* send q. update ramrod to configure Tx switching */ 2380 memset(&q_params, 0, sizeof(q_params)); 2381 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2382 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2383 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 2384 &q_params.params.update.update_flags); 2385 if (enable) 2386 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2387 &q_params.params.update.update_flags); 2388 else 2389 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2390 &q_params.params.update.update_flags); 2391 2392 /* send the ramrod on all the queues of the PF */ 2393 for_each_eth_queue(bp, i) { 2394 struct bnx2x_fastpath *fp = &bp->fp[i]; 2395 2396 /* Set the appropriate Queue object */ 2397 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 2398 2399 /* Update the Queue state */ 2400 rc = bnx2x_queue_state_change(bp, &q_params); 2401 if (rc) { 2402 BNX2X_ERR("Failed to configure Tx switching\n"); 2403 return rc; 2404 } 2405 } 2406 2407 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled"); 2408 return 0; 2409 } 2410 2411 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) 2412 { 2413 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); 2414 2415 if (!IS_SRIOV(bp)) { 2416 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); 2417 return -EINVAL; 2418 } 2419 2420 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", 2421 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2422 2423 /* HW channel is only operational when PF is up */ 2424 if (bp->state != BNX2X_STATE_OPEN) { 2425 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n"); 2426 return -EINVAL; 2427 } 2428 2429 /* we are always bound by the total_vfs in the configuration space */ 2430 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { 2431 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", 2432 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2433 num_vfs_param = BNX2X_NR_VIRTFN(bp); 2434 } 2435 2436 bp->requested_nr_virtfn = num_vfs_param; 2437 if (num_vfs_param == 0) { 2438 bnx2x_set_pf_tx_switching(bp, false); 2439 bnx2x_disable_sriov(bp); 2440 return 0; 2441 } else { 2442 return bnx2x_enable_sriov(bp); 2443 } 2444 } 2445 2446 #define IGU_ENTRY_SIZE 4 2447 2448 int bnx2x_enable_sriov(struct bnx2x *bp) 2449 { 2450 int rc = 0, req_vfs = bp->requested_nr_virtfn; 2451 int vf_idx, sb_idx, vfq_idx, qcount, first_vf; 2452 u32 igu_entry, address; 2453 u16 num_vf_queues; 2454 2455 if (req_vfs == 0) 2456 return 0; 2457 2458 first_vf = bp->vfdb->sriov.first_vf_in_pf; 2459 2460 /* statically distribute vf sb pool between VFs */ 2461 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES, 2462 BP_VFDB(bp)->vf_sbs_pool / req_vfs); 2463 2464 /* zero previous values learned from igu cam */ 2465 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) { 2466 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2467 2468 vf->sb_count = 0; 2469 vf_sb_count(BP_VF(bp, vf_idx)) = 0; 2470 } 2471 bp->vfdb->vf_sbs_pool = 0; 2472 2473 /* prepare IGU cam */ 2474 sb_idx = BP_VFDB(bp)->first_vf_igu_entry; 2475 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE; 2476 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2477 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) { 2478 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT | 2479 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT | 2480 IGU_REG_MAPPING_MEMORY_VALID; 2481 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", 2482 sb_idx, vf_idx); 2483 REG_WR(bp, address, igu_entry); 2484 sb_idx++; 2485 address += IGU_ENTRY_SIZE; 2486 } 2487 } 2488 2489 /* Reinitialize vf database according to igu cam */ 2490 bnx2x_get_vf_igu_cam_info(bp); 2491 2492 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", 2493 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues); 2494 2495 qcount = 0; 2496 for_each_vf(bp, vf_idx) { 2497 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2498 2499 /* set local queue arrays */ 2500 vf->vfqs = &bp->vfdb->vfqs[qcount]; 2501 qcount += vf_sb_count(vf); 2502 bnx2x_iov_static_resc(bp, vf); 2503 } 2504 2505 /* prepare msix vectors in VF configuration space - the value in the 2506 * PCI configuration space should be the index of the last entry, 2507 * namely one less than the actual size of the table 2508 */ 2509 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2510 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); 2511 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, 2512 num_vf_queues - 1); 2513 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n", 2514 vf_idx, num_vf_queues - 1); 2515 } 2516 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2517 2518 /* enable sriov. This will probe all the VFs, and consequentially cause 2519 * the "acquire" messages to appear on the VF PF channel. 2520 */ 2521 DP(BNX2X_MSG_IOV, "about to call enable sriov\n"); 2522 bnx2x_disable_sriov(bp); 2523 2524 rc = bnx2x_set_pf_tx_switching(bp, true); 2525 if (rc) 2526 return rc; 2527 2528 rc = pci_enable_sriov(bp->pdev, req_vfs); 2529 if (rc) { 2530 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); 2531 return rc; 2532 } 2533 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); 2534 return req_vfs; 2535 } 2536 2537 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) 2538 { 2539 int vfidx; 2540 struct pf_vf_bulletin_content *bulletin; 2541 2542 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); 2543 for_each_vf(bp, vfidx) { 2544 bulletin = BP_VF_BULLETIN(bp, vfidx); 2545 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2546 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0, 2547 htons(ETH_P_8021Q)); 2548 } 2549 } 2550 2551 void bnx2x_disable_sriov(struct bnx2x *bp) 2552 { 2553 if (pci_vfs_assigned(bp->pdev)) { 2554 DP(BNX2X_MSG_IOV, 2555 "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2556 return; 2557 } 2558 2559 pci_disable_sriov(bp->pdev); 2560 } 2561 2562 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 2563 struct bnx2x_virtf **vf, 2564 struct pf_vf_bulletin_content **bulletin, 2565 bool test_queue) 2566 { 2567 if (bp->state != BNX2X_STATE_OPEN) { 2568 BNX2X_ERR("PF is down - can't utilize iov-related functionality\n"); 2569 return -EINVAL; 2570 } 2571 2572 if (!IS_SRIOV(bp)) { 2573 BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n"); 2574 return -EINVAL; 2575 } 2576 2577 if (vfidx >= BNX2X_NR_VIRTFN(bp)) { 2578 BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n", 2579 vfidx, BNX2X_NR_VIRTFN(bp)); 2580 return -EINVAL; 2581 } 2582 2583 /* init members */ 2584 *vf = BP_VF(bp, vfidx); 2585 *bulletin = BP_VF_BULLETIN(bp, vfidx); 2586 2587 if (!*vf) { 2588 BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx); 2589 return -EINVAL; 2590 } 2591 2592 if (test_queue && !(*vf)->vfqs) { 2593 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n", 2594 vfidx); 2595 return -EINVAL; 2596 } 2597 2598 if (!*bulletin) { 2599 BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n", 2600 vfidx); 2601 return -EINVAL; 2602 } 2603 2604 return 0; 2605 } 2606 2607 int bnx2x_get_vf_config(struct net_device *dev, int vfidx, 2608 struct ifla_vf_info *ivi) 2609 { 2610 struct bnx2x *bp = netdev_priv(dev); 2611 struct bnx2x_virtf *vf = NULL; 2612 struct pf_vf_bulletin_content *bulletin = NULL; 2613 struct bnx2x_vlan_mac_obj *mac_obj; 2614 struct bnx2x_vlan_mac_obj *vlan_obj; 2615 int rc; 2616 2617 /* sanity and init */ 2618 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2619 if (rc) 2620 return rc; 2621 2622 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2623 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2624 if (!mac_obj || !vlan_obj) { 2625 BNX2X_ERR("VF partially initialized\n"); 2626 return -EINVAL; 2627 } 2628 2629 ivi->vf = vfidx; 2630 ivi->qos = 0; 2631 ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */ 2632 ivi->min_tx_rate = 0; 2633 ivi->spoofchk = 1; /*always enabled */ 2634 if (vf->state == VF_ENABLED) { 2635 /* mac and vlan are in vlan_mac objects */ 2636 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) { 2637 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, 2638 0, ETH_ALEN); 2639 vlan_obj->get_n_elements(bp, vlan_obj, 1, 2640 (u8 *)&ivi->vlan, 0, 2641 VLAN_HLEN); 2642 } 2643 } else { 2644 mutex_lock(&bp->vfdb->bulletin_mutex); 2645 /* mac */ 2646 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) 2647 /* mac configured by ndo so its in bulletin board */ 2648 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); 2649 else 2650 /* function has not been loaded yet. Show mac as 0s */ 2651 eth_zero_addr(ivi->mac); 2652 2653 /* vlan */ 2654 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2655 /* vlan configured by ndo so its in bulletin board */ 2656 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); 2657 else 2658 /* function has not been loaded yet. Show vlans as 0s */ 2659 memset(&ivi->vlan, 0, VLAN_HLEN); 2660 2661 mutex_unlock(&bp->vfdb->bulletin_mutex); 2662 } 2663 2664 return 0; 2665 } 2666 2667 /* New mac for VF. Consider these cases: 2668 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and 2669 * supply at acquire. 2670 * 2. VF has already been acquired but has not yet initialized - store in local 2671 * bulletin board. mac will be posted on VF bulletin board after VF init. VF 2672 * will configure this mac when it is ready. 2673 * 3. VF has already initialized but has not yet setup a queue - post the new 2674 * mac on VF's bulletin board right now. VF will configure this mac when it 2675 * is ready. 2676 * 4. VF has already set a queue - delete any macs already configured for this 2677 * queue and manually config the new mac. 2678 * In any event, once this function has been called refuse any attempts by the 2679 * VF to configure any mac for itself except for this mac. In case of a race 2680 * where the VF fails to see the new post on its bulletin board before sending a 2681 * mac configuration request, the PF will simply fail the request and VF can try 2682 * again after consulting its bulletin board. 2683 */ 2684 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) 2685 { 2686 struct bnx2x *bp = netdev_priv(dev); 2687 int rc, q_logical_state; 2688 struct bnx2x_virtf *vf = NULL; 2689 struct pf_vf_bulletin_content *bulletin = NULL; 2690 2691 if (!is_valid_ether_addr(mac)) { 2692 BNX2X_ERR("mac address invalid\n"); 2693 return -EINVAL; 2694 } 2695 2696 /* sanity and init */ 2697 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2698 if (rc) 2699 return rc; 2700 2701 mutex_lock(&bp->vfdb->bulletin_mutex); 2702 2703 /* update PF's copy of the VF's bulletin. Will no longer accept mac 2704 * configuration requests from vf unless match this mac 2705 */ 2706 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID; 2707 memcpy(bulletin->mac, mac, ETH_ALEN); 2708 2709 /* Post update on VF's bulletin board */ 2710 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2711 2712 /* release lock before checking return code */ 2713 mutex_unlock(&bp->vfdb->bulletin_mutex); 2714 2715 if (rc) { 2716 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2717 return rc; 2718 } 2719 2720 q_logical_state = 2721 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)); 2722 if (vf->state == VF_ENABLED && 2723 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { 2724 /* configure the mac in device on this vf's queue */ 2725 unsigned long ramrod_flags = 0; 2726 struct bnx2x_vlan_mac_obj *mac_obj; 2727 2728 /* User should be able to see failure reason in system logs */ 2729 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2730 return -EINVAL; 2731 2732 /* must lock vfpf channel to protect against vf flows */ 2733 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2734 2735 /* remove existing eth macs */ 2736 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2737 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true); 2738 if (rc) { 2739 BNX2X_ERR("failed to delete eth macs\n"); 2740 rc = -EINVAL; 2741 goto out; 2742 } 2743 2744 /* remove existing uc list macs */ 2745 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true); 2746 if (rc) { 2747 BNX2X_ERR("failed to delete uc_list macs\n"); 2748 rc = -EINVAL; 2749 goto out; 2750 } 2751 2752 /* configure the new mac to device */ 2753 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2754 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, 2755 BNX2X_ETH_MAC, &ramrod_flags); 2756 2757 out: 2758 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2759 } 2760 2761 return rc; 2762 } 2763 2764 static void bnx2x_set_vf_vlan_acceptance(struct bnx2x *bp, 2765 struct bnx2x_virtf *vf, bool accept) 2766 { 2767 struct bnx2x_rx_mode_ramrod_params rx_ramrod; 2768 unsigned long accept_flags; 2769 2770 /* need to remove/add the VF's accept_any_vlan bit */ 2771 accept_flags = bnx2x_leading_vfq(vf, accept_flags); 2772 if (accept) 2773 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2774 else 2775 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2776 2777 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf, 2778 accept_flags); 2779 bnx2x_leading_vfq(vf, accept_flags) = accept_flags; 2780 bnx2x_config_rx_mode(bp, &rx_ramrod); 2781 } 2782 2783 static int bnx2x_set_vf_vlan_filter(struct bnx2x *bp, struct bnx2x_virtf *vf, 2784 u16 vlan, bool add) 2785 { 2786 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 2787 unsigned long ramrod_flags = 0; 2788 int rc = 0; 2789 2790 /* configure the new vlan to device */ 2791 memset(&ramrod_param, 0, sizeof(ramrod_param)); 2792 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2793 ramrod_param.vlan_mac_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2794 ramrod_param.ramrod_flags = ramrod_flags; 2795 ramrod_param.user_req.u.vlan.vlan = vlan; 2796 ramrod_param.user_req.cmd = add ? BNX2X_VLAN_MAC_ADD 2797 : BNX2X_VLAN_MAC_DEL; 2798 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 2799 if (rc) { 2800 BNX2X_ERR("failed to configure vlan\n"); 2801 return -EINVAL; 2802 } 2803 2804 return 0; 2805 } 2806 2807 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos, 2808 __be16 vlan_proto) 2809 { 2810 struct pf_vf_bulletin_content *bulletin = NULL; 2811 struct bnx2x *bp = netdev_priv(dev); 2812 struct bnx2x_vlan_mac_obj *vlan_obj; 2813 unsigned long vlan_mac_flags = 0; 2814 unsigned long ramrod_flags = 0; 2815 struct bnx2x_virtf *vf = NULL; 2816 int i, rc; 2817 2818 if (vlan > 4095) { 2819 BNX2X_ERR("illegal vlan value %d\n", vlan); 2820 return -EINVAL; 2821 } 2822 2823 if (vlan_proto != htons(ETH_P_8021Q)) 2824 return -EPROTONOSUPPORT; 2825 2826 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", 2827 vfidx, vlan, 0); 2828 2829 /* sanity and init */ 2830 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2831 if (rc) 2832 return rc; 2833 2834 /* update PF's copy of the VF's bulletin. No point in posting the vlan 2835 * to the VF since it doesn't have anything to do with it. But it useful 2836 * to store it here in case the VF is not up yet and we can only 2837 * configure the vlan later when it does. Treat vlan id 0 as remove the 2838 * Host tag. 2839 */ 2840 mutex_lock(&bp->vfdb->bulletin_mutex); 2841 2842 if (vlan > 0) 2843 bulletin->valid_bitmap |= 1 << VLAN_VALID; 2844 else 2845 bulletin->valid_bitmap &= ~(1 << VLAN_VALID); 2846 bulletin->vlan = vlan; 2847 2848 /* Post update on VF's bulletin board */ 2849 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2850 if (rc) 2851 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2852 mutex_unlock(&bp->vfdb->bulletin_mutex); 2853 2854 /* is vf initialized and queue set up? */ 2855 if (vf->state != VF_ENABLED || 2856 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) != 2857 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2858 return rc; 2859 2860 /* User should be able to see error in system logs */ 2861 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2862 return -EINVAL; 2863 2864 /* must lock vfpf channel to protect against vf flows */ 2865 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2866 2867 /* remove existing vlans */ 2868 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2869 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2870 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, 2871 &ramrod_flags); 2872 if (rc) { 2873 BNX2X_ERR("failed to delete vlans\n"); 2874 rc = -EINVAL; 2875 goto out; 2876 } 2877 2878 /* clear accept_any_vlan when HV forces vlan, otherwise 2879 * according to VF capabilities 2880 */ 2881 if (vlan || !(vf->cfg_flags & VF_CFG_VLAN_FILTER)) 2882 bnx2x_set_vf_vlan_acceptance(bp, vf, !vlan); 2883 2884 rc = bnx2x_set_vf_vlan_filter(bp, vf, vlan, true); 2885 if (rc) 2886 goto out; 2887 2888 /* send queue update ramrods to configure default vlan and 2889 * silent vlan removal 2890 */ 2891 for_each_vfq(vf, i) { 2892 struct bnx2x_queue_state_params q_params = {NULL}; 2893 struct bnx2x_queue_update_params *update_params; 2894 2895 q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj); 2896 2897 /* validate the Q is UP */ 2898 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) != 2899 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2900 continue; 2901 2902 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2903 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2904 update_params = &q_params.params.update; 2905 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 2906 &update_params->update_flags); 2907 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 2908 &update_params->update_flags); 2909 if (vlan == 0) { 2910 /* if vlan is 0 then we want to leave the VF traffic 2911 * untagged, and leave the incoming traffic untouched 2912 * (i.e. do not remove any vlan tags). 2913 */ 2914 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2915 &update_params->update_flags); 2916 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2917 &update_params->update_flags); 2918 } else { 2919 /* configure default vlan to vf queue and set silent 2920 * vlan removal (the vf remains unaware of this vlan). 2921 */ 2922 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2923 &update_params->update_flags); 2924 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2925 &update_params->update_flags); 2926 update_params->def_vlan = vlan; 2927 update_params->silent_removal_value = 2928 vlan & VLAN_VID_MASK; 2929 update_params->silent_removal_mask = VLAN_VID_MASK; 2930 } 2931 2932 /* Update the Queue state */ 2933 rc = bnx2x_queue_state_change(bp, &q_params); 2934 if (rc) { 2935 BNX2X_ERR("Failed to configure default VLAN queue %d\n", 2936 i); 2937 goto out; 2938 } 2939 } 2940 out: 2941 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2942 2943 if (rc) 2944 DP(BNX2X_MSG_IOV, 2945 "updated VF[%d] vlan configuration (vlan = %d)\n", 2946 vfidx, vlan); 2947 2948 return rc; 2949 } 2950 2951 /* crc is the first field in the bulletin board. Compute the crc over the 2952 * entire bulletin board excluding the crc field itself. Use the length field 2953 * as the Bulletin Board was posted by a PF with possibly a different version 2954 * from the vf which will sample it. Therefore, the length is computed by the 2955 * PF and then used blindly by the VF. 2956 */ 2957 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin) 2958 { 2959 return crc32(BULLETIN_CRC_SEED, 2960 ((u8 *)bulletin) + sizeof(bulletin->crc), 2961 bulletin->length - sizeof(bulletin->crc)); 2962 } 2963 2964 /* Check for new posts on the bulletin board */ 2965 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) 2966 { 2967 struct pf_vf_bulletin_content *bulletin; 2968 int attempts; 2969 2970 /* sampling structure in mid post may result with corrupted data 2971 * validate crc to ensure coherency. 2972 */ 2973 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) { 2974 u32 crc; 2975 2976 /* sample the bulletin board */ 2977 memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin, 2978 sizeof(union pf_vf_bulletin)); 2979 2980 crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content); 2981 2982 if (bp->shadow_bulletin.content.crc == crc) 2983 break; 2984 2985 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n", 2986 bp->shadow_bulletin.content.crc, crc); 2987 } 2988 2989 if (attempts >= BULLETIN_ATTEMPTS) { 2990 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n", 2991 attempts); 2992 return PFVF_BULLETIN_CRC_ERR; 2993 } 2994 bulletin = &bp->shadow_bulletin.content; 2995 2996 /* bulletin board hasn't changed since last sample */ 2997 if (bp->old_bulletin.version == bulletin->version) 2998 return PFVF_BULLETIN_UNCHANGED; 2999 3000 /* the mac address in bulletin board is valid and is new */ 3001 if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID && 3002 !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) { 3003 /* update new mac to net device */ 3004 memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN); 3005 } 3006 3007 if (bulletin->valid_bitmap & (1 << LINK_VALID)) { 3008 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n", 3009 bulletin->link_speed, bulletin->link_flags); 3010 3011 bp->vf_link_vars.line_speed = bulletin->link_speed; 3012 bp->vf_link_vars.link_report_flags = 0; 3013 /* Link is down */ 3014 if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN) 3015 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, 3016 &bp->vf_link_vars.link_report_flags); 3017 /* Full DUPLEX */ 3018 if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX) 3019 __set_bit(BNX2X_LINK_REPORT_FD, 3020 &bp->vf_link_vars.link_report_flags); 3021 /* Rx Flow Control is ON */ 3022 if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON) 3023 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, 3024 &bp->vf_link_vars.link_report_flags); 3025 /* Tx Flow Control is ON */ 3026 if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON) 3027 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, 3028 &bp->vf_link_vars.link_report_flags); 3029 __bnx2x_link_report(bp); 3030 } 3031 3032 /* copy new bulletin board to bp */ 3033 memcpy(&bp->old_bulletin, bulletin, 3034 sizeof(struct pf_vf_bulletin_content)); 3035 3036 return PFVF_BULLETIN_UPDATED; 3037 } 3038 3039 void bnx2x_timer_sriov(struct bnx2x *bp) 3040 { 3041 bnx2x_sample_bulletin(bp); 3042 3043 /* if channel is down we need to self destruct */ 3044 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) 3045 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 3046 BNX2X_MSG_IOV); 3047 } 3048 3049 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) 3050 { 3051 /* vf doorbells are embedded within the regview */ 3052 return bp->regview + PXP_VF_ADDR_DB_START; 3053 } 3054 3055 void bnx2x_vf_pci_dealloc(struct bnx2x *bp) 3056 { 3057 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, 3058 sizeof(struct bnx2x_vf_mbx_msg)); 3059 BNX2X_PCI_FREE(bp->pf2vf_bulletin, bp->pf2vf_bulletin_mapping, 3060 sizeof(union pf_vf_bulletin)); 3061 } 3062 3063 int bnx2x_vf_pci_alloc(struct bnx2x *bp) 3064 { 3065 mutex_init(&bp->vf2pf_mutex); 3066 3067 /* allocate vf2pf mailbox for vf to pf channel */ 3068 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping, 3069 sizeof(struct bnx2x_vf_mbx_msg)); 3070 if (!bp->vf2pf_mbox) 3071 goto alloc_mem_err; 3072 3073 /* allocate pf 2 vf bulletin board */ 3074 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping, 3075 sizeof(union pf_vf_bulletin)); 3076 if (!bp->pf2vf_bulletin) 3077 goto alloc_mem_err; 3078 3079 bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true); 3080 3081 return 0; 3082 3083 alloc_mem_err: 3084 bnx2x_vf_pci_dealloc(bp); 3085 return -ENOMEM; 3086 } 3087 3088 void bnx2x_iov_channel_down(struct bnx2x *bp) 3089 { 3090 int vf_idx; 3091 struct pf_vf_bulletin_content *bulletin; 3092 3093 if (!IS_SRIOV(bp)) 3094 return; 3095 3096 for_each_vf(bp, vf_idx) { 3097 /* locate this VFs bulletin board and update the channel down 3098 * bit 3099 */ 3100 bulletin = BP_VF_BULLETIN(bp, vf_idx); 3101 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN; 3102 3103 /* update vf bulletin board */ 3104 bnx2x_post_vf_bulletin(bp, vf_idx); 3105 } 3106 } 3107 3108 void bnx2x_iov_task(struct work_struct *work) 3109 { 3110 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work); 3111 3112 if (!netif_running(bp->dev)) 3113 return; 3114 3115 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR, 3116 &bp->iov_task_state)) 3117 bnx2x_vf_handle_flr_event(bp); 3118 3119 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG, 3120 &bp->iov_task_state)) 3121 bnx2x_vf_mbx(bp); 3122 } 3123 3124 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) 3125 { 3126 smp_mb__before_atomic(); 3127 set_bit(flag, &bp->iov_task_state); 3128 smp_mb__after_atomic(); 3129 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); 3130 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0); 3131 } 3132