1 /* bnx2x_sriov.c: Broadcom Everest network driver. 2 * 3 * Copyright 2009-2013 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Shmulik Ravid <shmulikr@broadcom.com> 17 * Ariel Elior <ariele@broadcom.com> 18 * 19 */ 20 #include "bnx2x.h" 21 #include "bnx2x_init.h" 22 #include "bnx2x_cmn.h" 23 #include "bnx2x_sp.h" 24 #include <linux/crc32.h> 25 #include <linux/if_vlan.h> 26 27 /* General service functions */ 28 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 29 u16 pf_id) 30 { 31 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 32 pf_id); 33 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 34 pf_id); 35 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 36 pf_id); 37 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 38 pf_id); 39 } 40 41 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 42 u8 enable) 43 { 44 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 45 enable); 46 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 47 enable); 48 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 49 enable); 50 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 51 enable); 52 } 53 54 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 55 { 56 int idx; 57 58 for_each_vf(bp, idx) 59 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid) 60 break; 61 return idx; 62 } 63 64 static 65 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 66 { 67 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid); 68 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL; 69 } 70 71 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf, 72 u8 igu_sb_id, u8 segment, u16 index, u8 op, 73 u8 update) 74 { 75 /* acking a VF sb through the PF - use the GRC */ 76 u32 ctl; 77 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 78 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 79 u32 func_encode = vf->abs_vfid; 80 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id; 81 struct igu_regular cmd_data = {0}; 82 83 cmd_data.sb_id_and_flags = 84 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 85 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 86 (update << IGU_REGULAR_BUPDATE_SHIFT) | 87 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 88 89 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 90 func_encode << IGU_CTRL_REG_FID_SHIFT | 91 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 92 93 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 94 cmd_data.sb_id_and_flags, igu_addr_data); 95 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); 96 mmiowb(); 97 barrier(); 98 99 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 100 ctl, igu_addr_ctl); 101 REG_WR(bp, igu_addr_ctl, ctl); 102 mmiowb(); 103 barrier(); 104 } 105 106 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp, 107 struct bnx2x_virtf *vf, 108 bool print_err) 109 { 110 if (!bnx2x_leading_vfq(vf, sp_initialized)) { 111 if (print_err) 112 BNX2X_ERR("Slowpath objects not yet initialized!\n"); 113 else 114 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); 115 return false; 116 } 117 return true; 118 } 119 120 /* VFOP operations states */ 121 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf, 122 struct bnx2x_queue_init_params *init_params, 123 struct bnx2x_queue_setup_params *setup_params, 124 u16 q_idx, u16 sb_idx) 125 { 126 DP(BNX2X_MSG_IOV, 127 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", 128 vf->abs_vfid, 129 q_idx, 130 sb_idx, 131 init_params->tx.sb_cq_index, 132 init_params->tx.hc_rate, 133 setup_params->flags, 134 setup_params->txq_params.traffic_type); 135 } 136 137 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf, 138 struct bnx2x_queue_init_params *init_params, 139 struct bnx2x_queue_setup_params *setup_params, 140 u16 q_idx, u16 sb_idx) 141 { 142 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params; 143 144 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" 145 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n", 146 vf->abs_vfid, 147 q_idx, 148 sb_idx, 149 init_params->rx.sb_cq_index, 150 init_params->rx.hc_rate, 151 setup_params->gen_params.mtu, 152 rxq_params->buf_sz, 153 rxq_params->sge_buf_sz, 154 rxq_params->max_sges_pkt, 155 rxq_params->tpa_agg_sz, 156 setup_params->flags, 157 rxq_params->drop_flags, 158 rxq_params->cache_line_log); 159 } 160 161 void bnx2x_vfop_qctor_prep(struct bnx2x *bp, 162 struct bnx2x_virtf *vf, 163 struct bnx2x_vf_queue *q, 164 struct bnx2x_vf_queue_construct_params *p, 165 unsigned long q_type) 166 { 167 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init; 168 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup; 169 170 /* INIT */ 171 172 /* Enable host coalescing in the transition to INIT state */ 173 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags)) 174 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags); 175 176 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags)) 177 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags); 178 179 /* FW SB ID */ 180 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 181 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 182 183 /* context */ 184 init_p->cxts[0] = q->cxt; 185 186 /* SETUP */ 187 188 /* Setup-op general parameters */ 189 setup_p->gen_params.spcl_id = vf->sp_cl_id; 190 setup_p->gen_params.stat_id = vfq_stat_id(vf, q); 191 192 /* Setup-op pause params: 193 * Nothing to do, the pause thresholds are set by default to 0 which 194 * effectively turns off the feature for this queue. We don't want 195 * one queue (VF) to interfering with another queue (another VF) 196 */ 197 if (vf->cfg_flags & VF_CFG_FW_FC) 198 BNX2X_ERR("No support for pause to VFs (abs_vfid: %d)\n", 199 vf->abs_vfid); 200 /* Setup-op flags: 201 * collect statistics, zero statistics, local-switching, security, 202 * OV for Flex10, RSS and MCAST for leading 203 */ 204 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags)) 205 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags); 206 207 /* for VFs, enable tx switching, bd coherency, and mac address 208 * anti-spoofing 209 */ 210 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags); 211 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags); 212 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags); 213 214 /* Setup-op rx parameters */ 215 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) { 216 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params; 217 218 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q); 219 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx); 220 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid); 221 222 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags)) 223 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES; 224 } 225 226 /* Setup-op tx parameters */ 227 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) { 228 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss; 229 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 230 } 231 } 232 233 static int bnx2x_vf_queue_create(struct bnx2x *bp, 234 struct bnx2x_virtf *vf, int qid, 235 struct bnx2x_vf_queue_construct_params *qctor) 236 { 237 struct bnx2x_queue_state_params *q_params; 238 int rc = 0; 239 240 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 241 242 /* Prepare ramrod information */ 243 q_params = &qctor->qstate; 244 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj); 245 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags); 246 247 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) == 248 BNX2X_Q_LOGICAL_STATE_ACTIVE) { 249 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); 250 goto out; 251 } 252 253 /* Run Queue 'construction' ramrods */ 254 q_params->cmd = BNX2X_Q_CMD_INIT; 255 rc = bnx2x_queue_state_change(bp, q_params); 256 if (rc) 257 goto out; 258 259 memcpy(&q_params->params.setup, &qctor->prep_qsetup, 260 sizeof(struct bnx2x_queue_setup_params)); 261 q_params->cmd = BNX2X_Q_CMD_SETUP; 262 rc = bnx2x_queue_state_change(bp, q_params); 263 if (rc) 264 goto out; 265 266 /* enable interrupts */ 267 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)), 268 USTORM_ID, 0, IGU_INT_ENABLE, 0); 269 out: 270 return rc; 271 } 272 273 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf, 274 int qid) 275 { 276 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT, 277 BNX2X_Q_CMD_TERMINATE, 278 BNX2X_Q_CMD_CFC_DEL}; 279 struct bnx2x_queue_state_params q_params; 280 int rc, i; 281 282 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 283 284 /* Prepare ramrod information */ 285 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params)); 286 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 287 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 288 289 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) == 290 BNX2X_Q_LOGICAL_STATE_STOPPED) { 291 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); 292 goto out; 293 } 294 295 /* Run Queue 'destruction' ramrods */ 296 for (i = 0; i < ARRAY_SIZE(cmds); i++) { 297 q_params.cmd = cmds[i]; 298 rc = bnx2x_queue_state_change(bp, &q_params); 299 if (rc) { 300 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]); 301 return rc; 302 } 303 } 304 out: 305 /* Clean Context */ 306 if (bnx2x_vfq(vf, qid, cxt)) { 307 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0; 308 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0; 309 } 310 311 return 0; 312 } 313 314 static void 315 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid) 316 { 317 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 318 if (vf) { 319 /* the first igu entry belonging to VFs of this PF */ 320 if (!BP_VFDB(bp)->first_vf_igu_entry) 321 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id; 322 323 /* the first igu entry belonging to this VF */ 324 if (!vf_sb_count(vf)) 325 vf->igu_base_id = igu_sb_id; 326 327 ++vf_sb_count(vf); 328 ++vf->sb_count; 329 } 330 BP_VFDB(bp)->vf_sbs_pool++; 331 } 332 333 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp, 334 struct bnx2x_vlan_mac_obj *obj, 335 atomic_t *counter) 336 { 337 struct list_head *pos; 338 int read_lock; 339 int cnt = 0; 340 341 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj); 342 if (read_lock) 343 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); 344 345 list_for_each(pos, &obj->head) 346 cnt++; 347 348 if (!read_lock) 349 bnx2x_vlan_mac_h_read_unlock(bp, obj); 350 351 atomic_set(counter, cnt); 352 } 353 354 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf, 355 int qid, bool drv_only, bool mac) 356 { 357 struct bnx2x_vlan_mac_ramrod_params ramrod; 358 int rc; 359 360 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, 361 mac ? "MACs" : "VLANs"); 362 363 /* Prepare ramrod params */ 364 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 365 if (mac) { 366 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 367 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 368 } else { 369 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 370 &ramrod.user_req.vlan_mac_flags); 371 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 372 } 373 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL; 374 375 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 376 if (drv_only) 377 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 378 else 379 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 380 381 /* Start deleting */ 382 rc = ramrod.vlan_mac_obj->delete_all(bp, 383 ramrod.vlan_mac_obj, 384 &ramrod.user_req.vlan_mac_flags, 385 &ramrod.ramrod_flags); 386 if (rc) { 387 BNX2X_ERR("Failed to delete all %s\n", 388 mac ? "MACs" : "VLANs"); 389 return rc; 390 } 391 392 /* Clear the vlan counters */ 393 if (!mac) 394 atomic_set(&bnx2x_vfq(vf, qid, vlan_count), 0); 395 396 return 0; 397 } 398 399 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp, 400 struct bnx2x_virtf *vf, int qid, 401 struct bnx2x_vf_mac_vlan_filter *filter, 402 bool drv_only) 403 { 404 struct bnx2x_vlan_mac_ramrod_params ramrod; 405 int rc; 406 407 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", 408 vf->abs_vfid, filter->add ? "Adding" : "Deleting", 409 filter->type == BNX2X_VF_FILTER_MAC ? "MAC" : "VLAN"); 410 411 /* Prepare ramrod params */ 412 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 413 if (filter->type == BNX2X_VF_FILTER_VLAN) { 414 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 415 &ramrod.user_req.vlan_mac_flags); 416 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 417 ramrod.user_req.u.vlan.vlan = filter->vid; 418 } else { 419 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 420 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 421 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 422 } 423 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD : 424 BNX2X_VLAN_MAC_DEL; 425 426 /* Verify there are available vlan credits */ 427 if (filter->add && filter->type == BNX2X_VF_FILTER_VLAN && 428 (atomic_read(&bnx2x_vfq(vf, qid, vlan_count)) >= 429 vf_vlan_rules_cnt(vf))) { 430 BNX2X_ERR("No credits for vlan\n"); 431 return -ENOMEM; 432 } 433 434 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 435 if (drv_only) 436 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 437 else 438 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 439 440 /* Add/Remove the filter */ 441 rc = bnx2x_config_vlan_mac(bp, &ramrod); 442 if (rc && rc != -EEXIST) { 443 BNX2X_ERR("Failed to %s %s\n", 444 filter->add ? "add" : "delete", 445 filter->type == BNX2X_VF_FILTER_MAC ? "MAC" : 446 "VLAN"); 447 return rc; 448 } 449 450 /* Update the vlan counters */ 451 if (filter->type == BNX2X_VF_FILTER_VLAN) 452 bnx2x_vf_vlan_credit(bp, ramrod.vlan_mac_obj, 453 &bnx2x_vfq(vf, qid, vlan_count)); 454 455 return 0; 456 } 457 458 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf, 459 struct bnx2x_vf_mac_vlan_filters *filters, 460 int qid, bool drv_only) 461 { 462 int rc = 0, i; 463 464 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 465 466 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 467 return -EINVAL; 468 469 /* Prepare ramrod params */ 470 for (i = 0; i < filters->count; i++) { 471 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, 472 &filters->filters[i], drv_only); 473 if (rc) 474 break; 475 } 476 477 /* Rollback if needed */ 478 if (i != filters->count) { 479 BNX2X_ERR("Managed only %d/%d filters - rolling back\n", 480 i, filters->count + 1); 481 while (--i >= 0) { 482 filters->filters[i].add = !filters->filters[i].add; 483 bnx2x_vf_mac_vlan_config(bp, vf, qid, 484 &filters->filters[i], 485 drv_only); 486 } 487 } 488 489 /* It's our responsibility to free the filters */ 490 kfree(filters); 491 492 return rc; 493 } 494 495 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid, 496 struct bnx2x_vf_queue_construct_params *qctor) 497 { 498 int rc; 499 500 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 501 502 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor); 503 if (rc) 504 goto op_err; 505 506 /* Configure vlan0 for leading queue */ 507 if (!qid) { 508 struct bnx2x_vf_mac_vlan_filter filter; 509 510 memset(&filter, 0, sizeof(struct bnx2x_vf_mac_vlan_filter)); 511 filter.type = BNX2X_VF_FILTER_VLAN; 512 filter.add = true; 513 filter.vid = 0; 514 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, &filter, false); 515 if (rc) 516 goto op_err; 517 } 518 519 /* Schedule the configuration of any pending vlan filters */ 520 vf->cfg_flags |= VF_CFG_VLAN; 521 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN, 522 BNX2X_MSG_IOV); 523 return 0; 524 op_err: 525 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 526 return rc; 527 } 528 529 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf, 530 int qid) 531 { 532 int rc; 533 534 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 535 536 /* If needed, clean the filtering data base */ 537 if ((qid == LEADING_IDX) && 538 bnx2x_validate_vf_sp_objs(bp, vf, false)) { 539 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, false); 540 if (rc) 541 goto op_err; 542 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, true); 543 if (rc) 544 goto op_err; 545 } 546 547 /* Terminate queue */ 548 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) { 549 struct bnx2x_queue_state_params qstate; 550 551 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 552 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 553 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED; 554 qstate.cmd = BNX2X_Q_CMD_TERMINATE; 555 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 556 rc = bnx2x_queue_state_change(bp, &qstate); 557 if (rc) 558 goto op_err; 559 } 560 561 return 0; 562 op_err: 563 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 564 return rc; 565 } 566 567 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf, 568 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only) 569 { 570 struct bnx2x_mcast_list_elem *mc = NULL; 571 struct bnx2x_mcast_ramrod_params mcast; 572 int rc, i; 573 574 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 575 576 /* Prepare Multicast command */ 577 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params)); 578 mcast.mcast_obj = &vf->mcast_obj; 579 if (drv_only) 580 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags); 581 else 582 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags); 583 if (mc_num) { 584 mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem), 585 GFP_KERNEL); 586 if (!mc) { 587 BNX2X_ERR("Cannot Configure mulicasts due to lack of memory\n"); 588 return -ENOMEM; 589 } 590 } 591 592 /* clear existing mcasts */ 593 mcast.mcast_list_len = vf->mcast_list_len; 594 vf->mcast_list_len = mc_num; 595 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL); 596 if (rc) { 597 BNX2X_ERR("Failed to remove multicasts\n"); 598 return rc; 599 } 600 601 /* update mcast list on the ramrod params */ 602 if (mc_num) { 603 INIT_LIST_HEAD(&mcast.mcast_list); 604 for (i = 0; i < mc_num; i++) { 605 mc[i].mac = mcasts[i]; 606 list_add_tail(&mc[i].link, 607 &mcast.mcast_list); 608 } 609 610 /* add new mcasts */ 611 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_ADD); 612 if (rc) 613 BNX2X_ERR("Faled to add multicasts\n"); 614 kfree(mc); 615 } 616 617 return rc; 618 } 619 620 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid, 621 struct bnx2x_rx_mode_ramrod_params *ramrod, 622 struct bnx2x_virtf *vf, 623 unsigned long accept_flags) 624 { 625 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid); 626 627 memset(ramrod, 0, sizeof(*ramrod)); 628 ramrod->cid = vfq->cid; 629 ramrod->cl_id = vfq_cl_id(vf, vfq); 630 ramrod->rx_mode_obj = &bp->rx_mode_obj; 631 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid); 632 ramrod->rx_accept_flags = accept_flags; 633 ramrod->tx_accept_flags = accept_flags; 634 ramrod->pstate = &vf->filter_state; 635 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING; 636 637 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 638 set_bit(RAMROD_RX, &ramrod->ramrod_flags); 639 set_bit(RAMROD_TX, &ramrod->ramrod_flags); 640 641 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2); 642 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2); 643 } 644 645 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf, 646 int qid, unsigned long accept_flags) 647 { 648 struct bnx2x_rx_mode_ramrod_params ramrod; 649 650 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 651 652 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags); 653 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 654 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags; 655 return bnx2x_config_rx_mode(bp, &ramrod); 656 } 657 658 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid) 659 { 660 int rc; 661 662 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 663 664 /* Remove all classification configuration for leading queue */ 665 if (qid == LEADING_IDX) { 666 rc = bnx2x_vf_rxmode(bp, vf, qid, 0); 667 if (rc) 668 goto op_err; 669 670 /* Remove filtering if feasible */ 671 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) { 672 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 673 false, false); 674 if (rc) 675 goto op_err; 676 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 677 false, true); 678 if (rc) 679 goto op_err; 680 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false); 681 if (rc) 682 goto op_err; 683 } 684 } 685 686 /* Destroy queue */ 687 rc = bnx2x_vf_queue_destroy(bp, vf, qid); 688 if (rc) 689 goto op_err; 690 return rc; 691 op_err: 692 BNX2X_ERR("vf[%d:%d] error: rc %d\n", 693 vf->abs_vfid, qid, rc); 694 return rc; 695 } 696 697 /* VF enable primitives 698 * when pretend is required the caller is responsible 699 * for calling pretend prior to calling these routines 700 */ 701 702 /* internal vf enable - until vf is enabled internally all transactions 703 * are blocked. This routine should always be called last with pretend. 704 */ 705 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable) 706 { 707 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); 708 } 709 710 /* clears vf error in all semi blocks */ 711 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid) 712 { 713 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); 714 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); 715 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); 716 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); 717 } 718 719 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid) 720 { 721 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5; 722 u32 was_err_reg = 0; 723 724 switch (was_err_group) { 725 case 0: 726 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR; 727 break; 728 case 1: 729 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR; 730 break; 731 case 2: 732 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR; 733 break; 734 case 3: 735 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR; 736 break; 737 } 738 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); 739 } 740 741 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf) 742 { 743 int i; 744 u32 val; 745 746 /* Set VF masks and configuration - pretend */ 747 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 748 749 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 750 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 751 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 752 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 753 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 754 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 755 756 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 757 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); 758 if (vf->cfg_flags & VF_CFG_INT_SIMD) 759 val |= IGU_VF_CONF_SINGLE_ISR_EN; 760 val &= ~IGU_VF_CONF_PARENT_MASK; 761 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; 762 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 763 764 DP(BNX2X_MSG_IOV, 765 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n", 766 vf->abs_vfid, val); 767 768 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 769 770 /* iterate over all queues, clear sb consumer */ 771 for (i = 0; i < vf_sb_count(vf); i++) { 772 u8 igu_sb_id = vf_igu_sb(vf, i); 773 774 /* zero prod memory */ 775 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); 776 777 /* clear sb state machine */ 778 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id, 779 false /* VF */); 780 781 /* disable + update */ 782 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0, 783 IGU_INT_DISABLE, 1); 784 } 785 } 786 787 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid) 788 { 789 /* set the VF-PF association in the FW */ 790 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp)); 791 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1); 792 793 /* clear vf errors*/ 794 bnx2x_vf_semi_clear_err(bp, abs_vfid); 795 bnx2x_vf_pglue_clear_err(bp, abs_vfid); 796 797 /* internal vf-enable - pretend */ 798 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid)); 799 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); 800 bnx2x_vf_enable_internal(bp, true); 801 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 802 } 803 804 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf) 805 { 806 /* Reset vf in IGU interrupts are still disabled */ 807 bnx2x_vf_igu_reset(bp, vf); 808 809 /* pretend to enable the vf with the PBF */ 810 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 811 REG_WR(bp, PBF_REG_DISABLE_VF, 0); 812 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 813 } 814 815 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) 816 { 817 struct pci_dev *dev; 818 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 819 820 if (!vf) 821 return false; 822 823 dev = pci_get_bus_and_slot(vf->bus, vf->devfn); 824 if (dev) 825 return bnx2x_is_pcie_pending(dev); 826 return false; 827 } 828 829 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid) 830 { 831 /* Verify no pending pci transactions */ 832 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid)) 833 BNX2X_ERR("PCIE Transactions still pending\n"); 834 835 return 0; 836 } 837 838 /* must be called after the number of PF queues and the number of VFs are 839 * both known 840 */ 841 static void 842 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 843 { 844 struct vf_pf_resc_request *resc = &vf->alloc_resc; 845 u16 vlan_count = 0; 846 847 /* will be set only during VF-ACQUIRE */ 848 resc->num_rxqs = 0; 849 resc->num_txqs = 0; 850 851 /* no credit calculations for macs (just yet) */ 852 resc->num_mac_filters = 1; 853 854 /* divvy up vlan rules */ 855 vlan_count = bp->vlans_pool.check(&bp->vlans_pool); 856 vlan_count = 1 << ilog2(vlan_count); 857 resc->num_vlan_filters = vlan_count / BNX2X_NR_VIRTFN(bp); 858 859 /* no real limitation */ 860 resc->num_mc_filters = 0; 861 862 /* num_sbs already set */ 863 resc->num_sbs = vf->sb_count; 864 } 865 866 /* FLR routines: */ 867 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 868 { 869 /* reset the state variables */ 870 bnx2x_iov_static_resc(bp, vf); 871 vf->state = VF_FREE; 872 } 873 874 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf) 875 { 876 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 877 878 /* DQ usage counter */ 879 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 880 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT, 881 "DQ VF usage counter timed out", 882 poll_cnt); 883 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 884 885 /* FW cleanup command - poll for the results */ 886 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid), 887 poll_cnt)) 888 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid); 889 890 /* verify TX hw is flushed */ 891 bnx2x_tx_hw_flushed(bp, poll_cnt); 892 } 893 894 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf) 895 { 896 int rc, i; 897 898 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 899 900 /* the cleanup operations are valid if and only if the VF 901 * was first acquired. 902 */ 903 for (i = 0; i < vf_rxq_count(vf); i++) { 904 rc = bnx2x_vf_queue_flr(bp, vf, i); 905 if (rc) 906 goto out; 907 } 908 909 /* remove multicasts */ 910 bnx2x_vf_mcast(bp, vf, NULL, 0, true); 911 912 /* dispatch final cleanup and wait for HW queues to flush */ 913 bnx2x_vf_flr_clnup_hw(bp, vf); 914 915 /* release VF resources */ 916 bnx2x_vf_free_resc(bp, vf); 917 918 /* re-open the mailbox */ 919 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 920 return; 921 out: 922 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n", 923 vf->abs_vfid, i, rc); 924 } 925 926 static void bnx2x_vf_flr_clnup(struct bnx2x *bp) 927 { 928 struct bnx2x_virtf *vf; 929 int i; 930 931 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) { 932 /* VF should be RESET & in FLR cleanup states */ 933 if (bnx2x_vf(bp, i, state) != VF_RESET || 934 !bnx2x_vf(bp, i, flr_clnup_stage)) 935 continue; 936 937 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", 938 i, BNX2X_NR_VIRTFN(bp)); 939 940 vf = BP_VF(bp, i); 941 942 /* lock the vf pf channel */ 943 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 944 945 /* invoke the VF FLR SM */ 946 bnx2x_vf_flr(bp, vf); 947 948 /* mark the VF to be ACKED and continue */ 949 vf->flr_clnup_stage = false; 950 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 951 } 952 953 /* Acknowledge the handled VFs. 954 * we are acknowledge all the vfs which an flr was requested for, even 955 * if amongst them there are such that we never opened, since the mcp 956 * will interrupt us immediately again if we only ack some of the bits, 957 * resulting in an endless loop. This can happen for example in KVM 958 * where an 'all ones' flr request is sometimes given by hyper visor 959 */ 960 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", 961 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 962 for (i = 0; i < FLRD_VFS_DWORDS; i++) 963 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 964 bp->vfdb->flrd_vfs[i]); 965 966 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0); 967 968 /* clear the acked bits - better yet if the MCP implemented 969 * write to clear semantics 970 */ 971 for (i = 0; i < FLRD_VFS_DWORDS; i++) 972 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0); 973 } 974 975 void bnx2x_vf_handle_flr_event(struct bnx2x *bp) 976 { 977 int i; 978 979 /* Read FLR'd VFs */ 980 for (i = 0; i < FLRD_VFS_DWORDS; i++) 981 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]); 982 983 DP(BNX2X_MSG_MCP, 984 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n", 985 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 986 987 for_each_vf(bp, i) { 988 struct bnx2x_virtf *vf = BP_VF(bp, i); 989 u32 reset = 0; 990 991 if (vf->abs_vfid < 32) 992 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid); 993 else 994 reset = bp->vfdb->flrd_vfs[1] & 995 (1 << (vf->abs_vfid - 32)); 996 997 if (reset) { 998 /* set as reset and ready for cleanup */ 999 vf->state = VF_RESET; 1000 vf->flr_clnup_stage = true; 1001 1002 DP(BNX2X_MSG_IOV, 1003 "Initiating Final cleanup for VF %d\n", 1004 vf->abs_vfid); 1005 } 1006 } 1007 1008 /* do the FLR cleanup for all marked VFs*/ 1009 bnx2x_vf_flr_clnup(bp); 1010 } 1011 1012 /* IOV global initialization routines */ 1013 void bnx2x_iov_init_dq(struct bnx2x *bp) 1014 { 1015 if (!IS_SRIOV(bp)) 1016 return; 1017 1018 /* Set the DQ such that the CID reflect the abs_vfid */ 1019 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); 1020 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 1021 1022 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to 1023 * the PF L2 queues 1024 */ 1025 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 1026 1027 /* The VF window size is the log2 of the max number of CIDs per VF */ 1028 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 1029 1030 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 1031 * the Pf doorbell size although the 2 are independent. 1032 */ 1033 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); 1034 1035 /* No security checks for now - 1036 * configure single rule (out of 16) mask = 0x1, value = 0x0, 1037 * CID range 0 - 0x1ffff 1038 */ 1039 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); 1040 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); 1041 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 1042 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 1043 1044 /* set the VF doorbell threshold */ 1045 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 4); 1046 } 1047 1048 void bnx2x_iov_init_dmae(struct bnx2x *bp) 1049 { 1050 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV)) 1051 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); 1052 } 1053 1054 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid) 1055 { 1056 struct pci_dev *dev = bp->pdev; 1057 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1058 1059 return dev->bus->number + ((dev->devfn + iov->offset + 1060 iov->stride * vfid) >> 8); 1061 } 1062 1063 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid) 1064 { 1065 struct pci_dev *dev = bp->pdev; 1066 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1067 1068 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff; 1069 } 1070 1071 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf) 1072 { 1073 int i, n; 1074 struct pci_dev *dev = bp->pdev; 1075 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1076 1077 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) { 1078 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i); 1079 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i); 1080 1081 size /= iov->total; 1082 vf->bars[n].bar = start + size * vf->abs_vfid; 1083 vf->bars[n].size = size; 1084 } 1085 } 1086 1087 static int bnx2x_ari_enabled(struct pci_dev *dev) 1088 { 1089 return dev->bus->self && dev->bus->self->ari_enabled; 1090 } 1091 1092 static void 1093 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp) 1094 { 1095 int sb_id; 1096 u32 val; 1097 u8 fid, current_pf = 0; 1098 1099 /* IGU in normal mode - read CAM */ 1100 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) { 1101 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); 1102 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 1103 continue; 1104 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); 1105 if (fid & IGU_FID_ENCODE_IS_PF) 1106 current_pf = fid & IGU_FID_PF_NUM_MASK; 1107 else if (current_pf == BP_FUNC(bp)) 1108 bnx2x_vf_set_igu_info(bp, sb_id, 1109 (fid & IGU_FID_VF_NUM_MASK)); 1110 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", 1111 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"), 1112 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) : 1113 (fid & IGU_FID_VF_NUM_MASK)), sb_id, 1114 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); 1115 } 1116 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); 1117 } 1118 1119 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp) 1120 { 1121 if (bp->vfdb) { 1122 kfree(bp->vfdb->vfqs); 1123 kfree(bp->vfdb->vfs); 1124 kfree(bp->vfdb); 1125 } 1126 bp->vfdb = NULL; 1127 } 1128 1129 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1130 { 1131 int pos; 1132 struct pci_dev *dev = bp->pdev; 1133 1134 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 1135 if (!pos) { 1136 BNX2X_ERR("failed to find SRIOV capability in device\n"); 1137 return -ENODEV; 1138 } 1139 1140 iov->pos = pos; 1141 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); 1142 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); 1143 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total); 1144 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial); 1145 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset); 1146 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride); 1147 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); 1148 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); 1149 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); 1150 1151 return 0; 1152 } 1153 1154 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1155 { 1156 u32 val; 1157 1158 /* read the SRIOV capability structure 1159 * The fields can be read via configuration read or 1160 * directly from the device (starting at offset PCICFG_OFFSET) 1161 */ 1162 if (bnx2x_sriov_pci_cfg_info(bp, iov)) 1163 return -ENODEV; 1164 1165 /* get the number of SRIOV bars */ 1166 iov->nres = 0; 1167 1168 /* read the first_vfid */ 1169 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 1170 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) 1171 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp)); 1172 1173 DP(BNX2X_MSG_IOV, 1174 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n", 1175 BP_FUNC(bp), 1176 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total, 1177 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz); 1178 1179 return 0; 1180 } 1181 1182 /* must be called after PF bars are mapped */ 1183 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, 1184 int num_vfs_param) 1185 { 1186 int err, i; 1187 struct bnx2x_sriov *iov; 1188 struct pci_dev *dev = bp->pdev; 1189 1190 bp->vfdb = NULL; 1191 1192 /* verify is pf */ 1193 if (IS_VF(bp)) 1194 return 0; 1195 1196 /* verify sriov capability is present in configuration space */ 1197 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV)) 1198 return 0; 1199 1200 /* verify chip revision */ 1201 if (CHIP_IS_E1x(bp)) 1202 return 0; 1203 1204 /* check if SRIOV support is turned off */ 1205 if (!num_vfs_param) 1206 return 0; 1207 1208 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */ 1209 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) { 1210 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n", 1211 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID); 1212 return 0; 1213 } 1214 1215 /* SRIOV can be enabled only with MSIX */ 1216 if (int_mode_param == BNX2X_INT_MODE_MSI || 1217 int_mode_param == BNX2X_INT_MODE_INTX) { 1218 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); 1219 return 0; 1220 } 1221 1222 err = -EIO; 1223 /* verify ari is enabled */ 1224 if (!bnx2x_ari_enabled(bp->pdev)) { 1225 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); 1226 return 0; 1227 } 1228 1229 /* verify igu is in normal mode */ 1230 if (CHIP_INT_MODE_IS_BC(bp)) { 1231 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); 1232 return 0; 1233 } 1234 1235 /* allocate the vfs database */ 1236 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL); 1237 if (!bp->vfdb) { 1238 BNX2X_ERR("failed to allocate vf database\n"); 1239 err = -ENOMEM; 1240 goto failed; 1241 } 1242 1243 /* get the sriov info - Linux already collected all the pertinent 1244 * information, however the sriov structure is for the private use 1245 * of the pci module. Also we want this information regardless 1246 * of the hyper-visor. 1247 */ 1248 iov = &(bp->vfdb->sriov); 1249 err = bnx2x_sriov_info(bp, iov); 1250 if (err) 1251 goto failed; 1252 1253 /* SR-IOV capability was enabled but there are no VFs*/ 1254 if (iov->total == 0) 1255 goto failed; 1256 1257 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); 1258 1259 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", 1260 num_vfs_param, iov->nr_virtfn); 1261 1262 /* allocate the vf array */ 1263 bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * 1264 BNX2X_NR_VIRTFN(bp), GFP_KERNEL); 1265 if (!bp->vfdb->vfs) { 1266 BNX2X_ERR("failed to allocate vf array\n"); 1267 err = -ENOMEM; 1268 goto failed; 1269 } 1270 1271 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */ 1272 for_each_vf(bp, i) { 1273 bnx2x_vf(bp, i, index) = i; 1274 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i; 1275 bnx2x_vf(bp, i, state) = VF_FREE; 1276 mutex_init(&bnx2x_vf(bp, i, op_mutex)); 1277 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE; 1278 } 1279 1280 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */ 1281 bnx2x_get_vf_igu_cam_info(bp); 1282 1283 /* allocate the queue arrays for all VFs */ 1284 bp->vfdb->vfqs = kzalloc( 1285 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue), 1286 GFP_KERNEL); 1287 1288 DP(BNX2X_MSG_IOV, "bp->vfdb->vfqs was %p\n", bp->vfdb->vfqs); 1289 1290 if (!bp->vfdb->vfqs) { 1291 BNX2X_ERR("failed to allocate vf queue array\n"); 1292 err = -ENOMEM; 1293 goto failed; 1294 } 1295 1296 /* Prepare the VFs event synchronization mechanism */ 1297 mutex_init(&bp->vfdb->event_mutex); 1298 1299 return 0; 1300 failed: 1301 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err); 1302 __bnx2x_iov_free_vfdb(bp); 1303 return err; 1304 } 1305 1306 void bnx2x_iov_remove_one(struct bnx2x *bp) 1307 { 1308 int vf_idx; 1309 1310 /* if SRIOV is not enabled there's nothing to do */ 1311 if (!IS_SRIOV(bp)) 1312 return; 1313 1314 DP(BNX2X_MSG_IOV, "about to call disable sriov\n"); 1315 pci_disable_sriov(bp->pdev); 1316 DP(BNX2X_MSG_IOV, "sriov disabled\n"); 1317 1318 /* disable access to all VFs */ 1319 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) { 1320 bnx2x_pretend_func(bp, 1321 HW_VF_HANDLE(bp, 1322 bp->vfdb->sriov.first_vf_in_pf + 1323 vf_idx)); 1324 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", 1325 bp->vfdb->sriov.first_vf_in_pf + vf_idx); 1326 bnx2x_vf_enable_internal(bp, 0); 1327 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1328 } 1329 1330 /* free vf database */ 1331 __bnx2x_iov_free_vfdb(bp); 1332 } 1333 1334 void bnx2x_iov_free_mem(struct bnx2x *bp) 1335 { 1336 int i; 1337 1338 if (!IS_SRIOV(bp)) 1339 return; 1340 1341 /* free vfs hw contexts */ 1342 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1343 struct hw_dma *cxt = &bp->vfdb->context[i]; 1344 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size); 1345 } 1346 1347 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr, 1348 BP_VFDB(bp)->sp_dma.mapping, 1349 BP_VFDB(bp)->sp_dma.size); 1350 1351 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr, 1352 BP_VF_MBX_DMA(bp)->mapping, 1353 BP_VF_MBX_DMA(bp)->size); 1354 1355 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr, 1356 BP_VF_BULLETIN_DMA(bp)->mapping, 1357 BP_VF_BULLETIN_DMA(bp)->size); 1358 } 1359 1360 int bnx2x_iov_alloc_mem(struct bnx2x *bp) 1361 { 1362 size_t tot_size; 1363 int i, rc = 0; 1364 1365 if (!IS_SRIOV(bp)) 1366 return rc; 1367 1368 /* allocate vfs hw contexts */ 1369 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) * 1370 BNX2X_CIDS_PER_VF * sizeof(union cdu_context); 1371 1372 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1373 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i); 1374 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ); 1375 1376 if (cxt->size) { 1377 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size); 1378 if (!cxt->addr) 1379 goto alloc_mem_err; 1380 } else { 1381 cxt->addr = NULL; 1382 cxt->mapping = 0; 1383 } 1384 tot_size -= cxt->size; 1385 } 1386 1387 /* allocate vfs ramrods dma memory - client_init and set_mac */ 1388 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp); 1389 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping, 1390 tot_size); 1391 if (!BP_VFDB(bp)->sp_dma.addr) 1392 goto alloc_mem_err; 1393 BP_VFDB(bp)->sp_dma.size = tot_size; 1394 1395 /* allocate mailboxes */ 1396 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE; 1397 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping, 1398 tot_size); 1399 if (!BP_VF_MBX_DMA(bp)->addr) 1400 goto alloc_mem_err; 1401 1402 BP_VF_MBX_DMA(bp)->size = tot_size; 1403 1404 /* allocate local bulletin boards */ 1405 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE; 1406 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping, 1407 tot_size); 1408 if (!BP_VF_BULLETIN_DMA(bp)->addr) 1409 goto alloc_mem_err; 1410 1411 BP_VF_BULLETIN_DMA(bp)->size = tot_size; 1412 1413 return 0; 1414 1415 alloc_mem_err: 1416 return -ENOMEM; 1417 } 1418 1419 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf, 1420 struct bnx2x_vf_queue *q) 1421 { 1422 u8 cl_id = vfq_cl_id(vf, q); 1423 u8 func_id = FW_VF_HANDLE(vf->abs_vfid); 1424 unsigned long q_type = 0; 1425 1426 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1427 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1428 1429 /* Queue State object */ 1430 bnx2x_init_queue_obj(bp, &q->sp_obj, 1431 cl_id, &q->cid, 1, func_id, 1432 bnx2x_vf_sp(bp, vf, q_data), 1433 bnx2x_vf_sp_map(bp, vf, q_data), 1434 q_type); 1435 1436 /* sp indication is set only when vlan/mac/etc. are initialized */ 1437 q->sp_initialized = false; 1438 1439 DP(BNX2X_MSG_IOV, 1440 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n", 1441 vf->abs_vfid, q->sp_obj.func_id, q->cid); 1442 } 1443 1444 /* called by bnx2x_nic_load */ 1445 int bnx2x_iov_nic_init(struct bnx2x *bp) 1446 { 1447 int vfid; 1448 1449 if (!IS_SRIOV(bp)) { 1450 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); 1451 return 0; 1452 } 1453 1454 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); 1455 1456 /* let FLR complete ... */ 1457 msleep(100); 1458 1459 /* initialize vf database */ 1460 for_each_vf(bp, vfid) { 1461 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1462 1463 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) * 1464 BNX2X_CIDS_PER_VF; 1465 1466 union cdu_context *base_cxt = (union cdu_context *) 1467 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 1468 (base_vf_cid & (ILT_PAGE_CIDS-1)); 1469 1470 DP(BNX2X_MSG_IOV, 1471 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n", 1472 vf->abs_vfid, vf_sb_count(vf), base_vf_cid, 1473 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt); 1474 1475 /* init statically provisioned resources */ 1476 bnx2x_iov_static_resc(bp, vf); 1477 1478 /* queues are initialized during VF-ACQUIRE */ 1479 1480 /* reserve the vf vlan credit */ 1481 bp->vlans_pool.get(&bp->vlans_pool, vf_vlan_rules_cnt(vf)); 1482 1483 vf->filter_state = 0; 1484 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id); 1485 1486 /* init mcast object - This object will be re-initialized 1487 * during VF-ACQUIRE with the proper cl_id and cid. 1488 * It needs to be initialized here so that it can be safely 1489 * handled by a subsequent FLR flow. 1490 */ 1491 vf->mcast_list_len = 0; 1492 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF, 1493 0xFF, 0xFF, 0xFF, 1494 bnx2x_vf_sp(bp, vf, mcast_rdata), 1495 bnx2x_vf_sp_map(bp, vf, mcast_rdata), 1496 BNX2X_FILTER_MCAST_PENDING, 1497 &vf->filter_state, 1498 BNX2X_OBJ_TYPE_RX_TX); 1499 1500 /* set the mailbox message addresses */ 1501 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *) 1502 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid * 1503 MBX_MSG_ALIGNED_SIZE); 1504 1505 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping + 1506 vfid * MBX_MSG_ALIGNED_SIZE; 1507 1508 /* Enable vf mailbox */ 1509 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 1510 } 1511 1512 /* Final VF init */ 1513 for_each_vf(bp, vfid) { 1514 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1515 1516 /* fill in the BDF and bars */ 1517 vf->bus = bnx2x_vf_bus(bp, vfid); 1518 vf->devfn = bnx2x_vf_devfn(bp, vfid); 1519 bnx2x_vf_set_bars(bp, vf); 1520 1521 DP(BNX2X_MSG_IOV, 1522 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n", 1523 vf->abs_vfid, vf->bus, vf->devfn, 1524 (unsigned)vf->bars[0].bar, vf->bars[0].size, 1525 (unsigned)vf->bars[1].bar, vf->bars[1].size, 1526 (unsigned)vf->bars[2].bar, vf->bars[2].size); 1527 } 1528 1529 return 0; 1530 } 1531 1532 /* called by bnx2x_chip_cleanup */ 1533 int bnx2x_iov_chip_cleanup(struct bnx2x *bp) 1534 { 1535 int i; 1536 1537 if (!IS_SRIOV(bp)) 1538 return 0; 1539 1540 /* release all the VFs */ 1541 for_each_vf(bp, i) 1542 bnx2x_vf_release(bp, BP_VF(bp, i)); 1543 1544 return 0; 1545 } 1546 1547 /* called by bnx2x_init_hw_func, returns the next ilt line */ 1548 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) 1549 { 1550 int i; 1551 struct bnx2x_ilt *ilt = BP_ILT(bp); 1552 1553 if (!IS_SRIOV(bp)) 1554 return line; 1555 1556 /* set vfs ilt lines */ 1557 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1558 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i); 1559 1560 ilt->lines[line+i].page = hw_cxt->addr; 1561 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 1562 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 1563 } 1564 return line + i; 1565 } 1566 1567 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid) 1568 { 1569 return ((cid >= BNX2X_FIRST_VF_CID) && 1570 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS)); 1571 } 1572 1573 static 1574 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp, 1575 struct bnx2x_vf_queue *vfq, 1576 union event_ring_elem *elem) 1577 { 1578 unsigned long ramrod_flags = 0; 1579 int rc = 0; 1580 1581 /* Always push next commands out, don't wait here */ 1582 set_bit(RAMROD_CONT, &ramrod_flags); 1583 1584 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 1585 case BNX2X_FILTER_MAC_PENDING: 1586 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem, 1587 &ramrod_flags); 1588 break; 1589 case BNX2X_FILTER_VLAN_PENDING: 1590 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem, 1591 &ramrod_flags); 1592 break; 1593 default: 1594 BNX2X_ERR("Unsupported classification command: %d\n", 1595 elem->message.data.eth_event.echo); 1596 return; 1597 } 1598 if (rc < 0) 1599 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 1600 else if (rc > 0) 1601 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); 1602 } 1603 1604 static 1605 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp, 1606 struct bnx2x_virtf *vf) 1607 { 1608 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 1609 int rc; 1610 1611 rparam.mcast_obj = &vf->mcast_obj; 1612 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw); 1613 1614 /* If there are pending mcast commands - send them */ 1615 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) { 1616 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 1617 if (rc < 0) 1618 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 1619 rc); 1620 } 1621 } 1622 1623 static 1624 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp, 1625 struct bnx2x_virtf *vf) 1626 { 1627 smp_mb__before_clear_bit(); 1628 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 1629 smp_mb__after_clear_bit(); 1630 } 1631 1632 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp, 1633 struct bnx2x_virtf *vf) 1634 { 1635 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw); 1636 } 1637 1638 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) 1639 { 1640 struct bnx2x_virtf *vf; 1641 int qidx = 0, abs_vfid; 1642 u8 opcode; 1643 u16 cid = 0xffff; 1644 1645 if (!IS_SRIOV(bp)) 1646 return 1; 1647 1648 /* first get the cid - the only events we handle here are cfc-delete 1649 * and set-mac completion 1650 */ 1651 opcode = elem->message.opcode; 1652 1653 switch (opcode) { 1654 case EVENT_RING_OPCODE_CFC_DEL: 1655 cid = SW_CID((__force __le32) 1656 elem->message.data.cfc_del_event.cid); 1657 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); 1658 break; 1659 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1660 case EVENT_RING_OPCODE_MULTICAST_RULES: 1661 case EVENT_RING_OPCODE_FILTERS_RULES: 1662 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1663 cid = (elem->message.data.eth_event.echo & 1664 BNX2X_SWCID_MASK); 1665 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); 1666 break; 1667 case EVENT_RING_OPCODE_VF_FLR: 1668 abs_vfid = elem->message.data.vf_flr_event.vf_id; 1669 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", 1670 abs_vfid); 1671 goto get_vf; 1672 case EVENT_RING_OPCODE_MALICIOUS_VF: 1673 abs_vfid = elem->message.data.malicious_vf_event.vf_id; 1674 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", 1675 abs_vfid, 1676 elem->message.data.malicious_vf_event.err_id); 1677 goto get_vf; 1678 default: 1679 return 1; 1680 } 1681 1682 /* check if the cid is the VF range */ 1683 if (!bnx2x_iov_is_vf_cid(bp, cid)) { 1684 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); 1685 return 1; 1686 } 1687 1688 /* extract vf and rxq index from vf_cid - relies on the following: 1689 * 1. vfid on cid reflects the true abs_vfid 1690 * 2. The max number of VFs (per path) is 64 1691 */ 1692 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1); 1693 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1694 get_vf: 1695 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 1696 1697 if (!vf) { 1698 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n", 1699 cid, abs_vfid); 1700 return 0; 1701 } 1702 1703 switch (opcode) { 1704 case EVENT_RING_OPCODE_CFC_DEL: 1705 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", 1706 vf->abs_vfid, qidx); 1707 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp, 1708 &vfq_get(vf, 1709 qidx)->sp_obj, 1710 BNX2X_Q_CMD_CFC_DEL); 1711 break; 1712 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1713 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", 1714 vf->abs_vfid, qidx); 1715 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem); 1716 break; 1717 case EVENT_RING_OPCODE_MULTICAST_RULES: 1718 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", 1719 vf->abs_vfid, qidx); 1720 bnx2x_vf_handle_mcast_eqe(bp, vf); 1721 break; 1722 case EVENT_RING_OPCODE_FILTERS_RULES: 1723 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", 1724 vf->abs_vfid, qidx); 1725 bnx2x_vf_handle_filters_eqe(bp, vf); 1726 break; 1727 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1728 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", 1729 vf->abs_vfid, qidx); 1730 bnx2x_vf_handle_rss_update_eqe(bp, vf); 1731 case EVENT_RING_OPCODE_VF_FLR: 1732 case EVENT_RING_OPCODE_MALICIOUS_VF: 1733 /* Do nothing for now */ 1734 return 0; 1735 } 1736 1737 return 0; 1738 } 1739 1740 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid) 1741 { 1742 /* extract the vf from vf_cid - relies on the following: 1743 * 1. vfid on cid reflects the true abs_vfid 1744 * 2. The max number of VFs (per path) is 64 1745 */ 1746 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1747 return bnx2x_vf_by_abs_fid(bp, abs_vfid); 1748 } 1749 1750 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid, 1751 struct bnx2x_queue_sp_obj **q_obj) 1752 { 1753 struct bnx2x_virtf *vf; 1754 1755 if (!IS_SRIOV(bp)) 1756 return; 1757 1758 vf = bnx2x_vf_by_cid(bp, vf_cid); 1759 1760 if (vf) { 1761 /* extract queue index from vf_cid - relies on the following: 1762 * 1. vfid on cid reflects the true abs_vfid 1763 * 2. The max number of VFs (per path) is 64 1764 */ 1765 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1); 1766 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj); 1767 } else { 1768 BNX2X_ERR("No vf matching cid %d\n", vf_cid); 1769 } 1770 } 1771 1772 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) 1773 { 1774 int i; 1775 int first_queue_query_index, num_queues_req; 1776 dma_addr_t cur_data_offset; 1777 struct stats_query_entry *cur_query_entry; 1778 u8 stats_count = 0; 1779 bool is_fcoe = false; 1780 1781 if (!IS_SRIOV(bp)) 1782 return; 1783 1784 if (!NO_FCOE(bp)) 1785 is_fcoe = true; 1786 1787 /* fcoe adds one global request and one queue request */ 1788 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe; 1789 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1790 (is_fcoe ? 0 : 1); 1791 1792 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1793 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n", 1794 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index, 1795 first_queue_query_index + num_queues_req); 1796 1797 cur_data_offset = bp->fw_stats_data_mapping + 1798 offsetof(struct bnx2x_fw_stats_data, queue_stats) + 1799 num_queues_req * sizeof(struct per_queue_stats); 1800 1801 cur_query_entry = &bp->fw_stats_req-> 1802 query[first_queue_query_index + num_queues_req]; 1803 1804 for_each_vf(bp, i) { 1805 int j; 1806 struct bnx2x_virtf *vf = BP_VF(bp, i); 1807 1808 if (vf->state != VF_ENABLED) { 1809 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1810 "vf %d not enabled so no stats for it\n", 1811 vf->abs_vfid); 1812 continue; 1813 } 1814 1815 DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid); 1816 for_each_vfq(vf, j) { 1817 struct bnx2x_vf_queue *rxq = vfq_get(vf, j); 1818 1819 dma_addr_t q_stats_addr = 1820 vf->fw_stat_map + j * vf->stats_stride; 1821 1822 /* collect stats fro active queues only */ 1823 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) == 1824 BNX2X_Q_LOGICAL_STATE_STOPPED) 1825 continue; 1826 1827 /* create stats query entry for this queue */ 1828 cur_query_entry->kind = STATS_TYPE_QUEUE; 1829 cur_query_entry->index = vfq_stat_id(vf, rxq); 1830 cur_query_entry->funcID = 1831 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid)); 1832 cur_query_entry->address.hi = 1833 cpu_to_le32(U64_HI(q_stats_addr)); 1834 cur_query_entry->address.lo = 1835 cpu_to_le32(U64_LO(q_stats_addr)); 1836 DP(BNX2X_MSG_IOV, 1837 "added address %x %x for vf %d queue %d client %d\n", 1838 cur_query_entry->address.hi, 1839 cur_query_entry->address.lo, cur_query_entry->funcID, 1840 j, cur_query_entry->index); 1841 cur_query_entry++; 1842 cur_data_offset += sizeof(struct per_queue_stats); 1843 stats_count++; 1844 1845 /* all stats are coalesced to the leading queue */ 1846 if (vf->cfg_flags & VF_CFG_STATS_COALESCE) 1847 break; 1848 } 1849 } 1850 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count; 1851 } 1852 1853 static inline 1854 struct bnx2x_virtf *__vf_from_stat_id(struct bnx2x *bp, u8 stat_id) 1855 { 1856 int i; 1857 struct bnx2x_virtf *vf = NULL; 1858 1859 for_each_vf(bp, i) { 1860 vf = BP_VF(bp, i); 1861 if (stat_id >= vf->igu_base_id && 1862 stat_id < vf->igu_base_id + vf_sb_count(vf)) 1863 break; 1864 } 1865 return vf; 1866 } 1867 1868 /* VF API helpers */ 1869 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid, 1870 u8 enable) 1871 { 1872 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; 1873 u32 val = enable ? (abs_vfid | (1 << 6)) : 0; 1874 1875 REG_WR(bp, reg, val); 1876 } 1877 1878 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf) 1879 { 1880 int i; 1881 1882 for_each_vfq(vf, i) 1883 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 1884 vfq_qzone_id(vf, vfq_get(vf, i)), false); 1885 } 1886 1887 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf) 1888 { 1889 u32 val; 1890 1891 /* clear the VF configuration - pretend */ 1892 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 1893 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 1894 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | 1895 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK); 1896 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 1897 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1898 } 1899 1900 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf) 1901 { 1902 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF), 1903 BNX2X_VF_MAX_QUEUES); 1904 } 1905 1906 static 1907 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf, 1908 struct vf_pf_resc_request *req_resc) 1909 { 1910 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 1911 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 1912 1913 return ((req_resc->num_rxqs <= rxq_cnt) && 1914 (req_resc->num_txqs <= txq_cnt) && 1915 (req_resc->num_sbs <= vf_sb_count(vf)) && 1916 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) && 1917 (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf))); 1918 } 1919 1920 /* CORE VF API */ 1921 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf, 1922 struct vf_pf_resc_request *resc) 1923 { 1924 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) * 1925 BNX2X_CIDS_PER_VF; 1926 1927 union cdu_context *base_cxt = (union cdu_context *) 1928 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 1929 (base_vf_cid & (ILT_PAGE_CIDS-1)); 1930 int i; 1931 1932 /* if state is 'acquired' the VF was not released or FLR'd, in 1933 * this case the returned resources match the acquired already 1934 * acquired resources. Verify that the requested numbers do 1935 * not exceed the already acquired numbers. 1936 */ 1937 if (vf->state == VF_ACQUIRED) { 1938 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", 1939 vf->abs_vfid); 1940 1941 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 1942 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n", 1943 vf->abs_vfid); 1944 return -EINVAL; 1945 } 1946 return 0; 1947 } 1948 1949 /* Otherwise vf state must be 'free' or 'reset' */ 1950 if (vf->state != VF_FREE && vf->state != VF_RESET) { 1951 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n", 1952 vf->abs_vfid, vf->state); 1953 return -EINVAL; 1954 } 1955 1956 /* static allocation: 1957 * the global maximum number are fixed per VF. Fail the request if 1958 * requested number exceed these globals 1959 */ 1960 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 1961 DP(BNX2X_MSG_IOV, 1962 "cannot fulfill vf resource request. Placing maximal available values in response\n"); 1963 /* set the max resource in the vf */ 1964 return -ENOMEM; 1965 } 1966 1967 /* Set resources counters - 0 request means max available */ 1968 vf_sb_count(vf) = resc->num_sbs; 1969 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 1970 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 1971 if (resc->num_mac_filters) 1972 vf_mac_rules_cnt(vf) = resc->num_mac_filters; 1973 if (resc->num_vlan_filters) 1974 vf_vlan_rules_cnt(vf) = resc->num_vlan_filters; 1975 1976 DP(BNX2X_MSG_IOV, 1977 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n", 1978 vf_sb_count(vf), vf_rxq_count(vf), 1979 vf_txq_count(vf), vf_mac_rules_cnt(vf), 1980 vf_vlan_rules_cnt(vf)); 1981 1982 /* Initialize the queues */ 1983 if (!vf->vfqs) { 1984 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); 1985 return -EINVAL; 1986 } 1987 1988 for_each_vfq(vf, i) { 1989 struct bnx2x_vf_queue *q = vfq_get(vf, i); 1990 1991 if (!q) { 1992 BNX2X_ERR("q number %d was not allocated\n", i); 1993 return -EINVAL; 1994 } 1995 1996 q->index = i; 1997 q->cxt = &((base_cxt + i)->eth); 1998 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i; 1999 2000 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", 2001 vf->abs_vfid, i, q->index, q->cid, q->cxt); 2002 2003 /* init SP objects */ 2004 bnx2x_vfq_init(bp, vf, q); 2005 } 2006 vf->state = VF_ACQUIRED; 2007 return 0; 2008 } 2009 2010 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map) 2011 { 2012 struct bnx2x_func_init_params func_init = {0}; 2013 u16 flags = 0; 2014 int i; 2015 2016 /* the sb resources are initialized at this point, do the 2017 * FW/HW initializations 2018 */ 2019 for_each_vf_sb(vf, i) 2020 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true, 2021 vf_igu_sb(vf, i), vf_igu_sb(vf, i)); 2022 2023 /* Sanity checks */ 2024 if (vf->state != VF_ACQUIRED) { 2025 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", 2026 vf->abs_vfid, vf->state); 2027 return -EINVAL; 2028 } 2029 2030 /* let FLR complete ... */ 2031 msleep(100); 2032 2033 /* FLR cleanup epilogue */ 2034 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid)) 2035 return -EBUSY; 2036 2037 /* reset IGU VF statistics: MSIX */ 2038 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0); 2039 2040 /* vf init */ 2041 if (vf->cfg_flags & VF_CFG_STATS) 2042 flags |= (FUNC_FLG_STATS | FUNC_FLG_SPQ); 2043 2044 if (vf->cfg_flags & VF_CFG_TPA) 2045 flags |= FUNC_FLG_TPA; 2046 2047 if (is_vf_multi(vf)) 2048 flags |= FUNC_FLG_RSS; 2049 2050 /* function setup */ 2051 func_init.func_flgs = flags; 2052 func_init.pf_id = BP_FUNC(bp); 2053 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid); 2054 func_init.fw_stat_map = vf->fw_stat_map; 2055 func_init.spq_map = vf->spq_map; 2056 func_init.spq_prod = 0; 2057 bnx2x_func_init(bp, &func_init); 2058 2059 /* Enable the vf */ 2060 bnx2x_vf_enable_access(bp, vf->abs_vfid); 2061 bnx2x_vf_enable_traffic(bp, vf); 2062 2063 /* queue protection table */ 2064 for_each_vfq(vf, i) 2065 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2066 vfq_qzone_id(vf, vfq_get(vf, i)), true); 2067 2068 vf->state = VF_ENABLED; 2069 2070 /* update vf bulletin board */ 2071 bnx2x_post_vf_bulletin(bp, vf->index); 2072 2073 return 0; 2074 } 2075 2076 struct set_vf_state_cookie { 2077 struct bnx2x_virtf *vf; 2078 u8 state; 2079 }; 2080 2081 static void bnx2x_set_vf_state(void *cookie) 2082 { 2083 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie; 2084 2085 p->vf->state = p->state; 2086 } 2087 2088 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf) 2089 { 2090 int rc = 0, i; 2091 2092 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2093 2094 /* Close all queues */ 2095 for (i = 0; i < vf_rxq_count(vf); i++) { 2096 rc = bnx2x_vf_queue_teardown(bp, vf, i); 2097 if (rc) 2098 goto op_err; 2099 } 2100 2101 /* disable the interrupts */ 2102 DP(BNX2X_MSG_IOV, "disabling igu\n"); 2103 bnx2x_vf_igu_disable(bp, vf); 2104 2105 /* disable the VF */ 2106 DP(BNX2X_MSG_IOV, "clearing qtbl\n"); 2107 bnx2x_vf_clr_qtbl(bp, vf); 2108 2109 /* need to make sure there are no outstanding stats ramrods which may 2110 * cause the device to access the VF's stats buffer which it will free 2111 * as soon as we return from the close flow. 2112 */ 2113 { 2114 struct set_vf_state_cookie cookie; 2115 2116 cookie.vf = vf; 2117 cookie.state = VF_ACQUIRED; 2118 bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie); 2119 } 2120 2121 DP(BNX2X_MSG_IOV, "set state to acquired\n"); 2122 2123 return 0; 2124 op_err: 2125 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc); 2126 return rc; 2127 } 2128 2129 /* VF release can be called either: 1. The VF was acquired but 2130 * not enabled 2. the vf was enabled or in the process of being 2131 * enabled 2132 */ 2133 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf) 2134 { 2135 int rc; 2136 2137 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, 2138 vf->state == VF_FREE ? "Free" : 2139 vf->state == VF_ACQUIRED ? "Acquired" : 2140 vf->state == VF_ENABLED ? "Enabled" : 2141 vf->state == VF_RESET ? "Reset" : 2142 "Unknown"); 2143 2144 switch (vf->state) { 2145 case VF_ENABLED: 2146 rc = bnx2x_vf_close(bp, vf); 2147 if (rc) 2148 goto op_err; 2149 /* Fallthrough to release resources */ 2150 case VF_ACQUIRED: 2151 DP(BNX2X_MSG_IOV, "about to free resources\n"); 2152 bnx2x_vf_free_resc(bp, vf); 2153 break; 2154 2155 case VF_FREE: 2156 case VF_RESET: 2157 default: 2158 break; 2159 } 2160 return 0; 2161 op_err: 2162 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc); 2163 return rc; 2164 } 2165 2166 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2167 struct bnx2x_config_rss_params *rss) 2168 { 2169 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2170 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags); 2171 return bnx2x_config_rss(bp, rss); 2172 } 2173 2174 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2175 struct vfpf_tpa_tlv *tlv, 2176 struct bnx2x_queue_update_tpa_params *params) 2177 { 2178 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr; 2179 struct bnx2x_queue_state_params qstate; 2180 int qid, rc = 0; 2181 2182 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2183 2184 /* Set ramrod params */ 2185 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 2186 memcpy(&qstate.params.update_tpa, params, 2187 sizeof(struct bnx2x_queue_update_tpa_params)); 2188 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA; 2189 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 2190 2191 for (qid = 0; qid < vf_rxq_count(vf); qid++) { 2192 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 2193 qstate.params.update_tpa.sge_map = sge_addr[qid]; 2194 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", 2195 vf->abs_vfid, qid, U64_HI(sge_addr[qid]), 2196 U64_LO(sge_addr[qid])); 2197 rc = bnx2x_queue_state_change(bp, &qstate); 2198 if (rc) { 2199 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n", 2200 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]), 2201 vf->abs_vfid, qid); 2202 return rc; 2203 } 2204 } 2205 2206 return rc; 2207 } 2208 2209 /* VF release ~ VF close + VF release-resources 2210 * Release is the ultimate SW shutdown and is called whenever an 2211 * irrecoverable error is encountered. 2212 */ 2213 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf) 2214 { 2215 int rc; 2216 2217 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); 2218 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2219 2220 rc = bnx2x_vf_free(bp, vf); 2221 if (rc) 2222 WARN(rc, 2223 "VF[%d] Failed to allocate resources for release op- rc=%d\n", 2224 vf->abs_vfid, rc); 2225 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2226 return rc; 2227 } 2228 2229 static inline void bnx2x_vf_get_sbdf(struct bnx2x *bp, 2230 struct bnx2x_virtf *vf, u32 *sbdf) 2231 { 2232 *sbdf = vf->devfn | (vf->bus << 8); 2233 } 2234 2235 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2236 enum channel_tlvs tlv) 2237 { 2238 /* we don't lock the channel for unsupported tlvs */ 2239 if (!bnx2x_tlv_supported(tlv)) { 2240 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n"); 2241 return; 2242 } 2243 2244 /* lock the channel */ 2245 mutex_lock(&vf->op_mutex); 2246 2247 /* record the locking op */ 2248 vf->op_current = tlv; 2249 2250 /* log the lock */ 2251 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", 2252 vf->abs_vfid, tlv); 2253 } 2254 2255 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2256 enum channel_tlvs expected_tlv) 2257 { 2258 enum channel_tlvs current_tlv; 2259 2260 if (!vf) { 2261 BNX2X_ERR("VF was %p\n", vf); 2262 return; 2263 } 2264 2265 current_tlv = vf->op_current; 2266 2267 /* we don't unlock the channel for unsupported tlvs */ 2268 if (!bnx2x_tlv_supported(expected_tlv)) 2269 return; 2270 2271 WARN(expected_tlv != vf->op_current, 2272 "lock mismatch: expected %d found %d", expected_tlv, 2273 vf->op_current); 2274 2275 /* record the locking op */ 2276 vf->op_current = CHANNEL_TLV_NONE; 2277 2278 /* lock the channel */ 2279 mutex_unlock(&vf->op_mutex); 2280 2281 /* log the unlock */ 2282 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", 2283 vf->abs_vfid, vf->op_current); 2284 } 2285 2286 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable) 2287 { 2288 struct bnx2x_queue_state_params q_params; 2289 u32 prev_flags; 2290 int i, rc; 2291 2292 /* Verify changes are needed and record current Tx switching state */ 2293 prev_flags = bp->flags; 2294 if (enable) 2295 bp->flags |= TX_SWITCHING; 2296 else 2297 bp->flags &= ~TX_SWITCHING; 2298 if (prev_flags == bp->flags) 2299 return 0; 2300 2301 /* Verify state enables the sending of queue ramrods */ 2302 if ((bp->state != BNX2X_STATE_OPEN) || 2303 (bnx2x_get_q_logical_state(bp, 2304 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) != 2305 BNX2X_Q_LOGICAL_STATE_ACTIVE)) 2306 return 0; 2307 2308 /* send q. update ramrod to configure Tx switching */ 2309 memset(&q_params, 0, sizeof(q_params)); 2310 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2311 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2312 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 2313 &q_params.params.update.update_flags); 2314 if (enable) 2315 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2316 &q_params.params.update.update_flags); 2317 else 2318 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2319 &q_params.params.update.update_flags); 2320 2321 /* send the ramrod on all the queues of the PF */ 2322 for_each_eth_queue(bp, i) { 2323 struct bnx2x_fastpath *fp = &bp->fp[i]; 2324 2325 /* Set the appropriate Queue object */ 2326 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 2327 2328 /* Update the Queue state */ 2329 rc = bnx2x_queue_state_change(bp, &q_params); 2330 if (rc) { 2331 BNX2X_ERR("Failed to configure Tx switching\n"); 2332 return rc; 2333 } 2334 } 2335 2336 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled"); 2337 return 0; 2338 } 2339 2340 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) 2341 { 2342 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); 2343 2344 if (!IS_SRIOV(bp)) { 2345 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); 2346 return -EINVAL; 2347 } 2348 2349 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", 2350 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2351 2352 /* HW channel is only operational when PF is up */ 2353 if (bp->state != BNX2X_STATE_OPEN) { 2354 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n"); 2355 return -EINVAL; 2356 } 2357 2358 /* we are always bound by the total_vfs in the configuration space */ 2359 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { 2360 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", 2361 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2362 num_vfs_param = BNX2X_NR_VIRTFN(bp); 2363 } 2364 2365 bp->requested_nr_virtfn = num_vfs_param; 2366 if (num_vfs_param == 0) { 2367 bnx2x_set_pf_tx_switching(bp, false); 2368 pci_disable_sriov(dev); 2369 return 0; 2370 } else { 2371 return bnx2x_enable_sriov(bp); 2372 } 2373 } 2374 2375 #define IGU_ENTRY_SIZE 4 2376 2377 int bnx2x_enable_sriov(struct bnx2x *bp) 2378 { 2379 int rc = 0, req_vfs = bp->requested_nr_virtfn; 2380 int vf_idx, sb_idx, vfq_idx, qcount, first_vf; 2381 u32 igu_entry, address; 2382 u16 num_vf_queues; 2383 2384 if (req_vfs == 0) 2385 return 0; 2386 2387 first_vf = bp->vfdb->sriov.first_vf_in_pf; 2388 2389 /* statically distribute vf sb pool between VFs */ 2390 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES, 2391 BP_VFDB(bp)->vf_sbs_pool / req_vfs); 2392 2393 /* zero previous values learned from igu cam */ 2394 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) { 2395 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2396 2397 vf->sb_count = 0; 2398 vf_sb_count(BP_VF(bp, vf_idx)) = 0; 2399 } 2400 bp->vfdb->vf_sbs_pool = 0; 2401 2402 /* prepare IGU cam */ 2403 sb_idx = BP_VFDB(bp)->first_vf_igu_entry; 2404 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE; 2405 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2406 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) { 2407 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT | 2408 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT | 2409 IGU_REG_MAPPING_MEMORY_VALID; 2410 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", 2411 sb_idx, vf_idx); 2412 REG_WR(bp, address, igu_entry); 2413 sb_idx++; 2414 address += IGU_ENTRY_SIZE; 2415 } 2416 } 2417 2418 /* Reinitialize vf database according to igu cam */ 2419 bnx2x_get_vf_igu_cam_info(bp); 2420 2421 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", 2422 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues); 2423 2424 qcount = 0; 2425 for_each_vf(bp, vf_idx) { 2426 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2427 2428 /* set local queue arrays */ 2429 vf->vfqs = &bp->vfdb->vfqs[qcount]; 2430 qcount += vf_sb_count(vf); 2431 bnx2x_iov_static_resc(bp, vf); 2432 } 2433 2434 /* prepare msix vectors in VF configuration space - the value in the 2435 * PCI configuration space should be the index of the last entry, 2436 * namely one less than the actual size of the table 2437 */ 2438 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2439 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); 2440 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, 2441 num_vf_queues - 1); 2442 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n", 2443 vf_idx, num_vf_queues - 1); 2444 } 2445 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2446 2447 /* enable sriov. This will probe all the VFs, and consequentially cause 2448 * the "acquire" messages to appear on the VF PF channel. 2449 */ 2450 DP(BNX2X_MSG_IOV, "about to call enable sriov\n"); 2451 bnx2x_disable_sriov(bp); 2452 2453 rc = bnx2x_set_pf_tx_switching(bp, true); 2454 if (rc) 2455 return rc; 2456 2457 rc = pci_enable_sriov(bp->pdev, req_vfs); 2458 if (rc) { 2459 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); 2460 return rc; 2461 } 2462 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); 2463 return req_vfs; 2464 } 2465 2466 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) 2467 { 2468 int vfidx; 2469 struct pf_vf_bulletin_content *bulletin; 2470 2471 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); 2472 for_each_vf(bp, vfidx) { 2473 bulletin = BP_VF_BULLETIN(bp, vfidx); 2474 if (BP_VF(bp, vfidx)->cfg_flags & VF_CFG_VLAN) 2475 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0); 2476 } 2477 } 2478 2479 void bnx2x_disable_sriov(struct bnx2x *bp) 2480 { 2481 pci_disable_sriov(bp->pdev); 2482 } 2483 2484 static int bnx2x_vf_ndo_prep(struct bnx2x *bp, int vfidx, 2485 struct bnx2x_virtf **vf, 2486 struct pf_vf_bulletin_content **bulletin) 2487 { 2488 if (bp->state != BNX2X_STATE_OPEN) { 2489 BNX2X_ERR("vf ndo called though PF is down\n"); 2490 return -EINVAL; 2491 } 2492 2493 if (!IS_SRIOV(bp)) { 2494 BNX2X_ERR("vf ndo called though sriov is disabled\n"); 2495 return -EINVAL; 2496 } 2497 2498 if (vfidx >= BNX2X_NR_VIRTFN(bp)) { 2499 BNX2X_ERR("vf ndo called for uninitialized VF. vfidx was %d BNX2X_NR_VIRTFN was %d\n", 2500 vfidx, BNX2X_NR_VIRTFN(bp)); 2501 return -EINVAL; 2502 } 2503 2504 /* init members */ 2505 *vf = BP_VF(bp, vfidx); 2506 *bulletin = BP_VF_BULLETIN(bp, vfidx); 2507 2508 if (!*vf) { 2509 BNX2X_ERR("vf ndo called but vf struct is null. vfidx was %d\n", 2510 vfidx); 2511 return -EINVAL; 2512 } 2513 2514 if (!(*vf)->vfqs) { 2515 BNX2X_ERR("vf ndo called but vfqs struct is null. Was ndo invoked before dynamically enabling SR-IOV? vfidx was %d\n", 2516 vfidx); 2517 return -EINVAL; 2518 } 2519 2520 if (!*bulletin) { 2521 BNX2X_ERR("vf ndo called but Bulletin Board struct is null. vfidx was %d\n", 2522 vfidx); 2523 return -EINVAL; 2524 } 2525 2526 return 0; 2527 } 2528 2529 int bnx2x_get_vf_config(struct net_device *dev, int vfidx, 2530 struct ifla_vf_info *ivi) 2531 { 2532 struct bnx2x *bp = netdev_priv(dev); 2533 struct bnx2x_virtf *vf = NULL; 2534 struct pf_vf_bulletin_content *bulletin = NULL; 2535 struct bnx2x_vlan_mac_obj *mac_obj; 2536 struct bnx2x_vlan_mac_obj *vlan_obj; 2537 int rc; 2538 2539 /* sanity and init */ 2540 rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin); 2541 if (rc) 2542 return rc; 2543 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2544 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2545 if (!mac_obj || !vlan_obj) { 2546 BNX2X_ERR("VF partially initialized\n"); 2547 return -EINVAL; 2548 } 2549 2550 ivi->vf = vfidx; 2551 ivi->qos = 0; 2552 ivi->tx_rate = 10000; /* always 10G. TBA take from link struct */ 2553 ivi->spoofchk = 1; /*always enabled */ 2554 if (vf->state == VF_ENABLED) { 2555 /* mac and vlan are in vlan_mac objects */ 2556 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) { 2557 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, 2558 0, ETH_ALEN); 2559 vlan_obj->get_n_elements(bp, vlan_obj, 1, 2560 (u8 *)&ivi->vlan, 0, 2561 VLAN_HLEN); 2562 } 2563 } else { 2564 /* mac */ 2565 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) 2566 /* mac configured by ndo so its in bulletin board */ 2567 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); 2568 else 2569 /* function has not been loaded yet. Show mac as 0s */ 2570 memset(&ivi->mac, 0, ETH_ALEN); 2571 2572 /* vlan */ 2573 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2574 /* vlan configured by ndo so its in bulletin board */ 2575 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); 2576 else 2577 /* function has not been loaded yet. Show vlans as 0s */ 2578 memset(&ivi->vlan, 0, VLAN_HLEN); 2579 } 2580 2581 return 0; 2582 } 2583 2584 /* New mac for VF. Consider these cases: 2585 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and 2586 * supply at acquire. 2587 * 2. VF has already been acquired but has not yet initialized - store in local 2588 * bulletin board. mac will be posted on VF bulletin board after VF init. VF 2589 * will configure this mac when it is ready. 2590 * 3. VF has already initialized but has not yet setup a queue - post the new 2591 * mac on VF's bulletin board right now. VF will configure this mac when it 2592 * is ready. 2593 * 4. VF has already set a queue - delete any macs already configured for this 2594 * queue and manually config the new mac. 2595 * In any event, once this function has been called refuse any attempts by the 2596 * VF to configure any mac for itself except for this mac. In case of a race 2597 * where the VF fails to see the new post on its bulletin board before sending a 2598 * mac configuration request, the PF will simply fail the request and VF can try 2599 * again after consulting its bulletin board. 2600 */ 2601 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) 2602 { 2603 struct bnx2x *bp = netdev_priv(dev); 2604 int rc, q_logical_state; 2605 struct bnx2x_virtf *vf = NULL; 2606 struct pf_vf_bulletin_content *bulletin = NULL; 2607 2608 /* sanity and init */ 2609 rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin); 2610 if (rc) 2611 return rc; 2612 if (!is_valid_ether_addr(mac)) { 2613 BNX2X_ERR("mac address invalid\n"); 2614 return -EINVAL; 2615 } 2616 2617 /* update PF's copy of the VF's bulletin. Will no longer accept mac 2618 * configuration requests from vf unless match this mac 2619 */ 2620 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID; 2621 memcpy(bulletin->mac, mac, ETH_ALEN); 2622 2623 /* Post update on VF's bulletin board */ 2624 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2625 if (rc) { 2626 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2627 return rc; 2628 } 2629 2630 q_logical_state = 2631 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)); 2632 if (vf->state == VF_ENABLED && 2633 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { 2634 /* configure the mac in device on this vf's queue */ 2635 unsigned long ramrod_flags = 0; 2636 struct bnx2x_vlan_mac_obj *mac_obj; 2637 2638 /* User should be able to see failure reason in system logs */ 2639 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2640 return -EINVAL; 2641 2642 /* must lock vfpf channel to protect against vf flows */ 2643 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2644 2645 /* remove existing eth macs */ 2646 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2647 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true); 2648 if (rc) { 2649 BNX2X_ERR("failed to delete eth macs\n"); 2650 rc = -EINVAL; 2651 goto out; 2652 } 2653 2654 /* remove existing uc list macs */ 2655 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true); 2656 if (rc) { 2657 BNX2X_ERR("failed to delete uc_list macs\n"); 2658 rc = -EINVAL; 2659 goto out; 2660 } 2661 2662 /* configure the new mac to device */ 2663 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2664 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, 2665 BNX2X_ETH_MAC, &ramrod_flags); 2666 2667 out: 2668 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2669 } 2670 2671 return 0; 2672 } 2673 2674 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos) 2675 { 2676 struct bnx2x_queue_state_params q_params = {NULL}; 2677 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 2678 struct bnx2x_queue_update_params *update_params; 2679 struct pf_vf_bulletin_content *bulletin = NULL; 2680 struct bnx2x_rx_mode_ramrod_params rx_ramrod; 2681 struct bnx2x *bp = netdev_priv(dev); 2682 struct bnx2x_vlan_mac_obj *vlan_obj; 2683 unsigned long vlan_mac_flags = 0; 2684 unsigned long ramrod_flags = 0; 2685 struct bnx2x_virtf *vf = NULL; 2686 unsigned long accept_flags; 2687 int rc; 2688 2689 /* sanity and init */ 2690 rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin); 2691 if (rc) 2692 return rc; 2693 2694 if (vlan > 4095) { 2695 BNX2X_ERR("illegal vlan value %d\n", vlan); 2696 return -EINVAL; 2697 } 2698 2699 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", 2700 vfidx, vlan, 0); 2701 2702 /* update PF's copy of the VF's bulletin. No point in posting the vlan 2703 * to the VF since it doesn't have anything to do with it. But it useful 2704 * to store it here in case the VF is not up yet and we can only 2705 * configure the vlan later when it does. Treat vlan id 0 as remove the 2706 * Host tag. 2707 */ 2708 if (vlan > 0) 2709 bulletin->valid_bitmap |= 1 << VLAN_VALID; 2710 else 2711 bulletin->valid_bitmap &= ~(1 << VLAN_VALID); 2712 bulletin->vlan = vlan; 2713 2714 /* is vf initialized and queue set up? */ 2715 if (vf->state != VF_ENABLED || 2716 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) != 2717 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2718 return rc; 2719 2720 /* User should be able to see error in system logs */ 2721 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2722 return -EINVAL; 2723 2724 /* must lock vfpf channel to protect against vf flows */ 2725 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2726 2727 /* remove existing vlans */ 2728 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2729 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2730 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, 2731 &ramrod_flags); 2732 if (rc) { 2733 BNX2X_ERR("failed to delete vlans\n"); 2734 rc = -EINVAL; 2735 goto out; 2736 } 2737 2738 /* need to remove/add the VF's accept_any_vlan bit */ 2739 accept_flags = bnx2x_leading_vfq(vf, accept_flags); 2740 if (vlan) 2741 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2742 else 2743 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2744 2745 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf, 2746 accept_flags); 2747 bnx2x_leading_vfq(vf, accept_flags) = accept_flags; 2748 bnx2x_config_rx_mode(bp, &rx_ramrod); 2749 2750 /* configure the new vlan to device */ 2751 memset(&ramrod_param, 0, sizeof(ramrod_param)); 2752 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2753 ramrod_param.vlan_mac_obj = vlan_obj; 2754 ramrod_param.ramrod_flags = ramrod_flags; 2755 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 2756 &ramrod_param.user_req.vlan_mac_flags); 2757 ramrod_param.user_req.u.vlan.vlan = vlan; 2758 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 2759 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 2760 if (rc) { 2761 BNX2X_ERR("failed to configure vlan\n"); 2762 rc = -EINVAL; 2763 goto out; 2764 } 2765 2766 /* send queue update ramrod to configure default vlan and silent 2767 * vlan removal 2768 */ 2769 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2770 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2771 q_params.q_obj = &bnx2x_leading_vfq(vf, sp_obj); 2772 update_params = &q_params.params.update; 2773 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 2774 &update_params->update_flags); 2775 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 2776 &update_params->update_flags); 2777 if (vlan == 0) { 2778 /* if vlan is 0 then we want to leave the VF traffic 2779 * untagged, and leave the incoming traffic untouched 2780 * (i.e. do not remove any vlan tags). 2781 */ 2782 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2783 &update_params->update_flags); 2784 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2785 &update_params->update_flags); 2786 } else { 2787 /* configure default vlan to vf queue and set silent 2788 * vlan removal (the vf remains unaware of this vlan). 2789 */ 2790 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2791 &update_params->update_flags); 2792 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2793 &update_params->update_flags); 2794 update_params->def_vlan = vlan; 2795 update_params->silent_removal_value = 2796 vlan & VLAN_VID_MASK; 2797 update_params->silent_removal_mask = VLAN_VID_MASK; 2798 } 2799 2800 /* Update the Queue state */ 2801 rc = bnx2x_queue_state_change(bp, &q_params); 2802 if (rc) { 2803 BNX2X_ERR("Failed to configure default VLAN\n"); 2804 goto out; 2805 } 2806 2807 2808 /* clear the flag indicating that this VF needs its vlan 2809 * (will only be set if the HV configured the Vlan before vf was 2810 * up and we were called because the VF came up later 2811 */ 2812 out: 2813 vf->cfg_flags &= ~VF_CFG_VLAN; 2814 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2815 2816 return rc; 2817 } 2818 2819 /* crc is the first field in the bulletin board. Compute the crc over the 2820 * entire bulletin board excluding the crc field itself. Use the length field 2821 * as the Bulletin Board was posted by a PF with possibly a different version 2822 * from the vf which will sample it. Therefore, the length is computed by the 2823 * PF and the used blindly by the VF. 2824 */ 2825 u32 bnx2x_crc_vf_bulletin(struct bnx2x *bp, 2826 struct pf_vf_bulletin_content *bulletin) 2827 { 2828 return crc32(BULLETIN_CRC_SEED, 2829 ((u8 *)bulletin) + sizeof(bulletin->crc), 2830 bulletin->length - sizeof(bulletin->crc)); 2831 } 2832 2833 /* Check for new posts on the bulletin board */ 2834 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) 2835 { 2836 struct pf_vf_bulletin_content bulletin = bp->pf2vf_bulletin->content; 2837 int attempts; 2838 2839 /* bulletin board hasn't changed since last sample */ 2840 if (bp->old_bulletin.version == bulletin.version) 2841 return PFVF_BULLETIN_UNCHANGED; 2842 2843 /* validate crc of new bulletin board */ 2844 if (bp->old_bulletin.version != bp->pf2vf_bulletin->content.version) { 2845 /* sampling structure in mid post may result with corrupted data 2846 * validate crc to ensure coherency. 2847 */ 2848 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) { 2849 bulletin = bp->pf2vf_bulletin->content; 2850 if (bulletin.crc == bnx2x_crc_vf_bulletin(bp, 2851 &bulletin)) 2852 break; 2853 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n", 2854 bulletin.crc, 2855 bnx2x_crc_vf_bulletin(bp, &bulletin)); 2856 } 2857 if (attempts >= BULLETIN_ATTEMPTS) { 2858 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n", 2859 attempts); 2860 return PFVF_BULLETIN_CRC_ERR; 2861 } 2862 } 2863 2864 /* the mac address in bulletin board is valid and is new */ 2865 if (bulletin.valid_bitmap & 1 << MAC_ADDR_VALID && 2866 !ether_addr_equal(bulletin.mac, bp->old_bulletin.mac)) { 2867 /* update new mac to net device */ 2868 memcpy(bp->dev->dev_addr, bulletin.mac, ETH_ALEN); 2869 } 2870 2871 /* the vlan in bulletin board is valid and is new */ 2872 if (bulletin.valid_bitmap & 1 << VLAN_VALID) 2873 memcpy(&bulletin.vlan, &bp->old_bulletin.vlan, VLAN_HLEN); 2874 2875 /* copy new bulletin board to bp */ 2876 bp->old_bulletin = bulletin; 2877 2878 return PFVF_BULLETIN_UPDATED; 2879 } 2880 2881 void bnx2x_timer_sriov(struct bnx2x *bp) 2882 { 2883 bnx2x_sample_bulletin(bp); 2884 2885 /* if channel is down we need to self destruct */ 2886 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) 2887 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 2888 BNX2X_MSG_IOV); 2889 } 2890 2891 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) 2892 { 2893 /* vf doorbells are embedded within the regview */ 2894 return bp->regview + PXP_VF_ADDR_DB_START; 2895 } 2896 2897 int bnx2x_vf_pci_alloc(struct bnx2x *bp) 2898 { 2899 mutex_init(&bp->vf2pf_mutex); 2900 2901 /* allocate vf2pf mailbox for vf to pf channel */ 2902 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping, 2903 sizeof(struct bnx2x_vf_mbx_msg)); 2904 if (!bp->vf2pf_mbox) 2905 goto alloc_mem_err; 2906 2907 /* allocate pf 2 vf bulletin board */ 2908 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping, 2909 sizeof(union pf_vf_bulletin)); 2910 if (!bp->pf2vf_bulletin) 2911 goto alloc_mem_err; 2912 2913 return 0; 2914 2915 alloc_mem_err: 2916 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, 2917 sizeof(struct bnx2x_vf_mbx_msg)); 2918 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping, 2919 sizeof(union pf_vf_bulletin)); 2920 return -ENOMEM; 2921 } 2922 2923 void bnx2x_iov_channel_down(struct bnx2x *bp) 2924 { 2925 int vf_idx; 2926 struct pf_vf_bulletin_content *bulletin; 2927 2928 if (!IS_SRIOV(bp)) 2929 return; 2930 2931 for_each_vf(bp, vf_idx) { 2932 /* locate this VFs bulletin board and update the channel down 2933 * bit 2934 */ 2935 bulletin = BP_VF_BULLETIN(bp, vf_idx); 2936 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN; 2937 2938 /* update vf bulletin board */ 2939 bnx2x_post_vf_bulletin(bp, vf_idx); 2940 } 2941 } 2942 2943 void bnx2x_iov_task(struct work_struct *work) 2944 { 2945 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work); 2946 2947 if (!netif_running(bp->dev)) 2948 return; 2949 2950 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR, 2951 &bp->iov_task_state)) 2952 bnx2x_vf_handle_flr_event(bp); 2953 2954 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG, 2955 &bp->iov_task_state)) 2956 bnx2x_vf_mbx(bp); 2957 } 2958 2959 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) 2960 { 2961 smp_mb__before_clear_bit(); 2962 set_bit(flag, &bp->iov_task_state); 2963 smp_mb__after_clear_bit(); 2964 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); 2965 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0); 2966 } 2967