1 /* bnx2x_sriov.c: QLogic Everest network driver. 2 * 3 * Copyright 2009-2013 Broadcom Corporation 4 * Copyright 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * Unless you and QLogic execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2, available 10 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 11 * 12 * Notwithstanding the above, under no circumstances may you combine this 13 * software in any way with any other QLogic software provided under a 14 * license other than the GPL, without QLogic's express prior written 15 * consent. 16 * 17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 18 * Written by: Shmulik Ravid 19 * Ariel Elior <ariel.elior@qlogic.com> 20 * 21 */ 22 #include "bnx2x.h" 23 #include "bnx2x_init.h" 24 #include "bnx2x_cmn.h" 25 #include "bnx2x_sp.h" 26 #include <linux/crc32.h> 27 #include <linux/if_vlan.h> 28 29 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 30 struct bnx2x_virtf **vf, 31 struct pf_vf_bulletin_content **bulletin, 32 bool test_queue); 33 34 /* General service functions */ 35 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 36 u16 pf_id) 37 { 38 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 39 pf_id); 40 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 41 pf_id); 42 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 43 pf_id); 44 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 45 pf_id); 46 } 47 48 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 49 u8 enable) 50 { 51 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 52 enable); 53 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 54 enable); 55 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 56 enable); 57 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 58 enable); 59 } 60 61 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 62 { 63 int idx; 64 65 for_each_vf(bp, idx) 66 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid) 67 break; 68 return idx; 69 } 70 71 static 72 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 73 { 74 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid); 75 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL; 76 } 77 78 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf, 79 u8 igu_sb_id, u8 segment, u16 index, u8 op, 80 u8 update) 81 { 82 /* acking a VF sb through the PF - use the GRC */ 83 u32 ctl; 84 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 85 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 86 u32 func_encode = vf->abs_vfid; 87 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id; 88 struct igu_regular cmd_data = {0}; 89 90 cmd_data.sb_id_and_flags = 91 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 92 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 93 (update << IGU_REGULAR_BUPDATE_SHIFT) | 94 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 95 96 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 97 func_encode << IGU_CTRL_REG_FID_SHIFT | 98 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 99 100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 101 cmd_data.sb_id_and_flags, igu_addr_data); 102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); 103 mmiowb(); 104 barrier(); 105 106 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 107 ctl, igu_addr_ctl); 108 REG_WR(bp, igu_addr_ctl, ctl); 109 mmiowb(); 110 barrier(); 111 } 112 113 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp, 114 struct bnx2x_virtf *vf, 115 bool print_err) 116 { 117 if (!bnx2x_leading_vfq(vf, sp_initialized)) { 118 if (print_err) 119 BNX2X_ERR("Slowpath objects not yet initialized!\n"); 120 else 121 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); 122 return false; 123 } 124 return true; 125 } 126 127 /* VFOP operations states */ 128 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf, 129 struct bnx2x_queue_init_params *init_params, 130 struct bnx2x_queue_setup_params *setup_params, 131 u16 q_idx, u16 sb_idx) 132 { 133 DP(BNX2X_MSG_IOV, 134 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", 135 vf->abs_vfid, 136 q_idx, 137 sb_idx, 138 init_params->tx.sb_cq_index, 139 init_params->tx.hc_rate, 140 setup_params->flags, 141 setup_params->txq_params.traffic_type); 142 } 143 144 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf, 145 struct bnx2x_queue_init_params *init_params, 146 struct bnx2x_queue_setup_params *setup_params, 147 u16 q_idx, u16 sb_idx) 148 { 149 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params; 150 151 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" 152 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n", 153 vf->abs_vfid, 154 q_idx, 155 sb_idx, 156 init_params->rx.sb_cq_index, 157 init_params->rx.hc_rate, 158 setup_params->gen_params.mtu, 159 rxq_params->buf_sz, 160 rxq_params->sge_buf_sz, 161 rxq_params->max_sges_pkt, 162 rxq_params->tpa_agg_sz, 163 setup_params->flags, 164 rxq_params->drop_flags, 165 rxq_params->cache_line_log); 166 } 167 168 void bnx2x_vfop_qctor_prep(struct bnx2x *bp, 169 struct bnx2x_virtf *vf, 170 struct bnx2x_vf_queue *q, 171 struct bnx2x_vf_queue_construct_params *p, 172 unsigned long q_type) 173 { 174 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init; 175 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup; 176 177 /* INIT */ 178 179 /* Enable host coalescing in the transition to INIT state */ 180 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags)) 181 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags); 182 183 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags)) 184 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags); 185 186 /* FW SB ID */ 187 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 188 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 189 190 /* context */ 191 init_p->cxts[0] = q->cxt; 192 193 /* SETUP */ 194 195 /* Setup-op general parameters */ 196 setup_p->gen_params.spcl_id = vf->sp_cl_id; 197 setup_p->gen_params.stat_id = vfq_stat_id(vf, q); 198 setup_p->gen_params.fp_hsi = vf->fp_hsi; 199 200 /* Setup-op pause params: 201 * Nothing to do, the pause thresholds are set by default to 0 which 202 * effectively turns off the feature for this queue. We don't want 203 * one queue (VF) to interfering with another queue (another VF) 204 */ 205 if (vf->cfg_flags & VF_CFG_FW_FC) 206 BNX2X_ERR("No support for pause to VFs (abs_vfid: %d)\n", 207 vf->abs_vfid); 208 /* Setup-op flags: 209 * collect statistics, zero statistics, local-switching, security, 210 * OV for Flex10, RSS and MCAST for leading 211 */ 212 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags)) 213 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags); 214 215 /* for VFs, enable tx switching, bd coherency, and mac address 216 * anti-spoofing 217 */ 218 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags); 219 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags); 220 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags); 221 222 /* Setup-op rx parameters */ 223 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) { 224 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params; 225 226 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q); 227 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx); 228 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid); 229 230 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags)) 231 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES; 232 } 233 234 /* Setup-op tx parameters */ 235 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) { 236 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss; 237 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 238 } 239 } 240 241 static int bnx2x_vf_queue_create(struct bnx2x *bp, 242 struct bnx2x_virtf *vf, int qid, 243 struct bnx2x_vf_queue_construct_params *qctor) 244 { 245 struct bnx2x_queue_state_params *q_params; 246 int rc = 0; 247 248 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 249 250 /* Prepare ramrod information */ 251 q_params = &qctor->qstate; 252 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj); 253 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags); 254 255 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) == 256 BNX2X_Q_LOGICAL_STATE_ACTIVE) { 257 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); 258 goto out; 259 } 260 261 /* Run Queue 'construction' ramrods */ 262 q_params->cmd = BNX2X_Q_CMD_INIT; 263 rc = bnx2x_queue_state_change(bp, q_params); 264 if (rc) 265 goto out; 266 267 memcpy(&q_params->params.setup, &qctor->prep_qsetup, 268 sizeof(struct bnx2x_queue_setup_params)); 269 q_params->cmd = BNX2X_Q_CMD_SETUP; 270 rc = bnx2x_queue_state_change(bp, q_params); 271 if (rc) 272 goto out; 273 274 /* enable interrupts */ 275 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)), 276 USTORM_ID, 0, IGU_INT_ENABLE, 0); 277 out: 278 return rc; 279 } 280 281 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf, 282 int qid) 283 { 284 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT, 285 BNX2X_Q_CMD_TERMINATE, 286 BNX2X_Q_CMD_CFC_DEL}; 287 struct bnx2x_queue_state_params q_params; 288 int rc, i; 289 290 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 291 292 /* Prepare ramrod information */ 293 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params)); 294 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 295 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 296 297 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) == 298 BNX2X_Q_LOGICAL_STATE_STOPPED) { 299 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); 300 goto out; 301 } 302 303 /* Run Queue 'destruction' ramrods */ 304 for (i = 0; i < ARRAY_SIZE(cmds); i++) { 305 q_params.cmd = cmds[i]; 306 rc = bnx2x_queue_state_change(bp, &q_params); 307 if (rc) { 308 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]); 309 return rc; 310 } 311 } 312 out: 313 /* Clean Context */ 314 if (bnx2x_vfq(vf, qid, cxt)) { 315 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0; 316 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0; 317 } 318 319 return 0; 320 } 321 322 static void 323 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid) 324 { 325 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 326 if (vf) { 327 /* the first igu entry belonging to VFs of this PF */ 328 if (!BP_VFDB(bp)->first_vf_igu_entry) 329 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id; 330 331 /* the first igu entry belonging to this VF */ 332 if (!vf_sb_count(vf)) 333 vf->igu_base_id = igu_sb_id; 334 335 ++vf_sb_count(vf); 336 ++vf->sb_count; 337 } 338 BP_VFDB(bp)->vf_sbs_pool++; 339 } 340 341 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp, 342 struct bnx2x_vlan_mac_obj *obj, 343 atomic_t *counter) 344 { 345 struct list_head *pos; 346 int read_lock; 347 int cnt = 0; 348 349 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj); 350 if (read_lock) 351 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); 352 353 list_for_each(pos, &obj->head) 354 cnt++; 355 356 if (!read_lock) 357 bnx2x_vlan_mac_h_read_unlock(bp, obj); 358 359 atomic_set(counter, cnt); 360 } 361 362 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf, 363 int qid, bool drv_only, bool mac) 364 { 365 struct bnx2x_vlan_mac_ramrod_params ramrod; 366 int rc; 367 368 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, 369 mac ? "MACs" : "VLANs"); 370 371 /* Prepare ramrod params */ 372 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 373 if (mac) { 374 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 375 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 376 } else { 377 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 378 &ramrod.user_req.vlan_mac_flags); 379 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 380 } 381 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL; 382 383 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 384 if (drv_only) 385 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 386 else 387 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 388 389 /* Start deleting */ 390 rc = ramrod.vlan_mac_obj->delete_all(bp, 391 ramrod.vlan_mac_obj, 392 &ramrod.user_req.vlan_mac_flags, 393 &ramrod.ramrod_flags); 394 if (rc) { 395 BNX2X_ERR("Failed to delete all %s\n", 396 mac ? "MACs" : "VLANs"); 397 return rc; 398 } 399 400 /* Clear the vlan counters */ 401 if (!mac) 402 atomic_set(&bnx2x_vfq(vf, qid, vlan_count), 0); 403 404 return 0; 405 } 406 407 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp, 408 struct bnx2x_virtf *vf, int qid, 409 struct bnx2x_vf_mac_vlan_filter *filter, 410 bool drv_only) 411 { 412 struct bnx2x_vlan_mac_ramrod_params ramrod; 413 int rc; 414 415 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", 416 vf->abs_vfid, filter->add ? "Adding" : "Deleting", 417 filter->type == BNX2X_VF_FILTER_MAC ? "MAC" : "VLAN"); 418 419 /* Prepare ramrod params */ 420 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 421 if (filter->type == BNX2X_VF_FILTER_VLAN) { 422 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 423 &ramrod.user_req.vlan_mac_flags); 424 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 425 ramrod.user_req.u.vlan.vlan = filter->vid; 426 } else { 427 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 428 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 429 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 430 } 431 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD : 432 BNX2X_VLAN_MAC_DEL; 433 434 /* Verify there are available vlan credits */ 435 if (filter->add && filter->type == BNX2X_VF_FILTER_VLAN && 436 (atomic_read(&bnx2x_vfq(vf, qid, vlan_count)) >= 437 vf_vlan_rules_cnt(vf))) { 438 BNX2X_ERR("No credits for vlan [%d >= %d]\n", 439 atomic_read(&bnx2x_vfq(vf, qid, vlan_count)), 440 vf_vlan_rules_cnt(vf)); 441 return -ENOMEM; 442 } 443 444 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 445 if (drv_only) 446 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 447 else 448 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 449 450 /* Add/Remove the filter */ 451 rc = bnx2x_config_vlan_mac(bp, &ramrod); 452 if (rc && rc != -EEXIST) { 453 BNX2X_ERR("Failed to %s %s\n", 454 filter->add ? "add" : "delete", 455 filter->type == BNX2X_VF_FILTER_MAC ? "MAC" : 456 "VLAN"); 457 return rc; 458 } 459 460 /* Update the vlan counters */ 461 if (filter->type == BNX2X_VF_FILTER_VLAN) 462 bnx2x_vf_vlan_credit(bp, ramrod.vlan_mac_obj, 463 &bnx2x_vfq(vf, qid, vlan_count)); 464 465 return 0; 466 } 467 468 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf, 469 struct bnx2x_vf_mac_vlan_filters *filters, 470 int qid, bool drv_only) 471 { 472 int rc = 0, i; 473 474 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 475 476 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 477 return -EINVAL; 478 479 /* Prepare ramrod params */ 480 for (i = 0; i < filters->count; i++) { 481 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, 482 &filters->filters[i], drv_only); 483 if (rc) 484 break; 485 } 486 487 /* Rollback if needed */ 488 if (i != filters->count) { 489 BNX2X_ERR("Managed only %d/%d filters - rolling back\n", 490 i, filters->count + 1); 491 while (--i >= 0) { 492 filters->filters[i].add = !filters->filters[i].add; 493 bnx2x_vf_mac_vlan_config(bp, vf, qid, 494 &filters->filters[i], 495 drv_only); 496 } 497 } 498 499 /* It's our responsibility to free the filters */ 500 kfree(filters); 501 502 return rc; 503 } 504 505 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid, 506 struct bnx2x_vf_queue_construct_params *qctor) 507 { 508 int rc; 509 510 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 511 512 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor); 513 if (rc) 514 goto op_err; 515 516 /* Configure vlan0 for leading queue */ 517 if (!qid) { 518 struct bnx2x_vf_mac_vlan_filter filter; 519 520 memset(&filter, 0, sizeof(struct bnx2x_vf_mac_vlan_filter)); 521 filter.type = BNX2X_VF_FILTER_VLAN; 522 filter.add = true; 523 filter.vid = 0; 524 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, &filter, false); 525 if (rc) 526 goto op_err; 527 } 528 529 /* Schedule the configuration of any pending vlan filters */ 530 vf->cfg_flags |= VF_CFG_VLAN; 531 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN, 532 BNX2X_MSG_IOV); 533 return 0; 534 op_err: 535 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 536 return rc; 537 } 538 539 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf, 540 int qid) 541 { 542 int rc; 543 544 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 545 546 /* If needed, clean the filtering data base */ 547 if ((qid == LEADING_IDX) && 548 bnx2x_validate_vf_sp_objs(bp, vf, false)) { 549 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, false); 550 if (rc) 551 goto op_err; 552 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, true); 553 if (rc) 554 goto op_err; 555 } 556 557 /* Terminate queue */ 558 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) { 559 struct bnx2x_queue_state_params qstate; 560 561 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 562 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 563 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED; 564 qstate.cmd = BNX2X_Q_CMD_TERMINATE; 565 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 566 rc = bnx2x_queue_state_change(bp, &qstate); 567 if (rc) 568 goto op_err; 569 } 570 571 return 0; 572 op_err: 573 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 574 return rc; 575 } 576 577 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf, 578 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only) 579 { 580 struct bnx2x_mcast_list_elem *mc = NULL; 581 struct bnx2x_mcast_ramrod_params mcast; 582 int rc, i; 583 584 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 585 586 /* Prepare Multicast command */ 587 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params)); 588 mcast.mcast_obj = &vf->mcast_obj; 589 if (drv_only) 590 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags); 591 else 592 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags); 593 if (mc_num) { 594 mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem), 595 GFP_KERNEL); 596 if (!mc) { 597 BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n"); 598 return -ENOMEM; 599 } 600 } 601 602 /* clear existing mcasts */ 603 mcast.mcast_list_len = vf->mcast_list_len; 604 vf->mcast_list_len = mc_num; 605 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL); 606 if (rc) { 607 BNX2X_ERR("Failed to remove multicasts\n"); 608 kfree(mc); 609 return rc; 610 } 611 612 /* update mcast list on the ramrod params */ 613 if (mc_num) { 614 INIT_LIST_HEAD(&mcast.mcast_list); 615 for (i = 0; i < mc_num; i++) { 616 mc[i].mac = mcasts[i]; 617 list_add_tail(&mc[i].link, 618 &mcast.mcast_list); 619 } 620 621 /* add new mcasts */ 622 mcast.mcast_list_len = mc_num; 623 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_ADD); 624 if (rc) 625 BNX2X_ERR("Faled to add multicasts\n"); 626 kfree(mc); 627 } 628 629 return rc; 630 } 631 632 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid, 633 struct bnx2x_rx_mode_ramrod_params *ramrod, 634 struct bnx2x_virtf *vf, 635 unsigned long accept_flags) 636 { 637 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid); 638 639 memset(ramrod, 0, sizeof(*ramrod)); 640 ramrod->cid = vfq->cid; 641 ramrod->cl_id = vfq_cl_id(vf, vfq); 642 ramrod->rx_mode_obj = &bp->rx_mode_obj; 643 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid); 644 ramrod->rx_accept_flags = accept_flags; 645 ramrod->tx_accept_flags = accept_flags; 646 ramrod->pstate = &vf->filter_state; 647 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING; 648 649 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 650 set_bit(RAMROD_RX, &ramrod->ramrod_flags); 651 set_bit(RAMROD_TX, &ramrod->ramrod_flags); 652 653 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2); 654 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2); 655 } 656 657 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf, 658 int qid, unsigned long accept_flags) 659 { 660 struct bnx2x_rx_mode_ramrod_params ramrod; 661 662 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 663 664 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags); 665 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 666 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags; 667 return bnx2x_config_rx_mode(bp, &ramrod); 668 } 669 670 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid) 671 { 672 int rc; 673 674 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 675 676 /* Remove all classification configuration for leading queue */ 677 if (qid == LEADING_IDX) { 678 rc = bnx2x_vf_rxmode(bp, vf, qid, 0); 679 if (rc) 680 goto op_err; 681 682 /* Remove filtering if feasible */ 683 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) { 684 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 685 false, false); 686 if (rc) 687 goto op_err; 688 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 689 false, true); 690 if (rc) 691 goto op_err; 692 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false); 693 if (rc) 694 goto op_err; 695 } 696 } 697 698 /* Destroy queue */ 699 rc = bnx2x_vf_queue_destroy(bp, vf, qid); 700 if (rc) 701 goto op_err; 702 return rc; 703 op_err: 704 BNX2X_ERR("vf[%d:%d] error: rc %d\n", 705 vf->abs_vfid, qid, rc); 706 return rc; 707 } 708 709 /* VF enable primitives 710 * when pretend is required the caller is responsible 711 * for calling pretend prior to calling these routines 712 */ 713 714 /* internal vf enable - until vf is enabled internally all transactions 715 * are blocked. This routine should always be called last with pretend. 716 */ 717 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable) 718 { 719 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); 720 } 721 722 /* clears vf error in all semi blocks */ 723 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid) 724 { 725 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); 726 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); 727 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); 728 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); 729 } 730 731 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid) 732 { 733 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5; 734 u32 was_err_reg = 0; 735 736 switch (was_err_group) { 737 case 0: 738 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR; 739 break; 740 case 1: 741 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR; 742 break; 743 case 2: 744 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR; 745 break; 746 case 3: 747 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR; 748 break; 749 } 750 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); 751 } 752 753 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf) 754 { 755 int i; 756 u32 val; 757 758 /* Set VF masks and configuration - pretend */ 759 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 760 761 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 762 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 763 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 764 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 765 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 766 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 767 768 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 769 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); 770 if (vf->cfg_flags & VF_CFG_INT_SIMD) 771 val |= IGU_VF_CONF_SINGLE_ISR_EN; 772 val &= ~IGU_VF_CONF_PARENT_MASK; 773 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; 774 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 775 776 DP(BNX2X_MSG_IOV, 777 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n", 778 vf->abs_vfid, val); 779 780 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 781 782 /* iterate over all queues, clear sb consumer */ 783 for (i = 0; i < vf_sb_count(vf); i++) { 784 u8 igu_sb_id = vf_igu_sb(vf, i); 785 786 /* zero prod memory */ 787 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); 788 789 /* clear sb state machine */ 790 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id, 791 false /* VF */); 792 793 /* disable + update */ 794 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0, 795 IGU_INT_DISABLE, 1); 796 } 797 } 798 799 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid) 800 { 801 /* set the VF-PF association in the FW */ 802 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp)); 803 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1); 804 805 /* clear vf errors*/ 806 bnx2x_vf_semi_clear_err(bp, abs_vfid); 807 bnx2x_vf_pglue_clear_err(bp, abs_vfid); 808 809 /* internal vf-enable - pretend */ 810 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid)); 811 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); 812 bnx2x_vf_enable_internal(bp, true); 813 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 814 } 815 816 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf) 817 { 818 /* Reset vf in IGU interrupts are still disabled */ 819 bnx2x_vf_igu_reset(bp, vf); 820 821 /* pretend to enable the vf with the PBF */ 822 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 823 REG_WR(bp, PBF_REG_DISABLE_VF, 0); 824 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 825 } 826 827 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) 828 { 829 struct pci_dev *dev; 830 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 831 832 if (!vf) 833 return false; 834 835 dev = pci_get_bus_and_slot(vf->bus, vf->devfn); 836 if (dev) 837 return bnx2x_is_pcie_pending(dev); 838 return false; 839 } 840 841 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid) 842 { 843 /* Verify no pending pci transactions */ 844 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid)) 845 BNX2X_ERR("PCIE Transactions still pending\n"); 846 847 return 0; 848 } 849 850 static void bnx2x_iov_re_set_vlan_filters(struct bnx2x *bp, 851 struct bnx2x_virtf *vf, 852 int new) 853 { 854 int num = vf_vlan_rules_cnt(vf); 855 int diff = new - num; 856 bool rc = true; 857 858 DP(BNX2X_MSG_IOV, "vf[%d] - %d vlan filter credits [previously %d]\n", 859 vf->abs_vfid, new, num); 860 861 if (diff > 0) 862 rc = bp->vlans_pool.get(&bp->vlans_pool, diff); 863 else if (diff < 0) 864 rc = bp->vlans_pool.put(&bp->vlans_pool, -diff); 865 866 if (rc) 867 vf_vlan_rules_cnt(vf) = new; 868 else 869 DP(BNX2X_MSG_IOV, "vf[%d] - Failed to configure vlan filter credits change\n", 870 vf->abs_vfid); 871 } 872 873 /* must be called after the number of PF queues and the number of VFs are 874 * both known 875 */ 876 static void 877 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 878 { 879 struct vf_pf_resc_request *resc = &vf->alloc_resc; 880 u16 vlan_count = 0; 881 882 /* will be set only during VF-ACQUIRE */ 883 resc->num_rxqs = 0; 884 resc->num_txqs = 0; 885 886 /* no credit calculations for macs (just yet) */ 887 resc->num_mac_filters = 1; 888 889 /* divvy up vlan rules */ 890 bnx2x_iov_re_set_vlan_filters(bp, vf, 0); 891 vlan_count = bp->vlans_pool.check(&bp->vlans_pool); 892 vlan_count = 1 << ilog2(vlan_count); 893 bnx2x_iov_re_set_vlan_filters(bp, vf, 894 vlan_count / BNX2X_NR_VIRTFN(bp)); 895 896 /* no real limitation */ 897 resc->num_mc_filters = 0; 898 899 /* num_sbs already set */ 900 resc->num_sbs = vf->sb_count; 901 } 902 903 /* FLR routines: */ 904 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 905 { 906 /* reset the state variables */ 907 bnx2x_iov_static_resc(bp, vf); 908 vf->state = VF_FREE; 909 } 910 911 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf) 912 { 913 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 914 915 /* DQ usage counter */ 916 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 917 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT, 918 "DQ VF usage counter timed out", 919 poll_cnt); 920 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 921 922 /* FW cleanup command - poll for the results */ 923 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid), 924 poll_cnt)) 925 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid); 926 927 /* verify TX hw is flushed */ 928 bnx2x_tx_hw_flushed(bp, poll_cnt); 929 } 930 931 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf) 932 { 933 int rc, i; 934 935 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 936 937 /* the cleanup operations are valid if and only if the VF 938 * was first acquired. 939 */ 940 for (i = 0; i < vf_rxq_count(vf); i++) { 941 rc = bnx2x_vf_queue_flr(bp, vf, i); 942 if (rc) 943 goto out; 944 } 945 946 /* remove multicasts */ 947 bnx2x_vf_mcast(bp, vf, NULL, 0, true); 948 949 /* dispatch final cleanup and wait for HW queues to flush */ 950 bnx2x_vf_flr_clnup_hw(bp, vf); 951 952 /* release VF resources */ 953 bnx2x_vf_free_resc(bp, vf); 954 955 /* re-open the mailbox */ 956 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 957 return; 958 out: 959 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n", 960 vf->abs_vfid, i, rc); 961 } 962 963 static void bnx2x_vf_flr_clnup(struct bnx2x *bp) 964 { 965 struct bnx2x_virtf *vf; 966 int i; 967 968 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) { 969 /* VF should be RESET & in FLR cleanup states */ 970 if (bnx2x_vf(bp, i, state) != VF_RESET || 971 !bnx2x_vf(bp, i, flr_clnup_stage)) 972 continue; 973 974 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", 975 i, BNX2X_NR_VIRTFN(bp)); 976 977 vf = BP_VF(bp, i); 978 979 /* lock the vf pf channel */ 980 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 981 982 /* invoke the VF FLR SM */ 983 bnx2x_vf_flr(bp, vf); 984 985 /* mark the VF to be ACKED and continue */ 986 vf->flr_clnup_stage = false; 987 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 988 } 989 990 /* Acknowledge the handled VFs. 991 * we are acknowledge all the vfs which an flr was requested for, even 992 * if amongst them there are such that we never opened, since the mcp 993 * will interrupt us immediately again if we only ack some of the bits, 994 * resulting in an endless loop. This can happen for example in KVM 995 * where an 'all ones' flr request is sometimes given by hyper visor 996 */ 997 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", 998 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 999 for (i = 0; i < FLRD_VFS_DWORDS; i++) 1000 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 1001 bp->vfdb->flrd_vfs[i]); 1002 1003 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0); 1004 1005 /* clear the acked bits - better yet if the MCP implemented 1006 * write to clear semantics 1007 */ 1008 for (i = 0; i < FLRD_VFS_DWORDS; i++) 1009 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0); 1010 } 1011 1012 void bnx2x_vf_handle_flr_event(struct bnx2x *bp) 1013 { 1014 int i; 1015 1016 /* Read FLR'd VFs */ 1017 for (i = 0; i < FLRD_VFS_DWORDS; i++) 1018 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]); 1019 1020 DP(BNX2X_MSG_MCP, 1021 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n", 1022 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 1023 1024 for_each_vf(bp, i) { 1025 struct bnx2x_virtf *vf = BP_VF(bp, i); 1026 u32 reset = 0; 1027 1028 if (vf->abs_vfid < 32) 1029 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid); 1030 else 1031 reset = bp->vfdb->flrd_vfs[1] & 1032 (1 << (vf->abs_vfid - 32)); 1033 1034 if (reset) { 1035 /* set as reset and ready for cleanup */ 1036 vf->state = VF_RESET; 1037 vf->flr_clnup_stage = true; 1038 1039 DP(BNX2X_MSG_IOV, 1040 "Initiating Final cleanup for VF %d\n", 1041 vf->abs_vfid); 1042 } 1043 } 1044 1045 /* do the FLR cleanup for all marked VFs*/ 1046 bnx2x_vf_flr_clnup(bp); 1047 } 1048 1049 /* IOV global initialization routines */ 1050 void bnx2x_iov_init_dq(struct bnx2x *bp) 1051 { 1052 if (!IS_SRIOV(bp)) 1053 return; 1054 1055 /* Set the DQ such that the CID reflect the abs_vfid */ 1056 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); 1057 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 1058 1059 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to 1060 * the PF L2 queues 1061 */ 1062 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 1063 1064 /* The VF window size is the log2 of the max number of CIDs per VF */ 1065 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 1066 1067 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 1068 * the Pf doorbell size although the 2 are independent. 1069 */ 1070 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); 1071 1072 /* No security checks for now - 1073 * configure single rule (out of 16) mask = 0x1, value = 0x0, 1074 * CID range 0 - 0x1ffff 1075 */ 1076 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); 1077 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); 1078 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 1079 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 1080 1081 /* set the VF doorbell threshold. This threshold represents the amount 1082 * of doorbells allowed in the main DORQ fifo for a specific VF. 1083 */ 1084 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64); 1085 } 1086 1087 void bnx2x_iov_init_dmae(struct bnx2x *bp) 1088 { 1089 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV)) 1090 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); 1091 } 1092 1093 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid) 1094 { 1095 struct pci_dev *dev = bp->pdev; 1096 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1097 1098 return dev->bus->number + ((dev->devfn + iov->offset + 1099 iov->stride * vfid) >> 8); 1100 } 1101 1102 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid) 1103 { 1104 struct pci_dev *dev = bp->pdev; 1105 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1106 1107 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff; 1108 } 1109 1110 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf) 1111 { 1112 int i, n; 1113 struct pci_dev *dev = bp->pdev; 1114 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1115 1116 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) { 1117 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i); 1118 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i); 1119 1120 size /= iov->total; 1121 vf->bars[n].bar = start + size * vf->abs_vfid; 1122 vf->bars[n].size = size; 1123 } 1124 } 1125 1126 static int bnx2x_ari_enabled(struct pci_dev *dev) 1127 { 1128 return dev->bus->self && dev->bus->self->ari_enabled; 1129 } 1130 1131 static int 1132 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp) 1133 { 1134 int sb_id; 1135 u32 val; 1136 u8 fid, current_pf = 0; 1137 1138 /* IGU in normal mode - read CAM */ 1139 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) { 1140 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); 1141 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 1142 continue; 1143 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); 1144 if (fid & IGU_FID_ENCODE_IS_PF) 1145 current_pf = fid & IGU_FID_PF_NUM_MASK; 1146 else if (current_pf == BP_FUNC(bp)) 1147 bnx2x_vf_set_igu_info(bp, sb_id, 1148 (fid & IGU_FID_VF_NUM_MASK)); 1149 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", 1150 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"), 1151 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) : 1152 (fid & IGU_FID_VF_NUM_MASK)), sb_id, 1153 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); 1154 } 1155 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); 1156 return BP_VFDB(bp)->vf_sbs_pool; 1157 } 1158 1159 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp) 1160 { 1161 if (bp->vfdb) { 1162 kfree(bp->vfdb->vfqs); 1163 kfree(bp->vfdb->vfs); 1164 kfree(bp->vfdb); 1165 } 1166 bp->vfdb = NULL; 1167 } 1168 1169 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1170 { 1171 int pos; 1172 struct pci_dev *dev = bp->pdev; 1173 1174 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 1175 if (!pos) { 1176 BNX2X_ERR("failed to find SRIOV capability in device\n"); 1177 return -ENODEV; 1178 } 1179 1180 iov->pos = pos; 1181 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); 1182 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); 1183 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total); 1184 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial); 1185 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset); 1186 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride); 1187 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); 1188 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); 1189 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); 1190 1191 return 0; 1192 } 1193 1194 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1195 { 1196 u32 val; 1197 1198 /* read the SRIOV capability structure 1199 * The fields can be read via configuration read or 1200 * directly from the device (starting at offset PCICFG_OFFSET) 1201 */ 1202 if (bnx2x_sriov_pci_cfg_info(bp, iov)) 1203 return -ENODEV; 1204 1205 /* get the number of SRIOV bars */ 1206 iov->nres = 0; 1207 1208 /* read the first_vfid */ 1209 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 1210 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) 1211 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp)); 1212 1213 DP(BNX2X_MSG_IOV, 1214 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n", 1215 BP_FUNC(bp), 1216 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total, 1217 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz); 1218 1219 return 0; 1220 } 1221 1222 /* must be called after PF bars are mapped */ 1223 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, 1224 int num_vfs_param) 1225 { 1226 int err, i; 1227 struct bnx2x_sriov *iov; 1228 struct pci_dev *dev = bp->pdev; 1229 1230 bp->vfdb = NULL; 1231 1232 /* verify is pf */ 1233 if (IS_VF(bp)) 1234 return 0; 1235 1236 /* verify sriov capability is present in configuration space */ 1237 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV)) 1238 return 0; 1239 1240 /* verify chip revision */ 1241 if (CHIP_IS_E1x(bp)) 1242 return 0; 1243 1244 /* check if SRIOV support is turned off */ 1245 if (!num_vfs_param) 1246 return 0; 1247 1248 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */ 1249 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) { 1250 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n", 1251 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID); 1252 return 0; 1253 } 1254 1255 /* SRIOV can be enabled only with MSIX */ 1256 if (int_mode_param == BNX2X_INT_MODE_MSI || 1257 int_mode_param == BNX2X_INT_MODE_INTX) { 1258 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); 1259 return 0; 1260 } 1261 1262 err = -EIO; 1263 /* verify ari is enabled */ 1264 if (!bnx2x_ari_enabled(bp->pdev)) { 1265 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); 1266 return 0; 1267 } 1268 1269 /* verify igu is in normal mode */ 1270 if (CHIP_INT_MODE_IS_BC(bp)) { 1271 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); 1272 return 0; 1273 } 1274 1275 /* allocate the vfs database */ 1276 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL); 1277 if (!bp->vfdb) { 1278 BNX2X_ERR("failed to allocate vf database\n"); 1279 err = -ENOMEM; 1280 goto failed; 1281 } 1282 1283 /* get the sriov info - Linux already collected all the pertinent 1284 * information, however the sriov structure is for the private use 1285 * of the pci module. Also we want this information regardless 1286 * of the hyper-visor. 1287 */ 1288 iov = &(bp->vfdb->sriov); 1289 err = bnx2x_sriov_info(bp, iov); 1290 if (err) 1291 goto failed; 1292 1293 /* SR-IOV capability was enabled but there are no VFs*/ 1294 if (iov->total == 0) 1295 goto failed; 1296 1297 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); 1298 1299 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", 1300 num_vfs_param, iov->nr_virtfn); 1301 1302 /* allocate the vf array */ 1303 bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * 1304 BNX2X_NR_VIRTFN(bp), GFP_KERNEL); 1305 if (!bp->vfdb->vfs) { 1306 BNX2X_ERR("failed to allocate vf array\n"); 1307 err = -ENOMEM; 1308 goto failed; 1309 } 1310 1311 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */ 1312 for_each_vf(bp, i) { 1313 bnx2x_vf(bp, i, index) = i; 1314 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i; 1315 bnx2x_vf(bp, i, state) = VF_FREE; 1316 mutex_init(&bnx2x_vf(bp, i, op_mutex)); 1317 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE; 1318 } 1319 1320 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */ 1321 if (!bnx2x_get_vf_igu_cam_info(bp)) { 1322 BNX2X_ERR("No entries in IGU CAM for vfs\n"); 1323 err = -EINVAL; 1324 goto failed; 1325 } 1326 1327 /* allocate the queue arrays for all VFs */ 1328 bp->vfdb->vfqs = kzalloc( 1329 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue), 1330 GFP_KERNEL); 1331 1332 if (!bp->vfdb->vfqs) { 1333 BNX2X_ERR("failed to allocate vf queue array\n"); 1334 err = -ENOMEM; 1335 goto failed; 1336 } 1337 1338 /* Prepare the VFs event synchronization mechanism */ 1339 mutex_init(&bp->vfdb->event_mutex); 1340 1341 mutex_init(&bp->vfdb->bulletin_mutex); 1342 1343 if (SHMEM2_HAS(bp, sriov_switch_mode)) 1344 SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB); 1345 1346 return 0; 1347 failed: 1348 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err); 1349 __bnx2x_iov_free_vfdb(bp); 1350 return err; 1351 } 1352 1353 void bnx2x_iov_remove_one(struct bnx2x *bp) 1354 { 1355 int vf_idx; 1356 1357 /* if SRIOV is not enabled there's nothing to do */ 1358 if (!IS_SRIOV(bp)) 1359 return; 1360 1361 bnx2x_disable_sriov(bp); 1362 1363 /* disable access to all VFs */ 1364 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) { 1365 bnx2x_pretend_func(bp, 1366 HW_VF_HANDLE(bp, 1367 bp->vfdb->sriov.first_vf_in_pf + 1368 vf_idx)); 1369 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", 1370 bp->vfdb->sriov.first_vf_in_pf + vf_idx); 1371 bnx2x_vf_enable_internal(bp, 0); 1372 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1373 } 1374 1375 /* free vf database */ 1376 __bnx2x_iov_free_vfdb(bp); 1377 } 1378 1379 void bnx2x_iov_free_mem(struct bnx2x *bp) 1380 { 1381 int i; 1382 1383 if (!IS_SRIOV(bp)) 1384 return; 1385 1386 /* free vfs hw contexts */ 1387 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1388 struct hw_dma *cxt = &bp->vfdb->context[i]; 1389 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size); 1390 } 1391 1392 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr, 1393 BP_VFDB(bp)->sp_dma.mapping, 1394 BP_VFDB(bp)->sp_dma.size); 1395 1396 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr, 1397 BP_VF_MBX_DMA(bp)->mapping, 1398 BP_VF_MBX_DMA(bp)->size); 1399 1400 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr, 1401 BP_VF_BULLETIN_DMA(bp)->mapping, 1402 BP_VF_BULLETIN_DMA(bp)->size); 1403 } 1404 1405 int bnx2x_iov_alloc_mem(struct bnx2x *bp) 1406 { 1407 size_t tot_size; 1408 int i, rc = 0; 1409 1410 if (!IS_SRIOV(bp)) 1411 return rc; 1412 1413 /* allocate vfs hw contexts */ 1414 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) * 1415 BNX2X_CIDS_PER_VF * sizeof(union cdu_context); 1416 1417 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1418 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i); 1419 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ); 1420 1421 if (cxt->size) { 1422 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size); 1423 if (!cxt->addr) 1424 goto alloc_mem_err; 1425 } else { 1426 cxt->addr = NULL; 1427 cxt->mapping = 0; 1428 } 1429 tot_size -= cxt->size; 1430 } 1431 1432 /* allocate vfs ramrods dma memory - client_init and set_mac */ 1433 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp); 1434 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping, 1435 tot_size); 1436 if (!BP_VFDB(bp)->sp_dma.addr) 1437 goto alloc_mem_err; 1438 BP_VFDB(bp)->sp_dma.size = tot_size; 1439 1440 /* allocate mailboxes */ 1441 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE; 1442 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping, 1443 tot_size); 1444 if (!BP_VF_MBX_DMA(bp)->addr) 1445 goto alloc_mem_err; 1446 1447 BP_VF_MBX_DMA(bp)->size = tot_size; 1448 1449 /* allocate local bulletin boards */ 1450 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE; 1451 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping, 1452 tot_size); 1453 if (!BP_VF_BULLETIN_DMA(bp)->addr) 1454 goto alloc_mem_err; 1455 1456 BP_VF_BULLETIN_DMA(bp)->size = tot_size; 1457 1458 return 0; 1459 1460 alloc_mem_err: 1461 return -ENOMEM; 1462 } 1463 1464 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf, 1465 struct bnx2x_vf_queue *q) 1466 { 1467 u8 cl_id = vfq_cl_id(vf, q); 1468 u8 func_id = FW_VF_HANDLE(vf->abs_vfid); 1469 unsigned long q_type = 0; 1470 1471 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1472 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1473 1474 /* Queue State object */ 1475 bnx2x_init_queue_obj(bp, &q->sp_obj, 1476 cl_id, &q->cid, 1, func_id, 1477 bnx2x_vf_sp(bp, vf, q_data), 1478 bnx2x_vf_sp_map(bp, vf, q_data), 1479 q_type); 1480 1481 /* sp indication is set only when vlan/mac/etc. are initialized */ 1482 q->sp_initialized = false; 1483 1484 DP(BNX2X_MSG_IOV, 1485 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n", 1486 vf->abs_vfid, q->sp_obj.func_id, q->cid); 1487 } 1488 1489 static int bnx2x_max_speed_cap(struct bnx2x *bp) 1490 { 1491 u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)]; 1492 1493 if (supported & 1494 (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full)) 1495 return 20000; 1496 1497 return 10000; /* assume lowest supported speed is 10G */ 1498 } 1499 1500 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx) 1501 { 1502 struct bnx2x_link_report_data *state = &bp->last_reported_link; 1503 struct pf_vf_bulletin_content *bulletin; 1504 struct bnx2x_virtf *vf; 1505 bool update = true; 1506 int rc = 0; 1507 1508 /* sanity and init */ 1509 rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false); 1510 if (rc) 1511 return rc; 1512 1513 mutex_lock(&bp->vfdb->bulletin_mutex); 1514 1515 if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) { 1516 bulletin->valid_bitmap |= 1 << LINK_VALID; 1517 1518 bulletin->link_speed = state->line_speed; 1519 bulletin->link_flags = 0; 1520 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1521 &state->link_report_flags)) 1522 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1523 if (test_bit(BNX2X_LINK_REPORT_FD, 1524 &state->link_report_flags)) 1525 bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX; 1526 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON, 1527 &state->link_report_flags)) 1528 bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON; 1529 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON, 1530 &state->link_report_flags)) 1531 bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON; 1532 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE && 1533 !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1534 bulletin->valid_bitmap |= 1 << LINK_VALID; 1535 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1536 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE && 1537 (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1538 bulletin->valid_bitmap |= 1 << LINK_VALID; 1539 bulletin->link_speed = bnx2x_max_speed_cap(bp); 1540 bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN; 1541 } else { 1542 update = false; 1543 } 1544 1545 if (update) { 1546 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV, 1547 "vf %d mode %u speed %d flags %x\n", idx, 1548 vf->link_cfg, bulletin->link_speed, bulletin->link_flags); 1549 1550 /* Post update on VF's bulletin board */ 1551 rc = bnx2x_post_vf_bulletin(bp, idx); 1552 if (rc) { 1553 BNX2X_ERR("failed to update VF[%d] bulletin\n", idx); 1554 goto out; 1555 } 1556 } 1557 1558 out: 1559 mutex_unlock(&bp->vfdb->bulletin_mutex); 1560 return rc; 1561 } 1562 1563 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state) 1564 { 1565 struct bnx2x *bp = netdev_priv(dev); 1566 struct bnx2x_virtf *vf = BP_VF(bp, idx); 1567 1568 if (!vf) 1569 return -EINVAL; 1570 1571 if (vf->link_cfg == link_state) 1572 return 0; /* nothing todo */ 1573 1574 vf->link_cfg = link_state; 1575 1576 return bnx2x_iov_link_update_vf(bp, idx); 1577 } 1578 1579 void bnx2x_iov_link_update(struct bnx2x *bp) 1580 { 1581 int vfid; 1582 1583 if (!IS_SRIOV(bp)) 1584 return; 1585 1586 for_each_vf(bp, vfid) 1587 bnx2x_iov_link_update_vf(bp, vfid); 1588 } 1589 1590 /* called by bnx2x_nic_load */ 1591 int bnx2x_iov_nic_init(struct bnx2x *bp) 1592 { 1593 int vfid; 1594 1595 if (!IS_SRIOV(bp)) { 1596 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); 1597 return 0; 1598 } 1599 1600 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); 1601 1602 /* let FLR complete ... */ 1603 msleep(100); 1604 1605 /* initialize vf database */ 1606 for_each_vf(bp, vfid) { 1607 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1608 1609 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) * 1610 BNX2X_CIDS_PER_VF; 1611 1612 union cdu_context *base_cxt = (union cdu_context *) 1613 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 1614 (base_vf_cid & (ILT_PAGE_CIDS-1)); 1615 1616 DP(BNX2X_MSG_IOV, 1617 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n", 1618 vf->abs_vfid, vf_sb_count(vf), base_vf_cid, 1619 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt); 1620 1621 /* init statically provisioned resources */ 1622 bnx2x_iov_static_resc(bp, vf); 1623 1624 /* queues are initialized during VF-ACQUIRE */ 1625 vf->filter_state = 0; 1626 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id); 1627 1628 /* init mcast object - This object will be re-initialized 1629 * during VF-ACQUIRE with the proper cl_id and cid. 1630 * It needs to be initialized here so that it can be safely 1631 * handled by a subsequent FLR flow. 1632 */ 1633 vf->mcast_list_len = 0; 1634 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF, 1635 0xFF, 0xFF, 0xFF, 1636 bnx2x_vf_sp(bp, vf, mcast_rdata), 1637 bnx2x_vf_sp_map(bp, vf, mcast_rdata), 1638 BNX2X_FILTER_MCAST_PENDING, 1639 &vf->filter_state, 1640 BNX2X_OBJ_TYPE_RX_TX); 1641 1642 /* set the mailbox message addresses */ 1643 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *) 1644 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid * 1645 MBX_MSG_ALIGNED_SIZE); 1646 1647 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping + 1648 vfid * MBX_MSG_ALIGNED_SIZE; 1649 1650 /* Enable vf mailbox */ 1651 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 1652 } 1653 1654 /* Final VF init */ 1655 for_each_vf(bp, vfid) { 1656 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1657 1658 /* fill in the BDF and bars */ 1659 vf->bus = bnx2x_vf_bus(bp, vfid); 1660 vf->devfn = bnx2x_vf_devfn(bp, vfid); 1661 bnx2x_vf_set_bars(bp, vf); 1662 1663 DP(BNX2X_MSG_IOV, 1664 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n", 1665 vf->abs_vfid, vf->bus, vf->devfn, 1666 (unsigned)vf->bars[0].bar, vf->bars[0].size, 1667 (unsigned)vf->bars[1].bar, vf->bars[1].size, 1668 (unsigned)vf->bars[2].bar, vf->bars[2].size); 1669 } 1670 1671 return 0; 1672 } 1673 1674 /* called by bnx2x_chip_cleanup */ 1675 int bnx2x_iov_chip_cleanup(struct bnx2x *bp) 1676 { 1677 int i; 1678 1679 if (!IS_SRIOV(bp)) 1680 return 0; 1681 1682 /* release all the VFs */ 1683 for_each_vf(bp, i) 1684 bnx2x_vf_release(bp, BP_VF(bp, i)); 1685 1686 return 0; 1687 } 1688 1689 /* called by bnx2x_init_hw_func, returns the next ilt line */ 1690 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) 1691 { 1692 int i; 1693 struct bnx2x_ilt *ilt = BP_ILT(bp); 1694 1695 if (!IS_SRIOV(bp)) 1696 return line; 1697 1698 /* set vfs ilt lines */ 1699 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1700 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i); 1701 1702 ilt->lines[line+i].page = hw_cxt->addr; 1703 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 1704 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 1705 } 1706 return line + i; 1707 } 1708 1709 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid) 1710 { 1711 return ((cid >= BNX2X_FIRST_VF_CID) && 1712 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS)); 1713 } 1714 1715 static 1716 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp, 1717 struct bnx2x_vf_queue *vfq, 1718 union event_ring_elem *elem) 1719 { 1720 unsigned long ramrod_flags = 0; 1721 int rc = 0; 1722 1723 /* Always push next commands out, don't wait here */ 1724 set_bit(RAMROD_CONT, &ramrod_flags); 1725 1726 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 1727 case BNX2X_FILTER_MAC_PENDING: 1728 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem, 1729 &ramrod_flags); 1730 break; 1731 case BNX2X_FILTER_VLAN_PENDING: 1732 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem, 1733 &ramrod_flags); 1734 break; 1735 default: 1736 BNX2X_ERR("Unsupported classification command: %d\n", 1737 elem->message.data.eth_event.echo); 1738 return; 1739 } 1740 if (rc < 0) 1741 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 1742 else if (rc > 0) 1743 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); 1744 } 1745 1746 static 1747 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp, 1748 struct bnx2x_virtf *vf) 1749 { 1750 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 1751 int rc; 1752 1753 rparam.mcast_obj = &vf->mcast_obj; 1754 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw); 1755 1756 /* If there are pending mcast commands - send them */ 1757 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) { 1758 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 1759 if (rc < 0) 1760 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 1761 rc); 1762 } 1763 } 1764 1765 static 1766 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp, 1767 struct bnx2x_virtf *vf) 1768 { 1769 smp_mb__before_atomic(); 1770 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 1771 smp_mb__after_atomic(); 1772 } 1773 1774 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp, 1775 struct bnx2x_virtf *vf) 1776 { 1777 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw); 1778 } 1779 1780 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) 1781 { 1782 struct bnx2x_virtf *vf; 1783 int qidx = 0, abs_vfid; 1784 u8 opcode; 1785 u16 cid = 0xffff; 1786 1787 if (!IS_SRIOV(bp)) 1788 return 1; 1789 1790 /* first get the cid - the only events we handle here are cfc-delete 1791 * and set-mac completion 1792 */ 1793 opcode = elem->message.opcode; 1794 1795 switch (opcode) { 1796 case EVENT_RING_OPCODE_CFC_DEL: 1797 cid = SW_CID((__force __le32) 1798 elem->message.data.cfc_del_event.cid); 1799 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); 1800 break; 1801 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1802 case EVENT_RING_OPCODE_MULTICAST_RULES: 1803 case EVENT_RING_OPCODE_FILTERS_RULES: 1804 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1805 cid = (elem->message.data.eth_event.echo & 1806 BNX2X_SWCID_MASK); 1807 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); 1808 break; 1809 case EVENT_RING_OPCODE_VF_FLR: 1810 abs_vfid = elem->message.data.vf_flr_event.vf_id; 1811 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", 1812 abs_vfid); 1813 goto get_vf; 1814 case EVENT_RING_OPCODE_MALICIOUS_VF: 1815 abs_vfid = elem->message.data.malicious_vf_event.vf_id; 1816 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", 1817 abs_vfid, 1818 elem->message.data.malicious_vf_event.err_id); 1819 goto get_vf; 1820 default: 1821 return 1; 1822 } 1823 1824 /* check if the cid is the VF range */ 1825 if (!bnx2x_iov_is_vf_cid(bp, cid)) { 1826 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); 1827 return 1; 1828 } 1829 1830 /* extract vf and rxq index from vf_cid - relies on the following: 1831 * 1. vfid on cid reflects the true abs_vfid 1832 * 2. The max number of VFs (per path) is 64 1833 */ 1834 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1); 1835 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1836 get_vf: 1837 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 1838 1839 if (!vf) { 1840 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n", 1841 cid, abs_vfid); 1842 return 0; 1843 } 1844 1845 switch (opcode) { 1846 case EVENT_RING_OPCODE_CFC_DEL: 1847 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", 1848 vf->abs_vfid, qidx); 1849 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp, 1850 &vfq_get(vf, 1851 qidx)->sp_obj, 1852 BNX2X_Q_CMD_CFC_DEL); 1853 break; 1854 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1855 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", 1856 vf->abs_vfid, qidx); 1857 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem); 1858 break; 1859 case EVENT_RING_OPCODE_MULTICAST_RULES: 1860 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", 1861 vf->abs_vfid, qidx); 1862 bnx2x_vf_handle_mcast_eqe(bp, vf); 1863 break; 1864 case EVENT_RING_OPCODE_FILTERS_RULES: 1865 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", 1866 vf->abs_vfid, qidx); 1867 bnx2x_vf_handle_filters_eqe(bp, vf); 1868 break; 1869 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1870 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", 1871 vf->abs_vfid, qidx); 1872 bnx2x_vf_handle_rss_update_eqe(bp, vf); 1873 case EVENT_RING_OPCODE_VF_FLR: 1874 case EVENT_RING_OPCODE_MALICIOUS_VF: 1875 /* Do nothing for now */ 1876 return 0; 1877 } 1878 1879 return 0; 1880 } 1881 1882 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid) 1883 { 1884 /* extract the vf from vf_cid - relies on the following: 1885 * 1. vfid on cid reflects the true abs_vfid 1886 * 2. The max number of VFs (per path) is 64 1887 */ 1888 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1889 return bnx2x_vf_by_abs_fid(bp, abs_vfid); 1890 } 1891 1892 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid, 1893 struct bnx2x_queue_sp_obj **q_obj) 1894 { 1895 struct bnx2x_virtf *vf; 1896 1897 if (!IS_SRIOV(bp)) 1898 return; 1899 1900 vf = bnx2x_vf_by_cid(bp, vf_cid); 1901 1902 if (vf) { 1903 /* extract queue index from vf_cid - relies on the following: 1904 * 1. vfid on cid reflects the true abs_vfid 1905 * 2. The max number of VFs (per path) is 64 1906 */ 1907 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1); 1908 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj); 1909 } else { 1910 BNX2X_ERR("No vf matching cid %d\n", vf_cid); 1911 } 1912 } 1913 1914 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) 1915 { 1916 int i; 1917 int first_queue_query_index, num_queues_req; 1918 dma_addr_t cur_data_offset; 1919 struct stats_query_entry *cur_query_entry; 1920 u8 stats_count = 0; 1921 bool is_fcoe = false; 1922 1923 if (!IS_SRIOV(bp)) 1924 return; 1925 1926 if (!NO_FCOE(bp)) 1927 is_fcoe = true; 1928 1929 /* fcoe adds one global request and one queue request */ 1930 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe; 1931 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1932 (is_fcoe ? 0 : 1); 1933 1934 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1935 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n", 1936 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index, 1937 first_queue_query_index + num_queues_req); 1938 1939 cur_data_offset = bp->fw_stats_data_mapping + 1940 offsetof(struct bnx2x_fw_stats_data, queue_stats) + 1941 num_queues_req * sizeof(struct per_queue_stats); 1942 1943 cur_query_entry = &bp->fw_stats_req-> 1944 query[first_queue_query_index + num_queues_req]; 1945 1946 for_each_vf(bp, i) { 1947 int j; 1948 struct bnx2x_virtf *vf = BP_VF(bp, i); 1949 1950 if (vf->state != VF_ENABLED) { 1951 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1952 "vf %d not enabled so no stats for it\n", 1953 vf->abs_vfid); 1954 continue; 1955 } 1956 1957 DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid); 1958 for_each_vfq(vf, j) { 1959 struct bnx2x_vf_queue *rxq = vfq_get(vf, j); 1960 1961 dma_addr_t q_stats_addr = 1962 vf->fw_stat_map + j * vf->stats_stride; 1963 1964 /* collect stats fro active queues only */ 1965 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) == 1966 BNX2X_Q_LOGICAL_STATE_STOPPED) 1967 continue; 1968 1969 /* create stats query entry for this queue */ 1970 cur_query_entry->kind = STATS_TYPE_QUEUE; 1971 cur_query_entry->index = vfq_stat_id(vf, rxq); 1972 cur_query_entry->funcID = 1973 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid)); 1974 cur_query_entry->address.hi = 1975 cpu_to_le32(U64_HI(q_stats_addr)); 1976 cur_query_entry->address.lo = 1977 cpu_to_le32(U64_LO(q_stats_addr)); 1978 DP(BNX2X_MSG_IOV, 1979 "added address %x %x for vf %d queue %d client %d\n", 1980 cur_query_entry->address.hi, 1981 cur_query_entry->address.lo, cur_query_entry->funcID, 1982 j, cur_query_entry->index); 1983 cur_query_entry++; 1984 cur_data_offset += sizeof(struct per_queue_stats); 1985 stats_count++; 1986 1987 /* all stats are coalesced to the leading queue */ 1988 if (vf->cfg_flags & VF_CFG_STATS_COALESCE) 1989 break; 1990 } 1991 } 1992 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count; 1993 } 1994 1995 /* VF API helpers */ 1996 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid, 1997 u8 enable) 1998 { 1999 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; 2000 u32 val = enable ? (abs_vfid | (1 << 6)) : 0; 2001 2002 REG_WR(bp, reg, val); 2003 } 2004 2005 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf) 2006 { 2007 int i; 2008 2009 for_each_vfq(vf, i) 2010 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2011 vfq_qzone_id(vf, vfq_get(vf, i)), false); 2012 } 2013 2014 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf) 2015 { 2016 u32 val; 2017 2018 /* clear the VF configuration - pretend */ 2019 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 2020 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 2021 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | 2022 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK); 2023 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 2024 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2025 } 2026 2027 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf) 2028 { 2029 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF), 2030 BNX2X_VF_MAX_QUEUES); 2031 } 2032 2033 static 2034 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf, 2035 struct vf_pf_resc_request *req_resc) 2036 { 2037 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 2038 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 2039 2040 /* Save a vlan filter for the Hypervisor */ 2041 return ((req_resc->num_rxqs <= rxq_cnt) && 2042 (req_resc->num_txqs <= txq_cnt) && 2043 (req_resc->num_sbs <= vf_sb_count(vf)) && 2044 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) && 2045 (req_resc->num_vlan_filters <= vf_vlan_rules_visible_cnt(vf))); 2046 } 2047 2048 /* CORE VF API */ 2049 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf, 2050 struct vf_pf_resc_request *resc) 2051 { 2052 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) * 2053 BNX2X_CIDS_PER_VF; 2054 2055 union cdu_context *base_cxt = (union cdu_context *) 2056 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 2057 (base_vf_cid & (ILT_PAGE_CIDS-1)); 2058 int i; 2059 2060 /* if state is 'acquired' the VF was not released or FLR'd, in 2061 * this case the returned resources match the acquired already 2062 * acquired resources. Verify that the requested numbers do 2063 * not exceed the already acquired numbers. 2064 */ 2065 if (vf->state == VF_ACQUIRED) { 2066 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", 2067 vf->abs_vfid); 2068 2069 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2070 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n", 2071 vf->abs_vfid); 2072 return -EINVAL; 2073 } 2074 return 0; 2075 } 2076 2077 /* Otherwise vf state must be 'free' or 'reset' */ 2078 if (vf->state != VF_FREE && vf->state != VF_RESET) { 2079 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n", 2080 vf->abs_vfid, vf->state); 2081 return -EINVAL; 2082 } 2083 2084 /* static allocation: 2085 * the global maximum number are fixed per VF. Fail the request if 2086 * requested number exceed these globals 2087 */ 2088 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2089 DP(BNX2X_MSG_IOV, 2090 "cannot fulfill vf resource request. Placing maximal available values in response\n"); 2091 /* set the max resource in the vf */ 2092 return -ENOMEM; 2093 } 2094 2095 /* Set resources counters - 0 request means max available */ 2096 vf_sb_count(vf) = resc->num_sbs; 2097 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2098 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2099 if (resc->num_mac_filters) 2100 vf_mac_rules_cnt(vf) = resc->num_mac_filters; 2101 /* Add an additional vlan filter credit for the hypervisor */ 2102 bnx2x_iov_re_set_vlan_filters(bp, vf, resc->num_vlan_filters + 1); 2103 2104 DP(BNX2X_MSG_IOV, 2105 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n", 2106 vf_sb_count(vf), vf_rxq_count(vf), 2107 vf_txq_count(vf), vf_mac_rules_cnt(vf), 2108 vf_vlan_rules_visible_cnt(vf)); 2109 2110 /* Initialize the queues */ 2111 if (!vf->vfqs) { 2112 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); 2113 return -EINVAL; 2114 } 2115 2116 for_each_vfq(vf, i) { 2117 struct bnx2x_vf_queue *q = vfq_get(vf, i); 2118 2119 if (!q) { 2120 BNX2X_ERR("q number %d was not allocated\n", i); 2121 return -EINVAL; 2122 } 2123 2124 q->index = i; 2125 q->cxt = &((base_cxt + i)->eth); 2126 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i; 2127 2128 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", 2129 vf->abs_vfid, i, q->index, q->cid, q->cxt); 2130 2131 /* init SP objects */ 2132 bnx2x_vfq_init(bp, vf, q); 2133 } 2134 vf->state = VF_ACQUIRED; 2135 return 0; 2136 } 2137 2138 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map) 2139 { 2140 struct bnx2x_func_init_params func_init = {0}; 2141 u16 flags = 0; 2142 int i; 2143 2144 /* the sb resources are initialized at this point, do the 2145 * FW/HW initializations 2146 */ 2147 for_each_vf_sb(vf, i) 2148 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true, 2149 vf_igu_sb(vf, i), vf_igu_sb(vf, i)); 2150 2151 /* Sanity checks */ 2152 if (vf->state != VF_ACQUIRED) { 2153 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", 2154 vf->abs_vfid, vf->state); 2155 return -EINVAL; 2156 } 2157 2158 /* let FLR complete ... */ 2159 msleep(100); 2160 2161 /* FLR cleanup epilogue */ 2162 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid)) 2163 return -EBUSY; 2164 2165 /* reset IGU VF statistics: MSIX */ 2166 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0); 2167 2168 /* vf init */ 2169 if (vf->cfg_flags & VF_CFG_STATS) 2170 flags |= (FUNC_FLG_STATS | FUNC_FLG_SPQ); 2171 2172 if (vf->cfg_flags & VF_CFG_TPA) 2173 flags |= FUNC_FLG_TPA; 2174 2175 if (is_vf_multi(vf)) 2176 flags |= FUNC_FLG_RSS; 2177 2178 /* function setup */ 2179 func_init.func_flgs = flags; 2180 func_init.pf_id = BP_FUNC(bp); 2181 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid); 2182 func_init.fw_stat_map = vf->fw_stat_map; 2183 func_init.spq_map = vf->spq_map; 2184 func_init.spq_prod = 0; 2185 bnx2x_func_init(bp, &func_init); 2186 2187 /* Enable the vf */ 2188 bnx2x_vf_enable_access(bp, vf->abs_vfid); 2189 bnx2x_vf_enable_traffic(bp, vf); 2190 2191 /* queue protection table */ 2192 for_each_vfq(vf, i) 2193 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2194 vfq_qzone_id(vf, vfq_get(vf, i)), true); 2195 2196 vf->state = VF_ENABLED; 2197 2198 /* update vf bulletin board */ 2199 bnx2x_post_vf_bulletin(bp, vf->index); 2200 2201 return 0; 2202 } 2203 2204 struct set_vf_state_cookie { 2205 struct bnx2x_virtf *vf; 2206 u8 state; 2207 }; 2208 2209 static void bnx2x_set_vf_state(void *cookie) 2210 { 2211 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie; 2212 2213 p->vf->state = p->state; 2214 } 2215 2216 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf) 2217 { 2218 int rc = 0, i; 2219 2220 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2221 2222 /* Close all queues */ 2223 for (i = 0; i < vf_rxq_count(vf); i++) { 2224 rc = bnx2x_vf_queue_teardown(bp, vf, i); 2225 if (rc) 2226 goto op_err; 2227 } 2228 2229 /* disable the interrupts */ 2230 DP(BNX2X_MSG_IOV, "disabling igu\n"); 2231 bnx2x_vf_igu_disable(bp, vf); 2232 2233 /* disable the VF */ 2234 DP(BNX2X_MSG_IOV, "clearing qtbl\n"); 2235 bnx2x_vf_clr_qtbl(bp, vf); 2236 2237 /* need to make sure there are no outstanding stats ramrods which may 2238 * cause the device to access the VF's stats buffer which it will free 2239 * as soon as we return from the close flow. 2240 */ 2241 { 2242 struct set_vf_state_cookie cookie; 2243 2244 cookie.vf = vf; 2245 cookie.state = VF_ACQUIRED; 2246 rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie); 2247 if (rc) 2248 goto op_err; 2249 } 2250 2251 DP(BNX2X_MSG_IOV, "set state to acquired\n"); 2252 2253 return 0; 2254 op_err: 2255 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc); 2256 return rc; 2257 } 2258 2259 /* VF release can be called either: 1. The VF was acquired but 2260 * not enabled 2. the vf was enabled or in the process of being 2261 * enabled 2262 */ 2263 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf) 2264 { 2265 int rc; 2266 2267 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, 2268 vf->state == VF_FREE ? "Free" : 2269 vf->state == VF_ACQUIRED ? "Acquired" : 2270 vf->state == VF_ENABLED ? "Enabled" : 2271 vf->state == VF_RESET ? "Reset" : 2272 "Unknown"); 2273 2274 switch (vf->state) { 2275 case VF_ENABLED: 2276 rc = bnx2x_vf_close(bp, vf); 2277 if (rc) 2278 goto op_err; 2279 /* Fallthrough to release resources */ 2280 case VF_ACQUIRED: 2281 DP(BNX2X_MSG_IOV, "about to free resources\n"); 2282 bnx2x_vf_free_resc(bp, vf); 2283 break; 2284 2285 case VF_FREE: 2286 case VF_RESET: 2287 default: 2288 break; 2289 } 2290 return 0; 2291 op_err: 2292 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc); 2293 return rc; 2294 } 2295 2296 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2297 struct bnx2x_config_rss_params *rss) 2298 { 2299 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2300 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags); 2301 return bnx2x_config_rss(bp, rss); 2302 } 2303 2304 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2305 struct vfpf_tpa_tlv *tlv, 2306 struct bnx2x_queue_update_tpa_params *params) 2307 { 2308 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr; 2309 struct bnx2x_queue_state_params qstate; 2310 int qid, rc = 0; 2311 2312 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2313 2314 /* Set ramrod params */ 2315 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 2316 memcpy(&qstate.params.update_tpa, params, 2317 sizeof(struct bnx2x_queue_update_tpa_params)); 2318 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA; 2319 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 2320 2321 for (qid = 0; qid < vf_rxq_count(vf); qid++) { 2322 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 2323 qstate.params.update_tpa.sge_map = sge_addr[qid]; 2324 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", 2325 vf->abs_vfid, qid, U64_HI(sge_addr[qid]), 2326 U64_LO(sge_addr[qid])); 2327 rc = bnx2x_queue_state_change(bp, &qstate); 2328 if (rc) { 2329 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n", 2330 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]), 2331 vf->abs_vfid, qid); 2332 return rc; 2333 } 2334 } 2335 2336 return rc; 2337 } 2338 2339 /* VF release ~ VF close + VF release-resources 2340 * Release is the ultimate SW shutdown and is called whenever an 2341 * irrecoverable error is encountered. 2342 */ 2343 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf) 2344 { 2345 int rc; 2346 2347 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); 2348 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2349 2350 rc = bnx2x_vf_free(bp, vf); 2351 if (rc) 2352 WARN(rc, 2353 "VF[%d] Failed to allocate resources for release op- rc=%d\n", 2354 vf->abs_vfid, rc); 2355 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2356 return rc; 2357 } 2358 2359 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2360 enum channel_tlvs tlv) 2361 { 2362 /* we don't lock the channel for unsupported tlvs */ 2363 if (!bnx2x_tlv_supported(tlv)) { 2364 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n"); 2365 return; 2366 } 2367 2368 /* lock the channel */ 2369 mutex_lock(&vf->op_mutex); 2370 2371 /* record the locking op */ 2372 vf->op_current = tlv; 2373 2374 /* log the lock */ 2375 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", 2376 vf->abs_vfid, tlv); 2377 } 2378 2379 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2380 enum channel_tlvs expected_tlv) 2381 { 2382 enum channel_tlvs current_tlv; 2383 2384 if (!vf) { 2385 BNX2X_ERR("VF was %p\n", vf); 2386 return; 2387 } 2388 2389 current_tlv = vf->op_current; 2390 2391 /* we don't unlock the channel for unsupported tlvs */ 2392 if (!bnx2x_tlv_supported(expected_tlv)) 2393 return; 2394 2395 WARN(expected_tlv != vf->op_current, 2396 "lock mismatch: expected %d found %d", expected_tlv, 2397 vf->op_current); 2398 2399 /* record the locking op */ 2400 vf->op_current = CHANNEL_TLV_NONE; 2401 2402 /* lock the channel */ 2403 mutex_unlock(&vf->op_mutex); 2404 2405 /* log the unlock */ 2406 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", 2407 vf->abs_vfid, current_tlv); 2408 } 2409 2410 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable) 2411 { 2412 struct bnx2x_queue_state_params q_params; 2413 u32 prev_flags; 2414 int i, rc; 2415 2416 /* Verify changes are needed and record current Tx switching state */ 2417 prev_flags = bp->flags; 2418 if (enable) 2419 bp->flags |= TX_SWITCHING; 2420 else 2421 bp->flags &= ~TX_SWITCHING; 2422 if (prev_flags == bp->flags) 2423 return 0; 2424 2425 /* Verify state enables the sending of queue ramrods */ 2426 if ((bp->state != BNX2X_STATE_OPEN) || 2427 (bnx2x_get_q_logical_state(bp, 2428 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) != 2429 BNX2X_Q_LOGICAL_STATE_ACTIVE)) 2430 return 0; 2431 2432 /* send q. update ramrod to configure Tx switching */ 2433 memset(&q_params, 0, sizeof(q_params)); 2434 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2435 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2436 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 2437 &q_params.params.update.update_flags); 2438 if (enable) 2439 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2440 &q_params.params.update.update_flags); 2441 else 2442 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2443 &q_params.params.update.update_flags); 2444 2445 /* send the ramrod on all the queues of the PF */ 2446 for_each_eth_queue(bp, i) { 2447 struct bnx2x_fastpath *fp = &bp->fp[i]; 2448 2449 /* Set the appropriate Queue object */ 2450 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 2451 2452 /* Update the Queue state */ 2453 rc = bnx2x_queue_state_change(bp, &q_params); 2454 if (rc) { 2455 BNX2X_ERR("Failed to configure Tx switching\n"); 2456 return rc; 2457 } 2458 } 2459 2460 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled"); 2461 return 0; 2462 } 2463 2464 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) 2465 { 2466 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); 2467 2468 if (!IS_SRIOV(bp)) { 2469 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); 2470 return -EINVAL; 2471 } 2472 2473 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", 2474 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2475 2476 /* HW channel is only operational when PF is up */ 2477 if (bp->state != BNX2X_STATE_OPEN) { 2478 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n"); 2479 return -EINVAL; 2480 } 2481 2482 /* we are always bound by the total_vfs in the configuration space */ 2483 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { 2484 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", 2485 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2486 num_vfs_param = BNX2X_NR_VIRTFN(bp); 2487 } 2488 2489 bp->requested_nr_virtfn = num_vfs_param; 2490 if (num_vfs_param == 0) { 2491 bnx2x_set_pf_tx_switching(bp, false); 2492 bnx2x_disable_sriov(bp); 2493 return 0; 2494 } else { 2495 return bnx2x_enable_sriov(bp); 2496 } 2497 } 2498 2499 #define IGU_ENTRY_SIZE 4 2500 2501 int bnx2x_enable_sriov(struct bnx2x *bp) 2502 { 2503 int rc = 0, req_vfs = bp->requested_nr_virtfn; 2504 int vf_idx, sb_idx, vfq_idx, qcount, first_vf; 2505 u32 igu_entry, address; 2506 u16 num_vf_queues; 2507 2508 if (req_vfs == 0) 2509 return 0; 2510 2511 first_vf = bp->vfdb->sriov.first_vf_in_pf; 2512 2513 /* statically distribute vf sb pool between VFs */ 2514 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES, 2515 BP_VFDB(bp)->vf_sbs_pool / req_vfs); 2516 2517 /* zero previous values learned from igu cam */ 2518 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) { 2519 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2520 2521 vf->sb_count = 0; 2522 vf_sb_count(BP_VF(bp, vf_idx)) = 0; 2523 } 2524 bp->vfdb->vf_sbs_pool = 0; 2525 2526 /* prepare IGU cam */ 2527 sb_idx = BP_VFDB(bp)->first_vf_igu_entry; 2528 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE; 2529 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2530 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) { 2531 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT | 2532 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT | 2533 IGU_REG_MAPPING_MEMORY_VALID; 2534 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", 2535 sb_idx, vf_idx); 2536 REG_WR(bp, address, igu_entry); 2537 sb_idx++; 2538 address += IGU_ENTRY_SIZE; 2539 } 2540 } 2541 2542 /* Reinitialize vf database according to igu cam */ 2543 bnx2x_get_vf_igu_cam_info(bp); 2544 2545 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", 2546 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues); 2547 2548 qcount = 0; 2549 for_each_vf(bp, vf_idx) { 2550 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2551 2552 /* set local queue arrays */ 2553 vf->vfqs = &bp->vfdb->vfqs[qcount]; 2554 qcount += vf_sb_count(vf); 2555 bnx2x_iov_static_resc(bp, vf); 2556 } 2557 2558 /* prepare msix vectors in VF configuration space - the value in the 2559 * PCI configuration space should be the index of the last entry, 2560 * namely one less than the actual size of the table 2561 */ 2562 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2563 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); 2564 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, 2565 num_vf_queues - 1); 2566 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n", 2567 vf_idx, num_vf_queues - 1); 2568 } 2569 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2570 2571 /* enable sriov. This will probe all the VFs, and consequentially cause 2572 * the "acquire" messages to appear on the VF PF channel. 2573 */ 2574 DP(BNX2X_MSG_IOV, "about to call enable sriov\n"); 2575 bnx2x_disable_sriov(bp); 2576 2577 rc = bnx2x_set_pf_tx_switching(bp, true); 2578 if (rc) 2579 return rc; 2580 2581 rc = pci_enable_sriov(bp->pdev, req_vfs); 2582 if (rc) { 2583 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); 2584 return rc; 2585 } 2586 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); 2587 return req_vfs; 2588 } 2589 2590 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) 2591 { 2592 int vfidx; 2593 struct pf_vf_bulletin_content *bulletin; 2594 2595 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); 2596 for_each_vf(bp, vfidx) { 2597 bulletin = BP_VF_BULLETIN(bp, vfidx); 2598 if (BP_VF(bp, vfidx)->cfg_flags & VF_CFG_VLAN) 2599 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0); 2600 } 2601 } 2602 2603 void bnx2x_disable_sriov(struct bnx2x *bp) 2604 { 2605 if (pci_vfs_assigned(bp->pdev)) { 2606 DP(BNX2X_MSG_IOV, 2607 "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2608 return; 2609 } 2610 2611 pci_disable_sriov(bp->pdev); 2612 } 2613 2614 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 2615 struct bnx2x_virtf **vf, 2616 struct pf_vf_bulletin_content **bulletin, 2617 bool test_queue) 2618 { 2619 if (bp->state != BNX2X_STATE_OPEN) { 2620 BNX2X_ERR("PF is down - can't utilize iov-related functionality\n"); 2621 return -EINVAL; 2622 } 2623 2624 if (!IS_SRIOV(bp)) { 2625 BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n"); 2626 return -EINVAL; 2627 } 2628 2629 if (vfidx >= BNX2X_NR_VIRTFN(bp)) { 2630 BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n", 2631 vfidx, BNX2X_NR_VIRTFN(bp)); 2632 return -EINVAL; 2633 } 2634 2635 /* init members */ 2636 *vf = BP_VF(bp, vfidx); 2637 *bulletin = BP_VF_BULLETIN(bp, vfidx); 2638 2639 if (!*vf) { 2640 BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx); 2641 return -EINVAL; 2642 } 2643 2644 if (test_queue && !(*vf)->vfqs) { 2645 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n", 2646 vfidx); 2647 return -EINVAL; 2648 } 2649 2650 if (!*bulletin) { 2651 BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n", 2652 vfidx); 2653 return -EINVAL; 2654 } 2655 2656 return 0; 2657 } 2658 2659 int bnx2x_get_vf_config(struct net_device *dev, int vfidx, 2660 struct ifla_vf_info *ivi) 2661 { 2662 struct bnx2x *bp = netdev_priv(dev); 2663 struct bnx2x_virtf *vf = NULL; 2664 struct pf_vf_bulletin_content *bulletin = NULL; 2665 struct bnx2x_vlan_mac_obj *mac_obj; 2666 struct bnx2x_vlan_mac_obj *vlan_obj; 2667 int rc; 2668 2669 /* sanity and init */ 2670 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2671 if (rc) 2672 return rc; 2673 2674 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2675 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2676 if (!mac_obj || !vlan_obj) { 2677 BNX2X_ERR("VF partially initialized\n"); 2678 return -EINVAL; 2679 } 2680 2681 ivi->vf = vfidx; 2682 ivi->qos = 0; 2683 ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */ 2684 ivi->min_tx_rate = 0; 2685 ivi->spoofchk = 1; /*always enabled */ 2686 if (vf->state == VF_ENABLED) { 2687 /* mac and vlan are in vlan_mac objects */ 2688 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) { 2689 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, 2690 0, ETH_ALEN); 2691 vlan_obj->get_n_elements(bp, vlan_obj, 1, 2692 (u8 *)&ivi->vlan, 0, 2693 VLAN_HLEN); 2694 } 2695 } else { 2696 mutex_lock(&bp->vfdb->bulletin_mutex); 2697 /* mac */ 2698 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) 2699 /* mac configured by ndo so its in bulletin board */ 2700 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); 2701 else 2702 /* function has not been loaded yet. Show mac as 0s */ 2703 eth_zero_addr(ivi->mac); 2704 2705 /* vlan */ 2706 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2707 /* vlan configured by ndo so its in bulletin board */ 2708 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); 2709 else 2710 /* function has not been loaded yet. Show vlans as 0s */ 2711 memset(&ivi->vlan, 0, VLAN_HLEN); 2712 2713 mutex_unlock(&bp->vfdb->bulletin_mutex); 2714 } 2715 2716 return 0; 2717 } 2718 2719 /* New mac for VF. Consider these cases: 2720 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and 2721 * supply at acquire. 2722 * 2. VF has already been acquired but has not yet initialized - store in local 2723 * bulletin board. mac will be posted on VF bulletin board after VF init. VF 2724 * will configure this mac when it is ready. 2725 * 3. VF has already initialized but has not yet setup a queue - post the new 2726 * mac on VF's bulletin board right now. VF will configure this mac when it 2727 * is ready. 2728 * 4. VF has already set a queue - delete any macs already configured for this 2729 * queue and manually config the new mac. 2730 * In any event, once this function has been called refuse any attempts by the 2731 * VF to configure any mac for itself except for this mac. In case of a race 2732 * where the VF fails to see the new post on its bulletin board before sending a 2733 * mac configuration request, the PF will simply fail the request and VF can try 2734 * again after consulting its bulletin board. 2735 */ 2736 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) 2737 { 2738 struct bnx2x *bp = netdev_priv(dev); 2739 int rc, q_logical_state; 2740 struct bnx2x_virtf *vf = NULL; 2741 struct pf_vf_bulletin_content *bulletin = NULL; 2742 2743 if (!is_valid_ether_addr(mac)) { 2744 BNX2X_ERR("mac address invalid\n"); 2745 return -EINVAL; 2746 } 2747 2748 /* sanity and init */ 2749 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2750 if (rc) 2751 return rc; 2752 2753 mutex_lock(&bp->vfdb->bulletin_mutex); 2754 2755 /* update PF's copy of the VF's bulletin. Will no longer accept mac 2756 * configuration requests from vf unless match this mac 2757 */ 2758 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID; 2759 memcpy(bulletin->mac, mac, ETH_ALEN); 2760 2761 /* Post update on VF's bulletin board */ 2762 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2763 2764 /* release lock before checking return code */ 2765 mutex_unlock(&bp->vfdb->bulletin_mutex); 2766 2767 if (rc) { 2768 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2769 return rc; 2770 } 2771 2772 q_logical_state = 2773 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)); 2774 if (vf->state == VF_ENABLED && 2775 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { 2776 /* configure the mac in device on this vf's queue */ 2777 unsigned long ramrod_flags = 0; 2778 struct bnx2x_vlan_mac_obj *mac_obj; 2779 2780 /* User should be able to see failure reason in system logs */ 2781 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2782 return -EINVAL; 2783 2784 /* must lock vfpf channel to protect against vf flows */ 2785 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2786 2787 /* remove existing eth macs */ 2788 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2789 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true); 2790 if (rc) { 2791 BNX2X_ERR("failed to delete eth macs\n"); 2792 rc = -EINVAL; 2793 goto out; 2794 } 2795 2796 /* remove existing uc list macs */ 2797 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true); 2798 if (rc) { 2799 BNX2X_ERR("failed to delete uc_list macs\n"); 2800 rc = -EINVAL; 2801 goto out; 2802 } 2803 2804 /* configure the new mac to device */ 2805 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2806 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, 2807 BNX2X_ETH_MAC, &ramrod_flags); 2808 2809 out: 2810 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2811 } 2812 2813 return rc; 2814 } 2815 2816 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos) 2817 { 2818 struct bnx2x_queue_state_params q_params = {NULL}; 2819 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 2820 struct bnx2x_queue_update_params *update_params; 2821 struct pf_vf_bulletin_content *bulletin = NULL; 2822 struct bnx2x_rx_mode_ramrod_params rx_ramrod; 2823 struct bnx2x *bp = netdev_priv(dev); 2824 struct bnx2x_vlan_mac_obj *vlan_obj; 2825 unsigned long vlan_mac_flags = 0; 2826 unsigned long ramrod_flags = 0; 2827 struct bnx2x_virtf *vf = NULL; 2828 unsigned long accept_flags; 2829 int rc; 2830 2831 if (vlan > 4095) { 2832 BNX2X_ERR("illegal vlan value %d\n", vlan); 2833 return -EINVAL; 2834 } 2835 2836 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", 2837 vfidx, vlan, 0); 2838 2839 /* sanity and init */ 2840 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2841 if (rc) 2842 return rc; 2843 2844 /* update PF's copy of the VF's bulletin. No point in posting the vlan 2845 * to the VF since it doesn't have anything to do with it. But it useful 2846 * to store it here in case the VF is not up yet and we can only 2847 * configure the vlan later when it does. Treat vlan id 0 as remove the 2848 * Host tag. 2849 */ 2850 mutex_lock(&bp->vfdb->bulletin_mutex); 2851 2852 if (vlan > 0) 2853 bulletin->valid_bitmap |= 1 << VLAN_VALID; 2854 else 2855 bulletin->valid_bitmap &= ~(1 << VLAN_VALID); 2856 bulletin->vlan = vlan; 2857 2858 mutex_unlock(&bp->vfdb->bulletin_mutex); 2859 2860 /* is vf initialized and queue set up? */ 2861 if (vf->state != VF_ENABLED || 2862 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) != 2863 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2864 return rc; 2865 2866 /* User should be able to see error in system logs */ 2867 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2868 return -EINVAL; 2869 2870 /* must lock vfpf channel to protect against vf flows */ 2871 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2872 2873 /* remove existing vlans */ 2874 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2875 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2876 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, 2877 &ramrod_flags); 2878 if (rc) { 2879 BNX2X_ERR("failed to delete vlans\n"); 2880 rc = -EINVAL; 2881 goto out; 2882 } 2883 2884 /* need to remove/add the VF's accept_any_vlan bit */ 2885 accept_flags = bnx2x_leading_vfq(vf, accept_flags); 2886 if (vlan) 2887 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2888 else 2889 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2890 2891 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf, 2892 accept_flags); 2893 bnx2x_leading_vfq(vf, accept_flags) = accept_flags; 2894 bnx2x_config_rx_mode(bp, &rx_ramrod); 2895 2896 /* configure the new vlan to device */ 2897 memset(&ramrod_param, 0, sizeof(ramrod_param)); 2898 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2899 ramrod_param.vlan_mac_obj = vlan_obj; 2900 ramrod_param.ramrod_flags = ramrod_flags; 2901 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 2902 &ramrod_param.user_req.vlan_mac_flags); 2903 ramrod_param.user_req.u.vlan.vlan = vlan; 2904 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 2905 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 2906 if (rc) { 2907 BNX2X_ERR("failed to configure vlan\n"); 2908 rc = -EINVAL; 2909 goto out; 2910 } 2911 2912 /* send queue update ramrod to configure default vlan and silent 2913 * vlan removal 2914 */ 2915 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2916 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2917 q_params.q_obj = &bnx2x_leading_vfq(vf, sp_obj); 2918 update_params = &q_params.params.update; 2919 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 2920 &update_params->update_flags); 2921 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 2922 &update_params->update_flags); 2923 if (vlan == 0) { 2924 /* if vlan is 0 then we want to leave the VF traffic 2925 * untagged, and leave the incoming traffic untouched 2926 * (i.e. do not remove any vlan tags). 2927 */ 2928 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2929 &update_params->update_flags); 2930 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2931 &update_params->update_flags); 2932 } else { 2933 /* configure default vlan to vf queue and set silent 2934 * vlan removal (the vf remains unaware of this vlan). 2935 */ 2936 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2937 &update_params->update_flags); 2938 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2939 &update_params->update_flags); 2940 update_params->def_vlan = vlan; 2941 update_params->silent_removal_value = 2942 vlan & VLAN_VID_MASK; 2943 update_params->silent_removal_mask = VLAN_VID_MASK; 2944 } 2945 2946 /* Update the Queue state */ 2947 rc = bnx2x_queue_state_change(bp, &q_params); 2948 if (rc) { 2949 BNX2X_ERR("Failed to configure default VLAN\n"); 2950 goto out; 2951 } 2952 2953 2954 /* clear the flag indicating that this VF needs its vlan 2955 * (will only be set if the HV configured the Vlan before vf was 2956 * up and we were called because the VF came up later 2957 */ 2958 out: 2959 vf->cfg_flags &= ~VF_CFG_VLAN; 2960 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2961 2962 return rc; 2963 } 2964 2965 /* crc is the first field in the bulletin board. Compute the crc over the 2966 * entire bulletin board excluding the crc field itself. Use the length field 2967 * as the Bulletin Board was posted by a PF with possibly a different version 2968 * from the vf which will sample it. Therefore, the length is computed by the 2969 * PF and then used blindly by the VF. 2970 */ 2971 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin) 2972 { 2973 return crc32(BULLETIN_CRC_SEED, 2974 ((u8 *)bulletin) + sizeof(bulletin->crc), 2975 bulletin->length - sizeof(bulletin->crc)); 2976 } 2977 2978 /* Check for new posts on the bulletin board */ 2979 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) 2980 { 2981 struct pf_vf_bulletin_content *bulletin; 2982 int attempts; 2983 2984 /* sampling structure in mid post may result with corrupted data 2985 * validate crc to ensure coherency. 2986 */ 2987 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) { 2988 u32 crc; 2989 2990 /* sample the bulletin board */ 2991 memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin, 2992 sizeof(union pf_vf_bulletin)); 2993 2994 crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content); 2995 2996 if (bp->shadow_bulletin.content.crc == crc) 2997 break; 2998 2999 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n", 3000 bp->shadow_bulletin.content.crc, crc); 3001 } 3002 3003 if (attempts >= BULLETIN_ATTEMPTS) { 3004 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n", 3005 attempts); 3006 return PFVF_BULLETIN_CRC_ERR; 3007 } 3008 bulletin = &bp->shadow_bulletin.content; 3009 3010 /* bulletin board hasn't changed since last sample */ 3011 if (bp->old_bulletin.version == bulletin->version) 3012 return PFVF_BULLETIN_UNCHANGED; 3013 3014 /* the mac address in bulletin board is valid and is new */ 3015 if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID && 3016 !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) { 3017 /* update new mac to net device */ 3018 memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN); 3019 } 3020 3021 if (bulletin->valid_bitmap & (1 << LINK_VALID)) { 3022 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n", 3023 bulletin->link_speed, bulletin->link_flags); 3024 3025 bp->vf_link_vars.line_speed = bulletin->link_speed; 3026 bp->vf_link_vars.link_report_flags = 0; 3027 /* Link is down */ 3028 if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN) 3029 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, 3030 &bp->vf_link_vars.link_report_flags); 3031 /* Full DUPLEX */ 3032 if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX) 3033 __set_bit(BNX2X_LINK_REPORT_FD, 3034 &bp->vf_link_vars.link_report_flags); 3035 /* Rx Flow Control is ON */ 3036 if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON) 3037 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, 3038 &bp->vf_link_vars.link_report_flags); 3039 /* Tx Flow Control is ON */ 3040 if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON) 3041 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, 3042 &bp->vf_link_vars.link_report_flags); 3043 __bnx2x_link_report(bp); 3044 } 3045 3046 /* copy new bulletin board to bp */ 3047 memcpy(&bp->old_bulletin, bulletin, 3048 sizeof(struct pf_vf_bulletin_content)); 3049 3050 return PFVF_BULLETIN_UPDATED; 3051 } 3052 3053 void bnx2x_timer_sriov(struct bnx2x *bp) 3054 { 3055 bnx2x_sample_bulletin(bp); 3056 3057 /* if channel is down we need to self destruct */ 3058 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) 3059 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 3060 BNX2X_MSG_IOV); 3061 } 3062 3063 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) 3064 { 3065 /* vf doorbells are embedded within the regview */ 3066 return bp->regview + PXP_VF_ADDR_DB_START; 3067 } 3068 3069 void bnx2x_vf_pci_dealloc(struct bnx2x *bp) 3070 { 3071 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, 3072 sizeof(struct bnx2x_vf_mbx_msg)); 3073 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping, 3074 sizeof(union pf_vf_bulletin)); 3075 } 3076 3077 int bnx2x_vf_pci_alloc(struct bnx2x *bp) 3078 { 3079 mutex_init(&bp->vf2pf_mutex); 3080 3081 /* allocate vf2pf mailbox for vf to pf channel */ 3082 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping, 3083 sizeof(struct bnx2x_vf_mbx_msg)); 3084 if (!bp->vf2pf_mbox) 3085 goto alloc_mem_err; 3086 3087 /* allocate pf 2 vf bulletin board */ 3088 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping, 3089 sizeof(union pf_vf_bulletin)); 3090 if (!bp->pf2vf_bulletin) 3091 goto alloc_mem_err; 3092 3093 bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true); 3094 3095 return 0; 3096 3097 alloc_mem_err: 3098 bnx2x_vf_pci_dealloc(bp); 3099 return -ENOMEM; 3100 } 3101 3102 void bnx2x_iov_channel_down(struct bnx2x *bp) 3103 { 3104 int vf_idx; 3105 struct pf_vf_bulletin_content *bulletin; 3106 3107 if (!IS_SRIOV(bp)) 3108 return; 3109 3110 for_each_vf(bp, vf_idx) { 3111 /* locate this VFs bulletin board and update the channel down 3112 * bit 3113 */ 3114 bulletin = BP_VF_BULLETIN(bp, vf_idx); 3115 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN; 3116 3117 /* update vf bulletin board */ 3118 bnx2x_post_vf_bulletin(bp, vf_idx); 3119 } 3120 } 3121 3122 void bnx2x_iov_task(struct work_struct *work) 3123 { 3124 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work); 3125 3126 if (!netif_running(bp->dev)) 3127 return; 3128 3129 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR, 3130 &bp->iov_task_state)) 3131 bnx2x_vf_handle_flr_event(bp); 3132 3133 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG, 3134 &bp->iov_task_state)) 3135 bnx2x_vf_mbx(bp); 3136 } 3137 3138 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) 3139 { 3140 smp_mb__before_atomic(); 3141 set_bit(flag, &bp->iov_task_state); 3142 smp_mb__after_atomic(); 3143 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); 3144 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0); 3145 } 3146