1 /* bnx2x_sriov.c: Broadcom Everest network driver. 2 * 3 * Copyright 2009-2013 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 16 * Written by: Shmulik Ravid 17 * Ariel Elior <ariel.elior@qlogic.com> 18 * 19 */ 20 #include "bnx2x.h" 21 #include "bnx2x_init.h" 22 #include "bnx2x_cmn.h" 23 #include "bnx2x_sp.h" 24 #include <linux/crc32.h> 25 #include <linux/if_vlan.h> 26 27 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 28 struct bnx2x_virtf **vf, 29 struct pf_vf_bulletin_content **bulletin, 30 bool test_queue); 31 32 /* General service functions */ 33 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 34 u16 pf_id) 35 { 36 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 37 pf_id); 38 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 39 pf_id); 40 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 41 pf_id); 42 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 43 pf_id); 44 } 45 46 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 47 u8 enable) 48 { 49 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 50 enable); 51 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 52 enable); 53 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 54 enable); 55 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 56 enable); 57 } 58 59 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 60 { 61 int idx; 62 63 for_each_vf(bp, idx) 64 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid) 65 break; 66 return idx; 67 } 68 69 static 70 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid) 71 { 72 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid); 73 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL; 74 } 75 76 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf, 77 u8 igu_sb_id, u8 segment, u16 index, u8 op, 78 u8 update) 79 { 80 /* acking a VF sb through the PF - use the GRC */ 81 u32 ctl; 82 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 83 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 84 u32 func_encode = vf->abs_vfid; 85 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id; 86 struct igu_regular cmd_data = {0}; 87 88 cmd_data.sb_id_and_flags = 89 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 90 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 91 (update << IGU_REGULAR_BUPDATE_SHIFT) | 92 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 93 94 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 95 func_encode << IGU_CTRL_REG_FID_SHIFT | 96 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 97 98 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 99 cmd_data.sb_id_and_flags, igu_addr_data); 100 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); 101 mmiowb(); 102 barrier(); 103 104 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 105 ctl, igu_addr_ctl); 106 REG_WR(bp, igu_addr_ctl, ctl); 107 mmiowb(); 108 barrier(); 109 } 110 111 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp, 112 struct bnx2x_virtf *vf, 113 bool print_err) 114 { 115 if (!bnx2x_leading_vfq(vf, sp_initialized)) { 116 if (print_err) 117 BNX2X_ERR("Slowpath objects not yet initialized!\n"); 118 else 119 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n"); 120 return false; 121 } 122 return true; 123 } 124 125 /* VFOP operations states */ 126 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf, 127 struct bnx2x_queue_init_params *init_params, 128 struct bnx2x_queue_setup_params *setup_params, 129 u16 q_idx, u16 sb_idx) 130 { 131 DP(BNX2X_MSG_IOV, 132 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d", 133 vf->abs_vfid, 134 q_idx, 135 sb_idx, 136 init_params->tx.sb_cq_index, 137 init_params->tx.hc_rate, 138 setup_params->flags, 139 setup_params->txq_params.traffic_type); 140 } 141 142 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf, 143 struct bnx2x_queue_init_params *init_params, 144 struct bnx2x_queue_setup_params *setup_params, 145 u16 q_idx, u16 sb_idx) 146 { 147 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params; 148 149 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n" 150 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n", 151 vf->abs_vfid, 152 q_idx, 153 sb_idx, 154 init_params->rx.sb_cq_index, 155 init_params->rx.hc_rate, 156 setup_params->gen_params.mtu, 157 rxq_params->buf_sz, 158 rxq_params->sge_buf_sz, 159 rxq_params->max_sges_pkt, 160 rxq_params->tpa_agg_sz, 161 setup_params->flags, 162 rxq_params->drop_flags, 163 rxq_params->cache_line_log); 164 } 165 166 void bnx2x_vfop_qctor_prep(struct bnx2x *bp, 167 struct bnx2x_virtf *vf, 168 struct bnx2x_vf_queue *q, 169 struct bnx2x_vf_queue_construct_params *p, 170 unsigned long q_type) 171 { 172 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init; 173 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup; 174 175 /* INIT */ 176 177 /* Enable host coalescing in the transition to INIT state */ 178 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags)) 179 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags); 180 181 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags)) 182 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags); 183 184 /* FW SB ID */ 185 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 186 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 187 188 /* context */ 189 init_p->cxts[0] = q->cxt; 190 191 /* SETUP */ 192 193 /* Setup-op general parameters */ 194 setup_p->gen_params.spcl_id = vf->sp_cl_id; 195 setup_p->gen_params.stat_id = vfq_stat_id(vf, q); 196 197 /* Setup-op pause params: 198 * Nothing to do, the pause thresholds are set by default to 0 which 199 * effectively turns off the feature for this queue. We don't want 200 * one queue (VF) to interfering with another queue (another VF) 201 */ 202 if (vf->cfg_flags & VF_CFG_FW_FC) 203 BNX2X_ERR("No support for pause to VFs (abs_vfid: %d)\n", 204 vf->abs_vfid); 205 /* Setup-op flags: 206 * collect statistics, zero statistics, local-switching, security, 207 * OV for Flex10, RSS and MCAST for leading 208 */ 209 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags)) 210 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags); 211 212 /* for VFs, enable tx switching, bd coherency, and mac address 213 * anti-spoofing 214 */ 215 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags); 216 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags); 217 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags); 218 219 /* Setup-op rx parameters */ 220 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) { 221 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params; 222 223 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q); 224 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx); 225 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid); 226 227 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags)) 228 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES; 229 } 230 231 /* Setup-op tx parameters */ 232 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) { 233 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss; 234 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx); 235 } 236 } 237 238 static int bnx2x_vf_queue_create(struct bnx2x *bp, 239 struct bnx2x_virtf *vf, int qid, 240 struct bnx2x_vf_queue_construct_params *qctor) 241 { 242 struct bnx2x_queue_state_params *q_params; 243 int rc = 0; 244 245 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 246 247 /* Prepare ramrod information */ 248 q_params = &qctor->qstate; 249 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj); 250 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags); 251 252 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) == 253 BNX2X_Q_LOGICAL_STATE_ACTIVE) { 254 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n"); 255 goto out; 256 } 257 258 /* Run Queue 'construction' ramrods */ 259 q_params->cmd = BNX2X_Q_CMD_INIT; 260 rc = bnx2x_queue_state_change(bp, q_params); 261 if (rc) 262 goto out; 263 264 memcpy(&q_params->params.setup, &qctor->prep_qsetup, 265 sizeof(struct bnx2x_queue_setup_params)); 266 q_params->cmd = BNX2X_Q_CMD_SETUP; 267 rc = bnx2x_queue_state_change(bp, q_params); 268 if (rc) 269 goto out; 270 271 /* enable interrupts */ 272 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)), 273 USTORM_ID, 0, IGU_INT_ENABLE, 0); 274 out: 275 return rc; 276 } 277 278 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf, 279 int qid) 280 { 281 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT, 282 BNX2X_Q_CMD_TERMINATE, 283 BNX2X_Q_CMD_CFC_DEL}; 284 struct bnx2x_queue_state_params q_params; 285 int rc, i; 286 287 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 288 289 /* Prepare ramrod information */ 290 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params)); 291 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 292 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 293 294 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) == 295 BNX2X_Q_LOGICAL_STATE_STOPPED) { 296 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n"); 297 goto out; 298 } 299 300 /* Run Queue 'destruction' ramrods */ 301 for (i = 0; i < ARRAY_SIZE(cmds); i++) { 302 q_params.cmd = cmds[i]; 303 rc = bnx2x_queue_state_change(bp, &q_params); 304 if (rc) { 305 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]); 306 return rc; 307 } 308 } 309 out: 310 /* Clean Context */ 311 if (bnx2x_vfq(vf, qid, cxt)) { 312 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0; 313 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0; 314 } 315 316 return 0; 317 } 318 319 static void 320 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid) 321 { 322 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 323 if (vf) { 324 /* the first igu entry belonging to VFs of this PF */ 325 if (!BP_VFDB(bp)->first_vf_igu_entry) 326 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id; 327 328 /* the first igu entry belonging to this VF */ 329 if (!vf_sb_count(vf)) 330 vf->igu_base_id = igu_sb_id; 331 332 ++vf_sb_count(vf); 333 ++vf->sb_count; 334 } 335 BP_VFDB(bp)->vf_sbs_pool++; 336 } 337 338 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp, 339 struct bnx2x_vlan_mac_obj *obj, 340 atomic_t *counter) 341 { 342 struct list_head *pos; 343 int read_lock; 344 int cnt = 0; 345 346 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj); 347 if (read_lock) 348 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n"); 349 350 list_for_each(pos, &obj->head) 351 cnt++; 352 353 if (!read_lock) 354 bnx2x_vlan_mac_h_read_unlock(bp, obj); 355 356 atomic_set(counter, cnt); 357 } 358 359 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf, 360 int qid, bool drv_only, bool mac) 361 { 362 struct bnx2x_vlan_mac_ramrod_params ramrod; 363 int rc; 364 365 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid, 366 mac ? "MACs" : "VLANs"); 367 368 /* Prepare ramrod params */ 369 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 370 if (mac) { 371 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 372 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 373 } else { 374 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 375 &ramrod.user_req.vlan_mac_flags); 376 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 377 } 378 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL; 379 380 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 381 if (drv_only) 382 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 383 else 384 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 385 386 /* Start deleting */ 387 rc = ramrod.vlan_mac_obj->delete_all(bp, 388 ramrod.vlan_mac_obj, 389 &ramrod.user_req.vlan_mac_flags, 390 &ramrod.ramrod_flags); 391 if (rc) { 392 BNX2X_ERR("Failed to delete all %s\n", 393 mac ? "MACs" : "VLANs"); 394 return rc; 395 } 396 397 /* Clear the vlan counters */ 398 if (!mac) 399 atomic_set(&bnx2x_vfq(vf, qid, vlan_count), 0); 400 401 return 0; 402 } 403 404 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp, 405 struct bnx2x_virtf *vf, int qid, 406 struct bnx2x_vf_mac_vlan_filter *filter, 407 bool drv_only) 408 { 409 struct bnx2x_vlan_mac_ramrod_params ramrod; 410 int rc; 411 412 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n", 413 vf->abs_vfid, filter->add ? "Adding" : "Deleting", 414 filter->type == BNX2X_VF_FILTER_MAC ? "MAC" : "VLAN"); 415 416 /* Prepare ramrod params */ 417 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params)); 418 if (filter->type == BNX2X_VF_FILTER_VLAN) { 419 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 420 &ramrod.user_req.vlan_mac_flags); 421 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj); 422 ramrod.user_req.u.vlan.vlan = filter->vid; 423 } else { 424 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags); 425 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj); 426 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN); 427 } 428 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD : 429 BNX2X_VLAN_MAC_DEL; 430 431 /* Verify there are available vlan credits */ 432 if (filter->add && filter->type == BNX2X_VF_FILTER_VLAN && 433 (atomic_read(&bnx2x_vfq(vf, qid, vlan_count)) >= 434 vf_vlan_rules_cnt(vf))) { 435 BNX2X_ERR("No credits for vlan [%d >= %d]\n", 436 atomic_read(&bnx2x_vfq(vf, qid, vlan_count)), 437 vf_vlan_rules_cnt(vf)); 438 return -ENOMEM; 439 } 440 441 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags); 442 if (drv_only) 443 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags); 444 else 445 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 446 447 /* Add/Remove the filter */ 448 rc = bnx2x_config_vlan_mac(bp, &ramrod); 449 if (rc && rc != -EEXIST) { 450 BNX2X_ERR("Failed to %s %s\n", 451 filter->add ? "add" : "delete", 452 filter->type == BNX2X_VF_FILTER_MAC ? "MAC" : 453 "VLAN"); 454 return rc; 455 } 456 457 /* Update the vlan counters */ 458 if (filter->type == BNX2X_VF_FILTER_VLAN) 459 bnx2x_vf_vlan_credit(bp, ramrod.vlan_mac_obj, 460 &bnx2x_vfq(vf, qid, vlan_count)); 461 462 return 0; 463 } 464 465 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf, 466 struct bnx2x_vf_mac_vlan_filters *filters, 467 int qid, bool drv_only) 468 { 469 int rc = 0, i; 470 471 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 472 473 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 474 return -EINVAL; 475 476 /* Prepare ramrod params */ 477 for (i = 0; i < filters->count; i++) { 478 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, 479 &filters->filters[i], drv_only); 480 if (rc) 481 break; 482 } 483 484 /* Rollback if needed */ 485 if (i != filters->count) { 486 BNX2X_ERR("Managed only %d/%d filters - rolling back\n", 487 i, filters->count + 1); 488 while (--i >= 0) { 489 filters->filters[i].add = !filters->filters[i].add; 490 bnx2x_vf_mac_vlan_config(bp, vf, qid, 491 &filters->filters[i], 492 drv_only); 493 } 494 } 495 496 /* It's our responsibility to free the filters */ 497 kfree(filters); 498 499 return rc; 500 } 501 502 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid, 503 struct bnx2x_vf_queue_construct_params *qctor) 504 { 505 int rc; 506 507 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 508 509 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor); 510 if (rc) 511 goto op_err; 512 513 /* Configure vlan0 for leading queue */ 514 if (!qid) { 515 struct bnx2x_vf_mac_vlan_filter filter; 516 517 memset(&filter, 0, sizeof(struct bnx2x_vf_mac_vlan_filter)); 518 filter.type = BNX2X_VF_FILTER_VLAN; 519 filter.add = true; 520 filter.vid = 0; 521 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid, &filter, false); 522 if (rc) 523 goto op_err; 524 } 525 526 /* Schedule the configuration of any pending vlan filters */ 527 vf->cfg_flags |= VF_CFG_VLAN; 528 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN, 529 BNX2X_MSG_IOV); 530 return 0; 531 op_err: 532 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 533 return rc; 534 } 535 536 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf, 537 int qid) 538 { 539 int rc; 540 541 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 542 543 /* If needed, clean the filtering data base */ 544 if ((qid == LEADING_IDX) && 545 bnx2x_validate_vf_sp_objs(bp, vf, false)) { 546 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, false); 547 if (rc) 548 goto op_err; 549 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true, true); 550 if (rc) 551 goto op_err; 552 } 553 554 /* Terminate queue */ 555 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) { 556 struct bnx2x_queue_state_params qstate; 557 558 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 559 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 560 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED; 561 qstate.cmd = BNX2X_Q_CMD_TERMINATE; 562 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 563 rc = bnx2x_queue_state_change(bp, &qstate); 564 if (rc) 565 goto op_err; 566 } 567 568 return 0; 569 op_err: 570 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc); 571 return rc; 572 } 573 574 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf, 575 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only) 576 { 577 struct bnx2x_mcast_list_elem *mc = NULL; 578 struct bnx2x_mcast_ramrod_params mcast; 579 int rc, i; 580 581 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 582 583 /* Prepare Multicast command */ 584 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params)); 585 mcast.mcast_obj = &vf->mcast_obj; 586 if (drv_only) 587 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags); 588 else 589 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags); 590 if (mc_num) { 591 mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem), 592 GFP_KERNEL); 593 if (!mc) { 594 BNX2X_ERR("Cannot Configure mulicasts due to lack of memory\n"); 595 return -ENOMEM; 596 } 597 } 598 599 /* clear existing mcasts */ 600 mcast.mcast_list_len = vf->mcast_list_len; 601 vf->mcast_list_len = mc_num; 602 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL); 603 if (rc) { 604 BNX2X_ERR("Failed to remove multicasts\n"); 605 kfree(mc); 606 return rc; 607 } 608 609 /* update mcast list on the ramrod params */ 610 if (mc_num) { 611 INIT_LIST_HEAD(&mcast.mcast_list); 612 for (i = 0; i < mc_num; i++) { 613 mc[i].mac = mcasts[i]; 614 list_add_tail(&mc[i].link, 615 &mcast.mcast_list); 616 } 617 618 /* add new mcasts */ 619 mcast.mcast_list_len = mc_num; 620 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_ADD); 621 if (rc) 622 BNX2X_ERR("Faled to add multicasts\n"); 623 kfree(mc); 624 } 625 626 return rc; 627 } 628 629 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid, 630 struct bnx2x_rx_mode_ramrod_params *ramrod, 631 struct bnx2x_virtf *vf, 632 unsigned long accept_flags) 633 { 634 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid); 635 636 memset(ramrod, 0, sizeof(*ramrod)); 637 ramrod->cid = vfq->cid; 638 ramrod->cl_id = vfq_cl_id(vf, vfq); 639 ramrod->rx_mode_obj = &bp->rx_mode_obj; 640 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid); 641 ramrod->rx_accept_flags = accept_flags; 642 ramrod->tx_accept_flags = accept_flags; 643 ramrod->pstate = &vf->filter_state; 644 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING; 645 646 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 647 set_bit(RAMROD_RX, &ramrod->ramrod_flags); 648 set_bit(RAMROD_TX, &ramrod->ramrod_flags); 649 650 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2); 651 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2); 652 } 653 654 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf, 655 int qid, unsigned long accept_flags) 656 { 657 struct bnx2x_rx_mode_ramrod_params ramrod; 658 659 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 660 661 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags); 662 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags); 663 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags; 664 return bnx2x_config_rx_mode(bp, &ramrod); 665 } 666 667 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid) 668 { 669 int rc; 670 671 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid); 672 673 /* Remove all classification configuration for leading queue */ 674 if (qid == LEADING_IDX) { 675 rc = bnx2x_vf_rxmode(bp, vf, qid, 0); 676 if (rc) 677 goto op_err; 678 679 /* Remove filtering if feasible */ 680 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) { 681 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 682 false, false); 683 if (rc) 684 goto op_err; 685 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, 686 false, true); 687 if (rc) 688 goto op_err; 689 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false); 690 if (rc) 691 goto op_err; 692 } 693 } 694 695 /* Destroy queue */ 696 rc = bnx2x_vf_queue_destroy(bp, vf, qid); 697 if (rc) 698 goto op_err; 699 return rc; 700 op_err: 701 BNX2X_ERR("vf[%d:%d] error: rc %d\n", 702 vf->abs_vfid, qid, rc); 703 return rc; 704 } 705 706 /* VF enable primitives 707 * when pretend is required the caller is responsible 708 * for calling pretend prior to calling these routines 709 */ 710 711 /* internal vf enable - until vf is enabled internally all transactions 712 * are blocked. This routine should always be called last with pretend. 713 */ 714 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable) 715 { 716 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); 717 } 718 719 /* clears vf error in all semi blocks */ 720 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid) 721 { 722 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); 723 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); 724 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); 725 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); 726 } 727 728 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid) 729 { 730 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5; 731 u32 was_err_reg = 0; 732 733 switch (was_err_group) { 734 case 0: 735 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR; 736 break; 737 case 1: 738 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR; 739 break; 740 case 2: 741 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR; 742 break; 743 case 3: 744 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR; 745 break; 746 } 747 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); 748 } 749 750 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf) 751 { 752 int i; 753 u32 val; 754 755 /* Set VF masks and configuration - pretend */ 756 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 757 758 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 759 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 760 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 761 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 762 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 763 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 764 765 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 766 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN); 767 if (vf->cfg_flags & VF_CFG_INT_SIMD) 768 val |= IGU_VF_CONF_SINGLE_ISR_EN; 769 val &= ~IGU_VF_CONF_PARENT_MASK; 770 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT; 771 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 772 773 DP(BNX2X_MSG_IOV, 774 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n", 775 vf->abs_vfid, val); 776 777 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 778 779 /* iterate over all queues, clear sb consumer */ 780 for (i = 0; i < vf_sb_count(vf); i++) { 781 u8 igu_sb_id = vf_igu_sb(vf, i); 782 783 /* zero prod memory */ 784 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); 785 786 /* clear sb state machine */ 787 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id, 788 false /* VF */); 789 790 /* disable + update */ 791 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0, 792 IGU_INT_DISABLE, 1); 793 } 794 } 795 796 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid) 797 { 798 /* set the VF-PF association in the FW */ 799 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp)); 800 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1); 801 802 /* clear vf errors*/ 803 bnx2x_vf_semi_clear_err(bp, abs_vfid); 804 bnx2x_vf_pglue_clear_err(bp, abs_vfid); 805 806 /* internal vf-enable - pretend */ 807 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid)); 808 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid); 809 bnx2x_vf_enable_internal(bp, true); 810 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 811 } 812 813 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf) 814 { 815 /* Reset vf in IGU interrupts are still disabled */ 816 bnx2x_vf_igu_reset(bp, vf); 817 818 /* pretend to enable the vf with the PBF */ 819 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 820 REG_WR(bp, PBF_REG_DISABLE_VF, 0); 821 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 822 } 823 824 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid) 825 { 826 struct pci_dev *dev; 827 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 828 829 if (!vf) 830 return false; 831 832 dev = pci_get_bus_and_slot(vf->bus, vf->devfn); 833 if (dev) 834 return bnx2x_is_pcie_pending(dev); 835 return false; 836 } 837 838 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid) 839 { 840 /* Verify no pending pci transactions */ 841 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid)) 842 BNX2X_ERR("PCIE Transactions still pending\n"); 843 844 return 0; 845 } 846 847 static void bnx2x_iov_re_set_vlan_filters(struct bnx2x *bp, 848 struct bnx2x_virtf *vf, 849 int new) 850 { 851 int num = vf_vlan_rules_cnt(vf); 852 int diff = new - num; 853 bool rc = true; 854 855 DP(BNX2X_MSG_IOV, "vf[%d] - %d vlan filter credits [previously %d]\n", 856 vf->abs_vfid, new, num); 857 858 if (diff > 0) 859 rc = bp->vlans_pool.get(&bp->vlans_pool, diff); 860 else if (diff < 0) 861 rc = bp->vlans_pool.put(&bp->vlans_pool, -diff); 862 863 if (rc) 864 vf_vlan_rules_cnt(vf) = new; 865 else 866 DP(BNX2X_MSG_IOV, "vf[%d] - Failed to configure vlan filter credits change\n", 867 vf->abs_vfid); 868 } 869 870 /* must be called after the number of PF queues and the number of VFs are 871 * both known 872 */ 873 static void 874 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 875 { 876 struct vf_pf_resc_request *resc = &vf->alloc_resc; 877 u16 vlan_count = 0; 878 879 /* will be set only during VF-ACQUIRE */ 880 resc->num_rxqs = 0; 881 resc->num_txqs = 0; 882 883 /* no credit calculations for macs (just yet) */ 884 resc->num_mac_filters = 1; 885 886 /* divvy up vlan rules */ 887 bnx2x_iov_re_set_vlan_filters(bp, vf, 0); 888 vlan_count = bp->vlans_pool.check(&bp->vlans_pool); 889 vlan_count = 1 << ilog2(vlan_count); 890 bnx2x_iov_re_set_vlan_filters(bp, vf, 891 vlan_count / BNX2X_NR_VIRTFN(bp)); 892 893 /* no real limitation */ 894 resc->num_mc_filters = 0; 895 896 /* num_sbs already set */ 897 resc->num_sbs = vf->sb_count; 898 } 899 900 /* FLR routines: */ 901 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf) 902 { 903 /* reset the state variables */ 904 bnx2x_iov_static_resc(bp, vf); 905 vf->state = VF_FREE; 906 } 907 908 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf) 909 { 910 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 911 912 /* DQ usage counter */ 913 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 914 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT, 915 "DQ VF usage counter timed out", 916 poll_cnt); 917 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 918 919 /* FW cleanup command - poll for the results */ 920 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid), 921 poll_cnt)) 922 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid); 923 924 /* verify TX hw is flushed */ 925 bnx2x_tx_hw_flushed(bp, poll_cnt); 926 } 927 928 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf) 929 { 930 int rc, i; 931 932 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 933 934 /* the cleanup operations are valid if and only if the VF 935 * was first acquired. 936 */ 937 for (i = 0; i < vf_rxq_count(vf); i++) { 938 rc = bnx2x_vf_queue_flr(bp, vf, i); 939 if (rc) 940 goto out; 941 } 942 943 /* remove multicasts */ 944 bnx2x_vf_mcast(bp, vf, NULL, 0, true); 945 946 /* dispatch final cleanup and wait for HW queues to flush */ 947 bnx2x_vf_flr_clnup_hw(bp, vf); 948 949 /* release VF resources */ 950 bnx2x_vf_free_resc(bp, vf); 951 952 /* re-open the mailbox */ 953 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 954 return; 955 out: 956 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n", 957 vf->abs_vfid, i, rc); 958 } 959 960 static void bnx2x_vf_flr_clnup(struct bnx2x *bp) 961 { 962 struct bnx2x_virtf *vf; 963 int i; 964 965 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) { 966 /* VF should be RESET & in FLR cleanup states */ 967 if (bnx2x_vf(bp, i, state) != VF_RESET || 968 !bnx2x_vf(bp, i, flr_clnup_stage)) 969 continue; 970 971 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", 972 i, BNX2X_NR_VIRTFN(bp)); 973 974 vf = BP_VF(bp, i); 975 976 /* lock the vf pf channel */ 977 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 978 979 /* invoke the VF FLR SM */ 980 bnx2x_vf_flr(bp, vf); 981 982 /* mark the VF to be ACKED and continue */ 983 vf->flr_clnup_stage = false; 984 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR); 985 } 986 987 /* Acknowledge the handled VFs. 988 * we are acknowledge all the vfs which an flr was requested for, even 989 * if amongst them there are such that we never opened, since the mcp 990 * will interrupt us immediately again if we only ack some of the bits, 991 * resulting in an endless loop. This can happen for example in KVM 992 * where an 'all ones' flr request is sometimes given by hyper visor 993 */ 994 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n", 995 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 996 for (i = 0; i < FLRD_VFS_DWORDS; i++) 997 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 998 bp->vfdb->flrd_vfs[i]); 999 1000 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0); 1001 1002 /* clear the acked bits - better yet if the MCP implemented 1003 * write to clear semantics 1004 */ 1005 for (i = 0; i < FLRD_VFS_DWORDS; i++) 1006 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0); 1007 } 1008 1009 void bnx2x_vf_handle_flr_event(struct bnx2x *bp) 1010 { 1011 int i; 1012 1013 /* Read FLR'd VFs */ 1014 for (i = 0; i < FLRD_VFS_DWORDS; i++) 1015 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]); 1016 1017 DP(BNX2X_MSG_MCP, 1018 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n", 1019 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]); 1020 1021 for_each_vf(bp, i) { 1022 struct bnx2x_virtf *vf = BP_VF(bp, i); 1023 u32 reset = 0; 1024 1025 if (vf->abs_vfid < 32) 1026 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid); 1027 else 1028 reset = bp->vfdb->flrd_vfs[1] & 1029 (1 << (vf->abs_vfid - 32)); 1030 1031 if (reset) { 1032 /* set as reset and ready for cleanup */ 1033 vf->state = VF_RESET; 1034 vf->flr_clnup_stage = true; 1035 1036 DP(BNX2X_MSG_IOV, 1037 "Initiating Final cleanup for VF %d\n", 1038 vf->abs_vfid); 1039 } 1040 } 1041 1042 /* do the FLR cleanup for all marked VFs*/ 1043 bnx2x_vf_flr_clnup(bp); 1044 } 1045 1046 /* IOV global initialization routines */ 1047 void bnx2x_iov_init_dq(struct bnx2x *bp) 1048 { 1049 if (!IS_SRIOV(bp)) 1050 return; 1051 1052 /* Set the DQ such that the CID reflect the abs_vfid */ 1053 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); 1054 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 1055 1056 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to 1057 * the PF L2 queues 1058 */ 1059 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 1060 1061 /* The VF window size is the log2 of the max number of CIDs per VF */ 1062 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 1063 1064 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 1065 * the Pf doorbell size although the 2 are independent. 1066 */ 1067 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); 1068 1069 /* No security checks for now - 1070 * configure single rule (out of 16) mask = 0x1, value = 0x0, 1071 * CID range 0 - 0x1ffff 1072 */ 1073 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); 1074 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); 1075 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 1076 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 1077 1078 /* set the VF doorbell threshold. This threshold represents the amount 1079 * of doorbells allowed in the main DORQ fifo for a specific VF. 1080 */ 1081 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64); 1082 } 1083 1084 void bnx2x_iov_init_dmae(struct bnx2x *bp) 1085 { 1086 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV)) 1087 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); 1088 } 1089 1090 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid) 1091 { 1092 struct pci_dev *dev = bp->pdev; 1093 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1094 1095 return dev->bus->number + ((dev->devfn + iov->offset + 1096 iov->stride * vfid) >> 8); 1097 } 1098 1099 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid) 1100 { 1101 struct pci_dev *dev = bp->pdev; 1102 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1103 1104 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff; 1105 } 1106 1107 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf) 1108 { 1109 int i, n; 1110 struct pci_dev *dev = bp->pdev; 1111 struct bnx2x_sriov *iov = &bp->vfdb->sriov; 1112 1113 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) { 1114 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i); 1115 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i); 1116 1117 size /= iov->total; 1118 vf->bars[n].bar = start + size * vf->abs_vfid; 1119 vf->bars[n].size = size; 1120 } 1121 } 1122 1123 static int bnx2x_ari_enabled(struct pci_dev *dev) 1124 { 1125 return dev->bus->self && dev->bus->self->ari_enabled; 1126 } 1127 1128 static int 1129 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp) 1130 { 1131 int sb_id; 1132 u32 val; 1133 u8 fid, current_pf = 0; 1134 1135 /* IGU in normal mode - read CAM */ 1136 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) { 1137 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); 1138 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 1139 continue; 1140 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); 1141 if (fid & IGU_FID_ENCODE_IS_PF) 1142 current_pf = fid & IGU_FID_PF_NUM_MASK; 1143 else if (current_pf == BP_FUNC(bp)) 1144 bnx2x_vf_set_igu_info(bp, sb_id, 1145 (fid & IGU_FID_VF_NUM_MASK)); 1146 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", 1147 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"), 1148 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) : 1149 (fid & IGU_FID_VF_NUM_MASK)), sb_id, 1150 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)); 1151 } 1152 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool); 1153 return BP_VFDB(bp)->vf_sbs_pool; 1154 } 1155 1156 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp) 1157 { 1158 if (bp->vfdb) { 1159 kfree(bp->vfdb->vfqs); 1160 kfree(bp->vfdb->vfs); 1161 kfree(bp->vfdb); 1162 } 1163 bp->vfdb = NULL; 1164 } 1165 1166 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1167 { 1168 int pos; 1169 struct pci_dev *dev = bp->pdev; 1170 1171 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 1172 if (!pos) { 1173 BNX2X_ERR("failed to find SRIOV capability in device\n"); 1174 return -ENODEV; 1175 } 1176 1177 iov->pos = pos; 1178 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos); 1179 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl); 1180 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total); 1181 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial); 1182 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset); 1183 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride); 1184 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz); 1185 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap); 1186 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); 1187 1188 return 0; 1189 } 1190 1191 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov) 1192 { 1193 u32 val; 1194 1195 /* read the SRIOV capability structure 1196 * The fields can be read via configuration read or 1197 * directly from the device (starting at offset PCICFG_OFFSET) 1198 */ 1199 if (bnx2x_sriov_pci_cfg_info(bp, iov)) 1200 return -ENODEV; 1201 1202 /* get the number of SRIOV bars */ 1203 iov->nres = 0; 1204 1205 /* read the first_vfid */ 1206 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 1207 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK) 1208 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp)); 1209 1210 DP(BNX2X_MSG_IOV, 1211 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n", 1212 BP_FUNC(bp), 1213 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total, 1214 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz); 1215 1216 return 0; 1217 } 1218 1219 /* must be called after PF bars are mapped */ 1220 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param, 1221 int num_vfs_param) 1222 { 1223 int err, i; 1224 struct bnx2x_sriov *iov; 1225 struct pci_dev *dev = bp->pdev; 1226 1227 bp->vfdb = NULL; 1228 1229 /* verify is pf */ 1230 if (IS_VF(bp)) 1231 return 0; 1232 1233 /* verify sriov capability is present in configuration space */ 1234 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV)) 1235 return 0; 1236 1237 /* verify chip revision */ 1238 if (CHIP_IS_E1x(bp)) 1239 return 0; 1240 1241 /* check if SRIOV support is turned off */ 1242 if (!num_vfs_param) 1243 return 0; 1244 1245 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */ 1246 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) { 1247 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n", 1248 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID); 1249 return 0; 1250 } 1251 1252 /* SRIOV can be enabled only with MSIX */ 1253 if (int_mode_param == BNX2X_INT_MODE_MSI || 1254 int_mode_param == BNX2X_INT_MODE_INTX) { 1255 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n"); 1256 return 0; 1257 } 1258 1259 err = -EIO; 1260 /* verify ari is enabled */ 1261 if (!bnx2x_ari_enabled(bp->pdev)) { 1262 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n"); 1263 return 0; 1264 } 1265 1266 /* verify igu is in normal mode */ 1267 if (CHIP_INT_MODE_IS_BC(bp)) { 1268 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n"); 1269 return 0; 1270 } 1271 1272 /* allocate the vfs database */ 1273 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL); 1274 if (!bp->vfdb) { 1275 BNX2X_ERR("failed to allocate vf database\n"); 1276 err = -ENOMEM; 1277 goto failed; 1278 } 1279 1280 /* get the sriov info - Linux already collected all the pertinent 1281 * information, however the sriov structure is for the private use 1282 * of the pci module. Also we want this information regardless 1283 * of the hyper-visor. 1284 */ 1285 iov = &(bp->vfdb->sriov); 1286 err = bnx2x_sriov_info(bp, iov); 1287 if (err) 1288 goto failed; 1289 1290 /* SR-IOV capability was enabled but there are no VFs*/ 1291 if (iov->total == 0) 1292 goto failed; 1293 1294 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param); 1295 1296 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n", 1297 num_vfs_param, iov->nr_virtfn); 1298 1299 /* allocate the vf array */ 1300 bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) * 1301 BNX2X_NR_VIRTFN(bp), GFP_KERNEL); 1302 if (!bp->vfdb->vfs) { 1303 BNX2X_ERR("failed to allocate vf array\n"); 1304 err = -ENOMEM; 1305 goto failed; 1306 } 1307 1308 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */ 1309 for_each_vf(bp, i) { 1310 bnx2x_vf(bp, i, index) = i; 1311 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i; 1312 bnx2x_vf(bp, i, state) = VF_FREE; 1313 mutex_init(&bnx2x_vf(bp, i, op_mutex)); 1314 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE; 1315 } 1316 1317 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */ 1318 if (!bnx2x_get_vf_igu_cam_info(bp)) { 1319 BNX2X_ERR("No entries in IGU CAM for vfs\n"); 1320 err = -EINVAL; 1321 goto failed; 1322 } 1323 1324 /* allocate the queue arrays for all VFs */ 1325 bp->vfdb->vfqs = kzalloc( 1326 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue), 1327 GFP_KERNEL); 1328 1329 if (!bp->vfdb->vfqs) { 1330 BNX2X_ERR("failed to allocate vf queue array\n"); 1331 err = -ENOMEM; 1332 goto failed; 1333 } 1334 1335 /* Prepare the VFs event synchronization mechanism */ 1336 mutex_init(&bp->vfdb->event_mutex); 1337 1338 mutex_init(&bp->vfdb->bulletin_mutex); 1339 1340 return 0; 1341 failed: 1342 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err); 1343 __bnx2x_iov_free_vfdb(bp); 1344 return err; 1345 } 1346 1347 void bnx2x_iov_remove_one(struct bnx2x *bp) 1348 { 1349 int vf_idx; 1350 1351 /* if SRIOV is not enabled there's nothing to do */ 1352 if (!IS_SRIOV(bp)) 1353 return; 1354 1355 DP(BNX2X_MSG_IOV, "about to call disable sriov\n"); 1356 pci_disable_sriov(bp->pdev); 1357 DP(BNX2X_MSG_IOV, "sriov disabled\n"); 1358 1359 /* disable access to all VFs */ 1360 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) { 1361 bnx2x_pretend_func(bp, 1362 HW_VF_HANDLE(bp, 1363 bp->vfdb->sriov.first_vf_in_pf + 1364 vf_idx)); 1365 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n", 1366 bp->vfdb->sriov.first_vf_in_pf + vf_idx); 1367 bnx2x_vf_enable_internal(bp, 0); 1368 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 1369 } 1370 1371 /* free vf database */ 1372 __bnx2x_iov_free_vfdb(bp); 1373 } 1374 1375 void bnx2x_iov_free_mem(struct bnx2x *bp) 1376 { 1377 int i; 1378 1379 if (!IS_SRIOV(bp)) 1380 return; 1381 1382 /* free vfs hw contexts */ 1383 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1384 struct hw_dma *cxt = &bp->vfdb->context[i]; 1385 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size); 1386 } 1387 1388 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr, 1389 BP_VFDB(bp)->sp_dma.mapping, 1390 BP_VFDB(bp)->sp_dma.size); 1391 1392 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr, 1393 BP_VF_MBX_DMA(bp)->mapping, 1394 BP_VF_MBX_DMA(bp)->size); 1395 1396 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr, 1397 BP_VF_BULLETIN_DMA(bp)->mapping, 1398 BP_VF_BULLETIN_DMA(bp)->size); 1399 } 1400 1401 int bnx2x_iov_alloc_mem(struct bnx2x *bp) 1402 { 1403 size_t tot_size; 1404 int i, rc = 0; 1405 1406 if (!IS_SRIOV(bp)) 1407 return rc; 1408 1409 /* allocate vfs hw contexts */ 1410 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) * 1411 BNX2X_CIDS_PER_VF * sizeof(union cdu_context); 1412 1413 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1414 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i); 1415 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ); 1416 1417 if (cxt->size) { 1418 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size); 1419 if (!cxt->addr) 1420 goto alloc_mem_err; 1421 } else { 1422 cxt->addr = NULL; 1423 cxt->mapping = 0; 1424 } 1425 tot_size -= cxt->size; 1426 } 1427 1428 /* allocate vfs ramrods dma memory - client_init and set_mac */ 1429 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp); 1430 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping, 1431 tot_size); 1432 if (!BP_VFDB(bp)->sp_dma.addr) 1433 goto alloc_mem_err; 1434 BP_VFDB(bp)->sp_dma.size = tot_size; 1435 1436 /* allocate mailboxes */ 1437 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE; 1438 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping, 1439 tot_size); 1440 if (!BP_VF_MBX_DMA(bp)->addr) 1441 goto alloc_mem_err; 1442 1443 BP_VF_MBX_DMA(bp)->size = tot_size; 1444 1445 /* allocate local bulletin boards */ 1446 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE; 1447 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping, 1448 tot_size); 1449 if (!BP_VF_BULLETIN_DMA(bp)->addr) 1450 goto alloc_mem_err; 1451 1452 BP_VF_BULLETIN_DMA(bp)->size = tot_size; 1453 1454 return 0; 1455 1456 alloc_mem_err: 1457 return -ENOMEM; 1458 } 1459 1460 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf, 1461 struct bnx2x_vf_queue *q) 1462 { 1463 u8 cl_id = vfq_cl_id(vf, q); 1464 u8 func_id = FW_VF_HANDLE(vf->abs_vfid); 1465 unsigned long q_type = 0; 1466 1467 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1468 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1469 1470 /* Queue State object */ 1471 bnx2x_init_queue_obj(bp, &q->sp_obj, 1472 cl_id, &q->cid, 1, func_id, 1473 bnx2x_vf_sp(bp, vf, q_data), 1474 bnx2x_vf_sp_map(bp, vf, q_data), 1475 q_type); 1476 1477 /* sp indication is set only when vlan/mac/etc. are initialized */ 1478 q->sp_initialized = false; 1479 1480 DP(BNX2X_MSG_IOV, 1481 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n", 1482 vf->abs_vfid, q->sp_obj.func_id, q->cid); 1483 } 1484 1485 static int bnx2x_max_speed_cap(struct bnx2x *bp) 1486 { 1487 u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)]; 1488 1489 if (supported & 1490 (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full)) 1491 return 20000; 1492 1493 return 10000; /* assume lowest supported speed is 10G */ 1494 } 1495 1496 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx) 1497 { 1498 struct bnx2x_link_report_data *state = &bp->last_reported_link; 1499 struct pf_vf_bulletin_content *bulletin; 1500 struct bnx2x_virtf *vf; 1501 bool update = true; 1502 int rc = 0; 1503 1504 /* sanity and init */ 1505 rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false); 1506 if (rc) 1507 return rc; 1508 1509 mutex_lock(&bp->vfdb->bulletin_mutex); 1510 1511 if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) { 1512 bulletin->valid_bitmap |= 1 << LINK_VALID; 1513 1514 bulletin->link_speed = state->line_speed; 1515 bulletin->link_flags = 0; 1516 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1517 &state->link_report_flags)) 1518 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1519 if (test_bit(BNX2X_LINK_REPORT_FD, 1520 &state->link_report_flags)) 1521 bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX; 1522 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON, 1523 &state->link_report_flags)) 1524 bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON; 1525 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON, 1526 &state->link_report_flags)) 1527 bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON; 1528 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE && 1529 !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1530 bulletin->valid_bitmap |= 1 << LINK_VALID; 1531 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN; 1532 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE && 1533 (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) { 1534 bulletin->valid_bitmap |= 1 << LINK_VALID; 1535 bulletin->link_speed = bnx2x_max_speed_cap(bp); 1536 bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN; 1537 } else { 1538 update = false; 1539 } 1540 1541 if (update) { 1542 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV, 1543 "vf %d mode %u speed %d flags %x\n", idx, 1544 vf->link_cfg, bulletin->link_speed, bulletin->link_flags); 1545 1546 /* Post update on VF's bulletin board */ 1547 rc = bnx2x_post_vf_bulletin(bp, idx); 1548 if (rc) { 1549 BNX2X_ERR("failed to update VF[%d] bulletin\n", idx); 1550 goto out; 1551 } 1552 } 1553 1554 out: 1555 mutex_unlock(&bp->vfdb->bulletin_mutex); 1556 return rc; 1557 } 1558 1559 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state) 1560 { 1561 struct bnx2x *bp = netdev_priv(dev); 1562 struct bnx2x_virtf *vf = BP_VF(bp, idx); 1563 1564 if (!vf) 1565 return -EINVAL; 1566 1567 if (vf->link_cfg == link_state) 1568 return 0; /* nothing todo */ 1569 1570 vf->link_cfg = link_state; 1571 1572 return bnx2x_iov_link_update_vf(bp, idx); 1573 } 1574 1575 void bnx2x_iov_link_update(struct bnx2x *bp) 1576 { 1577 int vfid; 1578 1579 if (!IS_SRIOV(bp)) 1580 return; 1581 1582 for_each_vf(bp, vfid) 1583 bnx2x_iov_link_update_vf(bp, vfid); 1584 } 1585 1586 /* called by bnx2x_nic_load */ 1587 int bnx2x_iov_nic_init(struct bnx2x *bp) 1588 { 1589 int vfid; 1590 1591 if (!IS_SRIOV(bp)) { 1592 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n"); 1593 return 0; 1594 } 1595 1596 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn); 1597 1598 /* let FLR complete ... */ 1599 msleep(100); 1600 1601 /* initialize vf database */ 1602 for_each_vf(bp, vfid) { 1603 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1604 1605 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) * 1606 BNX2X_CIDS_PER_VF; 1607 1608 union cdu_context *base_cxt = (union cdu_context *) 1609 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 1610 (base_vf_cid & (ILT_PAGE_CIDS-1)); 1611 1612 DP(BNX2X_MSG_IOV, 1613 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n", 1614 vf->abs_vfid, vf_sb_count(vf), base_vf_cid, 1615 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt); 1616 1617 /* init statically provisioned resources */ 1618 bnx2x_iov_static_resc(bp, vf); 1619 1620 /* queues are initialized during VF-ACQUIRE */ 1621 vf->filter_state = 0; 1622 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id); 1623 1624 /* init mcast object - This object will be re-initialized 1625 * during VF-ACQUIRE with the proper cl_id and cid. 1626 * It needs to be initialized here so that it can be safely 1627 * handled by a subsequent FLR flow. 1628 */ 1629 vf->mcast_list_len = 0; 1630 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF, 1631 0xFF, 0xFF, 0xFF, 1632 bnx2x_vf_sp(bp, vf, mcast_rdata), 1633 bnx2x_vf_sp_map(bp, vf, mcast_rdata), 1634 BNX2X_FILTER_MCAST_PENDING, 1635 &vf->filter_state, 1636 BNX2X_OBJ_TYPE_RX_TX); 1637 1638 /* set the mailbox message addresses */ 1639 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *) 1640 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid * 1641 MBX_MSG_ALIGNED_SIZE); 1642 1643 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping + 1644 vfid * MBX_MSG_ALIGNED_SIZE; 1645 1646 /* Enable vf mailbox */ 1647 bnx2x_vf_enable_mbx(bp, vf->abs_vfid); 1648 } 1649 1650 /* Final VF init */ 1651 for_each_vf(bp, vfid) { 1652 struct bnx2x_virtf *vf = BP_VF(bp, vfid); 1653 1654 /* fill in the BDF and bars */ 1655 vf->bus = bnx2x_vf_bus(bp, vfid); 1656 vf->devfn = bnx2x_vf_devfn(bp, vfid); 1657 bnx2x_vf_set_bars(bp, vf); 1658 1659 DP(BNX2X_MSG_IOV, 1660 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n", 1661 vf->abs_vfid, vf->bus, vf->devfn, 1662 (unsigned)vf->bars[0].bar, vf->bars[0].size, 1663 (unsigned)vf->bars[1].bar, vf->bars[1].size, 1664 (unsigned)vf->bars[2].bar, vf->bars[2].size); 1665 } 1666 1667 return 0; 1668 } 1669 1670 /* called by bnx2x_chip_cleanup */ 1671 int bnx2x_iov_chip_cleanup(struct bnx2x *bp) 1672 { 1673 int i; 1674 1675 if (!IS_SRIOV(bp)) 1676 return 0; 1677 1678 /* release all the VFs */ 1679 for_each_vf(bp, i) 1680 bnx2x_vf_release(bp, BP_VF(bp, i)); 1681 1682 return 0; 1683 } 1684 1685 /* called by bnx2x_init_hw_func, returns the next ilt line */ 1686 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line) 1687 { 1688 int i; 1689 struct bnx2x_ilt *ilt = BP_ILT(bp); 1690 1691 if (!IS_SRIOV(bp)) 1692 return line; 1693 1694 /* set vfs ilt lines */ 1695 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) { 1696 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i); 1697 1698 ilt->lines[line+i].page = hw_cxt->addr; 1699 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 1700 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 1701 } 1702 return line + i; 1703 } 1704 1705 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid) 1706 { 1707 return ((cid >= BNX2X_FIRST_VF_CID) && 1708 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS)); 1709 } 1710 1711 static 1712 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp, 1713 struct bnx2x_vf_queue *vfq, 1714 union event_ring_elem *elem) 1715 { 1716 unsigned long ramrod_flags = 0; 1717 int rc = 0; 1718 1719 /* Always push next commands out, don't wait here */ 1720 set_bit(RAMROD_CONT, &ramrod_flags); 1721 1722 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 1723 case BNX2X_FILTER_MAC_PENDING: 1724 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem, 1725 &ramrod_flags); 1726 break; 1727 case BNX2X_FILTER_VLAN_PENDING: 1728 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem, 1729 &ramrod_flags); 1730 break; 1731 default: 1732 BNX2X_ERR("Unsupported classification command: %d\n", 1733 elem->message.data.eth_event.echo); 1734 return; 1735 } 1736 if (rc < 0) 1737 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 1738 else if (rc > 0) 1739 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n"); 1740 } 1741 1742 static 1743 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp, 1744 struct bnx2x_virtf *vf) 1745 { 1746 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 1747 int rc; 1748 1749 rparam.mcast_obj = &vf->mcast_obj; 1750 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw); 1751 1752 /* If there are pending mcast commands - send them */ 1753 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) { 1754 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 1755 if (rc < 0) 1756 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 1757 rc); 1758 } 1759 } 1760 1761 static 1762 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp, 1763 struct bnx2x_virtf *vf) 1764 { 1765 smp_mb__before_atomic(); 1766 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state); 1767 smp_mb__after_atomic(); 1768 } 1769 1770 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp, 1771 struct bnx2x_virtf *vf) 1772 { 1773 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw); 1774 } 1775 1776 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem) 1777 { 1778 struct bnx2x_virtf *vf; 1779 int qidx = 0, abs_vfid; 1780 u8 opcode; 1781 u16 cid = 0xffff; 1782 1783 if (!IS_SRIOV(bp)) 1784 return 1; 1785 1786 /* first get the cid - the only events we handle here are cfc-delete 1787 * and set-mac completion 1788 */ 1789 opcode = elem->message.opcode; 1790 1791 switch (opcode) { 1792 case EVENT_RING_OPCODE_CFC_DEL: 1793 cid = SW_CID((__force __le32) 1794 elem->message.data.cfc_del_event.cid); 1795 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid); 1796 break; 1797 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1798 case EVENT_RING_OPCODE_MULTICAST_RULES: 1799 case EVENT_RING_OPCODE_FILTERS_RULES: 1800 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1801 cid = (elem->message.data.eth_event.echo & 1802 BNX2X_SWCID_MASK); 1803 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid); 1804 break; 1805 case EVENT_RING_OPCODE_VF_FLR: 1806 abs_vfid = elem->message.data.vf_flr_event.vf_id; 1807 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n", 1808 abs_vfid); 1809 goto get_vf; 1810 case EVENT_RING_OPCODE_MALICIOUS_VF: 1811 abs_vfid = elem->message.data.malicious_vf_event.vf_id; 1812 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n", 1813 abs_vfid, 1814 elem->message.data.malicious_vf_event.err_id); 1815 goto get_vf; 1816 default: 1817 return 1; 1818 } 1819 1820 /* check if the cid is the VF range */ 1821 if (!bnx2x_iov_is_vf_cid(bp, cid)) { 1822 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid); 1823 return 1; 1824 } 1825 1826 /* extract vf and rxq index from vf_cid - relies on the following: 1827 * 1. vfid on cid reflects the true abs_vfid 1828 * 2. The max number of VFs (per path) is 64 1829 */ 1830 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1); 1831 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1832 get_vf: 1833 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid); 1834 1835 if (!vf) { 1836 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n", 1837 cid, abs_vfid); 1838 return 0; 1839 } 1840 1841 switch (opcode) { 1842 case EVENT_RING_OPCODE_CFC_DEL: 1843 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n", 1844 vf->abs_vfid, qidx); 1845 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp, 1846 &vfq_get(vf, 1847 qidx)->sp_obj, 1848 BNX2X_Q_CMD_CFC_DEL); 1849 break; 1850 case EVENT_RING_OPCODE_CLASSIFICATION_RULES: 1851 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n", 1852 vf->abs_vfid, qidx); 1853 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem); 1854 break; 1855 case EVENT_RING_OPCODE_MULTICAST_RULES: 1856 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n", 1857 vf->abs_vfid, qidx); 1858 bnx2x_vf_handle_mcast_eqe(bp, vf); 1859 break; 1860 case EVENT_RING_OPCODE_FILTERS_RULES: 1861 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n", 1862 vf->abs_vfid, qidx); 1863 bnx2x_vf_handle_filters_eqe(bp, vf); 1864 break; 1865 case EVENT_RING_OPCODE_RSS_UPDATE_RULES: 1866 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n", 1867 vf->abs_vfid, qidx); 1868 bnx2x_vf_handle_rss_update_eqe(bp, vf); 1869 case EVENT_RING_OPCODE_VF_FLR: 1870 case EVENT_RING_OPCODE_MALICIOUS_VF: 1871 /* Do nothing for now */ 1872 return 0; 1873 } 1874 1875 return 0; 1876 } 1877 1878 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid) 1879 { 1880 /* extract the vf from vf_cid - relies on the following: 1881 * 1. vfid on cid reflects the true abs_vfid 1882 * 2. The max number of VFs (per path) is 64 1883 */ 1884 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1); 1885 return bnx2x_vf_by_abs_fid(bp, abs_vfid); 1886 } 1887 1888 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid, 1889 struct bnx2x_queue_sp_obj **q_obj) 1890 { 1891 struct bnx2x_virtf *vf; 1892 1893 if (!IS_SRIOV(bp)) 1894 return; 1895 1896 vf = bnx2x_vf_by_cid(bp, vf_cid); 1897 1898 if (vf) { 1899 /* extract queue index from vf_cid - relies on the following: 1900 * 1. vfid on cid reflects the true abs_vfid 1901 * 2. The max number of VFs (per path) is 64 1902 */ 1903 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1); 1904 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj); 1905 } else { 1906 BNX2X_ERR("No vf matching cid %d\n", vf_cid); 1907 } 1908 } 1909 1910 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp) 1911 { 1912 int i; 1913 int first_queue_query_index, num_queues_req; 1914 dma_addr_t cur_data_offset; 1915 struct stats_query_entry *cur_query_entry; 1916 u8 stats_count = 0; 1917 bool is_fcoe = false; 1918 1919 if (!IS_SRIOV(bp)) 1920 return; 1921 1922 if (!NO_FCOE(bp)) 1923 is_fcoe = true; 1924 1925 /* fcoe adds one global request and one queue request */ 1926 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe; 1927 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1928 (is_fcoe ? 0 : 1); 1929 1930 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1931 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n", 1932 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index, 1933 first_queue_query_index + num_queues_req); 1934 1935 cur_data_offset = bp->fw_stats_data_mapping + 1936 offsetof(struct bnx2x_fw_stats_data, queue_stats) + 1937 num_queues_req * sizeof(struct per_queue_stats); 1938 1939 cur_query_entry = &bp->fw_stats_req-> 1940 query[first_queue_query_index + num_queues_req]; 1941 1942 for_each_vf(bp, i) { 1943 int j; 1944 struct bnx2x_virtf *vf = BP_VF(bp, i); 1945 1946 if (vf->state != VF_ENABLED) { 1947 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS), 1948 "vf %d not enabled so no stats for it\n", 1949 vf->abs_vfid); 1950 continue; 1951 } 1952 1953 DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid); 1954 for_each_vfq(vf, j) { 1955 struct bnx2x_vf_queue *rxq = vfq_get(vf, j); 1956 1957 dma_addr_t q_stats_addr = 1958 vf->fw_stat_map + j * vf->stats_stride; 1959 1960 /* collect stats fro active queues only */ 1961 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) == 1962 BNX2X_Q_LOGICAL_STATE_STOPPED) 1963 continue; 1964 1965 /* create stats query entry for this queue */ 1966 cur_query_entry->kind = STATS_TYPE_QUEUE; 1967 cur_query_entry->index = vfq_stat_id(vf, rxq); 1968 cur_query_entry->funcID = 1969 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid)); 1970 cur_query_entry->address.hi = 1971 cpu_to_le32(U64_HI(q_stats_addr)); 1972 cur_query_entry->address.lo = 1973 cpu_to_le32(U64_LO(q_stats_addr)); 1974 DP(BNX2X_MSG_IOV, 1975 "added address %x %x for vf %d queue %d client %d\n", 1976 cur_query_entry->address.hi, 1977 cur_query_entry->address.lo, cur_query_entry->funcID, 1978 j, cur_query_entry->index); 1979 cur_query_entry++; 1980 cur_data_offset += sizeof(struct per_queue_stats); 1981 stats_count++; 1982 1983 /* all stats are coalesced to the leading queue */ 1984 if (vf->cfg_flags & VF_CFG_STATS_COALESCE) 1985 break; 1986 } 1987 } 1988 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count; 1989 } 1990 1991 /* VF API helpers */ 1992 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid, 1993 u8 enable) 1994 { 1995 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; 1996 u32 val = enable ? (abs_vfid | (1 << 6)) : 0; 1997 1998 REG_WR(bp, reg, val); 1999 } 2000 2001 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf) 2002 { 2003 int i; 2004 2005 for_each_vfq(vf, i) 2006 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2007 vfq_qzone_id(vf, vfq_get(vf, i)), false); 2008 } 2009 2010 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf) 2011 { 2012 u32 val; 2013 2014 /* clear the VF configuration - pretend */ 2015 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid)); 2016 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 2017 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN | 2018 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK); 2019 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); 2020 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2021 } 2022 2023 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf) 2024 { 2025 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF), 2026 BNX2X_VF_MAX_QUEUES); 2027 } 2028 2029 static 2030 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf, 2031 struct vf_pf_resc_request *req_resc) 2032 { 2033 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 2034 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf); 2035 2036 /* Save a vlan filter for the Hypervisor */ 2037 return ((req_resc->num_rxqs <= rxq_cnt) && 2038 (req_resc->num_txqs <= txq_cnt) && 2039 (req_resc->num_sbs <= vf_sb_count(vf)) && 2040 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) && 2041 (req_resc->num_vlan_filters <= vf_vlan_rules_visible_cnt(vf))); 2042 } 2043 2044 /* CORE VF API */ 2045 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf, 2046 struct vf_pf_resc_request *resc) 2047 { 2048 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) * 2049 BNX2X_CIDS_PER_VF; 2050 2051 union cdu_context *base_cxt = (union cdu_context *) 2052 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr + 2053 (base_vf_cid & (ILT_PAGE_CIDS-1)); 2054 int i; 2055 2056 /* if state is 'acquired' the VF was not released or FLR'd, in 2057 * this case the returned resources match the acquired already 2058 * acquired resources. Verify that the requested numbers do 2059 * not exceed the already acquired numbers. 2060 */ 2061 if (vf->state == VF_ACQUIRED) { 2062 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n", 2063 vf->abs_vfid); 2064 2065 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2066 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n", 2067 vf->abs_vfid); 2068 return -EINVAL; 2069 } 2070 return 0; 2071 } 2072 2073 /* Otherwise vf state must be 'free' or 'reset' */ 2074 if (vf->state != VF_FREE && vf->state != VF_RESET) { 2075 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n", 2076 vf->abs_vfid, vf->state); 2077 return -EINVAL; 2078 } 2079 2080 /* static allocation: 2081 * the global maximum number are fixed per VF. Fail the request if 2082 * requested number exceed these globals 2083 */ 2084 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) { 2085 DP(BNX2X_MSG_IOV, 2086 "cannot fulfill vf resource request. Placing maximal available values in response\n"); 2087 /* set the max resource in the vf */ 2088 return -ENOMEM; 2089 } 2090 2091 /* Set resources counters - 0 request means max available */ 2092 vf_sb_count(vf) = resc->num_sbs; 2093 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2094 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf); 2095 if (resc->num_mac_filters) 2096 vf_mac_rules_cnt(vf) = resc->num_mac_filters; 2097 /* Add an additional vlan filter credit for the hypervisor */ 2098 bnx2x_iov_re_set_vlan_filters(bp, vf, resc->num_vlan_filters + 1); 2099 2100 DP(BNX2X_MSG_IOV, 2101 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n", 2102 vf_sb_count(vf), vf_rxq_count(vf), 2103 vf_txq_count(vf), vf_mac_rules_cnt(vf), 2104 vf_vlan_rules_visible_cnt(vf)); 2105 2106 /* Initialize the queues */ 2107 if (!vf->vfqs) { 2108 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n"); 2109 return -EINVAL; 2110 } 2111 2112 for_each_vfq(vf, i) { 2113 struct bnx2x_vf_queue *q = vfq_get(vf, i); 2114 2115 if (!q) { 2116 BNX2X_ERR("q number %d was not allocated\n", i); 2117 return -EINVAL; 2118 } 2119 2120 q->index = i; 2121 q->cxt = &((base_cxt + i)->eth); 2122 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i; 2123 2124 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n", 2125 vf->abs_vfid, i, q->index, q->cid, q->cxt); 2126 2127 /* init SP objects */ 2128 bnx2x_vfq_init(bp, vf, q); 2129 } 2130 vf->state = VF_ACQUIRED; 2131 return 0; 2132 } 2133 2134 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map) 2135 { 2136 struct bnx2x_func_init_params func_init = {0}; 2137 u16 flags = 0; 2138 int i; 2139 2140 /* the sb resources are initialized at this point, do the 2141 * FW/HW initializations 2142 */ 2143 for_each_vf_sb(vf, i) 2144 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true, 2145 vf_igu_sb(vf, i), vf_igu_sb(vf, i)); 2146 2147 /* Sanity checks */ 2148 if (vf->state != VF_ACQUIRED) { 2149 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n", 2150 vf->abs_vfid, vf->state); 2151 return -EINVAL; 2152 } 2153 2154 /* let FLR complete ... */ 2155 msleep(100); 2156 2157 /* FLR cleanup epilogue */ 2158 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid)) 2159 return -EBUSY; 2160 2161 /* reset IGU VF statistics: MSIX */ 2162 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0); 2163 2164 /* vf init */ 2165 if (vf->cfg_flags & VF_CFG_STATS) 2166 flags |= (FUNC_FLG_STATS | FUNC_FLG_SPQ); 2167 2168 if (vf->cfg_flags & VF_CFG_TPA) 2169 flags |= FUNC_FLG_TPA; 2170 2171 if (is_vf_multi(vf)) 2172 flags |= FUNC_FLG_RSS; 2173 2174 /* function setup */ 2175 func_init.func_flgs = flags; 2176 func_init.pf_id = BP_FUNC(bp); 2177 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid); 2178 func_init.fw_stat_map = vf->fw_stat_map; 2179 func_init.spq_map = vf->spq_map; 2180 func_init.spq_prod = 0; 2181 bnx2x_func_init(bp, &func_init); 2182 2183 /* Enable the vf */ 2184 bnx2x_vf_enable_access(bp, vf->abs_vfid); 2185 bnx2x_vf_enable_traffic(bp, vf); 2186 2187 /* queue protection table */ 2188 for_each_vfq(vf, i) 2189 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid, 2190 vfq_qzone_id(vf, vfq_get(vf, i)), true); 2191 2192 vf->state = VF_ENABLED; 2193 2194 /* update vf bulletin board */ 2195 bnx2x_post_vf_bulletin(bp, vf->index); 2196 2197 return 0; 2198 } 2199 2200 struct set_vf_state_cookie { 2201 struct bnx2x_virtf *vf; 2202 u8 state; 2203 }; 2204 2205 static void bnx2x_set_vf_state(void *cookie) 2206 { 2207 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie; 2208 2209 p->vf->state = p->state; 2210 } 2211 2212 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf) 2213 { 2214 int rc = 0, i; 2215 2216 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2217 2218 /* Close all queues */ 2219 for (i = 0; i < vf_rxq_count(vf); i++) { 2220 rc = bnx2x_vf_queue_teardown(bp, vf, i); 2221 if (rc) 2222 goto op_err; 2223 } 2224 2225 /* disable the interrupts */ 2226 DP(BNX2X_MSG_IOV, "disabling igu\n"); 2227 bnx2x_vf_igu_disable(bp, vf); 2228 2229 /* disable the VF */ 2230 DP(BNX2X_MSG_IOV, "clearing qtbl\n"); 2231 bnx2x_vf_clr_qtbl(bp, vf); 2232 2233 /* need to make sure there are no outstanding stats ramrods which may 2234 * cause the device to access the VF's stats buffer which it will free 2235 * as soon as we return from the close flow. 2236 */ 2237 { 2238 struct set_vf_state_cookie cookie; 2239 2240 cookie.vf = vf; 2241 cookie.state = VF_ACQUIRED; 2242 bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie); 2243 } 2244 2245 DP(BNX2X_MSG_IOV, "set state to acquired\n"); 2246 2247 return 0; 2248 op_err: 2249 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc); 2250 return rc; 2251 } 2252 2253 /* VF release can be called either: 1. The VF was acquired but 2254 * not enabled 2. the vf was enabled or in the process of being 2255 * enabled 2256 */ 2257 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf) 2258 { 2259 int rc; 2260 2261 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid, 2262 vf->state == VF_FREE ? "Free" : 2263 vf->state == VF_ACQUIRED ? "Acquired" : 2264 vf->state == VF_ENABLED ? "Enabled" : 2265 vf->state == VF_RESET ? "Reset" : 2266 "Unknown"); 2267 2268 switch (vf->state) { 2269 case VF_ENABLED: 2270 rc = bnx2x_vf_close(bp, vf); 2271 if (rc) 2272 goto op_err; 2273 /* Fallthrough to release resources */ 2274 case VF_ACQUIRED: 2275 DP(BNX2X_MSG_IOV, "about to free resources\n"); 2276 bnx2x_vf_free_resc(bp, vf); 2277 break; 2278 2279 case VF_FREE: 2280 case VF_RESET: 2281 default: 2282 break; 2283 } 2284 return 0; 2285 op_err: 2286 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc); 2287 return rc; 2288 } 2289 2290 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2291 struct bnx2x_config_rss_params *rss) 2292 { 2293 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2294 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags); 2295 return bnx2x_config_rss(bp, rss); 2296 } 2297 2298 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf, 2299 struct vfpf_tpa_tlv *tlv, 2300 struct bnx2x_queue_update_tpa_params *params) 2301 { 2302 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr; 2303 struct bnx2x_queue_state_params qstate; 2304 int qid, rc = 0; 2305 2306 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid); 2307 2308 /* Set ramrod params */ 2309 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params)); 2310 memcpy(&qstate.params.update_tpa, params, 2311 sizeof(struct bnx2x_queue_update_tpa_params)); 2312 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA; 2313 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags); 2314 2315 for (qid = 0; qid < vf_rxq_count(vf); qid++) { 2316 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj); 2317 qstate.params.update_tpa.sge_map = sge_addr[qid]; 2318 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n", 2319 vf->abs_vfid, qid, U64_HI(sge_addr[qid]), 2320 U64_LO(sge_addr[qid])); 2321 rc = bnx2x_queue_state_change(bp, &qstate); 2322 if (rc) { 2323 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n", 2324 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]), 2325 vf->abs_vfid, qid); 2326 return rc; 2327 } 2328 } 2329 2330 return rc; 2331 } 2332 2333 /* VF release ~ VF close + VF release-resources 2334 * Release is the ultimate SW shutdown and is called whenever an 2335 * irrecoverable error is encountered. 2336 */ 2337 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf) 2338 { 2339 int rc; 2340 2341 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid); 2342 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2343 2344 rc = bnx2x_vf_free(bp, vf); 2345 if (rc) 2346 WARN(rc, 2347 "VF[%d] Failed to allocate resources for release op- rc=%d\n", 2348 vf->abs_vfid, rc); 2349 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF); 2350 return rc; 2351 } 2352 2353 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2354 enum channel_tlvs tlv) 2355 { 2356 /* we don't lock the channel for unsupported tlvs */ 2357 if (!bnx2x_tlv_supported(tlv)) { 2358 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n"); 2359 return; 2360 } 2361 2362 /* lock the channel */ 2363 mutex_lock(&vf->op_mutex); 2364 2365 /* record the locking op */ 2366 vf->op_current = tlv; 2367 2368 /* log the lock */ 2369 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n", 2370 vf->abs_vfid, tlv); 2371 } 2372 2373 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf, 2374 enum channel_tlvs expected_tlv) 2375 { 2376 enum channel_tlvs current_tlv; 2377 2378 if (!vf) { 2379 BNX2X_ERR("VF was %p\n", vf); 2380 return; 2381 } 2382 2383 current_tlv = vf->op_current; 2384 2385 /* we don't unlock the channel for unsupported tlvs */ 2386 if (!bnx2x_tlv_supported(expected_tlv)) 2387 return; 2388 2389 WARN(expected_tlv != vf->op_current, 2390 "lock mismatch: expected %d found %d", expected_tlv, 2391 vf->op_current); 2392 2393 /* record the locking op */ 2394 vf->op_current = CHANNEL_TLV_NONE; 2395 2396 /* lock the channel */ 2397 mutex_unlock(&vf->op_mutex); 2398 2399 /* log the unlock */ 2400 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n", 2401 vf->abs_vfid, current_tlv); 2402 } 2403 2404 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable) 2405 { 2406 struct bnx2x_queue_state_params q_params; 2407 u32 prev_flags; 2408 int i, rc; 2409 2410 /* Verify changes are needed and record current Tx switching state */ 2411 prev_flags = bp->flags; 2412 if (enable) 2413 bp->flags |= TX_SWITCHING; 2414 else 2415 bp->flags &= ~TX_SWITCHING; 2416 if (prev_flags == bp->flags) 2417 return 0; 2418 2419 /* Verify state enables the sending of queue ramrods */ 2420 if ((bp->state != BNX2X_STATE_OPEN) || 2421 (bnx2x_get_q_logical_state(bp, 2422 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) != 2423 BNX2X_Q_LOGICAL_STATE_ACTIVE)) 2424 return 0; 2425 2426 /* send q. update ramrod to configure Tx switching */ 2427 memset(&q_params, 0, sizeof(q_params)); 2428 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2429 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2430 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG, 2431 &q_params.params.update.update_flags); 2432 if (enable) 2433 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2434 &q_params.params.update.update_flags); 2435 else 2436 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING, 2437 &q_params.params.update.update_flags); 2438 2439 /* send the ramrod on all the queues of the PF */ 2440 for_each_eth_queue(bp, i) { 2441 struct bnx2x_fastpath *fp = &bp->fp[i]; 2442 2443 /* Set the appropriate Queue object */ 2444 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 2445 2446 /* Update the Queue state */ 2447 rc = bnx2x_queue_state_change(bp, &q_params); 2448 if (rc) { 2449 BNX2X_ERR("Failed to configure Tx switching\n"); 2450 return rc; 2451 } 2452 } 2453 2454 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled"); 2455 return 0; 2456 } 2457 2458 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param) 2459 { 2460 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev)); 2461 2462 if (!IS_SRIOV(bp)) { 2463 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); 2464 return -EINVAL; 2465 } 2466 2467 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n", 2468 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2469 2470 /* HW channel is only operational when PF is up */ 2471 if (bp->state != BNX2X_STATE_OPEN) { 2472 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n"); 2473 return -EINVAL; 2474 } 2475 2476 /* we are always bound by the total_vfs in the configuration space */ 2477 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) { 2478 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n", 2479 num_vfs_param, BNX2X_NR_VIRTFN(bp)); 2480 num_vfs_param = BNX2X_NR_VIRTFN(bp); 2481 } 2482 2483 bp->requested_nr_virtfn = num_vfs_param; 2484 if (num_vfs_param == 0) { 2485 bnx2x_set_pf_tx_switching(bp, false); 2486 pci_disable_sriov(dev); 2487 return 0; 2488 } else { 2489 return bnx2x_enable_sriov(bp); 2490 } 2491 } 2492 2493 #define IGU_ENTRY_SIZE 4 2494 2495 int bnx2x_enable_sriov(struct bnx2x *bp) 2496 { 2497 int rc = 0, req_vfs = bp->requested_nr_virtfn; 2498 int vf_idx, sb_idx, vfq_idx, qcount, first_vf; 2499 u32 igu_entry, address; 2500 u16 num_vf_queues; 2501 2502 if (req_vfs == 0) 2503 return 0; 2504 2505 first_vf = bp->vfdb->sriov.first_vf_in_pf; 2506 2507 /* statically distribute vf sb pool between VFs */ 2508 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES, 2509 BP_VFDB(bp)->vf_sbs_pool / req_vfs); 2510 2511 /* zero previous values learned from igu cam */ 2512 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) { 2513 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2514 2515 vf->sb_count = 0; 2516 vf_sb_count(BP_VF(bp, vf_idx)) = 0; 2517 } 2518 bp->vfdb->vf_sbs_pool = 0; 2519 2520 /* prepare IGU cam */ 2521 sb_idx = BP_VFDB(bp)->first_vf_igu_entry; 2522 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE; 2523 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2524 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) { 2525 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT | 2526 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT | 2527 IGU_REG_MAPPING_MEMORY_VALID; 2528 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n", 2529 sb_idx, vf_idx); 2530 REG_WR(bp, address, igu_entry); 2531 sb_idx++; 2532 address += IGU_ENTRY_SIZE; 2533 } 2534 } 2535 2536 /* Reinitialize vf database according to igu cam */ 2537 bnx2x_get_vf_igu_cam_info(bp); 2538 2539 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n", 2540 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues); 2541 2542 qcount = 0; 2543 for_each_vf(bp, vf_idx) { 2544 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 2545 2546 /* set local queue arrays */ 2547 vf->vfqs = &bp->vfdb->vfqs[qcount]; 2548 qcount += vf_sb_count(vf); 2549 bnx2x_iov_static_resc(bp, vf); 2550 } 2551 2552 /* prepare msix vectors in VF configuration space - the value in the 2553 * PCI configuration space should be the index of the last entry, 2554 * namely one less than the actual size of the table 2555 */ 2556 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) { 2557 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); 2558 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, 2559 num_vf_queues - 1); 2560 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n", 2561 vf_idx, num_vf_queues - 1); 2562 } 2563 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 2564 2565 /* enable sriov. This will probe all the VFs, and consequentially cause 2566 * the "acquire" messages to appear on the VF PF channel. 2567 */ 2568 DP(BNX2X_MSG_IOV, "about to call enable sriov\n"); 2569 bnx2x_disable_sriov(bp); 2570 2571 rc = bnx2x_set_pf_tx_switching(bp, true); 2572 if (rc) 2573 return rc; 2574 2575 rc = pci_enable_sriov(bp->pdev, req_vfs); 2576 if (rc) { 2577 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc); 2578 return rc; 2579 } 2580 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs); 2581 return req_vfs; 2582 } 2583 2584 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp) 2585 { 2586 int vfidx; 2587 struct pf_vf_bulletin_content *bulletin; 2588 2589 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n"); 2590 for_each_vf(bp, vfidx) { 2591 bulletin = BP_VF_BULLETIN(bp, vfidx); 2592 if (BP_VF(bp, vfidx)->cfg_flags & VF_CFG_VLAN) 2593 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0); 2594 } 2595 } 2596 2597 void bnx2x_disable_sriov(struct bnx2x *bp) 2598 { 2599 pci_disable_sriov(bp->pdev); 2600 } 2601 2602 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx, 2603 struct bnx2x_virtf **vf, 2604 struct pf_vf_bulletin_content **bulletin, 2605 bool test_queue) 2606 { 2607 if (bp->state != BNX2X_STATE_OPEN) { 2608 BNX2X_ERR("PF is down - can't utilize iov-related functionality\n"); 2609 return -EINVAL; 2610 } 2611 2612 if (!IS_SRIOV(bp)) { 2613 BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n"); 2614 return -EINVAL; 2615 } 2616 2617 if (vfidx >= BNX2X_NR_VIRTFN(bp)) { 2618 BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n", 2619 vfidx, BNX2X_NR_VIRTFN(bp)); 2620 return -EINVAL; 2621 } 2622 2623 /* init members */ 2624 *vf = BP_VF(bp, vfidx); 2625 *bulletin = BP_VF_BULLETIN(bp, vfidx); 2626 2627 if (!*vf) { 2628 BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx); 2629 return -EINVAL; 2630 } 2631 2632 if (test_queue && !(*vf)->vfqs) { 2633 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n", 2634 vfidx); 2635 return -EINVAL; 2636 } 2637 2638 if (!*bulletin) { 2639 BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n", 2640 vfidx); 2641 return -EINVAL; 2642 } 2643 2644 return 0; 2645 } 2646 2647 int bnx2x_get_vf_config(struct net_device *dev, int vfidx, 2648 struct ifla_vf_info *ivi) 2649 { 2650 struct bnx2x *bp = netdev_priv(dev); 2651 struct bnx2x_virtf *vf = NULL; 2652 struct pf_vf_bulletin_content *bulletin = NULL; 2653 struct bnx2x_vlan_mac_obj *mac_obj; 2654 struct bnx2x_vlan_mac_obj *vlan_obj; 2655 int rc; 2656 2657 /* sanity and init */ 2658 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2659 if (rc) 2660 return rc; 2661 2662 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2663 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2664 if (!mac_obj || !vlan_obj) { 2665 BNX2X_ERR("VF partially initialized\n"); 2666 return -EINVAL; 2667 } 2668 2669 ivi->vf = vfidx; 2670 ivi->qos = 0; 2671 ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */ 2672 ivi->min_tx_rate = 0; 2673 ivi->spoofchk = 1; /*always enabled */ 2674 if (vf->state == VF_ENABLED) { 2675 /* mac and vlan are in vlan_mac objects */ 2676 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) { 2677 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac, 2678 0, ETH_ALEN); 2679 vlan_obj->get_n_elements(bp, vlan_obj, 1, 2680 (u8 *)&ivi->vlan, 0, 2681 VLAN_HLEN); 2682 } 2683 } else { 2684 mutex_lock(&bp->vfdb->bulletin_mutex); 2685 /* mac */ 2686 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID)) 2687 /* mac configured by ndo so its in bulletin board */ 2688 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN); 2689 else 2690 /* function has not been loaded yet. Show mac as 0s */ 2691 memset(&ivi->mac, 0, ETH_ALEN); 2692 2693 /* vlan */ 2694 if (bulletin->valid_bitmap & (1 << VLAN_VALID)) 2695 /* vlan configured by ndo so its in bulletin board */ 2696 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN); 2697 else 2698 /* function has not been loaded yet. Show vlans as 0s */ 2699 memset(&ivi->vlan, 0, VLAN_HLEN); 2700 2701 mutex_unlock(&bp->vfdb->bulletin_mutex); 2702 } 2703 2704 return 0; 2705 } 2706 2707 /* New mac for VF. Consider these cases: 2708 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and 2709 * supply at acquire. 2710 * 2. VF has already been acquired but has not yet initialized - store in local 2711 * bulletin board. mac will be posted on VF bulletin board after VF init. VF 2712 * will configure this mac when it is ready. 2713 * 3. VF has already initialized but has not yet setup a queue - post the new 2714 * mac on VF's bulletin board right now. VF will configure this mac when it 2715 * is ready. 2716 * 4. VF has already set a queue - delete any macs already configured for this 2717 * queue and manually config the new mac. 2718 * In any event, once this function has been called refuse any attempts by the 2719 * VF to configure any mac for itself except for this mac. In case of a race 2720 * where the VF fails to see the new post on its bulletin board before sending a 2721 * mac configuration request, the PF will simply fail the request and VF can try 2722 * again after consulting its bulletin board. 2723 */ 2724 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac) 2725 { 2726 struct bnx2x *bp = netdev_priv(dev); 2727 int rc, q_logical_state; 2728 struct bnx2x_virtf *vf = NULL; 2729 struct pf_vf_bulletin_content *bulletin = NULL; 2730 2731 if (!is_valid_ether_addr(mac)) { 2732 BNX2X_ERR("mac address invalid\n"); 2733 return -EINVAL; 2734 } 2735 2736 /* sanity and init */ 2737 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2738 if (rc) 2739 return rc; 2740 2741 mutex_lock(&bp->vfdb->bulletin_mutex); 2742 2743 /* update PF's copy of the VF's bulletin. Will no longer accept mac 2744 * configuration requests from vf unless match this mac 2745 */ 2746 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID; 2747 memcpy(bulletin->mac, mac, ETH_ALEN); 2748 2749 /* Post update on VF's bulletin board */ 2750 rc = bnx2x_post_vf_bulletin(bp, vfidx); 2751 2752 /* release lock before checking return code */ 2753 mutex_unlock(&bp->vfdb->bulletin_mutex); 2754 2755 if (rc) { 2756 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx); 2757 return rc; 2758 } 2759 2760 q_logical_state = 2761 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)); 2762 if (vf->state == VF_ENABLED && 2763 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) { 2764 /* configure the mac in device on this vf's queue */ 2765 unsigned long ramrod_flags = 0; 2766 struct bnx2x_vlan_mac_obj *mac_obj; 2767 2768 /* User should be able to see failure reason in system logs */ 2769 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2770 return -EINVAL; 2771 2772 /* must lock vfpf channel to protect against vf flows */ 2773 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2774 2775 /* remove existing eth macs */ 2776 mac_obj = &bnx2x_leading_vfq(vf, mac_obj); 2777 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true); 2778 if (rc) { 2779 BNX2X_ERR("failed to delete eth macs\n"); 2780 rc = -EINVAL; 2781 goto out; 2782 } 2783 2784 /* remove existing uc list macs */ 2785 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true); 2786 if (rc) { 2787 BNX2X_ERR("failed to delete uc_list macs\n"); 2788 rc = -EINVAL; 2789 goto out; 2790 } 2791 2792 /* configure the new mac to device */ 2793 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2794 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true, 2795 BNX2X_ETH_MAC, &ramrod_flags); 2796 2797 out: 2798 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC); 2799 } 2800 2801 return rc; 2802 } 2803 2804 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos) 2805 { 2806 struct bnx2x_queue_state_params q_params = {NULL}; 2807 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 2808 struct bnx2x_queue_update_params *update_params; 2809 struct pf_vf_bulletin_content *bulletin = NULL; 2810 struct bnx2x_rx_mode_ramrod_params rx_ramrod; 2811 struct bnx2x *bp = netdev_priv(dev); 2812 struct bnx2x_vlan_mac_obj *vlan_obj; 2813 unsigned long vlan_mac_flags = 0; 2814 unsigned long ramrod_flags = 0; 2815 struct bnx2x_virtf *vf = NULL; 2816 unsigned long accept_flags; 2817 int rc; 2818 2819 if (vlan > 4095) { 2820 BNX2X_ERR("illegal vlan value %d\n", vlan); 2821 return -EINVAL; 2822 } 2823 2824 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n", 2825 vfidx, vlan, 0); 2826 2827 /* sanity and init */ 2828 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true); 2829 if (rc) 2830 return rc; 2831 2832 /* update PF's copy of the VF's bulletin. No point in posting the vlan 2833 * to the VF since it doesn't have anything to do with it. But it useful 2834 * to store it here in case the VF is not up yet and we can only 2835 * configure the vlan later when it does. Treat vlan id 0 as remove the 2836 * Host tag. 2837 */ 2838 mutex_lock(&bp->vfdb->bulletin_mutex); 2839 2840 if (vlan > 0) 2841 bulletin->valid_bitmap |= 1 << VLAN_VALID; 2842 else 2843 bulletin->valid_bitmap &= ~(1 << VLAN_VALID); 2844 bulletin->vlan = vlan; 2845 2846 mutex_unlock(&bp->vfdb->bulletin_mutex); 2847 2848 /* is vf initialized and queue set up? */ 2849 if (vf->state != VF_ENABLED || 2850 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) != 2851 BNX2X_Q_LOGICAL_STATE_ACTIVE) 2852 return rc; 2853 2854 /* User should be able to see error in system logs */ 2855 if (!bnx2x_validate_vf_sp_objs(bp, vf, true)) 2856 return -EINVAL; 2857 2858 /* must lock vfpf channel to protect against vf flows */ 2859 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2860 2861 /* remove existing vlans */ 2862 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2863 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj); 2864 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags, 2865 &ramrod_flags); 2866 if (rc) { 2867 BNX2X_ERR("failed to delete vlans\n"); 2868 rc = -EINVAL; 2869 goto out; 2870 } 2871 2872 /* need to remove/add the VF's accept_any_vlan bit */ 2873 accept_flags = bnx2x_leading_vfq(vf, accept_flags); 2874 if (vlan) 2875 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2876 else 2877 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 2878 2879 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf, 2880 accept_flags); 2881 bnx2x_leading_vfq(vf, accept_flags) = accept_flags; 2882 bnx2x_config_rx_mode(bp, &rx_ramrod); 2883 2884 /* configure the new vlan to device */ 2885 memset(&ramrod_param, 0, sizeof(ramrod_param)); 2886 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 2887 ramrod_param.vlan_mac_obj = vlan_obj; 2888 ramrod_param.ramrod_flags = ramrod_flags; 2889 set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, 2890 &ramrod_param.user_req.vlan_mac_flags); 2891 ramrod_param.user_req.u.vlan.vlan = vlan; 2892 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 2893 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 2894 if (rc) { 2895 BNX2X_ERR("failed to configure vlan\n"); 2896 rc = -EINVAL; 2897 goto out; 2898 } 2899 2900 /* send queue update ramrod to configure default vlan and silent 2901 * vlan removal 2902 */ 2903 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 2904 q_params.cmd = BNX2X_Q_CMD_UPDATE; 2905 q_params.q_obj = &bnx2x_leading_vfq(vf, sp_obj); 2906 update_params = &q_params.params.update; 2907 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 2908 &update_params->update_flags); 2909 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 2910 &update_params->update_flags); 2911 if (vlan == 0) { 2912 /* if vlan is 0 then we want to leave the VF traffic 2913 * untagged, and leave the incoming traffic untouched 2914 * (i.e. do not remove any vlan tags). 2915 */ 2916 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2917 &update_params->update_flags); 2918 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2919 &update_params->update_flags); 2920 } else { 2921 /* configure default vlan to vf queue and set silent 2922 * vlan removal (the vf remains unaware of this vlan). 2923 */ 2924 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, 2925 &update_params->update_flags); 2926 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 2927 &update_params->update_flags); 2928 update_params->def_vlan = vlan; 2929 update_params->silent_removal_value = 2930 vlan & VLAN_VID_MASK; 2931 update_params->silent_removal_mask = VLAN_VID_MASK; 2932 } 2933 2934 /* Update the Queue state */ 2935 rc = bnx2x_queue_state_change(bp, &q_params); 2936 if (rc) { 2937 BNX2X_ERR("Failed to configure default VLAN\n"); 2938 goto out; 2939 } 2940 2941 2942 /* clear the flag indicating that this VF needs its vlan 2943 * (will only be set if the HV configured the Vlan before vf was 2944 * up and we were called because the VF came up later 2945 */ 2946 out: 2947 vf->cfg_flags &= ~VF_CFG_VLAN; 2948 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN); 2949 2950 return rc; 2951 } 2952 2953 /* crc is the first field in the bulletin board. Compute the crc over the 2954 * entire bulletin board excluding the crc field itself. Use the length field 2955 * as the Bulletin Board was posted by a PF with possibly a different version 2956 * from the vf which will sample it. Therefore, the length is computed by the 2957 * PF and then used blindly by the VF. 2958 */ 2959 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin) 2960 { 2961 return crc32(BULLETIN_CRC_SEED, 2962 ((u8 *)bulletin) + sizeof(bulletin->crc), 2963 bulletin->length - sizeof(bulletin->crc)); 2964 } 2965 2966 /* Check for new posts on the bulletin board */ 2967 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp) 2968 { 2969 struct pf_vf_bulletin_content *bulletin; 2970 int attempts; 2971 2972 /* sampling structure in mid post may result with corrupted data 2973 * validate crc to ensure coherency. 2974 */ 2975 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) { 2976 u32 crc; 2977 2978 /* sample the bulletin board */ 2979 memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin, 2980 sizeof(union pf_vf_bulletin)); 2981 2982 crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content); 2983 2984 if (bp->shadow_bulletin.content.crc == crc) 2985 break; 2986 2987 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n", 2988 bp->shadow_bulletin.content.crc, crc); 2989 } 2990 2991 if (attempts >= BULLETIN_ATTEMPTS) { 2992 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n", 2993 attempts); 2994 return PFVF_BULLETIN_CRC_ERR; 2995 } 2996 bulletin = &bp->shadow_bulletin.content; 2997 2998 /* bulletin board hasn't changed since last sample */ 2999 if (bp->old_bulletin.version == bulletin->version) 3000 return PFVF_BULLETIN_UNCHANGED; 3001 3002 /* the mac address in bulletin board is valid and is new */ 3003 if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID && 3004 !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) { 3005 /* update new mac to net device */ 3006 memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN); 3007 } 3008 3009 if (bulletin->valid_bitmap & (1 << LINK_VALID)) { 3010 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n", 3011 bulletin->link_speed, bulletin->link_flags); 3012 3013 bp->vf_link_vars.line_speed = bulletin->link_speed; 3014 bp->vf_link_vars.link_report_flags = 0; 3015 /* Link is down */ 3016 if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN) 3017 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN, 3018 &bp->vf_link_vars.link_report_flags); 3019 /* Full DUPLEX */ 3020 if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX) 3021 __set_bit(BNX2X_LINK_REPORT_FD, 3022 &bp->vf_link_vars.link_report_flags); 3023 /* Rx Flow Control is ON */ 3024 if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON) 3025 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, 3026 &bp->vf_link_vars.link_report_flags); 3027 /* Tx Flow Control is ON */ 3028 if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON) 3029 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, 3030 &bp->vf_link_vars.link_report_flags); 3031 __bnx2x_link_report(bp); 3032 } 3033 3034 /* copy new bulletin board to bp */ 3035 memcpy(&bp->old_bulletin, bulletin, 3036 sizeof(struct pf_vf_bulletin_content)); 3037 3038 return PFVF_BULLETIN_UPDATED; 3039 } 3040 3041 void bnx2x_timer_sriov(struct bnx2x *bp) 3042 { 3043 bnx2x_sample_bulletin(bp); 3044 3045 /* if channel is down we need to self destruct */ 3046 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) 3047 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 3048 BNX2X_MSG_IOV); 3049 } 3050 3051 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp) 3052 { 3053 /* vf doorbells are embedded within the regview */ 3054 return bp->regview + PXP_VF_ADDR_DB_START; 3055 } 3056 3057 void bnx2x_vf_pci_dealloc(struct bnx2x *bp) 3058 { 3059 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, 3060 sizeof(struct bnx2x_vf_mbx_msg)); 3061 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping, 3062 sizeof(union pf_vf_bulletin)); 3063 } 3064 3065 int bnx2x_vf_pci_alloc(struct bnx2x *bp) 3066 { 3067 mutex_init(&bp->vf2pf_mutex); 3068 3069 /* allocate vf2pf mailbox for vf to pf channel */ 3070 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping, 3071 sizeof(struct bnx2x_vf_mbx_msg)); 3072 if (!bp->vf2pf_mbox) 3073 goto alloc_mem_err; 3074 3075 /* allocate pf 2 vf bulletin board */ 3076 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping, 3077 sizeof(union pf_vf_bulletin)); 3078 if (!bp->pf2vf_bulletin) 3079 goto alloc_mem_err; 3080 3081 bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true); 3082 3083 return 0; 3084 3085 alloc_mem_err: 3086 bnx2x_vf_pci_dealloc(bp); 3087 return -ENOMEM; 3088 } 3089 3090 void bnx2x_iov_channel_down(struct bnx2x *bp) 3091 { 3092 int vf_idx; 3093 struct pf_vf_bulletin_content *bulletin; 3094 3095 if (!IS_SRIOV(bp)) 3096 return; 3097 3098 for_each_vf(bp, vf_idx) { 3099 /* locate this VFs bulletin board and update the channel down 3100 * bit 3101 */ 3102 bulletin = BP_VF_BULLETIN(bp, vf_idx); 3103 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN; 3104 3105 /* update vf bulletin board */ 3106 bnx2x_post_vf_bulletin(bp, vf_idx); 3107 } 3108 } 3109 3110 void bnx2x_iov_task(struct work_struct *work) 3111 { 3112 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work); 3113 3114 if (!netif_running(bp->dev)) 3115 return; 3116 3117 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR, 3118 &bp->iov_task_state)) 3119 bnx2x_vf_handle_flr_event(bp); 3120 3121 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG, 3122 &bp->iov_task_state)) 3123 bnx2x_vf_mbx(bp); 3124 } 3125 3126 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag) 3127 { 3128 smp_mb__before_atomic(); 3129 set_bit(flag, &bp->iov_task_state); 3130 smp_mb__after_atomic(); 3131 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag); 3132 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0); 3133 } 3134