1 /* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/module.h> 21 #include <linux/moduleparam.h> 22 #include <linux/kernel.h> 23 #include <linux/device.h> /* for dev_info() */ 24 #include <linux/timer.h> 25 #include <linux/errno.h> 26 #include <linux/ioport.h> 27 #include <linux/slab.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/bitops.h> 36 #include <linux/irq.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/time.h> 40 #include <linux/ethtool.h> 41 #include <linux/mii.h> 42 #include <linux/if_vlan.h> 43 #include <net/ip.h> 44 #include <net/ipv6.h> 45 #include <net/tcp.h> 46 #include <net/checksum.h> 47 #include <net/ip6_checksum.h> 48 #include <linux/workqueue.h> 49 #include <linux/crc32.h> 50 #include <linux/crc32c.h> 51 #include <linux/prefetch.h> 52 #include <linux/zlib.h> 53 #include <linux/io.h> 54 #include <linux/semaphore.h> 55 #include <linux/stringify.h> 56 #include <linux/vmalloc.h> 57 58 #include "bnx2x.h" 59 #include "bnx2x_init.h" 60 #include "bnx2x_init_ops.h" 61 #include "bnx2x_cmn.h" 62 #include "bnx2x_vfpf.h" 63 #include "bnx2x_dcb.h" 64 #include "bnx2x_sp.h" 65 66 #include <linux/firmware.h> 67 #include "bnx2x_fw_file_hdr.h" 68 /* FW files */ 69 #define FW_FILE_VERSION \ 70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 73 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 77 78 /* Time in jiffies before concluding the transmitter is hung */ 79 #define TX_TIMEOUT (5*HZ) 80 81 static char version[] = 82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 84 85 MODULE_AUTHOR("Eliezer Tamir"); 86 MODULE_DESCRIPTION("Broadcom NetXtreme II " 87 "BCM57710/57711/57711E/" 88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 89 "57840/57840_MF Driver"); 90 MODULE_LICENSE("GPL"); 91 MODULE_VERSION(DRV_MODULE_VERSION); 92 MODULE_FIRMWARE(FW_FILE_NAME_E1); 93 MODULE_FIRMWARE(FW_FILE_NAME_E1H); 94 MODULE_FIRMWARE(FW_FILE_NAME_E2); 95 96 int num_queues; 97 module_param(num_queues, int, 0); 98 MODULE_PARM_DESC(num_queues, 99 " Set number of queues (default is as a number of CPUs)"); 100 101 static int disable_tpa; 102 module_param(disable_tpa, int, 0); 103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 104 105 int int_mode; 106 module_param(int_mode, int, 0); 107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 108 "(1 INT#x; 2 MSI)"); 109 110 static int dropless_fc; 111 module_param(dropless_fc, int, 0); 112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 113 114 static int mrrs = -1; 115 module_param(mrrs, int, 0); 116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 117 118 static int debug; 119 module_param(debug, int, 0); 120 MODULE_PARM_DESC(debug, " Default debug msglevel"); 121 122 struct workqueue_struct *bnx2x_wq; 123 124 struct bnx2x_mac_vals { 125 u32 xmac_addr; 126 u32 xmac_val; 127 u32 emac_addr; 128 u32 emac_val; 129 u32 umac_addr; 130 u32 umac_val; 131 u32 bmac_addr; 132 u32 bmac_val[2]; 133 }; 134 135 enum bnx2x_board_type { 136 BCM57710 = 0, 137 BCM57711, 138 BCM57711E, 139 BCM57712, 140 BCM57712_MF, 141 BCM57712_VF, 142 BCM57800, 143 BCM57800_MF, 144 BCM57800_VF, 145 BCM57810, 146 BCM57810_MF, 147 BCM57810_VF, 148 BCM57840_4_10, 149 BCM57840_2_20, 150 BCM57840_MF, 151 BCM57840_VF, 152 BCM57811, 153 BCM57811_MF, 154 BCM57840_O, 155 BCM57840_MFO, 156 BCM57811_VF 157 }; 158 159 /* indexed by board_type, above */ 160 static struct { 161 char *name; 162 } board_info[] = { 163 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 164 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 165 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 166 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 167 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 168 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, 169 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 170 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 171 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, 172 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 173 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 174 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, 175 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, 176 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, 177 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, 178 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, 179 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, 180 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, 181 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 182 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, 183 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } 184 }; 185 186 #ifndef PCI_DEVICE_ID_NX2_57710 187 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 188 #endif 189 #ifndef PCI_DEVICE_ID_NX2_57711 190 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 191 #endif 192 #ifndef PCI_DEVICE_ID_NX2_57711E 193 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 194 #endif 195 #ifndef PCI_DEVICE_ID_NX2_57712 196 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 197 #endif 198 #ifndef PCI_DEVICE_ID_NX2_57712_MF 199 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 200 #endif 201 #ifndef PCI_DEVICE_ID_NX2_57712_VF 202 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF 203 #endif 204 #ifndef PCI_DEVICE_ID_NX2_57800 205 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 206 #endif 207 #ifndef PCI_DEVICE_ID_NX2_57800_MF 208 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 209 #endif 210 #ifndef PCI_DEVICE_ID_NX2_57800_VF 211 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF 212 #endif 213 #ifndef PCI_DEVICE_ID_NX2_57810 214 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 215 #endif 216 #ifndef PCI_DEVICE_ID_NX2_57810_MF 217 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 218 #endif 219 #ifndef PCI_DEVICE_ID_NX2_57840_O 220 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE 221 #endif 222 #ifndef PCI_DEVICE_ID_NX2_57810_VF 223 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF 224 #endif 225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10 226 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 227 #endif 228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20 229 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 230 #endif 231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO 232 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE 233 #endif 234 #ifndef PCI_DEVICE_ID_NX2_57840_MF 235 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 236 #endif 237 #ifndef PCI_DEVICE_ID_NX2_57840_VF 238 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF 239 #endif 240 #ifndef PCI_DEVICE_ID_NX2_57811 241 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 242 #endif 243 #ifndef PCI_DEVICE_ID_NX2_57811_MF 244 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF 245 #endif 246 #ifndef PCI_DEVICE_ID_NX2_57811_VF 247 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF 248 #endif 249 250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 251 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, 265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, 272 { 0 } 273 }; 274 275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 276 277 /* Global resources for unloading a previously loaded device */ 278 #define BNX2X_PREV_WAIT_NEEDED 1 279 static DEFINE_SEMAPHORE(bnx2x_prev_sem); 280 static LIST_HEAD(bnx2x_prev_list); 281 /**************************************************************************** 282 * General service functions 283 ****************************************************************************/ 284 285 static void __storm_memset_dma_mapping(struct bnx2x *bp, 286 u32 addr, dma_addr_t mapping) 287 { 288 REG_WR(bp, addr, U64_LO(mapping)); 289 REG_WR(bp, addr + 4, U64_HI(mapping)); 290 } 291 292 static void storm_memset_spq_addr(struct bnx2x *bp, 293 dma_addr_t mapping, u16 abs_fid) 294 { 295 u32 addr = XSEM_REG_FAST_MEMORY + 296 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 297 298 __storm_memset_dma_mapping(bp, addr, mapping); 299 } 300 301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 302 u16 pf_id) 303 { 304 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 305 pf_id); 306 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 307 pf_id); 308 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 309 pf_id); 310 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 311 pf_id); 312 } 313 314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 315 u8 enable) 316 { 317 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 318 enable); 319 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 320 enable); 321 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 322 enable); 323 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 324 enable); 325 } 326 327 static void storm_memset_eq_data(struct bnx2x *bp, 328 struct event_ring_data *eq_data, 329 u16 pfid) 330 { 331 size_t size = sizeof(struct event_ring_data); 332 333 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 334 335 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 336 } 337 338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 339 u16 pfid) 340 { 341 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 342 REG_WR16(bp, addr, eq_prod); 343 } 344 345 /* used only at init 346 * locking is done by mcp 347 */ 348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 349 { 350 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 351 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 352 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 353 PCICFG_VENDOR_ID_OFFSET); 354 } 355 356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 357 { 358 u32 val; 359 360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 361 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 363 PCICFG_VENDOR_ID_OFFSET); 364 365 return val; 366 } 367 368 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 369 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 370 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 371 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 372 #define DMAE_DP_DST_NONE "dst_addr [none]" 373 374 static void bnx2x_dp_dmae(struct bnx2x *bp, 375 struct dmae_command *dmae, int msglvl) 376 { 377 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 378 int i; 379 380 switch (dmae->opcode & DMAE_COMMAND_DST) { 381 case DMAE_CMD_DST_PCI: 382 if (src_type == DMAE_CMD_SRC_PCI) 383 DP(msglvl, "DMAE: opcode 0x%08x\n" 384 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 385 "comp_addr [%x:%08x], comp_val 0x%08x\n", 386 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 387 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 388 dmae->comp_addr_hi, dmae->comp_addr_lo, 389 dmae->comp_val); 390 else 391 DP(msglvl, "DMAE: opcode 0x%08x\n" 392 "src [%08x], len [%d*4], dst [%x:%08x]\n" 393 "comp_addr [%x:%08x], comp_val 0x%08x\n", 394 dmae->opcode, dmae->src_addr_lo >> 2, 395 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 396 dmae->comp_addr_hi, dmae->comp_addr_lo, 397 dmae->comp_val); 398 break; 399 case DMAE_CMD_DST_GRC: 400 if (src_type == DMAE_CMD_SRC_PCI) 401 DP(msglvl, "DMAE: opcode 0x%08x\n" 402 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 403 "comp_addr [%x:%08x], comp_val 0x%08x\n", 404 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 405 dmae->len, dmae->dst_addr_lo >> 2, 406 dmae->comp_addr_hi, dmae->comp_addr_lo, 407 dmae->comp_val); 408 else 409 DP(msglvl, "DMAE: opcode 0x%08x\n" 410 "src [%08x], len [%d*4], dst [%08x]\n" 411 "comp_addr [%x:%08x], comp_val 0x%08x\n", 412 dmae->opcode, dmae->src_addr_lo >> 2, 413 dmae->len, dmae->dst_addr_lo >> 2, 414 dmae->comp_addr_hi, dmae->comp_addr_lo, 415 dmae->comp_val); 416 break; 417 default: 418 if (src_type == DMAE_CMD_SRC_PCI) 419 DP(msglvl, "DMAE: opcode 0x%08x\n" 420 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 421 "comp_addr [%x:%08x] comp_val 0x%08x\n", 422 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 423 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 424 dmae->comp_val); 425 else 426 DP(msglvl, "DMAE: opcode 0x%08x\n" 427 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 428 "comp_addr [%x:%08x] comp_val 0x%08x\n", 429 dmae->opcode, dmae->src_addr_lo >> 2, 430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 431 dmae->comp_val); 432 break; 433 } 434 435 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) 436 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", 437 i, *(((u32 *)dmae) + i)); 438 } 439 440 /* copy command into DMAE command memory and set DMAE command go */ 441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 442 { 443 u32 cmd_offset; 444 int i; 445 446 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 447 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 448 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 449 } 450 REG_WR(bp, dmae_reg_go_c[idx], 1); 451 } 452 453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 454 { 455 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 456 DMAE_CMD_C_ENABLE); 457 } 458 459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 460 { 461 return opcode & ~DMAE_CMD_SRC_RESET; 462 } 463 464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 465 bool with_comp, u8 comp_type) 466 { 467 u32 opcode = 0; 468 469 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 470 (dst_type << DMAE_COMMAND_DST_SHIFT)); 471 472 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 473 474 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 475 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 476 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 477 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 478 479 #ifdef __BIG_ENDIAN 480 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 481 #else 482 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 483 #endif 484 if (with_comp) 485 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 486 return opcode; 487 } 488 489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 490 struct dmae_command *dmae, 491 u8 src_type, u8 dst_type) 492 { 493 memset(dmae, 0, sizeof(struct dmae_command)); 494 495 /* set the opcode */ 496 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 497 true, DMAE_COMP_PCI); 498 499 /* fill in the completion parameters */ 500 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 501 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 502 dmae->comp_val = DMAE_COMP_VAL; 503 } 504 505 /* issue a dmae command over the init-channel and wait for completion */ 506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) 507 { 508 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 509 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 510 int rc = 0; 511 512 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); 513 514 /* Lock the dmae channel. Disable BHs to prevent a dead-lock 515 * as long as this code is called both from syscall context and 516 * from ndo_set_rx_mode() flow that may be called from BH. 517 */ 518 spin_lock_bh(&bp->dmae_lock); 519 520 /* reset completion */ 521 *wb_comp = 0; 522 523 /* post the command on the channel used for initializations */ 524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 525 526 /* wait for completion */ 527 udelay(5); 528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 529 530 if (!cnt || 531 (bp->recovery_state != BNX2X_RECOVERY_DONE && 532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 533 BNX2X_ERR("DMAE timeout!\n"); 534 rc = DMAE_TIMEOUT; 535 goto unlock; 536 } 537 cnt--; 538 udelay(50); 539 } 540 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 541 BNX2X_ERR("DMAE PCI error!\n"); 542 rc = DMAE_PCI_ERROR; 543 } 544 545 unlock: 546 spin_unlock_bh(&bp->dmae_lock); 547 return rc; 548 } 549 550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 551 u32 len32) 552 { 553 int rc; 554 struct dmae_command dmae; 555 556 if (!bp->dmae_ready) { 557 u32 *data = bnx2x_sp(bp, wb_data[0]); 558 559 if (CHIP_IS_E1(bp)) 560 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 561 else 562 bnx2x_init_str_wr(bp, dst_addr, data, len32); 563 return; 564 } 565 566 /* set opcode and fixed command fields */ 567 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 568 569 /* fill in addresses and len */ 570 dmae.src_addr_lo = U64_LO(dma_addr); 571 dmae.src_addr_hi = U64_HI(dma_addr); 572 dmae.dst_addr_lo = dst_addr >> 2; 573 dmae.dst_addr_hi = 0; 574 dmae.len = len32; 575 576 /* issue the command and wait for completion */ 577 rc = bnx2x_issue_dmae_with_comp(bp, &dmae); 578 if (rc) { 579 BNX2X_ERR("DMAE returned failure %d\n", rc); 580 bnx2x_panic(); 581 } 582 } 583 584 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 585 { 586 int rc; 587 struct dmae_command dmae; 588 589 if (!bp->dmae_ready) { 590 u32 *data = bnx2x_sp(bp, wb_data[0]); 591 int i; 592 593 if (CHIP_IS_E1(bp)) 594 for (i = 0; i < len32; i++) 595 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 596 else 597 for (i = 0; i < len32; i++) 598 data[i] = REG_RD(bp, src_addr + i*4); 599 600 return; 601 } 602 603 /* set opcode and fixed command fields */ 604 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 605 606 /* fill in addresses and len */ 607 dmae.src_addr_lo = src_addr >> 2; 608 dmae.src_addr_hi = 0; 609 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 610 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 611 dmae.len = len32; 612 613 /* issue the command and wait for completion */ 614 rc = bnx2x_issue_dmae_with_comp(bp, &dmae); 615 if (rc) { 616 BNX2X_ERR("DMAE returned failure %d\n", rc); 617 bnx2x_panic(); 618 } 619 } 620 621 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 622 u32 addr, u32 len) 623 { 624 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 625 int offset = 0; 626 627 while (len > dmae_wr_max) { 628 bnx2x_write_dmae(bp, phys_addr + offset, 629 addr + offset, dmae_wr_max); 630 offset += dmae_wr_max * 4; 631 len -= dmae_wr_max; 632 } 633 634 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 635 } 636 637 static int bnx2x_mc_assert(struct bnx2x *bp) 638 { 639 char last_idx; 640 int i, rc = 0; 641 u32 row0, row1, row2, row3; 642 643 /* XSTORM */ 644 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 645 XSTORM_ASSERT_LIST_INDEX_OFFSET); 646 if (last_idx) 647 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 648 649 /* print the asserts */ 650 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 651 652 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 653 XSTORM_ASSERT_LIST_OFFSET(i)); 654 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 655 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 656 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 657 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 658 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 659 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 660 661 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 662 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 663 i, row3, row2, row1, row0); 664 rc++; 665 } else { 666 break; 667 } 668 } 669 670 /* TSTORM */ 671 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 672 TSTORM_ASSERT_LIST_INDEX_OFFSET); 673 if (last_idx) 674 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 675 676 /* print the asserts */ 677 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 678 679 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 680 TSTORM_ASSERT_LIST_OFFSET(i)); 681 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 682 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 683 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 684 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 685 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 686 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 687 688 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 689 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 690 i, row3, row2, row1, row0); 691 rc++; 692 } else { 693 break; 694 } 695 } 696 697 /* CSTORM */ 698 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 699 CSTORM_ASSERT_LIST_INDEX_OFFSET); 700 if (last_idx) 701 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 702 703 /* print the asserts */ 704 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 705 706 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 707 CSTORM_ASSERT_LIST_OFFSET(i)); 708 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 709 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 710 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 711 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 712 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 713 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 714 715 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 716 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 717 i, row3, row2, row1, row0); 718 rc++; 719 } else { 720 break; 721 } 722 } 723 724 /* USTORM */ 725 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 726 USTORM_ASSERT_LIST_INDEX_OFFSET); 727 if (last_idx) 728 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 729 730 /* print the asserts */ 731 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 732 733 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 734 USTORM_ASSERT_LIST_OFFSET(i)); 735 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 736 USTORM_ASSERT_LIST_OFFSET(i) + 4); 737 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 738 USTORM_ASSERT_LIST_OFFSET(i) + 8); 739 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 740 USTORM_ASSERT_LIST_OFFSET(i) + 12); 741 742 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 743 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 744 i, row3, row2, row1, row0); 745 rc++; 746 } else { 747 break; 748 } 749 } 750 751 return rc; 752 } 753 754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 755 { 756 u32 addr, val; 757 u32 mark, offset; 758 __be32 data[9]; 759 int word; 760 u32 trace_shmem_base; 761 if (BP_NOMCP(bp)) { 762 BNX2X_ERR("NO MCP - can not dump\n"); 763 return; 764 } 765 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 766 (bp->common.bc_ver & 0xff0000) >> 16, 767 (bp->common.bc_ver & 0xff00) >> 8, 768 (bp->common.bc_ver & 0xff)); 769 770 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 771 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 772 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 773 774 if (BP_PATH(bp) == 0) 775 trace_shmem_base = bp->common.shmem_base; 776 else 777 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 778 addr = trace_shmem_base - 0x800; 779 780 /* validate TRCB signature */ 781 mark = REG_RD(bp, addr); 782 if (mark != MFW_TRACE_SIGNATURE) { 783 BNX2X_ERR("Trace buffer signature is missing."); 784 return ; 785 } 786 787 /* read cyclic buffer pointer */ 788 addr += 4; 789 mark = REG_RD(bp, addr); 790 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 791 + ((mark + 0x3) & ~0x3) - 0x08000000; 792 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 793 794 printk("%s", lvl); 795 796 /* dump buffer after the mark */ 797 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 798 for (word = 0; word < 8; word++) 799 data[word] = htonl(REG_RD(bp, offset + 4*word)); 800 data[8] = 0x0; 801 pr_cont("%s", (char *)data); 802 } 803 804 /* dump buffer before the mark */ 805 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 806 for (word = 0; word < 8; word++) 807 data[word] = htonl(REG_RD(bp, offset + 4*word)); 808 data[8] = 0x0; 809 pr_cont("%s", (char *)data); 810 } 811 printk("%s" "end of fw dump\n", lvl); 812 } 813 814 static void bnx2x_fw_dump(struct bnx2x *bp) 815 { 816 bnx2x_fw_dump_lvl(bp, KERN_ERR); 817 } 818 819 static void bnx2x_hc_int_disable(struct bnx2x *bp) 820 { 821 int port = BP_PORT(bp); 822 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 823 u32 val = REG_RD(bp, addr); 824 825 /* in E1 we must use only PCI configuration space to disable 826 * MSI/MSIX capability 827 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 828 */ 829 if (CHIP_IS_E1(bp)) { 830 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 831 * Use mask register to prevent from HC sending interrupts 832 * after we exit the function 833 */ 834 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 835 836 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 837 HC_CONFIG_0_REG_INT_LINE_EN_0 | 838 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 839 } else 840 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 841 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 842 HC_CONFIG_0_REG_INT_LINE_EN_0 | 843 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 844 845 DP(NETIF_MSG_IFDOWN, 846 "write %x to HC %d (addr 0x%x)\n", 847 val, port, addr); 848 849 /* flush all outstanding writes */ 850 mmiowb(); 851 852 REG_WR(bp, addr, val); 853 if (REG_RD(bp, addr) != val) 854 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 855 } 856 857 static void bnx2x_igu_int_disable(struct bnx2x *bp) 858 { 859 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 860 861 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 862 IGU_PF_CONF_INT_LINE_EN | 863 IGU_PF_CONF_ATTN_BIT_EN); 864 865 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 866 867 /* flush all outstanding writes */ 868 mmiowb(); 869 870 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 871 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 872 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 873 } 874 875 static void bnx2x_int_disable(struct bnx2x *bp) 876 { 877 if (bp->common.int_block == INT_BLOCK_HC) 878 bnx2x_hc_int_disable(bp); 879 else 880 bnx2x_igu_int_disable(bp); 881 } 882 883 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) 884 { 885 int i; 886 u16 j; 887 struct hc_sp_status_block_data sp_sb_data; 888 int func = BP_FUNC(bp); 889 #ifdef BNX2X_STOP_ON_ERROR 890 u16 start = 0, end = 0; 891 u8 cos; 892 #endif 893 if (disable_int) 894 bnx2x_int_disable(bp); 895 896 bp->stats_state = STATS_STATE_DISABLED; 897 bp->eth_stats.unrecoverable_error++; 898 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 899 900 BNX2X_ERR("begin crash dump -----------------\n"); 901 902 /* Indices */ 903 /* Common */ 904 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 905 bp->def_idx, bp->def_att_idx, bp->attn_state, 906 bp->spq_prod_idx, bp->stats_counter); 907 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 908 bp->def_status_blk->atten_status_block.attn_bits, 909 bp->def_status_blk->atten_status_block.attn_bits_ack, 910 bp->def_status_blk->atten_status_block.status_block_id, 911 bp->def_status_blk->atten_status_block.attn_bits_index); 912 BNX2X_ERR(" def ("); 913 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 914 pr_cont("0x%x%s", 915 bp->def_status_blk->sp_sb.index_values[i], 916 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 917 918 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 919 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 920 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 921 i*sizeof(u32)); 922 923 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 924 sp_sb_data.igu_sb_id, 925 sp_sb_data.igu_seg_id, 926 sp_sb_data.p_func.pf_id, 927 sp_sb_data.p_func.vnic_id, 928 sp_sb_data.p_func.vf_id, 929 sp_sb_data.p_func.vf_valid, 930 sp_sb_data.state); 931 932 for_each_eth_queue(bp, i) { 933 struct bnx2x_fastpath *fp = &bp->fp[i]; 934 int loop; 935 struct hc_status_block_data_e2 sb_data_e2; 936 struct hc_status_block_data_e1x sb_data_e1x; 937 struct hc_status_block_sm *hc_sm_p = 938 CHIP_IS_E1x(bp) ? 939 sb_data_e1x.common.state_machine : 940 sb_data_e2.common.state_machine; 941 struct hc_index_data *hc_index_p = 942 CHIP_IS_E1x(bp) ? 943 sb_data_e1x.index_data : 944 sb_data_e2.index_data; 945 u8 data_size, cos; 946 u32 *sb_data_p; 947 struct bnx2x_fp_txdata txdata; 948 949 /* Rx */ 950 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 951 i, fp->rx_bd_prod, fp->rx_bd_cons, 952 fp->rx_comp_prod, 953 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 954 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 955 fp->rx_sge_prod, fp->last_max_sge, 956 le16_to_cpu(fp->fp_hc_idx)); 957 958 /* Tx */ 959 for_each_cos_in_tx_queue(fp, cos) 960 { 961 txdata = *fp->txdata_ptr[cos]; 962 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 963 i, txdata.tx_pkt_prod, 964 txdata.tx_pkt_cons, txdata.tx_bd_prod, 965 txdata.tx_bd_cons, 966 le16_to_cpu(*txdata.tx_cons_sb)); 967 } 968 969 loop = CHIP_IS_E1x(bp) ? 970 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 971 972 /* host sb data */ 973 974 if (IS_FCOE_FP(fp)) 975 continue; 976 977 BNX2X_ERR(" run indexes ("); 978 for (j = 0; j < HC_SB_MAX_SM; j++) 979 pr_cont("0x%x%s", 980 fp->sb_running_index[j], 981 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 982 983 BNX2X_ERR(" indexes ("); 984 for (j = 0; j < loop; j++) 985 pr_cont("0x%x%s", 986 fp->sb_index_values[j], 987 (j == loop - 1) ? ")" : " "); 988 /* fw sb data */ 989 data_size = CHIP_IS_E1x(bp) ? 990 sizeof(struct hc_status_block_data_e1x) : 991 sizeof(struct hc_status_block_data_e2); 992 data_size /= sizeof(u32); 993 sb_data_p = CHIP_IS_E1x(bp) ? 994 (u32 *)&sb_data_e1x : 995 (u32 *)&sb_data_e2; 996 /* copy sb data in here */ 997 for (j = 0; j < data_size; j++) 998 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 999 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 1000 j * sizeof(u32)); 1001 1002 if (!CHIP_IS_E1x(bp)) { 1003 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1004 sb_data_e2.common.p_func.pf_id, 1005 sb_data_e2.common.p_func.vf_id, 1006 sb_data_e2.common.p_func.vf_valid, 1007 sb_data_e2.common.p_func.vnic_id, 1008 sb_data_e2.common.same_igu_sb_1b, 1009 sb_data_e2.common.state); 1010 } else { 1011 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1012 sb_data_e1x.common.p_func.pf_id, 1013 sb_data_e1x.common.p_func.vf_id, 1014 sb_data_e1x.common.p_func.vf_valid, 1015 sb_data_e1x.common.p_func.vnic_id, 1016 sb_data_e1x.common.same_igu_sb_1b, 1017 sb_data_e1x.common.state); 1018 } 1019 1020 /* SB_SMs data */ 1021 for (j = 0; j < HC_SB_MAX_SM; j++) { 1022 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 1023 j, hc_sm_p[j].__flags, 1024 hc_sm_p[j].igu_sb_id, 1025 hc_sm_p[j].igu_seg_id, 1026 hc_sm_p[j].time_to_expire, 1027 hc_sm_p[j].timer_value); 1028 } 1029 1030 /* Indices data */ 1031 for (j = 0; j < loop; j++) { 1032 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 1033 hc_index_p[j].flags, 1034 hc_index_p[j].timeout); 1035 } 1036 } 1037 1038 #ifdef BNX2X_STOP_ON_ERROR 1039 1040 /* event queue */ 1041 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); 1042 for (i = 0; i < NUM_EQ_DESC; i++) { 1043 u32 *data = (u32 *)&bp->eq_ring[i].message.data; 1044 1045 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", 1046 i, bp->eq_ring[i].message.opcode, 1047 bp->eq_ring[i].message.error); 1048 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]); 1049 } 1050 1051 /* Rings */ 1052 /* Rx */ 1053 for_each_valid_rx_queue(bp, i) { 1054 struct bnx2x_fastpath *fp = &bp->fp[i]; 1055 1056 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 1057 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 1058 for (j = start; j != end; j = RX_BD(j + 1)) { 1059 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 1060 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 1061 1062 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 1063 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 1064 } 1065 1066 start = RX_SGE(fp->rx_sge_prod); 1067 end = RX_SGE(fp->last_max_sge); 1068 for (j = start; j != end; j = RX_SGE(j + 1)) { 1069 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 1070 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 1071 1072 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 1073 i, j, rx_sge[1], rx_sge[0], sw_page->page); 1074 } 1075 1076 start = RCQ_BD(fp->rx_comp_cons - 10); 1077 end = RCQ_BD(fp->rx_comp_cons + 503); 1078 for (j = start; j != end; j = RCQ_BD(j + 1)) { 1079 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 1080 1081 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 1082 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 1083 } 1084 } 1085 1086 /* Tx */ 1087 for_each_valid_tx_queue(bp, i) { 1088 struct bnx2x_fastpath *fp = &bp->fp[i]; 1089 for_each_cos_in_tx_queue(fp, cos) { 1090 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; 1091 1092 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 1093 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 1094 for (j = start; j != end; j = TX_BD(j + 1)) { 1095 struct sw_tx_bd *sw_bd = 1096 &txdata->tx_buf_ring[j]; 1097 1098 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 1099 i, cos, j, sw_bd->skb, 1100 sw_bd->first_bd); 1101 } 1102 1103 start = TX_BD(txdata->tx_bd_cons - 10); 1104 end = TX_BD(txdata->tx_bd_cons + 254); 1105 for (j = start; j != end; j = TX_BD(j + 1)) { 1106 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 1107 1108 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 1109 i, cos, j, tx_bd[0], tx_bd[1], 1110 tx_bd[2], tx_bd[3]); 1111 } 1112 } 1113 } 1114 #endif 1115 bnx2x_fw_dump(bp); 1116 bnx2x_mc_assert(bp); 1117 BNX2X_ERR("end crash dump -----------------\n"); 1118 } 1119 1120 /* 1121 * FLR Support for E2 1122 * 1123 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1124 * initialization. 1125 */ 1126 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ 1127 #define FLR_WAIT_INTERVAL 50 /* usec */ 1128 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1129 1130 struct pbf_pN_buf_regs { 1131 int pN; 1132 u32 init_crd; 1133 u32 crd; 1134 u32 crd_freed; 1135 }; 1136 1137 struct pbf_pN_cmd_regs { 1138 int pN; 1139 u32 lines_occup; 1140 u32 lines_freed; 1141 }; 1142 1143 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1144 struct pbf_pN_buf_regs *regs, 1145 u32 poll_count) 1146 { 1147 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1148 u32 cur_cnt = poll_count; 1149 1150 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1151 crd = crd_start = REG_RD(bp, regs->crd); 1152 init_crd = REG_RD(bp, regs->init_crd); 1153 1154 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1155 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1156 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1157 1158 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1159 (init_crd - crd_start))) { 1160 if (cur_cnt--) { 1161 udelay(FLR_WAIT_INTERVAL); 1162 crd = REG_RD(bp, regs->crd); 1163 crd_freed = REG_RD(bp, regs->crd_freed); 1164 } else { 1165 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1166 regs->pN); 1167 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1168 regs->pN, crd); 1169 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1170 regs->pN, crd_freed); 1171 break; 1172 } 1173 } 1174 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1175 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1176 } 1177 1178 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1179 struct pbf_pN_cmd_regs *regs, 1180 u32 poll_count) 1181 { 1182 u32 occup, to_free, freed, freed_start; 1183 u32 cur_cnt = poll_count; 1184 1185 occup = to_free = REG_RD(bp, regs->lines_occup); 1186 freed = freed_start = REG_RD(bp, regs->lines_freed); 1187 1188 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1189 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1190 1191 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1192 if (cur_cnt--) { 1193 udelay(FLR_WAIT_INTERVAL); 1194 occup = REG_RD(bp, regs->lines_occup); 1195 freed = REG_RD(bp, regs->lines_freed); 1196 } else { 1197 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1198 regs->pN); 1199 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1200 regs->pN, occup); 1201 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1202 regs->pN, freed); 1203 break; 1204 } 1205 } 1206 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1207 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1208 } 1209 1210 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1211 u32 expected, u32 poll_count) 1212 { 1213 u32 cur_cnt = poll_count; 1214 u32 val; 1215 1216 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1217 udelay(FLR_WAIT_INTERVAL); 1218 1219 return val; 1220 } 1221 1222 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1223 char *msg, u32 poll_cnt) 1224 { 1225 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1226 if (val != 0) { 1227 BNX2X_ERR("%s usage count=%d\n", msg, val); 1228 return 1; 1229 } 1230 return 0; 1231 } 1232 1233 /* Common routines with VF FLR cleanup */ 1234 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1235 { 1236 /* adjust polling timeout */ 1237 if (CHIP_REV_IS_EMUL(bp)) 1238 return FLR_POLL_CNT * 2000; 1239 1240 if (CHIP_REV_IS_FPGA(bp)) 1241 return FLR_POLL_CNT * 120; 1242 1243 return FLR_POLL_CNT; 1244 } 1245 1246 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1247 { 1248 struct pbf_pN_cmd_regs cmd_regs[] = { 1249 {0, (CHIP_IS_E3B0(bp)) ? 1250 PBF_REG_TQ_OCCUPANCY_Q0 : 1251 PBF_REG_P0_TQ_OCCUPANCY, 1252 (CHIP_IS_E3B0(bp)) ? 1253 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1254 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1255 {1, (CHIP_IS_E3B0(bp)) ? 1256 PBF_REG_TQ_OCCUPANCY_Q1 : 1257 PBF_REG_P1_TQ_OCCUPANCY, 1258 (CHIP_IS_E3B0(bp)) ? 1259 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1260 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1261 {4, (CHIP_IS_E3B0(bp)) ? 1262 PBF_REG_TQ_OCCUPANCY_LB_Q : 1263 PBF_REG_P4_TQ_OCCUPANCY, 1264 (CHIP_IS_E3B0(bp)) ? 1265 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1266 PBF_REG_P4_TQ_LINES_FREED_CNT} 1267 }; 1268 1269 struct pbf_pN_buf_regs buf_regs[] = { 1270 {0, (CHIP_IS_E3B0(bp)) ? 1271 PBF_REG_INIT_CRD_Q0 : 1272 PBF_REG_P0_INIT_CRD , 1273 (CHIP_IS_E3B0(bp)) ? 1274 PBF_REG_CREDIT_Q0 : 1275 PBF_REG_P0_CREDIT, 1276 (CHIP_IS_E3B0(bp)) ? 1277 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1278 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1279 {1, (CHIP_IS_E3B0(bp)) ? 1280 PBF_REG_INIT_CRD_Q1 : 1281 PBF_REG_P1_INIT_CRD, 1282 (CHIP_IS_E3B0(bp)) ? 1283 PBF_REG_CREDIT_Q1 : 1284 PBF_REG_P1_CREDIT, 1285 (CHIP_IS_E3B0(bp)) ? 1286 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1287 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1288 {4, (CHIP_IS_E3B0(bp)) ? 1289 PBF_REG_INIT_CRD_LB_Q : 1290 PBF_REG_P4_INIT_CRD, 1291 (CHIP_IS_E3B0(bp)) ? 1292 PBF_REG_CREDIT_LB_Q : 1293 PBF_REG_P4_CREDIT, 1294 (CHIP_IS_E3B0(bp)) ? 1295 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1296 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1297 }; 1298 1299 int i; 1300 1301 /* Verify the command queues are flushed P0, P1, P4 */ 1302 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1303 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1304 1305 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1306 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1307 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1308 } 1309 1310 #define OP_GEN_PARAM(param) \ 1311 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1312 1313 #define OP_GEN_TYPE(type) \ 1314 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1315 1316 #define OP_GEN_AGG_VECT(index) \ 1317 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1318 1319 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) 1320 { 1321 u32 op_gen_command = 0; 1322 u32 comp_addr = BAR_CSTRORM_INTMEM + 1323 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1324 int ret = 0; 1325 1326 if (REG_RD(bp, comp_addr)) { 1327 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1328 return 1; 1329 } 1330 1331 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1332 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1333 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 1334 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1335 1336 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1337 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); 1338 1339 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1340 BNX2X_ERR("FW final cleanup did not succeed\n"); 1341 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1342 (REG_RD(bp, comp_addr))); 1343 bnx2x_panic(); 1344 return 1; 1345 } 1346 /* Zero completion for next FLR */ 1347 REG_WR(bp, comp_addr, 0); 1348 1349 return ret; 1350 } 1351 1352 u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1353 { 1354 u16 status; 1355 1356 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 1357 return status & PCI_EXP_DEVSTA_TRPND; 1358 } 1359 1360 /* PF FLR specific routines 1361 */ 1362 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1363 { 1364 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1365 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1366 CFC_REG_NUM_LCIDS_INSIDE_PF, 1367 "CFC PF usage counter timed out", 1368 poll_cnt)) 1369 return 1; 1370 1371 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1372 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1373 DORQ_REG_PF_USAGE_CNT, 1374 "DQ PF usage counter timed out", 1375 poll_cnt)) 1376 return 1; 1377 1378 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1379 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1380 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1381 "QM PF usage counter timed out", 1382 poll_cnt)) 1383 return 1; 1384 1385 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1386 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1387 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1388 "Timers VNIC usage counter timed out", 1389 poll_cnt)) 1390 return 1; 1391 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1392 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1393 "Timers NUM_SCANS usage counter timed out", 1394 poll_cnt)) 1395 return 1; 1396 1397 /* Wait DMAE PF usage counter to zero */ 1398 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1399 dmae_reg_go_c[INIT_DMAE_C(bp)], 1400 "DMAE command register timed out", 1401 poll_cnt)) 1402 return 1; 1403 1404 return 0; 1405 } 1406 1407 static void bnx2x_hw_enable_status(struct bnx2x *bp) 1408 { 1409 u32 val; 1410 1411 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1412 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1413 1414 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1415 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1416 1417 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1418 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1419 1420 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1421 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1422 1423 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1424 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1425 1426 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1427 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1428 1429 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1430 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1431 1432 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1433 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1434 val); 1435 } 1436 1437 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1438 { 1439 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1440 1441 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1442 1443 /* Re-enable PF target read access */ 1444 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1445 1446 /* Poll HW usage counters */ 1447 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1448 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1449 return -EBUSY; 1450 1451 /* Zero the igu 'trailing edge' and 'leading edge' */ 1452 1453 /* Send the FW cleanup command */ 1454 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1455 return -EBUSY; 1456 1457 /* ATC cleanup */ 1458 1459 /* Verify TX hw is flushed */ 1460 bnx2x_tx_hw_flushed(bp, poll_cnt); 1461 1462 /* Wait 100ms (not adjusted according to platform) */ 1463 msleep(100); 1464 1465 /* Verify no pending pci transactions */ 1466 if (bnx2x_is_pcie_pending(bp->pdev)) 1467 BNX2X_ERR("PCIE Transactions still pending\n"); 1468 1469 /* Debug */ 1470 bnx2x_hw_enable_status(bp); 1471 1472 /* 1473 * Master enable - Due to WB DMAE writes performed before this 1474 * register is re-initialized as part of the regular function init 1475 */ 1476 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1477 1478 return 0; 1479 } 1480 1481 static void bnx2x_hc_int_enable(struct bnx2x *bp) 1482 { 1483 int port = BP_PORT(bp); 1484 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1485 u32 val = REG_RD(bp, addr); 1486 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1487 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1488 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1489 1490 if (msix) { 1491 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1492 HC_CONFIG_0_REG_INT_LINE_EN_0); 1493 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1495 if (single_msix) 1496 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 1497 } else if (msi) { 1498 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1499 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1500 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1501 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1502 } else { 1503 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1504 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1505 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1506 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1507 1508 if (!CHIP_IS_E1(bp)) { 1509 DP(NETIF_MSG_IFUP, 1510 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1511 1512 REG_WR(bp, addr, val); 1513 1514 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1515 } 1516 } 1517 1518 if (CHIP_IS_E1(bp)) 1519 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1520 1521 DP(NETIF_MSG_IFUP, 1522 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1523 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1524 1525 REG_WR(bp, addr, val); 1526 /* 1527 * Ensure that HC_CONFIG is written before leading/trailing edge config 1528 */ 1529 mmiowb(); 1530 barrier(); 1531 1532 if (!CHIP_IS_E1(bp)) { 1533 /* init leading/trailing edge */ 1534 if (IS_MF(bp)) { 1535 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1536 if (bp->port.pmf) 1537 /* enable nig and gpio3 attention */ 1538 val |= 0x1100; 1539 } else 1540 val = 0xffff; 1541 1542 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1543 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1544 } 1545 1546 /* Make sure that interrupts are indeed enabled from here on */ 1547 mmiowb(); 1548 } 1549 1550 static void bnx2x_igu_int_enable(struct bnx2x *bp) 1551 { 1552 u32 val; 1553 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1554 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1555 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1556 1557 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1558 1559 if (msix) { 1560 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1561 IGU_PF_CONF_SINGLE_ISR_EN); 1562 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1563 IGU_PF_CONF_ATTN_BIT_EN); 1564 1565 if (single_msix) 1566 val |= IGU_PF_CONF_SINGLE_ISR_EN; 1567 } else if (msi) { 1568 val &= ~IGU_PF_CONF_INT_LINE_EN; 1569 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1570 IGU_PF_CONF_ATTN_BIT_EN | 1571 IGU_PF_CONF_SINGLE_ISR_EN); 1572 } else { 1573 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1574 val |= (IGU_PF_CONF_INT_LINE_EN | 1575 IGU_PF_CONF_ATTN_BIT_EN | 1576 IGU_PF_CONF_SINGLE_ISR_EN); 1577 } 1578 1579 /* Clean previous status - need to configure igu prior to ack*/ 1580 if ((!msix) || single_msix) { 1581 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1582 bnx2x_ack_int(bp); 1583 } 1584 1585 val |= IGU_PF_CONF_FUNC_EN; 1586 1587 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1588 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1589 1590 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1591 1592 if (val & IGU_PF_CONF_INT_LINE_EN) 1593 pci_intx(bp->pdev, true); 1594 1595 barrier(); 1596 1597 /* init leading/trailing edge */ 1598 if (IS_MF(bp)) { 1599 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1600 if (bp->port.pmf) 1601 /* enable nig and gpio3 attention */ 1602 val |= 0x1100; 1603 } else 1604 val = 0xffff; 1605 1606 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1607 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1608 1609 /* Make sure that interrupts are indeed enabled from here on */ 1610 mmiowb(); 1611 } 1612 1613 void bnx2x_int_enable(struct bnx2x *bp) 1614 { 1615 if (bp->common.int_block == INT_BLOCK_HC) 1616 bnx2x_hc_int_enable(bp); 1617 else 1618 bnx2x_igu_int_enable(bp); 1619 } 1620 1621 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1622 { 1623 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1624 int i, offset; 1625 1626 if (disable_hw) 1627 /* prevent the HW from sending interrupts */ 1628 bnx2x_int_disable(bp); 1629 1630 /* make sure all ISRs are done */ 1631 if (msix) { 1632 synchronize_irq(bp->msix_table[0].vector); 1633 offset = 1; 1634 if (CNIC_SUPPORT(bp)) 1635 offset++; 1636 for_each_eth_queue(bp, i) 1637 synchronize_irq(bp->msix_table[offset++].vector); 1638 } else 1639 synchronize_irq(bp->pdev->irq); 1640 1641 /* make sure sp_task is not running */ 1642 cancel_delayed_work(&bp->sp_task); 1643 cancel_delayed_work(&bp->period_task); 1644 flush_workqueue(bnx2x_wq); 1645 } 1646 1647 /* fast path */ 1648 1649 /* 1650 * General service functions 1651 */ 1652 1653 /* Return true if succeeded to acquire the lock */ 1654 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1655 { 1656 u32 lock_status; 1657 u32 resource_bit = (1 << resource); 1658 int func = BP_FUNC(bp); 1659 u32 hw_lock_control_reg; 1660 1661 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1662 "Trying to take a lock on resource %d\n", resource); 1663 1664 /* Validating that the resource is within range */ 1665 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1666 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1667 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1668 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1669 return false; 1670 } 1671 1672 if (func <= 5) 1673 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1674 else 1675 hw_lock_control_reg = 1676 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1677 1678 /* Try to acquire the lock */ 1679 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1680 lock_status = REG_RD(bp, hw_lock_control_reg); 1681 if (lock_status & resource_bit) 1682 return true; 1683 1684 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1685 "Failed to get a lock on resource %d\n", resource); 1686 return false; 1687 } 1688 1689 /** 1690 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1691 * 1692 * @bp: driver handle 1693 * 1694 * Returns the recovery leader resource id according to the engine this function 1695 * belongs to. Currently only only 2 engines is supported. 1696 */ 1697 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1698 { 1699 if (BP_PATH(bp)) 1700 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1701 else 1702 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1703 } 1704 1705 /** 1706 * bnx2x_trylock_leader_lock- try to acquire a leader lock. 1707 * 1708 * @bp: driver handle 1709 * 1710 * Tries to acquire a leader lock for current engine. 1711 */ 1712 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1713 { 1714 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1715 } 1716 1717 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1718 1719 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ 1720 static int bnx2x_schedule_sp_task(struct bnx2x *bp) 1721 { 1722 /* Set the interrupt occurred bit for the sp-task to recognize it 1723 * must ack the interrupt and transition according to the IGU 1724 * state machine. 1725 */ 1726 atomic_set(&bp->interrupt_occurred, 1); 1727 1728 /* The sp_task must execute only after this bit 1729 * is set, otherwise we will get out of sync and miss all 1730 * further interrupts. Hence, the barrier. 1731 */ 1732 smp_wmb(); 1733 1734 /* schedule sp_task to workqueue */ 1735 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1736 } 1737 1738 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1739 { 1740 struct bnx2x *bp = fp->bp; 1741 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1742 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1743 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1744 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 1745 1746 DP(BNX2X_MSG_SP, 1747 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1748 fp->index, cid, command, bp->state, 1749 rr_cqe->ramrod_cqe.ramrod_type); 1750 1751 /* If cid is within VF range, replace the slowpath object with the 1752 * one corresponding to this VF 1753 */ 1754 if (cid >= BNX2X_FIRST_VF_CID && 1755 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) 1756 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); 1757 1758 switch (command) { 1759 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1760 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1761 drv_cmd = BNX2X_Q_CMD_UPDATE; 1762 break; 1763 1764 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1765 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1766 drv_cmd = BNX2X_Q_CMD_SETUP; 1767 break; 1768 1769 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1770 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1771 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1772 break; 1773 1774 case (RAMROD_CMD_ID_ETH_HALT): 1775 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1776 drv_cmd = BNX2X_Q_CMD_HALT; 1777 break; 1778 1779 case (RAMROD_CMD_ID_ETH_TERMINATE): 1780 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); 1781 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1782 break; 1783 1784 case (RAMROD_CMD_ID_ETH_EMPTY): 1785 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1786 drv_cmd = BNX2X_Q_CMD_EMPTY; 1787 break; 1788 1789 default: 1790 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1791 command, fp->index); 1792 return; 1793 } 1794 1795 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1796 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1797 /* q_obj->complete_cmd() failure means that this was 1798 * an unexpected completion. 1799 * 1800 * In this case we don't want to increase the bp->spq_left 1801 * because apparently we haven't sent this command the first 1802 * place. 1803 */ 1804 #ifdef BNX2X_STOP_ON_ERROR 1805 bnx2x_panic(); 1806 #else 1807 return; 1808 #endif 1809 /* SRIOV: reschedule any 'in_progress' operations */ 1810 bnx2x_iov_sp_event(bp, cid, true); 1811 1812 smp_mb__before_atomic_inc(); 1813 atomic_inc(&bp->cq_spq_left); 1814 /* push the change in bp->spq_left and towards the memory */ 1815 smp_mb__after_atomic_inc(); 1816 1817 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1818 1819 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 1820 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { 1821 /* if Q update ramrod is completed for last Q in AFEX vif set 1822 * flow, then ACK MCP at the end 1823 * 1824 * mark pending ACK to MCP bit. 1825 * prevent case that both bits are cleared. 1826 * At the end of load/unload driver checks that 1827 * sp_state is cleared, and this order prevents 1828 * races 1829 */ 1830 smp_mb__before_clear_bit(); 1831 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); 1832 wmb(); 1833 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 1834 smp_mb__after_clear_bit(); 1835 1836 /* schedule the sp task as mcp ack is required */ 1837 bnx2x_schedule_sp_task(bp); 1838 } 1839 1840 return; 1841 } 1842 1843 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1844 { 1845 struct bnx2x *bp = netdev_priv(dev_instance); 1846 u16 status = bnx2x_ack_int(bp); 1847 u16 mask; 1848 int i; 1849 u8 cos; 1850 1851 /* Return here if interrupt is shared and it's not for us */ 1852 if (unlikely(status == 0)) { 1853 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1854 return IRQ_NONE; 1855 } 1856 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1857 1858 #ifdef BNX2X_STOP_ON_ERROR 1859 if (unlikely(bp->panic)) 1860 return IRQ_HANDLED; 1861 #endif 1862 1863 for_each_eth_queue(bp, i) { 1864 struct bnx2x_fastpath *fp = &bp->fp[i]; 1865 1866 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); 1867 if (status & mask) { 1868 /* Handle Rx or Tx according to SB id */ 1869 for_each_cos_in_tx_queue(fp, cos) 1870 prefetch(fp->txdata_ptr[cos]->tx_cons_sb); 1871 prefetch(&fp->sb_running_index[SM_RX_ID]); 1872 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1873 status &= ~mask; 1874 } 1875 } 1876 1877 if (CNIC_SUPPORT(bp)) { 1878 mask = 0x2; 1879 if (status & (mask | 0x1)) { 1880 struct cnic_ops *c_ops = NULL; 1881 1882 rcu_read_lock(); 1883 c_ops = rcu_dereference(bp->cnic_ops); 1884 if (c_ops && (bp->cnic_eth_dev.drv_state & 1885 CNIC_DRV_STATE_HANDLES_IRQ)) 1886 c_ops->cnic_handler(bp->cnic_data, NULL); 1887 rcu_read_unlock(); 1888 1889 status &= ~mask; 1890 } 1891 } 1892 1893 if (unlikely(status & 0x1)) { 1894 1895 /* schedule sp task to perform default status block work, ack 1896 * attentions and enable interrupts. 1897 */ 1898 bnx2x_schedule_sp_task(bp); 1899 1900 status &= ~0x1; 1901 if (!status) 1902 return IRQ_HANDLED; 1903 } 1904 1905 if (unlikely(status)) 1906 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1907 status); 1908 1909 return IRQ_HANDLED; 1910 } 1911 1912 /* Link */ 1913 1914 /* 1915 * General service functions 1916 */ 1917 1918 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1919 { 1920 u32 lock_status; 1921 u32 resource_bit = (1 << resource); 1922 int func = BP_FUNC(bp); 1923 u32 hw_lock_control_reg; 1924 int cnt; 1925 1926 /* Validating that the resource is within range */ 1927 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1928 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1929 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1930 return -EINVAL; 1931 } 1932 1933 if (func <= 5) { 1934 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1935 } else { 1936 hw_lock_control_reg = 1937 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1938 } 1939 1940 /* Validating that the resource is not already taken */ 1941 lock_status = REG_RD(bp, hw_lock_control_reg); 1942 if (lock_status & resource_bit) { 1943 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 1944 lock_status, resource_bit); 1945 return -EEXIST; 1946 } 1947 1948 /* Try for 5 second every 5ms */ 1949 for (cnt = 0; cnt < 1000; cnt++) { 1950 /* Try to acquire the lock */ 1951 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1952 lock_status = REG_RD(bp, hw_lock_control_reg); 1953 if (lock_status & resource_bit) 1954 return 0; 1955 1956 usleep_range(5000, 10000); 1957 } 1958 BNX2X_ERR("Timeout\n"); 1959 return -EAGAIN; 1960 } 1961 1962 int bnx2x_release_leader_lock(struct bnx2x *bp) 1963 { 1964 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1965 } 1966 1967 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1968 { 1969 u32 lock_status; 1970 u32 resource_bit = (1 << resource); 1971 int func = BP_FUNC(bp); 1972 u32 hw_lock_control_reg; 1973 1974 /* Validating that the resource is within range */ 1975 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1976 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1977 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1978 return -EINVAL; 1979 } 1980 1981 if (func <= 5) { 1982 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1983 } else { 1984 hw_lock_control_reg = 1985 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1986 } 1987 1988 /* Validating that the resource is currently taken */ 1989 lock_status = REG_RD(bp, hw_lock_control_reg); 1990 if (!(lock_status & resource_bit)) { 1991 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", 1992 lock_status, resource_bit); 1993 return -EFAULT; 1994 } 1995 1996 REG_WR(bp, hw_lock_control_reg, resource_bit); 1997 return 0; 1998 } 1999 2000 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 2001 { 2002 /* The GPIO should be swapped if swap register is set and active */ 2003 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2004 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2005 int gpio_shift = gpio_num + 2006 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2007 u32 gpio_mask = (1 << gpio_shift); 2008 u32 gpio_reg; 2009 int value; 2010 2011 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2012 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2013 return -EINVAL; 2014 } 2015 2016 /* read GPIO value */ 2017 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2018 2019 /* get the requested pin value */ 2020 if ((gpio_reg & gpio_mask) == gpio_mask) 2021 value = 1; 2022 else 2023 value = 0; 2024 2025 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 2026 2027 return value; 2028 } 2029 2030 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2031 { 2032 /* The GPIO should be swapped if swap register is set and active */ 2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2035 int gpio_shift = gpio_num + 2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2037 u32 gpio_mask = (1 << gpio_shift); 2038 u32 gpio_reg; 2039 2040 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2042 return -EINVAL; 2043 } 2044 2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2046 /* read GPIO and mask except the float bits */ 2047 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2048 2049 switch (mode) { 2050 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2051 DP(NETIF_MSG_LINK, 2052 "Set GPIO %d (shift %d) -> output low\n", 2053 gpio_num, gpio_shift); 2054 /* clear FLOAT and set CLR */ 2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2057 break; 2058 2059 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2060 DP(NETIF_MSG_LINK, 2061 "Set GPIO %d (shift %d) -> output high\n", 2062 gpio_num, gpio_shift); 2063 /* clear FLOAT and set SET */ 2064 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2065 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2066 break; 2067 2068 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2069 DP(NETIF_MSG_LINK, 2070 "Set GPIO %d (shift %d) -> input\n", 2071 gpio_num, gpio_shift); 2072 /* set FLOAT */ 2073 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2074 break; 2075 2076 default: 2077 break; 2078 } 2079 2080 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2081 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2082 2083 return 0; 2084 } 2085 2086 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 2087 { 2088 u32 gpio_reg = 0; 2089 int rc = 0; 2090 2091 /* Any port swapping should be handled by caller. */ 2092 2093 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2094 /* read GPIO and mask except the float bits */ 2095 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2096 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2097 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2098 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2099 2100 switch (mode) { 2101 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2102 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2103 /* set CLR */ 2104 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2105 break; 2106 2107 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2108 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2109 /* set SET */ 2110 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2111 break; 2112 2113 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2114 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2115 /* set FLOAT */ 2116 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2117 break; 2118 2119 default: 2120 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2121 rc = -EINVAL; 2122 break; 2123 } 2124 2125 if (rc == 0) 2126 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2127 2128 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2129 2130 return rc; 2131 } 2132 2133 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2134 { 2135 /* The GPIO should be swapped if swap register is set and active */ 2136 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2137 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2138 int gpio_shift = gpio_num + 2139 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2140 u32 gpio_mask = (1 << gpio_shift); 2141 u32 gpio_reg; 2142 2143 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2144 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2145 return -EINVAL; 2146 } 2147 2148 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2149 /* read GPIO int */ 2150 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2151 2152 switch (mode) { 2153 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2154 DP(NETIF_MSG_LINK, 2155 "Clear GPIO INT %d (shift %d) -> output low\n", 2156 gpio_num, gpio_shift); 2157 /* clear SET and set CLR */ 2158 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2159 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2160 break; 2161 2162 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2163 DP(NETIF_MSG_LINK, 2164 "Set GPIO INT %d (shift %d) -> output high\n", 2165 gpio_num, gpio_shift); 2166 /* clear CLR and set SET */ 2167 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2168 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2169 break; 2170 2171 default: 2172 break; 2173 } 2174 2175 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2176 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2177 2178 return 0; 2179 } 2180 2181 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) 2182 { 2183 u32 spio_reg; 2184 2185 /* Only 2 SPIOs are configurable */ 2186 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 2187 BNX2X_ERR("Invalid SPIO 0x%x\n", spio); 2188 return -EINVAL; 2189 } 2190 2191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2192 /* read SPIO and mask except the float bits */ 2193 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 2194 2195 switch (mode) { 2196 case MISC_SPIO_OUTPUT_LOW: 2197 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); 2198 /* clear FLOAT and set CLR */ 2199 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2200 spio_reg |= (spio << MISC_SPIO_CLR_POS); 2201 break; 2202 2203 case MISC_SPIO_OUTPUT_HIGH: 2204 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); 2205 /* clear FLOAT and set SET */ 2206 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2207 spio_reg |= (spio << MISC_SPIO_SET_POS); 2208 break; 2209 2210 case MISC_SPIO_INPUT_HI_Z: 2211 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); 2212 /* set FLOAT */ 2213 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 2214 break; 2215 2216 default: 2217 break; 2218 } 2219 2220 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2221 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2222 2223 return 0; 2224 } 2225 2226 void bnx2x_calc_fc_adv(struct bnx2x *bp) 2227 { 2228 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2229 switch (bp->link_vars.ieee_fc & 2230 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2231 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2232 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2233 ADVERTISED_Pause); 2234 break; 2235 2236 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2237 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2238 ADVERTISED_Pause); 2239 break; 2240 2241 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2242 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2243 break; 2244 2245 default: 2246 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2247 ADVERTISED_Pause); 2248 break; 2249 } 2250 } 2251 2252 static void bnx2x_set_requested_fc(struct bnx2x *bp) 2253 { 2254 /* Initialize link parameters structure variables 2255 * It is recommended to turn off RX FC for jumbo frames 2256 * for better performance 2257 */ 2258 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2259 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2260 else 2261 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2262 } 2263 2264 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2265 { 2266 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); 2267 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2268 2269 if (!BP_NOMCP(bp)) { 2270 bnx2x_set_requested_fc(bp); 2271 bnx2x_acquire_phy_lock(bp); 2272 2273 if (load_mode == LOAD_DIAG) { 2274 struct link_params *lp = &bp->link_params; 2275 lp->loopback_mode = LOOPBACK_XGXS; 2276 /* do PHY loopback at 10G speed, if possible */ 2277 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2278 if (lp->speed_cap_mask[cfx_idx] & 2279 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2280 lp->req_line_speed[cfx_idx] = 2281 SPEED_10000; 2282 else 2283 lp->req_line_speed[cfx_idx] = 2284 SPEED_1000; 2285 } 2286 } 2287 2288 if (load_mode == LOAD_LOOPBACK_EXT) { 2289 struct link_params *lp = &bp->link_params; 2290 lp->loopback_mode = LOOPBACK_EXT; 2291 } 2292 2293 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2294 2295 bnx2x_release_phy_lock(bp); 2296 2297 bnx2x_calc_fc_adv(bp); 2298 2299 if (bp->link_vars.link_up) { 2300 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2301 bnx2x_link_report(bp); 2302 } 2303 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2304 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2305 return rc; 2306 } 2307 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2308 return -EINVAL; 2309 } 2310 2311 void bnx2x_link_set(struct bnx2x *bp) 2312 { 2313 if (!BP_NOMCP(bp)) { 2314 bnx2x_acquire_phy_lock(bp); 2315 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2316 bnx2x_release_phy_lock(bp); 2317 2318 bnx2x_calc_fc_adv(bp); 2319 } else 2320 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2321 } 2322 2323 static void bnx2x__link_reset(struct bnx2x *bp) 2324 { 2325 if (!BP_NOMCP(bp)) { 2326 bnx2x_acquire_phy_lock(bp); 2327 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); 2328 bnx2x_release_phy_lock(bp); 2329 } else 2330 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2331 } 2332 2333 void bnx2x_force_link_reset(struct bnx2x *bp) 2334 { 2335 bnx2x_acquire_phy_lock(bp); 2336 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2337 bnx2x_release_phy_lock(bp); 2338 } 2339 2340 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2341 { 2342 u8 rc = 0; 2343 2344 if (!BP_NOMCP(bp)) { 2345 bnx2x_acquire_phy_lock(bp); 2346 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2347 is_serdes); 2348 bnx2x_release_phy_lock(bp); 2349 } else 2350 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2351 2352 return rc; 2353 } 2354 2355 /* Calculates the sum of vn_min_rates. 2356 It's needed for further normalizing of the min_rates. 2357 Returns: 2358 sum of vn_min_rates. 2359 or 2360 0 - if all the min_rates are 0. 2361 In the later case fairness algorithm should be deactivated. 2362 If not all min_rates are zero then those that are zeroes will be set to 1. 2363 */ 2364 static void bnx2x_calc_vn_min(struct bnx2x *bp, 2365 struct cmng_init_input *input) 2366 { 2367 int all_zero = 1; 2368 int vn; 2369 2370 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2371 u32 vn_cfg = bp->mf_config[vn]; 2372 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2373 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2374 2375 /* Skip hidden vns */ 2376 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2377 vn_min_rate = 0; 2378 /* If min rate is zero - set it to 1 */ 2379 else if (!vn_min_rate) 2380 vn_min_rate = DEF_MIN_RATE; 2381 else 2382 all_zero = 0; 2383 2384 input->vnic_min_rate[vn] = vn_min_rate; 2385 } 2386 2387 /* if ETS or all min rates are zeros - disable fairness */ 2388 if (BNX2X_IS_ETS_ENABLED(bp)) { 2389 input->flags.cmng_enables &= 2390 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2391 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2392 } else if (all_zero) { 2393 input->flags.cmng_enables &= 2394 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2395 DP(NETIF_MSG_IFUP, 2396 "All MIN values are zeroes fairness will be disabled\n"); 2397 } else 2398 input->flags.cmng_enables |= 2399 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2400 } 2401 2402 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, 2403 struct cmng_init_input *input) 2404 { 2405 u16 vn_max_rate; 2406 u32 vn_cfg = bp->mf_config[vn]; 2407 2408 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2409 vn_max_rate = 0; 2410 else { 2411 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2412 2413 if (IS_MF_SI(bp)) { 2414 /* maxCfg in percents of linkspeed */ 2415 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2416 } else /* SD modes */ 2417 /* maxCfg is absolute in 100Mb units */ 2418 vn_max_rate = maxCfg * 100; 2419 } 2420 2421 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 2422 2423 input->vnic_max_rate[vn] = vn_max_rate; 2424 } 2425 2426 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2427 { 2428 if (CHIP_REV_IS_SLOW(bp)) 2429 return CMNG_FNS_NONE; 2430 if (IS_MF(bp)) 2431 return CMNG_FNS_MINMAX; 2432 2433 return CMNG_FNS_NONE; 2434 } 2435 2436 void bnx2x_read_mf_cfg(struct bnx2x *bp) 2437 { 2438 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2439 2440 if (BP_NOMCP(bp)) 2441 return; /* what should be the default value in this case */ 2442 2443 /* For 2 port configuration the absolute function number formula 2444 * is: 2445 * abs_func = 2 * vn + BP_PORT + BP_PATH 2446 * 2447 * and there are 4 functions per port 2448 * 2449 * For 4 port configuration it is 2450 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2451 * 2452 * and there are 2 functions per port 2453 */ 2454 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2455 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2456 2457 if (func >= E1H_FUNC_MAX) 2458 break; 2459 2460 bp->mf_config[vn] = 2461 MF_CFG_RD(bp, func_mf_config[func].config); 2462 } 2463 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2464 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); 2465 bp->flags |= MF_FUNC_DIS; 2466 } else { 2467 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2468 bp->flags &= ~MF_FUNC_DIS; 2469 } 2470 } 2471 2472 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2473 { 2474 struct cmng_init_input input; 2475 memset(&input, 0, sizeof(struct cmng_init_input)); 2476 2477 input.port_rate = bp->link_vars.line_speed; 2478 2479 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { 2480 int vn; 2481 2482 /* read mf conf from shmem */ 2483 if (read_cfg) 2484 bnx2x_read_mf_cfg(bp); 2485 2486 /* vn_weight_sum and enable fairness if not 0 */ 2487 bnx2x_calc_vn_min(bp, &input); 2488 2489 /* calculate and set min-max rate for each vn */ 2490 if (bp->port.pmf) 2491 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2492 bnx2x_calc_vn_max(bp, vn, &input); 2493 2494 /* always enable rate shaping and fairness */ 2495 input.flags.cmng_enables |= 2496 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2497 2498 bnx2x_init_cmng(&input, &bp->cmng); 2499 return; 2500 } 2501 2502 /* rate shaping and fairness are disabled */ 2503 DP(NETIF_MSG_IFUP, 2504 "rate shaping and fairness are disabled\n"); 2505 } 2506 2507 static void storm_memset_cmng(struct bnx2x *bp, 2508 struct cmng_init *cmng, 2509 u8 port) 2510 { 2511 int vn; 2512 size_t size = sizeof(struct cmng_struct_per_port); 2513 2514 u32 addr = BAR_XSTRORM_INTMEM + 2515 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 2516 2517 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); 2518 2519 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2520 int func = func_by_vn(bp, vn); 2521 2522 addr = BAR_XSTRORM_INTMEM + 2523 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); 2524 size = sizeof(struct rate_shaping_vars_per_vn); 2525 __storm_memset_struct(bp, addr, size, 2526 (u32 *)&cmng->vnic.vnic_max_rate[vn]); 2527 2528 addr = BAR_XSTRORM_INTMEM + 2529 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); 2530 size = sizeof(struct fairness_vars_per_vn); 2531 __storm_memset_struct(bp, addr, size, 2532 (u32 *)&cmng->vnic.vnic_min_rate[vn]); 2533 } 2534 } 2535 2536 /* init cmng mode in HW according to local configuration */ 2537 void bnx2x_set_local_cmng(struct bnx2x *bp) 2538 { 2539 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2540 2541 if (cmng_fns != CMNG_FNS_NONE) { 2542 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2543 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2544 } else { 2545 /* rate shaping and fairness are disabled */ 2546 DP(NETIF_MSG_IFUP, 2547 "single function mode without fairness\n"); 2548 } 2549 } 2550 2551 /* This function is called upon link interrupt */ 2552 static void bnx2x_link_attn(struct bnx2x *bp) 2553 { 2554 /* Make sure that we are synced with the current statistics */ 2555 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2556 2557 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2558 2559 if (bp->link_vars.link_up) { 2560 2561 /* dropless flow control */ 2562 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2563 int port = BP_PORT(bp); 2564 u32 pause_enabled = 0; 2565 2566 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2567 pause_enabled = 1; 2568 2569 REG_WR(bp, BAR_USTRORM_INTMEM + 2570 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2571 pause_enabled); 2572 } 2573 2574 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2575 struct host_port_stats *pstats; 2576 2577 pstats = bnx2x_sp(bp, port_stats); 2578 /* reset old mac stats */ 2579 memset(&(pstats->mac_stx[0]), 0, 2580 sizeof(struct mac_stx)); 2581 } 2582 if (bp->state == BNX2X_STATE_OPEN) 2583 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2584 } 2585 2586 if (bp->link_vars.link_up && bp->link_vars.line_speed) 2587 bnx2x_set_local_cmng(bp); 2588 2589 __bnx2x_link_report(bp); 2590 2591 if (IS_MF(bp)) 2592 bnx2x_link_sync_notify(bp); 2593 } 2594 2595 void bnx2x__link_status_update(struct bnx2x *bp) 2596 { 2597 if (bp->state != BNX2X_STATE_OPEN) 2598 return; 2599 2600 /* read updated dcb configuration */ 2601 if (IS_PF(bp)) { 2602 bnx2x_dcbx_pmf_update(bp); 2603 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2604 if (bp->link_vars.link_up) 2605 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2606 else 2607 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2608 /* indicate link status */ 2609 bnx2x_link_report(bp); 2610 2611 } else { /* VF */ 2612 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | 2613 SUPPORTED_10baseT_Full | 2614 SUPPORTED_100baseT_Half | 2615 SUPPORTED_100baseT_Full | 2616 SUPPORTED_1000baseT_Full | 2617 SUPPORTED_2500baseX_Full | 2618 SUPPORTED_10000baseT_Full | 2619 SUPPORTED_TP | 2620 SUPPORTED_FIBRE | 2621 SUPPORTED_Autoneg | 2622 SUPPORTED_Pause | 2623 SUPPORTED_Asym_Pause); 2624 bp->port.advertising[0] = bp->port.supported[0]; 2625 2626 bp->link_params.bp = bp; 2627 bp->link_params.port = BP_PORT(bp); 2628 bp->link_params.req_duplex[0] = DUPLEX_FULL; 2629 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; 2630 bp->link_params.req_line_speed[0] = SPEED_10000; 2631 bp->link_params.speed_cap_mask[0] = 0x7f0000; 2632 bp->link_params.switch_cfg = SWITCH_CFG_10G; 2633 bp->link_vars.mac_type = MAC_TYPE_BMAC; 2634 bp->link_vars.line_speed = SPEED_10000; 2635 bp->link_vars.link_status = 2636 (LINK_STATUS_LINK_UP | 2637 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 2638 bp->link_vars.link_up = 1; 2639 bp->link_vars.duplex = DUPLEX_FULL; 2640 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; 2641 __bnx2x_link_report(bp); 2642 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2643 } 2644 } 2645 2646 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, 2647 u16 vlan_val, u8 allowed_prio) 2648 { 2649 struct bnx2x_func_state_params func_params = {NULL}; 2650 struct bnx2x_func_afex_update_params *f_update_params = 2651 &func_params.params.afex_update; 2652 2653 func_params.f_obj = &bp->func_obj; 2654 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; 2655 2656 /* no need to wait for RAMROD completion, so don't 2657 * set RAMROD_COMP_WAIT flag 2658 */ 2659 2660 f_update_params->vif_id = vifid; 2661 f_update_params->afex_default_vlan = vlan_val; 2662 f_update_params->allowed_priorities = allowed_prio; 2663 2664 /* if ramrod can not be sent, response to MCP immediately */ 2665 if (bnx2x_func_state_change(bp, &func_params) < 0) 2666 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 2667 2668 return 0; 2669 } 2670 2671 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, 2672 u16 vif_index, u8 func_bit_map) 2673 { 2674 struct bnx2x_func_state_params func_params = {NULL}; 2675 struct bnx2x_func_afex_viflists_params *update_params = 2676 &func_params.params.afex_viflists; 2677 int rc; 2678 u32 drv_msg_code; 2679 2680 /* validate only LIST_SET and LIST_GET are received from switch */ 2681 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) 2682 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", 2683 cmd_type); 2684 2685 func_params.f_obj = &bp->func_obj; 2686 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; 2687 2688 /* set parameters according to cmd_type */ 2689 update_params->afex_vif_list_command = cmd_type; 2690 update_params->vif_list_index = vif_index; 2691 update_params->func_bit_map = 2692 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; 2693 update_params->func_to_clear = 0; 2694 drv_msg_code = 2695 (cmd_type == VIF_LIST_RULE_GET) ? 2696 DRV_MSG_CODE_AFEX_LISTGET_ACK : 2697 DRV_MSG_CODE_AFEX_LISTSET_ACK; 2698 2699 /* if ramrod can not be sent, respond to MCP immediately for 2700 * SET and GET requests (other are not triggered from MCP) 2701 */ 2702 rc = bnx2x_func_state_change(bp, &func_params); 2703 if (rc < 0) 2704 bnx2x_fw_command(bp, drv_msg_code, 0); 2705 2706 return 0; 2707 } 2708 2709 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) 2710 { 2711 struct afex_stats afex_stats; 2712 u32 func = BP_ABS_FUNC(bp); 2713 u32 mf_config; 2714 u16 vlan_val; 2715 u32 vlan_prio; 2716 u16 vif_id; 2717 u8 allowed_prio; 2718 u8 vlan_mode; 2719 u32 addr_to_write, vifid, addrs, stats_type, i; 2720 2721 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { 2722 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2723 DP(BNX2X_MSG_MCP, 2724 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); 2725 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); 2726 } 2727 2728 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { 2729 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2730 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); 2731 DP(BNX2X_MSG_MCP, 2732 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", 2733 vifid, addrs); 2734 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, 2735 addrs); 2736 } 2737 2738 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { 2739 addr_to_write = SHMEM2_RD(bp, 2740 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); 2741 stats_type = SHMEM2_RD(bp, 2742 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2743 2744 DP(BNX2X_MSG_MCP, 2745 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", 2746 addr_to_write); 2747 2748 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); 2749 2750 /* write response to scratchpad, for MCP */ 2751 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) 2752 REG_WR(bp, addr_to_write + i*sizeof(u32), 2753 *(((u32 *)(&afex_stats))+i)); 2754 2755 /* send ack message to MCP */ 2756 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); 2757 } 2758 2759 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { 2760 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); 2761 bp->mf_config[BP_VN(bp)] = mf_config; 2762 DP(BNX2X_MSG_MCP, 2763 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", 2764 mf_config); 2765 2766 /* if VIF_SET is "enabled" */ 2767 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { 2768 /* set rate limit directly to internal RAM */ 2769 struct cmng_init_input cmng_input; 2770 struct rate_shaping_vars_per_vn m_rs_vn; 2771 size_t size = sizeof(struct rate_shaping_vars_per_vn); 2772 u32 addr = BAR_XSTRORM_INTMEM + 2773 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); 2774 2775 bp->mf_config[BP_VN(bp)] = mf_config; 2776 2777 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); 2778 m_rs_vn.vn_counter.rate = 2779 cmng_input.vnic_max_rate[BP_VN(bp)]; 2780 m_rs_vn.vn_counter.quota = 2781 (m_rs_vn.vn_counter.rate * 2782 RS_PERIODIC_TIMEOUT_USEC) / 8; 2783 2784 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); 2785 2786 /* read relevant values from mf_cfg struct in shmem */ 2787 vif_id = 2788 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2789 FUNC_MF_CFG_E1HOV_TAG_MASK) >> 2790 FUNC_MF_CFG_E1HOV_TAG_SHIFT; 2791 vlan_val = 2792 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2793 FUNC_MF_CFG_AFEX_VLAN_MASK) >> 2794 FUNC_MF_CFG_AFEX_VLAN_SHIFT; 2795 vlan_prio = (mf_config & 2796 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 2797 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; 2798 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); 2799 vlan_mode = 2800 (MF_CFG_RD(bp, 2801 func_mf_config[func].afex_config) & 2802 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 2803 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; 2804 allowed_prio = 2805 (MF_CFG_RD(bp, 2806 func_mf_config[func].afex_config) & 2807 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 2808 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; 2809 2810 /* send ramrod to FW, return in case of failure */ 2811 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, 2812 allowed_prio)) 2813 return; 2814 2815 bp->afex_def_vlan_tag = vlan_val; 2816 bp->afex_vlan_mode = vlan_mode; 2817 } else { 2818 /* notify link down because BP->flags is disabled */ 2819 bnx2x_link_report(bp); 2820 2821 /* send INVALID VIF ramrod to FW */ 2822 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); 2823 2824 /* Reset the default afex VLAN */ 2825 bp->afex_def_vlan_tag = -1; 2826 } 2827 } 2828 } 2829 2830 static void bnx2x_pmf_update(struct bnx2x *bp) 2831 { 2832 int port = BP_PORT(bp); 2833 u32 val; 2834 2835 bp->port.pmf = 1; 2836 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2837 2838 /* 2839 * We need the mb() to ensure the ordering between the writing to 2840 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2841 */ 2842 smp_mb(); 2843 2844 /* queue a periodic task */ 2845 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2846 2847 bnx2x_dcbx_pmf_update(bp); 2848 2849 /* enable nig attention */ 2850 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2851 if (bp->common.int_block == INT_BLOCK_HC) { 2852 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2853 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2854 } else if (!CHIP_IS_E1x(bp)) { 2855 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2856 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2857 } 2858 2859 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2860 } 2861 2862 /* end of Link */ 2863 2864 /* slow path */ 2865 2866 /* 2867 * General service functions 2868 */ 2869 2870 /* send the MCP a request, block until there is a reply */ 2871 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2872 { 2873 int mb_idx = BP_FW_MB_IDX(bp); 2874 u32 seq; 2875 u32 rc = 0; 2876 u32 cnt = 1; 2877 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2878 2879 mutex_lock(&bp->fw_mb_mutex); 2880 seq = ++bp->fw_seq; 2881 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2882 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2883 2884 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2885 (command | seq), param); 2886 2887 do { 2888 /* let the FW do it's magic ... */ 2889 msleep(delay); 2890 2891 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2892 2893 /* Give the FW up to 5 second (500*10ms) */ 2894 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2895 2896 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2897 cnt*delay, rc, seq); 2898 2899 /* is this a reply to our command? */ 2900 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2901 rc &= FW_MSG_CODE_MASK; 2902 else { 2903 /* FW BUG! */ 2904 BNX2X_ERR("FW failed to respond!\n"); 2905 bnx2x_fw_dump(bp); 2906 rc = 0; 2907 } 2908 mutex_unlock(&bp->fw_mb_mutex); 2909 2910 return rc; 2911 } 2912 2913 static void storm_memset_func_cfg(struct bnx2x *bp, 2914 struct tstorm_eth_function_common_config *tcfg, 2915 u16 abs_fid) 2916 { 2917 size_t size = sizeof(struct tstorm_eth_function_common_config); 2918 2919 u32 addr = BAR_TSTRORM_INTMEM + 2920 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 2921 2922 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 2923 } 2924 2925 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2926 { 2927 if (CHIP_IS_E1x(bp)) { 2928 struct tstorm_eth_function_common_config tcfg = {0}; 2929 2930 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2931 } 2932 2933 /* Enable the function in the FW */ 2934 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2935 storm_memset_func_en(bp, p->func_id, 1); 2936 2937 /* spq */ 2938 if (p->func_flgs & FUNC_FLG_SPQ) { 2939 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2940 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2941 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2942 } 2943 } 2944 2945 /** 2946 * bnx2x_get_common_flags - Return common flags 2947 * 2948 * @bp device handle 2949 * @fp queue handle 2950 * @zero_stats TRUE if statistics zeroing is needed 2951 * 2952 * Return the flags that are common for the Tx-only and not normal connections. 2953 */ 2954 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2955 struct bnx2x_fastpath *fp, 2956 bool zero_stats) 2957 { 2958 unsigned long flags = 0; 2959 2960 /* PF driver will always initialize the Queue to an ACTIVE state */ 2961 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2962 2963 /* tx only connections collect statistics (on the same index as the 2964 * parent connection). The statistics are zeroed when the parent 2965 * connection is initialized. 2966 */ 2967 2968 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2969 if (zero_stats) 2970 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2971 2972 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); 2973 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); 2974 2975 #ifdef BNX2X_STOP_ON_ERROR 2976 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); 2977 #endif 2978 2979 return flags; 2980 } 2981 2982 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2983 struct bnx2x_fastpath *fp, 2984 bool leading) 2985 { 2986 unsigned long flags = 0; 2987 2988 /* calculate other queue flags */ 2989 if (IS_MF_SD(bp)) 2990 __set_bit(BNX2X_Q_FLG_OV, &flags); 2991 2992 if (IS_FCOE_FP(fp)) { 2993 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2994 /* For FCoE - force usage of default priority (for afex) */ 2995 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); 2996 } 2997 2998 if (!fp->disable_tpa) { 2999 __set_bit(BNX2X_Q_FLG_TPA, &flags); 3000 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 3001 if (fp->mode == TPA_MODE_GRO) 3002 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 3003 } 3004 3005 if (leading) { 3006 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 3007 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 3008 } 3009 3010 /* Always set HW VLAN stripping */ 3011 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 3012 3013 /* configure silent vlan removal */ 3014 if (IS_MF_AFEX(bp)) 3015 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); 3016 3017 return flags | bnx2x_get_common_flags(bp, fp, true); 3018 } 3019 3020 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 3021 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 3022 u8 cos) 3023 { 3024 gen_init->stat_id = bnx2x_stats_id(fp); 3025 gen_init->spcl_id = fp->cl_id; 3026 3027 /* Always use mini-jumbo MTU for FCoE L2 ring */ 3028 if (IS_FCOE_FP(fp)) 3029 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 3030 else 3031 gen_init->mtu = bp->dev->mtu; 3032 3033 gen_init->cos = cos; 3034 } 3035 3036 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 3037 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 3038 struct bnx2x_rxq_setup_params *rxq_init) 3039 { 3040 u8 max_sge = 0; 3041 u16 sge_sz = 0; 3042 u16 tpa_agg_size = 0; 3043 3044 if (!fp->disable_tpa) { 3045 pause->sge_th_lo = SGE_TH_LO(bp); 3046 pause->sge_th_hi = SGE_TH_HI(bp); 3047 3048 /* validate SGE ring has enough to cross high threshold */ 3049 WARN_ON(bp->dropless_fc && 3050 pause->sge_th_hi + FW_PREFETCH_CNT > 3051 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 3052 3053 tpa_agg_size = TPA_AGG_SIZE; 3054 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 3055 SGE_PAGE_SHIFT; 3056 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 3057 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 3058 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); 3059 } 3060 3061 /* pause - not for e1 */ 3062 if (!CHIP_IS_E1(bp)) { 3063 pause->bd_th_lo = BD_TH_LO(bp); 3064 pause->bd_th_hi = BD_TH_HI(bp); 3065 3066 pause->rcq_th_lo = RCQ_TH_LO(bp); 3067 pause->rcq_th_hi = RCQ_TH_HI(bp); 3068 /* 3069 * validate that rings have enough entries to cross 3070 * high thresholds 3071 */ 3072 WARN_ON(bp->dropless_fc && 3073 pause->bd_th_hi + FW_PREFETCH_CNT > 3074 bp->rx_ring_size); 3075 WARN_ON(bp->dropless_fc && 3076 pause->rcq_th_hi + FW_PREFETCH_CNT > 3077 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 3078 3079 pause->pri_map = 1; 3080 } 3081 3082 /* rxq setup */ 3083 rxq_init->dscr_map = fp->rx_desc_mapping; 3084 rxq_init->sge_map = fp->rx_sge_mapping; 3085 rxq_init->rcq_map = fp->rx_comp_mapping; 3086 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 3087 3088 /* This should be a maximum number of data bytes that may be 3089 * placed on the BD (not including paddings). 3090 */ 3091 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 3092 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 3093 3094 rxq_init->cl_qzone_id = fp->cl_qzone_id; 3095 rxq_init->tpa_agg_sz = tpa_agg_size; 3096 rxq_init->sge_buf_sz = sge_sz; 3097 rxq_init->max_sges_pkt = max_sge; 3098 rxq_init->rss_engine_id = BP_FUNC(bp); 3099 rxq_init->mcast_engine_id = BP_FUNC(bp); 3100 3101 /* Maximum number or simultaneous TPA aggregation for this Queue. 3102 * 3103 * For PF Clients it should be the maximum available number. 3104 * VF driver(s) may want to define it to a smaller value. 3105 */ 3106 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 3107 3108 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 3109 rxq_init->fw_sb_id = fp->fw_sb_id; 3110 3111 if (IS_FCOE_FP(fp)) 3112 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 3113 else 3114 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 3115 /* configure silent vlan removal 3116 * if multi function mode is afex, then mask default vlan 3117 */ 3118 if (IS_MF_AFEX(bp)) { 3119 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; 3120 rxq_init->silent_removal_mask = VLAN_VID_MASK; 3121 } 3122 } 3123 3124 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 3125 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 3126 u8 cos) 3127 { 3128 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; 3129 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 3130 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 3131 txq_init->fw_sb_id = fp->fw_sb_id; 3132 3133 /* 3134 * set the tss leading client id for TX classification == 3135 * leading RSS client id 3136 */ 3137 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 3138 3139 if (IS_FCOE_FP(fp)) { 3140 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 3141 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 3142 } 3143 } 3144 3145 static void bnx2x_pf_init(struct bnx2x *bp) 3146 { 3147 struct bnx2x_func_init_params func_init = {0}; 3148 struct event_ring_data eq_data = { {0} }; 3149 u16 flags; 3150 3151 if (!CHIP_IS_E1x(bp)) { 3152 /* reset IGU PF statistics: MSIX + ATTN */ 3153 /* PF */ 3154 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3155 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3156 (CHIP_MODE_IS_4_PORT(bp) ? 3157 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3158 /* ATTN */ 3159 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3160 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3161 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 3162 (CHIP_MODE_IS_4_PORT(bp) ? 3163 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3164 } 3165 3166 /* function setup flags */ 3167 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 3168 3169 /* This flag is relevant for E1x only. 3170 * E2 doesn't have a TPA configuration in a function level. 3171 */ 3172 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 3173 3174 func_init.func_flgs = flags; 3175 func_init.pf_id = BP_FUNC(bp); 3176 func_init.func_id = BP_FUNC(bp); 3177 func_init.spq_map = bp->spq_mapping; 3178 func_init.spq_prod = bp->spq_prod_idx; 3179 3180 bnx2x_func_init(bp, &func_init); 3181 3182 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 3183 3184 /* 3185 * Congestion management values depend on the link rate 3186 * There is no active link so initial link rate is set to 10 Gbps. 3187 * When the link comes up The congestion management values are 3188 * re-calculated according to the actual link rate. 3189 */ 3190 bp->link_vars.line_speed = SPEED_10000; 3191 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 3192 3193 /* Only the PMF sets the HW */ 3194 if (bp->port.pmf) 3195 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3196 3197 /* init Event Queue - PCI bus guarantees correct endianity*/ 3198 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 3199 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 3200 eq_data.producer = bp->eq_prod; 3201 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 3202 eq_data.sb_id = DEF_SB_ID; 3203 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 3204 } 3205 3206 static void bnx2x_e1h_disable(struct bnx2x *bp) 3207 { 3208 int port = BP_PORT(bp); 3209 3210 bnx2x_tx_disable(bp); 3211 3212 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 3213 } 3214 3215 static void bnx2x_e1h_enable(struct bnx2x *bp) 3216 { 3217 int port = BP_PORT(bp); 3218 3219 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 3220 3221 /* Tx queue should be only re-enabled */ 3222 netif_tx_wake_all_queues(bp->dev); 3223 3224 /* 3225 * Should not call netif_carrier_on since it will be called if the link 3226 * is up when checking for link state 3227 */ 3228 } 3229 3230 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 3231 3232 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 3233 { 3234 struct eth_stats_info *ether_stat = 3235 &bp->slowpath->drv_info_to_mcp.ether_stat; 3236 struct bnx2x_vlan_mac_obj *mac_obj = 3237 &bp->sp_objs->mac_obj; 3238 int i; 3239 3240 strlcpy(ether_stat->version, DRV_MODULE_VERSION, 3241 ETH_STAT_INFO_VERSION_LEN); 3242 3243 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the 3244 * mac_local field in ether_stat struct. The base address is offset by 2 3245 * bytes to account for the field being 8 bytes but a mac address is 3246 * only 6 bytes. Likewise, the stride for the get_n_elements function is 3247 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes 3248 * allocated by the ether_stat struct, so the macs will land in their 3249 * proper positions. 3250 */ 3251 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) 3252 memset(ether_stat->mac_local + i, 0, 3253 sizeof(ether_stat->mac_local[0])); 3254 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, 3255 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 3256 ether_stat->mac_local + MAC_PAD, MAC_PAD, 3257 ETH_ALEN); 3258 ether_stat->mtu_size = bp->dev->mtu; 3259 if (bp->dev->features & NETIF_F_RXCSUM) 3260 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 3261 if (bp->dev->features & NETIF_F_TSO) 3262 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 3263 ether_stat->feature_flags |= bp->common.boot_mode; 3264 3265 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 3266 3267 ether_stat->txq_size = bp->tx_ring_size; 3268 ether_stat->rxq_size = bp->rx_ring_size; 3269 } 3270 3271 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 3272 { 3273 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3274 struct fcoe_stats_info *fcoe_stat = 3275 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 3276 3277 if (!CNIC_LOADED(bp)) 3278 return; 3279 3280 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); 3281 3282 fcoe_stat->qos_priority = 3283 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 3284 3285 /* insert FCoE stats from ramrod response */ 3286 if (!NO_FCOE(bp)) { 3287 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 3288 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3289 tstorm_queue_statistics; 3290 3291 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 3292 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3293 xstorm_queue_statistics; 3294 3295 struct fcoe_statistics_params *fw_fcoe_stat = 3296 &bp->fw_stats_data->fcoe; 3297 3298 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, 3299 fcoe_stat->rx_bytes_lo, 3300 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 3301 3302 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3303 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 3304 fcoe_stat->rx_bytes_lo, 3305 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 3306 3307 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3308 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 3309 fcoe_stat->rx_bytes_lo, 3310 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 3311 3312 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3313 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 3314 fcoe_stat->rx_bytes_lo, 3315 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 3316 3317 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3318 fcoe_stat->rx_frames_lo, 3319 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3320 3321 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3322 fcoe_stat->rx_frames_lo, 3323 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3324 3325 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3326 fcoe_stat->rx_frames_lo, 3327 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3328 3329 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3330 fcoe_stat->rx_frames_lo, 3331 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3332 3333 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, 3334 fcoe_stat->tx_bytes_lo, 3335 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3336 3337 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3338 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3339 fcoe_stat->tx_bytes_lo, 3340 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3341 3342 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3343 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3344 fcoe_stat->tx_bytes_lo, 3345 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3346 3347 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3348 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3349 fcoe_stat->tx_bytes_lo, 3350 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3351 3352 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3353 fcoe_stat->tx_frames_lo, 3354 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3355 3356 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3357 fcoe_stat->tx_frames_lo, 3358 fcoe_q_xstorm_stats->ucast_pkts_sent); 3359 3360 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3361 fcoe_stat->tx_frames_lo, 3362 fcoe_q_xstorm_stats->bcast_pkts_sent); 3363 3364 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3365 fcoe_stat->tx_frames_lo, 3366 fcoe_q_xstorm_stats->mcast_pkts_sent); 3367 } 3368 3369 /* ask L5 driver to add data to the struct */ 3370 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3371 } 3372 3373 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3374 { 3375 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3376 struct iscsi_stats_info *iscsi_stat = 3377 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3378 3379 if (!CNIC_LOADED(bp)) 3380 return; 3381 3382 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, 3383 ETH_ALEN); 3384 3385 iscsi_stat->qos_priority = 3386 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3387 3388 /* ask L5 driver to add data to the struct */ 3389 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3390 } 3391 3392 /* called due to MCP event (on pmf): 3393 * reread new bandwidth configuration 3394 * configure FW 3395 * notify others function about the change 3396 */ 3397 static void bnx2x_config_mf_bw(struct bnx2x *bp) 3398 { 3399 if (bp->link_vars.link_up) { 3400 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3401 bnx2x_link_sync_notify(bp); 3402 } 3403 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3404 } 3405 3406 static void bnx2x_set_mf_bw(struct bnx2x *bp) 3407 { 3408 bnx2x_config_mf_bw(bp); 3409 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3410 } 3411 3412 static void bnx2x_handle_eee_event(struct bnx2x *bp) 3413 { 3414 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); 3415 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 3416 } 3417 3418 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3419 { 3420 enum drv_info_opcode op_code; 3421 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3422 3423 /* if drv_info version supported by MFW doesn't match - send NACK */ 3424 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3425 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3426 return; 3427 } 3428 3429 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3430 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3431 3432 memset(&bp->slowpath->drv_info_to_mcp, 0, 3433 sizeof(union drv_info_to_mcp)); 3434 3435 switch (op_code) { 3436 case ETH_STATS_OPCODE: 3437 bnx2x_drv_info_ether_stat(bp); 3438 break; 3439 case FCOE_STATS_OPCODE: 3440 bnx2x_drv_info_fcoe_stat(bp); 3441 break; 3442 case ISCSI_STATS_OPCODE: 3443 bnx2x_drv_info_iscsi_stat(bp); 3444 break; 3445 default: 3446 /* if op code isn't supported - send NACK */ 3447 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3448 return; 3449 } 3450 3451 /* if we got drv_info attn from MFW then these fields are defined in 3452 * shmem2 for sure 3453 */ 3454 SHMEM2_WR(bp, drv_info_host_addr_lo, 3455 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3456 SHMEM2_WR(bp, drv_info_host_addr_hi, 3457 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3458 3459 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3460 } 3461 3462 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3463 { 3464 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3465 3466 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3467 3468 /* 3469 * This is the only place besides the function initialization 3470 * where the bp->flags can change so it is done without any 3471 * locks 3472 */ 3473 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3474 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3475 bp->flags |= MF_FUNC_DIS; 3476 3477 bnx2x_e1h_disable(bp); 3478 } else { 3479 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3480 bp->flags &= ~MF_FUNC_DIS; 3481 3482 bnx2x_e1h_enable(bp); 3483 } 3484 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3485 } 3486 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3487 bnx2x_config_mf_bw(bp); 3488 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3489 } 3490 3491 /* Report results to MCP */ 3492 if (dcc_event) 3493 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3494 else 3495 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3496 } 3497 3498 /* must be called under the spq lock */ 3499 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3500 { 3501 struct eth_spe *next_spe = bp->spq_prod_bd; 3502 3503 if (bp->spq_prod_bd == bp->spq_last_bd) { 3504 bp->spq_prod_bd = bp->spq; 3505 bp->spq_prod_idx = 0; 3506 DP(BNX2X_MSG_SP, "end of spq\n"); 3507 } else { 3508 bp->spq_prod_bd++; 3509 bp->spq_prod_idx++; 3510 } 3511 return next_spe; 3512 } 3513 3514 /* must be called under the spq lock */ 3515 static void bnx2x_sp_prod_update(struct bnx2x *bp) 3516 { 3517 int func = BP_FUNC(bp); 3518 3519 /* 3520 * Make sure that BD data is updated before writing the producer: 3521 * BD data is written to the memory, the producer is read from the 3522 * memory, thus we need a full memory barrier to ensure the ordering. 3523 */ 3524 mb(); 3525 3526 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3527 bp->spq_prod_idx); 3528 mmiowb(); 3529 } 3530 3531 /** 3532 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3533 * 3534 * @cmd: command to check 3535 * @cmd_type: command type 3536 */ 3537 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3538 { 3539 if ((cmd_type == NONE_CONNECTION_TYPE) || 3540 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3541 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3542 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3543 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3544 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3545 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3546 return true; 3547 else 3548 return false; 3549 } 3550 3551 /** 3552 * bnx2x_sp_post - place a single command on an SP ring 3553 * 3554 * @bp: driver handle 3555 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3556 * @cid: SW CID the command is related to 3557 * @data_hi: command private data address (high 32 bits) 3558 * @data_lo: command private data address (low 32 bits) 3559 * @cmd_type: command type (e.g. NONE, ETH) 3560 * 3561 * SP data is handled as if it's always an address pair, thus data fields are 3562 * not swapped to little endian in upper functions. Instead this function swaps 3563 * data as if it's two u32 fields. 3564 */ 3565 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3566 u32 data_hi, u32 data_lo, int cmd_type) 3567 { 3568 struct eth_spe *spe; 3569 u16 type; 3570 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3571 3572 #ifdef BNX2X_STOP_ON_ERROR 3573 if (unlikely(bp->panic)) { 3574 BNX2X_ERR("Can't post SP when there is panic\n"); 3575 return -EIO; 3576 } 3577 #endif 3578 3579 spin_lock_bh(&bp->spq_lock); 3580 3581 if (common) { 3582 if (!atomic_read(&bp->eq_spq_left)) { 3583 BNX2X_ERR("BUG! EQ ring full!\n"); 3584 spin_unlock_bh(&bp->spq_lock); 3585 bnx2x_panic(); 3586 return -EBUSY; 3587 } 3588 } else if (!atomic_read(&bp->cq_spq_left)) { 3589 BNX2X_ERR("BUG! SPQ ring full!\n"); 3590 spin_unlock_bh(&bp->spq_lock); 3591 bnx2x_panic(); 3592 return -EBUSY; 3593 } 3594 3595 spe = bnx2x_sp_get_next(bp); 3596 3597 /* CID needs port number to be encoded int it */ 3598 spe->hdr.conn_and_cmd_data = 3599 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3600 HW_CID(bp, cid)); 3601 3602 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3603 3604 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3605 SPE_HDR_FUNCTION_ID); 3606 3607 spe->hdr.type = cpu_to_le16(type); 3608 3609 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3610 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3611 3612 /* 3613 * It's ok if the actual decrement is issued towards the memory 3614 * somewhere between the spin_lock and spin_unlock. Thus no 3615 * more explicit memory barrier is needed. 3616 */ 3617 if (common) 3618 atomic_dec(&bp->eq_spq_left); 3619 else 3620 atomic_dec(&bp->cq_spq_left); 3621 3622 DP(BNX2X_MSG_SP, 3623 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3624 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3625 (u32)(U64_LO(bp->spq_mapping) + 3626 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3627 HW_CID(bp, cid), data_hi, data_lo, type, 3628 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3629 3630 bnx2x_sp_prod_update(bp); 3631 spin_unlock_bh(&bp->spq_lock); 3632 return 0; 3633 } 3634 3635 /* acquire split MCP access lock register */ 3636 static int bnx2x_acquire_alr(struct bnx2x *bp) 3637 { 3638 u32 j, val; 3639 int rc = 0; 3640 3641 might_sleep(); 3642 for (j = 0; j < 1000; j++) { 3643 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); 3644 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); 3645 if (val & MCPR_ACCESS_LOCK_LOCK) 3646 break; 3647 3648 usleep_range(5000, 10000); 3649 } 3650 if (!(val & MCPR_ACCESS_LOCK_LOCK)) { 3651 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3652 rc = -EBUSY; 3653 } 3654 3655 return rc; 3656 } 3657 3658 /* release split MCP access lock register */ 3659 static void bnx2x_release_alr(struct bnx2x *bp) 3660 { 3661 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); 3662 } 3663 3664 #define BNX2X_DEF_SB_ATT_IDX 0x0001 3665 #define BNX2X_DEF_SB_IDX 0x0002 3666 3667 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3668 { 3669 struct host_sp_status_block *def_sb = bp->def_status_blk; 3670 u16 rc = 0; 3671 3672 barrier(); /* status block is written to by the chip */ 3673 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3674 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3675 rc |= BNX2X_DEF_SB_ATT_IDX; 3676 } 3677 3678 if (bp->def_idx != def_sb->sp_sb.running_index) { 3679 bp->def_idx = def_sb->sp_sb.running_index; 3680 rc |= BNX2X_DEF_SB_IDX; 3681 } 3682 3683 /* Do not reorder: indices reading should complete before handling */ 3684 barrier(); 3685 return rc; 3686 } 3687 3688 /* 3689 * slow path service functions 3690 */ 3691 3692 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3693 { 3694 int port = BP_PORT(bp); 3695 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3696 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3697 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3698 NIG_REG_MASK_INTERRUPT_PORT0; 3699 u32 aeu_mask; 3700 u32 nig_mask = 0; 3701 u32 reg_addr; 3702 3703 if (bp->attn_state & asserted) 3704 BNX2X_ERR("IGU ERROR\n"); 3705 3706 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3707 aeu_mask = REG_RD(bp, aeu_addr); 3708 3709 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3710 aeu_mask, asserted); 3711 aeu_mask &= ~(asserted & 0x3ff); 3712 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3713 3714 REG_WR(bp, aeu_addr, aeu_mask); 3715 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3716 3717 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3718 bp->attn_state |= asserted; 3719 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3720 3721 if (asserted & ATTN_HARD_WIRED_MASK) { 3722 if (asserted & ATTN_NIG_FOR_FUNC) { 3723 3724 bnx2x_acquire_phy_lock(bp); 3725 3726 /* save nig interrupt mask */ 3727 nig_mask = REG_RD(bp, nig_int_mask_addr); 3728 3729 /* If nig_mask is not set, no need to call the update 3730 * function. 3731 */ 3732 if (nig_mask) { 3733 REG_WR(bp, nig_int_mask_addr, 0); 3734 3735 bnx2x_link_attn(bp); 3736 } 3737 3738 /* handle unicore attn? */ 3739 } 3740 if (asserted & ATTN_SW_TIMER_4_FUNC) 3741 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3742 3743 if (asserted & GPIO_2_FUNC) 3744 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3745 3746 if (asserted & GPIO_3_FUNC) 3747 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3748 3749 if (asserted & GPIO_4_FUNC) 3750 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3751 3752 if (port == 0) { 3753 if (asserted & ATTN_GENERAL_ATTN_1) { 3754 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3755 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3756 } 3757 if (asserted & ATTN_GENERAL_ATTN_2) { 3758 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3759 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3760 } 3761 if (asserted & ATTN_GENERAL_ATTN_3) { 3762 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3763 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3764 } 3765 } else { 3766 if (asserted & ATTN_GENERAL_ATTN_4) { 3767 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3768 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3769 } 3770 if (asserted & ATTN_GENERAL_ATTN_5) { 3771 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3772 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3773 } 3774 if (asserted & ATTN_GENERAL_ATTN_6) { 3775 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3776 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3777 } 3778 } 3779 3780 } /* if hardwired */ 3781 3782 if (bp->common.int_block == INT_BLOCK_HC) 3783 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3784 COMMAND_REG_ATTN_BITS_SET); 3785 else 3786 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3787 3788 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3789 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3790 REG_WR(bp, reg_addr, asserted); 3791 3792 /* now set back the mask */ 3793 if (asserted & ATTN_NIG_FOR_FUNC) { 3794 /* Verify that IGU ack through BAR was written before restoring 3795 * NIG mask. This loop should exit after 2-3 iterations max. 3796 */ 3797 if (bp->common.int_block != INT_BLOCK_HC) { 3798 u32 cnt = 0, igu_acked; 3799 do { 3800 igu_acked = REG_RD(bp, 3801 IGU_REG_ATTENTION_ACK_BITS); 3802 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 3803 (++cnt < MAX_IGU_ATTN_ACK_TO)); 3804 if (!igu_acked) 3805 DP(NETIF_MSG_HW, 3806 "Failed to verify IGU ack on time\n"); 3807 barrier(); 3808 } 3809 REG_WR(bp, nig_int_mask_addr, nig_mask); 3810 bnx2x_release_phy_lock(bp); 3811 } 3812 } 3813 3814 static void bnx2x_fan_failure(struct bnx2x *bp) 3815 { 3816 int port = BP_PORT(bp); 3817 u32 ext_phy_config; 3818 /* mark the failure */ 3819 ext_phy_config = 3820 SHMEM_RD(bp, 3821 dev_info.port_hw_config[port].external_phy_config); 3822 3823 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3824 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3825 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3826 ext_phy_config); 3827 3828 /* log the failure */ 3829 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 3830 "Please contact OEM Support for assistance\n"); 3831 3832 /* Schedule device reset (unload) 3833 * This is due to some boards consuming sufficient power when driver is 3834 * up to overheat if fan fails. 3835 */ 3836 smp_mb__before_clear_bit(); 3837 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3838 smp_mb__after_clear_bit(); 3839 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3840 } 3841 3842 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3843 { 3844 int port = BP_PORT(bp); 3845 int reg_offset; 3846 u32 val; 3847 3848 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3849 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3850 3851 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3852 3853 val = REG_RD(bp, reg_offset); 3854 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3855 REG_WR(bp, reg_offset, val); 3856 3857 BNX2X_ERR("SPIO5 hw attention\n"); 3858 3859 /* Fan failure attention */ 3860 bnx2x_hw_reset_phy(&bp->link_params); 3861 bnx2x_fan_failure(bp); 3862 } 3863 3864 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3865 bnx2x_acquire_phy_lock(bp); 3866 bnx2x_handle_module_detect_int(&bp->link_params); 3867 bnx2x_release_phy_lock(bp); 3868 } 3869 3870 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3871 3872 val = REG_RD(bp, reg_offset); 3873 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3874 REG_WR(bp, reg_offset, val); 3875 3876 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3877 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3878 bnx2x_panic(); 3879 } 3880 } 3881 3882 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3883 { 3884 u32 val; 3885 3886 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3887 3888 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3889 BNX2X_ERR("DB hw attention 0x%x\n", val); 3890 /* DORQ discard attention */ 3891 if (val & 0x2) 3892 BNX2X_ERR("FATAL error from DORQ\n"); 3893 } 3894 3895 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3896 3897 int port = BP_PORT(bp); 3898 int reg_offset; 3899 3900 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3901 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3902 3903 val = REG_RD(bp, reg_offset); 3904 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3905 REG_WR(bp, reg_offset, val); 3906 3907 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3908 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3909 bnx2x_panic(); 3910 } 3911 } 3912 3913 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3914 { 3915 u32 val; 3916 3917 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3918 3919 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3920 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3921 /* CFC error attention */ 3922 if (val & 0x2) 3923 BNX2X_ERR("FATAL error from CFC\n"); 3924 } 3925 3926 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3927 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3928 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3929 /* RQ_USDMDP_FIFO_OVERFLOW */ 3930 if (val & 0x18000) 3931 BNX2X_ERR("FATAL error from PXP\n"); 3932 3933 if (!CHIP_IS_E1x(bp)) { 3934 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3935 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3936 } 3937 } 3938 3939 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3940 3941 int port = BP_PORT(bp); 3942 int reg_offset; 3943 3944 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3945 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3946 3947 val = REG_RD(bp, reg_offset); 3948 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3949 REG_WR(bp, reg_offset, val); 3950 3951 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3952 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3953 bnx2x_panic(); 3954 } 3955 } 3956 3957 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3958 { 3959 u32 val; 3960 3961 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3962 3963 if (attn & BNX2X_PMF_LINK_ASSERT) { 3964 int func = BP_FUNC(bp); 3965 3966 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3967 bnx2x_read_mf_cfg(bp); 3968 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3969 func_mf_config[BP_ABS_FUNC(bp)].config); 3970 val = SHMEM_RD(bp, 3971 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3972 if (val & DRV_STATUS_DCC_EVENT_MASK) 3973 bnx2x_dcc_event(bp, 3974 (val & DRV_STATUS_DCC_EVENT_MASK)); 3975 3976 if (val & DRV_STATUS_SET_MF_BW) 3977 bnx2x_set_mf_bw(bp); 3978 3979 if (val & DRV_STATUS_DRV_INFO_REQ) 3980 bnx2x_handle_drv_info_req(bp); 3981 3982 if (val & DRV_STATUS_VF_DISABLED) 3983 bnx2x_vf_handle_flr_event(bp); 3984 3985 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3986 bnx2x_pmf_update(bp); 3987 3988 if (bp->port.pmf && 3989 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3990 bp->dcbx_enabled > 0) 3991 /* start dcbx state machine */ 3992 bnx2x_dcbx_set_params(bp, 3993 BNX2X_DCBX_STATE_NEG_RECEIVED); 3994 if (val & DRV_STATUS_AFEX_EVENT_MASK) 3995 bnx2x_handle_afex_cmd(bp, 3996 val & DRV_STATUS_AFEX_EVENT_MASK); 3997 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 3998 bnx2x_handle_eee_event(bp); 3999 if (bp->link_vars.periodic_flags & 4000 PERIODIC_FLAGS_LINK_EVENT) { 4001 /* sync with link */ 4002 bnx2x_acquire_phy_lock(bp); 4003 bp->link_vars.periodic_flags &= 4004 ~PERIODIC_FLAGS_LINK_EVENT; 4005 bnx2x_release_phy_lock(bp); 4006 if (IS_MF(bp)) 4007 bnx2x_link_sync_notify(bp); 4008 bnx2x_link_report(bp); 4009 } 4010 /* Always call it here: bnx2x_link_report() will 4011 * prevent the link indication duplication. 4012 */ 4013 bnx2x__link_status_update(bp); 4014 } else if (attn & BNX2X_MC_ASSERT_BITS) { 4015 4016 BNX2X_ERR("MC assert!\n"); 4017 bnx2x_mc_assert(bp); 4018 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 4019 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 4020 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 4021 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 4022 bnx2x_panic(); 4023 4024 } else if (attn & BNX2X_MCP_ASSERT) { 4025 4026 BNX2X_ERR("MCP assert!\n"); 4027 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 4028 bnx2x_fw_dump(bp); 4029 4030 } else 4031 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 4032 } 4033 4034 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 4035 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 4036 if (attn & BNX2X_GRC_TIMEOUT) { 4037 val = CHIP_IS_E1(bp) ? 0 : 4038 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 4039 BNX2X_ERR("GRC time-out 0x%08x\n", val); 4040 } 4041 if (attn & BNX2X_GRC_RSV) { 4042 val = CHIP_IS_E1(bp) ? 0 : 4043 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 4044 BNX2X_ERR("GRC reserved 0x%08x\n", val); 4045 } 4046 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 4047 } 4048 } 4049 4050 /* 4051 * Bits map: 4052 * 0-7 - Engine0 load counter. 4053 * 8-15 - Engine1 load counter. 4054 * 16 - Engine0 RESET_IN_PROGRESS bit. 4055 * 17 - Engine1 RESET_IN_PROGRESS bit. 4056 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 4057 * on the engine 4058 * 19 - Engine1 ONE_IS_LOADED. 4059 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 4060 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 4061 * just the one belonging to its engine). 4062 * 4063 */ 4064 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 4065 4066 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 4067 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 4068 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 4069 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 4070 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 4071 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 4072 #define BNX2X_GLOBAL_RESET_BIT 0x00040000 4073 4074 /* 4075 * Set the GLOBAL_RESET bit. 4076 * 4077 * Should be run under rtnl lock 4078 */ 4079 void bnx2x_set_reset_global(struct bnx2x *bp) 4080 { 4081 u32 val; 4082 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4083 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4084 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 4085 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4086 } 4087 4088 /* 4089 * Clear the GLOBAL_RESET bit. 4090 * 4091 * Should be run under rtnl lock 4092 */ 4093 static void bnx2x_clear_reset_global(struct bnx2x *bp) 4094 { 4095 u32 val; 4096 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4097 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4098 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 4099 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4100 } 4101 4102 /* 4103 * Checks the GLOBAL_RESET bit. 4104 * 4105 * should be run under rtnl lock 4106 */ 4107 static bool bnx2x_reset_is_global(struct bnx2x *bp) 4108 { 4109 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4110 4111 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 4112 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 4113 } 4114 4115 /* 4116 * Clear RESET_IN_PROGRESS bit for the current engine. 4117 * 4118 * Should be run under rtnl lock 4119 */ 4120 static void bnx2x_set_reset_done(struct bnx2x *bp) 4121 { 4122 u32 val; 4123 u32 bit = BP_PATH(bp) ? 4124 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4125 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4126 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4127 4128 /* Clear the bit */ 4129 val &= ~bit; 4130 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4131 4132 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4133 } 4134 4135 /* 4136 * Set RESET_IN_PROGRESS for the current engine. 4137 * 4138 * should be run under rtnl lock 4139 */ 4140 void bnx2x_set_reset_in_progress(struct bnx2x *bp) 4141 { 4142 u32 val; 4143 u32 bit = BP_PATH(bp) ? 4144 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4145 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4146 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4147 4148 /* Set the bit */ 4149 val |= bit; 4150 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4151 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4152 } 4153 4154 /* 4155 * Checks the RESET_IN_PROGRESS bit for the given engine. 4156 * should be run under rtnl lock 4157 */ 4158 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 4159 { 4160 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4161 u32 bit = engine ? 4162 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4163 4164 /* return false if bit is set */ 4165 return (val & bit) ? false : true; 4166 } 4167 4168 /* 4169 * set pf load for the current pf. 4170 * 4171 * should be run under rtnl lock 4172 */ 4173 void bnx2x_set_pf_load(struct bnx2x *bp) 4174 { 4175 u32 val1, val; 4176 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4177 BNX2X_PATH0_LOAD_CNT_MASK; 4178 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4179 BNX2X_PATH0_LOAD_CNT_SHIFT; 4180 4181 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4182 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4183 4184 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 4185 4186 /* get the current counter value */ 4187 val1 = (val & mask) >> shift; 4188 4189 /* set bit of that PF */ 4190 val1 |= (1 << bp->pf_num); 4191 4192 /* clear the old value */ 4193 val &= ~mask; 4194 4195 /* set the new one */ 4196 val |= ((val1 << shift) & mask); 4197 4198 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4199 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4200 } 4201 4202 /** 4203 * bnx2x_clear_pf_load - clear pf load mark 4204 * 4205 * @bp: driver handle 4206 * 4207 * Should be run under rtnl lock. 4208 * Decrements the load counter for the current engine. Returns 4209 * whether other functions are still loaded 4210 */ 4211 bool bnx2x_clear_pf_load(struct bnx2x *bp) 4212 { 4213 u32 val1, val; 4214 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4215 BNX2X_PATH0_LOAD_CNT_MASK; 4216 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4217 BNX2X_PATH0_LOAD_CNT_SHIFT; 4218 4219 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4220 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4221 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 4222 4223 /* get the current counter value */ 4224 val1 = (val & mask) >> shift; 4225 4226 /* clear bit of that PF */ 4227 val1 &= ~(1 << bp->pf_num); 4228 4229 /* clear the old value */ 4230 val &= ~mask; 4231 4232 /* set the new one */ 4233 val |= ((val1 << shift) & mask); 4234 4235 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4237 return val1 != 0; 4238 } 4239 4240 /* 4241 * Read the load status for the current engine. 4242 * 4243 * should be run under rtnl lock 4244 */ 4245 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 4246 { 4247 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 4248 BNX2X_PATH0_LOAD_CNT_MASK); 4249 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4250 BNX2X_PATH0_LOAD_CNT_SHIFT); 4251 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4252 4253 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 4254 4255 val = (val & mask) >> shift; 4256 4257 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 4258 engine, val); 4259 4260 return val != 0; 4261 } 4262 4263 static void _print_parity(struct bnx2x *bp, u32 reg) 4264 { 4265 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); 4266 } 4267 4268 static void _print_next_block(int idx, const char *blk) 4269 { 4270 pr_cont("%s%s", idx ? ", " : "", blk); 4271 } 4272 4273 static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, 4274 int par_num, bool print) 4275 { 4276 int i = 0; 4277 u32 cur_bit = 0; 4278 for (i = 0; sig; i++) { 4279 cur_bit = ((u32)0x1 << i); 4280 if (sig & cur_bit) { 4281 switch (cur_bit) { 4282 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4283 if (print) { 4284 _print_next_block(par_num++, "BRB"); 4285 _print_parity(bp, 4286 BRB1_REG_BRB1_PRTY_STS); 4287 } 4288 break; 4289 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4290 if (print) { 4291 _print_next_block(par_num++, "PARSER"); 4292 _print_parity(bp, PRS_REG_PRS_PRTY_STS); 4293 } 4294 break; 4295 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4296 if (print) { 4297 _print_next_block(par_num++, "TSDM"); 4298 _print_parity(bp, 4299 TSDM_REG_TSDM_PRTY_STS); 4300 } 4301 break; 4302 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4303 if (print) { 4304 _print_next_block(par_num++, 4305 "SEARCHER"); 4306 _print_parity(bp, SRC_REG_SRC_PRTY_STS); 4307 } 4308 break; 4309 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4310 if (print) { 4311 _print_next_block(par_num++, "TCM"); 4312 _print_parity(bp, 4313 TCM_REG_TCM_PRTY_STS); 4314 } 4315 break; 4316 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 4317 if (print) { 4318 _print_next_block(par_num++, "TSEMI"); 4319 _print_parity(bp, 4320 TSEM_REG_TSEM_PRTY_STS_0); 4321 _print_parity(bp, 4322 TSEM_REG_TSEM_PRTY_STS_1); 4323 } 4324 break; 4325 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4326 if (print) { 4327 _print_next_block(par_num++, "XPB"); 4328 _print_parity(bp, GRCBASE_XPB + 4329 PB_REG_PB_PRTY_STS); 4330 } 4331 break; 4332 } 4333 4334 /* Clear the bit */ 4335 sig &= ~cur_bit; 4336 } 4337 } 4338 4339 return par_num; 4340 } 4341 4342 static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, 4343 int par_num, bool *global, 4344 bool print) 4345 { 4346 int i = 0; 4347 u32 cur_bit = 0; 4348 for (i = 0; sig; i++) { 4349 cur_bit = ((u32)0x1 << i); 4350 if (sig & cur_bit) { 4351 switch (cur_bit) { 4352 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4353 if (print) { 4354 _print_next_block(par_num++, "PBF"); 4355 _print_parity(bp, PBF_REG_PBF_PRTY_STS); 4356 } 4357 break; 4358 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4359 if (print) { 4360 _print_next_block(par_num++, "QM"); 4361 _print_parity(bp, QM_REG_QM_PRTY_STS); 4362 } 4363 break; 4364 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4365 if (print) { 4366 _print_next_block(par_num++, "TM"); 4367 _print_parity(bp, TM_REG_TM_PRTY_STS); 4368 } 4369 break; 4370 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4371 if (print) { 4372 _print_next_block(par_num++, "XSDM"); 4373 _print_parity(bp, 4374 XSDM_REG_XSDM_PRTY_STS); 4375 } 4376 break; 4377 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4378 if (print) { 4379 _print_next_block(par_num++, "XCM"); 4380 _print_parity(bp, XCM_REG_XCM_PRTY_STS); 4381 } 4382 break; 4383 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4384 if (print) { 4385 _print_next_block(par_num++, "XSEMI"); 4386 _print_parity(bp, 4387 XSEM_REG_XSEM_PRTY_STS_0); 4388 _print_parity(bp, 4389 XSEM_REG_XSEM_PRTY_STS_1); 4390 } 4391 break; 4392 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4393 if (print) { 4394 _print_next_block(par_num++, 4395 "DOORBELLQ"); 4396 _print_parity(bp, 4397 DORQ_REG_DORQ_PRTY_STS); 4398 } 4399 break; 4400 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4401 if (print) { 4402 _print_next_block(par_num++, "NIG"); 4403 if (CHIP_IS_E1x(bp)) { 4404 _print_parity(bp, 4405 NIG_REG_NIG_PRTY_STS); 4406 } else { 4407 _print_parity(bp, 4408 NIG_REG_NIG_PRTY_STS_0); 4409 _print_parity(bp, 4410 NIG_REG_NIG_PRTY_STS_1); 4411 } 4412 } 4413 break; 4414 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4415 if (print) 4416 _print_next_block(par_num++, 4417 "VAUX PCI CORE"); 4418 *global = true; 4419 break; 4420 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4421 if (print) { 4422 _print_next_block(par_num++, "DEBUG"); 4423 _print_parity(bp, DBG_REG_DBG_PRTY_STS); 4424 } 4425 break; 4426 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4427 if (print) { 4428 _print_next_block(par_num++, "USDM"); 4429 _print_parity(bp, 4430 USDM_REG_USDM_PRTY_STS); 4431 } 4432 break; 4433 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4434 if (print) { 4435 _print_next_block(par_num++, "UCM"); 4436 _print_parity(bp, UCM_REG_UCM_PRTY_STS); 4437 } 4438 break; 4439 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4440 if (print) { 4441 _print_next_block(par_num++, "USEMI"); 4442 _print_parity(bp, 4443 USEM_REG_USEM_PRTY_STS_0); 4444 _print_parity(bp, 4445 USEM_REG_USEM_PRTY_STS_1); 4446 } 4447 break; 4448 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4449 if (print) { 4450 _print_next_block(par_num++, "UPB"); 4451 _print_parity(bp, GRCBASE_UPB + 4452 PB_REG_PB_PRTY_STS); 4453 } 4454 break; 4455 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4456 if (print) { 4457 _print_next_block(par_num++, "CSDM"); 4458 _print_parity(bp, 4459 CSDM_REG_CSDM_PRTY_STS); 4460 } 4461 break; 4462 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4463 if (print) { 4464 _print_next_block(par_num++, "CCM"); 4465 _print_parity(bp, CCM_REG_CCM_PRTY_STS); 4466 } 4467 break; 4468 } 4469 4470 /* Clear the bit */ 4471 sig &= ~cur_bit; 4472 } 4473 } 4474 4475 return par_num; 4476 } 4477 4478 static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, 4479 int par_num, bool print) 4480 { 4481 int i = 0; 4482 u32 cur_bit = 0; 4483 for (i = 0; sig; i++) { 4484 cur_bit = ((u32)0x1 << i); 4485 if (sig & cur_bit) { 4486 switch (cur_bit) { 4487 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4488 if (print) { 4489 _print_next_block(par_num++, "CSEMI"); 4490 _print_parity(bp, 4491 CSEM_REG_CSEM_PRTY_STS_0); 4492 _print_parity(bp, 4493 CSEM_REG_CSEM_PRTY_STS_1); 4494 } 4495 break; 4496 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4497 if (print) { 4498 _print_next_block(par_num++, "PXP"); 4499 _print_parity(bp, PXP_REG_PXP_PRTY_STS); 4500 _print_parity(bp, 4501 PXP2_REG_PXP2_PRTY_STS_0); 4502 _print_parity(bp, 4503 PXP2_REG_PXP2_PRTY_STS_1); 4504 } 4505 break; 4506 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4507 if (print) 4508 _print_next_block(par_num++, 4509 "PXPPCICLOCKCLIENT"); 4510 break; 4511 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4512 if (print) { 4513 _print_next_block(par_num++, "CFC"); 4514 _print_parity(bp, 4515 CFC_REG_CFC_PRTY_STS); 4516 } 4517 break; 4518 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4519 if (print) { 4520 _print_next_block(par_num++, "CDU"); 4521 _print_parity(bp, CDU_REG_CDU_PRTY_STS); 4522 } 4523 break; 4524 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4525 if (print) { 4526 _print_next_block(par_num++, "DMAE"); 4527 _print_parity(bp, 4528 DMAE_REG_DMAE_PRTY_STS); 4529 } 4530 break; 4531 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4532 if (print) { 4533 _print_next_block(par_num++, "IGU"); 4534 if (CHIP_IS_E1x(bp)) 4535 _print_parity(bp, 4536 HC_REG_HC_PRTY_STS); 4537 else 4538 _print_parity(bp, 4539 IGU_REG_IGU_PRTY_STS); 4540 } 4541 break; 4542 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4543 if (print) { 4544 _print_next_block(par_num++, "MISC"); 4545 _print_parity(bp, 4546 MISC_REG_MISC_PRTY_STS); 4547 } 4548 break; 4549 } 4550 4551 /* Clear the bit */ 4552 sig &= ~cur_bit; 4553 } 4554 } 4555 4556 return par_num; 4557 } 4558 4559 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4560 bool *global, bool print) 4561 { 4562 int i = 0; 4563 u32 cur_bit = 0; 4564 for (i = 0; sig; i++) { 4565 cur_bit = ((u32)0x1 << i); 4566 if (sig & cur_bit) { 4567 switch (cur_bit) { 4568 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4569 if (print) 4570 _print_next_block(par_num++, "MCP ROM"); 4571 *global = true; 4572 break; 4573 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4574 if (print) 4575 _print_next_block(par_num++, 4576 "MCP UMP RX"); 4577 *global = true; 4578 break; 4579 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4580 if (print) 4581 _print_next_block(par_num++, 4582 "MCP UMP TX"); 4583 *global = true; 4584 break; 4585 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4586 if (print) 4587 _print_next_block(par_num++, 4588 "MCP SCPAD"); 4589 *global = true; 4590 break; 4591 } 4592 4593 /* Clear the bit */ 4594 sig &= ~cur_bit; 4595 } 4596 } 4597 4598 return par_num; 4599 } 4600 4601 static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, 4602 int par_num, bool print) 4603 { 4604 int i = 0; 4605 u32 cur_bit = 0; 4606 for (i = 0; sig; i++) { 4607 cur_bit = ((u32)0x1 << i); 4608 if (sig & cur_bit) { 4609 switch (cur_bit) { 4610 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4611 if (print) { 4612 _print_next_block(par_num++, "PGLUE_B"); 4613 _print_parity(bp, 4614 PGLUE_B_REG_PGLUE_B_PRTY_STS); 4615 } 4616 break; 4617 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4618 if (print) { 4619 _print_next_block(par_num++, "ATC"); 4620 _print_parity(bp, 4621 ATC_REG_ATC_PRTY_STS); 4622 } 4623 break; 4624 } 4625 4626 /* Clear the bit */ 4627 sig &= ~cur_bit; 4628 } 4629 } 4630 4631 return par_num; 4632 } 4633 4634 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4635 u32 *sig) 4636 { 4637 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4638 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4639 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4640 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4641 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4642 int par_num = 0; 4643 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4644 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4645 sig[0] & HW_PRTY_ASSERT_SET_0, 4646 sig[1] & HW_PRTY_ASSERT_SET_1, 4647 sig[2] & HW_PRTY_ASSERT_SET_2, 4648 sig[3] & HW_PRTY_ASSERT_SET_3, 4649 sig[4] & HW_PRTY_ASSERT_SET_4); 4650 if (print) 4651 netdev_err(bp->dev, 4652 "Parity errors detected in blocks: "); 4653 par_num = bnx2x_check_blocks_with_parity0(bp, 4654 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4655 par_num = bnx2x_check_blocks_with_parity1(bp, 4656 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4657 par_num = bnx2x_check_blocks_with_parity2(bp, 4658 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4659 par_num = bnx2x_check_blocks_with_parity3( 4660 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4661 par_num = bnx2x_check_blocks_with_parity4(bp, 4662 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4663 4664 if (print) 4665 pr_cont("\n"); 4666 4667 return true; 4668 } else 4669 return false; 4670 } 4671 4672 /** 4673 * bnx2x_chk_parity_attn - checks for parity attentions. 4674 * 4675 * @bp: driver handle 4676 * @global: true if there was a global attention 4677 * @print: show parity attention in syslog 4678 */ 4679 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4680 { 4681 struct attn_route attn = { {0} }; 4682 int port = BP_PORT(bp); 4683 4684 attn.sig[0] = REG_RD(bp, 4685 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4686 port*4); 4687 attn.sig[1] = REG_RD(bp, 4688 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4689 port*4); 4690 attn.sig[2] = REG_RD(bp, 4691 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4692 port*4); 4693 attn.sig[3] = REG_RD(bp, 4694 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4695 port*4); 4696 4697 if (!CHIP_IS_E1x(bp)) 4698 attn.sig[4] = REG_RD(bp, 4699 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4700 port*4); 4701 4702 return bnx2x_parity_attn(bp, global, print, attn.sig); 4703 } 4704 4705 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4706 { 4707 u32 val; 4708 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4709 4710 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4711 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4712 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4713 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 4714 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4715 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 4716 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4717 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 4718 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4719 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 4720 if (val & 4721 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4722 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 4723 if (val & 4724 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4725 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 4726 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4727 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 4728 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4729 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 4730 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4731 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 4732 } 4733 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4734 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4735 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4736 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4737 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4738 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4739 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 4740 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4741 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 4742 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4743 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 4744 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4745 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4746 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4747 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 4748 } 4749 4750 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4751 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4752 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4753 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4754 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4755 } 4756 } 4757 4758 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4759 { 4760 struct attn_route attn, *group_mask; 4761 int port = BP_PORT(bp); 4762 int index; 4763 u32 reg_addr; 4764 u32 val; 4765 u32 aeu_mask; 4766 bool global = false; 4767 4768 /* need to take HW lock because MCP or other port might also 4769 try to handle this event */ 4770 bnx2x_acquire_alr(bp); 4771 4772 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4773 #ifndef BNX2X_STOP_ON_ERROR 4774 bp->recovery_state = BNX2X_RECOVERY_INIT; 4775 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4776 /* Disable HW interrupts */ 4777 bnx2x_int_disable(bp); 4778 /* In case of parity errors don't handle attentions so that 4779 * other function would "see" parity errors. 4780 */ 4781 #else 4782 bnx2x_panic(); 4783 #endif 4784 bnx2x_release_alr(bp); 4785 return; 4786 } 4787 4788 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4789 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4790 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4791 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4792 if (!CHIP_IS_E1x(bp)) 4793 attn.sig[4] = 4794 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4795 else 4796 attn.sig[4] = 0; 4797 4798 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4799 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4800 4801 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4802 if (deasserted & (1 << index)) { 4803 group_mask = &bp->attn_group[index]; 4804 4805 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 4806 index, 4807 group_mask->sig[0], group_mask->sig[1], 4808 group_mask->sig[2], group_mask->sig[3], 4809 group_mask->sig[4]); 4810 4811 bnx2x_attn_int_deasserted4(bp, 4812 attn.sig[4] & group_mask->sig[4]); 4813 bnx2x_attn_int_deasserted3(bp, 4814 attn.sig[3] & group_mask->sig[3]); 4815 bnx2x_attn_int_deasserted1(bp, 4816 attn.sig[1] & group_mask->sig[1]); 4817 bnx2x_attn_int_deasserted2(bp, 4818 attn.sig[2] & group_mask->sig[2]); 4819 bnx2x_attn_int_deasserted0(bp, 4820 attn.sig[0] & group_mask->sig[0]); 4821 } 4822 } 4823 4824 bnx2x_release_alr(bp); 4825 4826 if (bp->common.int_block == INT_BLOCK_HC) 4827 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4828 COMMAND_REG_ATTN_BITS_CLR); 4829 else 4830 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4831 4832 val = ~deasserted; 4833 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4834 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4835 REG_WR(bp, reg_addr, val); 4836 4837 if (~bp->attn_state & deasserted) 4838 BNX2X_ERR("IGU ERROR\n"); 4839 4840 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4841 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4842 4843 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4844 aeu_mask = REG_RD(bp, reg_addr); 4845 4846 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4847 aeu_mask, deasserted); 4848 aeu_mask |= (deasserted & 0x3ff); 4849 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4850 4851 REG_WR(bp, reg_addr, aeu_mask); 4852 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4853 4854 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4855 bp->attn_state &= ~deasserted; 4856 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4857 } 4858 4859 static void bnx2x_attn_int(struct bnx2x *bp) 4860 { 4861 /* read local copy of bits */ 4862 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4863 attn_bits); 4864 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4865 attn_bits_ack); 4866 u32 attn_state = bp->attn_state; 4867 4868 /* look for changed bits */ 4869 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4870 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4871 4872 DP(NETIF_MSG_HW, 4873 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4874 attn_bits, attn_ack, asserted, deasserted); 4875 4876 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4877 BNX2X_ERR("BAD attention state\n"); 4878 4879 /* handle bits that were raised */ 4880 if (asserted) 4881 bnx2x_attn_int_asserted(bp, asserted); 4882 4883 if (deasserted) 4884 bnx2x_attn_int_deasserted(bp, deasserted); 4885 } 4886 4887 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4888 u16 index, u8 op, u8 update) 4889 { 4890 u32 igu_addr = bp->igu_base_addr; 4891 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4892 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4893 igu_addr); 4894 } 4895 4896 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4897 { 4898 /* No memory barriers */ 4899 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4900 mmiowb(); /* keep prod updates ordered */ 4901 } 4902 4903 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4904 union event_ring_elem *elem) 4905 { 4906 u8 err = elem->message.error; 4907 4908 if (!bp->cnic_eth_dev.starting_cid || 4909 (cid < bp->cnic_eth_dev.starting_cid && 4910 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4911 return 1; 4912 4913 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4914 4915 if (unlikely(err)) { 4916 4917 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4918 cid); 4919 bnx2x_panic_dump(bp, false); 4920 } 4921 bnx2x_cnic_cfc_comp(bp, cid, err); 4922 return 0; 4923 } 4924 4925 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4926 { 4927 struct bnx2x_mcast_ramrod_params rparam; 4928 int rc; 4929 4930 memset(&rparam, 0, sizeof(rparam)); 4931 4932 rparam.mcast_obj = &bp->mcast_obj; 4933 4934 netif_addr_lock_bh(bp->dev); 4935 4936 /* Clear pending state for the last command */ 4937 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4938 4939 /* If there are pending mcast commands - send them */ 4940 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4941 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4942 if (rc < 0) 4943 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4944 rc); 4945 } 4946 4947 netif_addr_unlock_bh(bp->dev); 4948 } 4949 4950 static void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4951 union event_ring_elem *elem) 4952 { 4953 unsigned long ramrod_flags = 0; 4954 int rc = 0; 4955 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4956 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4957 4958 /* Always push next commands out, don't wait here */ 4959 __set_bit(RAMROD_CONT, &ramrod_flags); 4960 4961 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo) 4962 >> BNX2X_SWCID_SHIFT) { 4963 case BNX2X_FILTER_MAC_PENDING: 4964 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 4965 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) 4966 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4967 else 4968 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; 4969 4970 break; 4971 case BNX2X_FILTER_MCAST_PENDING: 4972 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 4973 /* This is only relevant for 57710 where multicast MACs are 4974 * configured as unicast MACs using the same ramrod. 4975 */ 4976 bnx2x_handle_mcast_eqe(bp); 4977 return; 4978 default: 4979 BNX2X_ERR("Unsupported classification command: %d\n", 4980 elem->message.data.eth_event.echo); 4981 return; 4982 } 4983 4984 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4985 4986 if (rc < 0) 4987 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4988 else if (rc > 0) 4989 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4990 } 4991 4992 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4993 4994 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4995 { 4996 netif_addr_lock_bh(bp->dev); 4997 4998 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4999 5000 /* Send rx_mode command again if was requested */ 5001 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 5002 bnx2x_set_storm_rx_mode(bp); 5003 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 5004 &bp->sp_state)) 5005 bnx2x_set_iscsi_eth_rx_mode(bp, true); 5006 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 5007 &bp->sp_state)) 5008 bnx2x_set_iscsi_eth_rx_mode(bp, false); 5009 5010 netif_addr_unlock_bh(bp->dev); 5011 } 5012 5013 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, 5014 union event_ring_elem *elem) 5015 { 5016 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { 5017 DP(BNX2X_MSG_SP, 5018 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", 5019 elem->message.data.vif_list_event.func_bit_map); 5020 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, 5021 elem->message.data.vif_list_event.func_bit_map); 5022 } else if (elem->message.data.vif_list_event.echo == 5023 VIF_LIST_RULE_SET) { 5024 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); 5025 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); 5026 } 5027 } 5028 5029 /* called with rtnl_lock */ 5030 static void bnx2x_after_function_update(struct bnx2x *bp) 5031 { 5032 int q, rc; 5033 struct bnx2x_fastpath *fp; 5034 struct bnx2x_queue_state_params queue_params = {NULL}; 5035 struct bnx2x_queue_update_params *q_update_params = 5036 &queue_params.params.update; 5037 5038 /* Send Q update command with afex vlan removal values for all Qs */ 5039 queue_params.cmd = BNX2X_Q_CMD_UPDATE; 5040 5041 /* set silent vlan removal values according to vlan mode */ 5042 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 5043 &q_update_params->update_flags); 5044 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 5045 &q_update_params->update_flags); 5046 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5047 5048 /* in access mode mark mask and value are 0 to strip all vlans */ 5049 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { 5050 q_update_params->silent_removal_value = 0; 5051 q_update_params->silent_removal_mask = 0; 5052 } else { 5053 q_update_params->silent_removal_value = 5054 (bp->afex_def_vlan_tag & VLAN_VID_MASK); 5055 q_update_params->silent_removal_mask = VLAN_VID_MASK; 5056 } 5057 5058 for_each_eth_queue(bp, q) { 5059 /* Set the appropriate Queue object */ 5060 fp = &bp->fp[q]; 5061 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5062 5063 /* send the ramrod */ 5064 rc = bnx2x_queue_state_change(bp, &queue_params); 5065 if (rc < 0) 5066 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5067 q); 5068 } 5069 5070 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { 5071 fp = &bp->fp[FCOE_IDX(bp)]; 5072 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5073 5074 /* clear pending completion bit */ 5075 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5076 5077 /* mark latest Q bit */ 5078 smp_mb__before_clear_bit(); 5079 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 5080 smp_mb__after_clear_bit(); 5081 5082 /* send Q update ramrod for FCoE Q */ 5083 rc = bnx2x_queue_state_change(bp, &queue_params); 5084 if (rc < 0) 5085 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5086 q); 5087 } else { 5088 /* If no FCoE ring - ACK MCP now */ 5089 bnx2x_link_report(bp); 5090 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5091 } 5092 } 5093 5094 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 5095 struct bnx2x *bp, u32 cid) 5096 { 5097 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 5098 5099 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) 5100 return &bnx2x_fcoe_sp_obj(bp, q_obj); 5101 else 5102 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; 5103 } 5104 5105 static void bnx2x_eq_int(struct bnx2x *bp) 5106 { 5107 u16 hw_cons, sw_cons, sw_prod; 5108 union event_ring_elem *elem; 5109 u8 echo; 5110 u32 cid; 5111 u8 opcode; 5112 int rc, spqe_cnt = 0; 5113 struct bnx2x_queue_sp_obj *q_obj; 5114 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 5115 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 5116 5117 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 5118 5119 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 5120 * when we get the next-page we need to adjust so the loop 5121 * condition below will be met. The next element is the size of a 5122 * regular element and hence incrementing by 1 5123 */ 5124 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 5125 hw_cons++; 5126 5127 /* This function may never run in parallel with itself for a 5128 * specific bp, thus there is no need in "paired" read memory 5129 * barrier here. 5130 */ 5131 sw_cons = bp->eq_cons; 5132 sw_prod = bp->eq_prod; 5133 5134 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 5135 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 5136 5137 for (; sw_cons != hw_cons; 5138 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 5139 5140 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 5141 5142 rc = bnx2x_iov_eq_sp_event(bp, elem); 5143 if (!rc) { 5144 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", 5145 rc); 5146 goto next_spqe; 5147 } 5148 5149 /* elem CID originates from FW; actually LE */ 5150 cid = SW_CID((__force __le32) 5151 elem->message.data.cfc_del_event.cid); 5152 opcode = elem->message.opcode; 5153 5154 /* handle eq element */ 5155 switch (opcode) { 5156 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 5157 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n"); 5158 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event); 5159 continue; 5160 5161 case EVENT_RING_OPCODE_STAT_QUERY: 5162 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, 5163 "got statistics comp event %d\n", 5164 bp->stats_comp++); 5165 /* nothing to do with stats comp */ 5166 goto next_spqe; 5167 5168 case EVENT_RING_OPCODE_CFC_DEL: 5169 /* handle according to cid range */ 5170 /* 5171 * we may want to verify here that the bp state is 5172 * HALTING 5173 */ 5174 DP(BNX2X_MSG_SP, 5175 "got delete ramrod for MULTI[%d]\n", cid); 5176 5177 if (CNIC_LOADED(bp) && 5178 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 5179 goto next_spqe; 5180 5181 q_obj = bnx2x_cid_to_q_obj(bp, cid); 5182 5183 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 5184 break; 5185 5186 goto next_spqe; 5187 5188 case EVENT_RING_OPCODE_STOP_TRAFFIC: 5189 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 5190 if (f_obj->complete_cmd(bp, f_obj, 5191 BNX2X_F_CMD_TX_STOP)) 5192 break; 5193 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 5194 goto next_spqe; 5195 5196 case EVENT_RING_OPCODE_START_TRAFFIC: 5197 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 5198 if (f_obj->complete_cmd(bp, f_obj, 5199 BNX2X_F_CMD_TX_START)) 5200 break; 5201 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 5202 goto next_spqe; 5203 5204 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 5205 echo = elem->message.data.function_update_event.echo; 5206 if (echo == SWITCH_UPDATE) { 5207 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5208 "got FUNC_SWITCH_UPDATE ramrod\n"); 5209 if (f_obj->complete_cmd( 5210 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) 5211 break; 5212 5213 } else { 5214 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, 5215 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 5216 f_obj->complete_cmd(bp, f_obj, 5217 BNX2X_F_CMD_AFEX_UPDATE); 5218 5219 /* We will perform the Queues update from 5220 * sp_rtnl task as all Queue SP operations 5221 * should run under rtnl_lock. 5222 */ 5223 smp_mb__before_clear_bit(); 5224 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, 5225 &bp->sp_rtnl_state); 5226 smp_mb__after_clear_bit(); 5227 5228 schedule_delayed_work(&bp->sp_rtnl_task, 0); 5229 } 5230 5231 goto next_spqe; 5232 5233 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 5234 f_obj->complete_cmd(bp, f_obj, 5235 BNX2X_F_CMD_AFEX_VIFLISTS); 5236 bnx2x_after_afex_vif_lists(bp, elem); 5237 goto next_spqe; 5238 case EVENT_RING_OPCODE_FUNCTION_START: 5239 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5240 "got FUNC_START ramrod\n"); 5241 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 5242 break; 5243 5244 goto next_spqe; 5245 5246 case EVENT_RING_OPCODE_FUNCTION_STOP: 5247 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5248 "got FUNC_STOP ramrod\n"); 5249 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 5250 break; 5251 5252 goto next_spqe; 5253 } 5254 5255 switch (opcode | bp->state) { 5256 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5257 BNX2X_STATE_OPEN): 5258 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5259 BNX2X_STATE_OPENING_WAIT4_PORT): 5260 cid = elem->message.data.eth_event.echo & 5261 BNX2X_SWCID_MASK; 5262 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 5263 cid); 5264 rss_raw->clear_pending(rss_raw); 5265 break; 5266 5267 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 5268 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 5269 case (EVENT_RING_OPCODE_SET_MAC | 5270 BNX2X_STATE_CLOSING_WAIT4_HALT): 5271 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5272 BNX2X_STATE_OPEN): 5273 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5274 BNX2X_STATE_DIAG): 5275 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5276 BNX2X_STATE_CLOSING_WAIT4_HALT): 5277 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 5278 bnx2x_handle_classification_eqe(bp, elem); 5279 break; 5280 5281 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5282 BNX2X_STATE_OPEN): 5283 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5284 BNX2X_STATE_DIAG): 5285 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5286 BNX2X_STATE_CLOSING_WAIT4_HALT): 5287 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 5288 bnx2x_handle_mcast_eqe(bp); 5289 break; 5290 5291 case (EVENT_RING_OPCODE_FILTERS_RULES | 5292 BNX2X_STATE_OPEN): 5293 case (EVENT_RING_OPCODE_FILTERS_RULES | 5294 BNX2X_STATE_DIAG): 5295 case (EVENT_RING_OPCODE_FILTERS_RULES | 5296 BNX2X_STATE_CLOSING_WAIT4_HALT): 5297 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 5298 bnx2x_handle_rx_mode_eqe(bp); 5299 break; 5300 default: 5301 /* unknown event log error and continue */ 5302 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 5303 elem->message.opcode, bp->state); 5304 } 5305 next_spqe: 5306 spqe_cnt++; 5307 } /* for */ 5308 5309 smp_mb__before_atomic_inc(); 5310 atomic_add(spqe_cnt, &bp->eq_spq_left); 5311 5312 bp->eq_cons = sw_cons; 5313 bp->eq_prod = sw_prod; 5314 /* Make sure that above mem writes were issued towards the memory */ 5315 smp_wmb(); 5316 5317 /* update producer */ 5318 bnx2x_update_eq_prod(bp, bp->eq_prod); 5319 } 5320 5321 static void bnx2x_sp_task(struct work_struct *work) 5322 { 5323 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 5324 5325 DP(BNX2X_MSG_SP, "sp task invoked\n"); 5326 5327 /* make sure the atomic interrupt_occurred has been written */ 5328 smp_rmb(); 5329 if (atomic_read(&bp->interrupt_occurred)) { 5330 5331 /* what work needs to be performed? */ 5332 u16 status = bnx2x_update_dsb_idx(bp); 5333 5334 DP(BNX2X_MSG_SP, "status %x\n", status); 5335 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); 5336 atomic_set(&bp->interrupt_occurred, 0); 5337 5338 /* HW attentions */ 5339 if (status & BNX2X_DEF_SB_ATT_IDX) { 5340 bnx2x_attn_int(bp); 5341 status &= ~BNX2X_DEF_SB_ATT_IDX; 5342 } 5343 5344 /* SP events: STAT_QUERY and others */ 5345 if (status & BNX2X_DEF_SB_IDX) { 5346 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 5347 5348 if (FCOE_INIT(bp) && 5349 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 5350 /* Prevent local bottom-halves from running as 5351 * we are going to change the local NAPI list. 5352 */ 5353 local_bh_disable(); 5354 napi_schedule(&bnx2x_fcoe(bp, napi)); 5355 local_bh_enable(); 5356 } 5357 5358 /* Handle EQ completions */ 5359 bnx2x_eq_int(bp); 5360 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 5361 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 5362 5363 status &= ~BNX2X_DEF_SB_IDX; 5364 } 5365 5366 /* if status is non zero then perhaps something went wrong */ 5367 if (unlikely(status)) 5368 DP(BNX2X_MSG_SP, 5369 "got an unknown interrupt! (status 0x%x)\n", status); 5370 5371 /* ack status block only if something was actually handled */ 5372 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 5373 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 5374 } 5375 5376 /* must be called after the EQ processing (since eq leads to sriov 5377 * ramrod completion flows). 5378 * This flow may have been scheduled by the arrival of a ramrod 5379 * completion, or by the sriov code rescheduling itself. 5380 */ 5381 bnx2x_iov_sp_task(bp); 5382 5383 /* afex - poll to check if VIFSET_ACK should be sent to MFW */ 5384 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, 5385 &bp->sp_state)) { 5386 bnx2x_link_report(bp); 5387 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5388 } 5389 } 5390 5391 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 5392 { 5393 struct net_device *dev = dev_instance; 5394 struct bnx2x *bp = netdev_priv(dev); 5395 5396 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 5397 IGU_INT_DISABLE, 0); 5398 5399 #ifdef BNX2X_STOP_ON_ERROR 5400 if (unlikely(bp->panic)) 5401 return IRQ_HANDLED; 5402 #endif 5403 5404 if (CNIC_LOADED(bp)) { 5405 struct cnic_ops *c_ops; 5406 5407 rcu_read_lock(); 5408 c_ops = rcu_dereference(bp->cnic_ops); 5409 if (c_ops) 5410 c_ops->cnic_handler(bp->cnic_data, NULL); 5411 rcu_read_unlock(); 5412 } 5413 5414 /* schedule sp task to perform default status block work, ack 5415 * attentions and enable interrupts. 5416 */ 5417 bnx2x_schedule_sp_task(bp); 5418 5419 return IRQ_HANDLED; 5420 } 5421 5422 /* end of slow path */ 5423 5424 void bnx2x_drv_pulse(struct bnx2x *bp) 5425 { 5426 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 5427 bp->fw_drv_pulse_wr_seq); 5428 } 5429 5430 static void bnx2x_timer(unsigned long data) 5431 { 5432 struct bnx2x *bp = (struct bnx2x *) data; 5433 5434 if (!netif_running(bp->dev)) 5435 return; 5436 5437 if (IS_PF(bp) && 5438 !BP_NOMCP(bp)) { 5439 int mb_idx = BP_FW_MB_IDX(bp); 5440 u32 drv_pulse; 5441 u32 mcp_pulse; 5442 5443 ++bp->fw_drv_pulse_wr_seq; 5444 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 5445 /* TBD - add SYSTEM_TIME */ 5446 drv_pulse = bp->fw_drv_pulse_wr_seq; 5447 bnx2x_drv_pulse(bp); 5448 5449 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 5450 MCP_PULSE_SEQ_MASK); 5451 /* The delta between driver pulse and mcp response 5452 * should be 1 (before mcp response) or 0 (after mcp response) 5453 */ 5454 if ((drv_pulse != mcp_pulse) && 5455 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 5456 /* someone lost a heartbeat... */ 5457 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 5458 drv_pulse, mcp_pulse); 5459 } 5460 } 5461 5462 if (bp->state == BNX2X_STATE_OPEN) 5463 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 5464 5465 /* sample pf vf bulletin board for new posts from pf */ 5466 if (IS_VF(bp)) 5467 bnx2x_timer_sriov(bp); 5468 5469 mod_timer(&bp->timer, jiffies + bp->current_interval); 5470 } 5471 5472 /* end of Statistics */ 5473 5474 /* nic init */ 5475 5476 /* 5477 * nic init service functions 5478 */ 5479 5480 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 5481 { 5482 u32 i; 5483 if (!(len%4) && !(addr%4)) 5484 for (i = 0; i < len; i += 4) 5485 REG_WR(bp, addr + i, fill); 5486 else 5487 for (i = 0; i < len; i++) 5488 REG_WR8(bp, addr + i, fill); 5489 } 5490 5491 /* helper: writes FP SP data to FW - data_size in dwords */ 5492 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 5493 int fw_sb_id, 5494 u32 *sb_data_p, 5495 u32 data_size) 5496 { 5497 int index; 5498 for (index = 0; index < data_size; index++) 5499 REG_WR(bp, BAR_CSTRORM_INTMEM + 5500 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 5501 sizeof(u32)*index, 5502 *(sb_data_p + index)); 5503 } 5504 5505 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 5506 { 5507 u32 *sb_data_p; 5508 u32 data_size = 0; 5509 struct hc_status_block_data_e2 sb_data_e2; 5510 struct hc_status_block_data_e1x sb_data_e1x; 5511 5512 /* disable the function first */ 5513 if (!CHIP_IS_E1x(bp)) { 5514 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5515 sb_data_e2.common.state = SB_DISABLED; 5516 sb_data_e2.common.p_func.vf_valid = false; 5517 sb_data_p = (u32 *)&sb_data_e2; 5518 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5519 } else { 5520 memset(&sb_data_e1x, 0, 5521 sizeof(struct hc_status_block_data_e1x)); 5522 sb_data_e1x.common.state = SB_DISABLED; 5523 sb_data_e1x.common.p_func.vf_valid = false; 5524 sb_data_p = (u32 *)&sb_data_e1x; 5525 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5526 } 5527 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5528 5529 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5530 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 5531 CSTORM_STATUS_BLOCK_SIZE); 5532 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5533 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 5534 CSTORM_SYNC_BLOCK_SIZE); 5535 } 5536 5537 /* helper: writes SP SB data to FW */ 5538 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 5539 struct hc_sp_status_block_data *sp_sb_data) 5540 { 5541 int func = BP_FUNC(bp); 5542 int i; 5543 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 5544 REG_WR(bp, BAR_CSTRORM_INTMEM + 5545 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 5546 i*sizeof(u32), 5547 *((u32 *)sp_sb_data + i)); 5548 } 5549 5550 static void bnx2x_zero_sp_sb(struct bnx2x *bp) 5551 { 5552 int func = BP_FUNC(bp); 5553 struct hc_sp_status_block_data sp_sb_data; 5554 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5555 5556 sp_sb_data.state = SB_DISABLED; 5557 sp_sb_data.p_func.vf_valid = false; 5558 5559 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5560 5561 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5562 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 5563 CSTORM_SP_STATUS_BLOCK_SIZE); 5564 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5565 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 5566 CSTORM_SP_SYNC_BLOCK_SIZE); 5567 } 5568 5569 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 5570 int igu_sb_id, int igu_seg_id) 5571 { 5572 hc_sm->igu_sb_id = igu_sb_id; 5573 hc_sm->igu_seg_id = igu_seg_id; 5574 hc_sm->timer_value = 0xFF; 5575 hc_sm->time_to_expire = 0xFFFFFFFF; 5576 } 5577 5578 /* allocates state machine ids. */ 5579 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5580 { 5581 /* zero out state machine indices */ 5582 /* rx indices */ 5583 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5584 5585 /* tx indices */ 5586 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5587 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5588 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5589 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5590 5591 /* map indices */ 5592 /* rx indices */ 5593 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5594 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5595 5596 /* tx indices */ 5597 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5598 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5599 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5600 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5601 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5602 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5603 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5604 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5605 } 5606 5607 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5608 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5609 { 5610 int igu_seg_id; 5611 5612 struct hc_status_block_data_e2 sb_data_e2; 5613 struct hc_status_block_data_e1x sb_data_e1x; 5614 struct hc_status_block_sm *hc_sm_p; 5615 int data_size; 5616 u32 *sb_data_p; 5617 5618 if (CHIP_INT_MODE_IS_BC(bp)) 5619 igu_seg_id = HC_SEG_ACCESS_NORM; 5620 else 5621 igu_seg_id = IGU_SEG_ACCESS_NORM; 5622 5623 bnx2x_zero_fp_sb(bp, fw_sb_id); 5624 5625 if (!CHIP_IS_E1x(bp)) { 5626 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5627 sb_data_e2.common.state = SB_ENABLED; 5628 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5629 sb_data_e2.common.p_func.vf_id = vfid; 5630 sb_data_e2.common.p_func.vf_valid = vf_valid; 5631 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5632 sb_data_e2.common.same_igu_sb_1b = true; 5633 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5634 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5635 hc_sm_p = sb_data_e2.common.state_machine; 5636 sb_data_p = (u32 *)&sb_data_e2; 5637 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5638 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5639 } else { 5640 memset(&sb_data_e1x, 0, 5641 sizeof(struct hc_status_block_data_e1x)); 5642 sb_data_e1x.common.state = SB_ENABLED; 5643 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5644 sb_data_e1x.common.p_func.vf_id = 0xff; 5645 sb_data_e1x.common.p_func.vf_valid = false; 5646 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5647 sb_data_e1x.common.same_igu_sb_1b = true; 5648 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5649 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5650 hc_sm_p = sb_data_e1x.common.state_machine; 5651 sb_data_p = (u32 *)&sb_data_e1x; 5652 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5653 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5654 } 5655 5656 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5657 igu_sb_id, igu_seg_id); 5658 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5659 igu_sb_id, igu_seg_id); 5660 5661 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 5662 5663 /* write indices to HW - PCI guarantees endianity of regpairs */ 5664 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5665 } 5666 5667 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5668 u16 tx_usec, u16 rx_usec) 5669 { 5670 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5671 false, rx_usec); 5672 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5673 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5674 tx_usec); 5675 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5676 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5677 tx_usec); 5678 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5679 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5680 tx_usec); 5681 } 5682 5683 static void bnx2x_init_def_sb(struct bnx2x *bp) 5684 { 5685 struct host_sp_status_block *def_sb = bp->def_status_blk; 5686 dma_addr_t mapping = bp->def_status_blk_mapping; 5687 int igu_sp_sb_index; 5688 int igu_seg_id; 5689 int port = BP_PORT(bp); 5690 int func = BP_FUNC(bp); 5691 int reg_offset, reg_offset_en5; 5692 u64 section; 5693 int index; 5694 struct hc_sp_status_block_data sp_sb_data; 5695 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5696 5697 if (CHIP_INT_MODE_IS_BC(bp)) { 5698 igu_sp_sb_index = DEF_SB_IGU_ID; 5699 igu_seg_id = HC_SEG_ACCESS_DEF; 5700 } else { 5701 igu_sp_sb_index = bp->igu_dsb_id; 5702 igu_seg_id = IGU_SEG_ACCESS_DEF; 5703 } 5704 5705 /* ATTN */ 5706 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5707 atten_status_block); 5708 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5709 5710 bp->attn_state = 0; 5711 5712 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5713 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5714 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5715 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5716 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5717 int sindex; 5718 /* take care of sig[0]..sig[4] */ 5719 for (sindex = 0; sindex < 4; sindex++) 5720 bp->attn_group[index].sig[sindex] = 5721 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5722 5723 if (!CHIP_IS_E1x(bp)) 5724 /* 5725 * enable5 is separate from the rest of the registers, 5726 * and therefore the address skip is 4 5727 * and not 16 between the different groups 5728 */ 5729 bp->attn_group[index].sig[4] = REG_RD(bp, 5730 reg_offset_en5 + 0x4*index); 5731 else 5732 bp->attn_group[index].sig[4] = 0; 5733 } 5734 5735 if (bp->common.int_block == INT_BLOCK_HC) { 5736 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5737 HC_REG_ATTN_MSG0_ADDR_L); 5738 5739 REG_WR(bp, reg_offset, U64_LO(section)); 5740 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5741 } else if (!CHIP_IS_E1x(bp)) { 5742 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5743 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5744 } 5745 5746 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5747 sp_sb); 5748 5749 bnx2x_zero_sp_sb(bp); 5750 5751 /* PCI guarantees endianity of regpairs */ 5752 sp_sb_data.state = SB_ENABLED; 5753 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5754 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5755 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5756 sp_sb_data.igu_seg_id = igu_seg_id; 5757 sp_sb_data.p_func.pf_id = func; 5758 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5759 sp_sb_data.p_func.vf_id = 0xff; 5760 5761 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5762 5763 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5764 } 5765 5766 void bnx2x_update_coalesce(struct bnx2x *bp) 5767 { 5768 int i; 5769 5770 for_each_eth_queue(bp, i) 5771 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5772 bp->tx_ticks, bp->rx_ticks); 5773 } 5774 5775 static void bnx2x_init_sp_ring(struct bnx2x *bp) 5776 { 5777 spin_lock_init(&bp->spq_lock); 5778 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5779 5780 bp->spq_prod_idx = 0; 5781 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5782 bp->spq_prod_bd = bp->spq; 5783 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5784 } 5785 5786 static void bnx2x_init_eq_ring(struct bnx2x *bp) 5787 { 5788 int i; 5789 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5790 union event_ring_elem *elem = 5791 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5792 5793 elem->next_page.addr.hi = 5794 cpu_to_le32(U64_HI(bp->eq_mapping + 5795 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5796 elem->next_page.addr.lo = 5797 cpu_to_le32(U64_LO(bp->eq_mapping + 5798 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5799 } 5800 bp->eq_cons = 0; 5801 bp->eq_prod = NUM_EQ_DESC; 5802 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5803 /* we want a warning message before it gets wrought... */ 5804 atomic_set(&bp->eq_spq_left, 5805 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5806 } 5807 5808 /* called with netif_addr_lock_bh() */ 5809 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5810 unsigned long rx_mode_flags, 5811 unsigned long rx_accept_flags, 5812 unsigned long tx_accept_flags, 5813 unsigned long ramrod_flags) 5814 { 5815 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5816 int rc; 5817 5818 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5819 5820 /* Prepare ramrod parameters */ 5821 ramrod_param.cid = 0; 5822 ramrod_param.cl_id = cl_id; 5823 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5824 ramrod_param.func_id = BP_FUNC(bp); 5825 5826 ramrod_param.pstate = &bp->sp_state; 5827 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5828 5829 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5830 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5831 5832 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5833 5834 ramrod_param.ramrod_flags = ramrod_flags; 5835 ramrod_param.rx_mode_flags = rx_mode_flags; 5836 5837 ramrod_param.rx_accept_flags = rx_accept_flags; 5838 ramrod_param.tx_accept_flags = tx_accept_flags; 5839 5840 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5841 if (rc < 0) { 5842 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5843 return rc; 5844 } 5845 5846 return 0; 5847 } 5848 5849 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, 5850 unsigned long *rx_accept_flags, 5851 unsigned long *tx_accept_flags) 5852 { 5853 /* Clear the flags first */ 5854 *rx_accept_flags = 0; 5855 *tx_accept_flags = 0; 5856 5857 switch (rx_mode) { 5858 case BNX2X_RX_MODE_NONE: 5859 /* 5860 * 'drop all' supersedes any accept flags that may have been 5861 * passed to the function. 5862 */ 5863 break; 5864 case BNX2X_RX_MODE_NORMAL: 5865 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 5866 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); 5867 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 5868 5869 /* internal switching mode */ 5870 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 5871 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); 5872 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 5873 5874 break; 5875 case BNX2X_RX_MODE_ALLMULTI: 5876 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 5877 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 5878 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 5879 5880 /* internal switching mode */ 5881 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 5882 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 5883 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 5884 5885 break; 5886 case BNX2X_RX_MODE_PROMISC: 5887 /* According to definition of SI mode, iface in promisc mode 5888 * should receive matched and unmatched (in resolution of port) 5889 * unicast packets. 5890 */ 5891 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); 5892 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 5893 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 5894 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 5895 5896 /* internal switching mode */ 5897 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 5898 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 5899 5900 if (IS_MF_SI(bp)) 5901 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); 5902 else 5903 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 5904 5905 break; 5906 default: 5907 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); 5908 return -EINVAL; 5909 } 5910 5911 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ 5912 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5913 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 5914 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 5915 } 5916 5917 return 0; 5918 } 5919 5920 /* called with netif_addr_lock_bh() */ 5921 int bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5922 { 5923 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5924 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5925 int rc; 5926 5927 if (!NO_FCOE(bp)) 5928 /* Configure rx_mode of FCoE Queue */ 5929 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5930 5931 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, 5932 &tx_accept_flags); 5933 if (rc) 5934 return rc; 5935 5936 __set_bit(RAMROD_RX, &ramrod_flags); 5937 __set_bit(RAMROD_TX, &ramrod_flags); 5938 5939 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, 5940 rx_accept_flags, tx_accept_flags, 5941 ramrod_flags); 5942 } 5943 5944 static void bnx2x_init_internal_common(struct bnx2x *bp) 5945 { 5946 int i; 5947 5948 if (IS_MF_SI(bp)) 5949 /* 5950 * In switch independent mode, the TSTORM needs to accept 5951 * packets that failed classification, since approximate match 5952 * mac addresses aren't written to NIG LLH 5953 */ 5954 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5955 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5956 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5957 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5958 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5959 5960 /* Zero this manually as its initialization is 5961 currently missing in the initTool */ 5962 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5963 REG_WR(bp, BAR_USTRORM_INTMEM + 5964 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5965 if (!CHIP_IS_E1x(bp)) { 5966 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5967 CHIP_INT_MODE_IS_BC(bp) ? 5968 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5969 } 5970 } 5971 5972 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5973 { 5974 switch (load_code) { 5975 case FW_MSG_CODE_DRV_LOAD_COMMON: 5976 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5977 bnx2x_init_internal_common(bp); 5978 /* no break */ 5979 5980 case FW_MSG_CODE_DRV_LOAD_PORT: 5981 /* nothing to do */ 5982 /* no break */ 5983 5984 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5985 /* internal memory per function is 5986 initialized inside bnx2x_pf_init */ 5987 break; 5988 5989 default: 5990 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5991 break; 5992 } 5993 } 5994 5995 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5996 { 5997 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); 5998 } 5999 6000 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 6001 { 6002 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); 6003 } 6004 6005 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 6006 { 6007 if (CHIP_IS_E1x(fp->bp)) 6008 return BP_L_ID(fp->bp) + fp->index; 6009 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 6010 return bnx2x_fp_igu_sb_id(fp); 6011 } 6012 6013 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 6014 { 6015 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 6016 u8 cos; 6017 unsigned long q_type = 0; 6018 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 6019 fp->rx_queue = fp_idx; 6020 fp->cid = fp_idx; 6021 fp->cl_id = bnx2x_fp_cl_id(fp); 6022 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 6023 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 6024 /* qZone id equals to FW (per path) client id */ 6025 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 6026 6027 /* init shortcut */ 6028 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 6029 6030 /* Setup SB indices */ 6031 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 6032 6033 /* Configure Queue State object */ 6034 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 6035 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 6036 6037 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 6038 6039 /* init tx data */ 6040 for_each_cos_in_tx_queue(fp, cos) { 6041 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], 6042 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), 6043 FP_COS_TO_TXQ(fp, cos, bp), 6044 BNX2X_TX_SB_INDEX_BASE + cos, fp); 6045 cids[cos] = fp->txdata_ptr[cos]->cid; 6046 } 6047 6048 /* nothing more for vf to do here */ 6049 if (IS_VF(bp)) 6050 return; 6051 6052 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 6053 fp->fw_sb_id, fp->igu_sb_id); 6054 bnx2x_update_fpsb_idx(fp); 6055 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, 6056 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 6057 bnx2x_sp_mapping(bp, q_rdata), q_type); 6058 6059 /** 6060 * Configure classification DBs: Always enable Tx switching 6061 */ 6062 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 6063 6064 DP(NETIF_MSG_IFUP, 6065 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 6066 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 6067 fp->igu_sb_id); 6068 } 6069 6070 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 6071 { 6072 int i; 6073 6074 for (i = 1; i <= NUM_TX_RINGS; i++) { 6075 struct eth_tx_next_bd *tx_next_bd = 6076 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 6077 6078 tx_next_bd->addr_hi = 6079 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 6080 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6081 tx_next_bd->addr_lo = 6082 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 6083 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6084 } 6085 6086 *txdata->tx_cons_sb = cpu_to_le16(0); 6087 6088 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 6089 txdata->tx_db.data.zero_fill1 = 0; 6090 txdata->tx_db.data.prod = 0; 6091 6092 txdata->tx_pkt_prod = 0; 6093 txdata->tx_pkt_cons = 0; 6094 txdata->tx_bd_prod = 0; 6095 txdata->tx_bd_cons = 0; 6096 txdata->tx_pkt = 0; 6097 } 6098 6099 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) 6100 { 6101 int i; 6102 6103 for_each_tx_queue_cnic(bp, i) 6104 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); 6105 } 6106 6107 static void bnx2x_init_tx_rings(struct bnx2x *bp) 6108 { 6109 int i; 6110 u8 cos; 6111 6112 for_each_eth_queue(bp, i) 6113 for_each_cos_in_tx_queue(&bp->fp[i], cos) 6114 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); 6115 } 6116 6117 void bnx2x_nic_init_cnic(struct bnx2x *bp) 6118 { 6119 if (!NO_FCOE(bp)) 6120 bnx2x_init_fcoe_fp(bp); 6121 6122 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 6123 BNX2X_VF_ID_INVALID, false, 6124 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 6125 6126 /* ensure status block indices were read */ 6127 rmb(); 6128 bnx2x_init_rx_rings_cnic(bp); 6129 bnx2x_init_tx_rings_cnic(bp); 6130 6131 /* flush all */ 6132 mb(); 6133 mmiowb(); 6134 } 6135 6136 void bnx2x_pre_irq_nic_init(struct bnx2x *bp) 6137 { 6138 int i; 6139 6140 /* Setup NIC internals and enable interrupts */ 6141 for_each_eth_queue(bp, i) 6142 bnx2x_init_eth_fp(bp, i); 6143 6144 /* ensure status block indices were read */ 6145 rmb(); 6146 bnx2x_init_rx_rings(bp); 6147 bnx2x_init_tx_rings(bp); 6148 6149 if (IS_PF(bp)) { 6150 /* Initialize MOD_ABS interrupts */ 6151 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 6152 bp->common.shmem_base, 6153 bp->common.shmem2_base, BP_PORT(bp)); 6154 6155 /* initialize the default status block and sp ring */ 6156 bnx2x_init_def_sb(bp); 6157 bnx2x_update_dsb_idx(bp); 6158 bnx2x_init_sp_ring(bp); 6159 } else { 6160 bnx2x_memset_stats(bp); 6161 } 6162 } 6163 6164 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) 6165 { 6166 bnx2x_init_eq_ring(bp); 6167 bnx2x_init_internal(bp, load_code); 6168 bnx2x_pf_init(bp); 6169 bnx2x_stats_init(bp); 6170 6171 /* flush all before enabling interrupts */ 6172 mb(); 6173 mmiowb(); 6174 6175 bnx2x_int_enable(bp); 6176 6177 /* Check for SPIO5 */ 6178 bnx2x_attn_int_deasserted0(bp, 6179 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 6180 AEU_INPUTS_ATTN_BITS_SPIO5); 6181 } 6182 6183 /* gzip service functions */ 6184 static int bnx2x_gunzip_init(struct bnx2x *bp) 6185 { 6186 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 6187 &bp->gunzip_mapping, GFP_KERNEL); 6188 if (bp->gunzip_buf == NULL) 6189 goto gunzip_nomem1; 6190 6191 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 6192 if (bp->strm == NULL) 6193 goto gunzip_nomem2; 6194 6195 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 6196 if (bp->strm->workspace == NULL) 6197 goto gunzip_nomem3; 6198 6199 return 0; 6200 6201 gunzip_nomem3: 6202 kfree(bp->strm); 6203 bp->strm = NULL; 6204 6205 gunzip_nomem2: 6206 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6207 bp->gunzip_mapping); 6208 bp->gunzip_buf = NULL; 6209 6210 gunzip_nomem1: 6211 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 6212 return -ENOMEM; 6213 } 6214 6215 static void bnx2x_gunzip_end(struct bnx2x *bp) 6216 { 6217 if (bp->strm) { 6218 vfree(bp->strm->workspace); 6219 kfree(bp->strm); 6220 bp->strm = NULL; 6221 } 6222 6223 if (bp->gunzip_buf) { 6224 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6225 bp->gunzip_mapping); 6226 bp->gunzip_buf = NULL; 6227 } 6228 } 6229 6230 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 6231 { 6232 int n, rc; 6233 6234 /* check gzip header */ 6235 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 6236 BNX2X_ERR("Bad gzip header\n"); 6237 return -EINVAL; 6238 } 6239 6240 n = 10; 6241 6242 #define FNAME 0x8 6243 6244 if (zbuf[3] & FNAME) 6245 while ((zbuf[n++] != 0) && (n < len)); 6246 6247 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 6248 bp->strm->avail_in = len - n; 6249 bp->strm->next_out = bp->gunzip_buf; 6250 bp->strm->avail_out = FW_BUF_SIZE; 6251 6252 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 6253 if (rc != Z_OK) 6254 return rc; 6255 6256 rc = zlib_inflate(bp->strm, Z_FINISH); 6257 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 6258 netdev_err(bp->dev, "Firmware decompression error: %s\n", 6259 bp->strm->msg); 6260 6261 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 6262 if (bp->gunzip_outlen & 0x3) 6263 netdev_err(bp->dev, 6264 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 6265 bp->gunzip_outlen); 6266 bp->gunzip_outlen >>= 2; 6267 6268 zlib_inflateEnd(bp->strm); 6269 6270 if (rc == Z_STREAM_END) 6271 return 0; 6272 6273 return rc; 6274 } 6275 6276 /* nic load/unload */ 6277 6278 /* 6279 * General service functions 6280 */ 6281 6282 /* send a NIG loopback debug packet */ 6283 static void bnx2x_lb_pckt(struct bnx2x *bp) 6284 { 6285 u32 wb_write[3]; 6286 6287 /* Ethernet source and destination addresses */ 6288 wb_write[0] = 0x55555555; 6289 wb_write[1] = 0x55555555; 6290 wb_write[2] = 0x20; /* SOP */ 6291 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6292 6293 /* NON-IP protocol */ 6294 wb_write[0] = 0x09000000; 6295 wb_write[1] = 0x55555555; 6296 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 6297 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6298 } 6299 6300 /* some of the internal memories 6301 * are not directly readable from the driver 6302 * to test them we send debug packets 6303 */ 6304 static int bnx2x_int_mem_test(struct bnx2x *bp) 6305 { 6306 int factor; 6307 int count, i; 6308 u32 val = 0; 6309 6310 if (CHIP_REV_IS_FPGA(bp)) 6311 factor = 120; 6312 else if (CHIP_REV_IS_EMUL(bp)) 6313 factor = 200; 6314 else 6315 factor = 1; 6316 6317 /* Disable inputs of parser neighbor blocks */ 6318 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6319 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6320 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6321 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6322 6323 /* Write 0 to parser credits for CFC search request */ 6324 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6325 6326 /* send Ethernet packet */ 6327 bnx2x_lb_pckt(bp); 6328 6329 /* TODO do i reset NIG statistic? */ 6330 /* Wait until NIG register shows 1 packet of size 0x10 */ 6331 count = 1000 * factor; 6332 while (count) { 6333 6334 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6335 val = *bnx2x_sp(bp, wb_data[0]); 6336 if (val == 0x10) 6337 break; 6338 6339 usleep_range(10000, 20000); 6340 count--; 6341 } 6342 if (val != 0x10) { 6343 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6344 return -1; 6345 } 6346 6347 /* Wait until PRS register shows 1 packet */ 6348 count = 1000 * factor; 6349 while (count) { 6350 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6351 if (val == 1) 6352 break; 6353 6354 usleep_range(10000, 20000); 6355 count--; 6356 } 6357 if (val != 0x1) { 6358 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6359 return -2; 6360 } 6361 6362 /* Reset and init BRB, PRS */ 6363 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6364 msleep(50); 6365 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6366 msleep(50); 6367 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6368 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6369 6370 DP(NETIF_MSG_HW, "part2\n"); 6371 6372 /* Disable inputs of parser neighbor blocks */ 6373 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6374 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6375 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6376 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6377 6378 /* Write 0 to parser credits for CFC search request */ 6379 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6380 6381 /* send 10 Ethernet packets */ 6382 for (i = 0; i < 10; i++) 6383 bnx2x_lb_pckt(bp); 6384 6385 /* Wait until NIG register shows 10 + 1 6386 packets of size 11*0x10 = 0xb0 */ 6387 count = 1000 * factor; 6388 while (count) { 6389 6390 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6391 val = *bnx2x_sp(bp, wb_data[0]); 6392 if (val == 0xb0) 6393 break; 6394 6395 usleep_range(10000, 20000); 6396 count--; 6397 } 6398 if (val != 0xb0) { 6399 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6400 return -3; 6401 } 6402 6403 /* Wait until PRS register shows 2 packets */ 6404 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6405 if (val != 2) 6406 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6407 6408 /* Write 1 to parser credits for CFC search request */ 6409 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 6410 6411 /* Wait until PRS register shows 3 packets */ 6412 msleep(10 * factor); 6413 /* Wait until NIG register shows 1 packet of size 0x10 */ 6414 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6415 if (val != 3) 6416 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6417 6418 /* clear NIG EOP FIFO */ 6419 for (i = 0; i < 11; i++) 6420 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 6421 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 6422 if (val != 1) { 6423 BNX2X_ERR("clear of NIG failed\n"); 6424 return -4; 6425 } 6426 6427 /* Reset and init BRB, PRS, NIG */ 6428 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6429 msleep(50); 6430 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6431 msleep(50); 6432 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6433 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6434 if (!CNIC_SUPPORT(bp)) 6435 /* set NIC mode */ 6436 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6437 6438 /* Enable inputs of parser neighbor blocks */ 6439 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 6440 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 6441 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 6442 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 6443 6444 DP(NETIF_MSG_HW, "done\n"); 6445 6446 return 0; /* OK */ 6447 } 6448 6449 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 6450 { 6451 u32 val; 6452 6453 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6454 if (!CHIP_IS_E1x(bp)) 6455 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 6456 else 6457 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 6458 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6459 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6460 /* 6461 * mask read length error interrupts in brb for parser 6462 * (parsing unit and 'checksum and crc' unit) 6463 * these errors are legal (PU reads fixed length and CAC can cause 6464 * read length error on truncated packets) 6465 */ 6466 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 6467 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 6468 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 6469 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 6470 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 6471 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 6472 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 6473 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 6474 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 6475 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 6476 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 6477 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 6478 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 6479 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 6480 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 6481 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 6482 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 6483 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 6484 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 6485 6486 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 6487 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 6488 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; 6489 if (!CHIP_IS_E1x(bp)) 6490 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 6491 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; 6492 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); 6493 6494 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 6495 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 6496 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 6497 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 6498 6499 if (!CHIP_IS_E1x(bp)) 6500 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 6501 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 6502 6503 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 6504 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 6505 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 6506 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 6507 } 6508 6509 static void bnx2x_reset_common(struct bnx2x *bp) 6510 { 6511 u32 val = 0x1400; 6512 6513 /* reset_common */ 6514 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6515 0xd3ffff7f); 6516 6517 if (CHIP_IS_E3(bp)) { 6518 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6519 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6520 } 6521 6522 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 6523 } 6524 6525 static void bnx2x_setup_dmae(struct bnx2x *bp) 6526 { 6527 bp->dmae_ready = 0; 6528 spin_lock_init(&bp->dmae_lock); 6529 } 6530 6531 static void bnx2x_init_pxp(struct bnx2x *bp) 6532 { 6533 u16 devctl; 6534 int r_order, w_order; 6535 6536 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); 6537 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 6538 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 6539 if (bp->mrrs == -1) 6540 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 6541 else { 6542 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 6543 r_order = bp->mrrs; 6544 } 6545 6546 bnx2x_init_pxp_arb(bp, r_order, w_order); 6547 } 6548 6549 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 6550 { 6551 int is_required; 6552 u32 val; 6553 int port; 6554 6555 if (BP_NOMCP(bp)) 6556 return; 6557 6558 is_required = 0; 6559 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 6560 SHARED_HW_CFG_FAN_FAILURE_MASK; 6561 6562 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 6563 is_required = 1; 6564 6565 /* 6566 * The fan failure mechanism is usually related to the PHY type since 6567 * the power consumption of the board is affected by the PHY. Currently, 6568 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 6569 */ 6570 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 6571 for (port = PORT_0; port < PORT_MAX; port++) { 6572 is_required |= 6573 bnx2x_fan_failure_det_req( 6574 bp, 6575 bp->common.shmem_base, 6576 bp->common.shmem2_base, 6577 port); 6578 } 6579 6580 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 6581 6582 if (is_required == 0) 6583 return; 6584 6585 /* Fan failure is indicated by SPIO 5 */ 6586 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 6587 6588 /* set to active low mode */ 6589 val = REG_RD(bp, MISC_REG_SPIO_INT); 6590 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 6591 REG_WR(bp, MISC_REG_SPIO_INT, val); 6592 6593 /* enable interrupt to signal the IGU */ 6594 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6595 val |= MISC_SPIO_SPIO5; 6596 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 6597 } 6598 6599 void bnx2x_pf_disable(struct bnx2x *bp) 6600 { 6601 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 6602 val &= ~IGU_PF_CONF_FUNC_EN; 6603 6604 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 6605 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6606 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 6607 } 6608 6609 static void bnx2x__common_init_phy(struct bnx2x *bp) 6610 { 6611 u32 shmem_base[2], shmem2_base[2]; 6612 /* Avoid common init in case MFW supports LFA */ 6613 if (SHMEM2_RD(bp, size) > 6614 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 6615 return; 6616 shmem_base[0] = bp->common.shmem_base; 6617 shmem2_base[0] = bp->common.shmem2_base; 6618 if (!CHIP_IS_E1x(bp)) { 6619 shmem_base[1] = 6620 SHMEM2_RD(bp, other_shmem_base_addr); 6621 shmem2_base[1] = 6622 SHMEM2_RD(bp, other_shmem2_base_addr); 6623 } 6624 bnx2x_acquire_phy_lock(bp); 6625 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 6626 bp->common.chip_id); 6627 bnx2x_release_phy_lock(bp); 6628 } 6629 6630 /** 6631 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 6632 * 6633 * @bp: driver handle 6634 */ 6635 static int bnx2x_init_hw_common(struct bnx2x *bp) 6636 { 6637 u32 val; 6638 6639 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); 6640 6641 /* 6642 * take the RESET lock to protect undi_unload flow from accessing 6643 * registers while we're resetting the chip 6644 */ 6645 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6646 6647 bnx2x_reset_common(bp); 6648 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6649 6650 val = 0xfffc; 6651 if (CHIP_IS_E3(bp)) { 6652 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6653 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6654 } 6655 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6656 6657 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6658 6659 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6660 6661 if (!CHIP_IS_E1x(bp)) { 6662 u8 abs_func_id; 6663 6664 /** 6665 * 4-port mode or 2-port mode we need to turn of master-enable 6666 * for everyone, after that, turn it back on for self. 6667 * so, we disregard multi-function or not, and always disable 6668 * for all functions on the given path, this means 0,2,4,6 for 6669 * path 0 and 1,3,5,7 for path 1 6670 */ 6671 for (abs_func_id = BP_PATH(bp); 6672 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6673 if (abs_func_id == BP_ABS_FUNC(bp)) { 6674 REG_WR(bp, 6675 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6676 1); 6677 continue; 6678 } 6679 6680 bnx2x_pretend_func(bp, abs_func_id); 6681 /* clear pf enable */ 6682 bnx2x_pf_disable(bp); 6683 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6684 } 6685 } 6686 6687 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6688 if (CHIP_IS_E1(bp)) { 6689 /* enable HW interrupt from PXP on USDM overflow 6690 bit 16 on INT_MASK_0 */ 6691 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6692 } 6693 6694 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6695 bnx2x_init_pxp(bp); 6696 6697 #ifdef __BIG_ENDIAN 6698 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6699 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6700 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6701 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6702 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6703 /* make sure this value is 0 */ 6704 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6705 6706 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6707 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6708 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6709 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6710 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6711 #endif 6712 6713 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6714 6715 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6716 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6717 6718 /* let the HW do it's magic ... */ 6719 msleep(100); 6720 /* finish PXP init */ 6721 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6722 if (val != 1) { 6723 BNX2X_ERR("PXP2 CFG failed\n"); 6724 return -EBUSY; 6725 } 6726 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6727 if (val != 1) { 6728 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6729 return -EBUSY; 6730 } 6731 6732 /* Timers bug workaround E2 only. We need to set the entire ILT to 6733 * have entries with value "0" and valid bit on. 6734 * This needs to be done by the first PF that is loaded in a path 6735 * (i.e. common phase) 6736 */ 6737 if (!CHIP_IS_E1x(bp)) { 6738 /* In E2 there is a bug in the timers block that can cause function 6 / 7 6739 * (i.e. vnic3) to start even if it is marked as "scan-off". 6740 * This occurs when a different function (func2,3) is being marked 6741 * as "scan-off". Real-life scenario for example: if a driver is being 6742 * load-unloaded while func6,7 are down. This will cause the timer to access 6743 * the ilt, translate to a logical address and send a request to read/write. 6744 * Since the ilt for the function that is down is not valid, this will cause 6745 * a translation error which is unrecoverable. 6746 * The Workaround is intended to make sure that when this happens nothing fatal 6747 * will occur. The workaround: 6748 * 1. First PF driver which loads on a path will: 6749 * a. After taking the chip out of reset, by using pretend, 6750 * it will write "0" to the following registers of 6751 * the other vnics. 6752 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6753 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6754 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6755 * And for itself it will write '1' to 6756 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6757 * dmae-operations (writing to pram for example.) 6758 * note: can be done for only function 6,7 but cleaner this 6759 * way. 6760 * b. Write zero+valid to the entire ILT. 6761 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6762 * VNIC3 (of that port). The range allocated will be the 6763 * entire ILT. This is needed to prevent ILT range error. 6764 * 2. Any PF driver load flow: 6765 * a. ILT update with the physical addresses of the allocated 6766 * logical pages. 6767 * b. Wait 20msec. - note that this timeout is needed to make 6768 * sure there are no requests in one of the PXP internal 6769 * queues with "old" ILT addresses. 6770 * c. PF enable in the PGLC. 6771 * d. Clear the was_error of the PF in the PGLC. (could have 6772 * occurred while driver was down) 6773 * e. PF enable in the CFC (WEAK + STRONG) 6774 * f. Timers scan enable 6775 * 3. PF driver unload flow: 6776 * a. Clear the Timers scan_en. 6777 * b. Polling for scan_on=0 for that PF. 6778 * c. Clear the PF enable bit in the PXP. 6779 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6780 * e. Write zero+valid to all ILT entries (The valid bit must 6781 * stay set) 6782 * f. If this is VNIC 3 of a port then also init 6783 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6784 * to the last entry in the ILT. 6785 * 6786 * Notes: 6787 * Currently the PF error in the PGLC is non recoverable. 6788 * In the future the there will be a recovery routine for this error. 6789 * Currently attention is masked. 6790 * Having an MCP lock on the load/unload process does not guarantee that 6791 * there is no Timer disable during Func6/7 enable. This is because the 6792 * Timers scan is currently being cleared by the MCP on FLR. 6793 * Step 2.d can be done only for PF6/7 and the driver can also check if 6794 * there is error before clearing it. But the flow above is simpler and 6795 * more general. 6796 * All ILT entries are written by zero+valid and not just PF6/7 6797 * ILT entries since in the future the ILT entries allocation for 6798 * PF-s might be dynamic. 6799 */ 6800 struct ilt_client_info ilt_cli; 6801 struct bnx2x_ilt ilt; 6802 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6803 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6804 6805 /* initialize dummy TM client */ 6806 ilt_cli.start = 0; 6807 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6808 ilt_cli.client_num = ILT_CLIENT_TM; 6809 6810 /* Step 1: set zeroes to all ilt page entries with valid bit on 6811 * Step 2: set the timers first/last ilt entry to point 6812 * to the entire range to prevent ILT range error for 3rd/4th 6813 * vnic (this code assumes existence of the vnic) 6814 * 6815 * both steps performed by call to bnx2x_ilt_client_init_op() 6816 * with dummy TM client 6817 * 6818 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6819 * and his brother are split registers 6820 */ 6821 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6822 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6823 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6824 6825 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6826 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6827 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6828 } 6829 6830 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6831 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6832 6833 if (!CHIP_IS_E1x(bp)) { 6834 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6835 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6836 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6837 6838 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6839 6840 /* let the HW do it's magic ... */ 6841 do { 6842 msleep(200); 6843 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6844 } while (factor-- && (val != 1)); 6845 6846 if (val != 1) { 6847 BNX2X_ERR("ATC_INIT failed\n"); 6848 return -EBUSY; 6849 } 6850 } 6851 6852 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6853 6854 bnx2x_iov_init_dmae(bp); 6855 6856 /* clean the DMAE memory */ 6857 bp->dmae_ready = 1; 6858 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6859 6860 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6861 6862 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6863 6864 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6865 6866 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6867 6868 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6869 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6870 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6871 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6872 6873 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6874 6875 /* QM queues pointers table */ 6876 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6877 6878 /* soft reset pulse */ 6879 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6880 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6881 6882 if (CNIC_SUPPORT(bp)) 6883 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6884 6885 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6886 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6887 if (!CHIP_REV_IS_SLOW(bp)) 6888 /* enable hw interrupt from doorbell Q */ 6889 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6890 6891 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6892 6893 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6894 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6895 6896 if (!CHIP_IS_E1(bp)) 6897 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6898 6899 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { 6900 if (IS_MF_AFEX(bp)) { 6901 /* configure that VNTag and VLAN headers must be 6902 * received in afex mode 6903 */ 6904 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); 6905 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); 6906 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 6907 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 6908 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); 6909 } else { 6910 /* Bit-map indicating which L2 hdrs may appear 6911 * after the basic Ethernet header 6912 */ 6913 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6914 bp->path_has_ovlan ? 7 : 6); 6915 } 6916 } 6917 6918 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6919 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6920 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6921 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6922 6923 if (!CHIP_IS_E1x(bp)) { 6924 /* reset VFC memories */ 6925 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6926 VFC_MEMORIES_RST_REG_CAM_RST | 6927 VFC_MEMORIES_RST_REG_RAM_RST); 6928 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6929 VFC_MEMORIES_RST_REG_CAM_RST | 6930 VFC_MEMORIES_RST_REG_RAM_RST); 6931 6932 msleep(20); 6933 } 6934 6935 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6936 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6937 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6938 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6939 6940 /* sync semi rtc */ 6941 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6942 0x80000000); 6943 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6944 0x80000000); 6945 6946 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6947 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6948 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6949 6950 if (!CHIP_IS_E1x(bp)) { 6951 if (IS_MF_AFEX(bp)) { 6952 /* configure that VNTag and VLAN headers must be 6953 * sent in afex mode 6954 */ 6955 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); 6956 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); 6957 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 6958 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 6959 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); 6960 } else { 6961 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6962 bp->path_has_ovlan ? 7 : 6); 6963 } 6964 } 6965 6966 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6967 6968 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6969 6970 if (CNIC_SUPPORT(bp)) { 6971 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6972 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6973 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6974 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6975 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6976 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6977 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6978 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6979 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6980 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6981 } 6982 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6983 6984 if (sizeof(union cdu_context) != 1024) 6985 /* we currently assume that a context is 1024 bytes */ 6986 dev_alert(&bp->pdev->dev, 6987 "please adjust the size of cdu_context(%ld)\n", 6988 (long)sizeof(union cdu_context)); 6989 6990 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6991 val = (4 << 24) + (0 << 12) + 1024; 6992 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6993 6994 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6995 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6996 /* enable context validation interrupt from CFC */ 6997 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6998 6999 /* set the thresholds to prevent CFC/CDU race */ 7000 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 7001 7002 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 7003 7004 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 7005 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 7006 7007 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 7008 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 7009 7010 /* Reset PCIE errors for debug */ 7011 REG_WR(bp, 0x2814, 0xffffffff); 7012 REG_WR(bp, 0x3820, 0xffffffff); 7013 7014 if (!CHIP_IS_E1x(bp)) { 7015 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 7016 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 7017 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 7018 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 7019 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 7020 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 7021 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 7022 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 7023 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 7024 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 7025 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 7026 } 7027 7028 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 7029 if (!CHIP_IS_E1(bp)) { 7030 /* in E3 this done in per-port section */ 7031 if (!CHIP_IS_E3(bp)) 7032 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7033 } 7034 if (CHIP_IS_E1H(bp)) 7035 /* not applicable for E2 (and above ...) */ 7036 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 7037 7038 if (CHIP_REV_IS_SLOW(bp)) 7039 msleep(200); 7040 7041 /* finish CFC init */ 7042 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 7043 if (val != 1) { 7044 BNX2X_ERR("CFC LL_INIT failed\n"); 7045 return -EBUSY; 7046 } 7047 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 7048 if (val != 1) { 7049 BNX2X_ERR("CFC AC_INIT failed\n"); 7050 return -EBUSY; 7051 } 7052 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 7053 if (val != 1) { 7054 BNX2X_ERR("CFC CAM_INIT failed\n"); 7055 return -EBUSY; 7056 } 7057 REG_WR(bp, CFC_REG_DEBUG0, 0); 7058 7059 if (CHIP_IS_E1(bp)) { 7060 /* read NIG statistic 7061 to see if this is our first up since powerup */ 7062 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 7063 val = *bnx2x_sp(bp, wb_data[0]); 7064 7065 /* do internal memory self test */ 7066 if ((val == 0) && bnx2x_int_mem_test(bp)) { 7067 BNX2X_ERR("internal mem self test failed\n"); 7068 return -EBUSY; 7069 } 7070 } 7071 7072 bnx2x_setup_fan_failure_detection(bp); 7073 7074 /* clear PXP2 attentions */ 7075 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 7076 7077 bnx2x_enable_blocks_attention(bp); 7078 bnx2x_enable_blocks_parity(bp); 7079 7080 if (!BP_NOMCP(bp)) { 7081 if (CHIP_IS_E1x(bp)) 7082 bnx2x__common_init_phy(bp); 7083 } else 7084 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 7085 7086 return 0; 7087 } 7088 7089 /** 7090 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 7091 * 7092 * @bp: driver handle 7093 */ 7094 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 7095 { 7096 int rc = bnx2x_init_hw_common(bp); 7097 7098 if (rc) 7099 return rc; 7100 7101 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 7102 if (!BP_NOMCP(bp)) 7103 bnx2x__common_init_phy(bp); 7104 7105 return 0; 7106 } 7107 7108 static int bnx2x_init_hw_port(struct bnx2x *bp) 7109 { 7110 int port = BP_PORT(bp); 7111 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 7112 u32 low, high; 7113 u32 val; 7114 7115 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 7116 7117 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7118 7119 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 7120 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7121 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7122 7123 /* Timers bug workaround: disables the pf_master bit in pglue at 7124 * common phase, we need to enable it here before any dmae access are 7125 * attempted. Therefore we manually added the enable-master to the 7126 * port phase (it also happens in the function phase) 7127 */ 7128 if (!CHIP_IS_E1x(bp)) 7129 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 7130 7131 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 7132 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 7133 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 7134 bnx2x_init_block(bp, BLOCK_QM, init_phase); 7135 7136 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 7137 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 7138 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 7139 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 7140 7141 /* QM cid (connection) count */ 7142 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 7143 7144 if (CNIC_SUPPORT(bp)) { 7145 bnx2x_init_block(bp, BLOCK_TM, init_phase); 7146 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 7147 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 7148 } 7149 7150 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 7151 7152 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 7153 7154 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 7155 7156 if (IS_MF(bp)) 7157 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 7158 else if (bp->dev->mtu > 4096) { 7159 if (bp->flags & ONE_PORT_FLAG) 7160 low = 160; 7161 else { 7162 val = bp->dev->mtu; 7163 /* (24*1024 + val*4)/256 */ 7164 low = 96 + (val/64) + 7165 ((val % 64) ? 1 : 0); 7166 } 7167 } else 7168 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 7169 high = low + 56; /* 14*1024/256 */ 7170 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 7171 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 7172 } 7173 7174 if (CHIP_MODE_IS_4_PORT(bp)) 7175 REG_WR(bp, (BP_PORT(bp) ? 7176 BRB1_REG_MAC_GUARANTIED_1 : 7177 BRB1_REG_MAC_GUARANTIED_0), 40); 7178 7179 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 7180 if (CHIP_IS_E3B0(bp)) { 7181 if (IS_MF_AFEX(bp)) { 7182 /* configure headers for AFEX mode */ 7183 REG_WR(bp, BP_PORT(bp) ? 7184 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7185 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 7186 REG_WR(bp, BP_PORT(bp) ? 7187 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 7188 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 7189 REG_WR(bp, BP_PORT(bp) ? 7190 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 7191 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 7192 } else { 7193 /* Ovlan exists only if we are in multi-function + 7194 * switch-dependent mode, in switch-independent there 7195 * is no ovlan headers 7196 */ 7197 REG_WR(bp, BP_PORT(bp) ? 7198 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7199 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 7200 (bp->path_has_ovlan ? 7 : 6)); 7201 } 7202 } 7203 7204 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 7205 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 7206 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 7207 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 7208 7209 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 7210 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 7211 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 7212 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 7213 7214 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 7215 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 7216 7217 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 7218 7219 if (CHIP_IS_E1x(bp)) { 7220 /* configure PBF to work without PAUSE mtu 9000 */ 7221 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 7222 7223 /* update threshold */ 7224 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 7225 /* update init credit */ 7226 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 7227 7228 /* probe changes */ 7229 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 7230 udelay(50); 7231 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 7232 } 7233 7234 if (CNIC_SUPPORT(bp)) 7235 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 7236 7237 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 7238 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 7239 7240 if (CHIP_IS_E1(bp)) { 7241 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7242 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7243 } 7244 bnx2x_init_block(bp, BLOCK_HC, init_phase); 7245 7246 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 7247 7248 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 7249 /* init aeu_mask_attn_func_0/1: 7250 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use 7251 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF 7252 * bits 4-7 are used for "per vn group attention" */ 7253 val = IS_MF(bp) ? 0xF7 : 0x7; 7254 /* Enable DCBX attention for all but E1 */ 7255 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 7256 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 7257 7258 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7259 7260 if (!CHIP_IS_E1x(bp)) { 7261 /* Bit-map indicating which L2 hdrs may appear after the 7262 * basic Ethernet header 7263 */ 7264 if (IS_MF_AFEX(bp)) 7265 REG_WR(bp, BP_PORT(bp) ? 7266 NIG_REG_P1_HDRS_AFTER_BASIC : 7267 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 7268 else 7269 REG_WR(bp, BP_PORT(bp) ? 7270 NIG_REG_P1_HDRS_AFTER_BASIC : 7271 NIG_REG_P0_HDRS_AFTER_BASIC, 7272 IS_MF_SD(bp) ? 7 : 6); 7273 7274 if (CHIP_IS_E3(bp)) 7275 REG_WR(bp, BP_PORT(bp) ? 7276 NIG_REG_LLH1_MF_MODE : 7277 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7278 } 7279 if (!CHIP_IS_E3(bp)) 7280 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 7281 7282 if (!CHIP_IS_E1(bp)) { 7283 /* 0x2 disable mf_ov, 0x1 enable */ 7284 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 7285 (IS_MF_SD(bp) ? 0x1 : 0x2)); 7286 7287 if (!CHIP_IS_E1x(bp)) { 7288 val = 0; 7289 switch (bp->mf_mode) { 7290 case MULTI_FUNCTION_SD: 7291 val = 1; 7292 break; 7293 case MULTI_FUNCTION_SI: 7294 case MULTI_FUNCTION_AFEX: 7295 val = 2; 7296 break; 7297 } 7298 7299 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 7300 NIG_REG_LLH0_CLS_TYPE), val); 7301 } 7302 { 7303 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 7304 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 7305 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 7306 } 7307 } 7308 7309 /* If SPIO5 is set to generate interrupts, enable it for this port */ 7310 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 7311 if (val & MISC_SPIO_SPIO5) { 7312 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 7313 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 7314 val = REG_RD(bp, reg_addr); 7315 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 7316 REG_WR(bp, reg_addr, val); 7317 } 7318 7319 return 0; 7320 } 7321 7322 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 7323 { 7324 int reg; 7325 u32 wb_write[2]; 7326 7327 if (CHIP_IS_E1(bp)) 7328 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 7329 else 7330 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 7331 7332 wb_write[0] = ONCHIP_ADDR1(addr); 7333 wb_write[1] = ONCHIP_ADDR2(addr); 7334 REG_WR_DMAE(bp, reg, wb_write, 2); 7335 } 7336 7337 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) 7338 { 7339 u32 data, ctl, cnt = 100; 7340 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 7341 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 7342 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 7343 u32 sb_bit = 1 << (idu_sb_id%32); 7344 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 7345 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 7346 7347 /* Not supported in BC mode */ 7348 if (CHIP_INT_MODE_IS_BC(bp)) 7349 return; 7350 7351 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 7352 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 7353 IGU_REGULAR_CLEANUP_SET | 7354 IGU_REGULAR_BCLEANUP; 7355 7356 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 7357 func_encode << IGU_CTRL_REG_FID_SHIFT | 7358 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 7359 7360 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7361 data, igu_addr_data); 7362 REG_WR(bp, igu_addr_data, data); 7363 mmiowb(); 7364 barrier(); 7365 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7366 ctl, igu_addr_ctl); 7367 REG_WR(bp, igu_addr_ctl, ctl); 7368 mmiowb(); 7369 barrier(); 7370 7371 /* wait for clean up to finish */ 7372 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) 7373 msleep(20); 7374 7375 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 7376 DP(NETIF_MSG_HW, 7377 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", 7378 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 7379 } 7380 } 7381 7382 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 7383 { 7384 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 7385 } 7386 7387 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 7388 { 7389 u32 i, base = FUNC_ILT_BASE(func); 7390 for (i = base; i < base + ILT_PER_FUNC; i++) 7391 bnx2x_ilt_wr(bp, i, 0); 7392 } 7393 7394 static void bnx2x_init_searcher(struct bnx2x *bp) 7395 { 7396 int port = BP_PORT(bp); 7397 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 7398 /* T1 hash bits value determines the T1 number of entries */ 7399 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 7400 } 7401 7402 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) 7403 { 7404 int rc; 7405 struct bnx2x_func_state_params func_params = {NULL}; 7406 struct bnx2x_func_switch_update_params *switch_update_params = 7407 &func_params.params.switch_update; 7408 7409 /* Prepare parameters for function state transitions */ 7410 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7411 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 7412 7413 func_params.f_obj = &bp->func_obj; 7414 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 7415 7416 /* Function parameters */ 7417 switch_update_params->suspend = suspend; 7418 7419 rc = bnx2x_func_state_change(bp, &func_params); 7420 7421 return rc; 7422 } 7423 7424 static int bnx2x_reset_nic_mode(struct bnx2x *bp) 7425 { 7426 int rc, i, port = BP_PORT(bp); 7427 int vlan_en = 0, mac_en[NUM_MACS]; 7428 7429 /* Close input from network */ 7430 if (bp->mf_mode == SINGLE_FUNCTION) { 7431 bnx2x_set_rx_filter(&bp->link_params, 0); 7432 } else { 7433 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : 7434 NIG_REG_LLH0_FUNC_EN); 7435 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7436 NIG_REG_LLH0_FUNC_EN, 0); 7437 for (i = 0; i < NUM_MACS; i++) { 7438 mac_en[i] = REG_RD(bp, port ? 7439 (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7440 4 * i) : 7441 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 7442 4 * i)); 7443 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7444 4 * i) : 7445 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); 7446 } 7447 } 7448 7449 /* Close BMC to host */ 7450 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7451 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); 7452 7453 /* Suspend Tx switching to the PF. Completion of this ramrod 7454 * further guarantees that all the packets of that PF / child 7455 * VFs in BRB were processed by the Parser, so it is safe to 7456 * change the NIC_MODE register. 7457 */ 7458 rc = bnx2x_func_switch_update(bp, 1); 7459 if (rc) { 7460 BNX2X_ERR("Can't suspend tx-switching!\n"); 7461 return rc; 7462 } 7463 7464 /* Change NIC_MODE register */ 7465 REG_WR(bp, PRS_REG_NIC_MODE, 0); 7466 7467 /* Open input from network */ 7468 if (bp->mf_mode == SINGLE_FUNCTION) { 7469 bnx2x_set_rx_filter(&bp->link_params, 1); 7470 } else { 7471 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7472 NIG_REG_LLH0_FUNC_EN, vlan_en); 7473 for (i = 0; i < NUM_MACS; i++) { 7474 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7475 4 * i) : 7476 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 7477 mac_en[i]); 7478 } 7479 } 7480 7481 /* Enable BMC to host */ 7482 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7483 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); 7484 7485 /* Resume Tx switching to the PF */ 7486 rc = bnx2x_func_switch_update(bp, 0); 7487 if (rc) { 7488 BNX2X_ERR("Can't resume tx-switching!\n"); 7489 return rc; 7490 } 7491 7492 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 7493 return 0; 7494 } 7495 7496 int bnx2x_init_hw_func_cnic(struct bnx2x *bp) 7497 { 7498 int rc; 7499 7500 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); 7501 7502 if (CONFIGURE_NIC_MODE(bp)) { 7503 /* Configure searcher as part of function hw init */ 7504 bnx2x_init_searcher(bp); 7505 7506 /* Reset NIC mode */ 7507 rc = bnx2x_reset_nic_mode(bp); 7508 if (rc) 7509 BNX2X_ERR("Can't change NIC mode!\n"); 7510 return rc; 7511 } 7512 7513 return 0; 7514 } 7515 7516 static int bnx2x_init_hw_func(struct bnx2x *bp) 7517 { 7518 int port = BP_PORT(bp); 7519 int func = BP_FUNC(bp); 7520 int init_phase = PHASE_PF0 + func; 7521 struct bnx2x_ilt *ilt = BP_ILT(bp); 7522 u16 cdu_ilt_start; 7523 u32 addr, val; 7524 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 7525 int i, main_mem_width, rc; 7526 7527 DP(NETIF_MSG_HW, "starting func init func %d\n", func); 7528 7529 /* FLR cleanup - hmmm */ 7530 if (!CHIP_IS_E1x(bp)) { 7531 rc = bnx2x_pf_flr_clnup(bp); 7532 if (rc) { 7533 bnx2x_fw_dump(bp); 7534 return rc; 7535 } 7536 } 7537 7538 /* set MSI reconfigure capability */ 7539 if (bp->common.int_block == INT_BLOCK_HC) { 7540 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 7541 val = REG_RD(bp, addr); 7542 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 7543 REG_WR(bp, addr, val); 7544 } 7545 7546 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7547 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7548 7549 ilt = BP_ILT(bp); 7550 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7551 7552 if (IS_SRIOV(bp)) 7553 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; 7554 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); 7555 7556 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes 7557 * those of the VFs, so start line should be reset 7558 */ 7559 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7560 for (i = 0; i < L2_ILT_LINES(bp); i++) { 7561 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; 7562 ilt->lines[cdu_ilt_start + i].page_mapping = 7563 bp->context[i].cxt_mapping; 7564 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; 7565 } 7566 7567 bnx2x_ilt_init_op(bp, INITOP_SET); 7568 7569 if (!CONFIGURE_NIC_MODE(bp)) { 7570 bnx2x_init_searcher(bp); 7571 REG_WR(bp, PRS_REG_NIC_MODE, 0); 7572 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 7573 } else { 7574 /* Set NIC mode */ 7575 REG_WR(bp, PRS_REG_NIC_MODE, 1); 7576 DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); 7577 } 7578 7579 if (!CHIP_IS_E1x(bp)) { 7580 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 7581 7582 /* Turn on a single ISR mode in IGU if driver is going to use 7583 * INT#x or MSI 7584 */ 7585 if (!(bp->flags & USING_MSIX_FLAG)) 7586 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 7587 /* 7588 * Timers workaround bug: function init part. 7589 * Need to wait 20msec after initializing ILT, 7590 * needed to make sure there are no requests in 7591 * one of the PXP internal queues with "old" ILT addresses 7592 */ 7593 msleep(20); 7594 /* 7595 * Master enable - Due to WB DMAE writes performed before this 7596 * register is re-initialized as part of the regular function 7597 * init 7598 */ 7599 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 7600 /* Enable the function in IGU */ 7601 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 7602 } 7603 7604 bp->dmae_ready = 1; 7605 7606 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 7607 7608 if (!CHIP_IS_E1x(bp)) 7609 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 7610 7611 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 7612 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 7613 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7614 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 7615 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 7616 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 7617 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 7618 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 7619 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 7620 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 7621 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 7622 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 7623 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 7624 7625 if (!CHIP_IS_E1x(bp)) 7626 REG_WR(bp, QM_REG_PF_EN, 1); 7627 7628 if (!CHIP_IS_E1x(bp)) { 7629 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7630 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7631 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7632 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 7633 } 7634 bnx2x_init_block(bp, BLOCK_QM, init_phase); 7635 7636 bnx2x_init_block(bp, BLOCK_TM, init_phase); 7637 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 7638 7639 bnx2x_iov_init_dq(bp); 7640 7641 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 7642 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 7643 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 7644 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 7645 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 7646 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 7647 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 7648 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 7649 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 7650 if (!CHIP_IS_E1x(bp)) 7651 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 7652 7653 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 7654 7655 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 7656 7657 if (!CHIP_IS_E1x(bp)) 7658 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 7659 7660 if (IS_MF(bp)) { 7661 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 7662 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 7663 } 7664 7665 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 7666 7667 /* HC init per function */ 7668 if (bp->common.int_block == INT_BLOCK_HC) { 7669 if (CHIP_IS_E1H(bp)) { 7670 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 7671 7672 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7673 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7674 } 7675 bnx2x_init_block(bp, BLOCK_HC, init_phase); 7676 7677 } else { 7678 int num_segs, sb_idx, prod_offset; 7679 7680 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 7681 7682 if (!CHIP_IS_E1x(bp)) { 7683 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7684 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7685 } 7686 7687 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 7688 7689 if (!CHIP_IS_E1x(bp)) { 7690 int dsb_idx = 0; 7691 /** 7692 * Producer memory: 7693 * E2 mode: address 0-135 match to the mapping memory; 7694 * 136 - PF0 default prod; 137 - PF1 default prod; 7695 * 138 - PF2 default prod; 139 - PF3 default prod; 7696 * 140 - PF0 attn prod; 141 - PF1 attn prod; 7697 * 142 - PF2 attn prod; 143 - PF3 attn prod; 7698 * 144-147 reserved. 7699 * 7700 * E1.5 mode - In backward compatible mode; 7701 * for non default SB; each even line in the memory 7702 * holds the U producer and each odd line hold 7703 * the C producer. The first 128 producers are for 7704 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 7705 * producers are for the DSB for each PF. 7706 * Each PF has five segments: (the order inside each 7707 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 7708 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 7709 * 144-147 attn prods; 7710 */ 7711 /* non-default-status-blocks */ 7712 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 7713 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 7714 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 7715 prod_offset = (bp->igu_base_sb + sb_idx) * 7716 num_segs; 7717 7718 for (i = 0; i < num_segs; i++) { 7719 addr = IGU_REG_PROD_CONS_MEMORY + 7720 (prod_offset + i) * 4; 7721 REG_WR(bp, addr, 0); 7722 } 7723 /* send consumer update with value 0 */ 7724 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 7725 USTORM_ID, 0, IGU_INT_NOP, 1); 7726 bnx2x_igu_clear_sb(bp, 7727 bp->igu_base_sb + sb_idx); 7728 } 7729 7730 /* default-status-blocks */ 7731 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 7732 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 7733 7734 if (CHIP_MODE_IS_4_PORT(bp)) 7735 dsb_idx = BP_FUNC(bp); 7736 else 7737 dsb_idx = BP_VN(bp); 7738 7739 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 7740 IGU_BC_BASE_DSB_PROD + dsb_idx : 7741 IGU_NORM_BASE_DSB_PROD + dsb_idx); 7742 7743 /* 7744 * igu prods come in chunks of E1HVN_MAX (4) - 7745 * does not matters what is the current chip mode 7746 */ 7747 for (i = 0; i < (num_segs * E1HVN_MAX); 7748 i += E1HVN_MAX) { 7749 addr = IGU_REG_PROD_CONS_MEMORY + 7750 (prod_offset + i)*4; 7751 REG_WR(bp, addr, 0); 7752 } 7753 /* send consumer update with 0 */ 7754 if (CHIP_INT_MODE_IS_BC(bp)) { 7755 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7756 USTORM_ID, 0, IGU_INT_NOP, 1); 7757 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7758 CSTORM_ID, 0, IGU_INT_NOP, 1); 7759 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7760 XSTORM_ID, 0, IGU_INT_NOP, 1); 7761 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7762 TSTORM_ID, 0, IGU_INT_NOP, 1); 7763 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7764 ATTENTION_ID, 0, IGU_INT_NOP, 1); 7765 } else { 7766 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7767 USTORM_ID, 0, IGU_INT_NOP, 1); 7768 bnx2x_ack_sb(bp, bp->igu_dsb_id, 7769 ATTENTION_ID, 0, IGU_INT_NOP, 1); 7770 } 7771 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 7772 7773 /* !!! These should become driver const once 7774 rf-tool supports split-68 const */ 7775 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 7776 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 7777 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 7778 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 7779 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 7780 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 7781 } 7782 } 7783 7784 /* Reset PCIE errors for debug */ 7785 REG_WR(bp, 0x2114, 0xffffffff); 7786 REG_WR(bp, 0x2120, 0xffffffff); 7787 7788 if (CHIP_IS_E1x(bp)) { 7789 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 7790 main_mem_base = HC_REG_MAIN_MEMORY + 7791 BP_PORT(bp) * (main_mem_size * 4); 7792 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 7793 main_mem_width = 8; 7794 7795 val = REG_RD(bp, main_mem_prty_clr); 7796 if (val) 7797 DP(NETIF_MSG_HW, 7798 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", 7799 val); 7800 7801 /* Clear "false" parity errors in MSI-X table */ 7802 for (i = main_mem_base; 7803 i < main_mem_base + main_mem_size * 4; 7804 i += main_mem_width) { 7805 bnx2x_read_dmae(bp, i, main_mem_width / 4); 7806 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 7807 i, main_mem_width / 4); 7808 } 7809 /* Clear HC parity attention */ 7810 REG_RD(bp, main_mem_prty_clr); 7811 } 7812 7813 #ifdef BNX2X_STOP_ON_ERROR 7814 /* Enable STORMs SP logging */ 7815 REG_WR8(bp, BAR_USTRORM_INTMEM + 7816 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7817 REG_WR8(bp, BAR_TSTRORM_INTMEM + 7818 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7819 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7820 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7821 REG_WR8(bp, BAR_XSTRORM_INTMEM + 7822 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 7823 #endif 7824 7825 bnx2x_phy_probe(&bp->link_params); 7826 7827 return 0; 7828 } 7829 7830 void bnx2x_free_mem_cnic(struct bnx2x *bp) 7831 { 7832 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); 7833 7834 if (!CHIP_IS_E1x(bp)) 7835 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 7836 sizeof(struct host_hc_status_block_e2)); 7837 else 7838 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 7839 sizeof(struct host_hc_status_block_e1x)); 7840 7841 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7842 } 7843 7844 void bnx2x_free_mem(struct bnx2x *bp) 7845 { 7846 int i; 7847 7848 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 7849 sizeof(struct host_sp_status_block)); 7850 7851 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7852 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7853 7854 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 7855 sizeof(struct bnx2x_slowpath)); 7856 7857 for (i = 0; i < L2_ILT_LINES(bp); i++) 7858 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, 7859 bp->context[i].size); 7860 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 7861 7862 BNX2X_FREE(bp->ilt->lines); 7863 7864 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 7865 7866 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7867 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7868 7869 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 7870 7871 bnx2x_iov_free_mem(bp); 7872 } 7873 7874 int bnx2x_alloc_mem_cnic(struct bnx2x *bp) 7875 { 7876 if (!CHIP_IS_E1x(bp)) 7877 /* size = the status block + ramrod buffers */ 7878 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7879 sizeof(struct host_hc_status_block_e2)); 7880 else 7881 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, 7882 &bp->cnic_sb_mapping, 7883 sizeof(struct 7884 host_hc_status_block_e1x)); 7885 7886 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) 7887 /* allocate searcher T2 table, as it wasn't allocated before */ 7888 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7889 7890 /* write address to which L5 should insert its values */ 7891 bp->cnic_eth_dev.addr_drv_info_to_mcp = 7892 &bp->slowpath->drv_info_to_mcp; 7893 7894 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) 7895 goto alloc_mem_err; 7896 7897 return 0; 7898 7899 alloc_mem_err: 7900 bnx2x_free_mem_cnic(bp); 7901 BNX2X_ERR("Can't allocate memory\n"); 7902 return -ENOMEM; 7903 } 7904 7905 int bnx2x_alloc_mem(struct bnx2x *bp) 7906 { 7907 int i, allocated, context_size; 7908 7909 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) 7910 /* allocate searcher T2 table */ 7911 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7912 7913 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7914 sizeof(struct host_sp_status_block)); 7915 7916 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7917 sizeof(struct bnx2x_slowpath)); 7918 7919 /* Allocate memory for CDU context: 7920 * This memory is allocated separately and not in the generic ILT 7921 * functions because CDU differs in few aspects: 7922 * 1. There are multiple entities allocating memory for context - 7923 * 'regular' driver, CNIC and SRIOV driver. Each separately controls 7924 * its own ILT lines. 7925 * 2. Since CDU page-size is not a single 4KB page (which is the case 7926 * for the other ILT clients), to be efficient we want to support 7927 * allocation of sub-page-size in the last entry. 7928 * 3. Context pointers are used by the driver to pass to FW / update 7929 * the context (for the other ILT clients the pointers are used just to 7930 * free the memory during unload). 7931 */ 7932 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7933 7934 for (i = 0, allocated = 0; allocated < context_size; i++) { 7935 bp->context[i].size = min(CDU_ILT_PAGE_SZ, 7936 (context_size - allocated)); 7937 BNX2X_PCI_ALLOC(bp->context[i].vcxt, 7938 &bp->context[i].cxt_mapping, 7939 bp->context[i].size); 7940 allocated += bp->context[i].size; 7941 } 7942 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7943 7944 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7945 goto alloc_mem_err; 7946 7947 if (bnx2x_iov_alloc_mem(bp)) 7948 goto alloc_mem_err; 7949 7950 /* Slow path ring */ 7951 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7952 7953 /* EQ */ 7954 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7955 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7956 7957 return 0; 7958 7959 alloc_mem_err: 7960 bnx2x_free_mem(bp); 7961 BNX2X_ERR("Can't allocate memory\n"); 7962 return -ENOMEM; 7963 } 7964 7965 /* 7966 * Init service functions 7967 */ 7968 7969 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7970 struct bnx2x_vlan_mac_obj *obj, bool set, 7971 int mac_type, unsigned long *ramrod_flags) 7972 { 7973 int rc; 7974 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7975 7976 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7977 7978 /* Fill general parameters */ 7979 ramrod_param.vlan_mac_obj = obj; 7980 ramrod_param.ramrod_flags = *ramrod_flags; 7981 7982 /* Fill a user request section if needed */ 7983 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7984 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7985 7986 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7987 7988 /* Set the command: ADD or DEL */ 7989 if (set) 7990 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7991 else 7992 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7993 } 7994 7995 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7996 7997 if (rc == -EEXIST) { 7998 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 7999 /* do not treat adding same MAC as error */ 8000 rc = 0; 8001 } else if (rc < 0) 8002 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 8003 8004 return rc; 8005 } 8006 8007 int bnx2x_del_all_macs(struct bnx2x *bp, 8008 struct bnx2x_vlan_mac_obj *mac_obj, 8009 int mac_type, bool wait_for_comp) 8010 { 8011 int rc; 8012 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 8013 8014 /* Wait for completion of requested */ 8015 if (wait_for_comp) 8016 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8017 8018 /* Set the mac type of addresses we want to clear */ 8019 __set_bit(mac_type, &vlan_mac_flags); 8020 8021 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 8022 if (rc < 0) 8023 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 8024 8025 return rc; 8026 } 8027 8028 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 8029 { 8030 if (is_zero_ether_addr(bp->dev->dev_addr) && 8031 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { 8032 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, 8033 "Ignoring Zero MAC for STORAGE SD mode\n"); 8034 return 0; 8035 } 8036 8037 if (IS_PF(bp)) { 8038 unsigned long ramrod_flags = 0; 8039 8040 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 8041 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8042 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, 8043 &bp->sp_objs->mac_obj, set, 8044 BNX2X_ETH_MAC, &ramrod_flags); 8045 } else { /* vf */ 8046 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, 8047 bp->fp->index, true); 8048 } 8049 } 8050 8051 int bnx2x_setup_leading(struct bnx2x *bp) 8052 { 8053 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 8054 } 8055 8056 /** 8057 * bnx2x_set_int_mode - configure interrupt mode 8058 * 8059 * @bp: driver handle 8060 * 8061 * In case of MSI-X it will also try to enable MSI-X. 8062 */ 8063 int bnx2x_set_int_mode(struct bnx2x *bp) 8064 { 8065 int rc = 0; 8066 8067 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) 8068 return -EINVAL; 8069 8070 switch (int_mode) { 8071 case BNX2X_INT_MODE_MSIX: 8072 /* attempt to enable msix */ 8073 rc = bnx2x_enable_msix(bp); 8074 8075 /* msix attained */ 8076 if (!rc) 8077 return 0; 8078 8079 /* vfs use only msix */ 8080 if (rc && IS_VF(bp)) 8081 return rc; 8082 8083 /* failed to enable multiple MSI-X */ 8084 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", 8085 bp->num_queues, 8086 1 + bp->num_cnic_queues); 8087 8088 /* falling through... */ 8089 case BNX2X_INT_MODE_MSI: 8090 bnx2x_enable_msi(bp); 8091 8092 /* falling through... */ 8093 case BNX2X_INT_MODE_INTX: 8094 bp->num_ethernet_queues = 1; 8095 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 8096 BNX2X_DEV_INFO("set number of queues to 1\n"); 8097 break; 8098 default: 8099 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); 8100 return -EINVAL; 8101 } 8102 return 0; 8103 } 8104 8105 /* must be called prior to any HW initializations */ 8106 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 8107 { 8108 if (IS_SRIOV(bp)) 8109 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; 8110 return L2_ILT_LINES(bp); 8111 } 8112 8113 void bnx2x_ilt_set_info(struct bnx2x *bp) 8114 { 8115 struct ilt_client_info *ilt_client; 8116 struct bnx2x_ilt *ilt = BP_ILT(bp); 8117 u16 line = 0; 8118 8119 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 8120 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 8121 8122 /* CDU */ 8123 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 8124 ilt_client->client_num = ILT_CLIENT_CDU; 8125 ilt_client->page_size = CDU_ILT_PAGE_SZ; 8126 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 8127 ilt_client->start = line; 8128 line += bnx2x_cid_ilt_lines(bp); 8129 8130 if (CNIC_SUPPORT(bp)) 8131 line += CNIC_ILT_LINES; 8132 ilt_client->end = line - 1; 8133 8134 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8135 ilt_client->start, 8136 ilt_client->end, 8137 ilt_client->page_size, 8138 ilt_client->flags, 8139 ilog2(ilt_client->page_size >> 12)); 8140 8141 /* QM */ 8142 if (QM_INIT(bp->qm_cid_count)) { 8143 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 8144 ilt_client->client_num = ILT_CLIENT_QM; 8145 ilt_client->page_size = QM_ILT_PAGE_SZ; 8146 ilt_client->flags = 0; 8147 ilt_client->start = line; 8148 8149 /* 4 bytes for each cid */ 8150 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 8151 QM_ILT_PAGE_SZ); 8152 8153 ilt_client->end = line - 1; 8154 8155 DP(NETIF_MSG_IFUP, 8156 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8157 ilt_client->start, 8158 ilt_client->end, 8159 ilt_client->page_size, 8160 ilt_client->flags, 8161 ilog2(ilt_client->page_size >> 12)); 8162 } 8163 8164 if (CNIC_SUPPORT(bp)) { 8165 /* SRC */ 8166 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 8167 ilt_client->client_num = ILT_CLIENT_SRC; 8168 ilt_client->page_size = SRC_ILT_PAGE_SZ; 8169 ilt_client->flags = 0; 8170 ilt_client->start = line; 8171 line += SRC_ILT_LINES; 8172 ilt_client->end = line - 1; 8173 8174 DP(NETIF_MSG_IFUP, 8175 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8176 ilt_client->start, 8177 ilt_client->end, 8178 ilt_client->page_size, 8179 ilt_client->flags, 8180 ilog2(ilt_client->page_size >> 12)); 8181 8182 /* TM */ 8183 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 8184 ilt_client->client_num = ILT_CLIENT_TM; 8185 ilt_client->page_size = TM_ILT_PAGE_SZ; 8186 ilt_client->flags = 0; 8187 ilt_client->start = line; 8188 line += TM_ILT_LINES; 8189 ilt_client->end = line - 1; 8190 8191 DP(NETIF_MSG_IFUP, 8192 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8193 ilt_client->start, 8194 ilt_client->end, 8195 ilt_client->page_size, 8196 ilt_client->flags, 8197 ilog2(ilt_client->page_size >> 12)); 8198 } 8199 8200 BUG_ON(line > ILT_MAX_LINES); 8201 } 8202 8203 /** 8204 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 8205 * 8206 * @bp: driver handle 8207 * @fp: pointer to fastpath 8208 * @init_params: pointer to parameters structure 8209 * 8210 * parameters configured: 8211 * - HC configuration 8212 * - Queue's CDU context 8213 */ 8214 static void bnx2x_pf_q_prep_init(struct bnx2x *bp, 8215 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 8216 { 8217 u8 cos; 8218 int cxt_index, cxt_offset; 8219 8220 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 8221 if (!IS_FCOE_FP(fp)) { 8222 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 8223 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 8224 8225 /* If HC is supported, enable host coalescing in the transition 8226 * to INIT state. 8227 */ 8228 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 8229 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 8230 8231 /* HC rate */ 8232 init_params->rx.hc_rate = bp->rx_ticks ? 8233 (1000000 / bp->rx_ticks) : 0; 8234 init_params->tx.hc_rate = bp->tx_ticks ? 8235 (1000000 / bp->tx_ticks) : 0; 8236 8237 /* FW SB ID */ 8238 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 8239 fp->fw_sb_id; 8240 8241 /* 8242 * CQ index among the SB indices: FCoE clients uses the default 8243 * SB, therefore it's different. 8244 */ 8245 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 8246 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 8247 } 8248 8249 /* set maximum number of COSs supported by this queue */ 8250 init_params->max_cos = fp->max_cos; 8251 8252 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", 8253 fp->index, init_params->max_cos); 8254 8255 /* set the context pointers queue object */ 8256 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 8257 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; 8258 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * 8259 ILT_PAGE_CIDS); 8260 init_params->cxts[cos] = 8261 &bp->context[cxt_index].vcxt[cxt_offset].eth; 8262 } 8263 } 8264 8265 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8266 struct bnx2x_queue_state_params *q_params, 8267 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 8268 int tx_index, bool leading) 8269 { 8270 memset(tx_only_params, 0, sizeof(*tx_only_params)); 8271 8272 /* Set the command */ 8273 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 8274 8275 /* Set tx-only QUEUE flags: don't zero statistics */ 8276 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 8277 8278 /* choose the index of the cid to send the slow path on */ 8279 tx_only_params->cid_index = tx_index; 8280 8281 /* Set general TX_ONLY_SETUP parameters */ 8282 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 8283 8284 /* Set Tx TX_ONLY_SETUP parameters */ 8285 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 8286 8287 DP(NETIF_MSG_IFUP, 8288 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", 8289 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 8290 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 8291 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 8292 8293 /* send the ramrod */ 8294 return bnx2x_queue_state_change(bp, q_params); 8295 } 8296 8297 /** 8298 * bnx2x_setup_queue - setup queue 8299 * 8300 * @bp: driver handle 8301 * @fp: pointer to fastpath 8302 * @leading: is leading 8303 * 8304 * This function performs 2 steps in a Queue state machine 8305 * actually: 1) RESET->INIT 2) INIT->SETUP 8306 */ 8307 8308 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8309 bool leading) 8310 { 8311 struct bnx2x_queue_state_params q_params = {NULL}; 8312 struct bnx2x_queue_setup_params *setup_params = 8313 &q_params.params.setup; 8314 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 8315 &q_params.params.tx_only; 8316 int rc; 8317 u8 tx_index; 8318 8319 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); 8320 8321 /* reset IGU state skip FCoE L2 queue */ 8322 if (!IS_FCOE_FP(fp)) 8323 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 8324 IGU_INT_ENABLE, 0); 8325 8326 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8327 /* We want to wait for completion in this context */ 8328 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8329 8330 /* Prepare the INIT parameters */ 8331 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 8332 8333 /* Set the command */ 8334 q_params.cmd = BNX2X_Q_CMD_INIT; 8335 8336 /* Change the state to INIT */ 8337 rc = bnx2x_queue_state_change(bp, &q_params); 8338 if (rc) { 8339 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 8340 return rc; 8341 } 8342 8343 DP(NETIF_MSG_IFUP, "init complete\n"); 8344 8345 /* Now move the Queue to the SETUP state... */ 8346 memset(setup_params, 0, sizeof(*setup_params)); 8347 8348 /* Set QUEUE flags */ 8349 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 8350 8351 /* Set general SETUP parameters */ 8352 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 8353 FIRST_TX_COS_INDEX); 8354 8355 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 8356 &setup_params->rxq_params); 8357 8358 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 8359 FIRST_TX_COS_INDEX); 8360 8361 /* Set the command */ 8362 q_params.cmd = BNX2X_Q_CMD_SETUP; 8363 8364 if (IS_FCOE_FP(fp)) 8365 bp->fcoe_init = true; 8366 8367 /* Change the state to SETUP */ 8368 rc = bnx2x_queue_state_change(bp, &q_params); 8369 if (rc) { 8370 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 8371 return rc; 8372 } 8373 8374 /* loop through the relevant tx-only indices */ 8375 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8376 tx_index < fp->max_cos; 8377 tx_index++) { 8378 8379 /* prepare and send tx-only ramrod*/ 8380 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 8381 tx_only_params, tx_index, leading); 8382 if (rc) { 8383 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 8384 fp->index, tx_index); 8385 return rc; 8386 } 8387 } 8388 8389 return rc; 8390 } 8391 8392 static int bnx2x_stop_queue(struct bnx2x *bp, int index) 8393 { 8394 struct bnx2x_fastpath *fp = &bp->fp[index]; 8395 struct bnx2x_fp_txdata *txdata; 8396 struct bnx2x_queue_state_params q_params = {NULL}; 8397 int rc, tx_index; 8398 8399 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); 8400 8401 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8402 /* We want to wait for completion in this context */ 8403 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8404 8405 /* close tx-only connections */ 8406 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8407 tx_index < fp->max_cos; 8408 tx_index++){ 8409 8410 /* ascertain this is a normal queue*/ 8411 txdata = fp->txdata_ptr[tx_index]; 8412 8413 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", 8414 txdata->txq_index); 8415 8416 /* send halt terminate on tx-only connection */ 8417 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8418 memset(&q_params.params.terminate, 0, 8419 sizeof(q_params.params.terminate)); 8420 q_params.params.terminate.cid_index = tx_index; 8421 8422 rc = bnx2x_queue_state_change(bp, &q_params); 8423 if (rc) 8424 return rc; 8425 8426 /* send halt terminate on tx-only connection */ 8427 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8428 memset(&q_params.params.cfc_del, 0, 8429 sizeof(q_params.params.cfc_del)); 8430 q_params.params.cfc_del.cid_index = tx_index; 8431 rc = bnx2x_queue_state_change(bp, &q_params); 8432 if (rc) 8433 return rc; 8434 } 8435 /* Stop the primary connection: */ 8436 /* ...halt the connection */ 8437 q_params.cmd = BNX2X_Q_CMD_HALT; 8438 rc = bnx2x_queue_state_change(bp, &q_params); 8439 if (rc) 8440 return rc; 8441 8442 /* ...terminate the connection */ 8443 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8444 memset(&q_params.params.terminate, 0, 8445 sizeof(q_params.params.terminate)); 8446 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 8447 rc = bnx2x_queue_state_change(bp, &q_params); 8448 if (rc) 8449 return rc; 8450 /* ...delete cfc entry */ 8451 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8452 memset(&q_params.params.cfc_del, 0, 8453 sizeof(q_params.params.cfc_del)); 8454 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 8455 return bnx2x_queue_state_change(bp, &q_params); 8456 } 8457 8458 static void bnx2x_reset_func(struct bnx2x *bp) 8459 { 8460 int port = BP_PORT(bp); 8461 int func = BP_FUNC(bp); 8462 int i; 8463 8464 /* Disable the function in the FW */ 8465 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 8466 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 8467 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 8468 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 8469 8470 /* FP SBs */ 8471 for_each_eth_queue(bp, i) { 8472 struct bnx2x_fastpath *fp = &bp->fp[i]; 8473 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8474 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 8475 SB_DISABLED); 8476 } 8477 8478 if (CNIC_LOADED(bp)) 8479 /* CNIC SB */ 8480 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8481 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET 8482 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); 8483 8484 /* SP SB */ 8485 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8486 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 8487 SB_DISABLED); 8488 8489 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 8490 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 8491 0); 8492 8493 /* Configure IGU */ 8494 if (bp->common.int_block == INT_BLOCK_HC) { 8495 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 8496 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 8497 } else { 8498 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 8499 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 8500 } 8501 8502 if (CNIC_LOADED(bp)) { 8503 /* Disable Timer scan */ 8504 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 8505 /* 8506 * Wait for at least 10ms and up to 2 second for the timers 8507 * scan to complete 8508 */ 8509 for (i = 0; i < 200; i++) { 8510 usleep_range(10000, 20000); 8511 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 8512 break; 8513 } 8514 } 8515 /* Clear ILT */ 8516 bnx2x_clear_func_ilt(bp, func); 8517 8518 /* Timers workaround bug for E2: if this is vnic-3, 8519 * we need to set the entire ilt range for this timers. 8520 */ 8521 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 8522 struct ilt_client_info ilt_cli; 8523 /* use dummy TM client */ 8524 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 8525 ilt_cli.start = 0; 8526 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 8527 ilt_cli.client_num = ILT_CLIENT_TM; 8528 8529 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 8530 } 8531 8532 /* this assumes that reset_port() called before reset_func()*/ 8533 if (!CHIP_IS_E1x(bp)) 8534 bnx2x_pf_disable(bp); 8535 8536 bp->dmae_ready = 0; 8537 } 8538 8539 static void bnx2x_reset_port(struct bnx2x *bp) 8540 { 8541 int port = BP_PORT(bp); 8542 u32 val; 8543 8544 /* Reset physical Link */ 8545 bnx2x__link_reset(bp); 8546 8547 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 8548 8549 /* Do not rcv packets to BRB */ 8550 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 8551 /* Do not direct rcv packets that are not for MCP to the BRB */ 8552 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8553 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8554 8555 /* Configure AEU */ 8556 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 8557 8558 msleep(100); 8559 /* Check for BRB port occupancy */ 8560 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 8561 if (val) 8562 DP(NETIF_MSG_IFDOWN, 8563 "BRB1 is not empty %d blocks are occupied\n", val); 8564 8565 /* TODO: Close Doorbell port? */ 8566 } 8567 8568 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 8569 { 8570 struct bnx2x_func_state_params func_params = {NULL}; 8571 8572 /* Prepare parameters for function state transitions */ 8573 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 8574 8575 func_params.f_obj = &bp->func_obj; 8576 func_params.cmd = BNX2X_F_CMD_HW_RESET; 8577 8578 func_params.params.hw_init.load_phase = load_code; 8579 8580 return bnx2x_func_state_change(bp, &func_params); 8581 } 8582 8583 static int bnx2x_func_stop(struct bnx2x *bp) 8584 { 8585 struct bnx2x_func_state_params func_params = {NULL}; 8586 int rc; 8587 8588 /* Prepare parameters for function state transitions */ 8589 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 8590 func_params.f_obj = &bp->func_obj; 8591 func_params.cmd = BNX2X_F_CMD_STOP; 8592 8593 /* 8594 * Try to stop the function the 'good way'. If fails (in case 8595 * of a parity error during bnx2x_chip_cleanup()) and we are 8596 * not in a debug mode, perform a state transaction in order to 8597 * enable further HW_RESET transaction. 8598 */ 8599 rc = bnx2x_func_state_change(bp, &func_params); 8600 if (rc) { 8601 #ifdef BNX2X_STOP_ON_ERROR 8602 return rc; 8603 #else 8604 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); 8605 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 8606 return bnx2x_func_state_change(bp, &func_params); 8607 #endif 8608 } 8609 8610 return 0; 8611 } 8612 8613 /** 8614 * bnx2x_send_unload_req - request unload mode from the MCP. 8615 * 8616 * @bp: driver handle 8617 * @unload_mode: requested function's unload mode 8618 * 8619 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 8620 */ 8621 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 8622 { 8623 u32 reset_code = 0; 8624 int port = BP_PORT(bp); 8625 8626 /* Select the UNLOAD request mode */ 8627 if (unload_mode == UNLOAD_NORMAL) 8628 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8629 8630 else if (bp->flags & NO_WOL_FLAG) 8631 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 8632 8633 else if (bp->wol) { 8634 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 8635 u8 *mac_addr = bp->dev->dev_addr; 8636 u32 val; 8637 u16 pmc; 8638 8639 /* The mac address is written to entries 1-4 to 8640 * preserve entry 0 which is used by the PMF 8641 */ 8642 u8 entry = (BP_VN(bp) + 1)*8; 8643 8644 val = (mac_addr[0] << 8) | mac_addr[1]; 8645 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 8646 8647 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 8648 (mac_addr[4] << 8) | mac_addr[5]; 8649 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 8650 8651 /* Enable the PME and clear the status */ 8652 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 8653 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 8654 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 8655 8656 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 8657 8658 } else 8659 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8660 8661 /* Send the request to the MCP */ 8662 if (!BP_NOMCP(bp)) 8663 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8664 else { 8665 int path = BP_PATH(bp); 8666 8667 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", 8668 path, load_count[path][0], load_count[path][1], 8669 load_count[path][2]); 8670 load_count[path][0]--; 8671 load_count[path][1 + port]--; 8672 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", 8673 path, load_count[path][0], load_count[path][1], 8674 load_count[path][2]); 8675 if (load_count[path][0] == 0) 8676 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 8677 else if (load_count[path][1 + port] == 0) 8678 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 8679 else 8680 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 8681 } 8682 8683 return reset_code; 8684 } 8685 8686 /** 8687 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 8688 * 8689 * @bp: driver handle 8690 * @keep_link: true iff link should be kept up 8691 */ 8692 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) 8693 { 8694 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 8695 8696 /* Report UNLOAD_DONE to MCP */ 8697 if (!BP_NOMCP(bp)) 8698 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 8699 } 8700 8701 static int bnx2x_func_wait_started(struct bnx2x *bp) 8702 { 8703 int tout = 50; 8704 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 8705 8706 if (!bp->port.pmf) 8707 return 0; 8708 8709 /* 8710 * (assumption: No Attention from MCP at this stage) 8711 * PMF probably in the middle of TX disable/enable transaction 8712 * 1. Sync IRS for default SB 8713 * 2. Sync SP queue - this guarantees us that attention handling started 8714 * 3. Wait, that TX disable/enable transaction completes 8715 * 8716 * 1+2 guarantee that if DCBx attention was scheduled it already changed 8717 * pending bit of transaction from STARTED-->TX_STOPPED, if we already 8718 * received completion for the transaction the state is TX_STOPPED. 8719 * State will return to STARTED after completion of TX_STOPPED-->STARTED 8720 * transaction. 8721 */ 8722 8723 /* make sure default SB ISR is done */ 8724 if (msix) 8725 synchronize_irq(bp->msix_table[0].vector); 8726 else 8727 synchronize_irq(bp->pdev->irq); 8728 8729 flush_workqueue(bnx2x_wq); 8730 8731 while (bnx2x_func_get_state(bp, &bp->func_obj) != 8732 BNX2X_F_STATE_STARTED && tout--) 8733 msleep(20); 8734 8735 if (bnx2x_func_get_state(bp, &bp->func_obj) != 8736 BNX2X_F_STATE_STARTED) { 8737 #ifdef BNX2X_STOP_ON_ERROR 8738 BNX2X_ERR("Wrong function state\n"); 8739 return -EBUSY; 8740 #else 8741 /* 8742 * Failed to complete the transaction in a "good way" 8743 * Force both transactions with CLR bit 8744 */ 8745 struct bnx2x_func_state_params func_params = {NULL}; 8746 8747 DP(NETIF_MSG_IFDOWN, 8748 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 8749 8750 func_params.f_obj = &bp->func_obj; 8751 __set_bit(RAMROD_DRV_CLR_ONLY, 8752 &func_params.ramrod_flags); 8753 8754 /* STARTED-->TX_ST0PPED */ 8755 func_params.cmd = BNX2X_F_CMD_TX_STOP; 8756 bnx2x_func_state_change(bp, &func_params); 8757 8758 /* TX_ST0PPED-->STARTED */ 8759 func_params.cmd = BNX2X_F_CMD_TX_START; 8760 return bnx2x_func_state_change(bp, &func_params); 8761 #endif 8762 } 8763 8764 return 0; 8765 } 8766 8767 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) 8768 { 8769 int port = BP_PORT(bp); 8770 int i, rc = 0; 8771 u8 cos; 8772 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 8773 u32 reset_code; 8774 8775 /* Wait until tx fastpath tasks complete */ 8776 for_each_tx_queue(bp, i) { 8777 struct bnx2x_fastpath *fp = &bp->fp[i]; 8778 8779 for_each_cos_in_tx_queue(fp, cos) 8780 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); 8781 #ifdef BNX2X_STOP_ON_ERROR 8782 if (rc) 8783 return; 8784 #endif 8785 } 8786 8787 /* Give HW time to discard old tx messages */ 8788 usleep_range(1000, 2000); 8789 8790 /* Clean all ETH MACs */ 8791 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, 8792 false); 8793 if (rc < 0) 8794 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 8795 8796 /* Clean up UC list */ 8797 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, 8798 true); 8799 if (rc < 0) 8800 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", 8801 rc); 8802 8803 /* Disable LLH */ 8804 if (!CHIP_IS_E1(bp)) 8805 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 8806 8807 /* Set "drop all" (stop Rx). 8808 * We need to take a netif_addr_lock() here in order to prevent 8809 * a race between the completion code and this code. 8810 */ 8811 netif_addr_lock_bh(bp->dev); 8812 /* Schedule the rx_mode command */ 8813 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 8814 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 8815 else 8816 bnx2x_set_storm_rx_mode(bp); 8817 8818 /* Cleanup multicast configuration */ 8819 rparam.mcast_obj = &bp->mcast_obj; 8820 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 8821 if (rc < 0) 8822 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 8823 8824 netif_addr_unlock_bh(bp->dev); 8825 8826 bnx2x_iov_chip_cleanup(bp); 8827 8828 /* 8829 * Send the UNLOAD_REQUEST to the MCP. This will return if 8830 * this function should perform FUNC, PORT or COMMON HW 8831 * reset. 8832 */ 8833 reset_code = bnx2x_send_unload_req(bp, unload_mode); 8834 8835 /* 8836 * (assumption: No Attention from MCP at this stage) 8837 * PMF probably in the middle of TX disable/enable transaction 8838 */ 8839 rc = bnx2x_func_wait_started(bp); 8840 if (rc) { 8841 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 8842 #ifdef BNX2X_STOP_ON_ERROR 8843 return; 8844 #endif 8845 } 8846 8847 /* Close multi and leading connections 8848 * Completions for ramrods are collected in a synchronous way 8849 */ 8850 for_each_eth_queue(bp, i) 8851 if (bnx2x_stop_queue(bp, i)) 8852 #ifdef BNX2X_STOP_ON_ERROR 8853 return; 8854 #else 8855 goto unload_error; 8856 #endif 8857 8858 if (CNIC_LOADED(bp)) { 8859 for_each_cnic_queue(bp, i) 8860 if (bnx2x_stop_queue(bp, i)) 8861 #ifdef BNX2X_STOP_ON_ERROR 8862 return; 8863 #else 8864 goto unload_error; 8865 #endif 8866 } 8867 8868 /* If SP settings didn't get completed so far - something 8869 * very wrong has happen. 8870 */ 8871 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8872 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8873 8874 #ifndef BNX2X_STOP_ON_ERROR 8875 unload_error: 8876 #endif 8877 rc = bnx2x_func_stop(bp); 8878 if (rc) { 8879 BNX2X_ERR("Function stop failed!\n"); 8880 #ifdef BNX2X_STOP_ON_ERROR 8881 return; 8882 #endif 8883 } 8884 8885 /* Disable HW interrupts, NAPI */ 8886 bnx2x_netif_stop(bp, 1); 8887 /* Delete all NAPI objects */ 8888 bnx2x_del_all_napi(bp); 8889 if (CNIC_LOADED(bp)) 8890 bnx2x_del_all_napi_cnic(bp); 8891 8892 /* Release IRQs */ 8893 bnx2x_free_irq(bp); 8894 8895 /* Reset the chip */ 8896 rc = bnx2x_reset_hw(bp, reset_code); 8897 if (rc) 8898 BNX2X_ERR("HW_RESET failed\n"); 8899 8900 /* Report UNLOAD_DONE to MCP */ 8901 bnx2x_send_unload_done(bp, keep_link); 8902 } 8903 8904 void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8905 { 8906 u32 val; 8907 8908 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); 8909 8910 if (CHIP_IS_E1(bp)) { 8911 int port = BP_PORT(bp); 8912 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8913 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8914 8915 val = REG_RD(bp, addr); 8916 val &= ~(0x300); 8917 REG_WR(bp, addr, val); 8918 } else { 8919 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8920 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8921 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8922 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8923 } 8924 } 8925 8926 /* Close gates #2, #3 and #4: */ 8927 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8928 { 8929 u32 val; 8930 8931 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8932 if (!CHIP_IS_E1(bp)) { 8933 /* #4 */ 8934 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8935 /* #2 */ 8936 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8937 } 8938 8939 /* #3 */ 8940 if (CHIP_IS_E1x(bp)) { 8941 /* Prevent interrupts from HC on both ports */ 8942 val = REG_RD(bp, HC_REG_CONFIG_1); 8943 REG_WR(bp, HC_REG_CONFIG_1, 8944 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8945 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8946 8947 val = REG_RD(bp, HC_REG_CONFIG_0); 8948 REG_WR(bp, HC_REG_CONFIG_0, 8949 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8950 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8951 } else { 8952 /* Prevent incoming interrupts in IGU */ 8953 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8954 8955 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8956 (!close) ? 8957 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8958 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8959 } 8960 8961 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", 8962 close ? "closing" : "opening"); 8963 mmiowb(); 8964 } 8965 8966 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8967 8968 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8969 { 8970 /* Do some magic... */ 8971 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8972 *magic_val = val & SHARED_MF_CLP_MAGIC; 8973 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8974 } 8975 8976 /** 8977 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8978 * 8979 * @bp: driver handle 8980 * @magic_val: old value of the `magic' bit. 8981 */ 8982 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8983 { 8984 /* Restore the `magic' bit value... */ 8985 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8986 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8987 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8988 } 8989 8990 /** 8991 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8992 * 8993 * @bp: driver handle 8994 * @magic_val: old value of 'magic' bit. 8995 * 8996 * Takes care of CLP configurations. 8997 */ 8998 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8999 { 9000 u32 shmem; 9001 u32 validity_offset; 9002 9003 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); 9004 9005 /* Set `magic' bit in order to save MF config */ 9006 if (!CHIP_IS_E1(bp)) 9007 bnx2x_clp_reset_prep(bp, magic_val); 9008 9009 /* Get shmem offset */ 9010 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9011 validity_offset = 9012 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); 9013 9014 /* Clear validity map flags */ 9015 if (shmem > 0) 9016 REG_WR(bp, shmem + validity_offset, 0); 9017 } 9018 9019 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 9020 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 9021 9022 /** 9023 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 9024 * 9025 * @bp: driver handle 9026 */ 9027 static void bnx2x_mcp_wait_one(struct bnx2x *bp) 9028 { 9029 /* special handling for emulation and FPGA, 9030 wait 10 times longer */ 9031 if (CHIP_REV_IS_SLOW(bp)) 9032 msleep(MCP_ONE_TIMEOUT*10); 9033 else 9034 msleep(MCP_ONE_TIMEOUT); 9035 } 9036 9037 /* 9038 * initializes bp->common.shmem_base and waits for validity signature to appear 9039 */ 9040 static int bnx2x_init_shmem(struct bnx2x *bp) 9041 { 9042 int cnt = 0; 9043 u32 val = 0; 9044 9045 do { 9046 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9047 if (bp->common.shmem_base) { 9048 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 9049 if (val & SHR_MEM_VALIDITY_MB) 9050 return 0; 9051 } 9052 9053 bnx2x_mcp_wait_one(bp); 9054 9055 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 9056 9057 BNX2X_ERR("BAD MCP validity signature\n"); 9058 9059 return -ENODEV; 9060 } 9061 9062 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 9063 { 9064 int rc = bnx2x_init_shmem(bp); 9065 9066 /* Restore the `magic' bit value */ 9067 if (!CHIP_IS_E1(bp)) 9068 bnx2x_clp_reset_done(bp, magic_val); 9069 9070 return rc; 9071 } 9072 9073 static void bnx2x_pxp_prep(struct bnx2x *bp) 9074 { 9075 if (!CHIP_IS_E1(bp)) { 9076 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 9077 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 9078 mmiowb(); 9079 } 9080 } 9081 9082 /* 9083 * Reset the whole chip except for: 9084 * - PCIE core 9085 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 9086 * one reset bit) 9087 * - IGU 9088 * - MISC (including AEU) 9089 * - GRC 9090 * - RBCN, RBCP 9091 */ 9092 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 9093 { 9094 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 9095 u32 global_bits2, stay_reset2; 9096 9097 /* 9098 * Bits that have to be set in reset_mask2 if we want to reset 'global' 9099 * (per chip) blocks. 9100 */ 9101 global_bits2 = 9102 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 9103 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 9104 9105 /* Don't reset the following blocks. 9106 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 9107 * reset, as in 4 port device they might still be owned 9108 * by the MCP (there is only one leader per path). 9109 */ 9110 not_reset_mask1 = 9111 MISC_REGISTERS_RESET_REG_1_RST_HC | 9112 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 9113 MISC_REGISTERS_RESET_REG_1_RST_PXP; 9114 9115 not_reset_mask2 = 9116 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 9117 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 9118 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 9119 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 9120 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 9121 MISC_REGISTERS_RESET_REG_2_RST_GRC | 9122 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 9123 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 9124 MISC_REGISTERS_RESET_REG_2_RST_ATC | 9125 MISC_REGISTERS_RESET_REG_2_PGLC | 9126 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 9127 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 9128 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 9129 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 9130 MISC_REGISTERS_RESET_REG_2_UMAC0 | 9131 MISC_REGISTERS_RESET_REG_2_UMAC1; 9132 9133 /* 9134 * Keep the following blocks in reset: 9135 * - all xxMACs are handled by the bnx2x_link code. 9136 */ 9137 stay_reset2 = 9138 MISC_REGISTERS_RESET_REG_2_XMAC | 9139 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 9140 9141 /* Full reset masks according to the chip */ 9142 reset_mask1 = 0xffffffff; 9143 9144 if (CHIP_IS_E1(bp)) 9145 reset_mask2 = 0xffff; 9146 else if (CHIP_IS_E1H(bp)) 9147 reset_mask2 = 0x1ffff; 9148 else if (CHIP_IS_E2(bp)) 9149 reset_mask2 = 0xfffff; 9150 else /* CHIP_IS_E3 */ 9151 reset_mask2 = 0x3ffffff; 9152 9153 /* Don't reset global blocks unless we need to */ 9154 if (!global) 9155 reset_mask2 &= ~global_bits2; 9156 9157 /* 9158 * In case of attention in the QM, we need to reset PXP 9159 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 9160 * because otherwise QM reset would release 'close the gates' shortly 9161 * before resetting the PXP, then the PSWRQ would send a write 9162 * request to PGLUE. Then when PXP is reset, PGLUE would try to 9163 * read the payload data from PSWWR, but PSWWR would not 9164 * respond. The write queue in PGLUE would stuck, dmae commands 9165 * would not return. Therefore it's important to reset the second 9166 * reset register (containing the 9167 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 9168 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 9169 * bit). 9170 */ 9171 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 9172 reset_mask2 & (~not_reset_mask2)); 9173 9174 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 9175 reset_mask1 & (~not_reset_mask1)); 9176 9177 barrier(); 9178 mmiowb(); 9179 9180 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 9181 reset_mask2 & (~stay_reset2)); 9182 9183 barrier(); 9184 mmiowb(); 9185 9186 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 9187 mmiowb(); 9188 } 9189 9190 /** 9191 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 9192 * It should get cleared in no more than 1s. 9193 * 9194 * @bp: driver handle 9195 * 9196 * It should get cleared in no more than 1s. Returns 0 if 9197 * pending writes bit gets cleared. 9198 */ 9199 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 9200 { 9201 u32 cnt = 1000; 9202 u32 pend_bits = 0; 9203 9204 do { 9205 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 9206 9207 if (pend_bits == 0) 9208 break; 9209 9210 usleep_range(1000, 2000); 9211 } while (cnt-- > 0); 9212 9213 if (cnt <= 0) { 9214 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 9215 pend_bits); 9216 return -EBUSY; 9217 } 9218 9219 return 0; 9220 } 9221 9222 static int bnx2x_process_kill(struct bnx2x *bp, bool global) 9223 { 9224 int cnt = 1000; 9225 u32 val = 0; 9226 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 9227 u32 tags_63_32 = 0; 9228 9229 /* Empty the Tetris buffer, wait for 1s */ 9230 do { 9231 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 9232 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 9233 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 9234 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 9235 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 9236 if (CHIP_IS_E3(bp)) 9237 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); 9238 9239 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 9240 ((port_is_idle_0 & 0x1) == 0x1) && 9241 ((port_is_idle_1 & 0x1) == 0x1) && 9242 (pgl_exp_rom2 == 0xffffffff) && 9243 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) 9244 break; 9245 usleep_range(1000, 2000); 9246 } while (cnt-- > 0); 9247 9248 if (cnt <= 0) { 9249 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); 9250 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 9251 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 9252 pgl_exp_rom2); 9253 return -EAGAIN; 9254 } 9255 9256 barrier(); 9257 9258 /* Close gates #2, #3 and #4 */ 9259 bnx2x_set_234_gates(bp, true); 9260 9261 /* Poll for IGU VQs for 57712 and newer chips */ 9262 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 9263 return -EAGAIN; 9264 9265 /* TBD: Indicate that "process kill" is in progress to MCP */ 9266 9267 /* Clear "unprepared" bit */ 9268 REG_WR(bp, MISC_REG_UNPREPARED, 0); 9269 barrier(); 9270 9271 /* Make sure all is written to the chip before the reset */ 9272 mmiowb(); 9273 9274 /* Wait for 1ms to empty GLUE and PCI-E core queues, 9275 * PSWHST, GRC and PSWRD Tetris buffer. 9276 */ 9277 usleep_range(1000, 2000); 9278 9279 /* Prepare to chip reset: */ 9280 /* MCP */ 9281 if (global) 9282 bnx2x_reset_mcp_prep(bp, &val); 9283 9284 /* PXP */ 9285 bnx2x_pxp_prep(bp); 9286 barrier(); 9287 9288 /* reset the chip */ 9289 bnx2x_process_kill_chip_reset(bp, global); 9290 barrier(); 9291 9292 /* Recover after reset: */ 9293 /* MCP */ 9294 if (global && bnx2x_reset_mcp_comp(bp, val)) 9295 return -EAGAIN; 9296 9297 /* TBD: Add resetting the NO_MCP mode DB here */ 9298 9299 /* Open the gates #2, #3 and #4 */ 9300 bnx2x_set_234_gates(bp, false); 9301 9302 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 9303 * reset state, re-enable attentions. */ 9304 9305 return 0; 9306 } 9307 9308 static int bnx2x_leader_reset(struct bnx2x *bp) 9309 { 9310 int rc = 0; 9311 bool global = bnx2x_reset_is_global(bp); 9312 u32 load_code; 9313 9314 /* if not going to reset MCP - load "fake" driver to reset HW while 9315 * driver is owner of the HW 9316 */ 9317 if (!global && !BP_NOMCP(bp)) { 9318 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 9319 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 9320 if (!load_code) { 9321 BNX2X_ERR("MCP response failure, aborting\n"); 9322 rc = -EAGAIN; 9323 goto exit_leader_reset; 9324 } 9325 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 9326 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 9327 BNX2X_ERR("MCP unexpected resp, aborting\n"); 9328 rc = -EAGAIN; 9329 goto exit_leader_reset2; 9330 } 9331 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 9332 if (!load_code) { 9333 BNX2X_ERR("MCP response failure, aborting\n"); 9334 rc = -EAGAIN; 9335 goto exit_leader_reset2; 9336 } 9337 } 9338 9339 /* Try to recover after the failure */ 9340 if (bnx2x_process_kill(bp, global)) { 9341 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", 9342 BP_PATH(bp)); 9343 rc = -EAGAIN; 9344 goto exit_leader_reset2; 9345 } 9346 9347 /* 9348 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 9349 * state. 9350 */ 9351 bnx2x_set_reset_done(bp); 9352 if (global) 9353 bnx2x_clear_reset_global(bp); 9354 9355 exit_leader_reset2: 9356 /* unload "fake driver" if it was loaded */ 9357 if (!global && !BP_NOMCP(bp)) { 9358 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 9359 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 9360 } 9361 exit_leader_reset: 9362 bp->is_leader = 0; 9363 bnx2x_release_leader_lock(bp); 9364 smp_mb(); 9365 return rc; 9366 } 9367 9368 static void bnx2x_recovery_failed(struct bnx2x *bp) 9369 { 9370 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 9371 9372 /* Disconnect this device */ 9373 netif_device_detach(bp->dev); 9374 9375 /* 9376 * Block ifup for all function on this engine until "process kill" 9377 * or power cycle. 9378 */ 9379 bnx2x_set_reset_in_progress(bp); 9380 9381 /* Shut down the power */ 9382 bnx2x_set_power_state(bp, PCI_D3hot); 9383 9384 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9385 9386 smp_mb(); 9387 } 9388 9389 /* 9390 * Assumption: runs under rtnl lock. This together with the fact 9391 * that it's called only from bnx2x_sp_rtnl() ensure that it 9392 * will never be called when netif_running(bp->dev) is false. 9393 */ 9394 static void bnx2x_parity_recover(struct bnx2x *bp) 9395 { 9396 bool global = false; 9397 u32 error_recovered, error_unrecovered; 9398 bool is_parity; 9399 9400 DP(NETIF_MSG_HW, "Handling parity\n"); 9401 while (1) { 9402 switch (bp->recovery_state) { 9403 case BNX2X_RECOVERY_INIT: 9404 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 9405 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 9406 WARN_ON(!is_parity); 9407 9408 /* Try to get a LEADER_LOCK HW lock */ 9409 if (bnx2x_trylock_leader_lock(bp)) { 9410 bnx2x_set_reset_in_progress(bp); 9411 /* 9412 * Check if there is a global attention and if 9413 * there was a global attention, set the global 9414 * reset bit. 9415 */ 9416 9417 if (global) 9418 bnx2x_set_reset_global(bp); 9419 9420 bp->is_leader = 1; 9421 } 9422 9423 /* Stop the driver */ 9424 /* If interface has been removed - break */ 9425 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) 9426 return; 9427 9428 bp->recovery_state = BNX2X_RECOVERY_WAIT; 9429 9430 /* Ensure "is_leader", MCP command sequence and 9431 * "recovery_state" update values are seen on other 9432 * CPUs. 9433 */ 9434 smp_mb(); 9435 break; 9436 9437 case BNX2X_RECOVERY_WAIT: 9438 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 9439 if (bp->is_leader) { 9440 int other_engine = BP_PATH(bp) ? 0 : 1; 9441 bool other_load_status = 9442 bnx2x_get_load_status(bp, other_engine); 9443 bool load_status = 9444 bnx2x_get_load_status(bp, BP_PATH(bp)); 9445 global = bnx2x_reset_is_global(bp); 9446 9447 /* 9448 * In case of a parity in a global block, let 9449 * the first leader that performs a 9450 * leader_reset() reset the global blocks in 9451 * order to clear global attentions. Otherwise 9452 * the gates will remain closed for that 9453 * engine. 9454 */ 9455 if (load_status || 9456 (global && other_load_status)) { 9457 /* Wait until all other functions get 9458 * down. 9459 */ 9460 schedule_delayed_work(&bp->sp_rtnl_task, 9461 HZ/10); 9462 return; 9463 } else { 9464 /* If all other functions got down - 9465 * try to bring the chip back to 9466 * normal. In any case it's an exit 9467 * point for a leader. 9468 */ 9469 if (bnx2x_leader_reset(bp)) { 9470 bnx2x_recovery_failed(bp); 9471 return; 9472 } 9473 9474 /* If we are here, means that the 9475 * leader has succeeded and doesn't 9476 * want to be a leader any more. Try 9477 * to continue as a none-leader. 9478 */ 9479 break; 9480 } 9481 } else { /* non-leader */ 9482 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 9483 /* Try to get a LEADER_LOCK HW lock as 9484 * long as a former leader may have 9485 * been unloaded by the user or 9486 * released a leadership by another 9487 * reason. 9488 */ 9489 if (bnx2x_trylock_leader_lock(bp)) { 9490 /* I'm a leader now! Restart a 9491 * switch case. 9492 */ 9493 bp->is_leader = 1; 9494 break; 9495 } 9496 9497 schedule_delayed_work(&bp->sp_rtnl_task, 9498 HZ/10); 9499 return; 9500 9501 } else { 9502 /* 9503 * If there was a global attention, wait 9504 * for it to be cleared. 9505 */ 9506 if (bnx2x_reset_is_global(bp)) { 9507 schedule_delayed_work( 9508 &bp->sp_rtnl_task, 9509 HZ/10); 9510 return; 9511 } 9512 9513 error_recovered = 9514 bp->eth_stats.recoverable_error; 9515 error_unrecovered = 9516 bp->eth_stats.unrecoverable_error; 9517 bp->recovery_state = 9518 BNX2X_RECOVERY_NIC_LOADING; 9519 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 9520 error_unrecovered++; 9521 netdev_err(bp->dev, 9522 "Recovery failed. Power cycle needed\n"); 9523 /* Disconnect this device */ 9524 netif_device_detach(bp->dev); 9525 /* Shut down the power */ 9526 bnx2x_set_power_state( 9527 bp, PCI_D3hot); 9528 smp_mb(); 9529 } else { 9530 bp->recovery_state = 9531 BNX2X_RECOVERY_DONE; 9532 error_recovered++; 9533 smp_mb(); 9534 } 9535 bp->eth_stats.recoverable_error = 9536 error_recovered; 9537 bp->eth_stats.unrecoverable_error = 9538 error_unrecovered; 9539 9540 return; 9541 } 9542 } 9543 default: 9544 return; 9545 } 9546 } 9547 } 9548 9549 static int bnx2x_close(struct net_device *dev); 9550 9551 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 9552 * scheduled on a general queue in order to prevent a dead lock. 9553 */ 9554 static void bnx2x_sp_rtnl_task(struct work_struct *work) 9555 { 9556 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 9557 9558 rtnl_lock(); 9559 9560 if (!netif_running(bp->dev)) { 9561 rtnl_unlock(); 9562 return; 9563 } 9564 9565 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 9566 #ifdef BNX2X_STOP_ON_ERROR 9567 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 9568 "you will need to reboot when done\n"); 9569 goto sp_rtnl_not_reset; 9570 #endif 9571 /* 9572 * Clear all pending SP commands as we are going to reset the 9573 * function anyway. 9574 */ 9575 bp->sp_rtnl_state = 0; 9576 smp_mb(); 9577 9578 bnx2x_parity_recover(bp); 9579 9580 rtnl_unlock(); 9581 return; 9582 } 9583 9584 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 9585 #ifdef BNX2X_STOP_ON_ERROR 9586 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 9587 "you will need to reboot when done\n"); 9588 goto sp_rtnl_not_reset; 9589 #endif 9590 9591 /* 9592 * Clear all pending SP commands as we are going to reset the 9593 * function anyway. 9594 */ 9595 bp->sp_rtnl_state = 0; 9596 smp_mb(); 9597 9598 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 9599 bnx2x_nic_load(bp, LOAD_NORMAL); 9600 9601 rtnl_unlock(); 9602 return; 9603 } 9604 #ifdef BNX2X_STOP_ON_ERROR 9605 sp_rtnl_not_reset: 9606 #endif 9607 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 9608 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 9609 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) 9610 bnx2x_after_function_update(bp); 9611 /* 9612 * in case of fan failure we need to reset id if the "stop on error" 9613 * debug flag is set, since we trying to prevent permanent overheating 9614 * damage 9615 */ 9616 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 9617 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); 9618 netif_device_detach(bp->dev); 9619 bnx2x_close(bp->dev); 9620 rtnl_unlock(); 9621 return; 9622 } 9623 9624 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { 9625 DP(BNX2X_MSG_SP, 9626 "sending set mcast vf pf channel message from rtnl sp-task\n"); 9627 bnx2x_vfpf_set_mcast(bp->dev); 9628 } 9629 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 9630 &bp->sp_rtnl_state)){ 9631 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { 9632 bnx2x_tx_disable(bp); 9633 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); 9634 } 9635 } 9636 9637 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, 9638 &bp->sp_rtnl_state)) { 9639 DP(BNX2X_MSG_SP, 9640 "sending set storm rx mode vf pf channel message from rtnl sp-task\n"); 9641 bnx2x_vfpf_storm_rx_mode(bp); 9642 } 9643 9644 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, 9645 &bp->sp_rtnl_state)) 9646 bnx2x_pf_set_vfs_vlan(bp); 9647 9648 /* work which needs rtnl lock not-taken (as it takes the lock itself and 9649 * can be called from other contexts as well) 9650 */ 9651 rtnl_unlock(); 9652 9653 /* enable SR-IOV if applicable */ 9654 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, 9655 &bp->sp_rtnl_state)) { 9656 bnx2x_disable_sriov(bp); 9657 bnx2x_enable_sriov(bp); 9658 } 9659 } 9660 9661 static void bnx2x_period_task(struct work_struct *work) 9662 { 9663 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 9664 9665 if (!netif_running(bp->dev)) 9666 goto period_task_exit; 9667 9668 if (CHIP_REV_IS_SLOW(bp)) { 9669 BNX2X_ERR("period task called on emulation, ignoring\n"); 9670 goto period_task_exit; 9671 } 9672 9673 bnx2x_acquire_phy_lock(bp); 9674 /* 9675 * The barrier is needed to ensure the ordering between the writing to 9676 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 9677 * the reading here. 9678 */ 9679 smp_mb(); 9680 if (bp->port.pmf) { 9681 bnx2x_period_func(&bp->link_params, &bp->link_vars); 9682 9683 /* Re-queue task in 1 sec */ 9684 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 9685 } 9686 9687 bnx2x_release_phy_lock(bp); 9688 period_task_exit: 9689 return; 9690 } 9691 9692 /* 9693 * Init service functions 9694 */ 9695 9696 u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 9697 { 9698 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 9699 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 9700 return base + (BP_ABS_FUNC(bp)) * stride; 9701 } 9702 9703 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, 9704 struct bnx2x_mac_vals *vals) 9705 { 9706 u32 val, base_addr, offset, mask, reset_reg; 9707 bool mac_stopped = false; 9708 u8 port = BP_PORT(bp); 9709 9710 /* reset addresses as they also mark which values were changed */ 9711 vals->bmac_addr = 0; 9712 vals->umac_addr = 0; 9713 vals->xmac_addr = 0; 9714 vals->emac_addr = 0; 9715 9716 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); 9717 9718 if (!CHIP_IS_E3(bp)) { 9719 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 9720 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 9721 if ((mask & reset_reg) && val) { 9722 u32 wb_data[2]; 9723 BNX2X_DEV_INFO("Disable bmac Rx\n"); 9724 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM 9725 : NIG_REG_INGRESS_BMAC0_MEM; 9726 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL 9727 : BIGMAC_REGISTER_BMAC_CONTROL; 9728 9729 /* 9730 * use rd/wr since we cannot use dmae. This is safe 9731 * since MCP won't access the bus due to the request 9732 * to unload, and no function on the path can be 9733 * loaded at this time. 9734 */ 9735 wb_data[0] = REG_RD(bp, base_addr + offset); 9736 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); 9737 vals->bmac_addr = base_addr + offset; 9738 vals->bmac_val[0] = wb_data[0]; 9739 vals->bmac_val[1] = wb_data[1]; 9740 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 9741 REG_WR(bp, vals->bmac_addr, wb_data[0]); 9742 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); 9743 } 9744 BNX2X_DEV_INFO("Disable emac Rx\n"); 9745 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; 9746 vals->emac_val = REG_RD(bp, vals->emac_addr); 9747 REG_WR(bp, vals->emac_addr, 0); 9748 mac_stopped = true; 9749 } else { 9750 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 9751 BNX2X_DEV_INFO("Disable xmac Rx\n"); 9752 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 9753 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); 9754 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 9755 val & ~(1 << 1)); 9756 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 9757 val | (1 << 1)); 9758 vals->xmac_addr = base_addr + XMAC_REG_CTRL; 9759 vals->xmac_val = REG_RD(bp, vals->xmac_addr); 9760 REG_WR(bp, vals->xmac_addr, 0); 9761 mac_stopped = true; 9762 } 9763 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 9764 if (mask & reset_reg) { 9765 BNX2X_DEV_INFO("Disable umac Rx\n"); 9766 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 9767 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; 9768 vals->umac_val = REG_RD(bp, vals->umac_addr); 9769 REG_WR(bp, vals->umac_addr, 0); 9770 mac_stopped = true; 9771 } 9772 } 9773 9774 if (mac_stopped) 9775 msleep(20); 9776 } 9777 9778 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 9779 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) 9780 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 9781 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 9782 9783 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc) 9784 { 9785 u16 rcq, bd; 9786 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); 9787 9788 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; 9789 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; 9790 9791 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); 9792 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); 9793 9794 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", 9795 port, bd, rcq); 9796 } 9797 9798 static int bnx2x_prev_mcp_done(struct bnx2x *bp) 9799 { 9800 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 9801 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 9802 if (!rc) { 9803 BNX2X_ERR("MCP response failure, aborting\n"); 9804 return -EBUSY; 9805 } 9806 9807 return 0; 9808 } 9809 9810 static struct bnx2x_prev_path_list * 9811 bnx2x_prev_path_get_entry(struct bnx2x *bp) 9812 { 9813 struct bnx2x_prev_path_list *tmp_list; 9814 9815 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) 9816 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && 9817 bp->pdev->bus->number == tmp_list->bus && 9818 BP_PATH(bp) == tmp_list->path) 9819 return tmp_list; 9820 9821 return NULL; 9822 } 9823 9824 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) 9825 { 9826 struct bnx2x_prev_path_list *tmp_list; 9827 int rc; 9828 9829 rc = down_interruptible(&bnx2x_prev_sem); 9830 if (rc) { 9831 BNX2X_ERR("Received %d when tried to take lock\n", rc); 9832 return rc; 9833 } 9834 9835 tmp_list = bnx2x_prev_path_get_entry(bp); 9836 if (tmp_list) { 9837 tmp_list->aer = 1; 9838 rc = 0; 9839 } else { 9840 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", 9841 BP_PATH(bp)); 9842 } 9843 9844 up(&bnx2x_prev_sem); 9845 9846 return rc; 9847 } 9848 9849 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) 9850 { 9851 struct bnx2x_prev_path_list *tmp_list; 9852 int rc = false; 9853 9854 if (down_trylock(&bnx2x_prev_sem)) 9855 return false; 9856 9857 tmp_list = bnx2x_prev_path_get_entry(bp); 9858 if (tmp_list) { 9859 if (tmp_list->aer) { 9860 DP(NETIF_MSG_HW, "Path %d was marked by AER\n", 9861 BP_PATH(bp)); 9862 } else { 9863 rc = true; 9864 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", 9865 BP_PATH(bp)); 9866 } 9867 } 9868 9869 up(&bnx2x_prev_sem); 9870 9871 return rc; 9872 } 9873 9874 bool bnx2x_port_after_undi(struct bnx2x *bp) 9875 { 9876 struct bnx2x_prev_path_list *entry; 9877 bool val; 9878 9879 down(&bnx2x_prev_sem); 9880 9881 entry = bnx2x_prev_path_get_entry(bp); 9882 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); 9883 9884 up(&bnx2x_prev_sem); 9885 9886 return val; 9887 } 9888 9889 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) 9890 { 9891 struct bnx2x_prev_path_list *tmp_list; 9892 int rc; 9893 9894 rc = down_interruptible(&bnx2x_prev_sem); 9895 if (rc) { 9896 BNX2X_ERR("Received %d when tried to take lock\n", rc); 9897 return rc; 9898 } 9899 9900 /* Check whether the entry for this path already exists */ 9901 tmp_list = bnx2x_prev_path_get_entry(bp); 9902 if (tmp_list) { 9903 if (!tmp_list->aer) { 9904 BNX2X_ERR("Re-Marking the path.\n"); 9905 } else { 9906 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", 9907 BP_PATH(bp)); 9908 tmp_list->aer = 0; 9909 } 9910 up(&bnx2x_prev_sem); 9911 return 0; 9912 } 9913 up(&bnx2x_prev_sem); 9914 9915 /* Create an entry for this path and add it */ 9916 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); 9917 if (!tmp_list) { 9918 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); 9919 return -ENOMEM; 9920 } 9921 9922 tmp_list->bus = bp->pdev->bus->number; 9923 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); 9924 tmp_list->path = BP_PATH(bp); 9925 tmp_list->aer = 0; 9926 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; 9927 9928 rc = down_interruptible(&bnx2x_prev_sem); 9929 if (rc) { 9930 BNX2X_ERR("Received %d when tried to take lock\n", rc); 9931 kfree(tmp_list); 9932 } else { 9933 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", 9934 BP_PATH(bp)); 9935 list_add(&tmp_list->list, &bnx2x_prev_list); 9936 up(&bnx2x_prev_sem); 9937 } 9938 9939 return rc; 9940 } 9941 9942 static int bnx2x_do_flr(struct bnx2x *bp) 9943 { 9944 int i; 9945 u16 status; 9946 struct pci_dev *dev = bp->pdev; 9947 9948 if (CHIP_IS_E1x(bp)) { 9949 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); 9950 return -EINVAL; 9951 } 9952 9953 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 9954 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 9955 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", 9956 bp->common.bc_ver); 9957 return -EINVAL; 9958 } 9959 9960 /* Wait for Transaction Pending bit clean */ 9961 for (i = 0; i < 4; i++) { 9962 if (i) 9963 msleep((1 << (i - 1)) * 100); 9964 9965 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 9966 if (!(status & PCI_EXP_DEVSTA_TRPND)) 9967 goto clear; 9968 } 9969 9970 dev_err(&dev->dev, 9971 "transaction is not cleared; proceeding with reset anyway\n"); 9972 9973 clear: 9974 9975 BNX2X_DEV_INFO("Initiating FLR\n"); 9976 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); 9977 9978 return 0; 9979 } 9980 9981 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) 9982 { 9983 int rc; 9984 9985 BNX2X_DEV_INFO("Uncommon unload Flow\n"); 9986 9987 /* Test if previous unload process was already finished for this path */ 9988 if (bnx2x_prev_is_path_marked(bp)) 9989 return bnx2x_prev_mcp_done(bp); 9990 9991 BNX2X_DEV_INFO("Path is unmarked\n"); 9992 9993 /* If function has FLR capabilities, and existing FW version matches 9994 * the one required, then FLR will be sufficient to clean any residue 9995 * left by previous driver 9996 */ 9997 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION); 9998 9999 if (!rc) { 10000 /* fw version is good */ 10001 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); 10002 rc = bnx2x_do_flr(bp); 10003 } 10004 10005 if (!rc) { 10006 /* FLR was performed */ 10007 BNX2X_DEV_INFO("FLR successful\n"); 10008 return 0; 10009 } 10010 10011 BNX2X_DEV_INFO("Could not FLR\n"); 10012 10013 /* Close the MCP request, return failure*/ 10014 rc = bnx2x_prev_mcp_done(bp); 10015 if (!rc) 10016 rc = BNX2X_PREV_WAIT_NEEDED; 10017 10018 return rc; 10019 } 10020 10021 static int bnx2x_prev_unload_common(struct bnx2x *bp) 10022 { 10023 u32 reset_reg, tmp_reg = 0, rc; 10024 bool prev_undi = false; 10025 struct bnx2x_mac_vals mac_vals; 10026 10027 /* It is possible a previous function received 'common' answer, 10028 * but hasn't loaded yet, therefore creating a scenario of 10029 * multiple functions receiving 'common' on the same path. 10030 */ 10031 BNX2X_DEV_INFO("Common unload Flow\n"); 10032 10033 memset(&mac_vals, 0, sizeof(mac_vals)); 10034 10035 if (bnx2x_prev_is_path_marked(bp)) 10036 return bnx2x_prev_mcp_done(bp); 10037 10038 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 10039 10040 /* Reset should be performed after BRB is emptied */ 10041 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 10042 u32 timer_count = 1000; 10043 10044 /* Close the MAC Rx to prevent BRB from filling up */ 10045 bnx2x_prev_unload_close_mac(bp, &mac_vals); 10046 10047 /* close LLH filters towards the BRB */ 10048 bnx2x_set_rx_filter(&bp->link_params, 0); 10049 10050 /* Check if the UNDI driver was previously loaded 10051 * UNDI driver initializes CID offset for normal bell to 0x7 10052 */ 10053 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 10054 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 10055 if (tmp_reg == 0x7) { 10056 BNX2X_DEV_INFO("UNDI previously loaded\n"); 10057 prev_undi = true; 10058 /* clear the UNDI indication */ 10059 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 10060 /* clear possible idle check errors */ 10061 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); 10062 } 10063 } 10064 if (!CHIP_IS_E1x(bp)) 10065 /* block FW from writing to host */ 10066 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 10067 10068 /* wait until BRB is empty */ 10069 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10070 while (timer_count) { 10071 u32 prev_brb = tmp_reg; 10072 10073 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10074 if (!tmp_reg) 10075 break; 10076 10077 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); 10078 10079 /* reset timer as long as BRB actually gets emptied */ 10080 if (prev_brb > tmp_reg) 10081 timer_count = 1000; 10082 else 10083 timer_count--; 10084 10085 /* If UNDI resides in memory, manually increment it */ 10086 if (prev_undi) 10087 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); 10088 10089 udelay(10); 10090 } 10091 10092 if (!timer_count) 10093 BNX2X_ERR("Failed to empty BRB, hope for the best\n"); 10094 } 10095 10096 /* No packets are in the pipeline, path is ready for reset */ 10097 bnx2x_reset_common(bp); 10098 10099 if (mac_vals.xmac_addr) 10100 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); 10101 if (mac_vals.umac_addr) 10102 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val); 10103 if (mac_vals.emac_addr) 10104 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); 10105 if (mac_vals.bmac_addr) { 10106 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); 10107 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); 10108 } 10109 10110 rc = bnx2x_prev_mark_path(bp, prev_undi); 10111 if (rc) { 10112 bnx2x_prev_mcp_done(bp); 10113 return rc; 10114 } 10115 10116 return bnx2x_prev_mcp_done(bp); 10117 } 10118 10119 /* previous driver DMAE transaction may have occurred when pre-boot stage ended 10120 * and boot began, or when kdump kernel was loaded. Either case would invalidate 10121 * the addresses of the transaction, resulting in was-error bit set in the pci 10122 * causing all hw-to-host pcie transactions to timeout. If this happened we want 10123 * to clear the interrupt which detected this from the pglueb and the was done 10124 * bit 10125 */ 10126 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp) 10127 { 10128 if (!CHIP_IS_E1x(bp)) { 10129 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); 10130 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { 10131 DP(BNX2X_MSG_SP, 10132 "'was error' bit was found to be set in pglueb upon startup. Clearing\n"); 10133 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 10134 1 << BP_FUNC(bp)); 10135 } 10136 } 10137 } 10138 10139 static int bnx2x_prev_unload(struct bnx2x *bp) 10140 { 10141 int time_counter = 10; 10142 u32 rc, fw, hw_lock_reg, hw_lock_val; 10143 BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); 10144 10145 /* clear hw from errors which may have resulted from an interrupted 10146 * dmae transaction. 10147 */ 10148 bnx2x_prev_interrupted_dmae(bp); 10149 10150 /* Release previously held locks */ 10151 hw_lock_reg = (BP_FUNC(bp) <= 5) ? 10152 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : 10153 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); 10154 10155 hw_lock_val = REG_RD(bp, hw_lock_reg); 10156 if (hw_lock_val) { 10157 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 10158 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); 10159 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 10160 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); 10161 } 10162 10163 BNX2X_DEV_INFO("Release Previously held hw lock\n"); 10164 REG_WR(bp, hw_lock_reg, 0xffffffff); 10165 } else 10166 BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); 10167 10168 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { 10169 BNX2X_DEV_INFO("Release previously held alr\n"); 10170 bnx2x_release_alr(bp); 10171 } 10172 10173 do { 10174 int aer = 0; 10175 /* Lock MCP using an unload request */ 10176 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 10177 if (!fw) { 10178 BNX2X_ERR("MCP response failure, aborting\n"); 10179 rc = -EBUSY; 10180 break; 10181 } 10182 10183 rc = down_interruptible(&bnx2x_prev_sem); 10184 if (rc) { 10185 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", 10186 rc); 10187 } else { 10188 /* If Path is marked by EEH, ignore unload status */ 10189 aer = !!(bnx2x_prev_path_get_entry(bp) && 10190 bnx2x_prev_path_get_entry(bp)->aer); 10191 up(&bnx2x_prev_sem); 10192 } 10193 10194 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { 10195 rc = bnx2x_prev_unload_common(bp); 10196 break; 10197 } 10198 10199 /* non-common reply from MCP might require looping */ 10200 rc = bnx2x_prev_unload_uncommon(bp); 10201 if (rc != BNX2X_PREV_WAIT_NEEDED) 10202 break; 10203 10204 msleep(20); 10205 } while (--time_counter); 10206 10207 if (!time_counter || rc) { 10208 BNX2X_ERR("Failed unloading previous driver, aborting\n"); 10209 rc = -EBUSY; 10210 } 10211 10212 /* Mark function if its port was used to boot from SAN */ 10213 if (bnx2x_port_after_undi(bp)) 10214 bp->link_params.feature_config_flags |= 10215 FEATURE_CONFIG_BOOT_FROM_SAN; 10216 10217 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); 10218 10219 return rc; 10220 } 10221 10222 static void bnx2x_get_common_hwinfo(struct bnx2x *bp) 10223 { 10224 u32 val, val2, val3, val4, id, boot_mode; 10225 u16 pmc; 10226 10227 /* Get the chip revision id and number. */ 10228 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 10229 val = REG_RD(bp, MISC_REG_CHIP_NUM); 10230 id = ((val & 0xffff) << 16); 10231 val = REG_RD(bp, MISC_REG_CHIP_REV); 10232 id |= ((val & 0xf) << 12); 10233 10234 /* Metal is read from PCI regs, but we can't access >=0x400 from 10235 * the configuration space (so we need to reg_rd) 10236 */ 10237 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); 10238 id |= (((val >> 24) & 0xf) << 4); 10239 val = REG_RD(bp, MISC_REG_BOND_ID); 10240 id |= (val & 0xf); 10241 bp->common.chip_id = id; 10242 10243 /* force 57811 according to MISC register */ 10244 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 10245 if (CHIP_IS_57810(bp)) 10246 bp->common.chip_id = (CHIP_NUM_57811 << 16) | 10247 (bp->common.chip_id & 0x0000FFFF); 10248 else if (CHIP_IS_57810_MF(bp)) 10249 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | 10250 (bp->common.chip_id & 0x0000FFFF); 10251 bp->common.chip_id |= 0x1; 10252 } 10253 10254 /* Set doorbell size */ 10255 bp->db_size = (1 << BNX2X_DB_SHIFT); 10256 10257 if (!CHIP_IS_E1x(bp)) { 10258 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 10259 if ((val & 1) == 0) 10260 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 10261 else 10262 val = (val >> 1) & 1; 10263 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 10264 "2_PORT_MODE"); 10265 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 10266 CHIP_2_PORT_MODE; 10267 10268 if (CHIP_MODE_IS_4_PORT(bp)) 10269 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 10270 else 10271 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 10272 } else { 10273 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 10274 bp->pfid = bp->pf_num; /* 0..7 */ 10275 } 10276 10277 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); 10278 10279 bp->link_params.chip_id = bp->common.chip_id; 10280 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 10281 10282 val = (REG_RD(bp, 0x2874) & 0x55); 10283 if ((bp->common.chip_id & 0x1) || 10284 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 10285 bp->flags |= ONE_PORT_FLAG; 10286 BNX2X_DEV_INFO("single port device\n"); 10287 } 10288 10289 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 10290 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 10291 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 10292 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 10293 bp->common.flash_size, bp->common.flash_size); 10294 10295 bnx2x_init_shmem(bp); 10296 10297 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 10298 MISC_REG_GENERIC_CR_1 : 10299 MISC_REG_GENERIC_CR_0)); 10300 10301 bp->link_params.shmem_base = bp->common.shmem_base; 10302 bp->link_params.shmem2_base = bp->common.shmem2_base; 10303 if (SHMEM2_RD(bp, size) > 10304 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 10305 bp->link_params.lfa_base = 10306 REG_RD(bp, bp->common.shmem2_base + 10307 (u32)offsetof(struct shmem2_region, 10308 lfa_host_addr[BP_PORT(bp)])); 10309 else 10310 bp->link_params.lfa_base = 0; 10311 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 10312 bp->common.shmem_base, bp->common.shmem2_base); 10313 10314 if (!bp->common.shmem_base) { 10315 BNX2X_DEV_INFO("MCP not active\n"); 10316 bp->flags |= NO_MCP_FLAG; 10317 return; 10318 } 10319 10320 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 10321 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 10322 10323 bp->link_params.hw_led_mode = ((bp->common.hw_config & 10324 SHARED_HW_CFG_LED_MODE_MASK) >> 10325 SHARED_HW_CFG_LED_MODE_SHIFT); 10326 10327 bp->link_params.feature_config_flags = 0; 10328 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 10329 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 10330 bp->link_params.feature_config_flags |= 10331 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 10332 else 10333 bp->link_params.feature_config_flags &= 10334 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 10335 10336 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 10337 bp->common.bc_ver = val; 10338 BNX2X_DEV_INFO("bc_ver %X\n", val); 10339 if (val < BNX2X_BC_VER) { 10340 /* for now only warn 10341 * later we might need to enforce this */ 10342 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", 10343 BNX2X_BC_VER, val); 10344 } 10345 bp->link_params.feature_config_flags |= 10346 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 10347 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 10348 10349 bp->link_params.feature_config_flags |= 10350 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 10351 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 10352 bp->link_params.feature_config_flags |= 10353 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? 10354 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; 10355 bp->link_params.feature_config_flags |= 10356 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 10357 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 10358 10359 bp->link_params.feature_config_flags |= 10360 (val >= REQ_BC_VER_4_MT_SUPPORTED) ? 10361 FEATURE_CONFIG_MT_SUPPORT : 0; 10362 10363 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 10364 BC_SUPPORTS_PFC_STATS : 0; 10365 10366 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? 10367 BC_SUPPORTS_FCOE_FEATURES : 0; 10368 10369 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? 10370 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; 10371 10372 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? 10373 BC_SUPPORTS_RMMOD_CMD : 0; 10374 10375 boot_mode = SHMEM_RD(bp, 10376 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 10377 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 10378 switch (boot_mode) { 10379 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 10380 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 10381 break; 10382 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 10383 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 10384 break; 10385 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 10386 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 10387 break; 10388 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 10389 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 10390 break; 10391 } 10392 10393 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 10394 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 10395 10396 BNX2X_DEV_INFO("%sWoL capable\n", 10397 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 10398 10399 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 10400 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 10401 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 10402 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 10403 10404 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 10405 val, val2, val3, val4); 10406 } 10407 10408 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 10409 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 10410 10411 static int bnx2x_get_igu_cam_info(struct bnx2x *bp) 10412 { 10413 int pfid = BP_FUNC(bp); 10414 int igu_sb_id; 10415 u32 val; 10416 u8 fid, igu_sb_cnt = 0; 10417 10418 bp->igu_base_sb = 0xff; 10419 if (CHIP_INT_MODE_IS_BC(bp)) { 10420 int vn = BP_VN(bp); 10421 igu_sb_cnt = bp->igu_sb_cnt; 10422 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 10423 FP_SB_MAX_E1x; 10424 10425 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 10426 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 10427 10428 return 0; 10429 } 10430 10431 /* IGU in normal mode - read CAM */ 10432 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 10433 igu_sb_id++) { 10434 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 10435 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 10436 continue; 10437 fid = IGU_FID(val); 10438 if ((fid & IGU_FID_ENCODE_IS_PF)) { 10439 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 10440 continue; 10441 if (IGU_VEC(val) == 0) 10442 /* default status block */ 10443 bp->igu_dsb_id = igu_sb_id; 10444 else { 10445 if (bp->igu_base_sb == 0xff) 10446 bp->igu_base_sb = igu_sb_id; 10447 igu_sb_cnt++; 10448 } 10449 } 10450 } 10451 10452 #ifdef CONFIG_PCI_MSI 10453 /* Due to new PF resource allocation by MFW T7.4 and above, it's 10454 * optional that number of CAM entries will not be equal to the value 10455 * advertised in PCI. 10456 * Driver should use the minimal value of both as the actual status 10457 * block count 10458 */ 10459 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); 10460 #endif 10461 10462 if (igu_sb_cnt == 0) { 10463 BNX2X_ERR("CAM configuration error\n"); 10464 return -EINVAL; 10465 } 10466 10467 return 0; 10468 } 10469 10470 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) 10471 { 10472 int cfg_size = 0, idx, port = BP_PORT(bp); 10473 10474 /* Aggregation of supported attributes of all external phys */ 10475 bp->port.supported[0] = 0; 10476 bp->port.supported[1] = 0; 10477 switch (bp->link_params.num_phys) { 10478 case 1: 10479 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 10480 cfg_size = 1; 10481 break; 10482 case 2: 10483 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 10484 cfg_size = 1; 10485 break; 10486 case 3: 10487 if (bp->link_params.multi_phy_config & 10488 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 10489 bp->port.supported[1] = 10490 bp->link_params.phy[EXT_PHY1].supported; 10491 bp->port.supported[0] = 10492 bp->link_params.phy[EXT_PHY2].supported; 10493 } else { 10494 bp->port.supported[0] = 10495 bp->link_params.phy[EXT_PHY1].supported; 10496 bp->port.supported[1] = 10497 bp->link_params.phy[EXT_PHY2].supported; 10498 } 10499 cfg_size = 2; 10500 break; 10501 } 10502 10503 if (!(bp->port.supported[0] || bp->port.supported[1])) { 10504 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", 10505 SHMEM_RD(bp, 10506 dev_info.port_hw_config[port].external_phy_config), 10507 SHMEM_RD(bp, 10508 dev_info.port_hw_config[port].external_phy_config2)); 10509 return; 10510 } 10511 10512 if (CHIP_IS_E3(bp)) 10513 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 10514 else { 10515 switch (switch_cfg) { 10516 case SWITCH_CFG_1G: 10517 bp->port.phy_addr = REG_RD( 10518 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 10519 break; 10520 case SWITCH_CFG_10G: 10521 bp->port.phy_addr = REG_RD( 10522 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 10523 break; 10524 default: 10525 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 10526 bp->port.link_config[0]); 10527 return; 10528 } 10529 } 10530 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 10531 /* mask what we support according to speed_cap_mask per configuration */ 10532 for (idx = 0; idx < cfg_size; idx++) { 10533 if (!(bp->link_params.speed_cap_mask[idx] & 10534 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 10535 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 10536 10537 if (!(bp->link_params.speed_cap_mask[idx] & 10538 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 10539 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 10540 10541 if (!(bp->link_params.speed_cap_mask[idx] & 10542 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 10543 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 10544 10545 if (!(bp->link_params.speed_cap_mask[idx] & 10546 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 10547 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 10548 10549 if (!(bp->link_params.speed_cap_mask[idx] & 10550 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 10551 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 10552 SUPPORTED_1000baseT_Full); 10553 10554 if (!(bp->link_params.speed_cap_mask[idx] & 10555 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 10556 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 10557 10558 if (!(bp->link_params.speed_cap_mask[idx] & 10559 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 10560 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 10561 10562 if (!(bp->link_params.speed_cap_mask[idx] & 10563 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 10564 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; 10565 } 10566 10567 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 10568 bp->port.supported[1]); 10569 } 10570 10571 static void bnx2x_link_settings_requested(struct bnx2x *bp) 10572 { 10573 u32 link_config, idx, cfg_size = 0; 10574 bp->port.advertising[0] = 0; 10575 bp->port.advertising[1] = 0; 10576 switch (bp->link_params.num_phys) { 10577 case 1: 10578 case 2: 10579 cfg_size = 1; 10580 break; 10581 case 3: 10582 cfg_size = 2; 10583 break; 10584 } 10585 for (idx = 0; idx < cfg_size; idx++) { 10586 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 10587 link_config = bp->port.link_config[idx]; 10588 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 10589 case PORT_FEATURE_LINK_SPEED_AUTO: 10590 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 10591 bp->link_params.req_line_speed[idx] = 10592 SPEED_AUTO_NEG; 10593 bp->port.advertising[idx] |= 10594 bp->port.supported[idx]; 10595 if (bp->link_params.phy[EXT_PHY1].type == 10596 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 10597 bp->port.advertising[idx] |= 10598 (SUPPORTED_100baseT_Half | 10599 SUPPORTED_100baseT_Full); 10600 } else { 10601 /* force 10G, no AN */ 10602 bp->link_params.req_line_speed[idx] = 10603 SPEED_10000; 10604 bp->port.advertising[idx] |= 10605 (ADVERTISED_10000baseT_Full | 10606 ADVERTISED_FIBRE); 10607 continue; 10608 } 10609 break; 10610 10611 case PORT_FEATURE_LINK_SPEED_10M_FULL: 10612 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 10613 bp->link_params.req_line_speed[idx] = 10614 SPEED_10; 10615 bp->port.advertising[idx] |= 10616 (ADVERTISED_10baseT_Full | 10617 ADVERTISED_TP); 10618 } else { 10619 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10620 link_config, 10621 bp->link_params.speed_cap_mask[idx]); 10622 return; 10623 } 10624 break; 10625 10626 case PORT_FEATURE_LINK_SPEED_10M_HALF: 10627 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 10628 bp->link_params.req_line_speed[idx] = 10629 SPEED_10; 10630 bp->link_params.req_duplex[idx] = 10631 DUPLEX_HALF; 10632 bp->port.advertising[idx] |= 10633 (ADVERTISED_10baseT_Half | 10634 ADVERTISED_TP); 10635 } else { 10636 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10637 link_config, 10638 bp->link_params.speed_cap_mask[idx]); 10639 return; 10640 } 10641 break; 10642 10643 case PORT_FEATURE_LINK_SPEED_100M_FULL: 10644 if (bp->port.supported[idx] & 10645 SUPPORTED_100baseT_Full) { 10646 bp->link_params.req_line_speed[idx] = 10647 SPEED_100; 10648 bp->port.advertising[idx] |= 10649 (ADVERTISED_100baseT_Full | 10650 ADVERTISED_TP); 10651 } else { 10652 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10653 link_config, 10654 bp->link_params.speed_cap_mask[idx]); 10655 return; 10656 } 10657 break; 10658 10659 case PORT_FEATURE_LINK_SPEED_100M_HALF: 10660 if (bp->port.supported[idx] & 10661 SUPPORTED_100baseT_Half) { 10662 bp->link_params.req_line_speed[idx] = 10663 SPEED_100; 10664 bp->link_params.req_duplex[idx] = 10665 DUPLEX_HALF; 10666 bp->port.advertising[idx] |= 10667 (ADVERTISED_100baseT_Half | 10668 ADVERTISED_TP); 10669 } else { 10670 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10671 link_config, 10672 bp->link_params.speed_cap_mask[idx]); 10673 return; 10674 } 10675 break; 10676 10677 case PORT_FEATURE_LINK_SPEED_1G: 10678 if (bp->port.supported[idx] & 10679 SUPPORTED_1000baseT_Full) { 10680 bp->link_params.req_line_speed[idx] = 10681 SPEED_1000; 10682 bp->port.advertising[idx] |= 10683 (ADVERTISED_1000baseT_Full | 10684 ADVERTISED_TP); 10685 } else { 10686 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10687 link_config, 10688 bp->link_params.speed_cap_mask[idx]); 10689 return; 10690 } 10691 break; 10692 10693 case PORT_FEATURE_LINK_SPEED_2_5G: 10694 if (bp->port.supported[idx] & 10695 SUPPORTED_2500baseX_Full) { 10696 bp->link_params.req_line_speed[idx] = 10697 SPEED_2500; 10698 bp->port.advertising[idx] |= 10699 (ADVERTISED_2500baseX_Full | 10700 ADVERTISED_TP); 10701 } else { 10702 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10703 link_config, 10704 bp->link_params.speed_cap_mask[idx]); 10705 return; 10706 } 10707 break; 10708 10709 case PORT_FEATURE_LINK_SPEED_10G_CX4: 10710 if (bp->port.supported[idx] & 10711 SUPPORTED_10000baseT_Full) { 10712 bp->link_params.req_line_speed[idx] = 10713 SPEED_10000; 10714 bp->port.advertising[idx] |= 10715 (ADVERTISED_10000baseT_Full | 10716 ADVERTISED_FIBRE); 10717 } else { 10718 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 10719 link_config, 10720 bp->link_params.speed_cap_mask[idx]); 10721 return; 10722 } 10723 break; 10724 case PORT_FEATURE_LINK_SPEED_20G: 10725 bp->link_params.req_line_speed[idx] = SPEED_20000; 10726 10727 break; 10728 default: 10729 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", 10730 link_config); 10731 bp->link_params.req_line_speed[idx] = 10732 SPEED_AUTO_NEG; 10733 bp->port.advertising[idx] = 10734 bp->port.supported[idx]; 10735 break; 10736 } 10737 10738 bp->link_params.req_flow_ctrl[idx] = (link_config & 10739 PORT_FEATURE_FLOW_CONTROL_MASK); 10740 if (bp->link_params.req_flow_ctrl[idx] == 10741 BNX2X_FLOW_CTRL_AUTO) { 10742 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) 10743 bp->link_params.req_flow_ctrl[idx] = 10744 BNX2X_FLOW_CTRL_NONE; 10745 else 10746 bnx2x_set_requested_fc(bp); 10747 } 10748 10749 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", 10750 bp->link_params.req_line_speed[idx], 10751 bp->link_params.req_duplex[idx], 10752 bp->link_params.req_flow_ctrl[idx], 10753 bp->port.advertising[idx]); 10754 } 10755 } 10756 10757 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 10758 { 10759 __be16 mac_hi_be = cpu_to_be16(mac_hi); 10760 __be32 mac_lo_be = cpu_to_be32(mac_lo); 10761 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); 10762 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); 10763 } 10764 10765 static void bnx2x_get_port_hwinfo(struct bnx2x *bp) 10766 { 10767 int port = BP_PORT(bp); 10768 u32 config; 10769 u32 ext_phy_type, ext_phy_config, eee_mode; 10770 10771 bp->link_params.bp = bp; 10772 bp->link_params.port = port; 10773 10774 bp->link_params.lane_config = 10775 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 10776 10777 bp->link_params.speed_cap_mask[0] = 10778 SHMEM_RD(bp, 10779 dev_info.port_hw_config[port].speed_capability_mask) & 10780 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 10781 bp->link_params.speed_cap_mask[1] = 10782 SHMEM_RD(bp, 10783 dev_info.port_hw_config[port].speed_capability_mask2) & 10784 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 10785 bp->port.link_config[0] = 10786 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 10787 10788 bp->port.link_config[1] = 10789 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 10790 10791 bp->link_params.multi_phy_config = 10792 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 10793 /* If the device is capable of WoL, set the default state according 10794 * to the HW 10795 */ 10796 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 10797 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 10798 (config & PORT_FEATURE_WOL_ENABLED)); 10799 10800 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 10801 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) 10802 bp->flags |= NO_ISCSI_FLAG; 10803 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 10804 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) 10805 bp->flags |= NO_FCOE_FLAG; 10806 10807 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", 10808 bp->link_params.lane_config, 10809 bp->link_params.speed_cap_mask[0], 10810 bp->port.link_config[0]); 10811 10812 bp->link_params.switch_cfg = (bp->port.link_config[0] & 10813 PORT_FEATURE_CONNECTED_SWITCH_MASK); 10814 bnx2x_phy_probe(&bp->link_params); 10815 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 10816 10817 bnx2x_link_settings_requested(bp); 10818 10819 /* 10820 * If connected directly, work with the internal PHY, otherwise, work 10821 * with the external PHY 10822 */ 10823 ext_phy_config = 10824 SHMEM_RD(bp, 10825 dev_info.port_hw_config[port].external_phy_config); 10826 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 10827 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 10828 bp->mdio.prtad = bp->port.phy_addr; 10829 10830 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 10831 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 10832 bp->mdio.prtad = 10833 XGXS_EXT_PHY_ADDR(ext_phy_config); 10834 10835 /* Configure link feature according to nvram value */ 10836 eee_mode = (((SHMEM_RD(bp, dev_info. 10837 port_feature_config[port].eee_power_mode)) & 10838 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 10839 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 10840 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 10841 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | 10842 EEE_MODE_ENABLE_LPI | 10843 EEE_MODE_OUTPUT_TIME; 10844 } else { 10845 bp->link_params.eee_mode = 0; 10846 } 10847 } 10848 10849 void bnx2x_get_iscsi_info(struct bnx2x *bp) 10850 { 10851 u32 no_flags = NO_ISCSI_FLAG; 10852 int port = BP_PORT(bp); 10853 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 10854 drv_lic_key[port].max_iscsi_conn); 10855 10856 if (!CNIC_SUPPORT(bp)) { 10857 bp->flags |= no_flags; 10858 return; 10859 } 10860 10861 /* Get the number of maximum allowed iSCSI connections */ 10862 bp->cnic_eth_dev.max_iscsi_conn = 10863 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 10864 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 10865 10866 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 10867 bp->cnic_eth_dev.max_iscsi_conn); 10868 10869 /* 10870 * If maximum allowed number of connections is zero - 10871 * disable the feature. 10872 */ 10873 if (!bp->cnic_eth_dev.max_iscsi_conn) 10874 bp->flags |= no_flags; 10875 } 10876 10877 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) 10878 { 10879 /* Port info */ 10880 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 10881 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); 10882 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 10883 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); 10884 10885 /* Node info */ 10886 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 10887 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); 10888 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 10889 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); 10890 } 10891 10892 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) 10893 { 10894 u8 count = 0; 10895 10896 if (IS_MF(bp)) { 10897 u8 fid; 10898 10899 /* iterate over absolute function ids for this path: */ 10900 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { 10901 if (IS_MF_SD(bp)) { 10902 u32 cfg = MF_CFG_RD(bp, 10903 func_mf_config[fid].config); 10904 10905 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && 10906 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == 10907 FUNC_MF_CFG_PROTOCOL_FCOE)) 10908 count++; 10909 } else { 10910 u32 cfg = MF_CFG_RD(bp, 10911 func_ext_config[fid]. 10912 func_cfg); 10913 10914 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && 10915 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) 10916 count++; 10917 } 10918 } 10919 } else { /* SF */ 10920 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; 10921 10922 for (port = 0; port < port_cnt; port++) { 10923 u32 lic = SHMEM_RD(bp, 10924 drv_lic_key[port].max_fcoe_conn) ^ 10925 FW_ENCODE_32BIT_PATTERN; 10926 if (lic) 10927 count++; 10928 } 10929 } 10930 10931 return count; 10932 } 10933 10934 static void bnx2x_get_fcoe_info(struct bnx2x *bp) 10935 { 10936 int port = BP_PORT(bp); 10937 int func = BP_ABS_FUNC(bp); 10938 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 10939 drv_lic_key[port].max_fcoe_conn); 10940 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); 10941 10942 if (!CNIC_SUPPORT(bp)) { 10943 bp->flags |= NO_FCOE_FLAG; 10944 return; 10945 } 10946 10947 /* Get the number of maximum allowed FCoE connections */ 10948 bp->cnic_eth_dev.max_fcoe_conn = 10949 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 10950 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 10951 10952 /* Calculate the number of maximum allowed FCoE tasks */ 10953 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; 10954 10955 /* check if FCoE resources must be shared between different functions */ 10956 if (num_fcoe_func) 10957 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; 10958 10959 /* Read the WWN: */ 10960 if (!IS_MF(bp)) { 10961 /* Port info */ 10962 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 10963 SHMEM_RD(bp, 10964 dev_info.port_hw_config[port]. 10965 fcoe_wwn_port_name_upper); 10966 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 10967 SHMEM_RD(bp, 10968 dev_info.port_hw_config[port]. 10969 fcoe_wwn_port_name_lower); 10970 10971 /* Node info */ 10972 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 10973 SHMEM_RD(bp, 10974 dev_info.port_hw_config[port]. 10975 fcoe_wwn_node_name_upper); 10976 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 10977 SHMEM_RD(bp, 10978 dev_info.port_hw_config[port]. 10979 fcoe_wwn_node_name_lower); 10980 } else if (!IS_MF_SD(bp)) { 10981 /* 10982 * Read the WWN info only if the FCoE feature is enabled for 10983 * this function. 10984 */ 10985 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) 10986 bnx2x_get_ext_wwn_info(bp, func); 10987 10988 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) { 10989 bnx2x_get_ext_wwn_info(bp, func); 10990 } 10991 10992 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 10993 10994 /* 10995 * If maximum allowed number of connections is zero - 10996 * disable the feature. 10997 */ 10998 if (!bp->cnic_eth_dev.max_fcoe_conn) 10999 bp->flags |= NO_FCOE_FLAG; 11000 } 11001 11002 static void bnx2x_get_cnic_info(struct bnx2x *bp) 11003 { 11004 /* 11005 * iSCSI may be dynamically disabled but reading 11006 * info here we will decrease memory usage by driver 11007 * if the feature is disabled for good 11008 */ 11009 bnx2x_get_iscsi_info(bp); 11010 bnx2x_get_fcoe_info(bp); 11011 } 11012 11013 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) 11014 { 11015 u32 val, val2; 11016 int func = BP_ABS_FUNC(bp); 11017 int port = BP_PORT(bp); 11018 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 11019 u8 *fip_mac = bp->fip_mac; 11020 11021 if (IS_MF(bp)) { 11022 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 11023 * FCoE MAC then the appropriate feature should be disabled. 11024 * In non SD mode features configuration comes from struct 11025 * func_ext_config. 11026 */ 11027 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) { 11028 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 11029 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 11030 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11031 iscsi_mac_addr_upper); 11032 val = MF_CFG_RD(bp, func_ext_config[func]. 11033 iscsi_mac_addr_lower); 11034 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11035 BNX2X_DEV_INFO 11036 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11037 } else { 11038 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11039 } 11040 11041 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 11042 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11043 fcoe_mac_addr_upper); 11044 val = MF_CFG_RD(bp, func_ext_config[func]. 11045 fcoe_mac_addr_lower); 11046 bnx2x_set_mac_buf(fip_mac, val, val2); 11047 BNX2X_DEV_INFO 11048 ("Read FCoE L2 MAC: %pM\n", fip_mac); 11049 } else { 11050 bp->flags |= NO_FCOE_FLAG; 11051 } 11052 11053 bp->mf_ext_config = cfg; 11054 11055 } else { /* SD MODE */ 11056 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { 11057 /* use primary mac as iscsi mac */ 11058 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 11059 11060 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 11061 BNX2X_DEV_INFO 11062 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11063 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { 11064 /* use primary mac as fip mac */ 11065 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 11066 BNX2X_DEV_INFO("SD FCoE MODE\n"); 11067 BNX2X_DEV_INFO 11068 ("Read FIP MAC: %pM\n", fip_mac); 11069 } 11070 } 11071 11072 /* If this is a storage-only interface, use SAN mac as 11073 * primary MAC. Notice that for SD this is already the case, 11074 * as the SAN mac was copied from the primary MAC. 11075 */ 11076 if (IS_MF_FCOE_AFEX(bp)) 11077 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); 11078 } else { 11079 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11080 iscsi_mac_upper); 11081 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11082 iscsi_mac_lower); 11083 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11084 11085 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11086 fcoe_fip_mac_upper); 11087 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11088 fcoe_fip_mac_lower); 11089 bnx2x_set_mac_buf(fip_mac, val, val2); 11090 } 11091 11092 /* Disable iSCSI OOO if MAC configuration is invalid. */ 11093 if (!is_valid_ether_addr(iscsi_mac)) { 11094 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11095 memset(iscsi_mac, 0, ETH_ALEN); 11096 } 11097 11098 /* Disable FCoE if MAC configuration is invalid. */ 11099 if (!is_valid_ether_addr(fip_mac)) { 11100 bp->flags |= NO_FCOE_FLAG; 11101 memset(bp->fip_mac, 0, ETH_ALEN); 11102 } 11103 } 11104 11105 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) 11106 { 11107 u32 val, val2; 11108 int func = BP_ABS_FUNC(bp); 11109 int port = BP_PORT(bp); 11110 11111 /* Zero primary MAC configuration */ 11112 memset(bp->dev->dev_addr, 0, ETH_ALEN); 11113 11114 if (BP_NOMCP(bp)) { 11115 BNX2X_ERROR("warning: random MAC workaround active\n"); 11116 eth_hw_addr_random(bp->dev); 11117 } else if (IS_MF(bp)) { 11118 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 11119 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 11120 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 11121 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 11122 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 11123 11124 if (CNIC_SUPPORT(bp)) 11125 bnx2x_get_cnic_mac_hwinfo(bp); 11126 } else { 11127 /* in SF read MACs from port configuration */ 11128 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 11129 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 11130 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 11131 11132 if (CNIC_SUPPORT(bp)) 11133 bnx2x_get_cnic_mac_hwinfo(bp); 11134 } 11135 11136 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 11137 11138 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 11139 dev_err(&bp->pdev->dev, 11140 "bad Ethernet MAC address configuration: %pM\n" 11141 "change it manually before bringing up the appropriate network interface\n", 11142 bp->dev->dev_addr); 11143 } 11144 11145 static bool bnx2x_get_dropless_info(struct bnx2x *bp) 11146 { 11147 int tmp; 11148 u32 cfg; 11149 11150 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { 11151 /* Take function: tmp = func */ 11152 tmp = BP_ABS_FUNC(bp); 11153 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); 11154 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); 11155 } else { 11156 /* Take port: tmp = port */ 11157 tmp = BP_PORT(bp); 11158 cfg = SHMEM_RD(bp, 11159 dev_info.port_hw_config[tmp].generic_features); 11160 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); 11161 } 11162 return cfg; 11163 } 11164 11165 static int bnx2x_get_hwinfo(struct bnx2x *bp) 11166 { 11167 int /*abs*/func = BP_ABS_FUNC(bp); 11168 int vn; 11169 u32 val = 0; 11170 int rc = 0; 11171 11172 bnx2x_get_common_hwinfo(bp); 11173 11174 /* 11175 * initialize IGU parameters 11176 */ 11177 if (CHIP_IS_E1x(bp)) { 11178 bp->common.int_block = INT_BLOCK_HC; 11179 11180 bp->igu_dsb_id = DEF_SB_IGU_ID; 11181 bp->igu_base_sb = 0; 11182 } else { 11183 bp->common.int_block = INT_BLOCK_IGU; 11184 11185 /* do not allow device reset during IGU info processing */ 11186 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11187 11188 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 11189 11190 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11191 int tout = 5000; 11192 11193 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 11194 11195 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 11196 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 11197 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 11198 11199 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11200 tout--; 11201 usleep_range(1000, 2000); 11202 } 11203 11204 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11205 dev_err(&bp->pdev->dev, 11206 "FORCING Normal Mode failed!!!\n"); 11207 bnx2x_release_hw_lock(bp, 11208 HW_LOCK_RESOURCE_RESET); 11209 return -EPERM; 11210 } 11211 } 11212 11213 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11214 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 11215 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 11216 } else 11217 BNX2X_DEV_INFO("IGU Normal Mode\n"); 11218 11219 rc = bnx2x_get_igu_cam_info(bp); 11220 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11221 if (rc) 11222 return rc; 11223 } 11224 11225 /* 11226 * set base FW non-default (fast path) status block id, this value is 11227 * used to initialize the fw_sb_id saved on the fp/queue structure to 11228 * determine the id used by the FW. 11229 */ 11230 if (CHIP_IS_E1x(bp)) 11231 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 11232 else /* 11233 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 11234 * the same queue are indicated on the same IGU SB). So we prefer 11235 * FW and IGU SBs to be the same value. 11236 */ 11237 bp->base_fw_ndsb = bp->igu_base_sb; 11238 11239 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 11240 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 11241 bp->igu_sb_cnt, bp->base_fw_ndsb); 11242 11243 /* 11244 * Initialize MF configuration 11245 */ 11246 11247 bp->mf_ov = 0; 11248 bp->mf_mode = 0; 11249 vn = BP_VN(bp); 11250 11251 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 11252 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 11253 bp->common.shmem2_base, SHMEM2_RD(bp, size), 11254 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 11255 11256 if (SHMEM2_HAS(bp, mf_cfg_addr)) 11257 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 11258 else 11259 bp->common.mf_cfg_base = bp->common.shmem_base + 11260 offsetof(struct shmem_region, func_mb) + 11261 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 11262 /* 11263 * get mf configuration: 11264 * 1. Existence of MF configuration 11265 * 2. MAC address must be legal (check only upper bytes) 11266 * for Switch-Independent mode; 11267 * OVLAN must be legal for Switch-Dependent mode 11268 * 3. SF_MODE configures specific MF mode 11269 */ 11270 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 11271 /* get mf configuration */ 11272 val = SHMEM_RD(bp, 11273 dev_info.shared_feature_config.config); 11274 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 11275 11276 switch (val) { 11277 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 11278 val = MF_CFG_RD(bp, func_mf_config[func]. 11279 mac_upper); 11280 /* check for legal mac (upper bytes)*/ 11281 if (val != 0xffff) { 11282 bp->mf_mode = MULTI_FUNCTION_SI; 11283 bp->mf_config[vn] = MF_CFG_RD(bp, 11284 func_mf_config[func].config); 11285 } else 11286 BNX2X_DEV_INFO("illegal MAC address for SI\n"); 11287 break; 11288 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 11289 if ((!CHIP_IS_E1x(bp)) && 11290 (MF_CFG_RD(bp, func_mf_config[func]. 11291 mac_upper) != 0xffff) && 11292 (SHMEM2_HAS(bp, 11293 afex_driver_support))) { 11294 bp->mf_mode = MULTI_FUNCTION_AFEX; 11295 bp->mf_config[vn] = MF_CFG_RD(bp, 11296 func_mf_config[func].config); 11297 } else { 11298 BNX2X_DEV_INFO("can not configure afex mode\n"); 11299 } 11300 break; 11301 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 11302 /* get OV configuration */ 11303 val = MF_CFG_RD(bp, 11304 func_mf_config[FUNC_0].e1hov_tag); 11305 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 11306 11307 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 11308 bp->mf_mode = MULTI_FUNCTION_SD; 11309 bp->mf_config[vn] = MF_CFG_RD(bp, 11310 func_mf_config[func].config); 11311 } else 11312 BNX2X_DEV_INFO("illegal OV for SD\n"); 11313 break; 11314 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: 11315 bp->mf_config[vn] = 0; 11316 break; 11317 default: 11318 /* Unknown configuration: reset mf_config */ 11319 bp->mf_config[vn] = 0; 11320 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); 11321 } 11322 } 11323 11324 BNX2X_DEV_INFO("%s function mode\n", 11325 IS_MF(bp) ? "multi" : "single"); 11326 11327 switch (bp->mf_mode) { 11328 case MULTI_FUNCTION_SD: 11329 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 11330 FUNC_MF_CFG_E1HOV_TAG_MASK; 11331 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 11332 bp->mf_ov = val; 11333 bp->path_has_ovlan = true; 11334 11335 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", 11336 func, bp->mf_ov, bp->mf_ov); 11337 } else { 11338 dev_err(&bp->pdev->dev, 11339 "No valid MF OV for func %d, aborting\n", 11340 func); 11341 return -EPERM; 11342 } 11343 break; 11344 case MULTI_FUNCTION_AFEX: 11345 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); 11346 break; 11347 case MULTI_FUNCTION_SI: 11348 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", 11349 func); 11350 break; 11351 default: 11352 if (vn) { 11353 dev_err(&bp->pdev->dev, 11354 "VN %d is in a single function mode, aborting\n", 11355 vn); 11356 return -EPERM; 11357 } 11358 break; 11359 } 11360 11361 /* check if other port on the path needs ovlan: 11362 * Since MF configuration is shared between ports 11363 * Possible mixed modes are only 11364 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 11365 */ 11366 if (CHIP_MODE_IS_4_PORT(bp) && 11367 !bp->path_has_ovlan && 11368 !IS_MF(bp) && 11369 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 11370 u8 other_port = !BP_PORT(bp); 11371 u8 other_func = BP_PATH(bp) + 2*other_port; 11372 val = MF_CFG_RD(bp, 11373 func_mf_config[other_func].e1hov_tag); 11374 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 11375 bp->path_has_ovlan = true; 11376 } 11377 } 11378 11379 /* adjust igu_sb_cnt to MF for E1x */ 11380 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 11381 bp->igu_sb_cnt /= E1HVN_MAX; 11382 11383 /* port info */ 11384 bnx2x_get_port_hwinfo(bp); 11385 11386 /* Get MAC addresses */ 11387 bnx2x_get_mac_hwinfo(bp); 11388 11389 bnx2x_get_cnic_info(bp); 11390 11391 return rc; 11392 } 11393 11394 static void bnx2x_read_fwinfo(struct bnx2x *bp) 11395 { 11396 int cnt, i, block_end, rodi; 11397 char vpd_start[BNX2X_VPD_LEN+1]; 11398 char str_id_reg[VENDOR_ID_LEN+1]; 11399 char str_id_cap[VENDOR_ID_LEN+1]; 11400 char *vpd_data; 11401 char *vpd_extended_data = NULL; 11402 u8 len; 11403 11404 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 11405 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 11406 11407 if (cnt < BNX2X_VPD_LEN) 11408 goto out_not_found; 11409 11410 /* VPD RO tag should be first tag after identifier string, hence 11411 * we should be able to find it in first BNX2X_VPD_LEN chars 11412 */ 11413 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 11414 PCI_VPD_LRDT_RO_DATA); 11415 if (i < 0) 11416 goto out_not_found; 11417 11418 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 11419 pci_vpd_lrdt_size(&vpd_start[i]); 11420 11421 i += PCI_VPD_LRDT_TAG_SIZE; 11422 11423 if (block_end > BNX2X_VPD_LEN) { 11424 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 11425 if (vpd_extended_data == NULL) 11426 goto out_not_found; 11427 11428 /* read rest of vpd image into vpd_extended_data */ 11429 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 11430 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 11431 block_end - BNX2X_VPD_LEN, 11432 vpd_extended_data + BNX2X_VPD_LEN); 11433 if (cnt < (block_end - BNX2X_VPD_LEN)) 11434 goto out_not_found; 11435 vpd_data = vpd_extended_data; 11436 } else 11437 vpd_data = vpd_start; 11438 11439 /* now vpd_data holds full vpd content in both cases */ 11440 11441 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 11442 PCI_VPD_RO_KEYWORD_MFR_ID); 11443 if (rodi < 0) 11444 goto out_not_found; 11445 11446 len = pci_vpd_info_field_size(&vpd_data[rodi]); 11447 11448 if (len != VENDOR_ID_LEN) 11449 goto out_not_found; 11450 11451 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 11452 11453 /* vendor specific info */ 11454 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 11455 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 11456 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 11457 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 11458 11459 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 11460 PCI_VPD_RO_KEYWORD_VENDOR0); 11461 if (rodi >= 0) { 11462 len = pci_vpd_info_field_size(&vpd_data[rodi]); 11463 11464 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 11465 11466 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 11467 memcpy(bp->fw_ver, &vpd_data[rodi], len); 11468 bp->fw_ver[len] = ' '; 11469 } 11470 } 11471 kfree(vpd_extended_data); 11472 return; 11473 } 11474 out_not_found: 11475 kfree(vpd_extended_data); 11476 return; 11477 } 11478 11479 static void bnx2x_set_modes_bitmap(struct bnx2x *bp) 11480 { 11481 u32 flags = 0; 11482 11483 if (CHIP_REV_IS_FPGA(bp)) 11484 SET_FLAGS(flags, MODE_FPGA); 11485 else if (CHIP_REV_IS_EMUL(bp)) 11486 SET_FLAGS(flags, MODE_EMUL); 11487 else 11488 SET_FLAGS(flags, MODE_ASIC); 11489 11490 if (CHIP_MODE_IS_4_PORT(bp)) 11491 SET_FLAGS(flags, MODE_PORT4); 11492 else 11493 SET_FLAGS(flags, MODE_PORT2); 11494 11495 if (CHIP_IS_E2(bp)) 11496 SET_FLAGS(flags, MODE_E2); 11497 else if (CHIP_IS_E3(bp)) { 11498 SET_FLAGS(flags, MODE_E3); 11499 if (CHIP_REV(bp) == CHIP_REV_Ax) 11500 SET_FLAGS(flags, MODE_E3_A0); 11501 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 11502 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 11503 } 11504 11505 if (IS_MF(bp)) { 11506 SET_FLAGS(flags, MODE_MF); 11507 switch (bp->mf_mode) { 11508 case MULTI_FUNCTION_SD: 11509 SET_FLAGS(flags, MODE_MF_SD); 11510 break; 11511 case MULTI_FUNCTION_SI: 11512 SET_FLAGS(flags, MODE_MF_SI); 11513 break; 11514 case MULTI_FUNCTION_AFEX: 11515 SET_FLAGS(flags, MODE_MF_AFEX); 11516 break; 11517 } 11518 } else 11519 SET_FLAGS(flags, MODE_SF); 11520 11521 #if defined(__LITTLE_ENDIAN) 11522 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 11523 #else /*(__BIG_ENDIAN)*/ 11524 SET_FLAGS(flags, MODE_BIG_ENDIAN); 11525 #endif 11526 INIT_MODE_FLAGS(bp) = flags; 11527 } 11528 11529 static int bnx2x_init_bp(struct bnx2x *bp) 11530 { 11531 int func; 11532 int rc; 11533 11534 mutex_init(&bp->port.phy_mutex); 11535 mutex_init(&bp->fw_mb_mutex); 11536 spin_lock_init(&bp->stats_lock); 11537 sema_init(&bp->stats_sema, 1); 11538 11539 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 11540 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 11541 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 11542 if (IS_PF(bp)) { 11543 rc = bnx2x_get_hwinfo(bp); 11544 if (rc) 11545 return rc; 11546 } else { 11547 eth_zero_addr(bp->dev->dev_addr); 11548 } 11549 11550 bnx2x_set_modes_bitmap(bp); 11551 11552 rc = bnx2x_alloc_mem_bp(bp); 11553 if (rc) 11554 return rc; 11555 11556 bnx2x_read_fwinfo(bp); 11557 11558 func = BP_FUNC(bp); 11559 11560 /* need to reset chip if undi was active */ 11561 if (IS_PF(bp) && !BP_NOMCP(bp)) { 11562 /* init fw_seq */ 11563 bp->fw_seq = 11564 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 11565 DRV_MSG_SEQ_NUMBER_MASK; 11566 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 11567 11568 bnx2x_prev_unload(bp); 11569 } 11570 11571 if (CHIP_REV_IS_FPGA(bp)) 11572 dev_err(&bp->pdev->dev, "FPGA detected\n"); 11573 11574 if (BP_NOMCP(bp) && (func == 0)) 11575 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); 11576 11577 bp->disable_tpa = disable_tpa; 11578 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); 11579 11580 /* Set TPA flags */ 11581 if (bp->disable_tpa) { 11582 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 11583 bp->dev->features &= ~NETIF_F_LRO; 11584 } else { 11585 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 11586 bp->dev->features |= NETIF_F_LRO; 11587 } 11588 11589 if (CHIP_IS_E1(bp)) 11590 bp->dropless_fc = 0; 11591 else 11592 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); 11593 11594 bp->mrrs = mrrs; 11595 11596 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 11597 if (IS_VF(bp)) 11598 bp->rx_ring_size = MAX_RX_AVAIL; 11599 11600 /* make sure that the numbers are in the right granularity */ 11601 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 11602 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 11603 11604 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 11605 11606 init_timer(&bp->timer); 11607 bp->timer.expires = jiffies + bp->current_interval; 11608 bp->timer.data = (unsigned long) bp; 11609 bp->timer.function = bnx2x_timer; 11610 11611 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && 11612 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && 11613 SHMEM2_RD(bp, dcbx_lldp_params_offset) && 11614 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { 11615 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 11616 bnx2x_dcbx_init_params(bp); 11617 } else { 11618 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); 11619 } 11620 11621 if (CHIP_IS_E1x(bp)) 11622 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 11623 else 11624 bp->cnic_base_cl_id = FP_SB_MAX_E2; 11625 11626 /* multiple tx priority */ 11627 if (IS_VF(bp)) 11628 bp->max_cos = 1; 11629 else if (CHIP_IS_E1x(bp)) 11630 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 11631 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 11632 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 11633 else if (CHIP_IS_E3B0(bp)) 11634 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 11635 else 11636 BNX2X_ERR("unknown chip %x revision %x\n", 11637 CHIP_NUM(bp), CHIP_REV(bp)); 11638 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); 11639 11640 /* We need at least one default status block for slow-path events, 11641 * second status block for the L2 queue, and a third status block for 11642 * CNIC if supported. 11643 */ 11644 if (CNIC_SUPPORT(bp)) 11645 bp->min_msix_vec_cnt = 3; 11646 else 11647 bp->min_msix_vec_cnt = 2; 11648 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); 11649 11650 bp->dump_preset_idx = 1; 11651 11652 return rc; 11653 } 11654 11655 /**************************************************************************** 11656 * General service functions 11657 ****************************************************************************/ 11658 11659 /* 11660 * net_device service functions 11661 */ 11662 11663 /* called with rtnl_lock */ 11664 static int bnx2x_open(struct net_device *dev) 11665 { 11666 struct bnx2x *bp = netdev_priv(dev); 11667 bool global = false; 11668 int other_engine = BP_PATH(bp) ? 0 : 1; 11669 bool other_load_status, load_status; 11670 int rc; 11671 11672 bp->stats_init = true; 11673 11674 netif_carrier_off(dev); 11675 11676 bnx2x_set_power_state(bp, PCI_D0); 11677 11678 /* If parity had happen during the unload, then attentions 11679 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 11680 * want the first function loaded on the current engine to 11681 * complete the recovery. 11682 * Parity recovery is only relevant for PF driver. 11683 */ 11684 if (IS_PF(bp)) { 11685 other_load_status = bnx2x_get_load_status(bp, other_engine); 11686 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 11687 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 11688 bnx2x_chk_parity_attn(bp, &global, true)) { 11689 do { 11690 /* If there are attentions and they are in a 11691 * global blocks, set the GLOBAL_RESET bit 11692 * regardless whether it will be this function 11693 * that will complete the recovery or not. 11694 */ 11695 if (global) 11696 bnx2x_set_reset_global(bp); 11697 11698 /* Only the first function on the current 11699 * engine should try to recover in open. In case 11700 * of attentions in global blocks only the first 11701 * in the chip should try to recover. 11702 */ 11703 if ((!load_status && 11704 (!global || !other_load_status)) && 11705 bnx2x_trylock_leader_lock(bp) && 11706 !bnx2x_leader_reset(bp)) { 11707 netdev_info(bp->dev, 11708 "Recovered in open\n"); 11709 break; 11710 } 11711 11712 /* recovery has failed... */ 11713 bnx2x_set_power_state(bp, PCI_D3hot); 11714 bp->recovery_state = BNX2X_RECOVERY_FAILED; 11715 11716 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" 11717 "If you still see this message after a few retries then power cycle is required.\n"); 11718 11719 return -EAGAIN; 11720 } while (0); 11721 } 11722 } 11723 11724 bp->recovery_state = BNX2X_RECOVERY_DONE; 11725 rc = bnx2x_nic_load(bp, LOAD_OPEN); 11726 if (rc) 11727 return rc; 11728 return bnx2x_open_epilog(bp); 11729 } 11730 11731 /* called with rtnl_lock */ 11732 static int bnx2x_close(struct net_device *dev) 11733 { 11734 struct bnx2x *bp = netdev_priv(dev); 11735 11736 /* Unload the driver, release IRQs */ 11737 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); 11738 11739 return 0; 11740 } 11741 11742 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 11743 struct bnx2x_mcast_ramrod_params *p) 11744 { 11745 int mc_count = netdev_mc_count(bp->dev); 11746 struct bnx2x_mcast_list_elem *mc_mac = 11747 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 11748 struct netdev_hw_addr *ha; 11749 11750 if (!mc_mac) 11751 return -ENOMEM; 11752 11753 INIT_LIST_HEAD(&p->mcast_list); 11754 11755 netdev_for_each_mc_addr(ha, bp->dev) { 11756 mc_mac->mac = bnx2x_mc_addr(ha); 11757 list_add_tail(&mc_mac->link, &p->mcast_list); 11758 mc_mac++; 11759 } 11760 11761 p->mcast_list_len = mc_count; 11762 11763 return 0; 11764 } 11765 11766 static void bnx2x_free_mcast_macs_list( 11767 struct bnx2x_mcast_ramrod_params *p) 11768 { 11769 struct bnx2x_mcast_list_elem *mc_mac = 11770 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 11771 link); 11772 11773 WARN_ON(!mc_mac); 11774 kfree(mc_mac); 11775 } 11776 11777 /** 11778 * bnx2x_set_uc_list - configure a new unicast MACs list. 11779 * 11780 * @bp: driver handle 11781 * 11782 * We will use zero (0) as a MAC type for these MACs. 11783 */ 11784 static int bnx2x_set_uc_list(struct bnx2x *bp) 11785 { 11786 int rc; 11787 struct net_device *dev = bp->dev; 11788 struct netdev_hw_addr *ha; 11789 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; 11790 unsigned long ramrod_flags = 0; 11791 11792 /* First schedule a cleanup up of old configuration */ 11793 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 11794 if (rc < 0) { 11795 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 11796 return rc; 11797 } 11798 11799 netdev_for_each_uc_addr(ha, dev) { 11800 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 11801 BNX2X_UC_LIST_MAC, &ramrod_flags); 11802 if (rc == -EEXIST) { 11803 DP(BNX2X_MSG_SP, 11804 "Failed to schedule ADD operations: %d\n", rc); 11805 /* do not treat adding same MAC as error */ 11806 rc = 0; 11807 11808 } else if (rc < 0) { 11809 11810 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 11811 rc); 11812 return rc; 11813 } 11814 } 11815 11816 /* Execute the pending commands */ 11817 __set_bit(RAMROD_CONT, &ramrod_flags); 11818 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 11819 BNX2X_UC_LIST_MAC, &ramrod_flags); 11820 } 11821 11822 static int bnx2x_set_mc_list(struct bnx2x *bp) 11823 { 11824 struct net_device *dev = bp->dev; 11825 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 11826 int rc = 0; 11827 11828 rparam.mcast_obj = &bp->mcast_obj; 11829 11830 /* first, clear all configured multicast MACs */ 11831 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 11832 if (rc < 0) { 11833 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); 11834 return rc; 11835 } 11836 11837 /* then, configure a new MACs list */ 11838 if (netdev_mc_count(dev)) { 11839 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 11840 if (rc) { 11841 BNX2X_ERR("Failed to create multicast MACs list: %d\n", 11842 rc); 11843 return rc; 11844 } 11845 11846 /* Now add the new MACs */ 11847 rc = bnx2x_config_mcast(bp, &rparam, 11848 BNX2X_MCAST_CMD_ADD); 11849 if (rc < 0) 11850 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 11851 rc); 11852 11853 bnx2x_free_mcast_macs_list(&rparam); 11854 } 11855 11856 return rc; 11857 } 11858 11859 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 11860 void bnx2x_set_rx_mode(struct net_device *dev) 11861 { 11862 struct bnx2x *bp = netdev_priv(dev); 11863 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 11864 11865 if (bp->state != BNX2X_STATE_OPEN) { 11866 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 11867 return; 11868 } 11869 11870 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 11871 11872 if (dev->flags & IFF_PROMISC) 11873 rx_mode = BNX2X_RX_MODE_PROMISC; 11874 else if ((dev->flags & IFF_ALLMULTI) || 11875 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 11876 CHIP_IS_E1(bp))) 11877 rx_mode = BNX2X_RX_MODE_ALLMULTI; 11878 else { 11879 if (IS_PF(bp)) { 11880 /* some multicasts */ 11881 if (bnx2x_set_mc_list(bp) < 0) 11882 rx_mode = BNX2X_RX_MODE_ALLMULTI; 11883 11884 if (bnx2x_set_uc_list(bp) < 0) 11885 rx_mode = BNX2X_RX_MODE_PROMISC; 11886 } else { 11887 /* configuring mcast to a vf involves sleeping (when we 11888 * wait for the pf's response). Since this function is 11889 * called from non sleepable context we must schedule 11890 * a work item for this purpose 11891 */ 11892 smp_mb__before_clear_bit(); 11893 set_bit(BNX2X_SP_RTNL_VFPF_MCAST, 11894 &bp->sp_rtnl_state); 11895 smp_mb__after_clear_bit(); 11896 schedule_delayed_work(&bp->sp_rtnl_task, 0); 11897 } 11898 } 11899 11900 bp->rx_mode = rx_mode; 11901 /* handle ISCSI SD mode */ 11902 if (IS_MF_ISCSI_SD(bp)) 11903 bp->rx_mode = BNX2X_RX_MODE_NONE; 11904 11905 /* Schedule the rx_mode command */ 11906 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 11907 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 11908 return; 11909 } 11910 11911 if (IS_PF(bp)) { 11912 bnx2x_set_storm_rx_mode(bp); 11913 } else { 11914 /* configuring rx mode to storms in a vf involves sleeping (when 11915 * we wait for the pf's response). Since this function is 11916 * called from non sleepable context we must schedule 11917 * a work item for this purpose 11918 */ 11919 smp_mb__before_clear_bit(); 11920 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, 11921 &bp->sp_rtnl_state); 11922 smp_mb__after_clear_bit(); 11923 schedule_delayed_work(&bp->sp_rtnl_task, 0); 11924 } 11925 } 11926 11927 /* called with rtnl_lock */ 11928 static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 11929 int devad, u16 addr) 11930 { 11931 struct bnx2x *bp = netdev_priv(netdev); 11932 u16 value; 11933 int rc; 11934 11935 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 11936 prtad, devad, addr); 11937 11938 /* The HW expects different devad if CL22 is used */ 11939 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 11940 11941 bnx2x_acquire_phy_lock(bp); 11942 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 11943 bnx2x_release_phy_lock(bp); 11944 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 11945 11946 if (!rc) 11947 rc = value; 11948 return rc; 11949 } 11950 11951 /* called with rtnl_lock */ 11952 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 11953 u16 addr, u16 value) 11954 { 11955 struct bnx2x *bp = netdev_priv(netdev); 11956 int rc; 11957 11958 DP(NETIF_MSG_LINK, 11959 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", 11960 prtad, devad, addr, value); 11961 11962 /* The HW expects different devad if CL22 is used */ 11963 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 11964 11965 bnx2x_acquire_phy_lock(bp); 11966 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 11967 bnx2x_release_phy_lock(bp); 11968 return rc; 11969 } 11970 11971 /* called with rtnl_lock */ 11972 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 11973 { 11974 struct bnx2x *bp = netdev_priv(dev); 11975 struct mii_ioctl_data *mdio = if_mii(ifr); 11976 11977 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 11978 mdio->phy_id, mdio->reg_num, mdio->val_in); 11979 11980 if (!netif_running(dev)) 11981 return -EAGAIN; 11982 11983 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 11984 } 11985 11986 #ifdef CONFIG_NET_POLL_CONTROLLER 11987 static void poll_bnx2x(struct net_device *dev) 11988 { 11989 struct bnx2x *bp = netdev_priv(dev); 11990 int i; 11991 11992 for_each_eth_queue(bp, i) { 11993 struct bnx2x_fastpath *fp = &bp->fp[i]; 11994 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 11995 } 11996 } 11997 #endif 11998 11999 static int bnx2x_validate_addr(struct net_device *dev) 12000 { 12001 struct bnx2x *bp = netdev_priv(dev); 12002 12003 /* query the bulletin board for mac address configured by the PF */ 12004 if (IS_VF(bp)) 12005 bnx2x_sample_bulletin(bp); 12006 12007 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { 12008 BNX2X_ERR("Non-valid Ethernet address\n"); 12009 return -EADDRNOTAVAIL; 12010 } 12011 return 0; 12012 } 12013 12014 static const struct net_device_ops bnx2x_netdev_ops = { 12015 .ndo_open = bnx2x_open, 12016 .ndo_stop = bnx2x_close, 12017 .ndo_start_xmit = bnx2x_start_xmit, 12018 .ndo_select_queue = bnx2x_select_queue, 12019 .ndo_set_rx_mode = bnx2x_set_rx_mode, 12020 .ndo_set_mac_address = bnx2x_change_mac_addr, 12021 .ndo_validate_addr = bnx2x_validate_addr, 12022 .ndo_do_ioctl = bnx2x_ioctl, 12023 .ndo_change_mtu = bnx2x_change_mtu, 12024 .ndo_fix_features = bnx2x_fix_features, 12025 .ndo_set_features = bnx2x_set_features, 12026 .ndo_tx_timeout = bnx2x_tx_timeout, 12027 #ifdef CONFIG_NET_POLL_CONTROLLER 12028 .ndo_poll_controller = poll_bnx2x, 12029 #endif 12030 .ndo_setup_tc = bnx2x_setup_tc, 12031 #ifdef CONFIG_BNX2X_SRIOV 12032 .ndo_set_vf_mac = bnx2x_set_vf_mac, 12033 .ndo_set_vf_vlan = bnx2x_set_vf_vlan, 12034 .ndo_get_vf_config = bnx2x_get_vf_config, 12035 #endif 12036 #ifdef NETDEV_FCOE_WWNN 12037 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 12038 #endif 12039 12040 #ifdef CONFIG_NET_RX_BUSY_POLL 12041 .ndo_busy_poll = bnx2x_low_latency_recv, 12042 #endif 12043 }; 12044 12045 static int bnx2x_set_coherency_mask(struct bnx2x *bp) 12046 { 12047 struct device *dev = &bp->pdev->dev; 12048 12049 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 12050 bp->flags |= USING_DAC_FLAG; 12051 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 12052 dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); 12053 return -EIO; 12054 } 12055 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 12056 dev_err(dev, "System does not support DMA, aborting\n"); 12057 return -EIO; 12058 } 12059 12060 return 0; 12061 } 12062 12063 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, 12064 struct net_device *dev, unsigned long board_type) 12065 { 12066 int rc; 12067 u32 pci_cfg_dword; 12068 bool chip_is_e1x = (board_type == BCM57710 || 12069 board_type == BCM57711 || 12070 board_type == BCM57711E); 12071 12072 SET_NETDEV_DEV(dev, &pdev->dev); 12073 12074 bp->dev = dev; 12075 bp->pdev = pdev; 12076 12077 rc = pci_enable_device(pdev); 12078 if (rc) { 12079 dev_err(&bp->pdev->dev, 12080 "Cannot enable PCI device, aborting\n"); 12081 goto err_out; 12082 } 12083 12084 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 12085 dev_err(&bp->pdev->dev, 12086 "Cannot find PCI device base address, aborting\n"); 12087 rc = -ENODEV; 12088 goto err_out_disable; 12089 } 12090 12091 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 12092 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); 12093 rc = -ENODEV; 12094 goto err_out_disable; 12095 } 12096 12097 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); 12098 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == 12099 PCICFG_REVESION_ID_ERROR_VAL) { 12100 pr_err("PCI device error, probably due to fan failure, aborting\n"); 12101 rc = -ENODEV; 12102 goto err_out_disable; 12103 } 12104 12105 if (atomic_read(&pdev->enable_cnt) == 1) { 12106 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 12107 if (rc) { 12108 dev_err(&bp->pdev->dev, 12109 "Cannot obtain PCI resources, aborting\n"); 12110 goto err_out_disable; 12111 } 12112 12113 pci_set_master(pdev); 12114 pci_save_state(pdev); 12115 } 12116 12117 if (IS_PF(bp)) { 12118 bp->pm_cap = pdev->pm_cap; 12119 if (bp->pm_cap == 0) { 12120 dev_err(&bp->pdev->dev, 12121 "Cannot find power management capability, aborting\n"); 12122 rc = -EIO; 12123 goto err_out_release; 12124 } 12125 } 12126 12127 if (!pci_is_pcie(pdev)) { 12128 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 12129 rc = -EIO; 12130 goto err_out_release; 12131 } 12132 12133 rc = bnx2x_set_coherency_mask(bp); 12134 if (rc) 12135 goto err_out_release; 12136 12137 dev->mem_start = pci_resource_start(pdev, 0); 12138 dev->base_addr = dev->mem_start; 12139 dev->mem_end = pci_resource_end(pdev, 0); 12140 12141 dev->irq = pdev->irq; 12142 12143 bp->regview = pci_ioremap_bar(pdev, 0); 12144 if (!bp->regview) { 12145 dev_err(&bp->pdev->dev, 12146 "Cannot map register space, aborting\n"); 12147 rc = -ENOMEM; 12148 goto err_out_release; 12149 } 12150 12151 /* In E1/E1H use pci device function given by kernel. 12152 * In E2/E3 read physical function from ME register since these chips 12153 * support Physical Device Assignment where kernel BDF maybe arbitrary 12154 * (depending on hypervisor). 12155 */ 12156 if (chip_is_e1x) { 12157 bp->pf_num = PCI_FUNC(pdev->devfn); 12158 } else { 12159 /* chip is E2/3*/ 12160 pci_read_config_dword(bp->pdev, 12161 PCICFG_ME_REGISTER, &pci_cfg_dword); 12162 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 12163 ME_REG_ABS_PF_NUM_SHIFT); 12164 } 12165 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); 12166 12167 /* clean indirect addresses */ 12168 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 12169 PCICFG_VENDOR_ID_OFFSET); 12170 /* 12171 * Clean the following indirect addresses for all functions since it 12172 * is not used by the driver. 12173 */ 12174 if (IS_PF(bp)) { 12175 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 12176 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 12177 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 12178 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 12179 12180 if (chip_is_e1x) { 12181 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 12182 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 12183 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 12184 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 12185 } 12186 12187 /* Enable internal target-read (in case we are probed after PF 12188 * FLR). Must be done prior to any BAR read access. Only for 12189 * 57712 and up 12190 */ 12191 if (!chip_is_e1x) 12192 REG_WR(bp, 12193 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 12194 } 12195 12196 dev->watchdog_timeo = TX_TIMEOUT; 12197 12198 dev->netdev_ops = &bnx2x_netdev_ops; 12199 bnx2x_set_ethtool_ops(bp, dev); 12200 12201 dev->priv_flags |= IFF_UNICAST_FLT; 12202 12203 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 12204 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 12205 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | 12206 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; 12207 if (!CHIP_IS_E1x(bp)) { 12208 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; 12209 dev->hw_enc_features = 12210 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 12211 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 12212 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; 12213 } 12214 12215 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 12216 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 12217 12218 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; 12219 if (bp->flags & USING_DAC_FLAG) 12220 dev->features |= NETIF_F_HIGHDMA; 12221 12222 /* Add Loopback capability to the device */ 12223 dev->hw_features |= NETIF_F_LOOPBACK; 12224 12225 #ifdef BCM_DCBNL 12226 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 12227 #endif 12228 12229 /* get_port_hwinfo() will set prtad and mmds properly */ 12230 bp->mdio.prtad = MDIO_PRTAD_NONE; 12231 bp->mdio.mmds = 0; 12232 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 12233 bp->mdio.dev = dev; 12234 bp->mdio.mdio_read = bnx2x_mdio_read; 12235 bp->mdio.mdio_write = bnx2x_mdio_write; 12236 12237 return 0; 12238 12239 err_out_release: 12240 if (atomic_read(&pdev->enable_cnt) == 1) 12241 pci_release_regions(pdev); 12242 12243 err_out_disable: 12244 pci_disable_device(pdev); 12245 pci_set_drvdata(pdev, NULL); 12246 12247 err_out: 12248 return rc; 12249 } 12250 12251 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, 12252 enum bnx2x_pci_bus_speed *speed) 12253 { 12254 u32 link_speed, val = 0; 12255 12256 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val); 12257 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 12258 12259 link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 12260 12261 switch (link_speed) { 12262 case 3: 12263 *speed = BNX2X_PCI_LINK_SPEED_8000; 12264 break; 12265 case 2: 12266 *speed = BNX2X_PCI_LINK_SPEED_5000; 12267 break; 12268 default: 12269 *speed = BNX2X_PCI_LINK_SPEED_2500; 12270 } 12271 } 12272 12273 static int bnx2x_check_firmware(struct bnx2x *bp) 12274 { 12275 const struct firmware *firmware = bp->firmware; 12276 struct bnx2x_fw_file_hdr *fw_hdr; 12277 struct bnx2x_fw_file_section *sections; 12278 u32 offset, len, num_ops; 12279 __be16 *ops_offsets; 12280 int i; 12281 const u8 *fw_ver; 12282 12283 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { 12284 BNX2X_ERR("Wrong FW size\n"); 12285 return -EINVAL; 12286 } 12287 12288 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 12289 sections = (struct bnx2x_fw_file_section *)fw_hdr; 12290 12291 /* Make sure none of the offsets and sizes make us read beyond 12292 * the end of the firmware data */ 12293 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 12294 offset = be32_to_cpu(sections[i].offset); 12295 len = be32_to_cpu(sections[i].len); 12296 if (offset + len > firmware->size) { 12297 BNX2X_ERR("Section %d length is out of bounds\n", i); 12298 return -EINVAL; 12299 } 12300 } 12301 12302 /* Likewise for the init_ops offsets */ 12303 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 12304 ops_offsets = (__force __be16 *)(firmware->data + offset); 12305 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 12306 12307 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 12308 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 12309 BNX2X_ERR("Section offset %d is out of bounds\n", i); 12310 return -EINVAL; 12311 } 12312 } 12313 12314 /* Check FW version */ 12315 offset = be32_to_cpu(fw_hdr->fw_version.offset); 12316 fw_ver = firmware->data + offset; 12317 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 12318 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 12319 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 12320 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 12321 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 12322 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], 12323 BCM_5710_FW_MAJOR_VERSION, 12324 BCM_5710_FW_MINOR_VERSION, 12325 BCM_5710_FW_REVISION_VERSION, 12326 BCM_5710_FW_ENGINEERING_VERSION); 12327 return -EINVAL; 12328 } 12329 12330 return 0; 12331 } 12332 12333 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 12334 { 12335 const __be32 *source = (const __be32 *)_source; 12336 u32 *target = (u32 *)_target; 12337 u32 i; 12338 12339 for (i = 0; i < n/4; i++) 12340 target[i] = be32_to_cpu(source[i]); 12341 } 12342 12343 /* 12344 Ops array is stored in the following format: 12345 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 12346 */ 12347 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 12348 { 12349 const __be32 *source = (const __be32 *)_source; 12350 struct raw_op *target = (struct raw_op *)_target; 12351 u32 i, j, tmp; 12352 12353 for (i = 0, j = 0; i < n/8; i++, j += 2) { 12354 tmp = be32_to_cpu(source[j]); 12355 target[i].op = (tmp >> 24) & 0xff; 12356 target[i].offset = tmp & 0xffffff; 12357 target[i].raw_data = be32_to_cpu(source[j + 1]); 12358 } 12359 } 12360 12361 /* IRO array is stored in the following format: 12362 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 12363 */ 12364 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 12365 { 12366 const __be32 *source = (const __be32 *)_source; 12367 struct iro *target = (struct iro *)_target; 12368 u32 i, j, tmp; 12369 12370 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 12371 target[i].base = be32_to_cpu(source[j]); 12372 j++; 12373 tmp = be32_to_cpu(source[j]); 12374 target[i].m1 = (tmp >> 16) & 0xffff; 12375 target[i].m2 = tmp & 0xffff; 12376 j++; 12377 tmp = be32_to_cpu(source[j]); 12378 target[i].m3 = (tmp >> 16) & 0xffff; 12379 target[i].size = tmp & 0xffff; 12380 j++; 12381 } 12382 } 12383 12384 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 12385 { 12386 const __be16 *source = (const __be16 *)_source; 12387 u16 *target = (u16 *)_target; 12388 u32 i; 12389 12390 for (i = 0; i < n/2; i++) 12391 target[i] = be16_to_cpu(source[i]); 12392 } 12393 12394 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 12395 do { \ 12396 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 12397 bp->arr = kmalloc(len, GFP_KERNEL); \ 12398 if (!bp->arr) \ 12399 goto lbl; \ 12400 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 12401 (u8 *)bp->arr, len); \ 12402 } while (0) 12403 12404 static int bnx2x_init_firmware(struct bnx2x *bp) 12405 { 12406 const char *fw_file_name; 12407 struct bnx2x_fw_file_hdr *fw_hdr; 12408 int rc; 12409 12410 if (bp->firmware) 12411 return 0; 12412 12413 if (CHIP_IS_E1(bp)) 12414 fw_file_name = FW_FILE_NAME_E1; 12415 else if (CHIP_IS_E1H(bp)) 12416 fw_file_name = FW_FILE_NAME_E1H; 12417 else if (!CHIP_IS_E1x(bp)) 12418 fw_file_name = FW_FILE_NAME_E2; 12419 else { 12420 BNX2X_ERR("Unsupported chip revision\n"); 12421 return -EINVAL; 12422 } 12423 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 12424 12425 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 12426 if (rc) { 12427 BNX2X_ERR("Can't load firmware file %s\n", 12428 fw_file_name); 12429 goto request_firmware_exit; 12430 } 12431 12432 rc = bnx2x_check_firmware(bp); 12433 if (rc) { 12434 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 12435 goto request_firmware_exit; 12436 } 12437 12438 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 12439 12440 /* Initialize the pointers to the init arrays */ 12441 /* Blob */ 12442 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 12443 12444 /* Opcodes */ 12445 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 12446 12447 /* Offsets */ 12448 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 12449 be16_to_cpu_n); 12450 12451 /* STORMs firmware */ 12452 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12453 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 12454 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 12455 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 12456 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12457 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 12458 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 12459 be32_to_cpu(fw_hdr->usem_pram_data.offset); 12460 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12461 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 12462 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 12463 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 12464 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 12465 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 12466 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 12467 be32_to_cpu(fw_hdr->csem_pram_data.offset); 12468 /* IRO */ 12469 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 12470 12471 return 0; 12472 12473 iro_alloc_err: 12474 kfree(bp->init_ops_offsets); 12475 init_offsets_alloc_err: 12476 kfree(bp->init_ops); 12477 init_ops_alloc_err: 12478 kfree(bp->init_data); 12479 request_firmware_exit: 12480 release_firmware(bp->firmware); 12481 bp->firmware = NULL; 12482 12483 return rc; 12484 } 12485 12486 static void bnx2x_release_firmware(struct bnx2x *bp) 12487 { 12488 kfree(bp->init_ops_offsets); 12489 kfree(bp->init_ops); 12490 kfree(bp->init_data); 12491 release_firmware(bp->firmware); 12492 bp->firmware = NULL; 12493 } 12494 12495 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 12496 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 12497 .init_hw_cmn = bnx2x_init_hw_common, 12498 .init_hw_port = bnx2x_init_hw_port, 12499 .init_hw_func = bnx2x_init_hw_func, 12500 12501 .reset_hw_cmn = bnx2x_reset_common, 12502 .reset_hw_port = bnx2x_reset_port, 12503 .reset_hw_func = bnx2x_reset_func, 12504 12505 .gunzip_init = bnx2x_gunzip_init, 12506 .gunzip_end = bnx2x_gunzip_end, 12507 12508 .init_fw = bnx2x_init_firmware, 12509 .release_fw = bnx2x_release_firmware, 12510 }; 12511 12512 void bnx2x__init_func_obj(struct bnx2x *bp) 12513 { 12514 /* Prepare DMAE related driver resources */ 12515 bnx2x_setup_dmae(bp); 12516 12517 bnx2x_init_func_obj(bp, &bp->func_obj, 12518 bnx2x_sp(bp, func_rdata), 12519 bnx2x_sp_mapping(bp, func_rdata), 12520 bnx2x_sp(bp, func_afex_rdata), 12521 bnx2x_sp_mapping(bp, func_afex_rdata), 12522 &bnx2x_func_sp_drv); 12523 } 12524 12525 /* must be called after sriov-enable */ 12526 static int bnx2x_set_qm_cid_count(struct bnx2x *bp) 12527 { 12528 int cid_count = BNX2X_L2_MAX_CID(bp); 12529 12530 if (IS_SRIOV(bp)) 12531 cid_count += BNX2X_VF_CIDS; 12532 12533 if (CNIC_SUPPORT(bp)) 12534 cid_count += CNIC_CID_MAX; 12535 12536 return roundup(cid_count, QM_CID_ROUND); 12537 } 12538 12539 /** 12540 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 12541 * 12542 * @dev: pci device 12543 * 12544 */ 12545 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, 12546 int cnic_cnt, bool is_vf) 12547 { 12548 int pos, index; 12549 u16 control = 0; 12550 12551 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 12552 12553 /* 12554 * If MSI-X is not supported - return number of SBs needed to support 12555 * one fast path queue: one FP queue + SB for CNIC 12556 */ 12557 if (!pos) { 12558 dev_info(&pdev->dev, "no msix capability found\n"); 12559 return 1 + cnic_cnt; 12560 } 12561 dev_info(&pdev->dev, "msix capability found\n"); 12562 12563 /* 12564 * The value in the PCI configuration space is the index of the last 12565 * entry, namely one less than the actual size of the table, which is 12566 * exactly what we want to return from this function: number of all SBs 12567 * without the default SB. 12568 * For VFs there is no default SB, then we return (index+1). 12569 */ 12570 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 12571 12572 index = control & PCI_MSIX_FLAGS_QSIZE; 12573 12574 return is_vf ? index + 1 : index; 12575 } 12576 12577 static int set_max_cos_est(int chip_id) 12578 { 12579 switch (chip_id) { 12580 case BCM57710: 12581 case BCM57711: 12582 case BCM57711E: 12583 return BNX2X_MULTI_TX_COS_E1X; 12584 case BCM57712: 12585 case BCM57712_MF: 12586 case BCM57712_VF: 12587 return BNX2X_MULTI_TX_COS_E2_E3A0; 12588 case BCM57800: 12589 case BCM57800_MF: 12590 case BCM57800_VF: 12591 case BCM57810: 12592 case BCM57810_MF: 12593 case BCM57840_4_10: 12594 case BCM57840_2_20: 12595 case BCM57840_O: 12596 case BCM57840_MFO: 12597 case BCM57810_VF: 12598 case BCM57840_MF: 12599 case BCM57840_VF: 12600 case BCM57811: 12601 case BCM57811_MF: 12602 case BCM57811_VF: 12603 return BNX2X_MULTI_TX_COS_E3B0; 12604 return 1; 12605 default: 12606 pr_err("Unknown board_type (%d), aborting\n", chip_id); 12607 return -ENODEV; 12608 } 12609 } 12610 12611 static int set_is_vf(int chip_id) 12612 { 12613 switch (chip_id) { 12614 case BCM57712_VF: 12615 case BCM57800_VF: 12616 case BCM57810_VF: 12617 case BCM57840_VF: 12618 case BCM57811_VF: 12619 return true; 12620 default: 12621 return false; 12622 } 12623 } 12624 12625 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); 12626 12627 static int bnx2x_init_one(struct pci_dev *pdev, 12628 const struct pci_device_id *ent) 12629 { 12630 struct net_device *dev = NULL; 12631 struct bnx2x *bp; 12632 int pcie_width; 12633 enum bnx2x_pci_bus_speed pcie_speed; 12634 int rc, max_non_def_sbs; 12635 int rx_count, tx_count, rss_count, doorbell_size; 12636 int max_cos_est; 12637 bool is_vf; 12638 int cnic_cnt; 12639 12640 /* An estimated maximum supported CoS number according to the chip 12641 * version. 12642 * We will try to roughly estimate the maximum number of CoSes this chip 12643 * may support in order to minimize the memory allocated for Tx 12644 * netdev_queue's. This number will be accurately calculated during the 12645 * initialization of bp->max_cos based on the chip versions AND chip 12646 * revision in the bnx2x_init_bp(). 12647 */ 12648 max_cos_est = set_max_cos_est(ent->driver_data); 12649 if (max_cos_est < 0) 12650 return max_cos_est; 12651 is_vf = set_is_vf(ent->driver_data); 12652 cnic_cnt = is_vf ? 0 : 1; 12653 12654 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf); 12655 12656 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 12657 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt; 12658 12659 if (rss_count < 1) 12660 return -EINVAL; 12661 12662 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 12663 rx_count = rss_count + cnic_cnt; 12664 12665 /* Maximum number of netdev Tx queues: 12666 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 12667 */ 12668 tx_count = rss_count * max_cos_est + cnic_cnt; 12669 12670 /* dev zeroed in init_etherdev */ 12671 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 12672 if (!dev) 12673 return -ENOMEM; 12674 12675 bp = netdev_priv(dev); 12676 12677 bp->flags = 0; 12678 if (is_vf) 12679 bp->flags |= IS_VF_FLAG; 12680 12681 bp->igu_sb_cnt = max_non_def_sbs; 12682 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; 12683 bp->msg_enable = debug; 12684 bp->cnic_support = cnic_cnt; 12685 bp->cnic_probe = bnx2x_cnic_probe; 12686 12687 pci_set_drvdata(pdev, dev); 12688 12689 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); 12690 if (rc < 0) { 12691 free_netdev(dev); 12692 return rc; 12693 } 12694 12695 BNX2X_DEV_INFO("This is a %s function\n", 12696 IS_PF(bp) ? "physical" : "virtual"); 12697 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); 12698 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); 12699 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", 12700 tx_count, rx_count); 12701 12702 rc = bnx2x_init_bp(bp); 12703 if (rc) 12704 goto init_one_exit; 12705 12706 /* Map doorbells here as we need the real value of bp->max_cos which 12707 * is initialized in bnx2x_init_bp() to determine the number of 12708 * l2 connections. 12709 */ 12710 if (IS_VF(bp)) { 12711 bp->doorbells = bnx2x_vf_doorbells(bp); 12712 rc = bnx2x_vf_pci_alloc(bp); 12713 if (rc) 12714 goto init_one_exit; 12715 } else { 12716 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); 12717 if (doorbell_size > pci_resource_len(pdev, 2)) { 12718 dev_err(&bp->pdev->dev, 12719 "Cannot map doorbells, bar size too small, aborting\n"); 12720 rc = -ENOMEM; 12721 goto init_one_exit; 12722 } 12723 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 12724 doorbell_size); 12725 } 12726 if (!bp->doorbells) { 12727 dev_err(&bp->pdev->dev, 12728 "Cannot map doorbell space, aborting\n"); 12729 rc = -ENOMEM; 12730 goto init_one_exit; 12731 } 12732 12733 if (IS_VF(bp)) { 12734 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); 12735 if (rc) 12736 goto init_one_exit; 12737 } 12738 12739 /* Enable SRIOV if capability found in configuration space */ 12740 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); 12741 if (rc) 12742 goto init_one_exit; 12743 12744 /* calc qm_cid_count */ 12745 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 12746 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); 12747 12748 /* disable FCOE L2 queue for E1x*/ 12749 if (CHIP_IS_E1x(bp)) 12750 bp->flags |= NO_FCOE_FLAG; 12751 12752 /* Set bp->num_queues for MSI-X mode*/ 12753 bnx2x_set_num_queues(bp); 12754 12755 /* Configure interrupt mode: try to enable MSI-X/MSI if 12756 * needed. 12757 */ 12758 rc = bnx2x_set_int_mode(bp); 12759 if (rc) { 12760 dev_err(&pdev->dev, "Cannot set interrupts\n"); 12761 goto init_one_exit; 12762 } 12763 BNX2X_DEV_INFO("set interrupts successfully\n"); 12764 12765 /* register the net device */ 12766 rc = register_netdev(dev); 12767 if (rc) { 12768 dev_err(&pdev->dev, "Cannot register net device\n"); 12769 goto init_one_exit; 12770 } 12771 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); 12772 12773 if (!NO_FCOE(bp)) { 12774 /* Add storage MAC address */ 12775 rtnl_lock(); 12776 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 12777 rtnl_unlock(); 12778 } 12779 12780 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 12781 BNX2X_DEV_INFO("got pcie width %d and speed %d\n", 12782 pcie_width, pcie_speed); 12783 12784 BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 12785 board_info[ent->driver_data].name, 12786 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 12787 pcie_width, 12788 pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" : 12789 pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" : 12790 pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" : 12791 "Unknown", 12792 dev->base_addr, bp->pdev->irq, dev->dev_addr); 12793 12794 return 0; 12795 12796 init_one_exit: 12797 if (bp->regview) 12798 iounmap(bp->regview); 12799 12800 if (IS_PF(bp) && bp->doorbells) 12801 iounmap(bp->doorbells); 12802 12803 free_netdev(dev); 12804 12805 if (atomic_read(&pdev->enable_cnt) == 1) 12806 pci_release_regions(pdev); 12807 12808 pci_disable_device(pdev); 12809 pci_set_drvdata(pdev, NULL); 12810 12811 return rc; 12812 } 12813 12814 static void __bnx2x_remove(struct pci_dev *pdev, 12815 struct net_device *dev, 12816 struct bnx2x *bp, 12817 bool remove_netdev) 12818 { 12819 /* Delete storage MAC address */ 12820 if (!NO_FCOE(bp)) { 12821 rtnl_lock(); 12822 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 12823 rtnl_unlock(); 12824 } 12825 12826 #ifdef BCM_DCBNL 12827 /* Delete app tlvs from dcbnl */ 12828 bnx2x_dcbnl_update_applist(bp, true); 12829 #endif 12830 12831 if (IS_PF(bp) && 12832 !BP_NOMCP(bp) && 12833 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) 12834 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); 12835 12836 /* Close the interface - either directly or implicitly */ 12837 if (remove_netdev) { 12838 unregister_netdev(dev); 12839 } else { 12840 rtnl_lock(); 12841 dev_close(dev); 12842 rtnl_unlock(); 12843 } 12844 12845 bnx2x_iov_remove_one(bp); 12846 12847 /* Power on: we can't let PCI layer write to us while we are in D3 */ 12848 if (IS_PF(bp)) 12849 bnx2x_set_power_state(bp, PCI_D0); 12850 12851 /* Disable MSI/MSI-X */ 12852 bnx2x_disable_msi(bp); 12853 12854 /* Power off */ 12855 if (IS_PF(bp)) 12856 bnx2x_set_power_state(bp, PCI_D3hot); 12857 12858 /* Make sure RESET task is not scheduled before continuing */ 12859 cancel_delayed_work_sync(&bp->sp_rtnl_task); 12860 12861 /* send message via vfpf channel to release the resources of this vf */ 12862 if (IS_VF(bp)) 12863 bnx2x_vfpf_release(bp); 12864 12865 /* Assumes no further PCIe PM changes will occur */ 12866 if (system_state == SYSTEM_POWER_OFF) { 12867 pci_wake_from_d3(pdev, bp->wol); 12868 pci_set_power_state(pdev, PCI_D3hot); 12869 } 12870 12871 if (bp->regview) 12872 iounmap(bp->regview); 12873 12874 /* for vf doorbells are part of the regview and were unmapped along with 12875 * it. FW is only loaded by PF. 12876 */ 12877 if (IS_PF(bp)) { 12878 if (bp->doorbells) 12879 iounmap(bp->doorbells); 12880 12881 bnx2x_release_firmware(bp); 12882 } 12883 bnx2x_free_mem_bp(bp); 12884 12885 if (remove_netdev) 12886 free_netdev(dev); 12887 12888 if (atomic_read(&pdev->enable_cnt) == 1) 12889 pci_release_regions(pdev); 12890 12891 pci_disable_device(pdev); 12892 pci_set_drvdata(pdev, NULL); 12893 } 12894 12895 static void bnx2x_remove_one(struct pci_dev *pdev) 12896 { 12897 struct net_device *dev = pci_get_drvdata(pdev); 12898 struct bnx2x *bp; 12899 12900 if (!dev) { 12901 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 12902 return; 12903 } 12904 bp = netdev_priv(dev); 12905 12906 __bnx2x_remove(pdev, dev, bp, true); 12907 } 12908 12909 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 12910 { 12911 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; 12912 12913 bp->rx_mode = BNX2X_RX_MODE_NONE; 12914 12915 if (CNIC_LOADED(bp)) 12916 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 12917 12918 /* Stop Tx */ 12919 bnx2x_tx_disable(bp); 12920 /* Delete all NAPI objects */ 12921 bnx2x_del_all_napi(bp); 12922 if (CNIC_LOADED(bp)) 12923 bnx2x_del_all_napi_cnic(bp); 12924 netdev_reset_tc(bp->dev); 12925 12926 del_timer_sync(&bp->timer); 12927 cancel_delayed_work(&bp->sp_task); 12928 cancel_delayed_work(&bp->period_task); 12929 12930 spin_lock_bh(&bp->stats_lock); 12931 bp->stats_state = STATS_STATE_DISABLED; 12932 spin_unlock_bh(&bp->stats_lock); 12933 12934 bnx2x_save_statistics(bp); 12935 12936 netif_carrier_off(bp->dev); 12937 12938 return 0; 12939 } 12940 12941 /** 12942 * bnx2x_io_error_detected - called when PCI error is detected 12943 * @pdev: Pointer to PCI device 12944 * @state: The current pci connection state 12945 * 12946 * This function is called after a PCI bus error affecting 12947 * this device has been detected. 12948 */ 12949 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 12950 pci_channel_state_t state) 12951 { 12952 struct net_device *dev = pci_get_drvdata(pdev); 12953 struct bnx2x *bp = netdev_priv(dev); 12954 12955 rtnl_lock(); 12956 12957 BNX2X_ERR("IO error detected\n"); 12958 12959 netif_device_detach(dev); 12960 12961 if (state == pci_channel_io_perm_failure) { 12962 rtnl_unlock(); 12963 return PCI_ERS_RESULT_DISCONNECT; 12964 } 12965 12966 if (netif_running(dev)) 12967 bnx2x_eeh_nic_unload(bp); 12968 12969 bnx2x_prev_path_mark_eeh(bp); 12970 12971 pci_disable_device(pdev); 12972 12973 rtnl_unlock(); 12974 12975 /* Request a slot reset */ 12976 return PCI_ERS_RESULT_NEED_RESET; 12977 } 12978 12979 /** 12980 * bnx2x_io_slot_reset - called after the PCI bus has been reset 12981 * @pdev: Pointer to PCI device 12982 * 12983 * Restart the card from scratch, as if from a cold-boot. 12984 */ 12985 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 12986 { 12987 struct net_device *dev = pci_get_drvdata(pdev); 12988 struct bnx2x *bp = netdev_priv(dev); 12989 int i; 12990 12991 rtnl_lock(); 12992 BNX2X_ERR("IO slot reset initializing...\n"); 12993 if (pci_enable_device(pdev)) { 12994 dev_err(&pdev->dev, 12995 "Cannot re-enable PCI device after reset\n"); 12996 rtnl_unlock(); 12997 return PCI_ERS_RESULT_DISCONNECT; 12998 } 12999 13000 pci_set_master(pdev); 13001 pci_restore_state(pdev); 13002 pci_save_state(pdev); 13003 13004 if (netif_running(dev)) 13005 bnx2x_set_power_state(bp, PCI_D0); 13006 13007 if (netif_running(dev)) { 13008 BNX2X_ERR("IO slot reset --> driver unload\n"); 13009 13010 /* MCP should have been reset; Need to wait for validity */ 13011 bnx2x_init_shmem(bp); 13012 13013 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { 13014 u32 v; 13015 13016 v = SHMEM2_RD(bp, 13017 drv_capabilities_flag[BP_FW_MB_IDX(bp)]); 13018 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], 13019 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); 13020 } 13021 bnx2x_drain_tx_queues(bp); 13022 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); 13023 bnx2x_netif_stop(bp, 1); 13024 bnx2x_free_irq(bp); 13025 13026 /* Report UNLOAD_DONE to MCP */ 13027 bnx2x_send_unload_done(bp, true); 13028 13029 bp->sp_state = 0; 13030 bp->port.pmf = 0; 13031 13032 bnx2x_prev_unload(bp); 13033 13034 /* We should have reseted the engine, so It's fair to 13035 * assume the FW will no longer write to the bnx2x driver. 13036 */ 13037 bnx2x_squeeze_objects(bp); 13038 bnx2x_free_skbs(bp); 13039 for_each_rx_queue(bp, i) 13040 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 13041 bnx2x_free_fp_mem(bp); 13042 bnx2x_free_mem(bp); 13043 13044 bp->state = BNX2X_STATE_CLOSED; 13045 } 13046 13047 rtnl_unlock(); 13048 13049 return PCI_ERS_RESULT_RECOVERED; 13050 } 13051 13052 /** 13053 * bnx2x_io_resume - called when traffic can start flowing again 13054 * @pdev: Pointer to PCI device 13055 * 13056 * This callback is called when the error recovery driver tells us that 13057 * its OK to resume normal operation. 13058 */ 13059 static void bnx2x_io_resume(struct pci_dev *pdev) 13060 { 13061 struct net_device *dev = pci_get_drvdata(pdev); 13062 struct bnx2x *bp = netdev_priv(dev); 13063 13064 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 13065 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); 13066 return; 13067 } 13068 13069 rtnl_lock(); 13070 13071 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 13072 DRV_MSG_SEQ_NUMBER_MASK; 13073 13074 if (netif_running(dev)) 13075 bnx2x_nic_load(bp, LOAD_NORMAL); 13076 13077 netif_device_attach(dev); 13078 13079 rtnl_unlock(); 13080 } 13081 13082 static const struct pci_error_handlers bnx2x_err_handler = { 13083 .error_detected = bnx2x_io_error_detected, 13084 .slot_reset = bnx2x_io_slot_reset, 13085 .resume = bnx2x_io_resume, 13086 }; 13087 13088 static void bnx2x_shutdown(struct pci_dev *pdev) 13089 { 13090 struct net_device *dev = pci_get_drvdata(pdev); 13091 struct bnx2x *bp; 13092 13093 if (!dev) 13094 return; 13095 13096 bp = netdev_priv(dev); 13097 if (!bp) 13098 return; 13099 13100 rtnl_lock(); 13101 netif_device_detach(dev); 13102 rtnl_unlock(); 13103 13104 /* Don't remove the netdevice, as there are scenarios which will cause 13105 * the kernel to hang, e.g., when trying to remove bnx2i while the 13106 * rootfs is mounted from SAN. 13107 */ 13108 __bnx2x_remove(pdev, dev, bp, false); 13109 } 13110 13111 static struct pci_driver bnx2x_pci_driver = { 13112 .name = DRV_MODULE_NAME, 13113 .id_table = bnx2x_pci_tbl, 13114 .probe = bnx2x_init_one, 13115 .remove = bnx2x_remove_one, 13116 .suspend = bnx2x_suspend, 13117 .resume = bnx2x_resume, 13118 .err_handler = &bnx2x_err_handler, 13119 #ifdef CONFIG_BNX2X_SRIOV 13120 .sriov_configure = bnx2x_sriov_configure, 13121 #endif 13122 .shutdown = bnx2x_shutdown, 13123 }; 13124 13125 static int __init bnx2x_init(void) 13126 { 13127 int ret; 13128 13129 pr_info("%s", version); 13130 13131 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 13132 if (bnx2x_wq == NULL) { 13133 pr_err("Cannot create workqueue\n"); 13134 return -ENOMEM; 13135 } 13136 13137 ret = pci_register_driver(&bnx2x_pci_driver); 13138 if (ret) { 13139 pr_err("Cannot register driver\n"); 13140 destroy_workqueue(bnx2x_wq); 13141 } 13142 return ret; 13143 } 13144 13145 static void __exit bnx2x_cleanup(void) 13146 { 13147 struct list_head *pos, *q; 13148 13149 pci_unregister_driver(&bnx2x_pci_driver); 13150 13151 destroy_workqueue(bnx2x_wq); 13152 13153 /* Free globally allocated resources */ 13154 list_for_each_safe(pos, q, &bnx2x_prev_list) { 13155 struct bnx2x_prev_path_list *tmp = 13156 list_entry(pos, struct bnx2x_prev_path_list, list); 13157 list_del(pos); 13158 kfree(tmp); 13159 } 13160 } 13161 13162 void bnx2x_notify_link_changed(struct bnx2x *bp) 13163 { 13164 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 13165 } 13166 13167 module_init(bnx2x_init); 13168 module_exit(bnx2x_cleanup); 13169 13170 /** 13171 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 13172 * 13173 * @bp: driver handle 13174 * @set: set or clear the CAM entry 13175 * 13176 * This function will wait until the ramrod completion returns. 13177 * Return 0 if success, -ENODEV if ramrod doesn't return. 13178 */ 13179 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 13180 { 13181 unsigned long ramrod_flags = 0; 13182 13183 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 13184 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 13185 &bp->iscsi_l2_mac_obj, true, 13186 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 13187 } 13188 13189 /* count denotes the number of new completions we have seen */ 13190 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 13191 { 13192 struct eth_spe *spe; 13193 int cxt_index, cxt_offset; 13194 13195 #ifdef BNX2X_STOP_ON_ERROR 13196 if (unlikely(bp->panic)) 13197 return; 13198 #endif 13199 13200 spin_lock_bh(&bp->spq_lock); 13201 BUG_ON(bp->cnic_spq_pending < count); 13202 bp->cnic_spq_pending -= count; 13203 13204 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 13205 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 13206 & SPE_HDR_CONN_TYPE) >> 13207 SPE_HDR_CONN_TYPE_SHIFT; 13208 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 13209 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 13210 13211 /* Set validation for iSCSI L2 client before sending SETUP 13212 * ramrod 13213 */ 13214 if (type == ETH_CONNECTION_TYPE) { 13215 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { 13216 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / 13217 ILT_PAGE_CIDS; 13218 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - 13219 (cxt_index * ILT_PAGE_CIDS); 13220 bnx2x_set_ctx_validation(bp, 13221 &bp->context[cxt_index]. 13222 vcxt[cxt_offset].eth, 13223 BNX2X_ISCSI_ETH_CID(bp)); 13224 } 13225 } 13226 13227 /* 13228 * There may be not more than 8 L2, not more than 8 L5 SPEs 13229 * and in the air. We also check that number of outstanding 13230 * COMMON ramrods is not more than the EQ and SPQ can 13231 * accommodate. 13232 */ 13233 if (type == ETH_CONNECTION_TYPE) { 13234 if (!atomic_read(&bp->cq_spq_left)) 13235 break; 13236 else 13237 atomic_dec(&bp->cq_spq_left); 13238 } else if (type == NONE_CONNECTION_TYPE) { 13239 if (!atomic_read(&bp->eq_spq_left)) 13240 break; 13241 else 13242 atomic_dec(&bp->eq_spq_left); 13243 } else if ((type == ISCSI_CONNECTION_TYPE) || 13244 (type == FCOE_CONNECTION_TYPE)) { 13245 if (bp->cnic_spq_pending >= 13246 bp->cnic_eth_dev.max_kwqe_pending) 13247 break; 13248 else 13249 bp->cnic_spq_pending++; 13250 } else { 13251 BNX2X_ERR("Unknown SPE type: %d\n", type); 13252 bnx2x_panic(); 13253 break; 13254 } 13255 13256 spe = bnx2x_sp_get_next(bp); 13257 *spe = *bp->cnic_kwq_cons; 13258 13259 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", 13260 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 13261 13262 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 13263 bp->cnic_kwq_cons = bp->cnic_kwq; 13264 else 13265 bp->cnic_kwq_cons++; 13266 } 13267 bnx2x_sp_prod_update(bp); 13268 spin_unlock_bh(&bp->spq_lock); 13269 } 13270 13271 static int bnx2x_cnic_sp_queue(struct net_device *dev, 13272 struct kwqe_16 *kwqes[], u32 count) 13273 { 13274 struct bnx2x *bp = netdev_priv(dev); 13275 int i; 13276 13277 #ifdef BNX2X_STOP_ON_ERROR 13278 if (unlikely(bp->panic)) { 13279 BNX2X_ERR("Can't post to SP queue while panic\n"); 13280 return -EIO; 13281 } 13282 #endif 13283 13284 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 13285 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 13286 BNX2X_ERR("Handling parity error recovery. Try again later\n"); 13287 return -EAGAIN; 13288 } 13289 13290 spin_lock_bh(&bp->spq_lock); 13291 13292 for (i = 0; i < count; i++) { 13293 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 13294 13295 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 13296 break; 13297 13298 *bp->cnic_kwq_prod = *spe; 13299 13300 bp->cnic_kwq_pending++; 13301 13302 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", 13303 spe->hdr.conn_and_cmd_data, spe->hdr.type, 13304 spe->data.update_data_addr.hi, 13305 spe->data.update_data_addr.lo, 13306 bp->cnic_kwq_pending); 13307 13308 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 13309 bp->cnic_kwq_prod = bp->cnic_kwq; 13310 else 13311 bp->cnic_kwq_prod++; 13312 } 13313 13314 spin_unlock_bh(&bp->spq_lock); 13315 13316 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 13317 bnx2x_cnic_sp_post(bp, 0); 13318 13319 return i; 13320 } 13321 13322 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 13323 { 13324 struct cnic_ops *c_ops; 13325 int rc = 0; 13326 13327 mutex_lock(&bp->cnic_mutex); 13328 c_ops = rcu_dereference_protected(bp->cnic_ops, 13329 lockdep_is_held(&bp->cnic_mutex)); 13330 if (c_ops) 13331 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 13332 mutex_unlock(&bp->cnic_mutex); 13333 13334 return rc; 13335 } 13336 13337 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 13338 { 13339 struct cnic_ops *c_ops; 13340 int rc = 0; 13341 13342 rcu_read_lock(); 13343 c_ops = rcu_dereference(bp->cnic_ops); 13344 if (c_ops) 13345 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 13346 rcu_read_unlock(); 13347 13348 return rc; 13349 } 13350 13351 /* 13352 * for commands that have no data 13353 */ 13354 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 13355 { 13356 struct cnic_ctl_info ctl = {0}; 13357 13358 ctl.cmd = cmd; 13359 13360 return bnx2x_cnic_ctl_send(bp, &ctl); 13361 } 13362 13363 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 13364 { 13365 struct cnic_ctl_info ctl = {0}; 13366 13367 /* first we tell CNIC and only then we count this as a completion */ 13368 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 13369 ctl.data.comp.cid = cid; 13370 ctl.data.comp.error = err; 13371 13372 bnx2x_cnic_ctl_send_bh(bp, &ctl); 13373 bnx2x_cnic_sp_post(bp, 0); 13374 } 13375 13376 /* Called with netif_addr_lock_bh() taken. 13377 * Sets an rx_mode config for an iSCSI ETH client. 13378 * Doesn't block. 13379 * Completion should be checked outside. 13380 */ 13381 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 13382 { 13383 unsigned long accept_flags = 0, ramrod_flags = 0; 13384 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 13385 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 13386 13387 if (start) { 13388 /* Start accepting on iSCSI L2 ring. Accept all multicasts 13389 * because it's the only way for UIO Queue to accept 13390 * multicasts (in non-promiscuous mode only one Queue per 13391 * function will receive multicast packets (leading in our 13392 * case). 13393 */ 13394 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 13395 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 13396 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 13397 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 13398 13399 /* Clear STOP_PENDING bit if START is requested */ 13400 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 13401 13402 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 13403 } else 13404 /* Clear START_PENDING bit if STOP is requested */ 13405 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 13406 13407 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 13408 set_bit(sched_state, &bp->sp_state); 13409 else { 13410 __set_bit(RAMROD_RX, &ramrod_flags); 13411 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 13412 ramrod_flags); 13413 } 13414 } 13415 13416 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 13417 { 13418 struct bnx2x *bp = netdev_priv(dev); 13419 int rc = 0; 13420 13421 switch (ctl->cmd) { 13422 case DRV_CTL_CTXTBL_WR_CMD: { 13423 u32 index = ctl->data.io.offset; 13424 dma_addr_t addr = ctl->data.io.dma_addr; 13425 13426 bnx2x_ilt_wr(bp, index, addr); 13427 break; 13428 } 13429 13430 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 13431 int count = ctl->data.credit.credit_count; 13432 13433 bnx2x_cnic_sp_post(bp, count); 13434 break; 13435 } 13436 13437 /* rtnl_lock is held. */ 13438 case DRV_CTL_START_L2_CMD: { 13439 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13440 unsigned long sp_bits = 0; 13441 13442 /* Configure the iSCSI classification object */ 13443 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 13444 cp->iscsi_l2_client_id, 13445 cp->iscsi_l2_cid, BP_FUNC(bp), 13446 bnx2x_sp(bp, mac_rdata), 13447 bnx2x_sp_mapping(bp, mac_rdata), 13448 BNX2X_FILTER_MAC_PENDING, 13449 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 13450 &bp->macs_pool); 13451 13452 /* Set iSCSI MAC address */ 13453 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 13454 if (rc) 13455 break; 13456 13457 mmiowb(); 13458 barrier(); 13459 13460 /* Start accepting on iSCSI L2 ring */ 13461 13462 netif_addr_lock_bh(dev); 13463 bnx2x_set_iscsi_eth_rx_mode(bp, true); 13464 netif_addr_unlock_bh(dev); 13465 13466 /* bits to wait on */ 13467 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 13468 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 13469 13470 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 13471 BNX2X_ERR("rx_mode completion timed out!\n"); 13472 13473 break; 13474 } 13475 13476 /* rtnl_lock is held. */ 13477 case DRV_CTL_STOP_L2_CMD: { 13478 unsigned long sp_bits = 0; 13479 13480 /* Stop accepting on iSCSI L2 ring */ 13481 netif_addr_lock_bh(dev); 13482 bnx2x_set_iscsi_eth_rx_mode(bp, false); 13483 netif_addr_unlock_bh(dev); 13484 13485 /* bits to wait on */ 13486 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 13487 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 13488 13489 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 13490 BNX2X_ERR("rx_mode completion timed out!\n"); 13491 13492 mmiowb(); 13493 barrier(); 13494 13495 /* Unset iSCSI L2 MAC */ 13496 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 13497 BNX2X_ISCSI_ETH_MAC, true); 13498 break; 13499 } 13500 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 13501 int count = ctl->data.credit.credit_count; 13502 13503 smp_mb__before_atomic_inc(); 13504 atomic_add(count, &bp->cq_spq_left); 13505 smp_mb__after_atomic_inc(); 13506 break; 13507 } 13508 case DRV_CTL_ULP_REGISTER_CMD: { 13509 int ulp_type = ctl->data.register_data.ulp_type; 13510 13511 if (CHIP_IS_E3(bp)) { 13512 int idx = BP_FW_MB_IDX(bp); 13513 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 13514 int path = BP_PATH(bp); 13515 int port = BP_PORT(bp); 13516 int i; 13517 u32 scratch_offset; 13518 u32 *host_addr; 13519 13520 /* first write capability to shmem2 */ 13521 if (ulp_type == CNIC_ULP_ISCSI) 13522 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 13523 else if (ulp_type == CNIC_ULP_FCOE) 13524 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 13525 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 13526 13527 if ((ulp_type != CNIC_ULP_FCOE) || 13528 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || 13529 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) 13530 break; 13531 13532 /* if reached here - should write fcoe capabilities */ 13533 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); 13534 if (!scratch_offset) 13535 break; 13536 scratch_offset += offsetof(struct glob_ncsi_oem_data, 13537 fcoe_features[path][port]); 13538 host_addr = (u32 *) &(ctl->data.register_data. 13539 fcoe_features); 13540 for (i = 0; i < sizeof(struct fcoe_capabilities); 13541 i += 4) 13542 REG_WR(bp, scratch_offset + i, 13543 *(host_addr + i/4)); 13544 } 13545 break; 13546 } 13547 13548 case DRV_CTL_ULP_UNREGISTER_CMD: { 13549 int ulp_type = ctl->data.ulp_type; 13550 13551 if (CHIP_IS_E3(bp)) { 13552 int idx = BP_FW_MB_IDX(bp); 13553 u32 cap; 13554 13555 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 13556 if (ulp_type == CNIC_ULP_ISCSI) 13557 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 13558 else if (ulp_type == CNIC_ULP_FCOE) 13559 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 13560 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 13561 } 13562 break; 13563 } 13564 13565 default: 13566 BNX2X_ERR("unknown command %x\n", ctl->cmd); 13567 rc = -EINVAL; 13568 } 13569 13570 return rc; 13571 } 13572 13573 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 13574 { 13575 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13576 13577 if (bp->flags & USING_MSIX_FLAG) { 13578 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 13579 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 13580 cp->irq_arr[0].vector = bp->msix_table[1].vector; 13581 } else { 13582 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 13583 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 13584 } 13585 if (!CHIP_IS_E1x(bp)) 13586 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 13587 else 13588 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 13589 13590 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 13591 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 13592 cp->irq_arr[1].status_blk = bp->def_status_blk; 13593 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 13594 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 13595 13596 cp->num_irq = 2; 13597 } 13598 13599 void bnx2x_setup_cnic_info(struct bnx2x *bp) 13600 { 13601 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13602 13603 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 13604 bnx2x_cid_ilt_lines(bp); 13605 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 13606 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 13607 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 13608 13609 if (NO_ISCSI_OOO(bp)) 13610 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 13611 } 13612 13613 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 13614 void *data) 13615 { 13616 struct bnx2x *bp = netdev_priv(dev); 13617 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13618 int rc; 13619 13620 DP(NETIF_MSG_IFUP, "Register_cnic called\n"); 13621 13622 if (ops == NULL) { 13623 BNX2X_ERR("NULL ops received\n"); 13624 return -EINVAL; 13625 } 13626 13627 if (!CNIC_SUPPORT(bp)) { 13628 BNX2X_ERR("Can't register CNIC when not supported\n"); 13629 return -EOPNOTSUPP; 13630 } 13631 13632 if (!CNIC_LOADED(bp)) { 13633 rc = bnx2x_load_cnic(bp); 13634 if (rc) { 13635 BNX2X_ERR("CNIC-related load failed\n"); 13636 return rc; 13637 } 13638 } 13639 13640 bp->cnic_enabled = true; 13641 13642 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 13643 if (!bp->cnic_kwq) 13644 return -ENOMEM; 13645 13646 bp->cnic_kwq_cons = bp->cnic_kwq; 13647 bp->cnic_kwq_prod = bp->cnic_kwq; 13648 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 13649 13650 bp->cnic_spq_pending = 0; 13651 bp->cnic_kwq_pending = 0; 13652 13653 bp->cnic_data = data; 13654 13655 cp->num_irq = 0; 13656 cp->drv_state |= CNIC_DRV_STATE_REGD; 13657 cp->iro_arr = bp->iro_arr; 13658 13659 bnx2x_setup_cnic_irq_info(bp); 13660 13661 rcu_assign_pointer(bp->cnic_ops, ops); 13662 13663 return 0; 13664 } 13665 13666 static int bnx2x_unregister_cnic(struct net_device *dev) 13667 { 13668 struct bnx2x *bp = netdev_priv(dev); 13669 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13670 13671 mutex_lock(&bp->cnic_mutex); 13672 cp->drv_state = 0; 13673 RCU_INIT_POINTER(bp->cnic_ops, NULL); 13674 mutex_unlock(&bp->cnic_mutex); 13675 synchronize_rcu(); 13676 bp->cnic_enabled = false; 13677 kfree(bp->cnic_kwq); 13678 bp->cnic_kwq = NULL; 13679 13680 return 0; 13681 } 13682 13683 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 13684 { 13685 struct bnx2x *bp = netdev_priv(dev); 13686 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 13687 13688 /* If both iSCSI and FCoE are disabled - return NULL in 13689 * order to indicate CNIC that it should not try to work 13690 * with this device. 13691 */ 13692 if (NO_ISCSI(bp) && NO_FCOE(bp)) 13693 return NULL; 13694 13695 cp->drv_owner = THIS_MODULE; 13696 cp->chip_id = CHIP_ID(bp); 13697 cp->pdev = bp->pdev; 13698 cp->io_base = bp->regview; 13699 cp->io_base2 = bp->doorbells; 13700 cp->max_kwqe_pending = 8; 13701 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 13702 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 13703 bnx2x_cid_ilt_lines(bp); 13704 cp->ctx_tbl_len = CNIC_ILT_LINES; 13705 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 13706 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 13707 cp->drv_ctl = bnx2x_drv_ctl; 13708 cp->drv_register_cnic = bnx2x_register_cnic; 13709 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 13710 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 13711 cp->iscsi_l2_client_id = 13712 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 13713 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 13714 13715 if (NO_ISCSI_OOO(bp)) 13716 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 13717 13718 if (NO_ISCSI(bp)) 13719 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 13720 13721 if (NO_FCOE(bp)) 13722 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 13723 13724 BNX2X_DEV_INFO( 13725 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", 13726 cp->ctx_blk_size, 13727 cp->ctx_tbl_offset, 13728 cp->ctx_tbl_len, 13729 cp->starting_cid); 13730 return cp; 13731 } 13732 13733 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 13734 { 13735 struct bnx2x *bp = fp->bp; 13736 u32 offset = BAR_USTRORM_INTMEM; 13737 13738 if (IS_VF(bp)) 13739 return bnx2x_vf_ustorm_prods_offset(bp, fp); 13740 else if (!CHIP_IS_E1x(bp)) 13741 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 13742 else 13743 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 13744 13745 return offset; 13746 } 13747 13748 /* called only on E1H or E2. 13749 * When pretending to be PF, the pretend value is the function number 0...7 13750 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 13751 * combination 13752 */ 13753 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) 13754 { 13755 u32 pretend_reg; 13756 13757 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) 13758 return -1; 13759 13760 /* get my own pretend register */ 13761 pretend_reg = bnx2x_get_pretend_reg(bp); 13762 REG_WR(bp, pretend_reg, pretend_func_val); 13763 REG_RD(bp, pretend_reg); 13764 return 0; 13765 } 13766