1 /* bnx2x_main.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/module.h> 21 #include <linux/moduleparam.h> 22 #include <linux/kernel.h> 23 #include <linux/device.h> /* for dev_info() */ 24 #include <linux/timer.h> 25 #include <linux/errno.h> 26 #include <linux/ioport.h> 27 #include <linux/slab.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/bitops.h> 36 #include <linux/irq.h> 37 #include <linux/delay.h> 38 #include <asm/byteorder.h> 39 #include <linux/time.h> 40 #include <linux/ethtool.h> 41 #include <linux/mii.h> 42 #include <linux/if.h> 43 #include <linux/if_vlan.h> 44 #include <net/ip.h> 45 #include <net/ipv6.h> 46 #include <net/tcp.h> 47 #include <net/checksum.h> 48 #include <net/ip6_checksum.h> 49 #include <linux/workqueue.h> 50 #include <linux/crc32.h> 51 #include <linux/crc32c.h> 52 #include <linux/prefetch.h> 53 #include <linux/zlib.h> 54 #include <linux/io.h> 55 #include <linux/stringify.h> 56 #include <linux/vmalloc.h> 57 58 #include "bnx2x.h" 59 #include "bnx2x_init.h" 60 #include "bnx2x_init_ops.h" 61 #include "bnx2x_cmn.h" 62 #include "bnx2x_dcb.h" 63 #include "bnx2x_sp.h" 64 65 #include <linux/firmware.h> 66 #include "bnx2x_fw_file_hdr.h" 67 /* FW files */ 68 #define FW_FILE_VERSION \ 69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 72 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 76 77 /* Time in jiffies before concluding the transmitter is hung */ 78 #define TX_TIMEOUT (5*HZ) 79 80 static char version[] __devinitdata = 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 83 84 MODULE_AUTHOR("Eliezer Tamir"); 85 MODULE_DESCRIPTION("Broadcom NetXtreme II " 86 "BCM57710/57711/57711E/" 87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 88 "57840/57840_MF Driver"); 89 MODULE_LICENSE("GPL"); 90 MODULE_VERSION(DRV_MODULE_VERSION); 91 MODULE_FIRMWARE(FW_FILE_NAME_E1); 92 MODULE_FIRMWARE(FW_FILE_NAME_E1H); 93 MODULE_FIRMWARE(FW_FILE_NAME_E2); 94 95 static int multi_mode = 1; 96 module_param(multi_mode, int, 0); 97 MODULE_PARM_DESC(multi_mode, " Multi queue mode " 98 "(0 Disable; 1 Enable (default))"); 99 100 int num_queues; 101 module_param(num_queues, int, 0); 102 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 103 " (default is as a number of CPUs)"); 104 105 static int disable_tpa; 106 module_param(disable_tpa, int, 0); 107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 108 109 #define INT_MODE_INTx 1 110 #define INT_MODE_MSI 2 111 static int int_mode; 112 module_param(int_mode, int, 0); 113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 114 "(1 INT#x; 2 MSI)"); 115 116 static int dropless_fc; 117 module_param(dropless_fc, int, 0); 118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 119 120 static int mrrs = -1; 121 module_param(mrrs, int, 0); 122 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 123 124 static int debug; 125 module_param(debug, int, 0); 126 MODULE_PARM_DESC(debug, " Default debug msglevel"); 127 128 129 130 struct workqueue_struct *bnx2x_wq; 131 132 enum bnx2x_board_type { 133 BCM57710 = 0, 134 BCM57711, 135 BCM57711E, 136 BCM57712, 137 BCM57712_MF, 138 BCM57800, 139 BCM57800_MF, 140 BCM57810, 141 BCM57810_MF, 142 BCM57840, 143 BCM57840_MF 144 }; 145 146 /* indexed by board_type, above */ 147 static struct { 148 char *name; 149 } board_info[] __devinitdata = { 150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, 151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, 152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, 153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, 154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, 155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, 156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, 157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, 158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, 159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, 160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit " 161 "Ethernet Multi Function"} 162 }; 163 164 #ifndef PCI_DEVICE_ID_NX2_57710 165 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 166 #endif 167 #ifndef PCI_DEVICE_ID_NX2_57711 168 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 169 #endif 170 #ifndef PCI_DEVICE_ID_NX2_57711E 171 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 172 #endif 173 #ifndef PCI_DEVICE_ID_NX2_57712 174 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 175 #endif 176 #ifndef PCI_DEVICE_ID_NX2_57712_MF 177 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 178 #endif 179 #ifndef PCI_DEVICE_ID_NX2_57800 180 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 181 #endif 182 #ifndef PCI_DEVICE_ID_NX2_57800_MF 183 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 184 #endif 185 #ifndef PCI_DEVICE_ID_NX2_57810 186 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 187 #endif 188 #ifndef PCI_DEVICE_ID_NX2_57810_MF 189 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 190 #endif 191 #ifndef PCI_DEVICE_ID_NX2_57840 192 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840 193 #endif 194 #ifndef PCI_DEVICE_ID_NX2_57840_MF 195 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 196 #endif 197 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 }, 208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 209 { 0 } 210 }; 211 212 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 213 214 /**************************************************************************** 215 * General service functions 216 ****************************************************************************/ 217 218 static inline void __storm_memset_dma_mapping(struct bnx2x *bp, 219 u32 addr, dma_addr_t mapping) 220 { 221 REG_WR(bp, addr, U64_LO(mapping)); 222 REG_WR(bp, addr + 4, U64_HI(mapping)); 223 } 224 225 static inline void storm_memset_spq_addr(struct bnx2x *bp, 226 dma_addr_t mapping, u16 abs_fid) 227 { 228 u32 addr = XSEM_REG_FAST_MEMORY + 229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 230 231 __storm_memset_dma_mapping(bp, addr, mapping); 232 } 233 234 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 235 u16 pf_id) 236 { 237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 238 pf_id); 239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 240 pf_id); 241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 242 pf_id); 243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 244 pf_id); 245 } 246 247 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 248 u8 enable) 249 { 250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 251 enable); 252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 253 enable); 254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 255 enable); 256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 257 enable); 258 } 259 260 static inline void storm_memset_eq_data(struct bnx2x *bp, 261 struct event_ring_data *eq_data, 262 u16 pfid) 263 { 264 size_t size = sizeof(struct event_ring_data); 265 266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 267 268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 269 } 270 271 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 272 u16 pfid) 273 { 274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 275 REG_WR16(bp, addr, eq_prod); 276 } 277 278 /* used only at init 279 * locking is done by mcp 280 */ 281 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 282 { 283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 286 PCICFG_VENDOR_ID_OFFSET); 287 } 288 289 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 290 { 291 u32 val; 292 293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 296 PCICFG_VENDOR_ID_OFFSET); 297 298 return val; 299 } 300 301 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 302 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 303 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 304 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 305 #define DMAE_DP_DST_NONE "dst_addr [none]" 306 307 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, 308 int msglvl) 309 { 310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 311 312 switch (dmae->opcode & DMAE_COMMAND_DST) { 313 case DMAE_CMD_DST_PCI: 314 if (src_type == DMAE_CMD_SRC_PCI) 315 DP(msglvl, "DMAE: opcode 0x%08x\n" 316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 317 "comp_addr [%x:%08x], comp_val 0x%08x\n", 318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 320 dmae->comp_addr_hi, dmae->comp_addr_lo, 321 dmae->comp_val); 322 else 323 DP(msglvl, "DMAE: opcode 0x%08x\n" 324 "src [%08x], len [%d*4], dst [%x:%08x]\n" 325 "comp_addr [%x:%08x], comp_val 0x%08x\n", 326 dmae->opcode, dmae->src_addr_lo >> 2, 327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 328 dmae->comp_addr_hi, dmae->comp_addr_lo, 329 dmae->comp_val); 330 break; 331 case DMAE_CMD_DST_GRC: 332 if (src_type == DMAE_CMD_SRC_PCI) 333 DP(msglvl, "DMAE: opcode 0x%08x\n" 334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 335 "comp_addr [%x:%08x], comp_val 0x%08x\n", 336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 337 dmae->len, dmae->dst_addr_lo >> 2, 338 dmae->comp_addr_hi, dmae->comp_addr_lo, 339 dmae->comp_val); 340 else 341 DP(msglvl, "DMAE: opcode 0x%08x\n" 342 "src [%08x], len [%d*4], dst [%08x]\n" 343 "comp_addr [%x:%08x], comp_val 0x%08x\n", 344 dmae->opcode, dmae->src_addr_lo >> 2, 345 dmae->len, dmae->dst_addr_lo >> 2, 346 dmae->comp_addr_hi, dmae->comp_addr_lo, 347 dmae->comp_val); 348 break; 349 default: 350 if (src_type == DMAE_CMD_SRC_PCI) 351 DP(msglvl, "DMAE: opcode 0x%08x\n" 352 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 353 "comp_addr [%x:%08x] comp_val 0x%08x\n", 354 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 355 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 356 dmae->comp_val); 357 else 358 DP(msglvl, "DMAE: opcode 0x%08x\n" 359 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 360 "comp_addr [%x:%08x] comp_val 0x%08x\n", 361 dmae->opcode, dmae->src_addr_lo >> 2, 362 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 363 dmae->comp_val); 364 break; 365 } 366 367 } 368 369 /* copy command into DMAE command memory and set DMAE command go */ 370 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 371 { 372 u32 cmd_offset; 373 int i; 374 375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 378 } 379 REG_WR(bp, dmae_reg_go_c[idx], 1); 380 } 381 382 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 383 { 384 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 385 DMAE_CMD_C_ENABLE); 386 } 387 388 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 389 { 390 return opcode & ~DMAE_CMD_SRC_RESET; 391 } 392 393 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 394 bool with_comp, u8 comp_type) 395 { 396 u32 opcode = 0; 397 398 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 399 (dst_type << DMAE_COMMAND_DST_SHIFT)); 400 401 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 402 403 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 404 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 405 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 406 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 407 408 #ifdef __BIG_ENDIAN 409 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 410 #else 411 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 412 #endif 413 if (with_comp) 414 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 415 return opcode; 416 } 417 418 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 419 struct dmae_command *dmae, 420 u8 src_type, u8 dst_type) 421 { 422 memset(dmae, 0, sizeof(struct dmae_command)); 423 424 /* set the opcode */ 425 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 426 true, DMAE_COMP_PCI); 427 428 /* fill in the completion parameters */ 429 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 430 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 431 dmae->comp_val = DMAE_COMP_VAL; 432 } 433 434 /* issue a dmae command over the init-channel and wailt for completion */ 435 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, 436 struct dmae_command *dmae) 437 { 438 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 439 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 440 int rc = 0; 441 442 /* 443 * Lock the dmae channel. Disable BHs to prevent a dead-lock 444 * as long as this code is called both from syscall context and 445 * from ndo_set_rx_mode() flow that may be called from BH. 446 */ 447 spin_lock_bh(&bp->dmae_lock); 448 449 /* reset completion */ 450 *wb_comp = 0; 451 452 /* post the command on the channel used for initializations */ 453 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 454 455 /* wait for completion */ 456 udelay(5); 457 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 458 459 if (!cnt || 460 (bp->recovery_state != BNX2X_RECOVERY_DONE && 461 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 462 BNX2X_ERR("DMAE timeout!\n"); 463 rc = DMAE_TIMEOUT; 464 goto unlock; 465 } 466 cnt--; 467 udelay(50); 468 } 469 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 470 BNX2X_ERR("DMAE PCI error!\n"); 471 rc = DMAE_PCI_ERROR; 472 } 473 474 unlock: 475 spin_unlock_bh(&bp->dmae_lock); 476 return rc; 477 } 478 479 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 480 u32 len32) 481 { 482 struct dmae_command dmae; 483 484 if (!bp->dmae_ready) { 485 u32 *data = bnx2x_sp(bp, wb_data[0]); 486 487 if (CHIP_IS_E1(bp)) 488 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 489 else 490 bnx2x_init_str_wr(bp, dst_addr, data, len32); 491 return; 492 } 493 494 /* set opcode and fixed command fields */ 495 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 496 497 /* fill in addresses and len */ 498 dmae.src_addr_lo = U64_LO(dma_addr); 499 dmae.src_addr_hi = U64_HI(dma_addr); 500 dmae.dst_addr_lo = dst_addr >> 2; 501 dmae.dst_addr_hi = 0; 502 dmae.len = len32; 503 504 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 505 506 /* issue the command and wait for completion */ 507 bnx2x_issue_dmae_with_comp(bp, &dmae); 508 } 509 510 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 511 { 512 struct dmae_command dmae; 513 514 if (!bp->dmae_ready) { 515 u32 *data = bnx2x_sp(bp, wb_data[0]); 516 int i; 517 518 if (CHIP_IS_E1(bp)) 519 for (i = 0; i < len32; i++) 520 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 521 else 522 for (i = 0; i < len32; i++) 523 data[i] = REG_RD(bp, src_addr + i*4); 524 525 return; 526 } 527 528 /* set opcode and fixed command fields */ 529 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 530 531 /* fill in addresses and len */ 532 dmae.src_addr_lo = src_addr >> 2; 533 dmae.src_addr_hi = 0; 534 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 535 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 536 dmae.len = len32; 537 538 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF); 539 540 /* issue the command and wait for completion */ 541 bnx2x_issue_dmae_with_comp(bp, &dmae); 542 } 543 544 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 545 u32 addr, u32 len) 546 { 547 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 548 int offset = 0; 549 550 while (len > dmae_wr_max) { 551 bnx2x_write_dmae(bp, phys_addr + offset, 552 addr + offset, dmae_wr_max); 553 offset += dmae_wr_max * 4; 554 len -= dmae_wr_max; 555 } 556 557 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 558 } 559 560 /* used only for slowpath so not inlined */ 561 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo) 562 { 563 u32 wb_write[2]; 564 565 wb_write[0] = val_hi; 566 wb_write[1] = val_lo; 567 REG_WR_DMAE(bp, reg, wb_write, 2); 568 } 569 570 #ifdef USE_WB_RD 571 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg) 572 { 573 u32 wb_data[2]; 574 575 REG_RD_DMAE(bp, reg, wb_data, 2); 576 577 return HILO_U64(wb_data[0], wb_data[1]); 578 } 579 #endif 580 581 static int bnx2x_mc_assert(struct bnx2x *bp) 582 { 583 char last_idx; 584 int i, rc = 0; 585 u32 row0, row1, row2, row3; 586 587 /* XSTORM */ 588 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + 589 XSTORM_ASSERT_LIST_INDEX_OFFSET); 590 if (last_idx) 591 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 592 593 /* print the asserts */ 594 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 595 596 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + 597 XSTORM_ASSERT_LIST_OFFSET(i)); 598 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + 599 XSTORM_ASSERT_LIST_OFFSET(i) + 4); 600 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + 601 XSTORM_ASSERT_LIST_OFFSET(i) + 8); 602 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + 603 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 604 605 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 606 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 607 i, row3, row2, row1, row0); 608 rc++; 609 } else { 610 break; 611 } 612 } 613 614 /* TSTORM */ 615 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + 616 TSTORM_ASSERT_LIST_INDEX_OFFSET); 617 if (last_idx) 618 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 619 620 /* print the asserts */ 621 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 622 623 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + 624 TSTORM_ASSERT_LIST_OFFSET(i)); 625 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + 626 TSTORM_ASSERT_LIST_OFFSET(i) + 4); 627 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + 628 TSTORM_ASSERT_LIST_OFFSET(i) + 8); 629 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + 630 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 631 632 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 633 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 634 i, row3, row2, row1, row0); 635 rc++; 636 } else { 637 break; 638 } 639 } 640 641 /* CSTORM */ 642 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + 643 CSTORM_ASSERT_LIST_INDEX_OFFSET); 644 if (last_idx) 645 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 646 647 /* print the asserts */ 648 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 649 650 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + 651 CSTORM_ASSERT_LIST_OFFSET(i)); 652 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + 653 CSTORM_ASSERT_LIST_OFFSET(i) + 4); 654 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + 655 CSTORM_ASSERT_LIST_OFFSET(i) + 8); 656 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + 657 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 658 659 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 660 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 661 i, row3, row2, row1, row0); 662 rc++; 663 } else { 664 break; 665 } 666 } 667 668 /* USTORM */ 669 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + 670 USTORM_ASSERT_LIST_INDEX_OFFSET); 671 if (last_idx) 672 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 673 674 /* print the asserts */ 675 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 676 677 row0 = REG_RD(bp, BAR_USTRORM_INTMEM + 678 USTORM_ASSERT_LIST_OFFSET(i)); 679 row1 = REG_RD(bp, BAR_USTRORM_INTMEM + 680 USTORM_ASSERT_LIST_OFFSET(i) + 4); 681 row2 = REG_RD(bp, BAR_USTRORM_INTMEM + 682 USTORM_ASSERT_LIST_OFFSET(i) + 8); 683 row3 = REG_RD(bp, BAR_USTRORM_INTMEM + 684 USTORM_ASSERT_LIST_OFFSET(i) + 12); 685 686 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 687 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 688 i, row3, row2, row1, row0); 689 rc++; 690 } else { 691 break; 692 } 693 } 694 695 return rc; 696 } 697 698 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 699 { 700 u32 addr, val; 701 u32 mark, offset; 702 __be32 data[9]; 703 int word; 704 u32 trace_shmem_base; 705 if (BP_NOMCP(bp)) { 706 BNX2X_ERR("NO MCP - can not dump\n"); 707 return; 708 } 709 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 710 (bp->common.bc_ver & 0xff0000) >> 16, 711 (bp->common.bc_ver & 0xff00) >> 8, 712 (bp->common.bc_ver & 0xff)); 713 714 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 715 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 716 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 717 718 if (BP_PATH(bp) == 0) 719 trace_shmem_base = bp->common.shmem_base; 720 else 721 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 722 addr = trace_shmem_base - 0x800; 723 724 /* validate TRCB signature */ 725 mark = REG_RD(bp, addr); 726 if (mark != MFW_TRACE_SIGNATURE) { 727 BNX2X_ERR("Trace buffer signature is missing."); 728 return ; 729 } 730 731 /* read cyclic buffer pointer */ 732 addr += 4; 733 mark = REG_RD(bp, addr); 734 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 735 + ((mark + 0x3) & ~0x3) - 0x08000000; 736 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 737 738 printk("%s", lvl); 739 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 740 for (word = 0; word < 8; word++) 741 data[word] = htonl(REG_RD(bp, offset + 4*word)); 742 data[8] = 0x0; 743 pr_cont("%s", (char *)data); 744 } 745 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 746 for (word = 0; word < 8; word++) 747 data[word] = htonl(REG_RD(bp, offset + 4*word)); 748 data[8] = 0x0; 749 pr_cont("%s", (char *)data); 750 } 751 printk("%s" "end of fw dump\n", lvl); 752 } 753 754 static inline void bnx2x_fw_dump(struct bnx2x *bp) 755 { 756 bnx2x_fw_dump_lvl(bp, KERN_ERR); 757 } 758 759 void bnx2x_panic_dump(struct bnx2x *bp) 760 { 761 int i; 762 u16 j; 763 struct hc_sp_status_block_data sp_sb_data; 764 int func = BP_FUNC(bp); 765 #ifdef BNX2X_STOP_ON_ERROR 766 u16 start = 0, end = 0; 767 u8 cos; 768 #endif 769 770 bp->stats_state = STATS_STATE_DISABLED; 771 bp->eth_stats.unrecoverable_error++; 772 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 773 774 BNX2X_ERR("begin crash dump -----------------\n"); 775 776 /* Indices */ 777 /* Common */ 778 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 779 bp->def_idx, bp->def_att_idx, bp->attn_state, 780 bp->spq_prod_idx, bp->stats_counter); 781 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 782 bp->def_status_blk->atten_status_block.attn_bits, 783 bp->def_status_blk->atten_status_block.attn_bits_ack, 784 bp->def_status_blk->atten_status_block.status_block_id, 785 bp->def_status_blk->atten_status_block.attn_bits_index); 786 BNX2X_ERR(" def ("); 787 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 788 pr_cont("0x%x%s", 789 bp->def_status_blk->sp_sb.index_values[i], 790 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 791 792 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 793 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + 794 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 795 i*sizeof(u32)); 796 797 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 798 sp_sb_data.igu_sb_id, 799 sp_sb_data.igu_seg_id, 800 sp_sb_data.p_func.pf_id, 801 sp_sb_data.p_func.vnic_id, 802 sp_sb_data.p_func.vf_id, 803 sp_sb_data.p_func.vf_valid, 804 sp_sb_data.state); 805 806 807 for_each_eth_queue(bp, i) { 808 struct bnx2x_fastpath *fp = &bp->fp[i]; 809 int loop; 810 struct hc_status_block_data_e2 sb_data_e2; 811 struct hc_status_block_data_e1x sb_data_e1x; 812 struct hc_status_block_sm *hc_sm_p = 813 CHIP_IS_E1x(bp) ? 814 sb_data_e1x.common.state_machine : 815 sb_data_e2.common.state_machine; 816 struct hc_index_data *hc_index_p = 817 CHIP_IS_E1x(bp) ? 818 sb_data_e1x.index_data : 819 sb_data_e2.index_data; 820 u8 data_size, cos; 821 u32 *sb_data_p; 822 struct bnx2x_fp_txdata txdata; 823 824 /* Rx */ 825 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 826 i, fp->rx_bd_prod, fp->rx_bd_cons, 827 fp->rx_comp_prod, 828 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 829 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 830 fp->rx_sge_prod, fp->last_max_sge, 831 le16_to_cpu(fp->fp_hc_idx)); 832 833 /* Tx */ 834 for_each_cos_in_tx_queue(fp, cos) 835 { 836 txdata = fp->txdata[cos]; 837 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 838 i, txdata.tx_pkt_prod, 839 txdata.tx_pkt_cons, txdata.tx_bd_prod, 840 txdata.tx_bd_cons, 841 le16_to_cpu(*txdata.tx_cons_sb)); 842 } 843 844 loop = CHIP_IS_E1x(bp) ? 845 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 846 847 /* host sb data */ 848 849 #ifdef BCM_CNIC 850 if (IS_FCOE_FP(fp)) 851 continue; 852 #endif 853 BNX2X_ERR(" run indexes ("); 854 for (j = 0; j < HC_SB_MAX_SM; j++) 855 pr_cont("0x%x%s", 856 fp->sb_running_index[j], 857 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 858 859 BNX2X_ERR(" indexes ("); 860 for (j = 0; j < loop; j++) 861 pr_cont("0x%x%s", 862 fp->sb_index_values[j], 863 (j == loop - 1) ? ")" : " "); 864 /* fw sb data */ 865 data_size = CHIP_IS_E1x(bp) ? 866 sizeof(struct hc_status_block_data_e1x) : 867 sizeof(struct hc_status_block_data_e2); 868 data_size /= sizeof(u32); 869 sb_data_p = CHIP_IS_E1x(bp) ? 870 (u32 *)&sb_data_e1x : 871 (u32 *)&sb_data_e2; 872 /* copy sb data in here */ 873 for (j = 0; j < data_size; j++) 874 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 875 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 876 j * sizeof(u32)); 877 878 if (!CHIP_IS_E1x(bp)) { 879 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 880 sb_data_e2.common.p_func.pf_id, 881 sb_data_e2.common.p_func.vf_id, 882 sb_data_e2.common.p_func.vf_valid, 883 sb_data_e2.common.p_func.vnic_id, 884 sb_data_e2.common.same_igu_sb_1b, 885 sb_data_e2.common.state); 886 } else { 887 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 888 sb_data_e1x.common.p_func.pf_id, 889 sb_data_e1x.common.p_func.vf_id, 890 sb_data_e1x.common.p_func.vf_valid, 891 sb_data_e1x.common.p_func.vnic_id, 892 sb_data_e1x.common.same_igu_sb_1b, 893 sb_data_e1x.common.state); 894 } 895 896 /* SB_SMs data */ 897 for (j = 0; j < HC_SB_MAX_SM; j++) { 898 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 899 j, hc_sm_p[j].__flags, 900 hc_sm_p[j].igu_sb_id, 901 hc_sm_p[j].igu_seg_id, 902 hc_sm_p[j].time_to_expire, 903 hc_sm_p[j].timer_value); 904 } 905 906 /* Indecies data */ 907 for (j = 0; j < loop; j++) { 908 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 909 hc_index_p[j].flags, 910 hc_index_p[j].timeout); 911 } 912 } 913 914 #ifdef BNX2X_STOP_ON_ERROR 915 /* Rings */ 916 /* Rx */ 917 for_each_rx_queue(bp, i) { 918 struct bnx2x_fastpath *fp = &bp->fp[i]; 919 920 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 921 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 922 for (j = start; j != end; j = RX_BD(j + 1)) { 923 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 924 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 925 926 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 927 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 928 } 929 930 start = RX_SGE(fp->rx_sge_prod); 931 end = RX_SGE(fp->last_max_sge); 932 for (j = start; j != end; j = RX_SGE(j + 1)) { 933 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 934 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 935 936 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 937 i, j, rx_sge[1], rx_sge[0], sw_page->page); 938 } 939 940 start = RCQ_BD(fp->rx_comp_cons - 10); 941 end = RCQ_BD(fp->rx_comp_cons + 503); 942 for (j = start; j != end; j = RCQ_BD(j + 1)) { 943 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 944 945 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 946 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 947 } 948 } 949 950 /* Tx */ 951 for_each_tx_queue(bp, i) { 952 struct bnx2x_fastpath *fp = &bp->fp[i]; 953 for_each_cos_in_tx_queue(fp, cos) { 954 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 955 956 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 957 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 958 for (j = start; j != end; j = TX_BD(j + 1)) { 959 struct sw_tx_bd *sw_bd = 960 &txdata->tx_buf_ring[j]; 961 962 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 963 i, cos, j, sw_bd->skb, 964 sw_bd->first_bd); 965 } 966 967 start = TX_BD(txdata->tx_bd_cons - 10); 968 end = TX_BD(txdata->tx_bd_cons + 254); 969 for (j = start; j != end; j = TX_BD(j + 1)) { 970 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 971 972 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 973 i, cos, j, tx_bd[0], tx_bd[1], 974 tx_bd[2], tx_bd[3]); 975 } 976 } 977 } 978 #endif 979 bnx2x_fw_dump(bp); 980 bnx2x_mc_assert(bp); 981 BNX2X_ERR("end crash dump -----------------\n"); 982 } 983 984 /* 985 * FLR Support for E2 986 * 987 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 988 * initialization. 989 */ 990 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ 991 #define FLR_WAIT_INTERVAL 50 /* usec */ 992 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 993 994 struct pbf_pN_buf_regs { 995 int pN; 996 u32 init_crd; 997 u32 crd; 998 u32 crd_freed; 999 }; 1000 1001 struct pbf_pN_cmd_regs { 1002 int pN; 1003 u32 lines_occup; 1004 u32 lines_freed; 1005 }; 1006 1007 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1008 struct pbf_pN_buf_regs *regs, 1009 u32 poll_count) 1010 { 1011 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1012 u32 cur_cnt = poll_count; 1013 1014 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1015 crd = crd_start = REG_RD(bp, regs->crd); 1016 init_crd = REG_RD(bp, regs->init_crd); 1017 1018 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1019 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1020 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1021 1022 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1023 (init_crd - crd_start))) { 1024 if (cur_cnt--) { 1025 udelay(FLR_WAIT_INTERVAL); 1026 crd = REG_RD(bp, regs->crd); 1027 crd_freed = REG_RD(bp, regs->crd_freed); 1028 } else { 1029 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1030 regs->pN); 1031 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1032 regs->pN, crd); 1033 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1034 regs->pN, crd_freed); 1035 break; 1036 } 1037 } 1038 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1039 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1040 } 1041 1042 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1043 struct pbf_pN_cmd_regs *regs, 1044 u32 poll_count) 1045 { 1046 u32 occup, to_free, freed, freed_start; 1047 u32 cur_cnt = poll_count; 1048 1049 occup = to_free = REG_RD(bp, regs->lines_occup); 1050 freed = freed_start = REG_RD(bp, regs->lines_freed); 1051 1052 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1053 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1054 1055 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1056 if (cur_cnt--) { 1057 udelay(FLR_WAIT_INTERVAL); 1058 occup = REG_RD(bp, regs->lines_occup); 1059 freed = REG_RD(bp, regs->lines_freed); 1060 } else { 1061 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1062 regs->pN); 1063 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1064 regs->pN, occup); 1065 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1066 regs->pN, freed); 1067 break; 1068 } 1069 } 1070 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1071 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1072 } 1073 1074 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1075 u32 expected, u32 poll_count) 1076 { 1077 u32 cur_cnt = poll_count; 1078 u32 val; 1079 1080 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1081 udelay(FLR_WAIT_INTERVAL); 1082 1083 return val; 1084 } 1085 1086 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1087 char *msg, u32 poll_cnt) 1088 { 1089 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1090 if (val != 0) { 1091 BNX2X_ERR("%s usage count=%d\n", msg, val); 1092 return 1; 1093 } 1094 return 0; 1095 } 1096 1097 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1098 { 1099 /* adjust polling timeout */ 1100 if (CHIP_REV_IS_EMUL(bp)) 1101 return FLR_POLL_CNT * 2000; 1102 1103 if (CHIP_REV_IS_FPGA(bp)) 1104 return FLR_POLL_CNT * 120; 1105 1106 return FLR_POLL_CNT; 1107 } 1108 1109 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1110 { 1111 struct pbf_pN_cmd_regs cmd_regs[] = { 1112 {0, (CHIP_IS_E3B0(bp)) ? 1113 PBF_REG_TQ_OCCUPANCY_Q0 : 1114 PBF_REG_P0_TQ_OCCUPANCY, 1115 (CHIP_IS_E3B0(bp)) ? 1116 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1117 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1118 {1, (CHIP_IS_E3B0(bp)) ? 1119 PBF_REG_TQ_OCCUPANCY_Q1 : 1120 PBF_REG_P1_TQ_OCCUPANCY, 1121 (CHIP_IS_E3B0(bp)) ? 1122 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1123 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1124 {4, (CHIP_IS_E3B0(bp)) ? 1125 PBF_REG_TQ_OCCUPANCY_LB_Q : 1126 PBF_REG_P4_TQ_OCCUPANCY, 1127 (CHIP_IS_E3B0(bp)) ? 1128 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1129 PBF_REG_P4_TQ_LINES_FREED_CNT} 1130 }; 1131 1132 struct pbf_pN_buf_regs buf_regs[] = { 1133 {0, (CHIP_IS_E3B0(bp)) ? 1134 PBF_REG_INIT_CRD_Q0 : 1135 PBF_REG_P0_INIT_CRD , 1136 (CHIP_IS_E3B0(bp)) ? 1137 PBF_REG_CREDIT_Q0 : 1138 PBF_REG_P0_CREDIT, 1139 (CHIP_IS_E3B0(bp)) ? 1140 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1141 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1142 {1, (CHIP_IS_E3B0(bp)) ? 1143 PBF_REG_INIT_CRD_Q1 : 1144 PBF_REG_P1_INIT_CRD, 1145 (CHIP_IS_E3B0(bp)) ? 1146 PBF_REG_CREDIT_Q1 : 1147 PBF_REG_P1_CREDIT, 1148 (CHIP_IS_E3B0(bp)) ? 1149 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1150 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1151 {4, (CHIP_IS_E3B0(bp)) ? 1152 PBF_REG_INIT_CRD_LB_Q : 1153 PBF_REG_P4_INIT_CRD, 1154 (CHIP_IS_E3B0(bp)) ? 1155 PBF_REG_CREDIT_LB_Q : 1156 PBF_REG_P4_CREDIT, 1157 (CHIP_IS_E3B0(bp)) ? 1158 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1159 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1160 }; 1161 1162 int i; 1163 1164 /* Verify the command queues are flushed P0, P1, P4 */ 1165 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1166 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1167 1168 1169 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1170 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1171 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1172 } 1173 1174 #define OP_GEN_PARAM(param) \ 1175 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1176 1177 #define OP_GEN_TYPE(type) \ 1178 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1179 1180 #define OP_GEN_AGG_VECT(index) \ 1181 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1182 1183 1184 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 1185 u32 poll_cnt) 1186 { 1187 struct sdm_op_gen op_gen = {0}; 1188 1189 u32 comp_addr = BAR_CSTRORM_INTMEM + 1190 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1191 int ret = 0; 1192 1193 if (REG_RD(bp, comp_addr)) { 1194 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1195 return 1; 1196 } 1197 1198 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1199 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1200 op_gen.command |= OP_GEN_AGG_VECT(clnup_func); 1201 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1202 1203 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1204 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); 1205 1206 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1207 BNX2X_ERR("FW final cleanup did not succeed\n"); 1208 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1209 (REG_RD(bp, comp_addr))); 1210 ret = 1; 1211 } 1212 /* Zero completion for nxt FLR */ 1213 REG_WR(bp, comp_addr, 0); 1214 1215 return ret; 1216 } 1217 1218 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1219 { 1220 int pos; 1221 u16 status; 1222 1223 pos = pci_pcie_cap(dev); 1224 if (!pos) 1225 return false; 1226 1227 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 1228 return status & PCI_EXP_DEVSTA_TRPND; 1229 } 1230 1231 /* PF FLR specific routines 1232 */ 1233 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1234 { 1235 1236 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1237 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1238 CFC_REG_NUM_LCIDS_INSIDE_PF, 1239 "CFC PF usage counter timed out", 1240 poll_cnt)) 1241 return 1; 1242 1243 1244 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1245 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1246 DORQ_REG_PF_USAGE_CNT, 1247 "DQ PF usage counter timed out", 1248 poll_cnt)) 1249 return 1; 1250 1251 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1252 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1253 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1254 "QM PF usage counter timed out", 1255 poll_cnt)) 1256 return 1; 1257 1258 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1259 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1260 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1261 "Timers VNIC usage counter timed out", 1262 poll_cnt)) 1263 return 1; 1264 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1265 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1266 "Timers NUM_SCANS usage counter timed out", 1267 poll_cnt)) 1268 return 1; 1269 1270 /* Wait DMAE PF usage counter to zero */ 1271 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1272 dmae_reg_go_c[INIT_DMAE_C(bp)], 1273 "DMAE dommand register timed out", 1274 poll_cnt)) 1275 return 1; 1276 1277 return 0; 1278 } 1279 1280 static void bnx2x_hw_enable_status(struct bnx2x *bp) 1281 { 1282 u32 val; 1283 1284 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1285 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1286 1287 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1288 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1289 1290 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1291 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1292 1293 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1294 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1295 1296 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1297 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1298 1299 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1300 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1301 1302 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1303 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1304 1305 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1306 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1307 val); 1308 } 1309 1310 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1311 { 1312 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1313 1314 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1315 1316 /* Re-enable PF target read access */ 1317 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1318 1319 /* Poll HW usage counters */ 1320 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1321 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1322 return -EBUSY; 1323 1324 /* Zero the igu 'trailing edge' and 'leading edge' */ 1325 1326 /* Send the FW cleanup command */ 1327 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1328 return -EBUSY; 1329 1330 /* ATC cleanup */ 1331 1332 /* Verify TX hw is flushed */ 1333 bnx2x_tx_hw_flushed(bp, poll_cnt); 1334 1335 /* Wait 100ms (not adjusted according to platform) */ 1336 msleep(100); 1337 1338 /* Verify no pending pci transactions */ 1339 if (bnx2x_is_pcie_pending(bp->pdev)) 1340 BNX2X_ERR("PCIE Transactions still pending\n"); 1341 1342 /* Debug */ 1343 bnx2x_hw_enable_status(bp); 1344 1345 /* 1346 * Master enable - Due to WB DMAE writes performed before this 1347 * register is re-initialized as part of the regular function init 1348 */ 1349 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1350 1351 return 0; 1352 } 1353 1354 static void bnx2x_hc_int_enable(struct bnx2x *bp) 1355 { 1356 int port = BP_PORT(bp); 1357 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1358 u32 val = REG_RD(bp, addr); 1359 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1360 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1361 1362 if (msix) { 1363 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1364 HC_CONFIG_0_REG_INT_LINE_EN_0); 1365 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1366 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1367 } else if (msi) { 1368 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1369 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1370 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1371 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1372 } else { 1373 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1374 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1375 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1376 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1377 1378 if (!CHIP_IS_E1(bp)) { 1379 DP(NETIF_MSG_IFUP, 1380 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1381 1382 REG_WR(bp, addr, val); 1383 1384 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1385 } 1386 } 1387 1388 if (CHIP_IS_E1(bp)) 1389 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1390 1391 DP(NETIF_MSG_IFUP, 1392 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1393 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1394 1395 REG_WR(bp, addr, val); 1396 /* 1397 * Ensure that HC_CONFIG is written before leading/trailing edge config 1398 */ 1399 mmiowb(); 1400 barrier(); 1401 1402 if (!CHIP_IS_E1(bp)) { 1403 /* init leading/trailing edge */ 1404 if (IS_MF(bp)) { 1405 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1406 if (bp->port.pmf) 1407 /* enable nig and gpio3 attention */ 1408 val |= 0x1100; 1409 } else 1410 val = 0xffff; 1411 1412 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1413 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1414 } 1415 1416 /* Make sure that interrupts are indeed enabled from here on */ 1417 mmiowb(); 1418 } 1419 1420 static void bnx2x_igu_int_enable(struct bnx2x *bp) 1421 { 1422 u32 val; 1423 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1424 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0; 1425 1426 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1427 1428 if (msix) { 1429 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1430 IGU_PF_CONF_SINGLE_ISR_EN); 1431 val |= (IGU_PF_CONF_FUNC_EN | 1432 IGU_PF_CONF_MSI_MSIX_EN | 1433 IGU_PF_CONF_ATTN_BIT_EN); 1434 } else if (msi) { 1435 val &= ~IGU_PF_CONF_INT_LINE_EN; 1436 val |= (IGU_PF_CONF_FUNC_EN | 1437 IGU_PF_CONF_MSI_MSIX_EN | 1438 IGU_PF_CONF_ATTN_BIT_EN | 1439 IGU_PF_CONF_SINGLE_ISR_EN); 1440 } else { 1441 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1442 val |= (IGU_PF_CONF_FUNC_EN | 1443 IGU_PF_CONF_INT_LINE_EN | 1444 IGU_PF_CONF_ATTN_BIT_EN | 1445 IGU_PF_CONF_SINGLE_ISR_EN); 1446 } 1447 1448 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1449 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1450 1451 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1452 1453 barrier(); 1454 1455 /* init leading/trailing edge */ 1456 if (IS_MF(bp)) { 1457 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1458 if (bp->port.pmf) 1459 /* enable nig and gpio3 attention */ 1460 val |= 0x1100; 1461 } else 1462 val = 0xffff; 1463 1464 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1465 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1466 1467 /* Make sure that interrupts are indeed enabled from here on */ 1468 mmiowb(); 1469 } 1470 1471 void bnx2x_int_enable(struct bnx2x *bp) 1472 { 1473 if (bp->common.int_block == INT_BLOCK_HC) 1474 bnx2x_hc_int_enable(bp); 1475 else 1476 bnx2x_igu_int_enable(bp); 1477 } 1478 1479 static void bnx2x_hc_int_disable(struct bnx2x *bp) 1480 { 1481 int port = BP_PORT(bp); 1482 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1483 u32 val = REG_RD(bp, addr); 1484 1485 /* 1486 * in E1 we must use only PCI configuration space to disable 1487 * MSI/MSIX capablility 1488 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 1489 */ 1490 if (CHIP_IS_E1(bp)) { 1491 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 1492 * Use mask register to prevent from HC sending interrupts 1493 * after we exit the function 1494 */ 1495 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 1496 1497 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1498 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1499 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1500 } else 1501 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1502 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1503 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1504 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1505 1506 DP(NETIF_MSG_IFDOWN, 1507 "write %x to HC %d (addr 0x%x)\n", 1508 val, port, addr); 1509 1510 /* flush all outstanding writes */ 1511 mmiowb(); 1512 1513 REG_WR(bp, addr, val); 1514 if (REG_RD(bp, addr) != val) 1515 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1516 } 1517 1518 static void bnx2x_igu_int_disable(struct bnx2x *bp) 1519 { 1520 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1521 1522 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 1523 IGU_PF_CONF_INT_LINE_EN | 1524 IGU_PF_CONF_ATTN_BIT_EN); 1525 1526 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 1527 1528 /* flush all outstanding writes */ 1529 mmiowb(); 1530 1531 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1532 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 1533 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1534 } 1535 1536 void bnx2x_int_disable(struct bnx2x *bp) 1537 { 1538 if (bp->common.int_block == INT_BLOCK_HC) 1539 bnx2x_hc_int_disable(bp); 1540 else 1541 bnx2x_igu_int_disable(bp); 1542 } 1543 1544 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1545 { 1546 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1547 int i, offset; 1548 1549 if (disable_hw) 1550 /* prevent the HW from sending interrupts */ 1551 bnx2x_int_disable(bp); 1552 1553 /* make sure all ISRs are done */ 1554 if (msix) { 1555 synchronize_irq(bp->msix_table[0].vector); 1556 offset = 1; 1557 #ifdef BCM_CNIC 1558 offset++; 1559 #endif 1560 for_each_eth_queue(bp, i) 1561 synchronize_irq(bp->msix_table[offset++].vector); 1562 } else 1563 synchronize_irq(bp->pdev->irq); 1564 1565 /* make sure sp_task is not running */ 1566 cancel_delayed_work(&bp->sp_task); 1567 cancel_delayed_work(&bp->period_task); 1568 flush_workqueue(bnx2x_wq); 1569 } 1570 1571 /* fast path */ 1572 1573 /* 1574 * General service functions 1575 */ 1576 1577 /* Return true if succeeded to acquire the lock */ 1578 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1579 { 1580 u32 lock_status; 1581 u32 resource_bit = (1 << resource); 1582 int func = BP_FUNC(bp); 1583 u32 hw_lock_control_reg; 1584 1585 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1586 "Trying to take a lock on resource %d\n", resource); 1587 1588 /* Validating that the resource is within range */ 1589 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1590 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1591 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1592 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1593 return false; 1594 } 1595 1596 if (func <= 5) 1597 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1598 else 1599 hw_lock_control_reg = 1600 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1601 1602 /* Try to acquire the lock */ 1603 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1604 lock_status = REG_RD(bp, hw_lock_control_reg); 1605 if (lock_status & resource_bit) 1606 return true; 1607 1608 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1609 "Failed to get a lock on resource %d\n", resource); 1610 return false; 1611 } 1612 1613 /** 1614 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1615 * 1616 * @bp: driver handle 1617 * 1618 * Returns the recovery leader resource id according to the engine this function 1619 * belongs to. Currently only only 2 engines is supported. 1620 */ 1621 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1622 { 1623 if (BP_PATH(bp)) 1624 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1625 else 1626 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1627 } 1628 1629 /** 1630 * bnx2x_trylock_leader_lock- try to aquire a leader lock. 1631 * 1632 * @bp: driver handle 1633 * 1634 * Tries to aquire a leader lock for cuurent engine. 1635 */ 1636 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1637 { 1638 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1639 } 1640 1641 #ifdef BCM_CNIC 1642 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1643 #endif 1644 1645 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1646 { 1647 struct bnx2x *bp = fp->bp; 1648 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1649 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1650 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1651 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj; 1652 1653 DP(BNX2X_MSG_SP, 1654 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1655 fp->index, cid, command, bp->state, 1656 rr_cqe->ramrod_cqe.ramrod_type); 1657 1658 switch (command) { 1659 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1660 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1661 drv_cmd = BNX2X_Q_CMD_UPDATE; 1662 break; 1663 1664 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1665 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1666 drv_cmd = BNX2X_Q_CMD_SETUP; 1667 break; 1668 1669 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1670 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1671 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1672 break; 1673 1674 case (RAMROD_CMD_ID_ETH_HALT): 1675 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1676 drv_cmd = BNX2X_Q_CMD_HALT; 1677 break; 1678 1679 case (RAMROD_CMD_ID_ETH_TERMINATE): 1680 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); 1681 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1682 break; 1683 1684 case (RAMROD_CMD_ID_ETH_EMPTY): 1685 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1686 drv_cmd = BNX2X_Q_CMD_EMPTY; 1687 break; 1688 1689 default: 1690 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1691 command, fp->index); 1692 return; 1693 } 1694 1695 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1696 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1697 /* q_obj->complete_cmd() failure means that this was 1698 * an unexpected completion. 1699 * 1700 * In this case we don't want to increase the bp->spq_left 1701 * because apparently we haven't sent this command the first 1702 * place. 1703 */ 1704 #ifdef BNX2X_STOP_ON_ERROR 1705 bnx2x_panic(); 1706 #else 1707 return; 1708 #endif 1709 1710 smp_mb__before_atomic_inc(); 1711 atomic_inc(&bp->cq_spq_left); 1712 /* push the change in bp->spq_left and towards the memory */ 1713 smp_mb__after_atomic_inc(); 1714 1715 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1716 1717 return; 1718 } 1719 1720 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 1721 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) 1722 { 1723 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; 1724 1725 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, 1726 start); 1727 } 1728 1729 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1730 { 1731 struct bnx2x *bp = netdev_priv(dev_instance); 1732 u16 status = bnx2x_ack_int(bp); 1733 u16 mask; 1734 int i; 1735 u8 cos; 1736 1737 /* Return here if interrupt is shared and it's not for us */ 1738 if (unlikely(status == 0)) { 1739 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1740 return IRQ_NONE; 1741 } 1742 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1743 1744 #ifdef BNX2X_STOP_ON_ERROR 1745 if (unlikely(bp->panic)) 1746 return IRQ_HANDLED; 1747 #endif 1748 1749 for_each_eth_queue(bp, i) { 1750 struct bnx2x_fastpath *fp = &bp->fp[i]; 1751 1752 mask = 0x2 << (fp->index + CNIC_PRESENT); 1753 if (status & mask) { 1754 /* Handle Rx or Tx according to SB id */ 1755 prefetch(fp->rx_cons_sb); 1756 for_each_cos_in_tx_queue(fp, cos) 1757 prefetch(fp->txdata[cos].tx_cons_sb); 1758 prefetch(&fp->sb_running_index[SM_RX_ID]); 1759 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1760 status &= ~mask; 1761 } 1762 } 1763 1764 #ifdef BCM_CNIC 1765 mask = 0x2; 1766 if (status & (mask | 0x1)) { 1767 struct cnic_ops *c_ops = NULL; 1768 1769 if (likely(bp->state == BNX2X_STATE_OPEN)) { 1770 rcu_read_lock(); 1771 c_ops = rcu_dereference(bp->cnic_ops); 1772 if (c_ops) 1773 c_ops->cnic_handler(bp->cnic_data, NULL); 1774 rcu_read_unlock(); 1775 } 1776 1777 status &= ~mask; 1778 } 1779 #endif 1780 1781 if (unlikely(status & 0x1)) { 1782 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1783 1784 status &= ~0x1; 1785 if (!status) 1786 return IRQ_HANDLED; 1787 } 1788 1789 if (unlikely(status)) 1790 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1791 status); 1792 1793 return IRQ_HANDLED; 1794 } 1795 1796 /* Link */ 1797 1798 /* 1799 * General service functions 1800 */ 1801 1802 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1803 { 1804 u32 lock_status; 1805 u32 resource_bit = (1 << resource); 1806 int func = BP_FUNC(bp); 1807 u32 hw_lock_control_reg; 1808 int cnt; 1809 1810 /* Validating that the resource is within range */ 1811 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1812 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1813 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1814 return -EINVAL; 1815 } 1816 1817 if (func <= 5) { 1818 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1819 } else { 1820 hw_lock_control_reg = 1821 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1822 } 1823 1824 /* Validating that the resource is not already taken */ 1825 lock_status = REG_RD(bp, hw_lock_control_reg); 1826 if (lock_status & resource_bit) { 1827 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 1828 lock_status, resource_bit); 1829 return -EEXIST; 1830 } 1831 1832 /* Try for 5 second every 5ms */ 1833 for (cnt = 0; cnt < 1000; cnt++) { 1834 /* Try to acquire the lock */ 1835 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1836 lock_status = REG_RD(bp, hw_lock_control_reg); 1837 if (lock_status & resource_bit) 1838 return 0; 1839 1840 msleep(5); 1841 } 1842 BNX2X_ERR("Timeout\n"); 1843 return -EAGAIN; 1844 } 1845 1846 int bnx2x_release_leader_lock(struct bnx2x *bp) 1847 { 1848 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1849 } 1850 1851 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1852 { 1853 u32 lock_status; 1854 u32 resource_bit = (1 << resource); 1855 int func = BP_FUNC(bp); 1856 u32 hw_lock_control_reg; 1857 1858 /* Validating that the resource is within range */ 1859 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1860 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1861 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1862 return -EINVAL; 1863 } 1864 1865 if (func <= 5) { 1866 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1867 } else { 1868 hw_lock_control_reg = 1869 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1870 } 1871 1872 /* Validating that the resource is currently taken */ 1873 lock_status = REG_RD(bp, hw_lock_control_reg); 1874 if (!(lock_status & resource_bit)) { 1875 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", 1876 lock_status, resource_bit); 1877 return -EFAULT; 1878 } 1879 1880 REG_WR(bp, hw_lock_control_reg, resource_bit); 1881 return 0; 1882 } 1883 1884 1885 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 1886 { 1887 /* The GPIO should be swapped if swap register is set and active */ 1888 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1889 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1890 int gpio_shift = gpio_num + 1891 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1892 u32 gpio_mask = (1 << gpio_shift); 1893 u32 gpio_reg; 1894 int value; 1895 1896 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1897 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1898 return -EINVAL; 1899 } 1900 1901 /* read GPIO value */ 1902 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1903 1904 /* get the requested pin value */ 1905 if ((gpio_reg & gpio_mask) == gpio_mask) 1906 value = 1; 1907 else 1908 value = 0; 1909 1910 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); 1911 1912 return value; 1913 } 1914 1915 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 1916 { 1917 /* The GPIO should be swapped if swap register is set and active */ 1918 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1919 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 1920 int gpio_shift = gpio_num + 1921 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 1922 u32 gpio_mask = (1 << gpio_shift); 1923 u32 gpio_reg; 1924 1925 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1926 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 1927 return -EINVAL; 1928 } 1929 1930 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1931 /* read GPIO and mask except the float bits */ 1932 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1933 1934 switch (mode) { 1935 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1936 DP(NETIF_MSG_LINK, 1937 "Set GPIO %d (shift %d) -> output low\n", 1938 gpio_num, gpio_shift); 1939 /* clear FLOAT and set CLR */ 1940 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1941 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1942 break; 1943 1944 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1945 DP(NETIF_MSG_LINK, 1946 "Set GPIO %d (shift %d) -> output high\n", 1947 gpio_num, gpio_shift); 1948 /* clear FLOAT and set SET */ 1949 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1950 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1951 break; 1952 1953 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1954 DP(NETIF_MSG_LINK, 1955 "Set GPIO %d (shift %d) -> input\n", 1956 gpio_num, gpio_shift); 1957 /* set FLOAT */ 1958 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1959 break; 1960 1961 default: 1962 break; 1963 } 1964 1965 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1966 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1967 1968 return 0; 1969 } 1970 1971 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 1972 { 1973 u32 gpio_reg = 0; 1974 int rc = 0; 1975 1976 /* Any port swapping should be handled by caller. */ 1977 1978 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1979 /* read GPIO and mask except the float bits */ 1980 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 1981 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 1982 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 1983 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 1984 1985 switch (mode) { 1986 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1987 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 1988 /* set CLR */ 1989 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 1990 break; 1991 1992 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1993 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 1994 /* set SET */ 1995 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 1996 break; 1997 1998 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1999 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2000 /* set FLOAT */ 2001 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2002 break; 2003 2004 default: 2005 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2006 rc = -EINVAL; 2007 break; 2008 } 2009 2010 if (rc == 0) 2011 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2012 2013 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2014 2015 return rc; 2016 } 2017 2018 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2019 { 2020 /* The GPIO should be swapped if swap register is set and active */ 2021 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2022 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2023 int gpio_shift = gpio_num + 2024 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2025 u32 gpio_mask = (1 << gpio_shift); 2026 u32 gpio_reg; 2027 2028 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2029 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2030 return -EINVAL; 2031 } 2032 2033 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2034 /* read GPIO int */ 2035 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2036 2037 switch (mode) { 2038 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2039 DP(NETIF_MSG_LINK, 2040 "Clear GPIO INT %d (shift %d) -> output low\n", 2041 gpio_num, gpio_shift); 2042 /* clear SET and set CLR */ 2043 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2044 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2045 break; 2046 2047 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2048 DP(NETIF_MSG_LINK, 2049 "Set GPIO INT %d (shift %d) -> output high\n", 2050 gpio_num, gpio_shift); 2051 /* clear CLR and set SET */ 2052 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2053 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2054 break; 2055 2056 default: 2057 break; 2058 } 2059 2060 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2061 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2062 2063 return 0; 2064 } 2065 2066 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) 2067 { 2068 u32 spio_mask = (1 << spio_num); 2069 u32 spio_reg; 2070 2071 if ((spio_num < MISC_REGISTERS_SPIO_4) || 2072 (spio_num > MISC_REGISTERS_SPIO_7)) { 2073 BNX2X_ERR("Invalid SPIO %d\n", spio_num); 2074 return -EINVAL; 2075 } 2076 2077 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2078 /* read SPIO and mask except the float bits */ 2079 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 2080 2081 switch (mode) { 2082 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2083 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num); 2084 /* clear FLOAT and set CLR */ 2085 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2086 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2087 break; 2088 2089 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2090 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num); 2091 /* clear FLOAT and set SET */ 2092 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2093 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2094 break; 2095 2096 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2097 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num); 2098 /* set FLOAT */ 2099 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2100 break; 2101 2102 default: 2103 break; 2104 } 2105 2106 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2107 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2108 2109 return 0; 2110 } 2111 2112 void bnx2x_calc_fc_adv(struct bnx2x *bp) 2113 { 2114 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2115 switch (bp->link_vars.ieee_fc & 2116 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2117 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 2118 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2119 ADVERTISED_Pause); 2120 break; 2121 2122 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2123 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2124 ADVERTISED_Pause); 2125 break; 2126 2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2128 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2129 break; 2130 2131 default: 2132 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2133 ADVERTISED_Pause); 2134 break; 2135 } 2136 } 2137 2138 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2139 { 2140 if (!BP_NOMCP(bp)) { 2141 u8 rc; 2142 int cfx_idx = bnx2x_get_link_cfg_idx(bp); 2143 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2144 /* 2145 * Initialize link parameters structure variables 2146 * It is recommended to turn off RX FC for jumbo frames 2147 * for better performance 2148 */ 2149 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2150 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2151 else 2152 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2153 2154 bnx2x_acquire_phy_lock(bp); 2155 2156 if (load_mode == LOAD_DIAG) { 2157 struct link_params *lp = &bp->link_params; 2158 lp->loopback_mode = LOOPBACK_XGXS; 2159 /* do PHY loopback at 10G speed, if possible */ 2160 if (lp->req_line_speed[cfx_idx] < SPEED_10000) { 2161 if (lp->speed_cap_mask[cfx_idx] & 2162 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2163 lp->req_line_speed[cfx_idx] = 2164 SPEED_10000; 2165 else 2166 lp->req_line_speed[cfx_idx] = 2167 SPEED_1000; 2168 } 2169 } 2170 2171 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2172 2173 bnx2x_release_phy_lock(bp); 2174 2175 bnx2x_calc_fc_adv(bp); 2176 2177 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) { 2178 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2179 bnx2x_link_report(bp); 2180 } else 2181 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2182 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2183 return rc; 2184 } 2185 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2186 return -EINVAL; 2187 } 2188 2189 void bnx2x_link_set(struct bnx2x *bp) 2190 { 2191 if (!BP_NOMCP(bp)) { 2192 bnx2x_acquire_phy_lock(bp); 2193 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2194 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2195 bnx2x_release_phy_lock(bp); 2196 2197 bnx2x_calc_fc_adv(bp); 2198 } else 2199 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2200 } 2201 2202 static void bnx2x__link_reset(struct bnx2x *bp) 2203 { 2204 if (!BP_NOMCP(bp)) { 2205 bnx2x_acquire_phy_lock(bp); 2206 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2207 bnx2x_release_phy_lock(bp); 2208 } else 2209 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2210 } 2211 2212 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2213 { 2214 u8 rc = 0; 2215 2216 if (!BP_NOMCP(bp)) { 2217 bnx2x_acquire_phy_lock(bp); 2218 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2219 is_serdes); 2220 bnx2x_release_phy_lock(bp); 2221 } else 2222 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2223 2224 return rc; 2225 } 2226 2227 static void bnx2x_init_port_minmax(struct bnx2x *bp) 2228 { 2229 u32 r_param = bp->link_vars.line_speed / 8; 2230 u32 fair_periodic_timeout_usec; 2231 u32 t_fair; 2232 2233 memset(&(bp->cmng.rs_vars), 0, 2234 sizeof(struct rate_shaping_vars_per_port)); 2235 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port)); 2236 2237 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */ 2238 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4; 2239 2240 /* this is the threshold below which no timer arming will occur 2241 1.25 coefficient is for the threshold to be a little bigger 2242 than the real time, to compensate for timer in-accuracy */ 2243 bp->cmng.rs_vars.rs_threshold = 2244 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4; 2245 2246 /* resolution of fairness timer */ 2247 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 2248 /* for 10G it is 1000usec. for 1G it is 10000usec. */ 2249 t_fair = T_FAIR_COEF / bp->link_vars.line_speed; 2250 2251 /* this is the threshold below which we won't arm the timer anymore */ 2252 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES; 2253 2254 /* we multiply by 1e3/8 to get bytes/msec. 2255 We don't want the credits to pass a credit 2256 of the t_fair*FAIR_MEM (algorithm resolution) */ 2257 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM; 2258 /* since each tick is 4 usec */ 2259 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4; 2260 } 2261 2262 /* Calculates the sum of vn_min_rates. 2263 It's needed for further normalizing of the min_rates. 2264 Returns: 2265 sum of vn_min_rates. 2266 or 2267 0 - if all the min_rates are 0. 2268 In the later case fainess algorithm should be deactivated. 2269 If not all min_rates are zero then those that are zeroes will be set to 1. 2270 */ 2271 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 2272 { 2273 int all_zero = 1; 2274 int vn; 2275 2276 bp->vn_weight_sum = 0; 2277 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2278 u32 vn_cfg = bp->mf_config[vn]; 2279 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2280 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2281 2282 /* Skip hidden vns */ 2283 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2284 continue; 2285 2286 /* If min rate is zero - set it to 1 */ 2287 if (!vn_min_rate) 2288 vn_min_rate = DEF_MIN_RATE; 2289 else 2290 all_zero = 0; 2291 2292 bp->vn_weight_sum += vn_min_rate; 2293 } 2294 2295 /* if ETS or all min rates are zeros - disable fairness */ 2296 if (BNX2X_IS_ETS_ENABLED(bp)) { 2297 bp->cmng.flags.cmng_enables &= 2298 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2299 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2300 } else if (all_zero) { 2301 bp->cmng.flags.cmng_enables &= 2302 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2303 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2304 " fairness will be disabled\n"); 2305 } else 2306 bp->cmng.flags.cmng_enables |= 2307 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2308 } 2309 2310 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2311 { 2312 struct rate_shaping_vars_per_vn m_rs_vn; 2313 struct fairness_vars_per_vn m_fair_vn; 2314 u32 vn_cfg = bp->mf_config[vn]; 2315 int func = func_by_vn(bp, vn); 2316 u16 vn_min_rate, vn_max_rate; 2317 int i; 2318 2319 /* If function is hidden - set min and max to zeroes */ 2320 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 2321 vn_min_rate = 0; 2322 vn_max_rate = 0; 2323 2324 } else { 2325 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2326 2327 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2328 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2329 /* If fairness is enabled (not all min rates are zeroes) and 2330 if current min rate is zero - set it to 1. 2331 This is a requirement of the algorithm. */ 2332 if (bp->vn_weight_sum && (vn_min_rate == 0)) 2333 vn_min_rate = DEF_MIN_RATE; 2334 2335 if (IS_MF_SI(bp)) 2336 /* maxCfg in percents of linkspeed */ 2337 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2338 else 2339 /* maxCfg is absolute in 100Mb units */ 2340 vn_max_rate = maxCfg * 100; 2341 } 2342 2343 DP(NETIF_MSG_IFUP, 2344 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 2345 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 2346 2347 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn)); 2348 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn)); 2349 2350 /* global vn counter - maximal Mbps for this vn */ 2351 m_rs_vn.vn_counter.rate = vn_max_rate; 2352 2353 /* quota - number of bytes transmitted in this period */ 2354 m_rs_vn.vn_counter.quota = 2355 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8; 2356 2357 if (bp->vn_weight_sum) { 2358 /* credit for each period of the fairness algorithm: 2359 number of bytes in T_FAIR (the vn share the port rate). 2360 vn_weight_sum should not be larger than 10000, thus 2361 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater 2362 than zero */ 2363 m_fair_vn.vn_credit_delta = 2364 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2365 (8 * bp->vn_weight_sum))), 2366 (bp->cmng.fair_vars.fair_threshold + 2367 MIN_ABOVE_THRESH)); 2368 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2369 m_fair_vn.vn_credit_delta); 2370 } 2371 2372 /* Store it to internal memory */ 2373 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++) 2374 REG_WR(bp, BAR_XSTRORM_INTMEM + 2375 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4, 2376 ((u32 *)(&m_rs_vn))[i]); 2377 2378 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++) 2379 REG_WR(bp, BAR_XSTRORM_INTMEM + 2380 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4, 2381 ((u32 *)(&m_fair_vn))[i]); 2382 } 2383 2384 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2385 { 2386 if (CHIP_REV_IS_SLOW(bp)) 2387 return CMNG_FNS_NONE; 2388 if (IS_MF(bp)) 2389 return CMNG_FNS_MINMAX; 2390 2391 return CMNG_FNS_NONE; 2392 } 2393 2394 void bnx2x_read_mf_cfg(struct bnx2x *bp) 2395 { 2396 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2397 2398 if (BP_NOMCP(bp)) 2399 return; /* what should be the default bvalue in this case */ 2400 2401 /* For 2 port configuration the absolute function number formula 2402 * is: 2403 * abs_func = 2 * vn + BP_PORT + BP_PATH 2404 * 2405 * and there are 4 functions per port 2406 * 2407 * For 4 port configuration it is 2408 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2409 * 2410 * and there are 2 functions per port 2411 */ 2412 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2413 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2414 2415 if (func >= E1H_FUNC_MAX) 2416 break; 2417 2418 bp->mf_config[vn] = 2419 MF_CFG_RD(bp, func_mf_config[func].config); 2420 } 2421 } 2422 2423 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2424 { 2425 2426 if (cmng_type == CMNG_FNS_MINMAX) { 2427 int vn; 2428 2429 /* clear cmng_enables */ 2430 bp->cmng.flags.cmng_enables = 0; 2431 2432 /* read mf conf from shmem */ 2433 if (read_cfg) 2434 bnx2x_read_mf_cfg(bp); 2435 2436 /* Init rate shaping and fairness contexts */ 2437 bnx2x_init_port_minmax(bp); 2438 2439 /* vn_weight_sum and enable fairness if not 0 */ 2440 bnx2x_calc_vn_weight_sum(bp); 2441 2442 /* calculate and set min-max rate for each vn */ 2443 if (bp->port.pmf) 2444 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2445 bnx2x_init_vn_minmax(bp, vn); 2446 2447 /* always enable rate shaping and fairness */ 2448 bp->cmng.flags.cmng_enables |= 2449 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2450 if (!bp->vn_weight_sum) 2451 DP(NETIF_MSG_IFUP, "All MIN values are zeroes" 2452 " fairness will be disabled\n"); 2453 return; 2454 } 2455 2456 /* rate shaping and fairness are disabled */ 2457 DP(NETIF_MSG_IFUP, 2458 "rate shaping and fairness are disabled\n"); 2459 } 2460 2461 /* This function is called upon link interrupt */ 2462 static void bnx2x_link_attn(struct bnx2x *bp) 2463 { 2464 /* Make sure that we are synced with the current statistics */ 2465 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2466 2467 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2468 2469 if (bp->link_vars.link_up) { 2470 2471 /* dropless flow control */ 2472 if (!CHIP_IS_E1(bp) && bp->dropless_fc) { 2473 int port = BP_PORT(bp); 2474 u32 pause_enabled = 0; 2475 2476 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2477 pause_enabled = 1; 2478 2479 REG_WR(bp, BAR_USTRORM_INTMEM + 2480 USTORM_ETH_PAUSE_ENABLED_OFFSET(port), 2481 pause_enabled); 2482 } 2483 2484 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2485 struct host_port_stats *pstats; 2486 2487 pstats = bnx2x_sp(bp, port_stats); 2488 /* reset old mac stats */ 2489 memset(&(pstats->mac_stx[0]), 0, 2490 sizeof(struct mac_stx)); 2491 } 2492 if (bp->state == BNX2X_STATE_OPEN) 2493 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2494 } 2495 2496 if (bp->link_vars.link_up && bp->link_vars.line_speed) { 2497 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2498 2499 if (cmng_fns != CMNG_FNS_NONE) { 2500 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2501 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2502 } else 2503 /* rate shaping and fairness are disabled */ 2504 DP(NETIF_MSG_IFUP, 2505 "single function mode without fairness\n"); 2506 } 2507 2508 __bnx2x_link_report(bp); 2509 2510 if (IS_MF(bp)) 2511 bnx2x_link_sync_notify(bp); 2512 } 2513 2514 void bnx2x__link_status_update(struct bnx2x *bp) 2515 { 2516 if (bp->state != BNX2X_STATE_OPEN) 2517 return; 2518 2519 /* read updated dcb configuration */ 2520 bnx2x_dcbx_pmf_update(bp); 2521 2522 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2523 2524 if (bp->link_vars.link_up) 2525 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2526 else 2527 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2528 2529 /* indicate link status */ 2530 bnx2x_link_report(bp); 2531 } 2532 2533 static void bnx2x_pmf_update(struct bnx2x *bp) 2534 { 2535 int port = BP_PORT(bp); 2536 u32 val; 2537 2538 bp->port.pmf = 1; 2539 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2540 2541 /* 2542 * We need the mb() to ensure the ordering between the writing to 2543 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2544 */ 2545 smp_mb(); 2546 2547 /* queue a periodic task */ 2548 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2549 2550 bnx2x_dcbx_pmf_update(bp); 2551 2552 /* enable nig attention */ 2553 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2554 if (bp->common.int_block == INT_BLOCK_HC) { 2555 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2556 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2557 } else if (!CHIP_IS_E1x(bp)) { 2558 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 2559 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 2560 } 2561 2562 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2563 } 2564 2565 /* end of Link */ 2566 2567 /* slow path */ 2568 2569 /* 2570 * General service functions 2571 */ 2572 2573 /* send the MCP a request, block until there is a reply */ 2574 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 2575 { 2576 int mb_idx = BP_FW_MB_IDX(bp); 2577 u32 seq; 2578 u32 rc = 0; 2579 u32 cnt = 1; 2580 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2581 2582 mutex_lock(&bp->fw_mb_mutex); 2583 seq = ++bp->fw_seq; 2584 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 2585 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 2586 2587 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 2588 (command | seq), param); 2589 2590 do { 2591 /* let the FW do it's magic ... */ 2592 msleep(delay); 2593 2594 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 2595 2596 /* Give the FW up to 5 second (500*10ms) */ 2597 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2598 2599 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 2600 cnt*delay, rc, seq); 2601 2602 /* is this a reply to our command? */ 2603 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 2604 rc &= FW_MSG_CODE_MASK; 2605 else { 2606 /* FW BUG! */ 2607 BNX2X_ERR("FW failed to respond!\n"); 2608 bnx2x_fw_dump(bp); 2609 rc = 0; 2610 } 2611 mutex_unlock(&bp->fw_mb_mutex); 2612 2613 return rc; 2614 } 2615 2616 2617 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 2618 { 2619 if (CHIP_IS_E1x(bp)) { 2620 struct tstorm_eth_function_common_config tcfg = {0}; 2621 2622 storm_memset_func_cfg(bp, &tcfg, p->func_id); 2623 } 2624 2625 /* Enable the function in the FW */ 2626 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 2627 storm_memset_func_en(bp, p->func_id, 1); 2628 2629 /* spq */ 2630 if (p->func_flgs & FUNC_FLG_SPQ) { 2631 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 2632 REG_WR(bp, XSEM_REG_FAST_MEMORY + 2633 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 2634 } 2635 } 2636 2637 /** 2638 * bnx2x_get_tx_only_flags - Return common flags 2639 * 2640 * @bp device handle 2641 * @fp queue handle 2642 * @zero_stats TRUE if statistics zeroing is needed 2643 * 2644 * Return the flags that are common for the Tx-only and not normal connections. 2645 */ 2646 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 2647 struct bnx2x_fastpath *fp, 2648 bool zero_stats) 2649 { 2650 unsigned long flags = 0; 2651 2652 /* PF driver will always initialize the Queue to an ACTIVE state */ 2653 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 2654 2655 /* tx only connections collect statistics (on the same index as the 2656 * parent connection). The statistics are zeroed when the parent 2657 * connection is initialized. 2658 */ 2659 2660 __set_bit(BNX2X_Q_FLG_STATS, &flags); 2661 if (zero_stats) 2662 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 2663 2664 2665 return flags; 2666 } 2667 2668 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 2669 struct bnx2x_fastpath *fp, 2670 bool leading) 2671 { 2672 unsigned long flags = 0; 2673 2674 /* calculate other queue flags */ 2675 if (IS_MF_SD(bp)) 2676 __set_bit(BNX2X_Q_FLG_OV, &flags); 2677 2678 if (IS_FCOE_FP(fp)) 2679 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 2680 2681 if (!fp->disable_tpa) { 2682 __set_bit(BNX2X_Q_FLG_TPA, &flags); 2683 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 2684 if (fp->mode == TPA_MODE_GRO) 2685 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 2686 } 2687 2688 if (leading) { 2689 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 2690 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 2691 } 2692 2693 /* Always set HW VLAN stripping */ 2694 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 2695 2696 2697 return flags | bnx2x_get_common_flags(bp, fp, true); 2698 } 2699 2700 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 2701 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 2702 u8 cos) 2703 { 2704 gen_init->stat_id = bnx2x_stats_id(fp); 2705 gen_init->spcl_id = fp->cl_id; 2706 2707 /* Always use mini-jumbo MTU for FCoE L2 ring */ 2708 if (IS_FCOE_FP(fp)) 2709 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 2710 else 2711 gen_init->mtu = bp->dev->mtu; 2712 2713 gen_init->cos = cos; 2714 } 2715 2716 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 2717 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 2718 struct bnx2x_rxq_setup_params *rxq_init) 2719 { 2720 u8 max_sge = 0; 2721 u16 sge_sz = 0; 2722 u16 tpa_agg_size = 0; 2723 2724 if (!fp->disable_tpa) { 2725 pause->sge_th_lo = SGE_TH_LO(bp); 2726 pause->sge_th_hi = SGE_TH_HI(bp); 2727 2728 /* validate SGE ring has enough to cross high threshold */ 2729 WARN_ON(bp->dropless_fc && 2730 pause->sge_th_hi + FW_PREFETCH_CNT > 2731 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 2732 2733 tpa_agg_size = min_t(u32, 2734 (min_t(u32, 8, MAX_SKB_FRAGS) * 2735 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 2736 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 2737 SGE_PAGE_SHIFT; 2738 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 2739 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 2740 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, 2741 0xffff); 2742 } 2743 2744 /* pause - not for e1 */ 2745 if (!CHIP_IS_E1(bp)) { 2746 pause->bd_th_lo = BD_TH_LO(bp); 2747 pause->bd_th_hi = BD_TH_HI(bp); 2748 2749 pause->rcq_th_lo = RCQ_TH_LO(bp); 2750 pause->rcq_th_hi = RCQ_TH_HI(bp); 2751 /* 2752 * validate that rings have enough entries to cross 2753 * high thresholds 2754 */ 2755 WARN_ON(bp->dropless_fc && 2756 pause->bd_th_hi + FW_PREFETCH_CNT > 2757 bp->rx_ring_size); 2758 WARN_ON(bp->dropless_fc && 2759 pause->rcq_th_hi + FW_PREFETCH_CNT > 2760 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 2761 2762 pause->pri_map = 1; 2763 } 2764 2765 /* rxq setup */ 2766 rxq_init->dscr_map = fp->rx_desc_mapping; 2767 rxq_init->sge_map = fp->rx_sge_mapping; 2768 rxq_init->rcq_map = fp->rx_comp_mapping; 2769 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 2770 2771 /* This should be a maximum number of data bytes that may be 2772 * placed on the BD (not including paddings). 2773 */ 2774 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 2775 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 2776 2777 rxq_init->cl_qzone_id = fp->cl_qzone_id; 2778 rxq_init->tpa_agg_sz = tpa_agg_size; 2779 rxq_init->sge_buf_sz = sge_sz; 2780 rxq_init->max_sges_pkt = max_sge; 2781 rxq_init->rss_engine_id = BP_FUNC(bp); 2782 rxq_init->mcast_engine_id = BP_FUNC(bp); 2783 2784 /* Maximum number or simultaneous TPA aggregation for this Queue. 2785 * 2786 * For PF Clients it should be the maximum avaliable number. 2787 * VF driver(s) may want to define it to a smaller value. 2788 */ 2789 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 2790 2791 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 2792 rxq_init->fw_sb_id = fp->fw_sb_id; 2793 2794 if (IS_FCOE_FP(fp)) 2795 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 2796 else 2797 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 2798 } 2799 2800 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 2801 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 2802 u8 cos) 2803 { 2804 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping; 2805 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 2806 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 2807 txq_init->fw_sb_id = fp->fw_sb_id; 2808 2809 /* 2810 * set the tss leading client id for TX classfication == 2811 * leading RSS client id 2812 */ 2813 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 2814 2815 if (IS_FCOE_FP(fp)) { 2816 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 2817 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 2818 } 2819 } 2820 2821 static void bnx2x_pf_init(struct bnx2x *bp) 2822 { 2823 struct bnx2x_func_init_params func_init = {0}; 2824 struct event_ring_data eq_data = { {0} }; 2825 u16 flags; 2826 2827 if (!CHIP_IS_E1x(bp)) { 2828 /* reset IGU PF statistics: MSIX + ATTN */ 2829 /* PF */ 2830 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2831 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2832 (CHIP_MODE_IS_4_PORT(bp) ? 2833 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2834 /* ATTN */ 2835 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 2836 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 2837 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 2838 (CHIP_MODE_IS_4_PORT(bp) ? 2839 BP_FUNC(bp) : BP_VN(bp))*4, 0); 2840 } 2841 2842 /* function setup flags */ 2843 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 2844 2845 /* This flag is relevant for E1x only. 2846 * E2 doesn't have a TPA configuration in a function level. 2847 */ 2848 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; 2849 2850 func_init.func_flgs = flags; 2851 func_init.pf_id = BP_FUNC(bp); 2852 func_init.func_id = BP_FUNC(bp); 2853 func_init.spq_map = bp->spq_mapping; 2854 func_init.spq_prod = bp->spq_prod_idx; 2855 2856 bnx2x_func_init(bp, &func_init); 2857 2858 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 2859 2860 /* 2861 * Congestion management values depend on the link rate 2862 * There is no active link so initial link rate is set to 10 Gbps. 2863 * When the link comes up The congestion management values are 2864 * re-calculated according to the actual link rate. 2865 */ 2866 bp->link_vars.line_speed = SPEED_10000; 2867 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 2868 2869 /* Only the PMF sets the HW */ 2870 if (bp->port.pmf) 2871 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2872 2873 /* init Event Queue */ 2874 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 2875 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 2876 eq_data.producer = bp->eq_prod; 2877 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 2878 eq_data.sb_id = DEF_SB_ID; 2879 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 2880 } 2881 2882 2883 static void bnx2x_e1h_disable(struct bnx2x *bp) 2884 { 2885 int port = BP_PORT(bp); 2886 2887 bnx2x_tx_disable(bp); 2888 2889 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2890 } 2891 2892 static void bnx2x_e1h_enable(struct bnx2x *bp) 2893 { 2894 int port = BP_PORT(bp); 2895 2896 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2897 2898 /* Tx queue should be only reenabled */ 2899 netif_tx_wake_all_queues(bp->dev); 2900 2901 /* 2902 * Should not call netif_carrier_on since it will be called if the link 2903 * is up when checking for link state 2904 */ 2905 } 2906 2907 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 2908 2909 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 2910 { 2911 struct eth_stats_info *ether_stat = 2912 &bp->slowpath->drv_info_to_mcp.ether_stat; 2913 2914 /* leave last char as NULL */ 2915 memcpy(ether_stat->version, DRV_MODULE_VERSION, 2916 ETH_STAT_INFO_VERSION_LEN - 1); 2917 2918 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj, 2919 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 2920 ether_stat->mac_local); 2921 2922 ether_stat->mtu_size = bp->dev->mtu; 2923 2924 if (bp->dev->features & NETIF_F_RXCSUM) 2925 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 2926 if (bp->dev->features & NETIF_F_TSO) 2927 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 2928 ether_stat->feature_flags |= bp->common.boot_mode; 2929 2930 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 2931 2932 ether_stat->txq_size = bp->tx_ring_size; 2933 ether_stat->rxq_size = bp->rx_ring_size; 2934 } 2935 2936 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 2937 { 2938 #ifdef BCM_CNIC 2939 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 2940 struct fcoe_stats_info *fcoe_stat = 2941 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 2942 2943 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN); 2944 2945 fcoe_stat->qos_priority = 2946 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 2947 2948 /* insert FCoE stats from ramrod response */ 2949 if (!NO_FCOE(bp)) { 2950 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 2951 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2952 tstorm_queue_statistics; 2953 2954 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 2955 &bp->fw_stats_data->queue_stats[FCOE_IDX]. 2956 xstorm_queue_statistics; 2957 2958 struct fcoe_statistics_params *fw_fcoe_stat = 2959 &bp->fw_stats_data->fcoe; 2960 2961 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, 2962 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 2963 2964 ADD_64(fcoe_stat->rx_bytes_hi, 2965 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 2966 fcoe_stat->rx_bytes_lo, 2967 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 2968 2969 ADD_64(fcoe_stat->rx_bytes_hi, 2970 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 2971 fcoe_stat->rx_bytes_lo, 2972 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 2973 2974 ADD_64(fcoe_stat->rx_bytes_hi, 2975 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 2976 fcoe_stat->rx_bytes_lo, 2977 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 2978 2979 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2980 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 2981 2982 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2983 fcoe_q_tstorm_stats->rcv_ucast_pkts); 2984 2985 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2986 fcoe_q_tstorm_stats->rcv_bcast_pkts); 2987 2988 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, 2989 fcoe_q_tstorm_stats->rcv_mcast_pkts); 2990 2991 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, 2992 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 2993 2994 ADD_64(fcoe_stat->tx_bytes_hi, 2995 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 2996 fcoe_stat->tx_bytes_lo, 2997 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 2998 2999 ADD_64(fcoe_stat->tx_bytes_hi, 3000 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3001 fcoe_stat->tx_bytes_lo, 3002 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3003 3004 ADD_64(fcoe_stat->tx_bytes_hi, 3005 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3006 fcoe_stat->tx_bytes_lo, 3007 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3008 3009 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3010 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3011 3012 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3013 fcoe_q_xstorm_stats->ucast_pkts_sent); 3014 3015 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3016 fcoe_q_xstorm_stats->bcast_pkts_sent); 3017 3018 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, 3019 fcoe_q_xstorm_stats->mcast_pkts_sent); 3020 } 3021 3022 /* ask L5 driver to add data to the struct */ 3023 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3024 #endif 3025 } 3026 3027 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3028 { 3029 #ifdef BCM_CNIC 3030 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3031 struct iscsi_stats_info *iscsi_stat = 3032 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3033 3034 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); 3035 3036 iscsi_stat->qos_priority = 3037 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3038 3039 /* ask L5 driver to add data to the struct */ 3040 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3041 #endif 3042 } 3043 3044 /* called due to MCP event (on pmf): 3045 * reread new bandwidth configuration 3046 * configure FW 3047 * notify others function about the change 3048 */ 3049 static inline void bnx2x_config_mf_bw(struct bnx2x *bp) 3050 { 3051 if (bp->link_vars.link_up) { 3052 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3053 bnx2x_link_sync_notify(bp); 3054 } 3055 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3056 } 3057 3058 static inline void bnx2x_set_mf_bw(struct bnx2x *bp) 3059 { 3060 bnx2x_config_mf_bw(bp); 3061 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3062 } 3063 3064 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3065 { 3066 enum drv_info_opcode op_code; 3067 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3068 3069 /* if drv_info version supported by MFW doesn't match - send NACK */ 3070 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3071 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3072 return; 3073 } 3074 3075 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3076 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3077 3078 memset(&bp->slowpath->drv_info_to_mcp, 0, 3079 sizeof(union drv_info_to_mcp)); 3080 3081 switch (op_code) { 3082 case ETH_STATS_OPCODE: 3083 bnx2x_drv_info_ether_stat(bp); 3084 break; 3085 case FCOE_STATS_OPCODE: 3086 bnx2x_drv_info_fcoe_stat(bp); 3087 break; 3088 case ISCSI_STATS_OPCODE: 3089 bnx2x_drv_info_iscsi_stat(bp); 3090 break; 3091 default: 3092 /* if op code isn't supported - send NACK */ 3093 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3094 return; 3095 } 3096 3097 /* if we got drv_info attn from MFW then these fields are defined in 3098 * shmem2 for sure 3099 */ 3100 SHMEM2_WR(bp, drv_info_host_addr_lo, 3101 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3102 SHMEM2_WR(bp, drv_info_host_addr_hi, 3103 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3104 3105 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3106 } 3107 3108 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 3109 { 3110 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); 3111 3112 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 3113 3114 /* 3115 * This is the only place besides the function initialization 3116 * where the bp->flags can change so it is done without any 3117 * locks 3118 */ 3119 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3120 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3121 bp->flags |= MF_FUNC_DIS; 3122 3123 bnx2x_e1h_disable(bp); 3124 } else { 3125 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3126 bp->flags &= ~MF_FUNC_DIS; 3127 3128 bnx2x_e1h_enable(bp); 3129 } 3130 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 3131 } 3132 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 3133 bnx2x_config_mf_bw(bp); 3134 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 3135 } 3136 3137 /* Report results to MCP */ 3138 if (dcc_event) 3139 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); 3140 else 3141 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); 3142 } 3143 3144 /* must be called under the spq lock */ 3145 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3146 { 3147 struct eth_spe *next_spe = bp->spq_prod_bd; 3148 3149 if (bp->spq_prod_bd == bp->spq_last_bd) { 3150 bp->spq_prod_bd = bp->spq; 3151 bp->spq_prod_idx = 0; 3152 DP(BNX2X_MSG_SP, "end of spq\n"); 3153 } else { 3154 bp->spq_prod_bd++; 3155 bp->spq_prod_idx++; 3156 } 3157 return next_spe; 3158 } 3159 3160 /* must be called under the spq lock */ 3161 static inline void bnx2x_sp_prod_update(struct bnx2x *bp) 3162 { 3163 int func = BP_FUNC(bp); 3164 3165 /* 3166 * Make sure that BD data is updated before writing the producer: 3167 * BD data is written to the memory, the producer is read from the 3168 * memory, thus we need a full memory barrier to ensure the ordering. 3169 */ 3170 mb(); 3171 3172 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3173 bp->spq_prod_idx); 3174 mmiowb(); 3175 } 3176 3177 /** 3178 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3179 * 3180 * @cmd: command to check 3181 * @cmd_type: command type 3182 */ 3183 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3184 { 3185 if ((cmd_type == NONE_CONNECTION_TYPE) || 3186 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3187 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3188 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3189 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3190 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3191 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3192 return true; 3193 else 3194 return false; 3195 3196 } 3197 3198 3199 /** 3200 * bnx2x_sp_post - place a single command on an SP ring 3201 * 3202 * @bp: driver handle 3203 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3204 * @cid: SW CID the command is related to 3205 * @data_hi: command private data address (high 32 bits) 3206 * @data_lo: command private data address (low 32 bits) 3207 * @cmd_type: command type (e.g. NONE, ETH) 3208 * 3209 * SP data is handled as if it's always an address pair, thus data fields are 3210 * not swapped to little endian in upper functions. Instead this function swaps 3211 * data as if it's two u32 fields. 3212 */ 3213 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3214 u32 data_hi, u32 data_lo, int cmd_type) 3215 { 3216 struct eth_spe *spe; 3217 u16 type; 3218 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3219 3220 #ifdef BNX2X_STOP_ON_ERROR 3221 if (unlikely(bp->panic)) { 3222 BNX2X_ERR("Can't post SP when there is panic\n"); 3223 return -EIO; 3224 } 3225 #endif 3226 3227 spin_lock_bh(&bp->spq_lock); 3228 3229 if (common) { 3230 if (!atomic_read(&bp->eq_spq_left)) { 3231 BNX2X_ERR("BUG! EQ ring full!\n"); 3232 spin_unlock_bh(&bp->spq_lock); 3233 bnx2x_panic(); 3234 return -EBUSY; 3235 } 3236 } else if (!atomic_read(&bp->cq_spq_left)) { 3237 BNX2X_ERR("BUG! SPQ ring full!\n"); 3238 spin_unlock_bh(&bp->spq_lock); 3239 bnx2x_panic(); 3240 return -EBUSY; 3241 } 3242 3243 spe = bnx2x_sp_get_next(bp); 3244 3245 /* CID needs port number to be encoded int it */ 3246 spe->hdr.conn_and_cmd_data = 3247 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3248 HW_CID(bp, cid)); 3249 3250 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 3251 3252 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3253 SPE_HDR_FUNCTION_ID); 3254 3255 spe->hdr.type = cpu_to_le16(type); 3256 3257 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3258 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3259 3260 /* 3261 * It's ok if the actual decrement is issued towards the memory 3262 * somewhere between the spin_lock and spin_unlock. Thus no 3263 * more explict memory barrier is needed. 3264 */ 3265 if (common) 3266 atomic_dec(&bp->eq_spq_left); 3267 else 3268 atomic_dec(&bp->cq_spq_left); 3269 3270 3271 DP(BNX2X_MSG_SP, 3272 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3273 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3274 (u32)(U64_LO(bp->spq_mapping) + 3275 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3276 HW_CID(bp, cid), data_hi, data_lo, type, 3277 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3278 3279 bnx2x_sp_prod_update(bp); 3280 spin_unlock_bh(&bp->spq_lock); 3281 return 0; 3282 } 3283 3284 /* acquire split MCP access lock register */ 3285 static int bnx2x_acquire_alr(struct bnx2x *bp) 3286 { 3287 u32 j, val; 3288 int rc = 0; 3289 3290 might_sleep(); 3291 for (j = 0; j < 1000; j++) { 3292 val = (1UL << 31); 3293 REG_WR(bp, GRCBASE_MCP + 0x9c, val); 3294 val = REG_RD(bp, GRCBASE_MCP + 0x9c); 3295 if (val & (1L << 31)) 3296 break; 3297 3298 msleep(5); 3299 } 3300 if (!(val & (1L << 31))) { 3301 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3302 rc = -EBUSY; 3303 } 3304 3305 return rc; 3306 } 3307 3308 /* release split MCP access lock register */ 3309 static void bnx2x_release_alr(struct bnx2x *bp) 3310 { 3311 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 3312 } 3313 3314 #define BNX2X_DEF_SB_ATT_IDX 0x0001 3315 #define BNX2X_DEF_SB_IDX 0x0002 3316 3317 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3318 { 3319 struct host_sp_status_block *def_sb = bp->def_status_blk; 3320 u16 rc = 0; 3321 3322 barrier(); /* status block is written to by the chip */ 3323 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3324 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3325 rc |= BNX2X_DEF_SB_ATT_IDX; 3326 } 3327 3328 if (bp->def_idx != def_sb->sp_sb.running_index) { 3329 bp->def_idx = def_sb->sp_sb.running_index; 3330 rc |= BNX2X_DEF_SB_IDX; 3331 } 3332 3333 /* Do not reorder: indecies reading should complete before handling */ 3334 barrier(); 3335 return rc; 3336 } 3337 3338 /* 3339 * slow path service functions 3340 */ 3341 3342 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 3343 { 3344 int port = BP_PORT(bp); 3345 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 3346 MISC_REG_AEU_MASK_ATTN_FUNC_0; 3347 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 3348 NIG_REG_MASK_INTERRUPT_PORT0; 3349 u32 aeu_mask; 3350 u32 nig_mask = 0; 3351 u32 reg_addr; 3352 3353 if (bp->attn_state & asserted) 3354 BNX2X_ERR("IGU ERROR\n"); 3355 3356 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3357 aeu_mask = REG_RD(bp, aeu_addr); 3358 3359 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 3360 aeu_mask, asserted); 3361 aeu_mask &= ~(asserted & 0x3ff); 3362 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 3363 3364 REG_WR(bp, aeu_addr, aeu_mask); 3365 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 3366 3367 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 3368 bp->attn_state |= asserted; 3369 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 3370 3371 if (asserted & ATTN_HARD_WIRED_MASK) { 3372 if (asserted & ATTN_NIG_FOR_FUNC) { 3373 3374 bnx2x_acquire_phy_lock(bp); 3375 3376 /* save nig interrupt mask */ 3377 nig_mask = REG_RD(bp, nig_int_mask_addr); 3378 3379 /* If nig_mask is not set, no need to call the update 3380 * function. 3381 */ 3382 if (nig_mask) { 3383 REG_WR(bp, nig_int_mask_addr, 0); 3384 3385 bnx2x_link_attn(bp); 3386 } 3387 3388 /* handle unicore attn? */ 3389 } 3390 if (asserted & ATTN_SW_TIMER_4_FUNC) 3391 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 3392 3393 if (asserted & GPIO_2_FUNC) 3394 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 3395 3396 if (asserted & GPIO_3_FUNC) 3397 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 3398 3399 if (asserted & GPIO_4_FUNC) 3400 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 3401 3402 if (port == 0) { 3403 if (asserted & ATTN_GENERAL_ATTN_1) { 3404 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 3405 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 3406 } 3407 if (asserted & ATTN_GENERAL_ATTN_2) { 3408 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 3409 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 3410 } 3411 if (asserted & ATTN_GENERAL_ATTN_3) { 3412 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 3413 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 3414 } 3415 } else { 3416 if (asserted & ATTN_GENERAL_ATTN_4) { 3417 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 3418 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 3419 } 3420 if (asserted & ATTN_GENERAL_ATTN_5) { 3421 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 3422 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 3423 } 3424 if (asserted & ATTN_GENERAL_ATTN_6) { 3425 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 3426 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 3427 } 3428 } 3429 3430 } /* if hardwired */ 3431 3432 if (bp->common.int_block == INT_BLOCK_HC) 3433 reg_addr = (HC_REG_COMMAND_REG + port*32 + 3434 COMMAND_REG_ATTN_BITS_SET); 3435 else 3436 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 3437 3438 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 3439 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 3440 REG_WR(bp, reg_addr, asserted); 3441 3442 /* now set back the mask */ 3443 if (asserted & ATTN_NIG_FOR_FUNC) { 3444 REG_WR(bp, nig_int_mask_addr, nig_mask); 3445 bnx2x_release_phy_lock(bp); 3446 } 3447 } 3448 3449 static inline void bnx2x_fan_failure(struct bnx2x *bp) 3450 { 3451 int port = BP_PORT(bp); 3452 u32 ext_phy_config; 3453 /* mark the failure */ 3454 ext_phy_config = 3455 SHMEM_RD(bp, 3456 dev_info.port_hw_config[port].external_phy_config); 3457 3458 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 3459 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 3460 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 3461 ext_phy_config); 3462 3463 /* log the failure */ 3464 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 3465 "Please contact OEM Support for assistance\n"); 3466 3467 /* 3468 * Scheudle device reset (unload) 3469 * This is due to some boards consuming sufficient power when driver is 3470 * up to overheat if fan fails. 3471 */ 3472 smp_mb__before_clear_bit(); 3473 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); 3474 smp_mb__after_clear_bit(); 3475 schedule_delayed_work(&bp->sp_rtnl_task, 0); 3476 3477 } 3478 3479 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 3480 { 3481 int port = BP_PORT(bp); 3482 int reg_offset; 3483 u32 val; 3484 3485 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 3486 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 3487 3488 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 3489 3490 val = REG_RD(bp, reg_offset); 3491 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 3492 REG_WR(bp, reg_offset, val); 3493 3494 BNX2X_ERR("SPIO5 hw attention\n"); 3495 3496 /* Fan failure attention */ 3497 bnx2x_hw_reset_phy(&bp->link_params); 3498 bnx2x_fan_failure(bp); 3499 } 3500 3501 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 3502 bnx2x_acquire_phy_lock(bp); 3503 bnx2x_handle_module_detect_int(&bp->link_params); 3504 bnx2x_release_phy_lock(bp); 3505 } 3506 3507 if (attn & HW_INTERRUT_ASSERT_SET_0) { 3508 3509 val = REG_RD(bp, reg_offset); 3510 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 3511 REG_WR(bp, reg_offset, val); 3512 3513 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 3514 (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); 3515 bnx2x_panic(); 3516 } 3517 } 3518 3519 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 3520 { 3521 u32 val; 3522 3523 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 3524 3525 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 3526 BNX2X_ERR("DB hw attention 0x%x\n", val); 3527 /* DORQ discard attention */ 3528 if (val & 0x2) 3529 BNX2X_ERR("FATAL error from DORQ\n"); 3530 } 3531 3532 if (attn & HW_INTERRUT_ASSERT_SET_1) { 3533 3534 int port = BP_PORT(bp); 3535 int reg_offset; 3536 3537 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 3538 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 3539 3540 val = REG_RD(bp, reg_offset); 3541 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 3542 REG_WR(bp, reg_offset, val); 3543 3544 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 3545 (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); 3546 bnx2x_panic(); 3547 } 3548 } 3549 3550 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 3551 { 3552 u32 val; 3553 3554 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 3555 3556 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 3557 BNX2X_ERR("CFC hw attention 0x%x\n", val); 3558 /* CFC error attention */ 3559 if (val & 0x2) 3560 BNX2X_ERR("FATAL error from CFC\n"); 3561 } 3562 3563 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 3564 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 3565 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 3566 /* RQ_USDMDP_FIFO_OVERFLOW */ 3567 if (val & 0x18000) 3568 BNX2X_ERR("FATAL error from PXP\n"); 3569 3570 if (!CHIP_IS_E1x(bp)) { 3571 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 3572 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 3573 } 3574 } 3575 3576 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3577 3578 int port = BP_PORT(bp); 3579 int reg_offset; 3580 3581 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 3582 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 3583 3584 val = REG_RD(bp, reg_offset); 3585 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 3586 REG_WR(bp, reg_offset, val); 3587 3588 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 3589 (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); 3590 bnx2x_panic(); 3591 } 3592 } 3593 3594 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 3595 { 3596 u32 val; 3597 3598 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 3599 3600 if (attn & BNX2X_PMF_LINK_ASSERT) { 3601 int func = BP_FUNC(bp); 3602 3603 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3604 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 3605 func_mf_config[BP_ABS_FUNC(bp)].config); 3606 val = SHMEM_RD(bp, 3607 func_mb[BP_FW_MB_IDX(bp)].drv_status); 3608 if (val & DRV_STATUS_DCC_EVENT_MASK) 3609 bnx2x_dcc_event(bp, 3610 (val & DRV_STATUS_DCC_EVENT_MASK)); 3611 3612 if (val & DRV_STATUS_SET_MF_BW) 3613 bnx2x_set_mf_bw(bp); 3614 3615 if (val & DRV_STATUS_DRV_INFO_REQ) 3616 bnx2x_handle_drv_info_req(bp); 3617 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3618 bnx2x_pmf_update(bp); 3619 3620 if (bp->port.pmf && 3621 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 3622 bp->dcbx_enabled > 0) 3623 /* start dcbx state machine */ 3624 bnx2x_dcbx_set_params(bp, 3625 BNX2X_DCBX_STATE_NEG_RECEIVED); 3626 if (bp->link_vars.periodic_flags & 3627 PERIODIC_FLAGS_LINK_EVENT) { 3628 /* sync with link */ 3629 bnx2x_acquire_phy_lock(bp); 3630 bp->link_vars.periodic_flags &= 3631 ~PERIODIC_FLAGS_LINK_EVENT; 3632 bnx2x_release_phy_lock(bp); 3633 if (IS_MF(bp)) 3634 bnx2x_link_sync_notify(bp); 3635 bnx2x_link_report(bp); 3636 } 3637 /* Always call it here: bnx2x_link_report() will 3638 * prevent the link indication duplication. 3639 */ 3640 bnx2x__link_status_update(bp); 3641 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3642 3643 BNX2X_ERR("MC assert!\n"); 3644 bnx2x_mc_assert(bp); 3645 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 3646 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 3647 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 3648 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 3649 bnx2x_panic(); 3650 3651 } else if (attn & BNX2X_MCP_ASSERT) { 3652 3653 BNX2X_ERR("MCP assert!\n"); 3654 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 3655 bnx2x_fw_dump(bp); 3656 3657 } else 3658 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 3659 } 3660 3661 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3662 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3663 if (attn & BNX2X_GRC_TIMEOUT) { 3664 val = CHIP_IS_E1(bp) ? 0 : 3665 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 3666 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3667 } 3668 if (attn & BNX2X_GRC_RSV) { 3669 val = CHIP_IS_E1(bp) ? 0 : 3670 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 3671 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3672 } 3673 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3674 } 3675 } 3676 3677 /* 3678 * Bits map: 3679 * 0-7 - Engine0 load counter. 3680 * 8-15 - Engine1 load counter. 3681 * 16 - Engine0 RESET_IN_PROGRESS bit. 3682 * 17 - Engine1 RESET_IN_PROGRESS bit. 3683 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 3684 * on the engine 3685 * 19 - Engine1 ONE_IS_LOADED. 3686 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 3687 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 3688 * just the one belonging to its engine). 3689 * 3690 */ 3691 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 3692 3693 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 3694 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 3695 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 3696 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 3697 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 3698 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 3699 #define BNX2X_GLOBAL_RESET_BIT 0x00040000 3700 3701 /* 3702 * Set the GLOBAL_RESET bit. 3703 * 3704 * Should be run under rtnl lock 3705 */ 3706 void bnx2x_set_reset_global(struct bnx2x *bp) 3707 { 3708 u32 val; 3709 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3710 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3711 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 3712 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3713 } 3714 3715 /* 3716 * Clear the GLOBAL_RESET bit. 3717 * 3718 * Should be run under rtnl lock 3719 */ 3720 static inline void bnx2x_clear_reset_global(struct bnx2x *bp) 3721 { 3722 u32 val; 3723 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3724 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3725 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 3726 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3727 } 3728 3729 /* 3730 * Checks the GLOBAL_RESET bit. 3731 * 3732 * should be run under rtnl lock 3733 */ 3734 static inline bool bnx2x_reset_is_global(struct bnx2x *bp) 3735 { 3736 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3737 3738 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3739 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 3740 } 3741 3742 /* 3743 * Clear RESET_IN_PROGRESS bit for the current engine. 3744 * 3745 * Should be run under rtnl lock 3746 */ 3747 static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3748 { 3749 u32 val; 3750 u32 bit = BP_PATH(bp) ? 3751 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3752 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3753 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3754 3755 /* Clear the bit */ 3756 val &= ~bit; 3757 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3758 3759 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3760 } 3761 3762 /* 3763 * Set RESET_IN_PROGRESS for the current engine. 3764 * 3765 * should be run under rtnl lock 3766 */ 3767 void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3768 { 3769 u32 val; 3770 u32 bit = BP_PATH(bp) ? 3771 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3772 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3773 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3774 3775 /* Set the bit */ 3776 val |= bit; 3777 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3778 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3779 } 3780 3781 /* 3782 * Checks the RESET_IN_PROGRESS bit for the given engine. 3783 * should be run under rtnl lock 3784 */ 3785 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 3786 { 3787 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3788 u32 bit = engine ? 3789 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 3790 3791 /* return false if bit is set */ 3792 return (val & bit) ? false : true; 3793 } 3794 3795 /* 3796 * set pf load for the current pf. 3797 * 3798 * should be run under rtnl lock 3799 */ 3800 void bnx2x_set_pf_load(struct bnx2x *bp) 3801 { 3802 u32 val1, val; 3803 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3804 BNX2X_PATH0_LOAD_CNT_MASK; 3805 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3806 BNX2X_PATH0_LOAD_CNT_SHIFT; 3807 3808 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3809 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3810 3811 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 3812 3813 /* get the current counter value */ 3814 val1 = (val & mask) >> shift; 3815 3816 /* set bit of that PF */ 3817 val1 |= (1 << bp->pf_num); 3818 3819 /* clear the old value */ 3820 val &= ~mask; 3821 3822 /* set the new one */ 3823 val |= ((val1 << shift) & mask); 3824 3825 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3826 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3827 } 3828 3829 /** 3830 * bnx2x_clear_pf_load - clear pf load mark 3831 * 3832 * @bp: driver handle 3833 * 3834 * Should be run under rtnl lock. 3835 * Decrements the load counter for the current engine. Returns 3836 * whether other functions are still loaded 3837 */ 3838 bool bnx2x_clear_pf_load(struct bnx2x *bp) 3839 { 3840 u32 val1, val; 3841 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3842 BNX2X_PATH0_LOAD_CNT_MASK; 3843 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3844 BNX2X_PATH0_LOAD_CNT_SHIFT; 3845 3846 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3847 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3848 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 3849 3850 /* get the current counter value */ 3851 val1 = (val & mask) >> shift; 3852 3853 /* clear bit of that PF */ 3854 val1 &= ~(1 << bp->pf_num); 3855 3856 /* clear the old value */ 3857 val &= ~mask; 3858 3859 /* set the new one */ 3860 val |= ((val1 << shift) & mask); 3861 3862 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 3863 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3864 return val1 != 0; 3865 } 3866 3867 /* 3868 * Read the load status for the current engine. 3869 * 3870 * should be run under rtnl lock 3871 */ 3872 static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 3873 { 3874 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 3875 BNX2X_PATH0_LOAD_CNT_MASK); 3876 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 3877 BNX2X_PATH0_LOAD_CNT_SHIFT); 3878 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3879 3880 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 3881 3882 val = (val & mask) >> shift; 3883 3884 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 3885 engine, val); 3886 3887 return val != 0; 3888 } 3889 3890 /* 3891 * Reset the load status for the current engine. 3892 */ 3893 static inline void bnx2x_clear_load_status(struct bnx2x *bp) 3894 { 3895 u32 val; 3896 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 3897 BNX2X_PATH0_LOAD_CNT_MASK); 3898 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3899 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3900 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); 3901 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3902 } 3903 3904 static inline void _print_next_block(int idx, const char *blk) 3905 { 3906 pr_cont("%s%s", idx ? ", " : "", blk); 3907 } 3908 3909 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, 3910 bool print) 3911 { 3912 int i = 0; 3913 u32 cur_bit = 0; 3914 for (i = 0; sig; i++) { 3915 cur_bit = ((u32)0x1 << i); 3916 if (sig & cur_bit) { 3917 switch (cur_bit) { 3918 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3919 if (print) 3920 _print_next_block(par_num++, "BRB"); 3921 break; 3922 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3923 if (print) 3924 _print_next_block(par_num++, "PARSER"); 3925 break; 3926 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3927 if (print) 3928 _print_next_block(par_num++, "TSDM"); 3929 break; 3930 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3931 if (print) 3932 _print_next_block(par_num++, 3933 "SEARCHER"); 3934 break; 3935 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 3936 if (print) 3937 _print_next_block(par_num++, "TCM"); 3938 break; 3939 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3940 if (print) 3941 _print_next_block(par_num++, "TSEMI"); 3942 break; 3943 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3944 if (print) 3945 _print_next_block(par_num++, "XPB"); 3946 break; 3947 } 3948 3949 /* Clear the bit */ 3950 sig &= ~cur_bit; 3951 } 3952 } 3953 3954 return par_num; 3955 } 3956 3957 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, 3958 bool *global, bool print) 3959 { 3960 int i = 0; 3961 u32 cur_bit = 0; 3962 for (i = 0; sig; i++) { 3963 cur_bit = ((u32)0x1 << i); 3964 if (sig & cur_bit) { 3965 switch (cur_bit) { 3966 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 3967 if (print) 3968 _print_next_block(par_num++, "PBF"); 3969 break; 3970 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3971 if (print) 3972 _print_next_block(par_num++, "QM"); 3973 break; 3974 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 3975 if (print) 3976 _print_next_block(par_num++, "TM"); 3977 break; 3978 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3979 if (print) 3980 _print_next_block(par_num++, "XSDM"); 3981 break; 3982 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 3983 if (print) 3984 _print_next_block(par_num++, "XCM"); 3985 break; 3986 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3987 if (print) 3988 _print_next_block(par_num++, "XSEMI"); 3989 break; 3990 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3991 if (print) 3992 _print_next_block(par_num++, 3993 "DOORBELLQ"); 3994 break; 3995 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 3996 if (print) 3997 _print_next_block(par_num++, "NIG"); 3998 break; 3999 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4000 if (print) 4001 _print_next_block(par_num++, 4002 "VAUX PCI CORE"); 4003 *global = true; 4004 break; 4005 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4006 if (print) 4007 _print_next_block(par_num++, "DEBUG"); 4008 break; 4009 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4010 if (print) 4011 _print_next_block(par_num++, "USDM"); 4012 break; 4013 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4014 if (print) 4015 _print_next_block(par_num++, "UCM"); 4016 break; 4017 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4018 if (print) 4019 _print_next_block(par_num++, "USEMI"); 4020 break; 4021 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4022 if (print) 4023 _print_next_block(par_num++, "UPB"); 4024 break; 4025 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4026 if (print) 4027 _print_next_block(par_num++, "CSDM"); 4028 break; 4029 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4030 if (print) 4031 _print_next_block(par_num++, "CCM"); 4032 break; 4033 } 4034 4035 /* Clear the bit */ 4036 sig &= ~cur_bit; 4037 } 4038 } 4039 4040 return par_num; 4041 } 4042 4043 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, 4044 bool print) 4045 { 4046 int i = 0; 4047 u32 cur_bit = 0; 4048 for (i = 0; sig; i++) { 4049 cur_bit = ((u32)0x1 << i); 4050 if (sig & cur_bit) { 4051 switch (cur_bit) { 4052 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4053 if (print) 4054 _print_next_block(par_num++, "CSEMI"); 4055 break; 4056 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4057 if (print) 4058 _print_next_block(par_num++, "PXP"); 4059 break; 4060 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4061 if (print) 4062 _print_next_block(par_num++, 4063 "PXPPCICLOCKCLIENT"); 4064 break; 4065 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4066 if (print) 4067 _print_next_block(par_num++, "CFC"); 4068 break; 4069 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4070 if (print) 4071 _print_next_block(par_num++, "CDU"); 4072 break; 4073 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4074 if (print) 4075 _print_next_block(par_num++, "DMAE"); 4076 break; 4077 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4078 if (print) 4079 _print_next_block(par_num++, "IGU"); 4080 break; 4081 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4082 if (print) 4083 _print_next_block(par_num++, "MISC"); 4084 break; 4085 } 4086 4087 /* Clear the bit */ 4088 sig &= ~cur_bit; 4089 } 4090 } 4091 4092 return par_num; 4093 } 4094 4095 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4096 bool *global, bool print) 4097 { 4098 int i = 0; 4099 u32 cur_bit = 0; 4100 for (i = 0; sig; i++) { 4101 cur_bit = ((u32)0x1 << i); 4102 if (sig & cur_bit) { 4103 switch (cur_bit) { 4104 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4105 if (print) 4106 _print_next_block(par_num++, "MCP ROM"); 4107 *global = true; 4108 break; 4109 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4110 if (print) 4111 _print_next_block(par_num++, 4112 "MCP UMP RX"); 4113 *global = true; 4114 break; 4115 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4116 if (print) 4117 _print_next_block(par_num++, 4118 "MCP UMP TX"); 4119 *global = true; 4120 break; 4121 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4122 if (print) 4123 _print_next_block(par_num++, 4124 "MCP SCPAD"); 4125 *global = true; 4126 break; 4127 } 4128 4129 /* Clear the bit */ 4130 sig &= ~cur_bit; 4131 } 4132 } 4133 4134 return par_num; 4135 } 4136 4137 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, 4138 bool print) 4139 { 4140 int i = 0; 4141 u32 cur_bit = 0; 4142 for (i = 0; sig; i++) { 4143 cur_bit = ((u32)0x1 << i); 4144 if (sig & cur_bit) { 4145 switch (cur_bit) { 4146 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4147 if (print) 4148 _print_next_block(par_num++, "PGLUE_B"); 4149 break; 4150 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4151 if (print) 4152 _print_next_block(par_num++, "ATC"); 4153 break; 4154 } 4155 4156 /* Clear the bit */ 4157 sig &= ~cur_bit; 4158 } 4159 } 4160 4161 return par_num; 4162 } 4163 4164 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4165 u32 *sig) 4166 { 4167 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4168 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4169 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4170 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4171 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4172 int par_num = 0; 4173 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4174 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4175 sig[0] & HW_PRTY_ASSERT_SET_0, 4176 sig[1] & HW_PRTY_ASSERT_SET_1, 4177 sig[2] & HW_PRTY_ASSERT_SET_2, 4178 sig[3] & HW_PRTY_ASSERT_SET_3, 4179 sig[4] & HW_PRTY_ASSERT_SET_4); 4180 if (print) 4181 netdev_err(bp->dev, 4182 "Parity errors detected in blocks: "); 4183 par_num = bnx2x_check_blocks_with_parity0( 4184 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4185 par_num = bnx2x_check_blocks_with_parity1( 4186 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4187 par_num = bnx2x_check_blocks_with_parity2( 4188 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4189 par_num = bnx2x_check_blocks_with_parity3( 4190 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4191 par_num = bnx2x_check_blocks_with_parity4( 4192 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4193 4194 if (print) 4195 pr_cont("\n"); 4196 4197 return true; 4198 } else 4199 return false; 4200 } 4201 4202 /** 4203 * bnx2x_chk_parity_attn - checks for parity attentions. 4204 * 4205 * @bp: driver handle 4206 * @global: true if there was a global attention 4207 * @print: show parity attention in syslog 4208 */ 4209 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 4210 { 4211 struct attn_route attn = { {0} }; 4212 int port = BP_PORT(bp); 4213 4214 attn.sig[0] = REG_RD(bp, 4215 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 4216 port*4); 4217 attn.sig[1] = REG_RD(bp, 4218 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 4219 port*4); 4220 attn.sig[2] = REG_RD(bp, 4221 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 4222 port*4); 4223 attn.sig[3] = REG_RD(bp, 4224 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 4225 port*4); 4226 4227 if (!CHIP_IS_E1x(bp)) 4228 attn.sig[4] = REG_RD(bp, 4229 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 4230 port*4); 4231 4232 return bnx2x_parity_attn(bp, global, print, attn.sig); 4233 } 4234 4235 4236 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 4237 { 4238 u32 val; 4239 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 4240 4241 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4242 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4243 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4244 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 4245 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4246 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 4247 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4248 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 4249 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4250 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 4251 if (val & 4252 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4253 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 4254 if (val & 4255 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4256 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 4257 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4258 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 4259 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4260 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 4261 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4262 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 4263 } 4264 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4265 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4266 BNX2X_ERR("ATC hw attention 0x%x\n", val); 4267 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4268 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4269 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4270 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 4271 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4272 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 4273 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4274 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 4275 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4276 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4277 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4278 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 4279 } 4280 4281 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4282 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 4283 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 4284 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4285 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 4286 } 4287 4288 } 4289 4290 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 4291 { 4292 struct attn_route attn, *group_mask; 4293 int port = BP_PORT(bp); 4294 int index; 4295 u32 reg_addr; 4296 u32 val; 4297 u32 aeu_mask; 4298 bool global = false; 4299 4300 /* need to take HW lock because MCP or other port might also 4301 try to handle this event */ 4302 bnx2x_acquire_alr(bp); 4303 4304 if (bnx2x_chk_parity_attn(bp, &global, true)) { 4305 #ifndef BNX2X_STOP_ON_ERROR 4306 bp->recovery_state = BNX2X_RECOVERY_INIT; 4307 schedule_delayed_work(&bp->sp_rtnl_task, 0); 4308 /* Disable HW interrupts */ 4309 bnx2x_int_disable(bp); 4310 /* In case of parity errors don't handle attentions so that 4311 * other function would "see" parity errors. 4312 */ 4313 #else 4314 bnx2x_panic(); 4315 #endif 4316 bnx2x_release_alr(bp); 4317 return; 4318 } 4319 4320 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 4321 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 4322 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 4323 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 4324 if (!CHIP_IS_E1x(bp)) 4325 attn.sig[4] = 4326 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 4327 else 4328 attn.sig[4] = 0; 4329 4330 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 4331 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 4332 4333 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4334 if (deasserted & (1 << index)) { 4335 group_mask = &bp->attn_group[index]; 4336 4337 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 4338 index, 4339 group_mask->sig[0], group_mask->sig[1], 4340 group_mask->sig[2], group_mask->sig[3], 4341 group_mask->sig[4]); 4342 4343 bnx2x_attn_int_deasserted4(bp, 4344 attn.sig[4] & group_mask->sig[4]); 4345 bnx2x_attn_int_deasserted3(bp, 4346 attn.sig[3] & group_mask->sig[3]); 4347 bnx2x_attn_int_deasserted1(bp, 4348 attn.sig[1] & group_mask->sig[1]); 4349 bnx2x_attn_int_deasserted2(bp, 4350 attn.sig[2] & group_mask->sig[2]); 4351 bnx2x_attn_int_deasserted0(bp, 4352 attn.sig[0] & group_mask->sig[0]); 4353 } 4354 } 4355 4356 bnx2x_release_alr(bp); 4357 4358 if (bp->common.int_block == INT_BLOCK_HC) 4359 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4360 COMMAND_REG_ATTN_BITS_CLR); 4361 else 4362 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 4363 4364 val = ~deasserted; 4365 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 4366 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4367 REG_WR(bp, reg_addr, val); 4368 4369 if (~bp->attn_state & deasserted) 4370 BNX2X_ERR("IGU ERROR\n"); 4371 4372 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4373 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4374 4375 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4376 aeu_mask = REG_RD(bp, reg_addr); 4377 4378 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 4379 aeu_mask, deasserted); 4380 aeu_mask |= (deasserted & 0x3ff); 4381 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4382 4383 REG_WR(bp, reg_addr, aeu_mask); 4384 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4385 4386 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4387 bp->attn_state &= ~deasserted; 4388 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4389 } 4390 4391 static void bnx2x_attn_int(struct bnx2x *bp) 4392 { 4393 /* read local copy of bits */ 4394 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 4395 attn_bits); 4396 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 4397 attn_bits_ack); 4398 u32 attn_state = bp->attn_state; 4399 4400 /* look for changed bits */ 4401 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 4402 u32 deasserted = ~attn_bits & attn_ack & attn_state; 4403 4404 DP(NETIF_MSG_HW, 4405 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 4406 attn_bits, attn_ack, asserted, deasserted); 4407 4408 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 4409 BNX2X_ERR("BAD attention state\n"); 4410 4411 /* handle bits that were raised */ 4412 if (asserted) 4413 bnx2x_attn_int_asserted(bp, asserted); 4414 4415 if (deasserted) 4416 bnx2x_attn_int_deasserted(bp, deasserted); 4417 } 4418 4419 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 4420 u16 index, u8 op, u8 update) 4421 { 4422 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 4423 4424 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 4425 igu_addr); 4426 } 4427 4428 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 4429 { 4430 /* No memory barriers */ 4431 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 4432 mmiowb(); /* keep prod updates ordered */ 4433 } 4434 4435 #ifdef BCM_CNIC 4436 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 4437 union event_ring_elem *elem) 4438 { 4439 u8 err = elem->message.error; 4440 4441 if (!bp->cnic_eth_dev.starting_cid || 4442 (cid < bp->cnic_eth_dev.starting_cid && 4443 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 4444 return 1; 4445 4446 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 4447 4448 if (unlikely(err)) { 4449 4450 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 4451 cid); 4452 bnx2x_panic_dump(bp); 4453 } 4454 bnx2x_cnic_cfc_comp(bp, cid, err); 4455 return 0; 4456 } 4457 #endif 4458 4459 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 4460 { 4461 struct bnx2x_mcast_ramrod_params rparam; 4462 int rc; 4463 4464 memset(&rparam, 0, sizeof(rparam)); 4465 4466 rparam.mcast_obj = &bp->mcast_obj; 4467 4468 netif_addr_lock_bh(bp->dev); 4469 4470 /* Clear pending state for the last command */ 4471 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 4472 4473 /* If there are pending mcast commands - send them */ 4474 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 4475 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 4476 if (rc < 0) 4477 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 4478 rc); 4479 } 4480 4481 netif_addr_unlock_bh(bp->dev); 4482 } 4483 4484 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp, 4485 union event_ring_elem *elem) 4486 { 4487 unsigned long ramrod_flags = 0; 4488 int rc = 0; 4489 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; 4490 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 4491 4492 /* Always push next commands out, don't wait here */ 4493 __set_bit(RAMROD_CONT, &ramrod_flags); 4494 4495 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4496 case BNX2X_FILTER_MAC_PENDING: 4497 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 4498 #ifdef BCM_CNIC 4499 if (cid == BNX2X_ISCSI_ETH_CID) 4500 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4501 else 4502 #endif 4503 vlan_mac_obj = &bp->fp[cid].mac_obj; 4504 4505 break; 4506 case BNX2X_FILTER_MCAST_PENDING: 4507 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 4508 /* This is only relevant for 57710 where multicast MACs are 4509 * configured as unicast MACs using the same ramrod. 4510 */ 4511 bnx2x_handle_mcast_eqe(bp); 4512 return; 4513 default: 4514 BNX2X_ERR("Unsupported classification command: %d\n", 4515 elem->message.data.eth_event.echo); 4516 return; 4517 } 4518 4519 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 4520 4521 if (rc < 0) 4522 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 4523 else if (rc > 0) 4524 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 4525 4526 } 4527 4528 #ifdef BCM_CNIC 4529 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 4530 #endif 4531 4532 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 4533 { 4534 netif_addr_lock_bh(bp->dev); 4535 4536 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 4537 4538 /* Send rx_mode command again if was requested */ 4539 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 4540 bnx2x_set_storm_rx_mode(bp); 4541 #ifdef BCM_CNIC 4542 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 4543 &bp->sp_state)) 4544 bnx2x_set_iscsi_eth_rx_mode(bp, true); 4545 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 4546 &bp->sp_state)) 4547 bnx2x_set_iscsi_eth_rx_mode(bp, false); 4548 #endif 4549 4550 netif_addr_unlock_bh(bp->dev); 4551 } 4552 4553 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 4554 struct bnx2x *bp, u32 cid) 4555 { 4556 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 4557 #ifdef BCM_CNIC 4558 if (cid == BNX2X_FCOE_ETH_CID) 4559 return &bnx2x_fcoe(bp, q_obj); 4560 else 4561 #endif 4562 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj); 4563 } 4564 4565 static void bnx2x_eq_int(struct bnx2x *bp) 4566 { 4567 u16 hw_cons, sw_cons, sw_prod; 4568 union event_ring_elem *elem; 4569 u32 cid; 4570 u8 opcode; 4571 int spqe_cnt = 0; 4572 struct bnx2x_queue_sp_obj *q_obj; 4573 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 4574 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 4575 4576 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 4577 4578 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 4579 * when we get the the next-page we nned to adjust so the loop 4580 * condition below will be met. The next element is the size of a 4581 * regular element and hence incrementing by 1 4582 */ 4583 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 4584 hw_cons++; 4585 4586 /* This function may never run in parallel with itself for a 4587 * specific bp, thus there is no need in "paired" read memory 4588 * barrier here. 4589 */ 4590 sw_cons = bp->eq_cons; 4591 sw_prod = bp->eq_prod; 4592 4593 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 4594 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 4595 4596 for (; sw_cons != hw_cons; 4597 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 4598 4599 4600 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 4601 4602 cid = SW_CID(elem->message.data.cfc_del_event.cid); 4603 opcode = elem->message.opcode; 4604 4605 4606 /* handle eq element */ 4607 switch (opcode) { 4608 case EVENT_RING_OPCODE_STAT_QUERY: 4609 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, 4610 "got statistics comp event %d\n", 4611 bp->stats_comp++); 4612 /* nothing to do with stats comp */ 4613 goto next_spqe; 4614 4615 case EVENT_RING_OPCODE_CFC_DEL: 4616 /* handle according to cid range */ 4617 /* 4618 * we may want to verify here that the bp state is 4619 * HALTING 4620 */ 4621 DP(BNX2X_MSG_SP, 4622 "got delete ramrod for MULTI[%d]\n", cid); 4623 #ifdef BCM_CNIC 4624 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 4625 goto next_spqe; 4626 #endif 4627 q_obj = bnx2x_cid_to_q_obj(bp, cid); 4628 4629 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 4630 break; 4631 4632 4633 4634 goto next_spqe; 4635 4636 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4637 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 4638 if (f_obj->complete_cmd(bp, f_obj, 4639 BNX2X_F_CMD_TX_STOP)) 4640 break; 4641 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 4642 goto next_spqe; 4643 4644 case EVENT_RING_OPCODE_START_TRAFFIC: 4645 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 4646 if (f_obj->complete_cmd(bp, f_obj, 4647 BNX2X_F_CMD_TX_START)) 4648 break; 4649 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4650 goto next_spqe; 4651 case EVENT_RING_OPCODE_FUNCTION_START: 4652 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 4653 "got FUNC_START ramrod\n"); 4654 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4655 break; 4656 4657 goto next_spqe; 4658 4659 case EVENT_RING_OPCODE_FUNCTION_STOP: 4660 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 4661 "got FUNC_STOP ramrod\n"); 4662 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4663 break; 4664 4665 goto next_spqe; 4666 } 4667 4668 switch (opcode | bp->state) { 4669 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4670 BNX2X_STATE_OPEN): 4671 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 4672 BNX2X_STATE_OPENING_WAIT4_PORT): 4673 cid = elem->message.data.eth_event.echo & 4674 BNX2X_SWCID_MASK; 4675 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 4676 cid); 4677 rss_raw->clear_pending(rss_raw); 4678 break; 4679 4680 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 4681 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 4682 case (EVENT_RING_OPCODE_SET_MAC | 4683 BNX2X_STATE_CLOSING_WAIT4_HALT): 4684 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4685 BNX2X_STATE_OPEN): 4686 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4687 BNX2X_STATE_DIAG): 4688 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 4689 BNX2X_STATE_CLOSING_WAIT4_HALT): 4690 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); 4691 bnx2x_handle_classification_eqe(bp, elem); 4692 break; 4693 4694 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4695 BNX2X_STATE_OPEN): 4696 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4697 BNX2X_STATE_DIAG): 4698 case (EVENT_RING_OPCODE_MULTICAST_RULES | 4699 BNX2X_STATE_CLOSING_WAIT4_HALT): 4700 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 4701 bnx2x_handle_mcast_eqe(bp); 4702 break; 4703 4704 case (EVENT_RING_OPCODE_FILTERS_RULES | 4705 BNX2X_STATE_OPEN): 4706 case (EVENT_RING_OPCODE_FILTERS_RULES | 4707 BNX2X_STATE_DIAG): 4708 case (EVENT_RING_OPCODE_FILTERS_RULES | 4709 BNX2X_STATE_CLOSING_WAIT4_HALT): 4710 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 4711 bnx2x_handle_rx_mode_eqe(bp); 4712 break; 4713 default: 4714 /* unknown event log error and continue */ 4715 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 4716 elem->message.opcode, bp->state); 4717 } 4718 next_spqe: 4719 spqe_cnt++; 4720 } /* for */ 4721 4722 smp_mb__before_atomic_inc(); 4723 atomic_add(spqe_cnt, &bp->eq_spq_left); 4724 4725 bp->eq_cons = sw_cons; 4726 bp->eq_prod = sw_prod; 4727 /* Make sure that above mem writes were issued towards the memory */ 4728 smp_wmb(); 4729 4730 /* update producer */ 4731 bnx2x_update_eq_prod(bp, bp->eq_prod); 4732 } 4733 4734 static void bnx2x_sp_task(struct work_struct *work) 4735 { 4736 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 4737 u16 status; 4738 4739 status = bnx2x_update_dsb_idx(bp); 4740 /* if (status == 0) */ 4741 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4742 4743 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status); 4744 4745 /* HW attentions */ 4746 if (status & BNX2X_DEF_SB_ATT_IDX) { 4747 bnx2x_attn_int(bp); 4748 status &= ~BNX2X_DEF_SB_ATT_IDX; 4749 } 4750 4751 /* SP events: STAT_QUERY and others */ 4752 if (status & BNX2X_DEF_SB_IDX) { 4753 #ifdef BCM_CNIC 4754 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 4755 4756 if ((!NO_FCOE(bp)) && 4757 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 4758 /* 4759 * Prevent local bottom-halves from running as 4760 * we are going to change the local NAPI list. 4761 */ 4762 local_bh_disable(); 4763 napi_schedule(&bnx2x_fcoe(bp, napi)); 4764 local_bh_enable(); 4765 } 4766 #endif 4767 /* Handle EQ completions */ 4768 bnx2x_eq_int(bp); 4769 4770 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 4771 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 4772 4773 status &= ~BNX2X_DEF_SB_IDX; 4774 } 4775 4776 if (unlikely(status)) 4777 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", 4778 status); 4779 4780 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4781 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 4782 } 4783 4784 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 4785 { 4786 struct net_device *dev = dev_instance; 4787 struct bnx2x *bp = netdev_priv(dev); 4788 4789 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 4790 IGU_INT_DISABLE, 0); 4791 4792 #ifdef BNX2X_STOP_ON_ERROR 4793 if (unlikely(bp->panic)) 4794 return IRQ_HANDLED; 4795 #endif 4796 4797 #ifdef BCM_CNIC 4798 { 4799 struct cnic_ops *c_ops; 4800 4801 rcu_read_lock(); 4802 c_ops = rcu_dereference(bp->cnic_ops); 4803 if (c_ops) 4804 c_ops->cnic_handler(bp->cnic_data, NULL); 4805 rcu_read_unlock(); 4806 } 4807 #endif 4808 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 4809 4810 return IRQ_HANDLED; 4811 } 4812 4813 /* end of slow path */ 4814 4815 4816 void bnx2x_drv_pulse(struct bnx2x *bp) 4817 { 4818 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 4819 bp->fw_drv_pulse_wr_seq); 4820 } 4821 4822 4823 static void bnx2x_timer(unsigned long data) 4824 { 4825 struct bnx2x *bp = (struct bnx2x *) data; 4826 4827 if (!netif_running(bp->dev)) 4828 return; 4829 4830 if (!BP_NOMCP(bp)) { 4831 int mb_idx = BP_FW_MB_IDX(bp); 4832 u32 drv_pulse; 4833 u32 mcp_pulse; 4834 4835 ++bp->fw_drv_pulse_wr_seq; 4836 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 4837 /* TBD - add SYSTEM_TIME */ 4838 drv_pulse = bp->fw_drv_pulse_wr_seq; 4839 bnx2x_drv_pulse(bp); 4840 4841 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 4842 MCP_PULSE_SEQ_MASK); 4843 /* The delta between driver pulse and mcp response 4844 * should be 1 (before mcp response) or 0 (after mcp response) 4845 */ 4846 if ((drv_pulse != mcp_pulse) && 4847 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 4848 /* someone lost a heartbeat... */ 4849 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 4850 drv_pulse, mcp_pulse); 4851 } 4852 } 4853 4854 if (bp->state == BNX2X_STATE_OPEN) 4855 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 4856 4857 mod_timer(&bp->timer, jiffies + bp->current_interval); 4858 } 4859 4860 /* end of Statistics */ 4861 4862 /* nic init */ 4863 4864 /* 4865 * nic init service functions 4866 */ 4867 4868 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 4869 { 4870 u32 i; 4871 if (!(len%4) && !(addr%4)) 4872 for (i = 0; i < len; i += 4) 4873 REG_WR(bp, addr + i, fill); 4874 else 4875 for (i = 0; i < len; i++) 4876 REG_WR8(bp, addr + i, fill); 4877 4878 } 4879 4880 /* helper: writes FP SP data to FW - data_size in dwords */ 4881 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 4882 int fw_sb_id, 4883 u32 *sb_data_p, 4884 u32 data_size) 4885 { 4886 int index; 4887 for (index = 0; index < data_size; index++) 4888 REG_WR(bp, BAR_CSTRORM_INTMEM + 4889 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 4890 sizeof(u32)*index, 4891 *(sb_data_p + index)); 4892 } 4893 4894 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 4895 { 4896 u32 *sb_data_p; 4897 u32 data_size = 0; 4898 struct hc_status_block_data_e2 sb_data_e2; 4899 struct hc_status_block_data_e1x sb_data_e1x; 4900 4901 /* disable the function first */ 4902 if (!CHIP_IS_E1x(bp)) { 4903 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 4904 sb_data_e2.common.state = SB_DISABLED; 4905 sb_data_e2.common.p_func.vf_valid = false; 4906 sb_data_p = (u32 *)&sb_data_e2; 4907 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 4908 } else { 4909 memset(&sb_data_e1x, 0, 4910 sizeof(struct hc_status_block_data_e1x)); 4911 sb_data_e1x.common.state = SB_DISABLED; 4912 sb_data_e1x.common.p_func.vf_valid = false; 4913 sb_data_p = (u32 *)&sb_data_e1x; 4914 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 4915 } 4916 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 4917 4918 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4919 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 4920 CSTORM_STATUS_BLOCK_SIZE); 4921 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4922 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 4923 CSTORM_SYNC_BLOCK_SIZE); 4924 } 4925 4926 /* helper: writes SP SB data to FW */ 4927 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 4928 struct hc_sp_status_block_data *sp_sb_data) 4929 { 4930 int func = BP_FUNC(bp); 4931 int i; 4932 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 4933 REG_WR(bp, BAR_CSTRORM_INTMEM + 4934 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 4935 i*sizeof(u32), 4936 *((u32 *)sp_sb_data + i)); 4937 } 4938 4939 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp) 4940 { 4941 int func = BP_FUNC(bp); 4942 struct hc_sp_status_block_data sp_sb_data; 4943 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 4944 4945 sp_sb_data.state = SB_DISABLED; 4946 sp_sb_data.p_func.vf_valid = false; 4947 4948 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 4949 4950 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4951 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 4952 CSTORM_SP_STATUS_BLOCK_SIZE); 4953 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 4954 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 4955 CSTORM_SP_SYNC_BLOCK_SIZE); 4956 4957 } 4958 4959 4960 static inline 4961 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 4962 int igu_sb_id, int igu_seg_id) 4963 { 4964 hc_sm->igu_sb_id = igu_sb_id; 4965 hc_sm->igu_seg_id = igu_seg_id; 4966 hc_sm->timer_value = 0xFF; 4967 hc_sm->time_to_expire = 0xFFFFFFFF; 4968 } 4969 4970 4971 /* allocates state machine ids. */ 4972 static inline 4973 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 4974 { 4975 /* zero out state machine indices */ 4976 /* rx indices */ 4977 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4978 4979 /* tx indices */ 4980 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 4981 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 4982 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 4983 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 4984 4985 /* map indices */ 4986 /* rx indices */ 4987 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 4988 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4989 4990 /* tx indices */ 4991 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 4992 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4993 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 4994 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4995 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 4996 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4997 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 4998 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 4999 } 5000 5001 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5002 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5003 { 5004 int igu_seg_id; 5005 5006 struct hc_status_block_data_e2 sb_data_e2; 5007 struct hc_status_block_data_e1x sb_data_e1x; 5008 struct hc_status_block_sm *hc_sm_p; 5009 int data_size; 5010 u32 *sb_data_p; 5011 5012 if (CHIP_INT_MODE_IS_BC(bp)) 5013 igu_seg_id = HC_SEG_ACCESS_NORM; 5014 else 5015 igu_seg_id = IGU_SEG_ACCESS_NORM; 5016 5017 bnx2x_zero_fp_sb(bp, fw_sb_id); 5018 5019 if (!CHIP_IS_E1x(bp)) { 5020 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5021 sb_data_e2.common.state = SB_ENABLED; 5022 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5023 sb_data_e2.common.p_func.vf_id = vfid; 5024 sb_data_e2.common.p_func.vf_valid = vf_valid; 5025 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5026 sb_data_e2.common.same_igu_sb_1b = true; 5027 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5028 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5029 hc_sm_p = sb_data_e2.common.state_machine; 5030 sb_data_p = (u32 *)&sb_data_e2; 5031 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5032 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5033 } else { 5034 memset(&sb_data_e1x, 0, 5035 sizeof(struct hc_status_block_data_e1x)); 5036 sb_data_e1x.common.state = SB_ENABLED; 5037 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5038 sb_data_e1x.common.p_func.vf_id = 0xff; 5039 sb_data_e1x.common.p_func.vf_valid = false; 5040 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5041 sb_data_e1x.common.same_igu_sb_1b = true; 5042 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5043 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 5044 hc_sm_p = sb_data_e1x.common.state_machine; 5045 sb_data_p = (u32 *)&sb_data_e1x; 5046 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5047 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 5048 } 5049 5050 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 5051 igu_sb_id, igu_seg_id); 5052 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5053 igu_sb_id, igu_seg_id); 5054 5055 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 5056 5057 /* write indecies to HW */ 5058 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5059 } 5060 5061 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 5062 u16 tx_usec, u16 rx_usec) 5063 { 5064 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 5065 false, rx_usec); 5066 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5067 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 5068 tx_usec); 5069 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5070 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 5071 tx_usec); 5072 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 5073 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 5074 tx_usec); 5075 } 5076 5077 static void bnx2x_init_def_sb(struct bnx2x *bp) 5078 { 5079 struct host_sp_status_block *def_sb = bp->def_status_blk; 5080 dma_addr_t mapping = bp->def_status_blk_mapping; 5081 int igu_sp_sb_index; 5082 int igu_seg_id; 5083 int port = BP_PORT(bp); 5084 int func = BP_FUNC(bp); 5085 int reg_offset, reg_offset_en5; 5086 u64 section; 5087 int index; 5088 struct hc_sp_status_block_data sp_sb_data; 5089 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5090 5091 if (CHIP_INT_MODE_IS_BC(bp)) { 5092 igu_sp_sb_index = DEF_SB_IGU_ID; 5093 igu_seg_id = HC_SEG_ACCESS_DEF; 5094 } else { 5095 igu_sp_sb_index = bp->igu_dsb_id; 5096 igu_seg_id = IGU_SEG_ACCESS_DEF; 5097 } 5098 5099 /* ATTN */ 5100 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5101 atten_status_block); 5102 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 5103 5104 bp->attn_state = 0; 5105 5106 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5107 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5108 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 5109 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 5110 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5111 int sindex; 5112 /* take care of sig[0]..sig[4] */ 5113 for (sindex = 0; sindex < 4; sindex++) 5114 bp->attn_group[index].sig[sindex] = 5115 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 5116 5117 if (!CHIP_IS_E1x(bp)) 5118 /* 5119 * enable5 is separate from the rest of the registers, 5120 * and therefore the address skip is 4 5121 * and not 16 between the different groups 5122 */ 5123 bp->attn_group[index].sig[4] = REG_RD(bp, 5124 reg_offset_en5 + 0x4*index); 5125 else 5126 bp->attn_group[index].sig[4] = 0; 5127 } 5128 5129 if (bp->common.int_block == INT_BLOCK_HC) { 5130 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 5131 HC_REG_ATTN_MSG0_ADDR_L); 5132 5133 REG_WR(bp, reg_offset, U64_LO(section)); 5134 REG_WR(bp, reg_offset + 4, U64_HI(section)); 5135 } else if (!CHIP_IS_E1x(bp)) { 5136 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 5137 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 5138 } 5139 5140 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 5141 sp_sb); 5142 5143 bnx2x_zero_sp_sb(bp); 5144 5145 sp_sb_data.state = SB_ENABLED; 5146 sp_sb_data.host_sb_addr.lo = U64_LO(section); 5147 sp_sb_data.host_sb_addr.hi = U64_HI(section); 5148 sp_sb_data.igu_sb_id = igu_sp_sb_index; 5149 sp_sb_data.igu_seg_id = igu_seg_id; 5150 sp_sb_data.p_func.pf_id = func; 5151 sp_sb_data.p_func.vnic_id = BP_VN(bp); 5152 sp_sb_data.p_func.vf_id = 0xff; 5153 5154 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5155 5156 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 5157 } 5158 5159 void bnx2x_update_coalesce(struct bnx2x *bp) 5160 { 5161 int i; 5162 5163 for_each_eth_queue(bp, i) 5164 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 5165 bp->tx_ticks, bp->rx_ticks); 5166 } 5167 5168 static void bnx2x_init_sp_ring(struct bnx2x *bp) 5169 { 5170 spin_lock_init(&bp->spq_lock); 5171 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 5172 5173 bp->spq_prod_idx = 0; 5174 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 5175 bp->spq_prod_bd = bp->spq; 5176 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 5177 } 5178 5179 static void bnx2x_init_eq_ring(struct bnx2x *bp) 5180 { 5181 int i; 5182 for (i = 1; i <= NUM_EQ_PAGES; i++) { 5183 union event_ring_elem *elem = 5184 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 5185 5186 elem->next_page.addr.hi = 5187 cpu_to_le32(U64_HI(bp->eq_mapping + 5188 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 5189 elem->next_page.addr.lo = 5190 cpu_to_le32(U64_LO(bp->eq_mapping + 5191 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 5192 } 5193 bp->eq_cons = 0; 5194 bp->eq_prod = NUM_EQ_DESC; 5195 bp->eq_cons_sb = BNX2X_EQ_INDEX; 5196 /* we want a warning message before it gets rought... */ 5197 atomic_set(&bp->eq_spq_left, 5198 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 5199 } 5200 5201 5202 /* called with netif_addr_lock_bh() */ 5203 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 5204 unsigned long rx_mode_flags, 5205 unsigned long rx_accept_flags, 5206 unsigned long tx_accept_flags, 5207 unsigned long ramrod_flags) 5208 { 5209 struct bnx2x_rx_mode_ramrod_params ramrod_param; 5210 int rc; 5211 5212 memset(&ramrod_param, 0, sizeof(ramrod_param)); 5213 5214 /* Prepare ramrod parameters */ 5215 ramrod_param.cid = 0; 5216 ramrod_param.cl_id = cl_id; 5217 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 5218 ramrod_param.func_id = BP_FUNC(bp); 5219 5220 ramrod_param.pstate = &bp->sp_state; 5221 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 5222 5223 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 5224 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 5225 5226 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5227 5228 ramrod_param.ramrod_flags = ramrod_flags; 5229 ramrod_param.rx_mode_flags = rx_mode_flags; 5230 5231 ramrod_param.rx_accept_flags = rx_accept_flags; 5232 ramrod_param.tx_accept_flags = tx_accept_flags; 5233 5234 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 5235 if (rc < 0) { 5236 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 5237 return; 5238 } 5239 } 5240 5241 /* called with netif_addr_lock_bh() */ 5242 void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 5243 { 5244 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 5245 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 5246 5247 #ifdef BCM_CNIC 5248 if (!NO_FCOE(bp)) 5249 5250 /* Configure rx_mode of FCoE Queue */ 5251 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 5252 #endif 5253 5254 switch (bp->rx_mode) { 5255 case BNX2X_RX_MODE_NONE: 5256 /* 5257 * 'drop all' supersedes any accept flags that may have been 5258 * passed to the function. 5259 */ 5260 break; 5261 case BNX2X_RX_MODE_NORMAL: 5262 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5263 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); 5264 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5265 5266 /* internal switching mode */ 5267 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5268 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); 5269 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5270 5271 break; 5272 case BNX2X_RX_MODE_ALLMULTI: 5273 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5274 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5275 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5276 5277 /* internal switching mode */ 5278 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5279 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5280 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5281 5282 break; 5283 case BNX2X_RX_MODE_PROMISC: 5284 /* According to deffinition of SI mode, iface in promisc mode 5285 * should receive matched and unmatched (in resolution of port) 5286 * unicast packets. 5287 */ 5288 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); 5289 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); 5290 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); 5291 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); 5292 5293 /* internal switching mode */ 5294 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); 5295 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); 5296 5297 if (IS_MF_SI(bp)) 5298 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); 5299 else 5300 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); 5301 5302 break; 5303 default: 5304 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); 5305 return; 5306 } 5307 5308 if (bp->rx_mode != BNX2X_RX_MODE_NONE) { 5309 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); 5310 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); 5311 } 5312 5313 __set_bit(RAMROD_RX, &ramrod_flags); 5314 __set_bit(RAMROD_TX, &ramrod_flags); 5315 5316 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, 5317 tx_accept_flags, ramrod_flags); 5318 } 5319 5320 static void bnx2x_init_internal_common(struct bnx2x *bp) 5321 { 5322 int i; 5323 5324 if (IS_MF_SI(bp)) 5325 /* 5326 * In switch independent mode, the TSTORM needs to accept 5327 * packets that failed classification, since approximate match 5328 * mac addresses aren't written to NIG LLH 5329 */ 5330 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5331 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); 5332 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ 5333 REG_WR8(bp, BAR_TSTRORM_INTMEM + 5334 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); 5335 5336 /* Zero this manually as its initialization is 5337 currently missing in the initTool */ 5338 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 5339 REG_WR(bp, BAR_USTRORM_INTMEM + 5340 USTORM_AGG_DATA_OFFSET + i * 4, 0); 5341 if (!CHIP_IS_E1x(bp)) { 5342 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 5343 CHIP_INT_MODE_IS_BC(bp) ? 5344 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 5345 } 5346 } 5347 5348 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 5349 { 5350 switch (load_code) { 5351 case FW_MSG_CODE_DRV_LOAD_COMMON: 5352 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 5353 bnx2x_init_internal_common(bp); 5354 /* no break */ 5355 5356 case FW_MSG_CODE_DRV_LOAD_PORT: 5357 /* nothing to do */ 5358 /* no break */ 5359 5360 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5361 /* internal memory per function is 5362 initialized inside bnx2x_pf_init */ 5363 break; 5364 5365 default: 5366 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 5367 break; 5368 } 5369 } 5370 5371 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 5372 { 5373 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT; 5374 } 5375 5376 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 5377 { 5378 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT; 5379 } 5380 5381 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 5382 { 5383 if (CHIP_IS_E1x(fp->bp)) 5384 return BP_L_ID(fp->bp) + fp->index; 5385 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 5386 return bnx2x_fp_igu_sb_id(fp); 5387 } 5388 5389 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 5390 { 5391 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 5392 u8 cos; 5393 unsigned long q_type = 0; 5394 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 5395 fp->rx_queue = fp_idx; 5396 fp->cid = fp_idx; 5397 fp->cl_id = bnx2x_fp_cl_id(fp); 5398 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 5399 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 5400 /* qZone id equals to FW (per path) client id */ 5401 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 5402 5403 /* init shortcut */ 5404 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 5405 5406 /* Setup SB indicies */ 5407 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 5408 5409 /* Configure Queue State object */ 5410 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 5411 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 5412 5413 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 5414 5415 /* init tx data */ 5416 for_each_cos_in_tx_queue(fp, cos) { 5417 bnx2x_init_txdata(bp, &fp->txdata[cos], 5418 CID_COS_TO_TX_ONLY_CID(fp->cid, cos), 5419 FP_COS_TO_TXQ(fp, cos), 5420 BNX2X_TX_SB_INDEX_BASE + cos); 5421 cids[cos] = fp->txdata[cos].cid; 5422 } 5423 5424 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos, 5425 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 5426 bnx2x_sp_mapping(bp, q_rdata), q_type); 5427 5428 /** 5429 * Configure classification DBs: Always enable Tx switching 5430 */ 5431 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5432 5433 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 5434 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5435 fp->igu_sb_id); 5436 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5437 fp->fw_sb_id, fp->igu_sb_id); 5438 5439 bnx2x_update_fpsb_idx(fp); 5440 } 5441 5442 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 5443 { 5444 int i; 5445 5446 for_each_eth_queue(bp, i) 5447 bnx2x_init_eth_fp(bp, i); 5448 #ifdef BCM_CNIC 5449 if (!NO_FCOE(bp)) 5450 bnx2x_init_fcoe_fp(bp); 5451 5452 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 5453 BNX2X_VF_ID_INVALID, false, 5454 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 5455 5456 #endif 5457 5458 /* Initialize MOD_ABS interrupts */ 5459 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 5460 bp->common.shmem_base, bp->common.shmem2_base, 5461 BP_PORT(bp)); 5462 /* ensure status block indices were read */ 5463 rmb(); 5464 5465 bnx2x_init_def_sb(bp); 5466 bnx2x_update_dsb_idx(bp); 5467 bnx2x_init_rx_rings(bp); 5468 bnx2x_init_tx_rings(bp); 5469 bnx2x_init_sp_ring(bp); 5470 bnx2x_init_eq_ring(bp); 5471 bnx2x_init_internal(bp, load_code); 5472 bnx2x_pf_init(bp); 5473 bnx2x_stats_init(bp); 5474 5475 /* flush all before enabling interrupts */ 5476 mb(); 5477 mmiowb(); 5478 5479 bnx2x_int_enable(bp); 5480 5481 /* Check for SPIO5 */ 5482 bnx2x_attn_int_deasserted0(bp, 5483 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 5484 AEU_INPUTS_ATTN_BITS_SPIO5); 5485 } 5486 5487 /* end of nic init */ 5488 5489 /* 5490 * gzip service functions 5491 */ 5492 5493 static int bnx2x_gunzip_init(struct bnx2x *bp) 5494 { 5495 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 5496 &bp->gunzip_mapping, GFP_KERNEL); 5497 if (bp->gunzip_buf == NULL) 5498 goto gunzip_nomem1; 5499 5500 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 5501 if (bp->strm == NULL) 5502 goto gunzip_nomem2; 5503 5504 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 5505 if (bp->strm->workspace == NULL) 5506 goto gunzip_nomem3; 5507 5508 return 0; 5509 5510 gunzip_nomem3: 5511 kfree(bp->strm); 5512 bp->strm = NULL; 5513 5514 gunzip_nomem2: 5515 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5516 bp->gunzip_mapping); 5517 bp->gunzip_buf = NULL; 5518 5519 gunzip_nomem1: 5520 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 5521 return -ENOMEM; 5522 } 5523 5524 static void bnx2x_gunzip_end(struct bnx2x *bp) 5525 { 5526 if (bp->strm) { 5527 vfree(bp->strm->workspace); 5528 kfree(bp->strm); 5529 bp->strm = NULL; 5530 } 5531 5532 if (bp->gunzip_buf) { 5533 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 5534 bp->gunzip_mapping); 5535 bp->gunzip_buf = NULL; 5536 } 5537 } 5538 5539 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 5540 { 5541 int n, rc; 5542 5543 /* check gzip header */ 5544 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 5545 BNX2X_ERR("Bad gzip header\n"); 5546 return -EINVAL; 5547 } 5548 5549 n = 10; 5550 5551 #define FNAME 0x8 5552 5553 if (zbuf[3] & FNAME) 5554 while ((zbuf[n++] != 0) && (n < len)); 5555 5556 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 5557 bp->strm->avail_in = len - n; 5558 bp->strm->next_out = bp->gunzip_buf; 5559 bp->strm->avail_out = FW_BUF_SIZE; 5560 5561 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 5562 if (rc != Z_OK) 5563 return rc; 5564 5565 rc = zlib_inflate(bp->strm, Z_FINISH); 5566 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 5567 netdev_err(bp->dev, "Firmware decompression error: %s\n", 5568 bp->strm->msg); 5569 5570 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5571 if (bp->gunzip_outlen & 0x3) 5572 netdev_err(bp->dev, 5573 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 5574 bp->gunzip_outlen); 5575 bp->gunzip_outlen >>= 2; 5576 5577 zlib_inflateEnd(bp->strm); 5578 5579 if (rc == Z_STREAM_END) 5580 return 0; 5581 5582 return rc; 5583 } 5584 5585 /* nic load/unload */ 5586 5587 /* 5588 * General service functions 5589 */ 5590 5591 /* send a NIG loopback debug packet */ 5592 static void bnx2x_lb_pckt(struct bnx2x *bp) 5593 { 5594 u32 wb_write[3]; 5595 5596 /* Ethernet source and destination addresses */ 5597 wb_write[0] = 0x55555555; 5598 wb_write[1] = 0x55555555; 5599 wb_write[2] = 0x20; /* SOP */ 5600 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5601 5602 /* NON-IP protocol */ 5603 wb_write[0] = 0x09000000; 5604 wb_write[1] = 0x55555555; 5605 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 5606 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 5607 } 5608 5609 /* some of the internal memories 5610 * are not directly readable from the driver 5611 * to test them we send debug packets 5612 */ 5613 static int bnx2x_int_mem_test(struct bnx2x *bp) 5614 { 5615 int factor; 5616 int count, i; 5617 u32 val = 0; 5618 5619 if (CHIP_REV_IS_FPGA(bp)) 5620 factor = 120; 5621 else if (CHIP_REV_IS_EMUL(bp)) 5622 factor = 200; 5623 else 5624 factor = 1; 5625 5626 /* Disable inputs of parser neighbor blocks */ 5627 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5628 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5629 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5630 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5631 5632 /* Write 0 to parser credits for CFC search request */ 5633 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5634 5635 /* send Ethernet packet */ 5636 bnx2x_lb_pckt(bp); 5637 5638 /* TODO do i reset NIG statistic? */ 5639 /* Wait until NIG register shows 1 packet of size 0x10 */ 5640 count = 1000 * factor; 5641 while (count) { 5642 5643 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5644 val = *bnx2x_sp(bp, wb_data[0]); 5645 if (val == 0x10) 5646 break; 5647 5648 msleep(10); 5649 count--; 5650 } 5651 if (val != 0x10) { 5652 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5653 return -1; 5654 } 5655 5656 /* Wait until PRS register shows 1 packet */ 5657 count = 1000 * factor; 5658 while (count) { 5659 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5660 if (val == 1) 5661 break; 5662 5663 msleep(10); 5664 count--; 5665 } 5666 if (val != 0x1) { 5667 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5668 return -2; 5669 } 5670 5671 /* Reset and init BRB, PRS */ 5672 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5673 msleep(50); 5674 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5675 msleep(50); 5676 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5677 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5678 5679 DP(NETIF_MSG_HW, "part2\n"); 5680 5681 /* Disable inputs of parser neighbor blocks */ 5682 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 5683 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 5684 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 5685 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 5686 5687 /* Write 0 to parser credits for CFC search request */ 5688 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 5689 5690 /* send 10 Ethernet packets */ 5691 for (i = 0; i < 10; i++) 5692 bnx2x_lb_pckt(bp); 5693 5694 /* Wait until NIG register shows 10 + 1 5695 packets of size 11*0x10 = 0xb0 */ 5696 count = 1000 * factor; 5697 while (count) { 5698 5699 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5700 val = *bnx2x_sp(bp, wb_data[0]); 5701 if (val == 0xb0) 5702 break; 5703 5704 msleep(10); 5705 count--; 5706 } 5707 if (val != 0xb0) { 5708 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 5709 return -3; 5710 } 5711 5712 /* Wait until PRS register shows 2 packets */ 5713 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5714 if (val != 2) 5715 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5716 5717 /* Write 1 to parser credits for CFC search request */ 5718 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 5719 5720 /* Wait until PRS register shows 3 packets */ 5721 msleep(10 * factor); 5722 /* Wait until NIG register shows 1 packet of size 0x10 */ 5723 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 5724 if (val != 3) 5725 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 5726 5727 /* clear NIG EOP FIFO */ 5728 for (i = 0; i < 11; i++) 5729 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 5730 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 5731 if (val != 1) { 5732 BNX2X_ERR("clear of NIG failed\n"); 5733 return -4; 5734 } 5735 5736 /* Reset and init BRB, PRS, NIG */ 5737 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 5738 msleep(50); 5739 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 5740 msleep(50); 5741 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 5742 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 5743 #ifndef BCM_CNIC 5744 /* set NIC mode */ 5745 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5746 #endif 5747 5748 /* Enable inputs of parser neighbor blocks */ 5749 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 5750 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 5751 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 5752 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 5753 5754 DP(NETIF_MSG_HW, "done\n"); 5755 5756 return 0; /* OK */ 5757 } 5758 5759 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 5760 { 5761 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 5762 if (!CHIP_IS_E1x(bp)) 5763 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 5764 else 5765 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 5766 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5767 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 5768 /* 5769 * mask read length error interrupts in brb for parser 5770 * (parsing unit and 'checksum and crc' unit) 5771 * these errors are legal (PU reads fixed length and CAC can cause 5772 * read length error on truncated packets) 5773 */ 5774 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 5775 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 5776 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 5777 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 5778 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 5779 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 5780 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 5781 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 5782 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 5783 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 5784 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 5785 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 5786 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 5787 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 5788 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 5789 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 5790 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 5791 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 5792 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 5793 5794 if (CHIP_REV_IS_FPGA(bp)) 5795 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 5796 else if (!CHIP_IS_E1x(bp)) 5797 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 5798 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF 5799 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT 5800 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN 5801 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED 5802 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED)); 5803 else 5804 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 5805 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 5806 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 5807 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 5808 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 5809 5810 if (!CHIP_IS_E1x(bp)) 5811 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 5812 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 5813 5814 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 5815 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 5816 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 5817 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 5818 } 5819 5820 static void bnx2x_reset_common(struct bnx2x *bp) 5821 { 5822 u32 val = 0x1400; 5823 5824 /* reset_common */ 5825 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5826 0xd3ffff7f); 5827 5828 if (CHIP_IS_E3(bp)) { 5829 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 5830 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 5831 } 5832 5833 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 5834 } 5835 5836 static void bnx2x_setup_dmae(struct bnx2x *bp) 5837 { 5838 bp->dmae_ready = 0; 5839 spin_lock_init(&bp->dmae_lock); 5840 } 5841 5842 static void bnx2x_init_pxp(struct bnx2x *bp) 5843 { 5844 u16 devctl; 5845 int r_order, w_order; 5846 5847 pci_read_config_word(bp->pdev, 5848 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl); 5849 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 5850 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 5851 if (bp->mrrs == -1) 5852 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 5853 else { 5854 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 5855 r_order = bp->mrrs; 5856 } 5857 5858 bnx2x_init_pxp_arb(bp, r_order, w_order); 5859 } 5860 5861 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 5862 { 5863 int is_required; 5864 u32 val; 5865 int port; 5866 5867 if (BP_NOMCP(bp)) 5868 return; 5869 5870 is_required = 0; 5871 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 5872 SHARED_HW_CFG_FAN_FAILURE_MASK; 5873 5874 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 5875 is_required = 1; 5876 5877 /* 5878 * The fan failure mechanism is usually related to the PHY type since 5879 * the power consumption of the board is affected by the PHY. Currently, 5880 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 5881 */ 5882 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 5883 for (port = PORT_0; port < PORT_MAX; port++) { 5884 is_required |= 5885 bnx2x_fan_failure_det_req( 5886 bp, 5887 bp->common.shmem_base, 5888 bp->common.shmem2_base, 5889 port); 5890 } 5891 5892 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 5893 5894 if (is_required == 0) 5895 return; 5896 5897 /* Fan failure is indicated by SPIO 5 */ 5898 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, 5899 MISC_REGISTERS_SPIO_INPUT_HI_Z); 5900 5901 /* set to active low mode */ 5902 val = REG_RD(bp, MISC_REG_SPIO_INT); 5903 val |= ((1 << MISC_REGISTERS_SPIO_5) << 5904 MISC_REGISTERS_SPIO_INT_OLD_SET_POS); 5905 REG_WR(bp, MISC_REG_SPIO_INT, val); 5906 5907 /* enable interrupt to signal the IGU */ 5908 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 5909 val |= (1 << MISC_REGISTERS_SPIO_5); 5910 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 5911 } 5912 5913 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) 5914 { 5915 u32 offset = 0; 5916 5917 if (CHIP_IS_E1(bp)) 5918 return; 5919 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) 5920 return; 5921 5922 switch (BP_ABS_FUNC(bp)) { 5923 case 0: 5924 offset = PXP2_REG_PGL_PRETEND_FUNC_F0; 5925 break; 5926 case 1: 5927 offset = PXP2_REG_PGL_PRETEND_FUNC_F1; 5928 break; 5929 case 2: 5930 offset = PXP2_REG_PGL_PRETEND_FUNC_F2; 5931 break; 5932 case 3: 5933 offset = PXP2_REG_PGL_PRETEND_FUNC_F3; 5934 break; 5935 case 4: 5936 offset = PXP2_REG_PGL_PRETEND_FUNC_F4; 5937 break; 5938 case 5: 5939 offset = PXP2_REG_PGL_PRETEND_FUNC_F5; 5940 break; 5941 case 6: 5942 offset = PXP2_REG_PGL_PRETEND_FUNC_F6; 5943 break; 5944 case 7: 5945 offset = PXP2_REG_PGL_PRETEND_FUNC_F7; 5946 break; 5947 default: 5948 return; 5949 } 5950 5951 REG_WR(bp, offset, pretend_func_num); 5952 REG_RD(bp, offset); 5953 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5954 } 5955 5956 void bnx2x_pf_disable(struct bnx2x *bp) 5957 { 5958 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5959 val &= ~IGU_PF_CONF_FUNC_EN; 5960 5961 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 5962 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 5963 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 5964 } 5965 5966 static inline void bnx2x__common_init_phy(struct bnx2x *bp) 5967 { 5968 u32 shmem_base[2], shmem2_base[2]; 5969 shmem_base[0] = bp->common.shmem_base; 5970 shmem2_base[0] = bp->common.shmem2_base; 5971 if (!CHIP_IS_E1x(bp)) { 5972 shmem_base[1] = 5973 SHMEM2_RD(bp, other_shmem_base_addr); 5974 shmem2_base[1] = 5975 SHMEM2_RD(bp, other_shmem2_base_addr); 5976 } 5977 bnx2x_acquire_phy_lock(bp); 5978 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 5979 bp->common.chip_id); 5980 bnx2x_release_phy_lock(bp); 5981 } 5982 5983 /** 5984 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 5985 * 5986 * @bp: driver handle 5987 */ 5988 static int bnx2x_init_hw_common(struct bnx2x *bp) 5989 { 5990 u32 val; 5991 5992 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); 5993 5994 /* 5995 * take the UNDI lock to protect undi_unload flow from accessing 5996 * registers while we're resetting the chip 5997 */ 5998 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 5999 6000 bnx2x_reset_common(bp); 6001 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 6002 6003 val = 0xfffc; 6004 if (CHIP_IS_E3(bp)) { 6005 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6006 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6007 } 6008 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 6009 6010 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 6011 6012 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 6013 6014 if (!CHIP_IS_E1x(bp)) { 6015 u8 abs_func_id; 6016 6017 /** 6018 * 4-port mode or 2-port mode we need to turn of master-enable 6019 * for everyone, after that, turn it back on for self. 6020 * so, we disregard multi-function or not, and always disable 6021 * for all functions on the given path, this means 0,2,4,6 for 6022 * path 0 and 1,3,5,7 for path 1 6023 */ 6024 for (abs_func_id = BP_PATH(bp); 6025 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 6026 if (abs_func_id == BP_ABS_FUNC(bp)) { 6027 REG_WR(bp, 6028 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 6029 1); 6030 continue; 6031 } 6032 6033 bnx2x_pretend_func(bp, abs_func_id); 6034 /* clear pf enable */ 6035 bnx2x_pf_disable(bp); 6036 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6037 } 6038 } 6039 6040 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 6041 if (CHIP_IS_E1(bp)) { 6042 /* enable HW interrupt from PXP on USDM overflow 6043 bit 16 on INT_MASK_0 */ 6044 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6045 } 6046 6047 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 6048 bnx2x_init_pxp(bp); 6049 6050 #ifdef __BIG_ENDIAN 6051 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); 6052 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); 6053 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 6054 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 6055 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 6056 /* make sure this value is 0 */ 6057 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 6058 6059 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ 6060 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); 6061 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); 6062 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); 6063 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 6064 #endif 6065 6066 bnx2x_ilt_init_page_size(bp, INITOP_SET); 6067 6068 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 6069 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 6070 6071 /* let the HW do it's magic ... */ 6072 msleep(100); 6073 /* finish PXP init */ 6074 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 6075 if (val != 1) { 6076 BNX2X_ERR("PXP2 CFG failed\n"); 6077 return -EBUSY; 6078 } 6079 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 6080 if (val != 1) { 6081 BNX2X_ERR("PXP2 RD_INIT failed\n"); 6082 return -EBUSY; 6083 } 6084 6085 /* Timers bug workaround E2 only. We need to set the entire ILT to 6086 * have entries with value "0" and valid bit on. 6087 * This needs to be done by the first PF that is loaded in a path 6088 * (i.e. common phase) 6089 */ 6090 if (!CHIP_IS_E1x(bp)) { 6091 /* In E2 there is a bug in the timers block that can cause function 6 / 7 6092 * (i.e. vnic3) to start even if it is marked as "scan-off". 6093 * This occurs when a different function (func2,3) is being marked 6094 * as "scan-off". Real-life scenario for example: if a driver is being 6095 * load-unloaded while func6,7 are down. This will cause the timer to access 6096 * the ilt, translate to a logical address and send a request to read/write. 6097 * Since the ilt for the function that is down is not valid, this will cause 6098 * a translation error which is unrecoverable. 6099 * The Workaround is intended to make sure that when this happens nothing fatal 6100 * will occur. The workaround: 6101 * 1. First PF driver which loads on a path will: 6102 * a. After taking the chip out of reset, by using pretend, 6103 * it will write "0" to the following registers of 6104 * the other vnics. 6105 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6106 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 6107 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 6108 * And for itself it will write '1' to 6109 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 6110 * dmae-operations (writing to pram for example.) 6111 * note: can be done for only function 6,7 but cleaner this 6112 * way. 6113 * b. Write zero+valid to the entire ILT. 6114 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 6115 * VNIC3 (of that port). The range allocated will be the 6116 * entire ILT. This is needed to prevent ILT range error. 6117 * 2. Any PF driver load flow: 6118 * a. ILT update with the physical addresses of the allocated 6119 * logical pages. 6120 * b. Wait 20msec. - note that this timeout is needed to make 6121 * sure there are no requests in one of the PXP internal 6122 * queues with "old" ILT addresses. 6123 * c. PF enable in the PGLC. 6124 * d. Clear the was_error of the PF in the PGLC. (could have 6125 * occured while driver was down) 6126 * e. PF enable in the CFC (WEAK + STRONG) 6127 * f. Timers scan enable 6128 * 3. PF driver unload flow: 6129 * a. Clear the Timers scan_en. 6130 * b. Polling for scan_on=0 for that PF. 6131 * c. Clear the PF enable bit in the PXP. 6132 * d. Clear the PF enable in the CFC (WEAK + STRONG) 6133 * e. Write zero+valid to all ILT entries (The valid bit must 6134 * stay set) 6135 * f. If this is VNIC 3 of a port then also init 6136 * first_timers_ilt_entry to zero and last_timers_ilt_entry 6137 * to the last enrty in the ILT. 6138 * 6139 * Notes: 6140 * Currently the PF error in the PGLC is non recoverable. 6141 * In the future the there will be a recovery routine for this error. 6142 * Currently attention is masked. 6143 * Having an MCP lock on the load/unload process does not guarantee that 6144 * there is no Timer disable during Func6/7 enable. This is because the 6145 * Timers scan is currently being cleared by the MCP on FLR. 6146 * Step 2.d can be done only for PF6/7 and the driver can also check if 6147 * there is error before clearing it. But the flow above is simpler and 6148 * more general. 6149 * All ILT entries are written by zero+valid and not just PF6/7 6150 * ILT entries since in the future the ILT entries allocation for 6151 * PF-s might be dynamic. 6152 */ 6153 struct ilt_client_info ilt_cli; 6154 struct bnx2x_ilt ilt; 6155 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 6156 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 6157 6158 /* initialize dummy TM client */ 6159 ilt_cli.start = 0; 6160 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 6161 ilt_cli.client_num = ILT_CLIENT_TM; 6162 6163 /* Step 1: set zeroes to all ilt page entries with valid bit on 6164 * Step 2: set the timers first/last ilt entry to point 6165 * to the entire range to prevent ILT range error for 3rd/4th 6166 * vnic (this code assumes existance of the vnic) 6167 * 6168 * both steps performed by call to bnx2x_ilt_client_init_op() 6169 * with dummy TM client 6170 * 6171 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 6172 * and his brother are split registers 6173 */ 6174 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 6175 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 6176 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 6177 6178 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 6179 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 6180 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 6181 } 6182 6183 6184 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 6185 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 6186 6187 if (!CHIP_IS_E1x(bp)) { 6188 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 6189 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 6190 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 6191 6192 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 6193 6194 /* let the HW do it's magic ... */ 6195 do { 6196 msleep(200); 6197 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 6198 } while (factor-- && (val != 1)); 6199 6200 if (val != 1) { 6201 BNX2X_ERR("ATC_INIT failed\n"); 6202 return -EBUSY; 6203 } 6204 } 6205 6206 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 6207 6208 /* clean the DMAE memory */ 6209 bp->dmae_ready = 1; 6210 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 6211 6212 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 6213 6214 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 6215 6216 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 6217 6218 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 6219 6220 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 6221 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 6222 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 6223 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 6224 6225 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 6226 6227 6228 /* QM queues pointers table */ 6229 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 6230 6231 /* soft reset pulse */ 6232 REG_WR(bp, QM_REG_SOFT_RESET, 1); 6233 REG_WR(bp, QM_REG_SOFT_RESET, 0); 6234 6235 #ifdef BCM_CNIC 6236 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 6237 #endif 6238 6239 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 6240 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); 6241 if (!CHIP_REV_IS_SLOW(bp)) 6242 /* enable hw interrupt from doorbell Q */ 6243 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6244 6245 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6246 6247 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6248 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 6249 6250 if (!CHIP_IS_E1(bp)) 6251 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 6252 6253 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) 6254 /* Bit-map indicating which L2 hdrs may appear 6255 * after the basic Ethernet header 6256 */ 6257 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 6258 bp->path_has_ovlan ? 7 : 6); 6259 6260 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 6261 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 6262 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 6263 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 6264 6265 if (!CHIP_IS_E1x(bp)) { 6266 /* reset VFC memories */ 6267 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6268 VFC_MEMORIES_RST_REG_CAM_RST | 6269 VFC_MEMORIES_RST_REG_RAM_RST); 6270 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 6271 VFC_MEMORIES_RST_REG_CAM_RST | 6272 VFC_MEMORIES_RST_REG_RAM_RST); 6273 6274 msleep(20); 6275 } 6276 6277 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 6278 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 6279 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 6280 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 6281 6282 /* sync semi rtc */ 6283 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6284 0x80000000); 6285 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 6286 0x80000000); 6287 6288 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 6289 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 6290 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 6291 6292 if (!CHIP_IS_E1x(bp)) 6293 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 6294 bp->path_has_ovlan ? 7 : 6); 6295 6296 REG_WR(bp, SRC_REG_SOFT_RST, 1); 6297 6298 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 6299 6300 #ifdef BCM_CNIC 6301 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 6302 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 6303 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 6304 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 6305 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 6306 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 6307 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 6308 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 6309 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 6310 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 6311 #endif 6312 REG_WR(bp, SRC_REG_SOFT_RST, 0); 6313 6314 if (sizeof(union cdu_context) != 1024) 6315 /* we currently assume that a context is 1024 bytes */ 6316 dev_alert(&bp->pdev->dev, 6317 "please adjust the size of cdu_context(%ld)\n", 6318 (long)sizeof(union cdu_context)); 6319 6320 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6321 val = (4 << 24) + (0 << 12) + 1024; 6322 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 6323 6324 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 6325 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 6326 /* enable context validation interrupt from CFC */ 6327 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6328 6329 /* set the thresholds to prevent CFC/CDU race */ 6330 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 6331 6332 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 6333 6334 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 6335 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 6336 6337 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 6338 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 6339 6340 /* Reset PCIE errors for debug */ 6341 REG_WR(bp, 0x2814, 0xffffffff); 6342 REG_WR(bp, 0x3820, 0xffffffff); 6343 6344 if (!CHIP_IS_E1x(bp)) { 6345 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 6346 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 6347 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 6348 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 6349 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 6350 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 6351 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 6352 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 6353 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 6354 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 6355 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 6356 } 6357 6358 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 6359 if (!CHIP_IS_E1(bp)) { 6360 /* in E3 this done in per-port section */ 6361 if (!CHIP_IS_E3(bp)) 6362 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6363 } 6364 if (CHIP_IS_E1H(bp)) 6365 /* not applicable for E2 (and above ...) */ 6366 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 6367 6368 if (CHIP_REV_IS_SLOW(bp)) 6369 msleep(200); 6370 6371 /* finish CFC init */ 6372 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 6373 if (val != 1) { 6374 BNX2X_ERR("CFC LL_INIT failed\n"); 6375 return -EBUSY; 6376 } 6377 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 6378 if (val != 1) { 6379 BNX2X_ERR("CFC AC_INIT failed\n"); 6380 return -EBUSY; 6381 } 6382 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 6383 if (val != 1) { 6384 BNX2X_ERR("CFC CAM_INIT failed\n"); 6385 return -EBUSY; 6386 } 6387 REG_WR(bp, CFC_REG_DEBUG0, 0); 6388 6389 if (CHIP_IS_E1(bp)) { 6390 /* read NIG statistic 6391 to see if this is our first up since powerup */ 6392 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6393 val = *bnx2x_sp(bp, wb_data[0]); 6394 6395 /* do internal memory self test */ 6396 if ((val == 0) && bnx2x_int_mem_test(bp)) { 6397 BNX2X_ERR("internal mem self test failed\n"); 6398 return -EBUSY; 6399 } 6400 } 6401 6402 bnx2x_setup_fan_failure_detection(bp); 6403 6404 /* clear PXP2 attentions */ 6405 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 6406 6407 bnx2x_enable_blocks_attention(bp); 6408 bnx2x_enable_blocks_parity(bp); 6409 6410 if (!BP_NOMCP(bp)) { 6411 if (CHIP_IS_E1x(bp)) 6412 bnx2x__common_init_phy(bp); 6413 } else 6414 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 6415 6416 return 0; 6417 } 6418 6419 /** 6420 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 6421 * 6422 * @bp: driver handle 6423 */ 6424 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 6425 { 6426 int rc = bnx2x_init_hw_common(bp); 6427 6428 if (rc) 6429 return rc; 6430 6431 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 6432 if (!BP_NOMCP(bp)) 6433 bnx2x__common_init_phy(bp); 6434 6435 return 0; 6436 } 6437 6438 static int bnx2x_init_hw_port(struct bnx2x *bp) 6439 { 6440 int port = BP_PORT(bp); 6441 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 6442 u32 low, high; 6443 u32 val; 6444 6445 bnx2x__link_reset(bp); 6446 6447 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 6448 6449 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6450 6451 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6452 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6453 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6454 6455 /* Timers bug workaround: disables the pf_master bit in pglue at 6456 * common phase, we need to enable it here before any dmae access are 6457 * attempted. Therefore we manually added the enable-master to the 6458 * port phase (it also happens in the function phase) 6459 */ 6460 if (!CHIP_IS_E1x(bp)) 6461 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6462 6463 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6464 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6465 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6466 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6467 6468 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6469 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6470 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6471 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6472 6473 /* QM cid (connection) count */ 6474 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 6475 6476 #ifdef BCM_CNIC 6477 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6478 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 6479 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 6480 #endif 6481 6482 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6483 6484 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 6485 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6486 6487 if (IS_MF(bp)) 6488 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 6489 else if (bp->dev->mtu > 4096) { 6490 if (bp->flags & ONE_PORT_FLAG) 6491 low = 160; 6492 else { 6493 val = bp->dev->mtu; 6494 /* (24*1024 + val*4)/256 */ 6495 low = 96 + (val/64) + 6496 ((val % 64) ? 1 : 0); 6497 } 6498 } else 6499 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 6500 high = low + 56; /* 14*1024/256 */ 6501 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 6502 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 6503 } 6504 6505 if (CHIP_MODE_IS_4_PORT(bp)) 6506 REG_WR(bp, (BP_PORT(bp) ? 6507 BRB1_REG_MAC_GUARANTIED_1 : 6508 BRB1_REG_MAC_GUARANTIED_0), 40); 6509 6510 6511 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6512 if (CHIP_IS_E3B0(bp)) 6513 /* Ovlan exists only if we are in multi-function + 6514 * switch-dependent mode, in switch-independent there 6515 * is no ovlan headers 6516 */ 6517 REG_WR(bp, BP_PORT(bp) ? 6518 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 6519 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 6520 (bp->path_has_ovlan ? 7 : 6)); 6521 6522 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6523 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6524 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6525 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6526 6527 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6528 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6529 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6530 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6531 6532 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6533 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6534 6535 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6536 6537 if (CHIP_IS_E1x(bp)) { 6538 /* configure PBF to work without PAUSE mtu 9000 */ 6539 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 6540 6541 /* update threshold */ 6542 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 6543 /* update init credit */ 6544 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 6545 6546 /* probe changes */ 6547 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 6548 udelay(50); 6549 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 6550 } 6551 6552 #ifdef BCM_CNIC 6553 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6554 #endif 6555 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6556 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6557 6558 if (CHIP_IS_E1(bp)) { 6559 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6560 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6561 } 6562 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6563 6564 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6565 6566 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6567 /* init aeu_mask_attn_func_0/1: 6568 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 6569 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 6570 * bits 4-7 are used for "per vn group attention" */ 6571 val = IS_MF(bp) ? 0xF7 : 0x7; 6572 /* Enable DCBX attention for all but E1 */ 6573 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 6574 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 6575 6576 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6577 6578 if (!CHIP_IS_E1x(bp)) { 6579 /* Bit-map indicating which L2 hdrs may appear after the 6580 * basic Ethernet header 6581 */ 6582 REG_WR(bp, BP_PORT(bp) ? 6583 NIG_REG_P1_HDRS_AFTER_BASIC : 6584 NIG_REG_P0_HDRS_AFTER_BASIC, 6585 IS_MF_SD(bp) ? 7 : 6); 6586 6587 if (CHIP_IS_E3(bp)) 6588 REG_WR(bp, BP_PORT(bp) ? 6589 NIG_REG_LLH1_MF_MODE : 6590 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 6591 } 6592 if (!CHIP_IS_E3(bp)) 6593 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 6594 6595 if (!CHIP_IS_E1(bp)) { 6596 /* 0x2 disable mf_ov, 0x1 enable */ 6597 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 6598 (IS_MF_SD(bp) ? 0x1 : 0x2)); 6599 6600 if (!CHIP_IS_E1x(bp)) { 6601 val = 0; 6602 switch (bp->mf_mode) { 6603 case MULTI_FUNCTION_SD: 6604 val = 1; 6605 break; 6606 case MULTI_FUNCTION_SI: 6607 val = 2; 6608 break; 6609 } 6610 6611 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 6612 NIG_REG_LLH0_CLS_TYPE), val); 6613 } 6614 { 6615 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 6616 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 6617 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 6618 } 6619 } 6620 6621 6622 /* If SPIO5 is set to generate interrupts, enable it for this port */ 6623 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6624 if (val & (1 << MISC_REGISTERS_SPIO_5)) { 6625 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6626 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6627 val = REG_RD(bp, reg_addr); 6628 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 6629 REG_WR(bp, reg_addr, val); 6630 } 6631 6632 return 0; 6633 } 6634 6635 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 6636 { 6637 int reg; 6638 6639 if (CHIP_IS_E1(bp)) 6640 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 6641 else 6642 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 6643 6644 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 6645 } 6646 6647 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 6648 { 6649 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 6650 } 6651 6652 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 6653 { 6654 u32 i, base = FUNC_ILT_BASE(func); 6655 for (i = base; i < base + ILT_PER_FUNC; i++) 6656 bnx2x_ilt_wr(bp, i, 0); 6657 } 6658 6659 static int bnx2x_init_hw_func(struct bnx2x *bp) 6660 { 6661 int port = BP_PORT(bp); 6662 int func = BP_FUNC(bp); 6663 int init_phase = PHASE_PF0 + func; 6664 struct bnx2x_ilt *ilt = BP_ILT(bp); 6665 u16 cdu_ilt_start; 6666 u32 addr, val; 6667 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6668 int i, main_mem_width, rc; 6669 6670 DP(NETIF_MSG_HW, "starting func init func %d\n", func); 6671 6672 /* FLR cleanup - hmmm */ 6673 if (!CHIP_IS_E1x(bp)) { 6674 rc = bnx2x_pf_flr_clnup(bp); 6675 if (rc) 6676 return rc; 6677 } 6678 6679 /* set MSI reconfigure capability */ 6680 if (bp->common.int_block == INT_BLOCK_HC) { 6681 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 6682 val = REG_RD(bp, addr); 6683 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 6684 REG_WR(bp, addr, val); 6685 } 6686 6687 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 6688 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 6689 6690 ilt = BP_ILT(bp); 6691 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 6692 6693 for (i = 0; i < L2_ILT_LINES(bp); i++) { 6694 ilt->lines[cdu_ilt_start + i].page = 6695 bp->context.vcxt + (ILT_PAGE_CIDS * i); 6696 ilt->lines[cdu_ilt_start + i].page_mapping = 6697 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i); 6698 /* cdu ilt pages are allocated manually so there's no need to 6699 set the size */ 6700 } 6701 bnx2x_ilt_init_op(bp, INITOP_SET); 6702 6703 #ifdef BCM_CNIC 6704 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 6705 6706 /* T1 hash bits value determines the T1 number of entries */ 6707 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 6708 #endif 6709 6710 #ifndef BCM_CNIC 6711 /* set NIC mode */ 6712 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6713 #endif /* BCM_CNIC */ 6714 6715 if (!CHIP_IS_E1x(bp)) { 6716 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 6717 6718 /* Turn on a single ISR mode in IGU if driver is going to use 6719 * INT#x or MSI 6720 */ 6721 if (!(bp->flags & USING_MSIX_FLAG)) 6722 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 6723 /* 6724 * Timers workaround bug: function init part. 6725 * Need to wait 20msec after initializing ILT, 6726 * needed to make sure there are no requests in 6727 * one of the PXP internal queues with "old" ILT addresses 6728 */ 6729 msleep(20); 6730 /* 6731 * Master enable - Due to WB DMAE writes performed before this 6732 * register is re-initialized as part of the regular function 6733 * init 6734 */ 6735 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 6736 /* Enable the function in IGU */ 6737 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 6738 } 6739 6740 bp->dmae_ready = 1; 6741 6742 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 6743 6744 if (!CHIP_IS_E1x(bp)) 6745 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 6746 6747 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 6748 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 6749 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 6750 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 6751 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 6752 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 6753 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 6754 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 6755 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 6756 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 6757 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 6758 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 6759 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 6760 6761 if (!CHIP_IS_E1x(bp)) 6762 REG_WR(bp, QM_REG_PF_EN, 1); 6763 6764 if (!CHIP_IS_E1x(bp)) { 6765 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6766 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6767 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6768 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 6769 } 6770 bnx2x_init_block(bp, BLOCK_QM, init_phase); 6771 6772 bnx2x_init_block(bp, BLOCK_TM, init_phase); 6773 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 6774 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 6775 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 6776 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 6777 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 6778 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 6779 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 6780 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 6781 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 6782 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 6783 if (!CHIP_IS_E1x(bp)) 6784 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 6785 6786 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 6787 6788 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 6789 6790 if (!CHIP_IS_E1x(bp)) 6791 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 6792 6793 if (IS_MF(bp)) { 6794 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 6795 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); 6796 } 6797 6798 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 6799 6800 /* HC init per function */ 6801 if (bp->common.int_block == INT_BLOCK_HC) { 6802 if (CHIP_IS_E1H(bp)) { 6803 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6804 6805 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6806 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6807 } 6808 bnx2x_init_block(bp, BLOCK_HC, init_phase); 6809 6810 } else { 6811 int num_segs, sb_idx, prod_offset; 6812 6813 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 6814 6815 if (!CHIP_IS_E1x(bp)) { 6816 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 6817 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 6818 } 6819 6820 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 6821 6822 if (!CHIP_IS_E1x(bp)) { 6823 int dsb_idx = 0; 6824 /** 6825 * Producer memory: 6826 * E2 mode: address 0-135 match to the mapping memory; 6827 * 136 - PF0 default prod; 137 - PF1 default prod; 6828 * 138 - PF2 default prod; 139 - PF3 default prod; 6829 * 140 - PF0 attn prod; 141 - PF1 attn prod; 6830 * 142 - PF2 attn prod; 143 - PF3 attn prod; 6831 * 144-147 reserved. 6832 * 6833 * E1.5 mode - In backward compatible mode; 6834 * for non default SB; each even line in the memory 6835 * holds the U producer and each odd line hold 6836 * the C producer. The first 128 producers are for 6837 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 6838 * producers are for the DSB for each PF. 6839 * Each PF has five segments: (the order inside each 6840 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 6841 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 6842 * 144-147 attn prods; 6843 */ 6844 /* non-default-status-blocks */ 6845 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6846 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 6847 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 6848 prod_offset = (bp->igu_base_sb + sb_idx) * 6849 num_segs; 6850 6851 for (i = 0; i < num_segs; i++) { 6852 addr = IGU_REG_PROD_CONS_MEMORY + 6853 (prod_offset + i) * 4; 6854 REG_WR(bp, addr, 0); 6855 } 6856 /* send consumer update with value 0 */ 6857 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 6858 USTORM_ID, 0, IGU_INT_NOP, 1); 6859 bnx2x_igu_clear_sb(bp, 6860 bp->igu_base_sb + sb_idx); 6861 } 6862 6863 /* default-status-blocks */ 6864 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 6865 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 6866 6867 if (CHIP_MODE_IS_4_PORT(bp)) 6868 dsb_idx = BP_FUNC(bp); 6869 else 6870 dsb_idx = BP_VN(bp); 6871 6872 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6873 IGU_BC_BASE_DSB_PROD + dsb_idx : 6874 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6875 6876 /* 6877 * igu prods come in chunks of E1HVN_MAX (4) - 6878 * does not matters what is the current chip mode 6879 */ 6880 for (i = 0; i < (num_segs * E1HVN_MAX); 6881 i += E1HVN_MAX) { 6882 addr = IGU_REG_PROD_CONS_MEMORY + 6883 (prod_offset + i)*4; 6884 REG_WR(bp, addr, 0); 6885 } 6886 /* send consumer update with 0 */ 6887 if (CHIP_INT_MODE_IS_BC(bp)) { 6888 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6889 USTORM_ID, 0, IGU_INT_NOP, 1); 6890 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6891 CSTORM_ID, 0, IGU_INT_NOP, 1); 6892 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6893 XSTORM_ID, 0, IGU_INT_NOP, 1); 6894 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6895 TSTORM_ID, 0, IGU_INT_NOP, 1); 6896 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6897 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6898 } else { 6899 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6900 USTORM_ID, 0, IGU_INT_NOP, 1); 6901 bnx2x_ack_sb(bp, bp->igu_dsb_id, 6902 ATTENTION_ID, 0, IGU_INT_NOP, 1); 6903 } 6904 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 6905 6906 /* !!! these should become driver const once 6907 rf-tool supports split-68 const */ 6908 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 6909 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 6910 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 6911 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 6912 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 6913 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 6914 } 6915 } 6916 6917 /* Reset PCIE errors for debug */ 6918 REG_WR(bp, 0x2114, 0xffffffff); 6919 REG_WR(bp, 0x2120, 0xffffffff); 6920 6921 if (CHIP_IS_E1x(bp)) { 6922 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 6923 main_mem_base = HC_REG_MAIN_MEMORY + 6924 BP_PORT(bp) * (main_mem_size * 4); 6925 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 6926 main_mem_width = 8; 6927 6928 val = REG_RD(bp, main_mem_prty_clr); 6929 if (val) 6930 DP(NETIF_MSG_HW, 6931 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", 6932 val); 6933 6934 /* Clear "false" parity errors in MSI-X table */ 6935 for (i = main_mem_base; 6936 i < main_mem_base + main_mem_size * 4; 6937 i += main_mem_width) { 6938 bnx2x_read_dmae(bp, i, main_mem_width / 4); 6939 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 6940 i, main_mem_width / 4); 6941 } 6942 /* Clear HC parity attention */ 6943 REG_RD(bp, main_mem_prty_clr); 6944 } 6945 6946 #ifdef BNX2X_STOP_ON_ERROR 6947 /* Enable STORMs SP logging */ 6948 REG_WR8(bp, BAR_USTRORM_INTMEM + 6949 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6950 REG_WR8(bp, BAR_TSTRORM_INTMEM + 6951 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6952 REG_WR8(bp, BAR_CSTRORM_INTMEM + 6953 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6954 REG_WR8(bp, BAR_XSTRORM_INTMEM + 6955 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 6956 #endif 6957 6958 bnx2x_phy_probe(&bp->link_params); 6959 6960 return 0; 6961 } 6962 6963 6964 void bnx2x_free_mem(struct bnx2x *bp) 6965 { 6966 /* fastpath */ 6967 bnx2x_free_fp_mem(bp); 6968 /* end of fastpath */ 6969 6970 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 6971 sizeof(struct host_sp_status_block)); 6972 6973 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 6974 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 6975 6976 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 6977 sizeof(struct bnx2x_slowpath)); 6978 6979 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping, 6980 bp->context.size); 6981 6982 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 6983 6984 BNX2X_FREE(bp->ilt->lines); 6985 6986 #ifdef BCM_CNIC 6987 if (!CHIP_IS_E1x(bp)) 6988 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 6989 sizeof(struct host_hc_status_block_e2)); 6990 else 6991 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 6992 sizeof(struct host_hc_status_block_e1x)); 6993 6994 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 6995 #endif 6996 6997 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 6998 6999 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 7000 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7001 } 7002 7003 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) 7004 { 7005 int num_groups; 7006 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; 7007 7008 /* number of queues for statistics is number of eth queues + FCoE */ 7009 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; 7010 7011 /* Total number of FW statistics requests = 7012 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + 7013 * num of queues 7014 */ 7015 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; 7016 7017 7018 /* Request is built from stats_query_header and an array of 7019 * stats_query_cmd_group each of which contains 7020 * STATS_QUERY_CMD_COUNT rules. The real number or requests is 7021 * configured in the stats_query_header. 7022 */ 7023 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + 7024 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); 7025 7026 bp->fw_stats_req_sz = sizeof(struct stats_query_header) + 7027 num_groups * sizeof(struct stats_query_cmd_group); 7028 7029 /* Data for statistics requests + stats_conter 7030 * 7031 * stats_counter holds per-STORM counters that are incremented 7032 * when STORM has finished with the current request. 7033 * 7034 * memory for FCoE offloaded statistics are counted anyway, 7035 * even if they will not be sent. 7036 */ 7037 bp->fw_stats_data_sz = sizeof(struct per_port_stats) + 7038 sizeof(struct per_pf_stats) + 7039 sizeof(struct fcoe_statistics_params) + 7040 sizeof(struct per_queue_stats) * num_queue_stats + 7041 sizeof(struct stats_counter); 7042 7043 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, 7044 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7045 7046 /* Set shortcuts */ 7047 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; 7048 bp->fw_stats_req_mapping = bp->fw_stats_mapping; 7049 7050 bp->fw_stats_data = (struct bnx2x_fw_stats_data *) 7051 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); 7052 7053 bp->fw_stats_data_mapping = bp->fw_stats_mapping + 7054 bp->fw_stats_req_sz; 7055 return 0; 7056 7057 alloc_mem_err: 7058 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7059 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7060 BNX2X_ERR("Can't allocate memory\n"); 7061 return -ENOMEM; 7062 } 7063 7064 7065 int bnx2x_alloc_mem(struct bnx2x *bp) 7066 { 7067 #ifdef BCM_CNIC 7068 if (!CHIP_IS_E1x(bp)) 7069 /* size = the status block + ramrod buffers */ 7070 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, 7071 sizeof(struct host_hc_status_block_e2)); 7072 else 7073 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping, 7074 sizeof(struct host_hc_status_block_e1x)); 7075 7076 /* allocate searcher T2 table */ 7077 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); 7078 #endif 7079 7080 7081 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 7082 sizeof(struct host_sp_status_block)); 7083 7084 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 7085 sizeof(struct bnx2x_slowpath)); 7086 7087 #ifdef BCM_CNIC 7088 /* write address to which L5 should insert its values */ 7089 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp; 7090 #endif 7091 7092 /* Allocated memory for FW statistics */ 7093 if (bnx2x_alloc_fw_stats_mem(bp)) 7094 goto alloc_mem_err; 7095 7096 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 7097 7098 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping, 7099 bp->context.size); 7100 7101 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); 7102 7103 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 7104 goto alloc_mem_err; 7105 7106 /* Slow path ring */ 7107 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 7108 7109 /* EQ */ 7110 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, 7111 BCM_PAGE_SIZE * NUM_EQ_PAGES); 7112 7113 7114 /* fastpath */ 7115 /* need to be done at the end, since it's self adjusting to amount 7116 * of memory available for RSS queues 7117 */ 7118 if (bnx2x_alloc_fp_mem(bp)) 7119 goto alloc_mem_err; 7120 return 0; 7121 7122 alloc_mem_err: 7123 bnx2x_free_mem(bp); 7124 BNX2X_ERR("Can't allocate memory\n"); 7125 return -ENOMEM; 7126 } 7127 7128 /* 7129 * Init service functions 7130 */ 7131 7132 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 7133 struct bnx2x_vlan_mac_obj *obj, bool set, 7134 int mac_type, unsigned long *ramrod_flags) 7135 { 7136 int rc; 7137 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 7138 7139 memset(&ramrod_param, 0, sizeof(ramrod_param)); 7140 7141 /* Fill general parameters */ 7142 ramrod_param.vlan_mac_obj = obj; 7143 ramrod_param.ramrod_flags = *ramrod_flags; 7144 7145 /* Fill a user request section if needed */ 7146 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 7147 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 7148 7149 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 7150 7151 /* Set the command: ADD or DEL */ 7152 if (set) 7153 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 7154 else 7155 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 7156 } 7157 7158 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 7159 if (rc < 0) 7160 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 7161 return rc; 7162 } 7163 7164 int bnx2x_del_all_macs(struct bnx2x *bp, 7165 struct bnx2x_vlan_mac_obj *mac_obj, 7166 int mac_type, bool wait_for_comp) 7167 { 7168 int rc; 7169 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 7170 7171 /* Wait for completion of requested */ 7172 if (wait_for_comp) 7173 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7174 7175 /* Set the mac type of addresses we want to clear */ 7176 __set_bit(mac_type, &vlan_mac_flags); 7177 7178 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 7179 if (rc < 0) 7180 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 7181 7182 return rc; 7183 } 7184 7185 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 7186 { 7187 unsigned long ramrod_flags = 0; 7188 7189 #ifdef BCM_CNIC 7190 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_STORAGE_SD(bp)) { 7191 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, 7192 "Ignoring Zero MAC for STORAGE SD mode\n"); 7193 return 0; 7194 } 7195 #endif 7196 7197 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 7198 7199 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 7200 /* Eth MAC is set on RSS leading client (fp[0]) */ 7201 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set, 7202 BNX2X_ETH_MAC, &ramrod_flags); 7203 } 7204 7205 int bnx2x_setup_leading(struct bnx2x *bp) 7206 { 7207 return bnx2x_setup_queue(bp, &bp->fp[0], 1); 7208 } 7209 7210 /** 7211 * bnx2x_set_int_mode - configure interrupt mode 7212 * 7213 * @bp: driver handle 7214 * 7215 * In case of MSI-X it will also try to enable MSI-X. 7216 */ 7217 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp) 7218 { 7219 switch (int_mode) { 7220 case INT_MODE_MSI: 7221 bnx2x_enable_msi(bp); 7222 /* falling through... */ 7223 case INT_MODE_INTx: 7224 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7225 BNX2X_DEV_INFO("set number of queues to 1\n"); 7226 break; 7227 default: 7228 /* Set number of queues according to bp->multi_mode value */ 7229 bnx2x_set_num_queues(bp); 7230 7231 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 7232 7233 /* if we can't use MSI-X we only need one fp, 7234 * so try to enable MSI-X with the requested number of fp's 7235 * and fallback to MSI or legacy INTx with one fp 7236 */ 7237 if (bnx2x_enable_msix(bp)) { 7238 /* failed to enable MSI-X */ 7239 BNX2X_DEV_INFO("Failed to enable MSI-X (%d), set number of queues to %d\n", 7240 bp->num_queues, 1 + NON_ETH_CONTEXT_USE); 7241 7242 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7243 7244 /* Try to enable MSI */ 7245 if (!(bp->flags & DISABLE_MSI_FLAG)) 7246 bnx2x_enable_msi(bp); 7247 } 7248 break; 7249 } 7250 } 7251 7252 /* must be called prioir to any HW initializations */ 7253 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 7254 { 7255 return L2_ILT_LINES(bp); 7256 } 7257 7258 void bnx2x_ilt_set_info(struct bnx2x *bp) 7259 { 7260 struct ilt_client_info *ilt_client; 7261 struct bnx2x_ilt *ilt = BP_ILT(bp); 7262 u16 line = 0; 7263 7264 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 7265 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 7266 7267 /* CDU */ 7268 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 7269 ilt_client->client_num = ILT_CLIENT_CDU; 7270 ilt_client->page_size = CDU_ILT_PAGE_SZ; 7271 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 7272 ilt_client->start = line; 7273 line += bnx2x_cid_ilt_lines(bp); 7274 #ifdef BCM_CNIC 7275 line += CNIC_ILT_LINES; 7276 #endif 7277 ilt_client->end = line - 1; 7278 7279 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7280 ilt_client->start, 7281 ilt_client->end, 7282 ilt_client->page_size, 7283 ilt_client->flags, 7284 ilog2(ilt_client->page_size >> 12)); 7285 7286 /* QM */ 7287 if (QM_INIT(bp->qm_cid_count)) { 7288 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 7289 ilt_client->client_num = ILT_CLIENT_QM; 7290 ilt_client->page_size = QM_ILT_PAGE_SZ; 7291 ilt_client->flags = 0; 7292 ilt_client->start = line; 7293 7294 /* 4 bytes for each cid */ 7295 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 7296 QM_ILT_PAGE_SZ); 7297 7298 ilt_client->end = line - 1; 7299 7300 DP(NETIF_MSG_IFUP, 7301 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7302 ilt_client->start, 7303 ilt_client->end, 7304 ilt_client->page_size, 7305 ilt_client->flags, 7306 ilog2(ilt_client->page_size >> 12)); 7307 7308 } 7309 /* SRC */ 7310 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 7311 #ifdef BCM_CNIC 7312 ilt_client->client_num = ILT_CLIENT_SRC; 7313 ilt_client->page_size = SRC_ILT_PAGE_SZ; 7314 ilt_client->flags = 0; 7315 ilt_client->start = line; 7316 line += SRC_ILT_LINES; 7317 ilt_client->end = line - 1; 7318 7319 DP(NETIF_MSG_IFUP, 7320 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7321 ilt_client->start, 7322 ilt_client->end, 7323 ilt_client->page_size, 7324 ilt_client->flags, 7325 ilog2(ilt_client->page_size >> 12)); 7326 7327 #else 7328 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7329 #endif 7330 7331 /* TM */ 7332 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 7333 #ifdef BCM_CNIC 7334 ilt_client->client_num = ILT_CLIENT_TM; 7335 ilt_client->page_size = TM_ILT_PAGE_SZ; 7336 ilt_client->flags = 0; 7337 ilt_client->start = line; 7338 line += TM_ILT_LINES; 7339 ilt_client->end = line - 1; 7340 7341 DP(NETIF_MSG_IFUP, 7342 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 7343 ilt_client->start, 7344 ilt_client->end, 7345 ilt_client->page_size, 7346 ilt_client->flags, 7347 ilog2(ilt_client->page_size >> 12)); 7348 7349 #else 7350 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM); 7351 #endif 7352 BUG_ON(line > ILT_MAX_LINES); 7353 } 7354 7355 /** 7356 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 7357 * 7358 * @bp: driver handle 7359 * @fp: pointer to fastpath 7360 * @init_params: pointer to parameters structure 7361 * 7362 * parameters configured: 7363 * - HC configuration 7364 * - Queue's CDU context 7365 */ 7366 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp, 7367 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 7368 { 7369 7370 u8 cos; 7371 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 7372 if (!IS_FCOE_FP(fp)) { 7373 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 7374 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 7375 7376 /* If HC is supporterd, enable host coalescing in the transition 7377 * to INIT state. 7378 */ 7379 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 7380 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 7381 7382 /* HC rate */ 7383 init_params->rx.hc_rate = bp->rx_ticks ? 7384 (1000000 / bp->rx_ticks) : 0; 7385 init_params->tx.hc_rate = bp->tx_ticks ? 7386 (1000000 / bp->tx_ticks) : 0; 7387 7388 /* FW SB ID */ 7389 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 7390 fp->fw_sb_id; 7391 7392 /* 7393 * CQ index among the SB indices: FCoE clients uses the default 7394 * SB, therefore it's different. 7395 */ 7396 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 7397 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 7398 } 7399 7400 /* set maximum number of COSs supported by this queue */ 7401 init_params->max_cos = fp->max_cos; 7402 7403 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", 7404 fp->index, init_params->max_cos); 7405 7406 /* set the context pointers queue object */ 7407 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) 7408 init_params->cxts[cos] = 7409 &bp->context.vcxt[fp->txdata[cos].cid].eth; 7410 } 7411 7412 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7413 struct bnx2x_queue_state_params *q_params, 7414 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 7415 int tx_index, bool leading) 7416 { 7417 memset(tx_only_params, 0, sizeof(*tx_only_params)); 7418 7419 /* Set the command */ 7420 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 7421 7422 /* Set tx-only QUEUE flags: don't zero statistics */ 7423 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 7424 7425 /* choose the index of the cid to send the slow path on */ 7426 tx_only_params->cid_index = tx_index; 7427 7428 /* Set general TX_ONLY_SETUP parameters */ 7429 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 7430 7431 /* Set Tx TX_ONLY_SETUP parameters */ 7432 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7433 7434 DP(NETIF_MSG_IFUP, 7435 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", 7436 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7437 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7438 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7439 7440 /* send the ramrod */ 7441 return bnx2x_queue_state_change(bp, q_params); 7442 } 7443 7444 7445 /** 7446 * bnx2x_setup_queue - setup queue 7447 * 7448 * @bp: driver handle 7449 * @fp: pointer to fastpath 7450 * @leading: is leading 7451 * 7452 * This function performs 2 steps in a Queue state machine 7453 * actually: 1) RESET->INIT 2) INIT->SETUP 7454 */ 7455 7456 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 7457 bool leading) 7458 { 7459 struct bnx2x_queue_state_params q_params = {NULL}; 7460 struct bnx2x_queue_setup_params *setup_params = 7461 &q_params.params.setup; 7462 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 7463 &q_params.params.tx_only; 7464 int rc; 7465 u8 tx_index; 7466 7467 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); 7468 7469 /* reset IGU state skip FCoE L2 queue */ 7470 if (!IS_FCOE_FP(fp)) 7471 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 7472 IGU_INT_ENABLE, 0); 7473 7474 q_params.q_obj = &fp->q_obj; 7475 /* We want to wait for completion in this context */ 7476 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7477 7478 /* Prepare the INIT parameters */ 7479 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 7480 7481 /* Set the command */ 7482 q_params.cmd = BNX2X_Q_CMD_INIT; 7483 7484 /* Change the state to INIT */ 7485 rc = bnx2x_queue_state_change(bp, &q_params); 7486 if (rc) { 7487 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 7488 return rc; 7489 } 7490 7491 DP(NETIF_MSG_IFUP, "init complete\n"); 7492 7493 7494 /* Now move the Queue to the SETUP state... */ 7495 memset(setup_params, 0, sizeof(*setup_params)); 7496 7497 /* Set QUEUE flags */ 7498 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 7499 7500 /* Set general SETUP parameters */ 7501 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 7502 FIRST_TX_COS_INDEX); 7503 7504 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 7505 &setup_params->rxq_params); 7506 7507 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 7508 FIRST_TX_COS_INDEX); 7509 7510 /* Set the command */ 7511 q_params.cmd = BNX2X_Q_CMD_SETUP; 7512 7513 /* Change the state to SETUP */ 7514 rc = bnx2x_queue_state_change(bp, &q_params); 7515 if (rc) { 7516 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 7517 return rc; 7518 } 7519 7520 /* loop through the relevant tx-only indices */ 7521 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7522 tx_index < fp->max_cos; 7523 tx_index++) { 7524 7525 /* prepare and send tx-only ramrod*/ 7526 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 7527 tx_only_params, tx_index, leading); 7528 if (rc) { 7529 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 7530 fp->index, tx_index); 7531 return rc; 7532 } 7533 } 7534 7535 return rc; 7536 } 7537 7538 static int bnx2x_stop_queue(struct bnx2x *bp, int index) 7539 { 7540 struct bnx2x_fastpath *fp = &bp->fp[index]; 7541 struct bnx2x_fp_txdata *txdata; 7542 struct bnx2x_queue_state_params q_params = {NULL}; 7543 int rc, tx_index; 7544 7545 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); 7546 7547 q_params.q_obj = &fp->q_obj; 7548 /* We want to wait for completion in this context */ 7549 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 7550 7551 7552 /* close tx-only connections */ 7553 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 7554 tx_index < fp->max_cos; 7555 tx_index++){ 7556 7557 /* ascertain this is a normal queue*/ 7558 txdata = &fp->txdata[tx_index]; 7559 7560 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", 7561 txdata->txq_index); 7562 7563 /* send halt terminate on tx-only connection */ 7564 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7565 memset(&q_params.params.terminate, 0, 7566 sizeof(q_params.params.terminate)); 7567 q_params.params.terminate.cid_index = tx_index; 7568 7569 rc = bnx2x_queue_state_change(bp, &q_params); 7570 if (rc) 7571 return rc; 7572 7573 /* send halt terminate on tx-only connection */ 7574 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7575 memset(&q_params.params.cfc_del, 0, 7576 sizeof(q_params.params.cfc_del)); 7577 q_params.params.cfc_del.cid_index = tx_index; 7578 rc = bnx2x_queue_state_change(bp, &q_params); 7579 if (rc) 7580 return rc; 7581 } 7582 /* Stop the primary connection: */ 7583 /* ...halt the connection */ 7584 q_params.cmd = BNX2X_Q_CMD_HALT; 7585 rc = bnx2x_queue_state_change(bp, &q_params); 7586 if (rc) 7587 return rc; 7588 7589 /* ...terminate the connection */ 7590 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 7591 memset(&q_params.params.terminate, 0, 7592 sizeof(q_params.params.terminate)); 7593 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 7594 rc = bnx2x_queue_state_change(bp, &q_params); 7595 if (rc) 7596 return rc; 7597 /* ...delete cfc entry */ 7598 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 7599 memset(&q_params.params.cfc_del, 0, 7600 sizeof(q_params.params.cfc_del)); 7601 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 7602 return bnx2x_queue_state_change(bp, &q_params); 7603 } 7604 7605 7606 static void bnx2x_reset_func(struct bnx2x *bp) 7607 { 7608 int port = BP_PORT(bp); 7609 int func = BP_FUNC(bp); 7610 int i; 7611 7612 /* Disable the function in the FW */ 7613 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 7614 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 7615 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 7616 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 7617 7618 /* FP SBs */ 7619 for_each_eth_queue(bp, i) { 7620 struct bnx2x_fastpath *fp = &bp->fp[i]; 7621 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7622 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 7623 SB_DISABLED); 7624 } 7625 7626 #ifdef BCM_CNIC 7627 /* CNIC SB */ 7628 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7629 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)), 7630 SB_DISABLED); 7631 #endif 7632 /* SP SB */ 7633 REG_WR8(bp, BAR_CSTRORM_INTMEM + 7634 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 7635 SB_DISABLED); 7636 7637 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 7638 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 7639 0); 7640 7641 /* Configure IGU */ 7642 if (bp->common.int_block == INT_BLOCK_HC) { 7643 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7644 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7645 } else { 7646 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 7647 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 7648 } 7649 7650 #ifdef BCM_CNIC 7651 /* Disable Timer scan */ 7652 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 7653 /* 7654 * Wait for at least 10ms and up to 2 second for the timers scan to 7655 * complete 7656 */ 7657 for (i = 0; i < 200; i++) { 7658 msleep(10); 7659 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 7660 break; 7661 } 7662 #endif 7663 /* Clear ILT */ 7664 bnx2x_clear_func_ilt(bp, func); 7665 7666 /* Timers workaround bug for E2: if this is vnic-3, 7667 * we need to set the entire ilt range for this timers. 7668 */ 7669 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 7670 struct ilt_client_info ilt_cli; 7671 /* use dummy TM client */ 7672 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7673 ilt_cli.start = 0; 7674 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7675 ilt_cli.client_num = ILT_CLIENT_TM; 7676 7677 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 7678 } 7679 7680 /* this assumes that reset_port() called before reset_func()*/ 7681 if (!CHIP_IS_E1x(bp)) 7682 bnx2x_pf_disable(bp); 7683 7684 bp->dmae_ready = 0; 7685 } 7686 7687 static void bnx2x_reset_port(struct bnx2x *bp) 7688 { 7689 int port = BP_PORT(bp); 7690 u32 val; 7691 7692 /* Reset physical Link */ 7693 bnx2x__link_reset(bp); 7694 7695 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7696 7697 /* Do not rcv packets to BRB */ 7698 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 7699 /* Do not direct rcv packets that are not for MCP to the BRB */ 7700 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 7701 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 7702 7703 /* Configure AEU */ 7704 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 7705 7706 msleep(100); 7707 /* Check for BRB port occupancy */ 7708 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 7709 if (val) 7710 DP(NETIF_MSG_IFDOWN, 7711 "BRB1 is not empty %d blocks are occupied\n", val); 7712 7713 /* TODO: Close Doorbell port? */ 7714 } 7715 7716 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 7717 { 7718 struct bnx2x_func_state_params func_params = {NULL}; 7719 7720 /* Prepare parameters for function state transitions */ 7721 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7722 7723 func_params.f_obj = &bp->func_obj; 7724 func_params.cmd = BNX2X_F_CMD_HW_RESET; 7725 7726 func_params.params.hw_init.load_phase = load_code; 7727 7728 return bnx2x_func_state_change(bp, &func_params); 7729 } 7730 7731 static inline int bnx2x_func_stop(struct bnx2x *bp) 7732 { 7733 struct bnx2x_func_state_params func_params = {NULL}; 7734 int rc; 7735 7736 /* Prepare parameters for function state transitions */ 7737 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7738 func_params.f_obj = &bp->func_obj; 7739 func_params.cmd = BNX2X_F_CMD_STOP; 7740 7741 /* 7742 * Try to stop the function the 'good way'. If fails (in case 7743 * of a parity error during bnx2x_chip_cleanup()) and we are 7744 * not in a debug mode, perform a state transaction in order to 7745 * enable further HW_RESET transaction. 7746 */ 7747 rc = bnx2x_func_state_change(bp, &func_params); 7748 if (rc) { 7749 #ifdef BNX2X_STOP_ON_ERROR 7750 return rc; 7751 #else 7752 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); 7753 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7754 return bnx2x_func_state_change(bp, &func_params); 7755 #endif 7756 } 7757 7758 return 0; 7759 } 7760 7761 /** 7762 * bnx2x_send_unload_req - request unload mode from the MCP. 7763 * 7764 * @bp: driver handle 7765 * @unload_mode: requested function's unload mode 7766 * 7767 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 7768 */ 7769 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 7770 { 7771 u32 reset_code = 0; 7772 int port = BP_PORT(bp); 7773 7774 /* Select the UNLOAD request mode */ 7775 if (unload_mode == UNLOAD_NORMAL) 7776 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7777 7778 else if (bp->flags & NO_WOL_FLAG) 7779 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 7780 7781 else if (bp->wol) { 7782 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7783 u8 *mac_addr = bp->dev->dev_addr; 7784 u32 val; 7785 u16 pmc; 7786 7787 /* The mac address is written to entries 1-4 to 7788 * preserve entry 0 which is used by the PMF 7789 */ 7790 u8 entry = (BP_VN(bp) + 1)*8; 7791 7792 val = (mac_addr[0] << 8) | mac_addr[1]; 7793 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7794 7795 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 7796 (mac_addr[4] << 8) | mac_addr[5]; 7797 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 7798 7799 /* Enable the PME and clear the status */ 7800 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); 7801 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 7802 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); 7803 7804 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 7805 7806 } else 7807 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7808 7809 /* Send the request to the MCP */ 7810 if (!BP_NOMCP(bp)) 7811 reset_code = bnx2x_fw_command(bp, reset_code, 0); 7812 else { 7813 int path = BP_PATH(bp); 7814 7815 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", 7816 path, load_count[path][0], load_count[path][1], 7817 load_count[path][2]); 7818 load_count[path][0]--; 7819 load_count[path][1 + port]--; 7820 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", 7821 path, load_count[path][0], load_count[path][1], 7822 load_count[path][2]); 7823 if (load_count[path][0] == 0) 7824 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7825 else if (load_count[path][1 + port] == 0) 7826 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7827 else 7828 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7829 } 7830 7831 return reset_code; 7832 } 7833 7834 /** 7835 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 7836 * 7837 * @bp: driver handle 7838 */ 7839 void bnx2x_send_unload_done(struct bnx2x *bp) 7840 { 7841 /* Report UNLOAD_DONE to MCP */ 7842 if (!BP_NOMCP(bp)) 7843 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 7844 } 7845 7846 static inline int bnx2x_func_wait_started(struct bnx2x *bp) 7847 { 7848 int tout = 50; 7849 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 7850 7851 if (!bp->port.pmf) 7852 return 0; 7853 7854 /* 7855 * (assumption: No Attention from MCP at this stage) 7856 * PMF probably in the middle of TXdisable/enable transaction 7857 * 1. Sync IRS for default SB 7858 * 2. Sync SP queue - this guarantes us that attention handling started 7859 * 3. Wait, that TXdisable/enable transaction completes 7860 * 7861 * 1+2 guranty that if DCBx attention was scheduled it already changed 7862 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy 7863 * received complettion for the transaction the state is TX_STOPPED. 7864 * State will return to STARTED after completion of TX_STOPPED-->STARTED 7865 * transaction. 7866 */ 7867 7868 /* make sure default SB ISR is done */ 7869 if (msix) 7870 synchronize_irq(bp->msix_table[0].vector); 7871 else 7872 synchronize_irq(bp->pdev->irq); 7873 7874 flush_workqueue(bnx2x_wq); 7875 7876 while (bnx2x_func_get_state(bp, &bp->func_obj) != 7877 BNX2X_F_STATE_STARTED && tout--) 7878 msleep(20); 7879 7880 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7881 BNX2X_F_STATE_STARTED) { 7882 #ifdef BNX2X_STOP_ON_ERROR 7883 BNX2X_ERR("Wrong function state\n"); 7884 return -EBUSY; 7885 #else 7886 /* 7887 * Failed to complete the transaction in a "good way" 7888 * Force both transactions with CLR bit 7889 */ 7890 struct bnx2x_func_state_params func_params = {NULL}; 7891 7892 DP(NETIF_MSG_IFDOWN, 7893 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7894 7895 func_params.f_obj = &bp->func_obj; 7896 __set_bit(RAMROD_DRV_CLR_ONLY, 7897 &func_params.ramrod_flags); 7898 7899 /* STARTED-->TX_ST0PPED */ 7900 func_params.cmd = BNX2X_F_CMD_TX_STOP; 7901 bnx2x_func_state_change(bp, &func_params); 7902 7903 /* TX_ST0PPED-->STARTED */ 7904 func_params.cmd = BNX2X_F_CMD_TX_START; 7905 return bnx2x_func_state_change(bp, &func_params); 7906 #endif 7907 } 7908 7909 return 0; 7910 } 7911 7912 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7913 { 7914 int port = BP_PORT(bp); 7915 int i, rc = 0; 7916 u8 cos; 7917 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 7918 u32 reset_code; 7919 7920 /* Wait until tx fastpath tasks complete */ 7921 for_each_tx_queue(bp, i) { 7922 struct bnx2x_fastpath *fp = &bp->fp[i]; 7923 7924 for_each_cos_in_tx_queue(fp, cos) 7925 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]); 7926 #ifdef BNX2X_STOP_ON_ERROR 7927 if (rc) 7928 return; 7929 #endif 7930 } 7931 7932 /* Give HW time to discard old tx messages */ 7933 usleep_range(1000, 1000); 7934 7935 /* Clean all ETH MACs */ 7936 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false); 7937 if (rc < 0) 7938 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 7939 7940 /* Clean up UC list */ 7941 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7942 true); 7943 if (rc < 0) 7944 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", 7945 rc); 7946 7947 /* Disable LLH */ 7948 if (!CHIP_IS_E1(bp)) 7949 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7950 7951 /* Set "drop all" (stop Rx). 7952 * We need to take a netif_addr_lock() here in order to prevent 7953 * a race between the completion code and this code. 7954 */ 7955 netif_addr_lock_bh(bp->dev); 7956 /* Schedule the rx_mode command */ 7957 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 7958 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 7959 else 7960 bnx2x_set_storm_rx_mode(bp); 7961 7962 /* Cleanup multicast configuration */ 7963 rparam.mcast_obj = &bp->mcast_obj; 7964 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 7965 if (rc < 0) 7966 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 7967 7968 netif_addr_unlock_bh(bp->dev); 7969 7970 7971 7972 /* 7973 * Send the UNLOAD_REQUEST to the MCP. This will return if 7974 * this function should perform FUNC, PORT or COMMON HW 7975 * reset. 7976 */ 7977 reset_code = bnx2x_send_unload_req(bp, unload_mode); 7978 7979 /* 7980 * (assumption: No Attention from MCP at this stage) 7981 * PMF probably in the middle of TXdisable/enable transaction 7982 */ 7983 rc = bnx2x_func_wait_started(bp); 7984 if (rc) { 7985 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 7986 #ifdef BNX2X_STOP_ON_ERROR 7987 return; 7988 #endif 7989 } 7990 7991 /* Close multi and leading connections 7992 * Completions for ramrods are collected in a synchronous way 7993 */ 7994 for_each_queue(bp, i) 7995 if (bnx2x_stop_queue(bp, i)) 7996 #ifdef BNX2X_STOP_ON_ERROR 7997 return; 7998 #else 7999 goto unload_error; 8000 #endif 8001 /* If SP settings didn't get completed so far - something 8002 * very wrong has happen. 8003 */ 8004 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 8005 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 8006 8007 #ifndef BNX2X_STOP_ON_ERROR 8008 unload_error: 8009 #endif 8010 rc = bnx2x_func_stop(bp); 8011 if (rc) { 8012 BNX2X_ERR("Function stop failed!\n"); 8013 #ifdef BNX2X_STOP_ON_ERROR 8014 return; 8015 #endif 8016 } 8017 8018 /* Disable HW interrupts, NAPI */ 8019 bnx2x_netif_stop(bp, 1); 8020 8021 /* Release IRQs */ 8022 bnx2x_free_irq(bp); 8023 8024 /* Reset the chip */ 8025 rc = bnx2x_reset_hw(bp, reset_code); 8026 if (rc) 8027 BNX2X_ERR("HW_RESET failed\n"); 8028 8029 8030 /* Report UNLOAD_DONE to MCP */ 8031 bnx2x_send_unload_done(bp); 8032 } 8033 8034 void bnx2x_disable_close_the_gate(struct bnx2x *bp) 8035 { 8036 u32 val; 8037 8038 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); 8039 8040 if (CHIP_IS_E1(bp)) { 8041 int port = BP_PORT(bp); 8042 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8043 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8044 8045 val = REG_RD(bp, addr); 8046 val &= ~(0x300); 8047 REG_WR(bp, addr, val); 8048 } else { 8049 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 8050 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 8051 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 8052 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 8053 } 8054 } 8055 8056 /* Close gates #2, #3 and #4: */ 8057 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 8058 { 8059 u32 val; 8060 8061 /* Gates #2 and #4a are closed/opened for "not E1" only */ 8062 if (!CHIP_IS_E1(bp)) { 8063 /* #4 */ 8064 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 8065 /* #2 */ 8066 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 8067 } 8068 8069 /* #3 */ 8070 if (CHIP_IS_E1x(bp)) { 8071 /* Prevent interrupts from HC on both ports */ 8072 val = REG_RD(bp, HC_REG_CONFIG_1); 8073 REG_WR(bp, HC_REG_CONFIG_1, 8074 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 8075 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 8076 8077 val = REG_RD(bp, HC_REG_CONFIG_0); 8078 REG_WR(bp, HC_REG_CONFIG_0, 8079 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 8080 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 8081 } else { 8082 /* Prevent incomming interrupts in IGU */ 8083 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 8084 8085 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 8086 (!close) ? 8087 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 8088 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8089 } 8090 8091 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", 8092 close ? "closing" : "opening"); 8093 mmiowb(); 8094 } 8095 8096 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 8097 8098 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 8099 { 8100 /* Do some magic... */ 8101 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8102 *magic_val = val & SHARED_MF_CLP_MAGIC; 8103 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 8104 } 8105 8106 /** 8107 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 8108 * 8109 * @bp: driver handle 8110 * @magic_val: old value of the `magic' bit. 8111 */ 8112 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 8113 { 8114 /* Restore the `magic' bit value... */ 8115 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 8116 MF_CFG_WR(bp, shared_mf_config.clp_mb, 8117 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 8118 } 8119 8120 /** 8121 * bnx2x_reset_mcp_prep - prepare for MCP reset. 8122 * 8123 * @bp: driver handle 8124 * @magic_val: old value of 'magic' bit. 8125 * 8126 * Takes care of CLP configurations. 8127 */ 8128 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 8129 { 8130 u32 shmem; 8131 u32 validity_offset; 8132 8133 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); 8134 8135 /* Set `magic' bit in order to save MF config */ 8136 if (!CHIP_IS_E1(bp)) 8137 bnx2x_clp_reset_prep(bp, magic_val); 8138 8139 /* Get shmem offset */ 8140 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8141 validity_offset = offsetof(struct shmem_region, validity_map[0]); 8142 8143 /* Clear validity map flags */ 8144 if (shmem > 0) 8145 REG_WR(bp, shmem + validity_offset, 0); 8146 } 8147 8148 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 8149 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 8150 8151 /** 8152 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 8153 * 8154 * @bp: driver handle 8155 */ 8156 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 8157 { 8158 /* special handling for emulation and FPGA, 8159 wait 10 times longer */ 8160 if (CHIP_REV_IS_SLOW(bp)) 8161 msleep(MCP_ONE_TIMEOUT*10); 8162 else 8163 msleep(MCP_ONE_TIMEOUT); 8164 } 8165 8166 /* 8167 * initializes bp->common.shmem_base and waits for validity signature to appear 8168 */ 8169 static int bnx2x_init_shmem(struct bnx2x *bp) 8170 { 8171 int cnt = 0; 8172 u32 val = 0; 8173 8174 do { 8175 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 8176 if (bp->common.shmem_base) { 8177 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 8178 if (val & SHR_MEM_VALIDITY_MB) 8179 return 0; 8180 } 8181 8182 bnx2x_mcp_wait_one(bp); 8183 8184 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 8185 8186 BNX2X_ERR("BAD MCP validity signature\n"); 8187 8188 return -ENODEV; 8189 } 8190 8191 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 8192 { 8193 int rc = bnx2x_init_shmem(bp); 8194 8195 /* Restore the `magic' bit value */ 8196 if (!CHIP_IS_E1(bp)) 8197 bnx2x_clp_reset_done(bp, magic_val); 8198 8199 return rc; 8200 } 8201 8202 static void bnx2x_pxp_prep(struct bnx2x *bp) 8203 { 8204 if (!CHIP_IS_E1(bp)) { 8205 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 8206 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 8207 mmiowb(); 8208 } 8209 } 8210 8211 /* 8212 * Reset the whole chip except for: 8213 * - PCIE core 8214 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 8215 * one reset bit) 8216 * - IGU 8217 * - MISC (including AEU) 8218 * - GRC 8219 * - RBCN, RBCP 8220 */ 8221 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 8222 { 8223 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 8224 u32 global_bits2, stay_reset2; 8225 8226 /* 8227 * Bits that have to be set in reset_mask2 if we want to reset 'global' 8228 * (per chip) blocks. 8229 */ 8230 global_bits2 = 8231 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 8232 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 8233 8234 /* Don't reset the following blocks */ 8235 not_reset_mask1 = 8236 MISC_REGISTERS_RESET_REG_1_RST_HC | 8237 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 8238 MISC_REGISTERS_RESET_REG_1_RST_PXP; 8239 8240 not_reset_mask2 = 8241 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 8242 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 8243 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 8244 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 8245 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 8246 MISC_REGISTERS_RESET_REG_2_RST_GRC | 8247 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 8248 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 8249 MISC_REGISTERS_RESET_REG_2_RST_ATC | 8250 MISC_REGISTERS_RESET_REG_2_PGLC; 8251 8252 /* 8253 * Keep the following blocks in reset: 8254 * - all xxMACs are handled by the bnx2x_link code. 8255 */ 8256 stay_reset2 = 8257 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 8258 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 8259 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 8260 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 8261 MISC_REGISTERS_RESET_REG_2_UMAC0 | 8262 MISC_REGISTERS_RESET_REG_2_UMAC1 | 8263 MISC_REGISTERS_RESET_REG_2_XMAC | 8264 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 8265 8266 /* Full reset masks according to the chip */ 8267 reset_mask1 = 0xffffffff; 8268 8269 if (CHIP_IS_E1(bp)) 8270 reset_mask2 = 0xffff; 8271 else if (CHIP_IS_E1H(bp)) 8272 reset_mask2 = 0x1ffff; 8273 else if (CHIP_IS_E2(bp)) 8274 reset_mask2 = 0xfffff; 8275 else /* CHIP_IS_E3 */ 8276 reset_mask2 = 0x3ffffff; 8277 8278 /* Don't reset global blocks unless we need to */ 8279 if (!global) 8280 reset_mask2 &= ~global_bits2; 8281 8282 /* 8283 * In case of attention in the QM, we need to reset PXP 8284 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 8285 * because otherwise QM reset would release 'close the gates' shortly 8286 * before resetting the PXP, then the PSWRQ would send a write 8287 * request to PGLUE. Then when PXP is reset, PGLUE would try to 8288 * read the payload data from PSWWR, but PSWWR would not 8289 * respond. The write queue in PGLUE would stuck, dmae commands 8290 * would not return. Therefore it's important to reset the second 8291 * reset register (containing the 8292 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 8293 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 8294 * bit). 8295 */ 8296 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8297 reset_mask2 & (~not_reset_mask2)); 8298 8299 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8300 reset_mask1 & (~not_reset_mask1)); 8301 8302 barrier(); 8303 mmiowb(); 8304 8305 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 8306 reset_mask2 & (~stay_reset2)); 8307 8308 barrier(); 8309 mmiowb(); 8310 8311 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 8312 mmiowb(); 8313 } 8314 8315 /** 8316 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 8317 * It should get cleared in no more than 1s. 8318 * 8319 * @bp: driver handle 8320 * 8321 * It should get cleared in no more than 1s. Returns 0 if 8322 * pending writes bit gets cleared. 8323 */ 8324 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 8325 { 8326 u32 cnt = 1000; 8327 u32 pend_bits = 0; 8328 8329 do { 8330 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 8331 8332 if (pend_bits == 0) 8333 break; 8334 8335 usleep_range(1000, 1000); 8336 } while (cnt-- > 0); 8337 8338 if (cnt <= 0) { 8339 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 8340 pend_bits); 8341 return -EBUSY; 8342 } 8343 8344 return 0; 8345 } 8346 8347 static int bnx2x_process_kill(struct bnx2x *bp, bool global) 8348 { 8349 int cnt = 1000; 8350 u32 val = 0; 8351 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 8352 8353 8354 /* Empty the Tetris buffer, wait for 1s */ 8355 do { 8356 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 8357 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 8358 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 8359 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 8360 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 8361 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 8362 ((port_is_idle_0 & 0x1) == 0x1) && 8363 ((port_is_idle_1 & 0x1) == 0x1) && 8364 (pgl_exp_rom2 == 0xffffffff)) 8365 break; 8366 usleep_range(1000, 1000); 8367 } while (cnt-- > 0); 8368 8369 if (cnt <= 0) { 8370 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); 8371 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 8372 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8373 pgl_exp_rom2); 8374 return -EAGAIN; 8375 } 8376 8377 barrier(); 8378 8379 /* Close gates #2, #3 and #4 */ 8380 bnx2x_set_234_gates(bp, true); 8381 8382 /* Poll for IGU VQs for 57712 and newer chips */ 8383 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 8384 return -EAGAIN; 8385 8386 8387 /* TBD: Indicate that "process kill" is in progress to MCP */ 8388 8389 /* Clear "unprepared" bit */ 8390 REG_WR(bp, MISC_REG_UNPREPARED, 0); 8391 barrier(); 8392 8393 /* Make sure all is written to the chip before the reset */ 8394 mmiowb(); 8395 8396 /* Wait for 1ms to empty GLUE and PCI-E core queues, 8397 * PSWHST, GRC and PSWRD Tetris buffer. 8398 */ 8399 usleep_range(1000, 1000); 8400 8401 /* Prepare to chip reset: */ 8402 /* MCP */ 8403 if (global) 8404 bnx2x_reset_mcp_prep(bp, &val); 8405 8406 /* PXP */ 8407 bnx2x_pxp_prep(bp); 8408 barrier(); 8409 8410 /* reset the chip */ 8411 bnx2x_process_kill_chip_reset(bp, global); 8412 barrier(); 8413 8414 /* Recover after reset: */ 8415 /* MCP */ 8416 if (global && bnx2x_reset_mcp_comp(bp, val)) 8417 return -EAGAIN; 8418 8419 /* TBD: Add resetting the NO_MCP mode DB here */ 8420 8421 /* PXP */ 8422 bnx2x_pxp_prep(bp); 8423 8424 /* Open the gates #2, #3 and #4 */ 8425 bnx2x_set_234_gates(bp, false); 8426 8427 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 8428 * reset state, re-enable attentions. */ 8429 8430 return 0; 8431 } 8432 8433 int bnx2x_leader_reset(struct bnx2x *bp) 8434 { 8435 int rc = 0; 8436 bool global = bnx2x_reset_is_global(bp); 8437 u32 load_code; 8438 8439 /* if not going to reset MCP - load "fake" driver to reset HW while 8440 * driver is owner of the HW 8441 */ 8442 if (!global && !BP_NOMCP(bp)) { 8443 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0); 8444 if (!load_code) { 8445 BNX2X_ERR("MCP response failure, aborting\n"); 8446 rc = -EAGAIN; 8447 goto exit_leader_reset; 8448 } 8449 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 8450 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 8451 BNX2X_ERR("MCP unexpected resp, aborting\n"); 8452 rc = -EAGAIN; 8453 goto exit_leader_reset2; 8454 } 8455 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 8456 if (!load_code) { 8457 BNX2X_ERR("MCP response failure, aborting\n"); 8458 rc = -EAGAIN; 8459 goto exit_leader_reset2; 8460 } 8461 } 8462 8463 /* Try to recover after the failure */ 8464 if (bnx2x_process_kill(bp, global)) { 8465 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", 8466 BP_PATH(bp)); 8467 rc = -EAGAIN; 8468 goto exit_leader_reset2; 8469 } 8470 8471 /* 8472 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 8473 * state. 8474 */ 8475 bnx2x_set_reset_done(bp); 8476 if (global) 8477 bnx2x_clear_reset_global(bp); 8478 8479 exit_leader_reset2: 8480 /* unload "fake driver" if it was loaded */ 8481 if (!global && !BP_NOMCP(bp)) { 8482 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 8483 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8484 } 8485 exit_leader_reset: 8486 bp->is_leader = 0; 8487 bnx2x_release_leader_lock(bp); 8488 smp_mb(); 8489 return rc; 8490 } 8491 8492 static inline void bnx2x_recovery_failed(struct bnx2x *bp) 8493 { 8494 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 8495 8496 /* Disconnect this device */ 8497 netif_device_detach(bp->dev); 8498 8499 /* 8500 * Block ifup for all function on this engine until "process kill" 8501 * or power cycle. 8502 */ 8503 bnx2x_set_reset_in_progress(bp); 8504 8505 /* Shut down the power */ 8506 bnx2x_set_power_state(bp, PCI_D3hot); 8507 8508 bp->recovery_state = BNX2X_RECOVERY_FAILED; 8509 8510 smp_mb(); 8511 } 8512 8513 /* 8514 * Assumption: runs under rtnl lock. This together with the fact 8515 * that it's called only from bnx2x_sp_rtnl() ensure that it 8516 * will never be called when netif_running(bp->dev) is false. 8517 */ 8518 static void bnx2x_parity_recover(struct bnx2x *bp) 8519 { 8520 bool global = false; 8521 u32 error_recovered, error_unrecovered; 8522 bool is_parity; 8523 8524 DP(NETIF_MSG_HW, "Handling parity\n"); 8525 while (1) { 8526 switch (bp->recovery_state) { 8527 case BNX2X_RECOVERY_INIT: 8528 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 8529 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 8530 WARN_ON(!is_parity); 8531 8532 /* Try to get a LEADER_LOCK HW lock */ 8533 if (bnx2x_trylock_leader_lock(bp)) { 8534 bnx2x_set_reset_in_progress(bp); 8535 /* 8536 * Check if there is a global attention and if 8537 * there was a global attention, set the global 8538 * reset bit. 8539 */ 8540 8541 if (global) 8542 bnx2x_set_reset_global(bp); 8543 8544 bp->is_leader = 1; 8545 } 8546 8547 /* Stop the driver */ 8548 /* If interface has been removed - break */ 8549 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY)) 8550 return; 8551 8552 bp->recovery_state = BNX2X_RECOVERY_WAIT; 8553 8554 /* Ensure "is_leader", MCP command sequence and 8555 * "recovery_state" update values are seen on other 8556 * CPUs. 8557 */ 8558 smp_mb(); 8559 break; 8560 8561 case BNX2X_RECOVERY_WAIT: 8562 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 8563 if (bp->is_leader) { 8564 int other_engine = BP_PATH(bp) ? 0 : 1; 8565 bool other_load_status = 8566 bnx2x_get_load_status(bp, other_engine); 8567 bool load_status = 8568 bnx2x_get_load_status(bp, BP_PATH(bp)); 8569 global = bnx2x_reset_is_global(bp); 8570 8571 /* 8572 * In case of a parity in a global block, let 8573 * the first leader that performs a 8574 * leader_reset() reset the global blocks in 8575 * order to clear global attentions. Otherwise 8576 * the the gates will remain closed for that 8577 * engine. 8578 */ 8579 if (load_status || 8580 (global && other_load_status)) { 8581 /* Wait until all other functions get 8582 * down. 8583 */ 8584 schedule_delayed_work(&bp->sp_rtnl_task, 8585 HZ/10); 8586 return; 8587 } else { 8588 /* If all other functions got down - 8589 * try to bring the chip back to 8590 * normal. In any case it's an exit 8591 * point for a leader. 8592 */ 8593 if (bnx2x_leader_reset(bp)) { 8594 bnx2x_recovery_failed(bp); 8595 return; 8596 } 8597 8598 /* If we are here, means that the 8599 * leader has succeeded and doesn't 8600 * want to be a leader any more. Try 8601 * to continue as a none-leader. 8602 */ 8603 break; 8604 } 8605 } else { /* non-leader */ 8606 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 8607 /* Try to get a LEADER_LOCK HW lock as 8608 * long as a former leader may have 8609 * been unloaded by the user or 8610 * released a leadership by another 8611 * reason. 8612 */ 8613 if (bnx2x_trylock_leader_lock(bp)) { 8614 /* I'm a leader now! Restart a 8615 * switch case. 8616 */ 8617 bp->is_leader = 1; 8618 break; 8619 } 8620 8621 schedule_delayed_work(&bp->sp_rtnl_task, 8622 HZ/10); 8623 return; 8624 8625 } else { 8626 /* 8627 * If there was a global attention, wait 8628 * for it to be cleared. 8629 */ 8630 if (bnx2x_reset_is_global(bp)) { 8631 schedule_delayed_work( 8632 &bp->sp_rtnl_task, 8633 HZ/10); 8634 return; 8635 } 8636 8637 error_recovered = 8638 bp->eth_stats.recoverable_error; 8639 error_unrecovered = 8640 bp->eth_stats.unrecoverable_error; 8641 bp->recovery_state = 8642 BNX2X_RECOVERY_NIC_LOADING; 8643 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 8644 error_unrecovered++; 8645 netdev_err(bp->dev, 8646 "Recovery failed. Power cycle needed\n"); 8647 /* Disconnect this device */ 8648 netif_device_detach(bp->dev); 8649 /* Shut down the power */ 8650 bnx2x_set_power_state( 8651 bp, PCI_D3hot); 8652 smp_mb(); 8653 } else { 8654 bp->recovery_state = 8655 BNX2X_RECOVERY_DONE; 8656 error_recovered++; 8657 smp_mb(); 8658 } 8659 bp->eth_stats.recoverable_error = 8660 error_recovered; 8661 bp->eth_stats.unrecoverable_error = 8662 error_unrecovered; 8663 8664 return; 8665 } 8666 } 8667 default: 8668 return; 8669 } 8670 } 8671 } 8672 8673 static int bnx2x_close(struct net_device *dev); 8674 8675 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 8676 * scheduled on a general queue in order to prevent a dead lock. 8677 */ 8678 static void bnx2x_sp_rtnl_task(struct work_struct *work) 8679 { 8680 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 8681 8682 rtnl_lock(); 8683 8684 if (!netif_running(bp->dev)) 8685 goto sp_rtnl_exit; 8686 8687 /* if stop on error is defined no recovery flows should be executed */ 8688 #ifdef BNX2X_STOP_ON_ERROR 8689 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 8690 "you will need to reboot when done\n"); 8691 goto sp_rtnl_not_reset; 8692 #endif 8693 8694 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 8695 /* 8696 * Clear all pending SP commands as we are going to reset the 8697 * function anyway. 8698 */ 8699 bp->sp_rtnl_state = 0; 8700 smp_mb(); 8701 8702 bnx2x_parity_recover(bp); 8703 8704 goto sp_rtnl_exit; 8705 } 8706 8707 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 8708 /* 8709 * Clear all pending SP commands as we are going to reset the 8710 * function anyway. 8711 */ 8712 bp->sp_rtnl_state = 0; 8713 smp_mb(); 8714 8715 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 8716 bnx2x_nic_load(bp, LOAD_NORMAL); 8717 8718 goto sp_rtnl_exit; 8719 } 8720 #ifdef BNX2X_STOP_ON_ERROR 8721 sp_rtnl_not_reset: 8722 #endif 8723 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 8724 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 8725 8726 /* 8727 * in case of fan failure we need to reset id if the "stop on error" 8728 * debug flag is set, since we trying to prevent permanent overheating 8729 * damage 8730 */ 8731 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8732 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); 8733 netif_device_detach(bp->dev); 8734 bnx2x_close(bp->dev); 8735 } 8736 8737 sp_rtnl_exit: 8738 rtnl_unlock(); 8739 } 8740 8741 /* end of nic load/unload */ 8742 8743 static void bnx2x_period_task(struct work_struct *work) 8744 { 8745 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 8746 8747 if (!netif_running(bp->dev)) 8748 goto period_task_exit; 8749 8750 if (CHIP_REV_IS_SLOW(bp)) { 8751 BNX2X_ERR("period task called on emulation, ignoring\n"); 8752 goto period_task_exit; 8753 } 8754 8755 bnx2x_acquire_phy_lock(bp); 8756 /* 8757 * The barrier is needed to ensure the ordering between the writing to 8758 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 8759 * the reading here. 8760 */ 8761 smp_mb(); 8762 if (bp->port.pmf) { 8763 bnx2x_period_func(&bp->link_params, &bp->link_vars); 8764 8765 /* Re-queue task in 1 sec */ 8766 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 8767 } 8768 8769 bnx2x_release_phy_lock(bp); 8770 period_task_exit: 8771 return; 8772 } 8773 8774 /* 8775 * Init service functions 8776 */ 8777 8778 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 8779 { 8780 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 8781 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 8782 return base + (BP_ABS_FUNC(bp)) * stride; 8783 } 8784 8785 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) 8786 { 8787 u32 reg = bnx2x_get_pretend_reg(bp); 8788 8789 /* Flush all outstanding writes */ 8790 mmiowb(); 8791 8792 /* Pretend to be function 0 */ 8793 REG_WR(bp, reg, 0); 8794 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ 8795 8796 /* From now we are in the "like-E1" mode */ 8797 bnx2x_int_disable(bp); 8798 8799 /* Flush all outstanding writes */ 8800 mmiowb(); 8801 8802 /* Restore the original function */ 8803 REG_WR(bp, reg, BP_ABS_FUNC(bp)); 8804 REG_RD(bp, reg); 8805 } 8806 8807 static inline void bnx2x_undi_int_disable(struct bnx2x *bp) 8808 { 8809 if (CHIP_IS_E1(bp)) 8810 bnx2x_int_disable(bp); 8811 else 8812 bnx2x_undi_int_disable_e1h(bp); 8813 } 8814 8815 static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8816 { 8817 u32 val; 8818 8819 /* possibly another driver is trying to reset the chip */ 8820 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8821 8822 /* check if doorbell queue is reset */ 8823 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET) 8824 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 8825 8826 /* 8827 * Check if it is the UNDI driver 8828 * UNDI driver initializes CID offset for normal bell to 0x7 8829 */ 8830 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 8831 if (val == 0x7) { 8832 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8833 /* save our pf_num */ 8834 int orig_pf_num = bp->pf_num; 8835 int port; 8836 u32 swap_en, swap_val, value; 8837 8838 /* clear the UNDI indication */ 8839 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 8840 8841 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 8842 8843 /* try unload UNDI on port 0 */ 8844 bp->pf_num = 0; 8845 bp->fw_seq = 8846 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8847 DRV_MSG_SEQ_NUMBER_MASK); 8848 reset_code = bnx2x_fw_command(bp, reset_code, 0); 8849 8850 /* if UNDI is loaded on the other port */ 8851 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 8852 8853 /* send "DONE" for previous unload */ 8854 bnx2x_fw_command(bp, 8855 DRV_MSG_CODE_UNLOAD_DONE, 0); 8856 8857 /* unload UNDI on port 1 */ 8858 bp->pf_num = 1; 8859 bp->fw_seq = 8860 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & 8861 DRV_MSG_SEQ_NUMBER_MASK); 8862 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 8863 8864 bnx2x_fw_command(bp, reset_code, 0); 8865 } 8866 8867 bnx2x_undi_int_disable(bp); 8868 port = BP_PORT(bp); 8869 8870 /* close input traffic and wait for it */ 8871 /* Do not rcv packets to BRB */ 8872 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK : 8873 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); 8874 /* Do not direct rcv packets that are not for MCP to 8875 * the BRB */ 8876 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 8877 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 8878 /* clear AEU */ 8879 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8880 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); 8881 msleep(10); 8882 8883 /* save NIG port swap info */ 8884 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8885 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8886 /* reset device */ 8887 REG_WR(bp, 8888 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 8889 0xd3ffffff); 8890 8891 value = 0x1400; 8892 if (CHIP_IS_E3(bp)) { 8893 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 8894 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 8895 } 8896 8897 REG_WR(bp, 8898 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 8899 value); 8900 8901 /* take the NIG out of reset and restore swap values */ 8902 REG_WR(bp, 8903 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 8904 MISC_REGISTERS_RESET_REG_1_RST_NIG); 8905 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 8906 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 8907 8908 /* send unload done to the MCP */ 8909 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 8910 8911 /* restore our func and fw_seq */ 8912 bp->pf_num = orig_pf_num; 8913 } 8914 } 8915 8916 /* now it's safe to release the lock */ 8917 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 8918 } 8919 8920 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 8921 { 8922 u32 val, val2, val3, val4, id, boot_mode; 8923 u16 pmc; 8924 8925 /* Get the chip revision id and number. */ 8926 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 8927 val = REG_RD(bp, MISC_REG_CHIP_NUM); 8928 id = ((val & 0xffff) << 16); 8929 val = REG_RD(bp, MISC_REG_CHIP_REV); 8930 id |= ((val & 0xf) << 12); 8931 val = REG_RD(bp, MISC_REG_CHIP_METAL); 8932 id |= ((val & 0xff) << 4); 8933 val = REG_RD(bp, MISC_REG_BOND_ID); 8934 id |= (val & 0xf); 8935 bp->common.chip_id = id; 8936 8937 /* Set doorbell size */ 8938 bp->db_size = (1 << BNX2X_DB_SHIFT); 8939 8940 if (!CHIP_IS_E1x(bp)) { 8941 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 8942 if ((val & 1) == 0) 8943 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 8944 else 8945 val = (val >> 1) & 1; 8946 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 8947 "2_PORT_MODE"); 8948 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 8949 CHIP_2_PORT_MODE; 8950 8951 if (CHIP_MODE_IS_4_PORT(bp)) 8952 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 8953 else 8954 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 8955 } else { 8956 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 8957 bp->pfid = bp->pf_num; /* 0..7 */ 8958 } 8959 8960 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); 8961 8962 bp->link_params.chip_id = bp->common.chip_id; 8963 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8964 8965 val = (REG_RD(bp, 0x2874) & 0x55); 8966 if ((bp->common.chip_id & 0x1) || 8967 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 8968 bp->flags |= ONE_PORT_FLAG; 8969 BNX2X_DEV_INFO("single port device\n"); 8970 } 8971 8972 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 8973 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 8974 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 8975 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 8976 bp->common.flash_size, bp->common.flash_size); 8977 8978 bnx2x_init_shmem(bp); 8979 8980 8981 8982 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 8983 MISC_REG_GENERIC_CR_1 : 8984 MISC_REG_GENERIC_CR_0)); 8985 8986 bp->link_params.shmem_base = bp->common.shmem_base; 8987 bp->link_params.shmem2_base = bp->common.shmem2_base; 8988 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 8989 bp->common.shmem_base, bp->common.shmem2_base); 8990 8991 if (!bp->common.shmem_base) { 8992 BNX2X_DEV_INFO("MCP not active\n"); 8993 bp->flags |= NO_MCP_FLAG; 8994 return; 8995 } 8996 8997 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 8998 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 8999 9000 bp->link_params.hw_led_mode = ((bp->common.hw_config & 9001 SHARED_HW_CFG_LED_MODE_MASK) >> 9002 SHARED_HW_CFG_LED_MODE_SHIFT); 9003 9004 bp->link_params.feature_config_flags = 0; 9005 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 9006 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 9007 bp->link_params.feature_config_flags |= 9008 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9009 else 9010 bp->link_params.feature_config_flags &= 9011 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 9012 9013 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 9014 bp->common.bc_ver = val; 9015 BNX2X_DEV_INFO("bc_ver %X\n", val); 9016 if (val < BNX2X_BC_VER) { 9017 /* for now only warn 9018 * later we might need to enforce this */ 9019 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", 9020 BNX2X_BC_VER, val); 9021 } 9022 bp->link_params.feature_config_flags |= 9023 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9024 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 9025 9026 bp->link_params.feature_config_flags |= 9027 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 9028 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 9029 9030 bp->link_params.feature_config_flags |= 9031 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 9032 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 9033 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 9034 BC_SUPPORTS_PFC_STATS : 0; 9035 9036 boot_mode = SHMEM_RD(bp, 9037 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 9038 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 9039 switch (boot_mode) { 9040 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 9041 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 9042 break; 9043 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 9044 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 9045 break; 9046 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 9047 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 9048 break; 9049 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 9050 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 9051 break; 9052 } 9053 9054 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); 9055 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 9056 9057 BNX2X_DEV_INFO("%sWoL capable\n", 9058 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 9059 9060 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 9061 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 9062 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 9063 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 9064 9065 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 9066 val, val2, val3, val4); 9067 } 9068 9069 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 9070 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 9071 9072 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 9073 { 9074 int pfid = BP_FUNC(bp); 9075 int igu_sb_id; 9076 u32 val; 9077 u8 fid, igu_sb_cnt = 0; 9078 9079 bp->igu_base_sb = 0xff; 9080 if (CHIP_INT_MODE_IS_BC(bp)) { 9081 int vn = BP_VN(bp); 9082 igu_sb_cnt = bp->igu_sb_cnt; 9083 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 9084 FP_SB_MAX_E1x; 9085 9086 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 9087 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 9088 9089 return; 9090 } 9091 9092 /* IGU in normal mode - read CAM */ 9093 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 9094 igu_sb_id++) { 9095 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 9096 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 9097 continue; 9098 fid = IGU_FID(val); 9099 if ((fid & IGU_FID_ENCODE_IS_PF)) { 9100 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 9101 continue; 9102 if (IGU_VEC(val) == 0) 9103 /* default status block */ 9104 bp->igu_dsb_id = igu_sb_id; 9105 else { 9106 if (bp->igu_base_sb == 0xff) 9107 bp->igu_base_sb = igu_sb_id; 9108 igu_sb_cnt++; 9109 } 9110 } 9111 } 9112 9113 #ifdef CONFIG_PCI_MSI 9114 /* 9115 * It's expected that number of CAM entries for this functions is equal 9116 * to the number evaluated based on the MSI-X table size. We want a 9117 * harsh warning if these values are different! 9118 */ 9119 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); 9120 #endif 9121 9122 if (igu_sb_cnt == 0) 9123 BNX2X_ERR("CAM configuration error\n"); 9124 } 9125 9126 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 9127 u32 switch_cfg) 9128 { 9129 int cfg_size = 0, idx, port = BP_PORT(bp); 9130 9131 /* Aggregation of supported attributes of all external phys */ 9132 bp->port.supported[0] = 0; 9133 bp->port.supported[1] = 0; 9134 switch (bp->link_params.num_phys) { 9135 case 1: 9136 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 9137 cfg_size = 1; 9138 break; 9139 case 2: 9140 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 9141 cfg_size = 1; 9142 break; 9143 case 3: 9144 if (bp->link_params.multi_phy_config & 9145 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 9146 bp->port.supported[1] = 9147 bp->link_params.phy[EXT_PHY1].supported; 9148 bp->port.supported[0] = 9149 bp->link_params.phy[EXT_PHY2].supported; 9150 } else { 9151 bp->port.supported[0] = 9152 bp->link_params.phy[EXT_PHY1].supported; 9153 bp->port.supported[1] = 9154 bp->link_params.phy[EXT_PHY2].supported; 9155 } 9156 cfg_size = 2; 9157 break; 9158 } 9159 9160 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9161 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", 9162 SHMEM_RD(bp, 9163 dev_info.port_hw_config[port].external_phy_config), 9164 SHMEM_RD(bp, 9165 dev_info.port_hw_config[port].external_phy_config2)); 9166 return; 9167 } 9168 9169 if (CHIP_IS_E3(bp)) 9170 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 9171 else { 9172 switch (switch_cfg) { 9173 case SWITCH_CFG_1G: 9174 bp->port.phy_addr = REG_RD( 9175 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 9176 break; 9177 case SWITCH_CFG_10G: 9178 bp->port.phy_addr = REG_RD( 9179 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 9180 break; 9181 default: 9182 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 9183 bp->port.link_config[0]); 9184 return; 9185 } 9186 } 9187 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 9188 /* mask what we support according to speed_cap_mask per configuration */ 9189 for (idx = 0; idx < cfg_size; idx++) { 9190 if (!(bp->link_params.speed_cap_mask[idx] & 9191 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 9192 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 9193 9194 if (!(bp->link_params.speed_cap_mask[idx] & 9195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 9196 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 9197 9198 if (!(bp->link_params.speed_cap_mask[idx] & 9199 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 9200 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 9201 9202 if (!(bp->link_params.speed_cap_mask[idx] & 9203 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 9204 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 9205 9206 if (!(bp->link_params.speed_cap_mask[idx] & 9207 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 9208 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 9209 SUPPORTED_1000baseT_Full); 9210 9211 if (!(bp->link_params.speed_cap_mask[idx] & 9212 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 9213 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 9214 9215 if (!(bp->link_params.speed_cap_mask[idx] & 9216 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 9217 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 9218 9219 } 9220 9221 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 9222 bp->port.supported[1]); 9223 } 9224 9225 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 9226 { 9227 u32 link_config, idx, cfg_size = 0; 9228 bp->port.advertising[0] = 0; 9229 bp->port.advertising[1] = 0; 9230 switch (bp->link_params.num_phys) { 9231 case 1: 9232 case 2: 9233 cfg_size = 1; 9234 break; 9235 case 3: 9236 cfg_size = 2; 9237 break; 9238 } 9239 for (idx = 0; idx < cfg_size; idx++) { 9240 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 9241 link_config = bp->port.link_config[idx]; 9242 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 9243 case PORT_FEATURE_LINK_SPEED_AUTO: 9244 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 9245 bp->link_params.req_line_speed[idx] = 9246 SPEED_AUTO_NEG; 9247 bp->port.advertising[idx] |= 9248 bp->port.supported[idx]; 9249 if (bp->link_params.phy[EXT_PHY1].type == 9250 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 9251 bp->port.advertising[idx] |= 9252 (SUPPORTED_100baseT_Half | 9253 SUPPORTED_100baseT_Full); 9254 } else { 9255 /* force 10G, no AN */ 9256 bp->link_params.req_line_speed[idx] = 9257 SPEED_10000; 9258 bp->port.advertising[idx] |= 9259 (ADVERTISED_10000baseT_Full | 9260 ADVERTISED_FIBRE); 9261 continue; 9262 } 9263 break; 9264 9265 case PORT_FEATURE_LINK_SPEED_10M_FULL: 9266 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 9267 bp->link_params.req_line_speed[idx] = 9268 SPEED_10; 9269 bp->port.advertising[idx] |= 9270 (ADVERTISED_10baseT_Full | 9271 ADVERTISED_TP); 9272 } else { 9273 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9274 link_config, 9275 bp->link_params.speed_cap_mask[idx]); 9276 return; 9277 } 9278 break; 9279 9280 case PORT_FEATURE_LINK_SPEED_10M_HALF: 9281 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 9282 bp->link_params.req_line_speed[idx] = 9283 SPEED_10; 9284 bp->link_params.req_duplex[idx] = 9285 DUPLEX_HALF; 9286 bp->port.advertising[idx] |= 9287 (ADVERTISED_10baseT_Half | 9288 ADVERTISED_TP); 9289 } else { 9290 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9291 link_config, 9292 bp->link_params.speed_cap_mask[idx]); 9293 return; 9294 } 9295 break; 9296 9297 case PORT_FEATURE_LINK_SPEED_100M_FULL: 9298 if (bp->port.supported[idx] & 9299 SUPPORTED_100baseT_Full) { 9300 bp->link_params.req_line_speed[idx] = 9301 SPEED_100; 9302 bp->port.advertising[idx] |= 9303 (ADVERTISED_100baseT_Full | 9304 ADVERTISED_TP); 9305 } else { 9306 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9307 link_config, 9308 bp->link_params.speed_cap_mask[idx]); 9309 return; 9310 } 9311 break; 9312 9313 case PORT_FEATURE_LINK_SPEED_100M_HALF: 9314 if (bp->port.supported[idx] & 9315 SUPPORTED_100baseT_Half) { 9316 bp->link_params.req_line_speed[idx] = 9317 SPEED_100; 9318 bp->link_params.req_duplex[idx] = 9319 DUPLEX_HALF; 9320 bp->port.advertising[idx] |= 9321 (ADVERTISED_100baseT_Half | 9322 ADVERTISED_TP); 9323 } else { 9324 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9325 link_config, 9326 bp->link_params.speed_cap_mask[idx]); 9327 return; 9328 } 9329 break; 9330 9331 case PORT_FEATURE_LINK_SPEED_1G: 9332 if (bp->port.supported[idx] & 9333 SUPPORTED_1000baseT_Full) { 9334 bp->link_params.req_line_speed[idx] = 9335 SPEED_1000; 9336 bp->port.advertising[idx] |= 9337 (ADVERTISED_1000baseT_Full | 9338 ADVERTISED_TP); 9339 } else { 9340 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9341 link_config, 9342 bp->link_params.speed_cap_mask[idx]); 9343 return; 9344 } 9345 break; 9346 9347 case PORT_FEATURE_LINK_SPEED_2_5G: 9348 if (bp->port.supported[idx] & 9349 SUPPORTED_2500baseX_Full) { 9350 bp->link_params.req_line_speed[idx] = 9351 SPEED_2500; 9352 bp->port.advertising[idx] |= 9353 (ADVERTISED_2500baseX_Full | 9354 ADVERTISED_TP); 9355 } else { 9356 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9357 link_config, 9358 bp->link_params.speed_cap_mask[idx]); 9359 return; 9360 } 9361 break; 9362 9363 case PORT_FEATURE_LINK_SPEED_10G_CX4: 9364 if (bp->port.supported[idx] & 9365 SUPPORTED_10000baseT_Full) { 9366 bp->link_params.req_line_speed[idx] = 9367 SPEED_10000; 9368 bp->port.advertising[idx] |= 9369 (ADVERTISED_10000baseT_Full | 9370 ADVERTISED_FIBRE); 9371 } else { 9372 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 9373 link_config, 9374 bp->link_params.speed_cap_mask[idx]); 9375 return; 9376 } 9377 break; 9378 case PORT_FEATURE_LINK_SPEED_20G: 9379 bp->link_params.req_line_speed[idx] = SPEED_20000; 9380 9381 break; 9382 default: 9383 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", 9384 link_config); 9385 bp->link_params.req_line_speed[idx] = 9386 SPEED_AUTO_NEG; 9387 bp->port.advertising[idx] = 9388 bp->port.supported[idx]; 9389 break; 9390 } 9391 9392 bp->link_params.req_flow_ctrl[idx] = (link_config & 9393 PORT_FEATURE_FLOW_CONTROL_MASK); 9394 if ((bp->link_params.req_flow_ctrl[idx] == 9395 BNX2X_FLOW_CTRL_AUTO) && 9396 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) { 9397 bp->link_params.req_flow_ctrl[idx] = 9398 BNX2X_FLOW_CTRL_NONE; 9399 } 9400 9401 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", 9402 bp->link_params.req_line_speed[idx], 9403 bp->link_params.req_duplex[idx], 9404 bp->link_params.req_flow_ctrl[idx], 9405 bp->port.advertising[idx]); 9406 } 9407 } 9408 9409 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 9410 { 9411 mac_hi = cpu_to_be16(mac_hi); 9412 mac_lo = cpu_to_be32(mac_lo); 9413 memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); 9414 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); 9415 } 9416 9417 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 9418 { 9419 int port = BP_PORT(bp); 9420 u32 config; 9421 u32 ext_phy_type, ext_phy_config; 9422 9423 bp->link_params.bp = bp; 9424 bp->link_params.port = port; 9425 9426 bp->link_params.lane_config = 9427 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 9428 9429 bp->link_params.speed_cap_mask[0] = 9430 SHMEM_RD(bp, 9431 dev_info.port_hw_config[port].speed_capability_mask); 9432 bp->link_params.speed_cap_mask[1] = 9433 SHMEM_RD(bp, 9434 dev_info.port_hw_config[port].speed_capability_mask2); 9435 bp->port.link_config[0] = 9436 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 9437 9438 bp->port.link_config[1] = 9439 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 9440 9441 bp->link_params.multi_phy_config = 9442 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 9443 /* If the device is capable of WoL, set the default state according 9444 * to the HW 9445 */ 9446 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 9447 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9448 (config & PORT_FEATURE_WOL_ENABLED)); 9449 9450 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", 9451 bp->link_params.lane_config, 9452 bp->link_params.speed_cap_mask[0], 9453 bp->port.link_config[0]); 9454 9455 bp->link_params.switch_cfg = (bp->port.link_config[0] & 9456 PORT_FEATURE_CONNECTED_SWITCH_MASK); 9457 bnx2x_phy_probe(&bp->link_params); 9458 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 9459 9460 bnx2x_link_settings_requested(bp); 9461 9462 /* 9463 * If connected directly, work with the internal PHY, otherwise, work 9464 * with the external PHY 9465 */ 9466 ext_phy_config = 9467 SHMEM_RD(bp, 9468 dev_info.port_hw_config[port].external_phy_config); 9469 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 9470 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9471 bp->mdio.prtad = bp->port.phy_addr; 9472 9473 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 9474 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 9475 bp->mdio.prtad = 9476 XGXS_EXT_PHY_ADDR(ext_phy_config); 9477 9478 /* 9479 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s) 9480 * In MF mode, it is set to cover self test cases 9481 */ 9482 if (IS_MF(bp)) 9483 bp->port.need_hw_lock = 1; 9484 else 9485 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp, 9486 bp->common.shmem_base, 9487 bp->common.shmem2_base); 9488 } 9489 9490 void bnx2x_get_iscsi_info(struct bnx2x *bp) 9491 { 9492 u32 no_flags = NO_ISCSI_FLAG; 9493 #ifdef BCM_CNIC 9494 int port = BP_PORT(bp); 9495 9496 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9497 drv_lic_key[port].max_iscsi_conn); 9498 9499 /* Get the number of maximum allowed iSCSI connections */ 9500 bp->cnic_eth_dev.max_iscsi_conn = 9501 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 9502 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 9503 9504 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 9505 bp->cnic_eth_dev.max_iscsi_conn); 9506 9507 /* 9508 * If maximum allowed number of connections is zero - 9509 * disable the feature. 9510 */ 9511 if (!bp->cnic_eth_dev.max_iscsi_conn) 9512 bp->flags |= no_flags; 9513 #else 9514 bp->flags |= no_flags; 9515 #endif 9516 } 9517 9518 #ifdef BCM_CNIC 9519 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) 9520 { 9521 /* Port info */ 9522 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9523 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); 9524 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9525 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); 9526 9527 /* Node info */ 9528 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9529 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); 9530 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9531 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); 9532 } 9533 #endif 9534 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) 9535 { 9536 #ifdef BCM_CNIC 9537 int port = BP_PORT(bp); 9538 int func = BP_ABS_FUNC(bp); 9539 9540 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 9541 drv_lic_key[port].max_fcoe_conn); 9542 9543 /* Get the number of maximum allowed FCoE connections */ 9544 bp->cnic_eth_dev.max_fcoe_conn = 9545 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 9546 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 9547 9548 /* Read the WWN: */ 9549 if (!IS_MF(bp)) { 9550 /* Port info */ 9551 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 9552 SHMEM_RD(bp, 9553 dev_info.port_hw_config[port]. 9554 fcoe_wwn_port_name_upper); 9555 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 9556 SHMEM_RD(bp, 9557 dev_info.port_hw_config[port]. 9558 fcoe_wwn_port_name_lower); 9559 9560 /* Node info */ 9561 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 9562 SHMEM_RD(bp, 9563 dev_info.port_hw_config[port]. 9564 fcoe_wwn_node_name_upper); 9565 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 9566 SHMEM_RD(bp, 9567 dev_info.port_hw_config[port]. 9568 fcoe_wwn_node_name_lower); 9569 } else if (!IS_MF_SD(bp)) { 9570 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9571 9572 /* 9573 * Read the WWN info only if the FCoE feature is enabled for 9574 * this function. 9575 */ 9576 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 9577 bnx2x_get_ext_wwn_info(bp, func); 9578 9579 } else if (IS_MF_FCOE_SD(bp)) 9580 bnx2x_get_ext_wwn_info(bp, func); 9581 9582 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 9583 9584 /* 9585 * If maximum allowed number of connections is zero - 9586 * disable the feature. 9587 */ 9588 if (!bp->cnic_eth_dev.max_fcoe_conn) 9589 bp->flags |= NO_FCOE_FLAG; 9590 #else 9591 bp->flags |= NO_FCOE_FLAG; 9592 #endif 9593 } 9594 9595 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp) 9596 { 9597 /* 9598 * iSCSI may be dynamically disabled but reading 9599 * info here we will decrease memory usage by driver 9600 * if the feature is disabled for good 9601 */ 9602 bnx2x_get_iscsi_info(bp); 9603 bnx2x_get_fcoe_info(bp); 9604 } 9605 9606 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp) 9607 { 9608 u32 val, val2; 9609 int func = BP_ABS_FUNC(bp); 9610 int port = BP_PORT(bp); 9611 #ifdef BCM_CNIC 9612 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 9613 u8 *fip_mac = bp->fip_mac; 9614 #endif 9615 9616 /* Zero primary MAC configuration */ 9617 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9618 9619 if (BP_NOMCP(bp)) { 9620 BNX2X_ERROR("warning: random MAC workaround active\n"); 9621 eth_hw_addr_random(bp->dev); 9622 } else if (IS_MF(bp)) { 9623 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 9624 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 9625 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 9626 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) 9627 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9628 9629 #ifdef BCM_CNIC 9630 /* 9631 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 9632 * FCoE MAC then the appropriate feature should be disabled. 9633 * 9634 * In non SD mode features configuration comes from 9635 * struct func_ext_config. 9636 */ 9637 if (!IS_MF_SD(bp)) { 9638 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 9639 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 9640 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9641 iscsi_mac_addr_upper); 9642 val = MF_CFG_RD(bp, func_ext_config[func]. 9643 iscsi_mac_addr_lower); 9644 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9645 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9646 iscsi_mac); 9647 } else 9648 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 9649 9650 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 9651 val2 = MF_CFG_RD(bp, func_ext_config[func]. 9652 fcoe_mac_addr_upper); 9653 val = MF_CFG_RD(bp, func_ext_config[func]. 9654 fcoe_mac_addr_lower); 9655 bnx2x_set_mac_buf(fip_mac, val, val2); 9656 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n", 9657 fip_mac); 9658 9659 } else 9660 bp->flags |= NO_FCOE_FLAG; 9661 } else { /* SD MODE */ 9662 if (IS_MF_STORAGE_SD(bp)) { 9663 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { 9664 /* use primary mac as iscsi mac */ 9665 memcpy(iscsi_mac, bp->dev->dev_addr, 9666 ETH_ALEN); 9667 9668 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 9669 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n", 9670 iscsi_mac); 9671 } else { /* FCoE */ 9672 memcpy(fip_mac, bp->dev->dev_addr, 9673 ETH_ALEN); 9674 BNX2X_DEV_INFO("SD FCoE MODE\n"); 9675 BNX2X_DEV_INFO("Read FIP MAC: %pM\n", 9676 fip_mac); 9677 } 9678 /* Zero primary MAC configuration */ 9679 memset(bp->dev->dev_addr, 0, ETH_ALEN); 9680 } 9681 } 9682 #endif 9683 } else { 9684 /* in SF read MACs from port configuration */ 9685 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 9686 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 9687 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); 9688 9689 #ifdef BCM_CNIC 9690 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9691 iscsi_mac_upper); 9692 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9693 iscsi_mac_lower); 9694 bnx2x_set_mac_buf(iscsi_mac, val, val2); 9695 9696 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9697 fcoe_fip_mac_upper); 9698 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 9699 fcoe_fip_mac_lower); 9700 bnx2x_set_mac_buf(fip_mac, val, val2); 9701 #endif 9702 } 9703 9704 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 9705 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 9706 9707 #ifdef BCM_CNIC 9708 /* Disable iSCSI if MAC configuration is 9709 * invalid. 9710 */ 9711 if (!is_valid_ether_addr(iscsi_mac)) { 9712 bp->flags |= NO_ISCSI_FLAG; 9713 memset(iscsi_mac, 0, ETH_ALEN); 9714 } 9715 9716 /* Disable FCoE if MAC configuration is 9717 * invalid. 9718 */ 9719 if (!is_valid_ether_addr(fip_mac)) { 9720 bp->flags |= NO_FCOE_FLAG; 9721 memset(bp->fip_mac, 0, ETH_ALEN); 9722 } 9723 #endif 9724 9725 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9726 dev_err(&bp->pdev->dev, 9727 "bad Ethernet MAC address configuration: %pM\n" 9728 "change it manually before bringing up the appropriate network interface\n", 9729 bp->dev->dev_addr); 9730 9731 9732 } 9733 9734 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9735 { 9736 int /*abs*/func = BP_ABS_FUNC(bp); 9737 int vn; 9738 u32 val = 0; 9739 int rc = 0; 9740 9741 bnx2x_get_common_hwinfo(bp); 9742 9743 /* 9744 * initialize IGU parameters 9745 */ 9746 if (CHIP_IS_E1x(bp)) { 9747 bp->common.int_block = INT_BLOCK_HC; 9748 9749 bp->igu_dsb_id = DEF_SB_IGU_ID; 9750 bp->igu_base_sb = 0; 9751 } else { 9752 bp->common.int_block = INT_BLOCK_IGU; 9753 9754 /* do not allow device reset during IGU info preocessing */ 9755 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9756 9757 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9758 9759 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9760 int tout = 5000; 9761 9762 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 9763 9764 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 9765 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 9766 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 9767 9768 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9769 tout--; 9770 usleep_range(1000, 1000); 9771 } 9772 9773 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 9774 dev_err(&bp->pdev->dev, 9775 "FORCING Normal Mode failed!!!\n"); 9776 return -EPERM; 9777 } 9778 } 9779 9780 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 9781 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 9782 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 9783 } else 9784 BNX2X_DEV_INFO("IGU Normal Mode\n"); 9785 9786 bnx2x_get_igu_cam_info(bp); 9787 9788 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9789 } 9790 9791 /* 9792 * set base FW non-default (fast path) status block id, this value is 9793 * used to initialize the fw_sb_id saved on the fp/queue structure to 9794 * determine the id used by the FW. 9795 */ 9796 if (CHIP_IS_E1x(bp)) 9797 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 9798 else /* 9799 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 9800 * the same queue are indicated on the same IGU SB). So we prefer 9801 * FW and IGU SBs to be the same value. 9802 */ 9803 bp->base_fw_ndsb = bp->igu_base_sb; 9804 9805 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 9806 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 9807 bp->igu_sb_cnt, bp->base_fw_ndsb); 9808 9809 /* 9810 * Initialize MF configuration 9811 */ 9812 9813 bp->mf_ov = 0; 9814 bp->mf_mode = 0; 9815 vn = BP_VN(bp); 9816 9817 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9818 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9819 bp->common.shmem2_base, SHMEM2_RD(bp, size), 9820 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 9821 9822 if (SHMEM2_HAS(bp, mf_cfg_addr)) 9823 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 9824 else 9825 bp->common.mf_cfg_base = bp->common.shmem_base + 9826 offsetof(struct shmem_region, func_mb) + 9827 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 9828 /* 9829 * get mf configuration: 9830 * 1. existence of MF configuration 9831 * 2. MAC address must be legal (check only upper bytes) 9832 * for Switch-Independent mode; 9833 * OVLAN must be legal for Switch-Dependent mode 9834 * 3. SF_MODE configures specific MF mode 9835 */ 9836 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9837 /* get mf configuration */ 9838 val = SHMEM_RD(bp, 9839 dev_info.shared_feature_config.config); 9840 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 9841 9842 switch (val) { 9843 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 9844 val = MF_CFG_RD(bp, func_mf_config[func]. 9845 mac_upper); 9846 /* check for legal mac (upper bytes)*/ 9847 if (val != 0xffff) { 9848 bp->mf_mode = MULTI_FUNCTION_SI; 9849 bp->mf_config[vn] = MF_CFG_RD(bp, 9850 func_mf_config[func].config); 9851 } else 9852 BNX2X_DEV_INFO("illegal MAC address for SI\n"); 9853 break; 9854 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9855 /* get OV configuration */ 9856 val = MF_CFG_RD(bp, 9857 func_mf_config[FUNC_0].e1hov_tag); 9858 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 9859 9860 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9861 bp->mf_mode = MULTI_FUNCTION_SD; 9862 bp->mf_config[vn] = MF_CFG_RD(bp, 9863 func_mf_config[func].config); 9864 } else 9865 BNX2X_DEV_INFO("illegal OV for SD\n"); 9866 break; 9867 default: 9868 /* Unknown configuration: reset mf_config */ 9869 bp->mf_config[vn] = 0; 9870 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); 9871 } 9872 } 9873 9874 BNX2X_DEV_INFO("%s function mode\n", 9875 IS_MF(bp) ? "multi" : "single"); 9876 9877 switch (bp->mf_mode) { 9878 case MULTI_FUNCTION_SD: 9879 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 9880 FUNC_MF_CFG_E1HOV_TAG_MASK; 9881 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 9882 bp->mf_ov = val; 9883 bp->path_has_ovlan = true; 9884 9885 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", 9886 func, bp->mf_ov, bp->mf_ov); 9887 } else { 9888 dev_err(&bp->pdev->dev, 9889 "No valid MF OV for func %d, aborting\n", 9890 func); 9891 return -EPERM; 9892 } 9893 break; 9894 case MULTI_FUNCTION_SI: 9895 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", 9896 func); 9897 break; 9898 default: 9899 if (vn) { 9900 dev_err(&bp->pdev->dev, 9901 "VN %d is in a single function mode, aborting\n", 9902 vn); 9903 return -EPERM; 9904 } 9905 break; 9906 } 9907 9908 /* check if other port on the path needs ovlan: 9909 * Since MF configuration is shared between ports 9910 * Possible mixed modes are only 9911 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 9912 */ 9913 if (CHIP_MODE_IS_4_PORT(bp) && 9914 !bp->path_has_ovlan && 9915 !IS_MF(bp) && 9916 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 9917 u8 other_port = !BP_PORT(bp); 9918 u8 other_func = BP_PATH(bp) + 2*other_port; 9919 val = MF_CFG_RD(bp, 9920 func_mf_config[other_func].e1hov_tag); 9921 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 9922 bp->path_has_ovlan = true; 9923 } 9924 } 9925 9926 /* adjust igu_sb_cnt to MF for E1x */ 9927 if (CHIP_IS_E1x(bp) && IS_MF(bp)) 9928 bp->igu_sb_cnt /= E1HVN_MAX; 9929 9930 /* port info */ 9931 bnx2x_get_port_hwinfo(bp); 9932 9933 /* Get MAC addresses */ 9934 bnx2x_get_mac_hwinfo(bp); 9935 9936 bnx2x_get_cnic_info(bp); 9937 9938 return rc; 9939 } 9940 9941 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp) 9942 { 9943 int cnt, i, block_end, rodi; 9944 char vpd_start[BNX2X_VPD_LEN+1]; 9945 char str_id_reg[VENDOR_ID_LEN+1]; 9946 char str_id_cap[VENDOR_ID_LEN+1]; 9947 char *vpd_data; 9948 char *vpd_extended_data = NULL; 9949 u8 len; 9950 9951 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); 9952 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 9953 9954 if (cnt < BNX2X_VPD_LEN) 9955 goto out_not_found; 9956 9957 /* VPD RO tag should be first tag after identifier string, hence 9958 * we should be able to find it in first BNX2X_VPD_LEN chars 9959 */ 9960 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, 9961 PCI_VPD_LRDT_RO_DATA); 9962 if (i < 0) 9963 goto out_not_found; 9964 9965 block_end = i + PCI_VPD_LRDT_TAG_SIZE + 9966 pci_vpd_lrdt_size(&vpd_start[i]); 9967 9968 i += PCI_VPD_LRDT_TAG_SIZE; 9969 9970 if (block_end > BNX2X_VPD_LEN) { 9971 vpd_extended_data = kmalloc(block_end, GFP_KERNEL); 9972 if (vpd_extended_data == NULL) 9973 goto out_not_found; 9974 9975 /* read rest of vpd image into vpd_extended_data */ 9976 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); 9977 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, 9978 block_end - BNX2X_VPD_LEN, 9979 vpd_extended_data + BNX2X_VPD_LEN); 9980 if (cnt < (block_end - BNX2X_VPD_LEN)) 9981 goto out_not_found; 9982 vpd_data = vpd_extended_data; 9983 } else 9984 vpd_data = vpd_start; 9985 9986 /* now vpd_data holds full vpd content in both cases */ 9987 9988 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 9989 PCI_VPD_RO_KEYWORD_MFR_ID); 9990 if (rodi < 0) 9991 goto out_not_found; 9992 9993 len = pci_vpd_info_field_size(&vpd_data[rodi]); 9994 9995 if (len != VENDOR_ID_LEN) 9996 goto out_not_found; 9997 9998 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 9999 10000 /* vendor specific info */ 10001 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 10002 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); 10003 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || 10004 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { 10005 10006 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, 10007 PCI_VPD_RO_KEYWORD_VENDOR0); 10008 if (rodi >= 0) { 10009 len = pci_vpd_info_field_size(&vpd_data[rodi]); 10010 10011 rodi += PCI_VPD_INFO_FLD_HDR_SIZE; 10012 10013 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { 10014 memcpy(bp->fw_ver, &vpd_data[rodi], len); 10015 bp->fw_ver[len] = ' '; 10016 } 10017 } 10018 kfree(vpd_extended_data); 10019 return; 10020 } 10021 out_not_found: 10022 kfree(vpd_extended_data); 10023 return; 10024 } 10025 10026 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp) 10027 { 10028 u32 flags = 0; 10029 10030 if (CHIP_REV_IS_FPGA(bp)) 10031 SET_FLAGS(flags, MODE_FPGA); 10032 else if (CHIP_REV_IS_EMUL(bp)) 10033 SET_FLAGS(flags, MODE_EMUL); 10034 else 10035 SET_FLAGS(flags, MODE_ASIC); 10036 10037 if (CHIP_MODE_IS_4_PORT(bp)) 10038 SET_FLAGS(flags, MODE_PORT4); 10039 else 10040 SET_FLAGS(flags, MODE_PORT2); 10041 10042 if (CHIP_IS_E2(bp)) 10043 SET_FLAGS(flags, MODE_E2); 10044 else if (CHIP_IS_E3(bp)) { 10045 SET_FLAGS(flags, MODE_E3); 10046 if (CHIP_REV(bp) == CHIP_REV_Ax) 10047 SET_FLAGS(flags, MODE_E3_A0); 10048 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 10049 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 10050 } 10051 10052 if (IS_MF(bp)) { 10053 SET_FLAGS(flags, MODE_MF); 10054 switch (bp->mf_mode) { 10055 case MULTI_FUNCTION_SD: 10056 SET_FLAGS(flags, MODE_MF_SD); 10057 break; 10058 case MULTI_FUNCTION_SI: 10059 SET_FLAGS(flags, MODE_MF_SI); 10060 break; 10061 } 10062 } else 10063 SET_FLAGS(flags, MODE_SF); 10064 10065 #if defined(__LITTLE_ENDIAN) 10066 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 10067 #else /*(__BIG_ENDIAN)*/ 10068 SET_FLAGS(flags, MODE_BIG_ENDIAN); 10069 #endif 10070 INIT_MODE_FLAGS(bp) = flags; 10071 } 10072 10073 static int __devinit bnx2x_init_bp(struct bnx2x *bp) 10074 { 10075 int func; 10076 int rc; 10077 10078 mutex_init(&bp->port.phy_mutex); 10079 mutex_init(&bp->fw_mb_mutex); 10080 spin_lock_init(&bp->stats_lock); 10081 #ifdef BCM_CNIC 10082 mutex_init(&bp->cnic_mutex); 10083 #endif 10084 10085 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 10086 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 10087 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 10088 rc = bnx2x_get_hwinfo(bp); 10089 if (rc) 10090 return rc; 10091 10092 bnx2x_set_modes_bitmap(bp); 10093 10094 rc = bnx2x_alloc_mem_bp(bp); 10095 if (rc) 10096 return rc; 10097 10098 bnx2x_read_fwinfo(bp); 10099 10100 func = BP_FUNC(bp); 10101 10102 /* need to reset chip if undi was active */ 10103 if (!BP_NOMCP(bp)) 10104 bnx2x_undi_unload(bp); 10105 10106 if (CHIP_REV_IS_FPGA(bp)) 10107 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10108 10109 if (BP_NOMCP(bp) && (func == 0)) 10110 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); 10111 10112 bp->multi_mode = multi_mode; 10113 10114 bp->disable_tpa = disable_tpa; 10115 10116 #ifdef BCM_CNIC 10117 bp->disable_tpa |= IS_MF_STORAGE_SD(bp); 10118 #endif 10119 10120 /* Set TPA flags */ 10121 if (bp->disable_tpa) { 10122 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10123 bp->dev->features &= ~NETIF_F_LRO; 10124 } else { 10125 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); 10126 bp->dev->features |= NETIF_F_LRO; 10127 } 10128 10129 if (CHIP_IS_E1(bp)) 10130 bp->dropless_fc = 0; 10131 else 10132 bp->dropless_fc = dropless_fc; 10133 10134 bp->mrrs = mrrs; 10135 10136 bp->tx_ring_size = MAX_TX_AVAIL; 10137 10138 /* make sure that the numbers are in the right granularity */ 10139 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 10140 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 10141 10142 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 10143 10144 init_timer(&bp->timer); 10145 bp->timer.expires = jiffies + bp->current_interval; 10146 bp->timer.data = (unsigned long) bp; 10147 bp->timer.function = bnx2x_timer; 10148 10149 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 10150 bnx2x_dcbx_init_params(bp); 10151 10152 #ifdef BCM_CNIC 10153 if (CHIP_IS_E1x(bp)) 10154 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 10155 else 10156 bp->cnic_base_cl_id = FP_SB_MAX_E2; 10157 #endif 10158 10159 /* multiple tx priority */ 10160 if (CHIP_IS_E1x(bp)) 10161 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 10162 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 10163 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 10164 if (CHIP_IS_E3B0(bp)) 10165 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 10166 10167 bp->gro_check = bnx2x_need_gro_check(bp->dev->mtu); 10168 10169 return rc; 10170 } 10171 10172 10173 /**************************************************************************** 10174 * General service functions 10175 ****************************************************************************/ 10176 10177 /* 10178 * net_device service functions 10179 */ 10180 10181 /* called with rtnl_lock */ 10182 static int bnx2x_open(struct net_device *dev) 10183 { 10184 struct bnx2x *bp = netdev_priv(dev); 10185 bool global = false; 10186 int other_engine = BP_PATH(bp) ? 0 : 1; 10187 bool other_load_status, load_status; 10188 10189 bp->stats_init = true; 10190 10191 netif_carrier_off(dev); 10192 10193 bnx2x_set_power_state(bp, PCI_D0); 10194 10195 other_load_status = bnx2x_get_load_status(bp, other_engine); 10196 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 10197 10198 /* 10199 * If parity had happen during the unload, then attentions 10200 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 10201 * want the first function loaded on the current engine to 10202 * complete the recovery. 10203 */ 10204 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 10205 bnx2x_chk_parity_attn(bp, &global, true)) 10206 do { 10207 /* 10208 * If there are attentions and they are in a global 10209 * blocks, set the GLOBAL_RESET bit regardless whether 10210 * it will be this function that will complete the 10211 * recovery or not. 10212 */ 10213 if (global) 10214 bnx2x_set_reset_global(bp); 10215 10216 /* 10217 * Only the first function on the current engine should 10218 * try to recover in open. In case of attentions in 10219 * global blocks only the first in the chip should try 10220 * to recover. 10221 */ 10222 if ((!load_status && 10223 (!global || !other_load_status)) && 10224 bnx2x_trylock_leader_lock(bp) && 10225 !bnx2x_leader_reset(bp)) { 10226 netdev_info(bp->dev, "Recovered in open\n"); 10227 break; 10228 } 10229 10230 /* recovery has failed... */ 10231 bnx2x_set_power_state(bp, PCI_D3hot); 10232 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10233 10234 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" 10235 "If you still see this message after a few retries then power cycle is required.\n"); 10236 10237 return -EAGAIN; 10238 } while (0); 10239 10240 bp->recovery_state = BNX2X_RECOVERY_DONE; 10241 return bnx2x_nic_load(bp, LOAD_OPEN); 10242 } 10243 10244 /* called with rtnl_lock */ 10245 static int bnx2x_close(struct net_device *dev) 10246 { 10247 struct bnx2x *bp = netdev_priv(dev); 10248 10249 /* Unload the driver, release IRQs */ 10250 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 10251 10252 /* Power off */ 10253 bnx2x_set_power_state(bp, PCI_D3hot); 10254 10255 return 0; 10256 } 10257 10258 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 10259 struct bnx2x_mcast_ramrod_params *p) 10260 { 10261 int mc_count = netdev_mc_count(bp->dev); 10262 struct bnx2x_mcast_list_elem *mc_mac = 10263 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); 10264 struct netdev_hw_addr *ha; 10265 10266 if (!mc_mac) 10267 return -ENOMEM; 10268 10269 INIT_LIST_HEAD(&p->mcast_list); 10270 10271 netdev_for_each_mc_addr(ha, bp->dev) { 10272 mc_mac->mac = bnx2x_mc_addr(ha); 10273 list_add_tail(&mc_mac->link, &p->mcast_list); 10274 mc_mac++; 10275 } 10276 10277 p->mcast_list_len = mc_count; 10278 10279 return 0; 10280 } 10281 10282 static inline void bnx2x_free_mcast_macs_list( 10283 struct bnx2x_mcast_ramrod_params *p) 10284 { 10285 struct bnx2x_mcast_list_elem *mc_mac = 10286 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, 10287 link); 10288 10289 WARN_ON(!mc_mac); 10290 kfree(mc_mac); 10291 } 10292 10293 /** 10294 * bnx2x_set_uc_list - configure a new unicast MACs list. 10295 * 10296 * @bp: driver handle 10297 * 10298 * We will use zero (0) as a MAC type for these MACs. 10299 */ 10300 static inline int bnx2x_set_uc_list(struct bnx2x *bp) 10301 { 10302 int rc; 10303 struct net_device *dev = bp->dev; 10304 struct netdev_hw_addr *ha; 10305 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj; 10306 unsigned long ramrod_flags = 0; 10307 10308 /* First schedule a cleanup up of old configuration */ 10309 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 10310 if (rc < 0) { 10311 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 10312 return rc; 10313 } 10314 10315 netdev_for_each_uc_addr(ha, dev) { 10316 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 10317 BNX2X_UC_LIST_MAC, &ramrod_flags); 10318 if (rc < 0) { 10319 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 10320 rc); 10321 return rc; 10322 } 10323 } 10324 10325 /* Execute the pending commands */ 10326 __set_bit(RAMROD_CONT, &ramrod_flags); 10327 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 10328 BNX2X_UC_LIST_MAC, &ramrod_flags); 10329 } 10330 10331 static inline int bnx2x_set_mc_list(struct bnx2x *bp) 10332 { 10333 struct net_device *dev = bp->dev; 10334 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 10335 int rc = 0; 10336 10337 rparam.mcast_obj = &bp->mcast_obj; 10338 10339 /* first, clear all configured multicast MACs */ 10340 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10341 if (rc < 0) { 10342 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); 10343 return rc; 10344 } 10345 10346 /* then, configure a new MACs list */ 10347 if (netdev_mc_count(dev)) { 10348 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10349 if (rc) { 10350 BNX2X_ERR("Failed to create multicast MACs list: %d\n", 10351 rc); 10352 return rc; 10353 } 10354 10355 /* Now add the new MACs */ 10356 rc = bnx2x_config_mcast(bp, &rparam, 10357 BNX2X_MCAST_CMD_ADD); 10358 if (rc < 0) 10359 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 10360 rc); 10361 10362 bnx2x_free_mcast_macs_list(&rparam); 10363 } 10364 10365 return rc; 10366 } 10367 10368 10369 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 10370 void bnx2x_set_rx_mode(struct net_device *dev) 10371 { 10372 struct bnx2x *bp = netdev_priv(dev); 10373 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 10374 10375 if (bp->state != BNX2X_STATE_OPEN) { 10376 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 10377 return; 10378 } 10379 10380 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 10381 10382 if (dev->flags & IFF_PROMISC) 10383 rx_mode = BNX2X_RX_MODE_PROMISC; 10384 else if ((dev->flags & IFF_ALLMULTI) || 10385 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && 10386 CHIP_IS_E1(bp))) 10387 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10388 else { 10389 /* some multicasts */ 10390 if (bnx2x_set_mc_list(bp) < 0) 10391 rx_mode = BNX2X_RX_MODE_ALLMULTI; 10392 10393 if (bnx2x_set_uc_list(bp) < 0) 10394 rx_mode = BNX2X_RX_MODE_PROMISC; 10395 } 10396 10397 bp->rx_mode = rx_mode; 10398 #ifdef BCM_CNIC 10399 /* handle ISCSI SD mode */ 10400 if (IS_MF_ISCSI_SD(bp)) 10401 bp->rx_mode = BNX2X_RX_MODE_NONE; 10402 #endif 10403 10404 /* Schedule the rx_mode command */ 10405 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 10406 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 10407 return; 10408 } 10409 10410 bnx2x_set_storm_rx_mode(bp); 10411 } 10412 10413 /* called with rtnl_lock */ 10414 static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 10415 int devad, u16 addr) 10416 { 10417 struct bnx2x *bp = netdev_priv(netdev); 10418 u16 value; 10419 int rc; 10420 10421 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 10422 prtad, devad, addr); 10423 10424 /* The HW expects different devad if CL22 is used */ 10425 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10426 10427 bnx2x_acquire_phy_lock(bp); 10428 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 10429 bnx2x_release_phy_lock(bp); 10430 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 10431 10432 if (!rc) 10433 rc = value; 10434 return rc; 10435 } 10436 10437 /* called with rtnl_lock */ 10438 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 10439 u16 addr, u16 value) 10440 { 10441 struct bnx2x *bp = netdev_priv(netdev); 10442 int rc; 10443 10444 DP(NETIF_MSG_LINK, 10445 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", 10446 prtad, devad, addr, value); 10447 10448 /* The HW expects different devad if CL22 is used */ 10449 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10450 10451 bnx2x_acquire_phy_lock(bp); 10452 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 10453 bnx2x_release_phy_lock(bp); 10454 return rc; 10455 } 10456 10457 /* called with rtnl_lock */ 10458 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 10459 { 10460 struct bnx2x *bp = netdev_priv(dev); 10461 struct mii_ioctl_data *mdio = if_mii(ifr); 10462 10463 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 10464 mdio->phy_id, mdio->reg_num, mdio->val_in); 10465 10466 if (!netif_running(dev)) 10467 return -EAGAIN; 10468 10469 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 10470 } 10471 10472 #ifdef CONFIG_NET_POLL_CONTROLLER 10473 static void poll_bnx2x(struct net_device *dev) 10474 { 10475 struct bnx2x *bp = netdev_priv(dev); 10476 10477 disable_irq(bp->pdev->irq); 10478 bnx2x_interrupt(bp->pdev->irq, dev); 10479 enable_irq(bp->pdev->irq); 10480 } 10481 #endif 10482 10483 static int bnx2x_validate_addr(struct net_device *dev) 10484 { 10485 struct bnx2x *bp = netdev_priv(dev); 10486 10487 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { 10488 BNX2X_ERR("Non-valid Ethernet address\n"); 10489 return -EADDRNOTAVAIL; 10490 } 10491 return 0; 10492 } 10493 10494 static const struct net_device_ops bnx2x_netdev_ops = { 10495 .ndo_open = bnx2x_open, 10496 .ndo_stop = bnx2x_close, 10497 .ndo_start_xmit = bnx2x_start_xmit, 10498 .ndo_select_queue = bnx2x_select_queue, 10499 .ndo_set_rx_mode = bnx2x_set_rx_mode, 10500 .ndo_set_mac_address = bnx2x_change_mac_addr, 10501 .ndo_validate_addr = bnx2x_validate_addr, 10502 .ndo_do_ioctl = bnx2x_ioctl, 10503 .ndo_change_mtu = bnx2x_change_mtu, 10504 .ndo_fix_features = bnx2x_fix_features, 10505 .ndo_set_features = bnx2x_set_features, 10506 .ndo_tx_timeout = bnx2x_tx_timeout, 10507 #ifdef CONFIG_NET_POLL_CONTROLLER 10508 .ndo_poll_controller = poll_bnx2x, 10509 #endif 10510 .ndo_setup_tc = bnx2x_setup_tc, 10511 10512 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 10513 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 10514 #endif 10515 }; 10516 10517 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp) 10518 { 10519 struct device *dev = &bp->pdev->dev; 10520 10521 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10522 bp->flags |= USING_DAC_FLAG; 10523 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10524 dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); 10525 return -EIO; 10526 } 10527 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10528 dev_err(dev, "System does not support DMA, aborting\n"); 10529 return -EIO; 10530 } 10531 10532 return 0; 10533 } 10534 10535 static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 10536 struct net_device *dev, 10537 unsigned long board_type) 10538 { 10539 struct bnx2x *bp; 10540 int rc; 10541 u32 pci_cfg_dword; 10542 bool chip_is_e1x = (board_type == BCM57710 || 10543 board_type == BCM57711 || 10544 board_type == BCM57711E); 10545 10546 SET_NETDEV_DEV(dev, &pdev->dev); 10547 bp = netdev_priv(dev); 10548 10549 bp->dev = dev; 10550 bp->pdev = pdev; 10551 bp->flags = 0; 10552 10553 rc = pci_enable_device(pdev); 10554 if (rc) { 10555 dev_err(&bp->pdev->dev, 10556 "Cannot enable PCI device, aborting\n"); 10557 goto err_out; 10558 } 10559 10560 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 10561 dev_err(&bp->pdev->dev, 10562 "Cannot find PCI device base address, aborting\n"); 10563 rc = -ENODEV; 10564 goto err_out_disable; 10565 } 10566 10567 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 10568 dev_err(&bp->pdev->dev, "Cannot find second PCI device" 10569 " base address, aborting\n"); 10570 rc = -ENODEV; 10571 goto err_out_disable; 10572 } 10573 10574 if (atomic_read(&pdev->enable_cnt) == 1) { 10575 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 10576 if (rc) { 10577 dev_err(&bp->pdev->dev, 10578 "Cannot obtain PCI resources, aborting\n"); 10579 goto err_out_disable; 10580 } 10581 10582 pci_set_master(pdev); 10583 pci_save_state(pdev); 10584 } 10585 10586 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 10587 if (bp->pm_cap == 0) { 10588 dev_err(&bp->pdev->dev, 10589 "Cannot find power management capability, aborting\n"); 10590 rc = -EIO; 10591 goto err_out_release; 10592 } 10593 10594 if (!pci_is_pcie(pdev)) { 10595 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10596 rc = -EIO; 10597 goto err_out_release; 10598 } 10599 10600 rc = bnx2x_set_coherency_mask(bp); 10601 if (rc) 10602 goto err_out_release; 10603 10604 dev->mem_start = pci_resource_start(pdev, 0); 10605 dev->base_addr = dev->mem_start; 10606 dev->mem_end = pci_resource_end(pdev, 0); 10607 10608 dev->irq = pdev->irq; 10609 10610 bp->regview = pci_ioremap_bar(pdev, 0); 10611 if (!bp->regview) { 10612 dev_err(&bp->pdev->dev, 10613 "Cannot map register space, aborting\n"); 10614 rc = -ENOMEM; 10615 goto err_out_release; 10616 } 10617 10618 /* In E1/E1H use pci device function given by kernel. 10619 * In E2/E3 read physical function from ME register since these chips 10620 * support Physical Device Assignment where kernel BDF maybe arbitrary 10621 * (depending on hypervisor). 10622 */ 10623 if (chip_is_e1x) 10624 bp->pf_num = PCI_FUNC(pdev->devfn); 10625 else {/* chip is E2/3*/ 10626 pci_read_config_dword(bp->pdev, 10627 PCICFG_ME_REGISTER, &pci_cfg_dword); 10628 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10629 ME_REG_ABS_PF_NUM_SHIFT); 10630 } 10631 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); 10632 10633 bnx2x_set_power_state(bp, PCI_D0); 10634 10635 /* clean indirect addresses */ 10636 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 10637 PCICFG_VENDOR_ID_OFFSET); 10638 /* 10639 * Clean the following indirect addresses for all functions since it 10640 * is not used by the driver. 10641 */ 10642 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 10643 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 10644 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 10645 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 10646 10647 if (chip_is_e1x) { 10648 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 10649 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 10650 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 10651 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 10652 } 10653 10654 /* 10655 * Enable internal target-read (in case we are probed after PF FLR). 10656 * Must be done prior to any BAR read access. Only for 57712 and up 10657 */ 10658 if (!chip_is_e1x) 10659 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 10660 10661 /* Reset the load counter */ 10662 bnx2x_clear_load_status(bp); 10663 10664 dev->watchdog_timeo = TX_TIMEOUT; 10665 10666 dev->netdev_ops = &bnx2x_netdev_ops; 10667 bnx2x_set_ethtool_ops(dev); 10668 10669 dev->priv_flags |= IFF_UNICAST_FLT; 10670 10671 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10672 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 10673 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | 10674 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; 10675 10676 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 10677 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 10678 10679 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; 10680 if (bp->flags & USING_DAC_FLAG) 10681 dev->features |= NETIF_F_HIGHDMA; 10682 10683 /* Add Loopback capability to the device */ 10684 dev->hw_features |= NETIF_F_LOOPBACK; 10685 10686 #ifdef BCM_DCBNL 10687 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 10688 #endif 10689 10690 /* get_port_hwinfo() will set prtad and mmds properly */ 10691 bp->mdio.prtad = MDIO_PRTAD_NONE; 10692 bp->mdio.mmds = 0; 10693 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10694 bp->mdio.dev = dev; 10695 bp->mdio.mdio_read = bnx2x_mdio_read; 10696 bp->mdio.mdio_write = bnx2x_mdio_write; 10697 10698 return 0; 10699 10700 err_out_release: 10701 if (atomic_read(&pdev->enable_cnt) == 1) 10702 pci_release_regions(pdev); 10703 10704 err_out_disable: 10705 pci_disable_device(pdev); 10706 pci_set_drvdata(pdev, NULL); 10707 10708 err_out: 10709 return rc; 10710 } 10711 10712 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp, 10713 int *width, int *speed) 10714 { 10715 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); 10716 10717 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; 10718 10719 /* return value of 1=2.5GHz 2=5GHz */ 10720 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 10721 } 10722 10723 static int bnx2x_check_firmware(struct bnx2x *bp) 10724 { 10725 const struct firmware *firmware = bp->firmware; 10726 struct bnx2x_fw_file_hdr *fw_hdr; 10727 struct bnx2x_fw_file_section *sections; 10728 u32 offset, len, num_ops; 10729 u16 *ops_offsets; 10730 int i; 10731 const u8 *fw_ver; 10732 10733 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { 10734 BNX2X_ERR("Wrong FW size\n"); 10735 return -EINVAL; 10736 } 10737 10738 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10739 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10740 10741 /* Make sure none of the offsets and sizes make us read beyond 10742 * the end of the firmware data */ 10743 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 10744 offset = be32_to_cpu(sections[i].offset); 10745 len = be32_to_cpu(sections[i].len); 10746 if (offset + len > firmware->size) { 10747 BNX2X_ERR("Section %d length is out of bounds\n", i); 10748 return -EINVAL; 10749 } 10750 } 10751 10752 /* Likewise for the init_ops offsets */ 10753 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 10754 ops_offsets = (u16 *)(firmware->data + offset); 10755 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 10756 10757 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10758 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10759 BNX2X_ERR("Section offset %d is out of bounds\n", i); 10760 return -EINVAL; 10761 } 10762 } 10763 10764 /* Check FW version */ 10765 offset = be32_to_cpu(fw_hdr->fw_version.offset); 10766 fw_ver = firmware->data + offset; 10767 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || 10768 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10769 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10770 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10771 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10772 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], 10773 BCM_5710_FW_MAJOR_VERSION, 10774 BCM_5710_FW_MINOR_VERSION, 10775 BCM_5710_FW_REVISION_VERSION, 10776 BCM_5710_FW_ENGINEERING_VERSION); 10777 return -EINVAL; 10778 } 10779 10780 return 0; 10781 } 10782 10783 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10784 { 10785 const __be32 *source = (const __be32 *)_source; 10786 u32 *target = (u32 *)_target; 10787 u32 i; 10788 10789 for (i = 0; i < n/4; i++) 10790 target[i] = be32_to_cpu(source[i]); 10791 } 10792 10793 /* 10794 Ops array is stored in the following format: 10795 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 10796 */ 10797 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 10798 { 10799 const __be32 *source = (const __be32 *)_source; 10800 struct raw_op *target = (struct raw_op *)_target; 10801 u32 i, j, tmp; 10802 10803 for (i = 0, j = 0; i < n/8; i++, j += 2) { 10804 tmp = be32_to_cpu(source[j]); 10805 target[i].op = (tmp >> 24) & 0xff; 10806 target[i].offset = tmp & 0xffffff; 10807 target[i].raw_data = be32_to_cpu(source[j + 1]); 10808 } 10809 } 10810 10811 /** 10812 * IRO array is stored in the following format: 10813 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 10814 */ 10815 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 10816 { 10817 const __be32 *source = (const __be32 *)_source; 10818 struct iro *target = (struct iro *)_target; 10819 u32 i, j, tmp; 10820 10821 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 10822 target[i].base = be32_to_cpu(source[j]); 10823 j++; 10824 tmp = be32_to_cpu(source[j]); 10825 target[i].m1 = (tmp >> 16) & 0xffff; 10826 target[i].m2 = tmp & 0xffff; 10827 j++; 10828 tmp = be32_to_cpu(source[j]); 10829 target[i].m3 = (tmp >> 16) & 0xffff; 10830 target[i].size = tmp & 0xffff; 10831 j++; 10832 } 10833 } 10834 10835 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 10836 { 10837 const __be16 *source = (const __be16 *)_source; 10838 u16 *target = (u16 *)_target; 10839 u32 i; 10840 10841 for (i = 0; i < n/2; i++) 10842 target[i] = be16_to_cpu(source[i]); 10843 } 10844 10845 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 10846 do { \ 10847 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 10848 bp->arr = kmalloc(len, GFP_KERNEL); \ 10849 if (!bp->arr) \ 10850 goto lbl; \ 10851 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 10852 (u8 *)bp->arr, len); \ 10853 } while (0) 10854 10855 static int bnx2x_init_firmware(struct bnx2x *bp) 10856 { 10857 const char *fw_file_name; 10858 struct bnx2x_fw_file_hdr *fw_hdr; 10859 int rc; 10860 10861 if (bp->firmware) 10862 return 0; 10863 10864 if (CHIP_IS_E1(bp)) 10865 fw_file_name = FW_FILE_NAME_E1; 10866 else if (CHIP_IS_E1H(bp)) 10867 fw_file_name = FW_FILE_NAME_E1H; 10868 else if (!CHIP_IS_E1x(bp)) 10869 fw_file_name = FW_FILE_NAME_E2; 10870 else { 10871 BNX2X_ERR("Unsupported chip revision\n"); 10872 return -EINVAL; 10873 } 10874 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 10875 10876 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 10877 if (rc) { 10878 BNX2X_ERR("Can't load firmware file %s\n", 10879 fw_file_name); 10880 goto request_firmware_exit; 10881 } 10882 10883 rc = bnx2x_check_firmware(bp); 10884 if (rc) { 10885 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 10886 goto request_firmware_exit; 10887 } 10888 10889 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 10890 10891 /* Initialize the pointers to the init arrays */ 10892 /* Blob */ 10893 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 10894 10895 /* Opcodes */ 10896 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 10897 10898 /* Offsets */ 10899 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 10900 be16_to_cpu_n); 10901 10902 /* STORMs firmware */ 10903 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10904 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 10905 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 10906 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 10907 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10908 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 10909 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 10910 be32_to_cpu(fw_hdr->usem_pram_data.offset); 10911 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10912 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 10913 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 10914 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 10915 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 10916 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 10917 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 10918 be32_to_cpu(fw_hdr->csem_pram_data.offset); 10919 /* IRO */ 10920 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 10921 10922 return 0; 10923 10924 iro_alloc_err: 10925 kfree(bp->init_ops_offsets); 10926 init_offsets_alloc_err: 10927 kfree(bp->init_ops); 10928 init_ops_alloc_err: 10929 kfree(bp->init_data); 10930 request_firmware_exit: 10931 release_firmware(bp->firmware); 10932 bp->firmware = NULL; 10933 10934 return rc; 10935 } 10936 10937 static void bnx2x_release_firmware(struct bnx2x *bp) 10938 { 10939 kfree(bp->init_ops_offsets); 10940 kfree(bp->init_ops); 10941 kfree(bp->init_data); 10942 release_firmware(bp->firmware); 10943 bp->firmware = NULL; 10944 } 10945 10946 10947 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 10948 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 10949 .init_hw_cmn = bnx2x_init_hw_common, 10950 .init_hw_port = bnx2x_init_hw_port, 10951 .init_hw_func = bnx2x_init_hw_func, 10952 10953 .reset_hw_cmn = bnx2x_reset_common, 10954 .reset_hw_port = bnx2x_reset_port, 10955 .reset_hw_func = bnx2x_reset_func, 10956 10957 .gunzip_init = bnx2x_gunzip_init, 10958 .gunzip_end = bnx2x_gunzip_end, 10959 10960 .init_fw = bnx2x_init_firmware, 10961 .release_fw = bnx2x_release_firmware, 10962 }; 10963 10964 void bnx2x__init_func_obj(struct bnx2x *bp) 10965 { 10966 /* Prepare DMAE related driver resources */ 10967 bnx2x_setup_dmae(bp); 10968 10969 bnx2x_init_func_obj(bp, &bp->func_obj, 10970 bnx2x_sp(bp, func_rdata), 10971 bnx2x_sp_mapping(bp, func_rdata), 10972 &bnx2x_func_sp_drv); 10973 } 10974 10975 /* must be called after sriov-enable */ 10976 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp) 10977 { 10978 int cid_count = BNX2X_L2_CID_COUNT(bp); 10979 10980 #ifdef BCM_CNIC 10981 cid_count += CNIC_CID_MAX; 10982 #endif 10983 return roundup(cid_count, QM_CID_ROUND); 10984 } 10985 10986 /** 10987 * bnx2x_get_num_none_def_sbs - return the number of none default SBs 10988 * 10989 * @dev: pci device 10990 * 10991 */ 10992 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev) 10993 { 10994 int pos; 10995 u16 control; 10996 10997 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 10998 10999 /* 11000 * If MSI-X is not supported - return number of SBs needed to support 11001 * one fast path queue: one FP queue + SB for CNIC 11002 */ 11003 if (!pos) 11004 return 1 + CNIC_PRESENT; 11005 11006 /* 11007 * The value in the PCI configuration space is the index of the last 11008 * entry, namely one less than the actual size of the table, which is 11009 * exactly what we want to return from this function: number of all SBs 11010 * without the default SB. 11011 */ 11012 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 11013 return control & PCI_MSIX_FLAGS_QSIZE; 11014 } 11015 11016 static int __devinit bnx2x_init_one(struct pci_dev *pdev, 11017 const struct pci_device_id *ent) 11018 { 11019 struct net_device *dev = NULL; 11020 struct bnx2x *bp; 11021 int pcie_width, pcie_speed; 11022 int rc, max_non_def_sbs; 11023 int rx_count, tx_count, rss_count; 11024 /* 11025 * An estimated maximum supported CoS number according to the chip 11026 * version. 11027 * We will try to roughly estimate the maximum number of CoSes this chip 11028 * may support in order to minimize the memory allocated for Tx 11029 * netdev_queue's. This number will be accurately calculated during the 11030 * initialization of bp->max_cos based on the chip versions AND chip 11031 * revision in the bnx2x_init_bp(). 11032 */ 11033 u8 max_cos_est = 0; 11034 11035 switch (ent->driver_data) { 11036 case BCM57710: 11037 case BCM57711: 11038 case BCM57711E: 11039 max_cos_est = BNX2X_MULTI_TX_COS_E1X; 11040 break; 11041 11042 case BCM57712: 11043 case BCM57712_MF: 11044 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0; 11045 break; 11046 11047 case BCM57800: 11048 case BCM57800_MF: 11049 case BCM57810: 11050 case BCM57810_MF: 11051 case BCM57840: 11052 case BCM57840_MF: 11053 max_cos_est = BNX2X_MULTI_TX_COS_E3B0; 11054 break; 11055 11056 default: 11057 pr_err("Unknown board_type (%ld), aborting\n", 11058 ent->driver_data); 11059 return -ENODEV; 11060 } 11061 11062 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev); 11063 11064 /* !!! FIXME !!! 11065 * Do not allow the maximum SB count to grow above 16 11066 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48. 11067 * We will use the FP_SB_MAX_E1x macro for this matter. 11068 */ 11069 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs); 11070 11071 WARN_ON(!max_non_def_sbs); 11072 11073 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 11074 rss_count = max_non_def_sbs - CNIC_PRESENT; 11075 11076 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 11077 rx_count = rss_count + FCOE_PRESENT; 11078 11079 /* 11080 * Maximum number of netdev Tx queues: 11081 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 11082 */ 11083 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT; 11084 11085 /* dev zeroed in init_etherdev */ 11086 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 11087 if (!dev) 11088 return -ENOMEM; 11089 11090 bp = netdev_priv(dev); 11091 11092 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", 11093 tx_count, rx_count); 11094 11095 bp->igu_sb_cnt = max_non_def_sbs; 11096 bp->msg_enable = debug; 11097 pci_set_drvdata(pdev, dev); 11098 11099 rc = bnx2x_init_dev(pdev, dev, ent->driver_data); 11100 if (rc < 0) { 11101 free_netdev(dev); 11102 return rc; 11103 } 11104 11105 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs); 11106 11107 rc = bnx2x_init_bp(bp); 11108 if (rc) 11109 goto init_one_exit; 11110 11111 /* 11112 * Map doorbels here as we need the real value of bp->max_cos which 11113 * is initialized in bnx2x_init_bp(). 11114 */ 11115 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 11116 min_t(u64, BNX2X_DB_SIZE(bp), 11117 pci_resource_len(pdev, 2))); 11118 if (!bp->doorbells) { 11119 dev_err(&bp->pdev->dev, 11120 "Cannot map doorbell space, aborting\n"); 11121 rc = -ENOMEM; 11122 goto init_one_exit; 11123 } 11124 11125 /* calc qm_cid_count */ 11126 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 11127 11128 #ifdef BCM_CNIC 11129 /* disable FCOE L2 queue for E1x */ 11130 if (CHIP_IS_E1x(bp)) 11131 bp->flags |= NO_FCOE_FLAG; 11132 11133 #endif 11134 11135 /* Configure interrupt mode: try to enable MSI-X/MSI if 11136 * needed, set bp->num_queues appropriately. 11137 */ 11138 bnx2x_set_int_mode(bp); 11139 11140 /* Add all NAPI objects */ 11141 bnx2x_add_all_napi(bp); 11142 11143 rc = register_netdev(dev); 11144 if (rc) { 11145 dev_err(&pdev->dev, "Cannot register net device\n"); 11146 goto init_one_exit; 11147 } 11148 11149 #ifdef BCM_CNIC 11150 if (!NO_FCOE(bp)) { 11151 /* Add storage MAC address */ 11152 rtnl_lock(); 11153 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11154 rtnl_unlock(); 11155 } 11156 #endif 11157 11158 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11159 11160 BNX2X_DEV_INFO( 11161 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11162 board_info[ent->driver_data].name, 11163 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11164 pcie_width, 11165 ((!CHIP_IS_E2(bp) && pcie_speed == 2) || 11166 (CHIP_IS_E2(bp) && pcie_speed == 1)) ? 11167 "5GHz (Gen2)" : "2.5GHz", 11168 dev->base_addr, bp->pdev->irq, dev->dev_addr); 11169 11170 return 0; 11171 11172 init_one_exit: 11173 if (bp->regview) 11174 iounmap(bp->regview); 11175 11176 if (bp->doorbells) 11177 iounmap(bp->doorbells); 11178 11179 free_netdev(dev); 11180 11181 if (atomic_read(&pdev->enable_cnt) == 1) 11182 pci_release_regions(pdev); 11183 11184 pci_disable_device(pdev); 11185 pci_set_drvdata(pdev, NULL); 11186 11187 return rc; 11188 } 11189 11190 static void __devexit bnx2x_remove_one(struct pci_dev *pdev) 11191 { 11192 struct net_device *dev = pci_get_drvdata(pdev); 11193 struct bnx2x *bp; 11194 11195 if (!dev) { 11196 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 11197 return; 11198 } 11199 bp = netdev_priv(dev); 11200 11201 #ifdef BCM_CNIC 11202 /* Delete storage MAC address */ 11203 if (!NO_FCOE(bp)) { 11204 rtnl_lock(); 11205 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 11206 rtnl_unlock(); 11207 } 11208 #endif 11209 11210 #ifdef BCM_DCBNL 11211 /* Delete app tlvs from dcbnl */ 11212 bnx2x_dcbnl_update_applist(bp, true); 11213 #endif 11214 11215 unregister_netdev(dev); 11216 11217 /* Delete all NAPI objects */ 11218 bnx2x_del_all_napi(bp); 11219 11220 /* Power on: we can't let PCI layer write to us while we are in D3 */ 11221 bnx2x_set_power_state(bp, PCI_D0); 11222 11223 /* Disable MSI/MSI-X */ 11224 bnx2x_disable_msi(bp); 11225 11226 /* Power off */ 11227 bnx2x_set_power_state(bp, PCI_D3hot); 11228 11229 /* Make sure RESET task is not scheduled before continuing */ 11230 cancel_delayed_work_sync(&bp->sp_rtnl_task); 11231 11232 if (bp->regview) 11233 iounmap(bp->regview); 11234 11235 if (bp->doorbells) 11236 iounmap(bp->doorbells); 11237 11238 bnx2x_release_firmware(bp); 11239 11240 bnx2x_free_mem_bp(bp); 11241 11242 free_netdev(dev); 11243 11244 if (atomic_read(&pdev->enable_cnt) == 1) 11245 pci_release_regions(pdev); 11246 11247 pci_disable_device(pdev); 11248 pci_set_drvdata(pdev, NULL); 11249 } 11250 11251 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 11252 { 11253 int i; 11254 11255 bp->state = BNX2X_STATE_ERROR; 11256 11257 bp->rx_mode = BNX2X_RX_MODE_NONE; 11258 11259 #ifdef BCM_CNIC 11260 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 11261 #endif 11262 /* Stop Tx */ 11263 bnx2x_tx_disable(bp); 11264 11265 bnx2x_netif_stop(bp, 0); 11266 11267 del_timer_sync(&bp->timer); 11268 11269 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11270 11271 /* Release IRQs */ 11272 bnx2x_free_irq(bp); 11273 11274 /* Free SKBs, SGEs, TPA pool and driver internals */ 11275 bnx2x_free_skbs(bp); 11276 11277 for_each_rx_queue(bp, i) 11278 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 11279 11280 bnx2x_free_mem(bp); 11281 11282 bp->state = BNX2X_STATE_CLOSED; 11283 11284 netif_carrier_off(bp->dev); 11285 11286 return 0; 11287 } 11288 11289 static void bnx2x_eeh_recover(struct bnx2x *bp) 11290 { 11291 u32 val; 11292 11293 mutex_init(&bp->port.phy_mutex); 11294 11295 11296 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 11297 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11298 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) 11299 BNX2X_ERR("BAD MCP validity signature\n"); 11300 } 11301 11302 /** 11303 * bnx2x_io_error_detected - called when PCI error is detected 11304 * @pdev: Pointer to PCI device 11305 * @state: The current pci connection state 11306 * 11307 * This function is called after a PCI bus error affecting 11308 * this device has been detected. 11309 */ 11310 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 11311 pci_channel_state_t state) 11312 { 11313 struct net_device *dev = pci_get_drvdata(pdev); 11314 struct bnx2x *bp = netdev_priv(dev); 11315 11316 rtnl_lock(); 11317 11318 netif_device_detach(dev); 11319 11320 if (state == pci_channel_io_perm_failure) { 11321 rtnl_unlock(); 11322 return PCI_ERS_RESULT_DISCONNECT; 11323 } 11324 11325 if (netif_running(dev)) 11326 bnx2x_eeh_nic_unload(bp); 11327 11328 pci_disable_device(pdev); 11329 11330 rtnl_unlock(); 11331 11332 /* Request a slot reset */ 11333 return PCI_ERS_RESULT_NEED_RESET; 11334 } 11335 11336 /** 11337 * bnx2x_io_slot_reset - called after the PCI bus has been reset 11338 * @pdev: Pointer to PCI device 11339 * 11340 * Restart the card from scratch, as if from a cold-boot. 11341 */ 11342 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 11343 { 11344 struct net_device *dev = pci_get_drvdata(pdev); 11345 struct bnx2x *bp = netdev_priv(dev); 11346 11347 rtnl_lock(); 11348 11349 if (pci_enable_device(pdev)) { 11350 dev_err(&pdev->dev, 11351 "Cannot re-enable PCI device after reset\n"); 11352 rtnl_unlock(); 11353 return PCI_ERS_RESULT_DISCONNECT; 11354 } 11355 11356 pci_set_master(pdev); 11357 pci_restore_state(pdev); 11358 11359 if (netif_running(dev)) 11360 bnx2x_set_power_state(bp, PCI_D0); 11361 11362 rtnl_unlock(); 11363 11364 return PCI_ERS_RESULT_RECOVERED; 11365 } 11366 11367 /** 11368 * bnx2x_io_resume - called when traffic can start flowing again 11369 * @pdev: Pointer to PCI device 11370 * 11371 * This callback is called when the error recovery driver tells us that 11372 * its OK to resume normal operation. 11373 */ 11374 static void bnx2x_io_resume(struct pci_dev *pdev) 11375 { 11376 struct net_device *dev = pci_get_drvdata(pdev); 11377 struct bnx2x *bp = netdev_priv(dev); 11378 11379 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11380 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); 11381 return; 11382 } 11383 11384 rtnl_lock(); 11385 11386 bnx2x_eeh_recover(bp); 11387 11388 if (netif_running(dev)) 11389 bnx2x_nic_load(bp, LOAD_NORMAL); 11390 11391 netif_device_attach(dev); 11392 11393 rtnl_unlock(); 11394 } 11395 11396 static struct pci_error_handlers bnx2x_err_handler = { 11397 .error_detected = bnx2x_io_error_detected, 11398 .slot_reset = bnx2x_io_slot_reset, 11399 .resume = bnx2x_io_resume, 11400 }; 11401 11402 static struct pci_driver bnx2x_pci_driver = { 11403 .name = DRV_MODULE_NAME, 11404 .id_table = bnx2x_pci_tbl, 11405 .probe = bnx2x_init_one, 11406 .remove = __devexit_p(bnx2x_remove_one), 11407 .suspend = bnx2x_suspend, 11408 .resume = bnx2x_resume, 11409 .err_handler = &bnx2x_err_handler, 11410 }; 11411 11412 static int __init bnx2x_init(void) 11413 { 11414 int ret; 11415 11416 pr_info("%s", version); 11417 11418 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 11419 if (bnx2x_wq == NULL) { 11420 pr_err("Cannot create workqueue\n"); 11421 return -ENOMEM; 11422 } 11423 11424 ret = pci_register_driver(&bnx2x_pci_driver); 11425 if (ret) { 11426 pr_err("Cannot register driver\n"); 11427 destroy_workqueue(bnx2x_wq); 11428 } 11429 return ret; 11430 } 11431 11432 static void __exit bnx2x_cleanup(void) 11433 { 11434 pci_unregister_driver(&bnx2x_pci_driver); 11435 11436 destroy_workqueue(bnx2x_wq); 11437 } 11438 11439 void bnx2x_notify_link_changed(struct bnx2x *bp) 11440 { 11441 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 11442 } 11443 11444 module_init(bnx2x_init); 11445 module_exit(bnx2x_cleanup); 11446 11447 #ifdef BCM_CNIC 11448 /** 11449 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 11450 * 11451 * @bp: driver handle 11452 * @set: set or clear the CAM entry 11453 * 11454 * This function will wait until the ramdord completion returns. 11455 * Return 0 if success, -ENODEV if ramrod doesn't return. 11456 */ 11457 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 11458 { 11459 unsigned long ramrod_flags = 0; 11460 11461 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11462 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 11463 &bp->iscsi_l2_mac_obj, true, 11464 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 11465 } 11466 11467 /* count denotes the number of new completions we have seen */ 11468 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 11469 { 11470 struct eth_spe *spe; 11471 11472 #ifdef BNX2X_STOP_ON_ERROR 11473 if (unlikely(bp->panic)) 11474 return; 11475 #endif 11476 11477 spin_lock_bh(&bp->spq_lock); 11478 BUG_ON(bp->cnic_spq_pending < count); 11479 bp->cnic_spq_pending -= count; 11480 11481 11482 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 11483 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 11484 & SPE_HDR_CONN_TYPE) >> 11485 SPE_HDR_CONN_TYPE_SHIFT; 11486 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 11487 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 11488 11489 /* Set validation for iSCSI L2 client before sending SETUP 11490 * ramrod 11491 */ 11492 if (type == ETH_CONNECTION_TYPE) { 11493 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) 11494 bnx2x_set_ctx_validation(bp, &bp->context. 11495 vcxt[BNX2X_ISCSI_ETH_CID].eth, 11496 BNX2X_ISCSI_ETH_CID); 11497 } 11498 11499 /* 11500 * There may be not more than 8 L2, not more than 8 L5 SPEs 11501 * and in the air. We also check that number of outstanding 11502 * COMMON ramrods is not more than the EQ and SPQ can 11503 * accommodate. 11504 */ 11505 if (type == ETH_CONNECTION_TYPE) { 11506 if (!atomic_read(&bp->cq_spq_left)) 11507 break; 11508 else 11509 atomic_dec(&bp->cq_spq_left); 11510 } else if (type == NONE_CONNECTION_TYPE) { 11511 if (!atomic_read(&bp->eq_spq_left)) 11512 break; 11513 else 11514 atomic_dec(&bp->eq_spq_left); 11515 } else if ((type == ISCSI_CONNECTION_TYPE) || 11516 (type == FCOE_CONNECTION_TYPE)) { 11517 if (bp->cnic_spq_pending >= 11518 bp->cnic_eth_dev.max_kwqe_pending) 11519 break; 11520 else 11521 bp->cnic_spq_pending++; 11522 } else { 11523 BNX2X_ERR("Unknown SPE type: %d\n", type); 11524 bnx2x_panic(); 11525 break; 11526 } 11527 11528 spe = bnx2x_sp_get_next(bp); 11529 *spe = *bp->cnic_kwq_cons; 11530 11531 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", 11532 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11533 11534 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11535 bp->cnic_kwq_cons = bp->cnic_kwq; 11536 else 11537 bp->cnic_kwq_cons++; 11538 } 11539 bnx2x_sp_prod_update(bp); 11540 spin_unlock_bh(&bp->spq_lock); 11541 } 11542 11543 static int bnx2x_cnic_sp_queue(struct net_device *dev, 11544 struct kwqe_16 *kwqes[], u32 count) 11545 { 11546 struct bnx2x *bp = netdev_priv(dev); 11547 int i; 11548 11549 #ifdef BNX2X_STOP_ON_ERROR 11550 if (unlikely(bp->panic)) { 11551 BNX2X_ERR("Can't post to SP queue while panic\n"); 11552 return -EIO; 11553 } 11554 #endif 11555 11556 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 11557 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 11558 BNX2X_ERR("Handling parity error recovery. Try again later\n"); 11559 return -EAGAIN; 11560 } 11561 11562 spin_lock_bh(&bp->spq_lock); 11563 11564 for (i = 0; i < count; i++) { 11565 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 11566 11567 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 11568 break; 11569 11570 *bp->cnic_kwq_prod = *spe; 11571 11572 bp->cnic_kwq_pending++; 11573 11574 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", 11575 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11576 spe->data.update_data_addr.hi, 11577 spe->data.update_data_addr.lo, 11578 bp->cnic_kwq_pending); 11579 11580 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 11581 bp->cnic_kwq_prod = bp->cnic_kwq; 11582 else 11583 bp->cnic_kwq_prod++; 11584 } 11585 11586 spin_unlock_bh(&bp->spq_lock); 11587 11588 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 11589 bnx2x_cnic_sp_post(bp, 0); 11590 11591 return i; 11592 } 11593 11594 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11595 { 11596 struct cnic_ops *c_ops; 11597 int rc = 0; 11598 11599 mutex_lock(&bp->cnic_mutex); 11600 c_ops = rcu_dereference_protected(bp->cnic_ops, 11601 lockdep_is_held(&bp->cnic_mutex)); 11602 if (c_ops) 11603 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11604 mutex_unlock(&bp->cnic_mutex); 11605 11606 return rc; 11607 } 11608 11609 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 11610 { 11611 struct cnic_ops *c_ops; 11612 int rc = 0; 11613 11614 rcu_read_lock(); 11615 c_ops = rcu_dereference(bp->cnic_ops); 11616 if (c_ops) 11617 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 11618 rcu_read_unlock(); 11619 11620 return rc; 11621 } 11622 11623 /* 11624 * for commands that have no data 11625 */ 11626 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 11627 { 11628 struct cnic_ctl_info ctl = {0}; 11629 11630 ctl.cmd = cmd; 11631 11632 return bnx2x_cnic_ctl_send(bp, &ctl); 11633 } 11634 11635 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 11636 { 11637 struct cnic_ctl_info ctl = {0}; 11638 11639 /* first we tell CNIC and only then we count this as a completion */ 11640 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 11641 ctl.data.comp.cid = cid; 11642 ctl.data.comp.error = err; 11643 11644 bnx2x_cnic_ctl_send_bh(bp, &ctl); 11645 bnx2x_cnic_sp_post(bp, 0); 11646 } 11647 11648 11649 /* Called with netif_addr_lock_bh() taken. 11650 * Sets an rx_mode config for an iSCSI ETH client. 11651 * Doesn't block. 11652 * Completion should be checked outside. 11653 */ 11654 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 11655 { 11656 unsigned long accept_flags = 0, ramrod_flags = 0; 11657 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11658 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 11659 11660 if (start) { 11661 /* Start accepting on iSCSI L2 ring. Accept all multicasts 11662 * because it's the only way for UIO Queue to accept 11663 * multicasts (in non-promiscuous mode only one Queue per 11664 * function will receive multicast packets (leading in our 11665 * case). 11666 */ 11667 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 11668 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 11669 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 11670 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 11671 11672 /* Clear STOP_PENDING bit if START is requested */ 11673 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 11674 11675 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 11676 } else 11677 /* Clear START_PENDING bit if STOP is requested */ 11678 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 11679 11680 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 11681 set_bit(sched_state, &bp->sp_state); 11682 else { 11683 __set_bit(RAMROD_RX, &ramrod_flags); 11684 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 11685 ramrod_flags); 11686 } 11687 } 11688 11689 11690 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 11691 { 11692 struct bnx2x *bp = netdev_priv(dev); 11693 int rc = 0; 11694 11695 switch (ctl->cmd) { 11696 case DRV_CTL_CTXTBL_WR_CMD: { 11697 u32 index = ctl->data.io.offset; 11698 dma_addr_t addr = ctl->data.io.dma_addr; 11699 11700 bnx2x_ilt_wr(bp, index, addr); 11701 break; 11702 } 11703 11704 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 11705 int count = ctl->data.credit.credit_count; 11706 11707 bnx2x_cnic_sp_post(bp, count); 11708 break; 11709 } 11710 11711 /* rtnl_lock is held. */ 11712 case DRV_CTL_START_L2_CMD: { 11713 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11714 unsigned long sp_bits = 0; 11715 11716 /* Configure the iSCSI classification object */ 11717 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 11718 cp->iscsi_l2_client_id, 11719 cp->iscsi_l2_cid, BP_FUNC(bp), 11720 bnx2x_sp(bp, mac_rdata), 11721 bnx2x_sp_mapping(bp, mac_rdata), 11722 BNX2X_FILTER_MAC_PENDING, 11723 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 11724 &bp->macs_pool); 11725 11726 /* Set iSCSI MAC address */ 11727 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 11728 if (rc) 11729 break; 11730 11731 mmiowb(); 11732 barrier(); 11733 11734 /* Start accepting on iSCSI L2 ring */ 11735 11736 netif_addr_lock_bh(dev); 11737 bnx2x_set_iscsi_eth_rx_mode(bp, true); 11738 netif_addr_unlock_bh(dev); 11739 11740 /* bits to wait on */ 11741 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11742 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 11743 11744 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11745 BNX2X_ERR("rx_mode completion timed out!\n"); 11746 11747 break; 11748 } 11749 11750 /* rtnl_lock is held. */ 11751 case DRV_CTL_STOP_L2_CMD: { 11752 unsigned long sp_bits = 0; 11753 11754 /* Stop accepting on iSCSI L2 ring */ 11755 netif_addr_lock_bh(dev); 11756 bnx2x_set_iscsi_eth_rx_mode(bp, false); 11757 netif_addr_unlock_bh(dev); 11758 11759 /* bits to wait on */ 11760 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 11761 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 11762 11763 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 11764 BNX2X_ERR("rx_mode completion timed out!\n"); 11765 11766 mmiowb(); 11767 barrier(); 11768 11769 /* Unset iSCSI L2 MAC */ 11770 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 11771 BNX2X_ISCSI_ETH_MAC, true); 11772 break; 11773 } 11774 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 11775 int count = ctl->data.credit.credit_count; 11776 11777 smp_mb__before_atomic_inc(); 11778 atomic_add(count, &bp->cq_spq_left); 11779 smp_mb__after_atomic_inc(); 11780 break; 11781 } 11782 case DRV_CTL_ULP_REGISTER_CMD: { 11783 int ulp_type = ctl->data.ulp_type; 11784 11785 if (CHIP_IS_E3(bp)) { 11786 int idx = BP_FW_MB_IDX(bp); 11787 u32 cap; 11788 11789 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11790 if (ulp_type == CNIC_ULP_ISCSI) 11791 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11792 else if (ulp_type == CNIC_ULP_FCOE) 11793 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11794 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11795 } 11796 break; 11797 } 11798 case DRV_CTL_ULP_UNREGISTER_CMD: { 11799 int ulp_type = ctl->data.ulp_type; 11800 11801 if (CHIP_IS_E3(bp)) { 11802 int idx = BP_FW_MB_IDX(bp); 11803 u32 cap; 11804 11805 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 11806 if (ulp_type == CNIC_ULP_ISCSI) 11807 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 11808 else if (ulp_type == CNIC_ULP_FCOE) 11809 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 11810 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 11811 } 11812 break; 11813 } 11814 11815 default: 11816 BNX2X_ERR("unknown command %x\n", ctl->cmd); 11817 rc = -EINVAL; 11818 } 11819 11820 return rc; 11821 } 11822 11823 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 11824 { 11825 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11826 11827 if (bp->flags & USING_MSIX_FLAG) { 11828 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 11829 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 11830 cp->irq_arr[0].vector = bp->msix_table[1].vector; 11831 } else { 11832 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 11833 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 11834 } 11835 if (!CHIP_IS_E1x(bp)) 11836 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 11837 else 11838 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 11839 11840 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 11841 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 11842 cp->irq_arr[1].status_blk = bp->def_status_blk; 11843 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 11844 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 11845 11846 cp->num_irq = 2; 11847 } 11848 11849 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 11850 void *data) 11851 { 11852 struct bnx2x *bp = netdev_priv(dev); 11853 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11854 11855 if (ops == NULL) { 11856 BNX2X_ERR("NULL ops received\n"); 11857 return -EINVAL; 11858 } 11859 11860 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11861 if (!bp->cnic_kwq) 11862 return -ENOMEM; 11863 11864 bp->cnic_kwq_cons = bp->cnic_kwq; 11865 bp->cnic_kwq_prod = bp->cnic_kwq; 11866 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 11867 11868 bp->cnic_spq_pending = 0; 11869 bp->cnic_kwq_pending = 0; 11870 11871 bp->cnic_data = data; 11872 11873 cp->num_irq = 0; 11874 cp->drv_state |= CNIC_DRV_STATE_REGD; 11875 cp->iro_arr = bp->iro_arr; 11876 11877 bnx2x_setup_cnic_irq_info(bp); 11878 11879 rcu_assign_pointer(bp->cnic_ops, ops); 11880 11881 return 0; 11882 } 11883 11884 static int bnx2x_unregister_cnic(struct net_device *dev) 11885 { 11886 struct bnx2x *bp = netdev_priv(dev); 11887 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11888 11889 mutex_lock(&bp->cnic_mutex); 11890 cp->drv_state = 0; 11891 RCU_INIT_POINTER(bp->cnic_ops, NULL); 11892 mutex_unlock(&bp->cnic_mutex); 11893 synchronize_rcu(); 11894 kfree(bp->cnic_kwq); 11895 bp->cnic_kwq = NULL; 11896 11897 return 0; 11898 } 11899 11900 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 11901 { 11902 struct bnx2x *bp = netdev_priv(dev); 11903 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11904 11905 /* If both iSCSI and FCoE are disabled - return NULL in 11906 * order to indicate CNIC that it should not try to work 11907 * with this device. 11908 */ 11909 if (NO_ISCSI(bp) && NO_FCOE(bp)) 11910 return NULL; 11911 11912 cp->drv_owner = THIS_MODULE; 11913 cp->chip_id = CHIP_ID(bp); 11914 cp->pdev = bp->pdev; 11915 cp->io_base = bp->regview; 11916 cp->io_base2 = bp->doorbells; 11917 cp->max_kwqe_pending = 8; 11918 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 11919 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 11920 bnx2x_cid_ilt_lines(bp); 11921 cp->ctx_tbl_len = CNIC_ILT_LINES; 11922 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 11923 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 11924 cp->drv_ctl = bnx2x_drv_ctl; 11925 cp->drv_register_cnic = bnx2x_register_cnic; 11926 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 11927 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID; 11928 cp->iscsi_l2_client_id = 11929 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 11930 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID; 11931 11932 if (NO_ISCSI_OOO(bp)) 11933 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 11934 11935 if (NO_ISCSI(bp)) 11936 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 11937 11938 if (NO_FCOE(bp)) 11939 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11940 11941 BNX2X_DEV_INFO( 11942 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", 11943 cp->ctx_blk_size, 11944 cp->ctx_tbl_offset, 11945 cp->ctx_tbl_len, 11946 cp->starting_cid); 11947 return cp; 11948 } 11949 EXPORT_SYMBOL(bnx2x_cnic_probe); 11950 11951 #endif /* BCM_CNIC */ 11952 11953