1 /* bnx2x_main.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/kernel.h> 25 #include <linux/device.h> /* for dev_info() */ 26 #include <linux/timer.h> 27 #include <linux/errno.h> 28 #include <linux/ioport.h> 29 #include <linux/slab.h> 30 #include <linux/interrupt.h> 31 #include <linux/pci.h> 32 #include <linux/aer.h> 33 #include <linux/init.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/bitops.h> 39 #include <linux/irq.h> 40 #include <linux/delay.h> 41 #include <asm/byteorder.h> 42 #include <linux/time.h> 43 #include <linux/ethtool.h> 44 #include <linux/mii.h> 45 #include <linux/if_vlan.h> 46 #include <linux/crash_dump.h> 47 #include <net/ip.h> 48 #include <net/ipv6.h> 49 #include <net/tcp.h> 50 #include <net/vxlan.h> 51 #include <net/checksum.h> 52 #include <net/ip6_checksum.h> 53 #include <linux/workqueue.h> 54 #include <linux/crc32.h> 55 #include <linux/crc32c.h> 56 #include <linux/prefetch.h> 57 #include <linux/zlib.h> 58 #include <linux/io.h> 59 #include <linux/semaphore.h> 60 #include <linux/stringify.h> 61 #include <linux/vmalloc.h> 62 #include "bnx2x.h" 63 #include "bnx2x_init.h" 64 #include "bnx2x_init_ops.h" 65 #include "bnx2x_cmn.h" 66 #include "bnx2x_vfpf.h" 67 #include "bnx2x_dcb.h" 68 #include "bnx2x_sp.h" 69 #include <linux/firmware.h> 70 #include "bnx2x_fw_file_hdr.h" 71 /* FW files */ 72 #define FW_FILE_VERSION \ 73 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 74 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 75 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 76 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 77 78 #define FW_FILE_VERSION_V15 \ 79 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 80 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 81 __stringify(BCM_5710_FW_REVISION_VERSION_V15) "." \ 82 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 83 84 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 85 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 86 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 87 #define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw" 88 #define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw" 89 #define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw" 90 91 /* Time in jiffies before concluding the transmitter is hung */ 92 #define TX_TIMEOUT (5*HZ) 93 94 MODULE_AUTHOR("Eliezer Tamir"); 95 MODULE_DESCRIPTION("QLogic " 96 "BCM57710/57711/57711E/" 97 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 98 "57840/57840_MF Driver"); 99 MODULE_LICENSE("GPL"); 100 MODULE_FIRMWARE(FW_FILE_NAME_E1); 101 MODULE_FIRMWARE(FW_FILE_NAME_E1H); 102 MODULE_FIRMWARE(FW_FILE_NAME_E2); 103 104 int bnx2x_num_queues; 105 module_param_named(num_queues, bnx2x_num_queues, int, 0444); 106 MODULE_PARM_DESC(num_queues, 107 " Set number of queues (default is as a number of CPUs)"); 108 109 static int disable_tpa; 110 module_param(disable_tpa, int, 0444); 111 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 112 113 static int int_mode; 114 module_param(int_mode, int, 0444); 115 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 116 "(1 INT#x; 2 MSI)"); 117 118 static int dropless_fc; 119 module_param(dropless_fc, int, 0444); 120 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 121 122 static int mrrs = -1; 123 module_param(mrrs, int, 0444); 124 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 125 126 static int debug; 127 module_param(debug, int, 0444); 128 MODULE_PARM_DESC(debug, " Default debug msglevel"); 129 130 static struct workqueue_struct *bnx2x_wq; 131 struct workqueue_struct *bnx2x_iov_wq; 132 133 struct bnx2x_mac_vals { 134 u32 xmac_addr; 135 u32 xmac_val; 136 u32 emac_addr; 137 u32 emac_val; 138 u32 umac_addr[2]; 139 u32 umac_val[2]; 140 u32 bmac_addr; 141 u32 bmac_val[2]; 142 }; 143 144 enum bnx2x_board_type { 145 BCM57710 = 0, 146 BCM57711, 147 BCM57711E, 148 BCM57712, 149 BCM57712_MF, 150 BCM57712_VF, 151 BCM57800, 152 BCM57800_MF, 153 BCM57800_VF, 154 BCM57810, 155 BCM57810_MF, 156 BCM57810_VF, 157 BCM57840_4_10, 158 BCM57840_2_20, 159 BCM57840_MF, 160 BCM57840_VF, 161 BCM57811, 162 BCM57811_MF, 163 BCM57840_O, 164 BCM57840_MFO, 165 BCM57811_VF 166 }; 167 168 /* indexed by board_type, above */ 169 static struct { 170 char *name; 171 } board_info[] = { 172 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" }, 173 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" }, 174 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" }, 175 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" }, 176 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" }, 177 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" }, 178 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" }, 179 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" }, 180 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" }, 181 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" }, 182 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" }, 183 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" }, 184 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" }, 185 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" }, 186 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, 187 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }, 188 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" }, 189 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" }, 190 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" }, 191 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, 192 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" } 193 }; 194 195 #ifndef PCI_DEVICE_ID_NX2_57710 196 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 197 #endif 198 #ifndef PCI_DEVICE_ID_NX2_57711 199 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 200 #endif 201 #ifndef PCI_DEVICE_ID_NX2_57711E 202 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 203 #endif 204 #ifndef PCI_DEVICE_ID_NX2_57712 205 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 206 #endif 207 #ifndef PCI_DEVICE_ID_NX2_57712_MF 208 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 209 #endif 210 #ifndef PCI_DEVICE_ID_NX2_57712_VF 211 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF 212 #endif 213 #ifndef PCI_DEVICE_ID_NX2_57800 214 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 215 #endif 216 #ifndef PCI_DEVICE_ID_NX2_57800_MF 217 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 218 #endif 219 #ifndef PCI_DEVICE_ID_NX2_57800_VF 220 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF 221 #endif 222 #ifndef PCI_DEVICE_ID_NX2_57810 223 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 224 #endif 225 #ifndef PCI_DEVICE_ID_NX2_57810_MF 226 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 227 #endif 228 #ifndef PCI_DEVICE_ID_NX2_57840_O 229 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE 230 #endif 231 #ifndef PCI_DEVICE_ID_NX2_57810_VF 232 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF 233 #endif 234 #ifndef PCI_DEVICE_ID_NX2_57840_4_10 235 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 236 #endif 237 #ifndef PCI_DEVICE_ID_NX2_57840_2_20 238 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 239 #endif 240 #ifndef PCI_DEVICE_ID_NX2_57840_MFO 241 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE 242 #endif 243 #ifndef PCI_DEVICE_ID_NX2_57840_MF 244 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 245 #endif 246 #ifndef PCI_DEVICE_ID_NX2_57840_VF 247 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF 248 #endif 249 #ifndef PCI_DEVICE_ID_NX2_57811 250 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 251 #endif 252 #ifndef PCI_DEVICE_ID_NX2_57811_MF 253 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF 254 #endif 255 #ifndef PCI_DEVICE_ID_NX2_57811_VF 256 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF 257 #endif 258 259 static const struct pci_device_id bnx2x_pci_tbl[] = { 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 273 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, 275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, 276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, 277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 278 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 280 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 281 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, 282 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, 283 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, 284 { 0 } 285 }; 286 287 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 288 289 const u32 dmae_reg_go_c[] = { 290 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 291 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 292 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 293 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 294 }; 295 296 /* Global resources for unloading a previously loaded device */ 297 #define BNX2X_PREV_WAIT_NEEDED 1 298 static DEFINE_SEMAPHORE(bnx2x_prev_sem); 299 static LIST_HEAD(bnx2x_prev_list); 300 301 /* Forward declaration */ 302 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); 303 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); 304 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp); 305 306 /**************************************************************************** 307 * General service functions 308 ****************************************************************************/ 309 310 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr); 311 312 static void __storm_memset_dma_mapping(struct bnx2x *bp, 313 u32 addr, dma_addr_t mapping) 314 { 315 REG_WR(bp, addr, U64_LO(mapping)); 316 REG_WR(bp, addr + 4, U64_HI(mapping)); 317 } 318 319 static void storm_memset_spq_addr(struct bnx2x *bp, 320 dma_addr_t mapping, u16 abs_fid) 321 { 322 u32 addr = XSEM_REG_FAST_MEMORY + 323 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 324 325 __storm_memset_dma_mapping(bp, addr, mapping); 326 } 327 328 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 329 u16 pf_id) 330 { 331 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 332 pf_id); 333 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 334 pf_id); 335 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 336 pf_id); 337 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 338 pf_id); 339 } 340 341 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 342 u8 enable) 343 { 344 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 345 enable); 346 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 347 enable); 348 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 349 enable); 350 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 351 enable); 352 } 353 354 static void storm_memset_eq_data(struct bnx2x *bp, 355 struct event_ring_data *eq_data, 356 u16 pfid) 357 { 358 size_t size = sizeof(struct event_ring_data); 359 360 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 361 362 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 363 } 364 365 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 366 u16 pfid) 367 { 368 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 369 REG_WR16(bp, addr, eq_prod); 370 } 371 372 /* used only at init 373 * locking is done by mcp 374 */ 375 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 376 { 377 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 378 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 379 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 380 PCICFG_VENDOR_ID_OFFSET); 381 } 382 383 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 384 { 385 u32 val; 386 387 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 388 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 389 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 390 PCICFG_VENDOR_ID_OFFSET); 391 392 return val; 393 } 394 395 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 396 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 397 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 398 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 399 #define DMAE_DP_DST_NONE "dst_addr [none]" 400 401 static void bnx2x_dp_dmae(struct bnx2x *bp, 402 struct dmae_command *dmae, int msglvl) 403 { 404 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 405 int i; 406 407 switch (dmae->opcode & DMAE_COMMAND_DST) { 408 case DMAE_CMD_DST_PCI: 409 if (src_type == DMAE_CMD_SRC_PCI) 410 DP(msglvl, "DMAE: opcode 0x%08x\n" 411 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 412 "comp_addr [%x:%08x], comp_val 0x%08x\n", 413 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 414 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 415 dmae->comp_addr_hi, dmae->comp_addr_lo, 416 dmae->comp_val); 417 else 418 DP(msglvl, "DMAE: opcode 0x%08x\n" 419 "src [%08x], len [%d*4], dst [%x:%08x]\n" 420 "comp_addr [%x:%08x], comp_val 0x%08x\n", 421 dmae->opcode, dmae->src_addr_lo >> 2, 422 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 423 dmae->comp_addr_hi, dmae->comp_addr_lo, 424 dmae->comp_val); 425 break; 426 case DMAE_CMD_DST_GRC: 427 if (src_type == DMAE_CMD_SRC_PCI) 428 DP(msglvl, "DMAE: opcode 0x%08x\n" 429 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 430 "comp_addr [%x:%08x], comp_val 0x%08x\n", 431 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 432 dmae->len, dmae->dst_addr_lo >> 2, 433 dmae->comp_addr_hi, dmae->comp_addr_lo, 434 dmae->comp_val); 435 else 436 DP(msglvl, "DMAE: opcode 0x%08x\n" 437 "src [%08x], len [%d*4], dst [%08x]\n" 438 "comp_addr [%x:%08x], comp_val 0x%08x\n", 439 dmae->opcode, dmae->src_addr_lo >> 2, 440 dmae->len, dmae->dst_addr_lo >> 2, 441 dmae->comp_addr_hi, dmae->comp_addr_lo, 442 dmae->comp_val); 443 break; 444 default: 445 if (src_type == DMAE_CMD_SRC_PCI) 446 DP(msglvl, "DMAE: opcode 0x%08x\n" 447 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 448 "comp_addr [%x:%08x] comp_val 0x%08x\n", 449 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 450 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 451 dmae->comp_val); 452 else 453 DP(msglvl, "DMAE: opcode 0x%08x\n" 454 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 455 "comp_addr [%x:%08x] comp_val 0x%08x\n", 456 dmae->opcode, dmae->src_addr_lo >> 2, 457 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 458 dmae->comp_val); 459 break; 460 } 461 462 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) 463 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", 464 i, *(((u32 *)dmae) + i)); 465 } 466 467 /* copy command into DMAE command memory and set DMAE command go */ 468 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 469 { 470 u32 cmd_offset; 471 int i; 472 473 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 474 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 475 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 476 } 477 REG_WR(bp, dmae_reg_go_c[idx], 1); 478 } 479 480 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 481 { 482 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 483 DMAE_CMD_C_ENABLE); 484 } 485 486 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 487 { 488 return opcode & ~DMAE_CMD_SRC_RESET; 489 } 490 491 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 492 bool with_comp, u8 comp_type) 493 { 494 u32 opcode = 0; 495 496 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 497 (dst_type << DMAE_COMMAND_DST_SHIFT)); 498 499 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 500 501 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 502 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 503 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 504 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 505 506 #ifdef __BIG_ENDIAN 507 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 508 #else 509 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 510 #endif 511 if (with_comp) 512 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 513 return opcode; 514 } 515 516 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 517 struct dmae_command *dmae, 518 u8 src_type, u8 dst_type) 519 { 520 memset(dmae, 0, sizeof(struct dmae_command)); 521 522 /* set the opcode */ 523 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 524 true, DMAE_COMP_PCI); 525 526 /* fill in the completion parameters */ 527 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 528 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 529 dmae->comp_val = DMAE_COMP_VAL; 530 } 531 532 /* issue a dmae command over the init-channel and wait for completion */ 533 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 534 u32 *comp) 535 { 536 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 537 int rc = 0; 538 539 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); 540 541 /* Lock the dmae channel. Disable BHs to prevent a dead-lock 542 * as long as this code is called both from syscall context and 543 * from ndo_set_rx_mode() flow that may be called from BH. 544 */ 545 546 spin_lock_bh(&bp->dmae_lock); 547 548 /* reset completion */ 549 *comp = 0; 550 551 /* post the command on the channel used for initializations */ 552 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 553 554 /* wait for completion */ 555 udelay(5); 556 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 557 558 if (!cnt || 559 (bp->recovery_state != BNX2X_RECOVERY_DONE && 560 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 561 BNX2X_ERR("DMAE timeout!\n"); 562 rc = DMAE_TIMEOUT; 563 goto unlock; 564 } 565 cnt--; 566 udelay(50); 567 } 568 if (*comp & DMAE_PCI_ERR_FLAG) { 569 BNX2X_ERR("DMAE PCI error!\n"); 570 rc = DMAE_PCI_ERROR; 571 } 572 573 unlock: 574 575 spin_unlock_bh(&bp->dmae_lock); 576 577 return rc; 578 } 579 580 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 581 u32 len32) 582 { 583 int rc; 584 struct dmae_command dmae; 585 586 if (!bp->dmae_ready) { 587 u32 *data = bnx2x_sp(bp, wb_data[0]); 588 589 if (CHIP_IS_E1(bp)) 590 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 591 else 592 bnx2x_init_str_wr(bp, dst_addr, data, len32); 593 return; 594 } 595 596 /* set opcode and fixed command fields */ 597 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 598 599 /* fill in addresses and len */ 600 dmae.src_addr_lo = U64_LO(dma_addr); 601 dmae.src_addr_hi = U64_HI(dma_addr); 602 dmae.dst_addr_lo = dst_addr >> 2; 603 dmae.dst_addr_hi = 0; 604 dmae.len = len32; 605 606 /* issue the command and wait for completion */ 607 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); 608 if (rc) { 609 BNX2X_ERR("DMAE returned failure %d\n", rc); 610 #ifdef BNX2X_STOP_ON_ERROR 611 bnx2x_panic(); 612 #endif 613 } 614 } 615 616 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 617 { 618 int rc; 619 struct dmae_command dmae; 620 621 if (!bp->dmae_ready) { 622 u32 *data = bnx2x_sp(bp, wb_data[0]); 623 int i; 624 625 if (CHIP_IS_E1(bp)) 626 for (i = 0; i < len32; i++) 627 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 628 else 629 for (i = 0; i < len32; i++) 630 data[i] = REG_RD(bp, src_addr + i*4); 631 632 return; 633 } 634 635 /* set opcode and fixed command fields */ 636 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 637 638 /* fill in addresses and len */ 639 dmae.src_addr_lo = src_addr >> 2; 640 dmae.src_addr_hi = 0; 641 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 642 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 643 dmae.len = len32; 644 645 /* issue the command and wait for completion */ 646 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); 647 if (rc) { 648 BNX2X_ERR("DMAE returned failure %d\n", rc); 649 #ifdef BNX2X_STOP_ON_ERROR 650 bnx2x_panic(); 651 #endif 652 } 653 } 654 655 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 656 u32 addr, u32 len) 657 { 658 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 659 int offset = 0; 660 661 while (len > dmae_wr_max) { 662 bnx2x_write_dmae(bp, phys_addr + offset, 663 addr + offset, dmae_wr_max); 664 offset += dmae_wr_max * 4; 665 len -= dmae_wr_max; 666 } 667 668 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 669 } 670 671 enum storms { 672 XSTORM, 673 TSTORM, 674 CSTORM, 675 USTORM, 676 MAX_STORMS 677 }; 678 679 #define STORMS_NUM 4 680 #define REGS_IN_ENTRY 4 681 682 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, 683 enum storms storm, 684 int entry) 685 { 686 switch (storm) { 687 case XSTORM: 688 return XSTORM_ASSERT_LIST_OFFSET(entry); 689 case TSTORM: 690 return TSTORM_ASSERT_LIST_OFFSET(entry); 691 case CSTORM: 692 return CSTORM_ASSERT_LIST_OFFSET(entry); 693 case USTORM: 694 return USTORM_ASSERT_LIST_OFFSET(entry); 695 case MAX_STORMS: 696 default: 697 BNX2X_ERR("unknown storm\n"); 698 } 699 return -EINVAL; 700 } 701 702 static int bnx2x_mc_assert(struct bnx2x *bp) 703 { 704 char last_idx; 705 int i, j, rc = 0; 706 enum storms storm; 707 u32 regs[REGS_IN_ENTRY]; 708 u32 bar_storm_intmem[STORMS_NUM] = { 709 BAR_XSTRORM_INTMEM, 710 BAR_TSTRORM_INTMEM, 711 BAR_CSTRORM_INTMEM, 712 BAR_USTRORM_INTMEM 713 }; 714 u32 storm_assert_list_index[STORMS_NUM] = { 715 XSTORM_ASSERT_LIST_INDEX_OFFSET, 716 TSTORM_ASSERT_LIST_INDEX_OFFSET, 717 CSTORM_ASSERT_LIST_INDEX_OFFSET, 718 USTORM_ASSERT_LIST_INDEX_OFFSET 719 }; 720 char *storms_string[STORMS_NUM] = { 721 "XSTORM", 722 "TSTORM", 723 "CSTORM", 724 "USTORM" 725 }; 726 727 for (storm = XSTORM; storm < MAX_STORMS; storm++) { 728 last_idx = REG_RD8(bp, bar_storm_intmem[storm] + 729 storm_assert_list_index[storm]); 730 if (last_idx) 731 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", 732 storms_string[storm], last_idx); 733 734 /* print the asserts */ 735 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 736 /* read a single assert entry */ 737 for (j = 0; j < REGS_IN_ENTRY; j++) 738 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + 739 bnx2x_get_assert_list_entry(bp, 740 storm, 741 i) + 742 sizeof(u32) * j); 743 744 /* log entry if it contains a valid assert */ 745 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { 746 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 747 storms_string[storm], i, regs[3], 748 regs[2], regs[1], regs[0]); 749 rc++; 750 } else { 751 break; 752 } 753 } 754 } 755 756 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n", 757 CHIP_IS_E1(bp) ? "everest1" : 758 CHIP_IS_E1H(bp) ? "everest1h" : 759 CHIP_IS_E2(bp) ? "everest2" : "everest3", 760 bp->fw_major, bp->fw_minor, bp->fw_rev); 761 762 return rc; 763 } 764 765 #define MCPR_TRACE_BUFFER_SIZE (0x800) 766 #define SCRATCH_BUFFER_SIZE(bp) \ 767 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000)) 768 769 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 770 { 771 u32 addr, val; 772 u32 mark, offset; 773 __be32 data[9]; 774 int word; 775 u32 trace_shmem_base; 776 if (BP_NOMCP(bp)) { 777 BNX2X_ERR("NO MCP - can not dump\n"); 778 return; 779 } 780 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 781 (bp->common.bc_ver & 0xff0000) >> 16, 782 (bp->common.bc_ver & 0xff00) >> 8, 783 (bp->common.bc_ver & 0xff)); 784 785 if (pci_channel_offline(bp->pdev)) { 786 BNX2X_ERR("Cannot dump MCP info while in PCI error\n"); 787 return; 788 } 789 790 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 791 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 792 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 793 794 if (BP_PATH(bp) == 0) 795 trace_shmem_base = bp->common.shmem_base; 796 else 797 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 798 799 /* sanity */ 800 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || 801 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + 802 SCRATCH_BUFFER_SIZE(bp)) { 803 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n", 804 trace_shmem_base); 805 return; 806 } 807 808 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; 809 810 /* validate TRCB signature */ 811 mark = REG_RD(bp, addr); 812 if (mark != MFW_TRACE_SIGNATURE) { 813 BNX2X_ERR("Trace buffer signature is missing."); 814 return ; 815 } 816 817 /* read cyclic buffer pointer */ 818 addr += 4; 819 mark = REG_RD(bp, addr); 820 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; 821 if (mark >= trace_shmem_base || mark < addr + 4) { 822 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n"); 823 return; 824 } 825 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 826 827 printk("%s", lvl); 828 829 /* dump buffer after the mark */ 830 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { 831 for (word = 0; word < 8; word++) 832 data[word] = htonl(REG_RD(bp, offset + 4*word)); 833 data[8] = 0x0; 834 pr_cont("%s", (char *)data); 835 } 836 837 /* dump buffer before the mark */ 838 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 839 for (word = 0; word < 8; word++) 840 data[word] = htonl(REG_RD(bp, offset + 4*word)); 841 data[8] = 0x0; 842 pr_cont("%s", (char *)data); 843 } 844 printk("%s" "end of fw dump\n", lvl); 845 } 846 847 static void bnx2x_fw_dump(struct bnx2x *bp) 848 { 849 bnx2x_fw_dump_lvl(bp, KERN_ERR); 850 } 851 852 static void bnx2x_hc_int_disable(struct bnx2x *bp) 853 { 854 int port = BP_PORT(bp); 855 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 856 u32 val = REG_RD(bp, addr); 857 858 /* in E1 we must use only PCI configuration space to disable 859 * MSI/MSIX capability 860 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 861 */ 862 if (CHIP_IS_E1(bp)) { 863 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 864 * Use mask register to prevent from HC sending interrupts 865 * after we exit the function 866 */ 867 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 868 869 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 870 HC_CONFIG_0_REG_INT_LINE_EN_0 | 871 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 872 } else 873 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 874 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 875 HC_CONFIG_0_REG_INT_LINE_EN_0 | 876 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 877 878 DP(NETIF_MSG_IFDOWN, 879 "write %x to HC %d (addr 0x%x)\n", 880 val, port, addr); 881 882 REG_WR(bp, addr, val); 883 if (REG_RD(bp, addr) != val) 884 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 885 } 886 887 static void bnx2x_igu_int_disable(struct bnx2x *bp) 888 { 889 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 890 891 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 892 IGU_PF_CONF_INT_LINE_EN | 893 IGU_PF_CONF_ATTN_BIT_EN); 894 895 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 896 897 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 898 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 899 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 900 } 901 902 static void bnx2x_int_disable(struct bnx2x *bp) 903 { 904 if (bp->common.int_block == INT_BLOCK_HC) 905 bnx2x_hc_int_disable(bp); 906 else 907 bnx2x_igu_int_disable(bp); 908 } 909 910 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) 911 { 912 int i; 913 u16 j; 914 struct hc_sp_status_block_data sp_sb_data; 915 int func = BP_FUNC(bp); 916 #ifdef BNX2X_STOP_ON_ERROR 917 u16 start = 0, end = 0; 918 u8 cos; 919 #endif 920 if (IS_PF(bp) && disable_int) 921 bnx2x_int_disable(bp); 922 923 bp->stats_state = STATS_STATE_DISABLED; 924 bp->eth_stats.unrecoverable_error++; 925 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 926 927 BNX2X_ERR("begin crash dump -----------------\n"); 928 929 /* Indices */ 930 /* Common */ 931 if (IS_PF(bp)) { 932 struct host_sp_status_block *def_sb = bp->def_status_blk; 933 int data_size, cstorm_offset; 934 935 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 936 bp->def_idx, bp->def_att_idx, bp->attn_state, 937 bp->spq_prod_idx, bp->stats_counter); 938 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 939 def_sb->atten_status_block.attn_bits, 940 def_sb->atten_status_block.attn_bits_ack, 941 def_sb->atten_status_block.status_block_id, 942 def_sb->atten_status_block.attn_bits_index); 943 BNX2X_ERR(" def ("); 944 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 945 pr_cont("0x%x%s", 946 def_sb->sp_sb.index_values[i], 947 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 948 949 data_size = sizeof(struct hc_sp_status_block_data) / 950 sizeof(u32); 951 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func); 952 for (i = 0; i < data_size; i++) 953 *((u32 *)&sp_sb_data + i) = 954 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + 955 i * sizeof(u32)); 956 957 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 958 sp_sb_data.igu_sb_id, 959 sp_sb_data.igu_seg_id, 960 sp_sb_data.p_func.pf_id, 961 sp_sb_data.p_func.vnic_id, 962 sp_sb_data.p_func.vf_id, 963 sp_sb_data.p_func.vf_valid, 964 sp_sb_data.state); 965 } 966 967 for_each_eth_queue(bp, i) { 968 struct bnx2x_fastpath *fp = &bp->fp[i]; 969 int loop; 970 struct hc_status_block_data_e2 sb_data_e2; 971 struct hc_status_block_data_e1x sb_data_e1x; 972 struct hc_status_block_sm *hc_sm_p = 973 CHIP_IS_E1x(bp) ? 974 sb_data_e1x.common.state_machine : 975 sb_data_e2.common.state_machine; 976 struct hc_index_data *hc_index_p = 977 CHIP_IS_E1x(bp) ? 978 sb_data_e1x.index_data : 979 sb_data_e2.index_data; 980 u8 data_size, cos; 981 u32 *sb_data_p; 982 struct bnx2x_fp_txdata txdata; 983 984 if (!bp->fp) 985 break; 986 987 if (!fp->rx_cons_sb) 988 continue; 989 990 /* Rx */ 991 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 992 i, fp->rx_bd_prod, fp->rx_bd_cons, 993 fp->rx_comp_prod, 994 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 995 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 996 fp->rx_sge_prod, fp->last_max_sge, 997 le16_to_cpu(fp->fp_hc_idx)); 998 999 /* Tx */ 1000 for_each_cos_in_tx_queue(fp, cos) 1001 { 1002 if (!fp->txdata_ptr[cos]) 1003 break; 1004 1005 txdata = *fp->txdata_ptr[cos]; 1006 1007 if (!txdata.tx_cons_sb) 1008 continue; 1009 1010 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 1011 i, txdata.tx_pkt_prod, 1012 txdata.tx_pkt_cons, txdata.tx_bd_prod, 1013 txdata.tx_bd_cons, 1014 le16_to_cpu(*txdata.tx_cons_sb)); 1015 } 1016 1017 loop = CHIP_IS_E1x(bp) ? 1018 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 1019 1020 /* host sb data */ 1021 1022 if (IS_FCOE_FP(fp)) 1023 continue; 1024 1025 BNX2X_ERR(" run indexes ("); 1026 for (j = 0; j < HC_SB_MAX_SM; j++) 1027 pr_cont("0x%x%s", 1028 fp->sb_running_index[j], 1029 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 1030 1031 BNX2X_ERR(" indexes ("); 1032 for (j = 0; j < loop; j++) 1033 pr_cont("0x%x%s", 1034 fp->sb_index_values[j], 1035 (j == loop - 1) ? ")" : " "); 1036 1037 /* VF cannot access FW refelection for status block */ 1038 if (IS_VF(bp)) 1039 continue; 1040 1041 /* fw sb data */ 1042 data_size = CHIP_IS_E1x(bp) ? 1043 sizeof(struct hc_status_block_data_e1x) : 1044 sizeof(struct hc_status_block_data_e2); 1045 data_size /= sizeof(u32); 1046 sb_data_p = CHIP_IS_E1x(bp) ? 1047 (u32 *)&sb_data_e1x : 1048 (u32 *)&sb_data_e2; 1049 /* copy sb data in here */ 1050 for (j = 0; j < data_size; j++) 1051 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 1052 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 1053 j * sizeof(u32)); 1054 1055 if (!CHIP_IS_E1x(bp)) { 1056 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1057 sb_data_e2.common.p_func.pf_id, 1058 sb_data_e2.common.p_func.vf_id, 1059 sb_data_e2.common.p_func.vf_valid, 1060 sb_data_e2.common.p_func.vnic_id, 1061 sb_data_e2.common.same_igu_sb_1b, 1062 sb_data_e2.common.state); 1063 } else { 1064 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1065 sb_data_e1x.common.p_func.pf_id, 1066 sb_data_e1x.common.p_func.vf_id, 1067 sb_data_e1x.common.p_func.vf_valid, 1068 sb_data_e1x.common.p_func.vnic_id, 1069 sb_data_e1x.common.same_igu_sb_1b, 1070 sb_data_e1x.common.state); 1071 } 1072 1073 /* SB_SMs data */ 1074 for (j = 0; j < HC_SB_MAX_SM; j++) { 1075 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 1076 j, hc_sm_p[j].__flags, 1077 hc_sm_p[j].igu_sb_id, 1078 hc_sm_p[j].igu_seg_id, 1079 hc_sm_p[j].time_to_expire, 1080 hc_sm_p[j].timer_value); 1081 } 1082 1083 /* Indices data */ 1084 for (j = 0; j < loop; j++) { 1085 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 1086 hc_index_p[j].flags, 1087 hc_index_p[j].timeout); 1088 } 1089 } 1090 1091 #ifdef BNX2X_STOP_ON_ERROR 1092 if (IS_PF(bp)) { 1093 /* event queue */ 1094 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); 1095 for (i = 0; i < NUM_EQ_DESC; i++) { 1096 u32 *data = (u32 *)&bp->eq_ring[i].message.data; 1097 1098 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", 1099 i, bp->eq_ring[i].message.opcode, 1100 bp->eq_ring[i].message.error); 1101 BNX2X_ERR("data: %x %x %x\n", 1102 data[0], data[1], data[2]); 1103 } 1104 } 1105 1106 /* Rings */ 1107 /* Rx */ 1108 for_each_valid_rx_queue(bp, i) { 1109 struct bnx2x_fastpath *fp = &bp->fp[i]; 1110 1111 if (!bp->fp) 1112 break; 1113 1114 if (!fp->rx_cons_sb) 1115 continue; 1116 1117 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 1118 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 1119 for (j = start; j != end; j = RX_BD(j + 1)) { 1120 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 1121 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 1122 1123 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 1124 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 1125 } 1126 1127 start = RX_SGE(fp->rx_sge_prod); 1128 end = RX_SGE(fp->last_max_sge); 1129 for (j = start; j != end; j = RX_SGE(j + 1)) { 1130 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 1131 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 1132 1133 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 1134 i, j, rx_sge[1], rx_sge[0], sw_page->page); 1135 } 1136 1137 start = RCQ_BD(fp->rx_comp_cons - 10); 1138 end = RCQ_BD(fp->rx_comp_cons + 503); 1139 for (j = start; j != end; j = RCQ_BD(j + 1)) { 1140 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 1141 1142 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 1143 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 1144 } 1145 } 1146 1147 /* Tx */ 1148 for_each_valid_tx_queue(bp, i) { 1149 struct bnx2x_fastpath *fp = &bp->fp[i]; 1150 1151 if (!bp->fp) 1152 break; 1153 1154 for_each_cos_in_tx_queue(fp, cos) { 1155 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; 1156 1157 if (!fp->txdata_ptr[cos]) 1158 break; 1159 1160 if (!txdata->tx_cons_sb) 1161 continue; 1162 1163 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 1164 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 1165 for (j = start; j != end; j = TX_BD(j + 1)) { 1166 struct sw_tx_bd *sw_bd = 1167 &txdata->tx_buf_ring[j]; 1168 1169 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 1170 i, cos, j, sw_bd->skb, 1171 sw_bd->first_bd); 1172 } 1173 1174 start = TX_BD(txdata->tx_bd_cons - 10); 1175 end = TX_BD(txdata->tx_bd_cons + 254); 1176 for (j = start; j != end; j = TX_BD(j + 1)) { 1177 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 1178 1179 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 1180 i, cos, j, tx_bd[0], tx_bd[1], 1181 tx_bd[2], tx_bd[3]); 1182 } 1183 } 1184 } 1185 #endif 1186 if (IS_PF(bp)) { 1187 int tmp_msg_en = bp->msg_enable; 1188 1189 bnx2x_fw_dump(bp); 1190 bp->msg_enable |= NETIF_MSG_HW; 1191 BNX2X_ERR("Idle check (1st round) ----------\n"); 1192 bnx2x_idle_chk(bp); 1193 BNX2X_ERR("Idle check (2nd round) ----------\n"); 1194 bnx2x_idle_chk(bp); 1195 bp->msg_enable = tmp_msg_en; 1196 bnx2x_mc_assert(bp); 1197 } 1198 1199 BNX2X_ERR("end crash dump -----------------\n"); 1200 } 1201 1202 /* 1203 * FLR Support for E2 1204 * 1205 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1206 * initialization. 1207 */ 1208 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ 1209 #define FLR_WAIT_INTERVAL 50 /* usec */ 1210 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1211 1212 struct pbf_pN_buf_regs { 1213 int pN; 1214 u32 init_crd; 1215 u32 crd; 1216 u32 crd_freed; 1217 }; 1218 1219 struct pbf_pN_cmd_regs { 1220 int pN; 1221 u32 lines_occup; 1222 u32 lines_freed; 1223 }; 1224 1225 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1226 struct pbf_pN_buf_regs *regs, 1227 u32 poll_count) 1228 { 1229 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1230 u32 cur_cnt = poll_count; 1231 1232 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1233 crd = crd_start = REG_RD(bp, regs->crd); 1234 init_crd = REG_RD(bp, regs->init_crd); 1235 1236 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1237 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1238 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1239 1240 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1241 (init_crd - crd_start))) { 1242 if (cur_cnt--) { 1243 udelay(FLR_WAIT_INTERVAL); 1244 crd = REG_RD(bp, regs->crd); 1245 crd_freed = REG_RD(bp, regs->crd_freed); 1246 } else { 1247 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1248 regs->pN); 1249 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1250 regs->pN, crd); 1251 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1252 regs->pN, crd_freed); 1253 break; 1254 } 1255 } 1256 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1257 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1258 } 1259 1260 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1261 struct pbf_pN_cmd_regs *regs, 1262 u32 poll_count) 1263 { 1264 u32 occup, to_free, freed, freed_start; 1265 u32 cur_cnt = poll_count; 1266 1267 occup = to_free = REG_RD(bp, regs->lines_occup); 1268 freed = freed_start = REG_RD(bp, regs->lines_freed); 1269 1270 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1271 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1272 1273 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1274 if (cur_cnt--) { 1275 udelay(FLR_WAIT_INTERVAL); 1276 occup = REG_RD(bp, regs->lines_occup); 1277 freed = REG_RD(bp, regs->lines_freed); 1278 } else { 1279 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1280 regs->pN); 1281 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1282 regs->pN, occup); 1283 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1284 regs->pN, freed); 1285 break; 1286 } 1287 } 1288 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1289 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1290 } 1291 1292 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1293 u32 expected, u32 poll_count) 1294 { 1295 u32 cur_cnt = poll_count; 1296 u32 val; 1297 1298 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1299 udelay(FLR_WAIT_INTERVAL); 1300 1301 return val; 1302 } 1303 1304 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1305 char *msg, u32 poll_cnt) 1306 { 1307 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1308 if (val != 0) { 1309 BNX2X_ERR("%s usage count=%d\n", msg, val); 1310 return 1; 1311 } 1312 return 0; 1313 } 1314 1315 /* Common routines with VF FLR cleanup */ 1316 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1317 { 1318 /* adjust polling timeout */ 1319 if (CHIP_REV_IS_EMUL(bp)) 1320 return FLR_POLL_CNT * 2000; 1321 1322 if (CHIP_REV_IS_FPGA(bp)) 1323 return FLR_POLL_CNT * 120; 1324 1325 return FLR_POLL_CNT; 1326 } 1327 1328 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1329 { 1330 struct pbf_pN_cmd_regs cmd_regs[] = { 1331 {0, (CHIP_IS_E3B0(bp)) ? 1332 PBF_REG_TQ_OCCUPANCY_Q0 : 1333 PBF_REG_P0_TQ_OCCUPANCY, 1334 (CHIP_IS_E3B0(bp)) ? 1335 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1336 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1337 {1, (CHIP_IS_E3B0(bp)) ? 1338 PBF_REG_TQ_OCCUPANCY_Q1 : 1339 PBF_REG_P1_TQ_OCCUPANCY, 1340 (CHIP_IS_E3B0(bp)) ? 1341 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1342 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1343 {4, (CHIP_IS_E3B0(bp)) ? 1344 PBF_REG_TQ_OCCUPANCY_LB_Q : 1345 PBF_REG_P4_TQ_OCCUPANCY, 1346 (CHIP_IS_E3B0(bp)) ? 1347 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1348 PBF_REG_P4_TQ_LINES_FREED_CNT} 1349 }; 1350 1351 struct pbf_pN_buf_regs buf_regs[] = { 1352 {0, (CHIP_IS_E3B0(bp)) ? 1353 PBF_REG_INIT_CRD_Q0 : 1354 PBF_REG_P0_INIT_CRD , 1355 (CHIP_IS_E3B0(bp)) ? 1356 PBF_REG_CREDIT_Q0 : 1357 PBF_REG_P0_CREDIT, 1358 (CHIP_IS_E3B0(bp)) ? 1359 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1360 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1361 {1, (CHIP_IS_E3B0(bp)) ? 1362 PBF_REG_INIT_CRD_Q1 : 1363 PBF_REG_P1_INIT_CRD, 1364 (CHIP_IS_E3B0(bp)) ? 1365 PBF_REG_CREDIT_Q1 : 1366 PBF_REG_P1_CREDIT, 1367 (CHIP_IS_E3B0(bp)) ? 1368 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1369 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1370 {4, (CHIP_IS_E3B0(bp)) ? 1371 PBF_REG_INIT_CRD_LB_Q : 1372 PBF_REG_P4_INIT_CRD, 1373 (CHIP_IS_E3B0(bp)) ? 1374 PBF_REG_CREDIT_LB_Q : 1375 PBF_REG_P4_CREDIT, 1376 (CHIP_IS_E3B0(bp)) ? 1377 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1378 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1379 }; 1380 1381 int i; 1382 1383 /* Verify the command queues are flushed P0, P1, P4 */ 1384 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1385 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1386 1387 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1388 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1389 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1390 } 1391 1392 #define OP_GEN_PARAM(param) \ 1393 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1394 1395 #define OP_GEN_TYPE(type) \ 1396 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1397 1398 #define OP_GEN_AGG_VECT(index) \ 1399 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1400 1401 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) 1402 { 1403 u32 op_gen_command = 0; 1404 u32 comp_addr = BAR_CSTRORM_INTMEM + 1405 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1406 1407 if (REG_RD(bp, comp_addr)) { 1408 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1409 return 1; 1410 } 1411 1412 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1413 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1414 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 1415 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1416 1417 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1418 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); 1419 1420 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1421 BNX2X_ERR("FW final cleanup did not succeed\n"); 1422 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1423 (REG_RD(bp, comp_addr))); 1424 bnx2x_panic(); 1425 return 1; 1426 } 1427 /* Zero completion for next FLR */ 1428 REG_WR(bp, comp_addr, 0); 1429 1430 return 0; 1431 } 1432 1433 u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1434 { 1435 u16 status; 1436 1437 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 1438 return status & PCI_EXP_DEVSTA_TRPND; 1439 } 1440 1441 /* PF FLR specific routines 1442 */ 1443 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1444 { 1445 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1446 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1447 CFC_REG_NUM_LCIDS_INSIDE_PF, 1448 "CFC PF usage counter timed out", 1449 poll_cnt)) 1450 return 1; 1451 1452 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1453 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1454 DORQ_REG_PF_USAGE_CNT, 1455 "DQ PF usage counter timed out", 1456 poll_cnt)) 1457 return 1; 1458 1459 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1460 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1461 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1462 "QM PF usage counter timed out", 1463 poll_cnt)) 1464 return 1; 1465 1466 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1467 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1468 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1469 "Timers VNIC usage counter timed out", 1470 poll_cnt)) 1471 return 1; 1472 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1473 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1474 "Timers NUM_SCANS usage counter timed out", 1475 poll_cnt)) 1476 return 1; 1477 1478 /* Wait DMAE PF usage counter to zero */ 1479 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1480 dmae_reg_go_c[INIT_DMAE_C(bp)], 1481 "DMAE command register timed out", 1482 poll_cnt)) 1483 return 1; 1484 1485 return 0; 1486 } 1487 1488 static void bnx2x_hw_enable_status(struct bnx2x *bp) 1489 { 1490 u32 val; 1491 1492 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1493 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1494 1495 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1496 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1497 1498 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1499 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1500 1501 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1502 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1503 1504 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1505 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1506 1507 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1508 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1509 1510 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1511 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1512 1513 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1514 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1515 val); 1516 } 1517 1518 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1519 { 1520 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1521 1522 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1523 1524 /* Re-enable PF target read access */ 1525 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1526 1527 /* Poll HW usage counters */ 1528 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1529 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1530 return -EBUSY; 1531 1532 /* Zero the igu 'trailing edge' and 'leading edge' */ 1533 1534 /* Send the FW cleanup command */ 1535 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1536 return -EBUSY; 1537 1538 /* ATC cleanup */ 1539 1540 /* Verify TX hw is flushed */ 1541 bnx2x_tx_hw_flushed(bp, poll_cnt); 1542 1543 /* Wait 100ms (not adjusted according to platform) */ 1544 msleep(100); 1545 1546 /* Verify no pending pci transactions */ 1547 if (bnx2x_is_pcie_pending(bp->pdev)) 1548 BNX2X_ERR("PCIE Transactions still pending\n"); 1549 1550 /* Debug */ 1551 bnx2x_hw_enable_status(bp); 1552 1553 /* 1554 * Master enable - Due to WB DMAE writes performed before this 1555 * register is re-initialized as part of the regular function init 1556 */ 1557 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1558 1559 return 0; 1560 } 1561 1562 static void bnx2x_hc_int_enable(struct bnx2x *bp) 1563 { 1564 int port = BP_PORT(bp); 1565 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1566 u32 val = REG_RD(bp, addr); 1567 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1568 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1569 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1570 1571 if (msix) { 1572 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1573 HC_CONFIG_0_REG_INT_LINE_EN_0); 1574 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1575 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1576 if (single_msix) 1577 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 1578 } else if (msi) { 1579 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1580 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1581 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1582 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1583 } else { 1584 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1585 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1586 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1587 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1588 1589 if (!CHIP_IS_E1(bp)) { 1590 DP(NETIF_MSG_IFUP, 1591 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1592 1593 REG_WR(bp, addr, val); 1594 1595 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1596 } 1597 } 1598 1599 if (CHIP_IS_E1(bp)) 1600 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1601 1602 DP(NETIF_MSG_IFUP, 1603 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1604 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1605 1606 REG_WR(bp, addr, val); 1607 /* 1608 * Ensure that HC_CONFIG is written before leading/trailing edge config 1609 */ 1610 barrier(); 1611 1612 if (!CHIP_IS_E1(bp)) { 1613 /* init leading/trailing edge */ 1614 if (IS_MF(bp)) { 1615 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1616 if (bp->port.pmf) 1617 /* enable nig and gpio3 attention */ 1618 val |= 0x1100; 1619 } else 1620 val = 0xffff; 1621 1622 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1623 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1624 } 1625 } 1626 1627 static void bnx2x_igu_int_enable(struct bnx2x *bp) 1628 { 1629 u32 val; 1630 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1631 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1632 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1633 1634 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1635 1636 if (msix) { 1637 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1638 IGU_PF_CONF_SINGLE_ISR_EN); 1639 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1640 IGU_PF_CONF_ATTN_BIT_EN); 1641 1642 if (single_msix) 1643 val |= IGU_PF_CONF_SINGLE_ISR_EN; 1644 } else if (msi) { 1645 val &= ~IGU_PF_CONF_INT_LINE_EN; 1646 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1647 IGU_PF_CONF_ATTN_BIT_EN | 1648 IGU_PF_CONF_SINGLE_ISR_EN); 1649 } else { 1650 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1651 val |= (IGU_PF_CONF_INT_LINE_EN | 1652 IGU_PF_CONF_ATTN_BIT_EN | 1653 IGU_PF_CONF_SINGLE_ISR_EN); 1654 } 1655 1656 /* Clean previous status - need to configure igu prior to ack*/ 1657 if ((!msix) || single_msix) { 1658 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1659 bnx2x_ack_int(bp); 1660 } 1661 1662 val |= IGU_PF_CONF_FUNC_EN; 1663 1664 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1665 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1666 1667 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1668 1669 if (val & IGU_PF_CONF_INT_LINE_EN) 1670 pci_intx(bp->pdev, true); 1671 1672 barrier(); 1673 1674 /* init leading/trailing edge */ 1675 if (IS_MF(bp)) { 1676 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1677 if (bp->port.pmf) 1678 /* enable nig and gpio3 attention */ 1679 val |= 0x1100; 1680 } else 1681 val = 0xffff; 1682 1683 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1684 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1685 } 1686 1687 void bnx2x_int_enable(struct bnx2x *bp) 1688 { 1689 if (bp->common.int_block == INT_BLOCK_HC) 1690 bnx2x_hc_int_enable(bp); 1691 else 1692 bnx2x_igu_int_enable(bp); 1693 } 1694 1695 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1696 { 1697 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1698 int i, offset; 1699 1700 if (disable_hw) 1701 /* prevent the HW from sending interrupts */ 1702 bnx2x_int_disable(bp); 1703 1704 /* make sure all ISRs are done */ 1705 if (msix) { 1706 synchronize_irq(bp->msix_table[0].vector); 1707 offset = 1; 1708 if (CNIC_SUPPORT(bp)) 1709 offset++; 1710 for_each_eth_queue(bp, i) 1711 synchronize_irq(bp->msix_table[offset++].vector); 1712 } else 1713 synchronize_irq(bp->pdev->irq); 1714 1715 /* make sure sp_task is not running */ 1716 cancel_delayed_work(&bp->sp_task); 1717 cancel_delayed_work(&bp->period_task); 1718 flush_workqueue(bnx2x_wq); 1719 } 1720 1721 /* fast path */ 1722 1723 /* 1724 * General service functions 1725 */ 1726 1727 /* Return true if succeeded to acquire the lock */ 1728 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1729 { 1730 u32 lock_status; 1731 u32 resource_bit = (1 << resource); 1732 int func = BP_FUNC(bp); 1733 u32 hw_lock_control_reg; 1734 1735 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1736 "Trying to take a lock on resource %d\n", resource); 1737 1738 /* Validating that the resource is within range */ 1739 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1740 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1741 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1742 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1743 return false; 1744 } 1745 1746 if (func <= 5) 1747 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1748 else 1749 hw_lock_control_reg = 1750 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1751 1752 /* Try to acquire the lock */ 1753 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1754 lock_status = REG_RD(bp, hw_lock_control_reg); 1755 if (lock_status & resource_bit) 1756 return true; 1757 1758 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1759 "Failed to get a lock on resource %d\n", resource); 1760 return false; 1761 } 1762 1763 /** 1764 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1765 * 1766 * @bp: driver handle 1767 * 1768 * Returns the recovery leader resource id according to the engine this function 1769 * belongs to. Currently only only 2 engines is supported. 1770 */ 1771 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1772 { 1773 if (BP_PATH(bp)) 1774 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1775 else 1776 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1777 } 1778 1779 /** 1780 * bnx2x_trylock_leader_lock- try to acquire a leader lock. 1781 * 1782 * @bp: driver handle 1783 * 1784 * Tries to acquire a leader lock for current engine. 1785 */ 1786 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1787 { 1788 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1789 } 1790 1791 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1792 1793 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ 1794 static int bnx2x_schedule_sp_task(struct bnx2x *bp) 1795 { 1796 /* Set the interrupt occurred bit for the sp-task to recognize it 1797 * must ack the interrupt and transition according to the IGU 1798 * state machine. 1799 */ 1800 atomic_set(&bp->interrupt_occurred, 1); 1801 1802 /* The sp_task must execute only after this bit 1803 * is set, otherwise we will get out of sync and miss all 1804 * further interrupts. Hence, the barrier. 1805 */ 1806 smp_wmb(); 1807 1808 /* schedule sp_task to workqueue */ 1809 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1810 } 1811 1812 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1813 { 1814 struct bnx2x *bp = fp->bp; 1815 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1816 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1817 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1818 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 1819 1820 DP(BNX2X_MSG_SP, 1821 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1822 fp->index, cid, command, bp->state, 1823 rr_cqe->ramrod_cqe.ramrod_type); 1824 1825 /* If cid is within VF range, replace the slowpath object with the 1826 * one corresponding to this VF 1827 */ 1828 if (cid >= BNX2X_FIRST_VF_CID && 1829 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) 1830 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); 1831 1832 switch (command) { 1833 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1834 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1835 drv_cmd = BNX2X_Q_CMD_UPDATE; 1836 break; 1837 1838 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1839 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1840 drv_cmd = BNX2X_Q_CMD_SETUP; 1841 break; 1842 1843 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1844 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1845 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1846 break; 1847 1848 case (RAMROD_CMD_ID_ETH_HALT): 1849 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1850 drv_cmd = BNX2X_Q_CMD_HALT; 1851 break; 1852 1853 case (RAMROD_CMD_ID_ETH_TERMINATE): 1854 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); 1855 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1856 break; 1857 1858 case (RAMROD_CMD_ID_ETH_EMPTY): 1859 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1860 drv_cmd = BNX2X_Q_CMD_EMPTY; 1861 break; 1862 1863 case (RAMROD_CMD_ID_ETH_TPA_UPDATE): 1864 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); 1865 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA; 1866 break; 1867 1868 default: 1869 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1870 command, fp->index); 1871 return; 1872 } 1873 1874 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1875 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1876 /* q_obj->complete_cmd() failure means that this was 1877 * an unexpected completion. 1878 * 1879 * In this case we don't want to increase the bp->spq_left 1880 * because apparently we haven't sent this command the first 1881 * place. 1882 */ 1883 #ifdef BNX2X_STOP_ON_ERROR 1884 bnx2x_panic(); 1885 #else 1886 return; 1887 #endif 1888 1889 smp_mb__before_atomic(); 1890 atomic_inc(&bp->cq_spq_left); 1891 /* push the change in bp->spq_left and towards the memory */ 1892 smp_mb__after_atomic(); 1893 1894 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1895 1896 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 1897 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { 1898 /* if Q update ramrod is completed for last Q in AFEX vif set 1899 * flow, then ACK MCP at the end 1900 * 1901 * mark pending ACK to MCP bit. 1902 * prevent case that both bits are cleared. 1903 * At the end of load/unload driver checks that 1904 * sp_state is cleared, and this order prevents 1905 * races 1906 */ 1907 smp_mb__before_atomic(); 1908 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); 1909 wmb(); 1910 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 1911 smp_mb__after_atomic(); 1912 1913 /* schedule the sp task as mcp ack is required */ 1914 bnx2x_schedule_sp_task(bp); 1915 } 1916 1917 return; 1918 } 1919 1920 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1921 { 1922 struct bnx2x *bp = netdev_priv(dev_instance); 1923 u16 status = bnx2x_ack_int(bp); 1924 u16 mask; 1925 int i; 1926 u8 cos; 1927 1928 /* Return here if interrupt is shared and it's not for us */ 1929 if (unlikely(status == 0)) { 1930 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1931 return IRQ_NONE; 1932 } 1933 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1934 1935 #ifdef BNX2X_STOP_ON_ERROR 1936 if (unlikely(bp->panic)) 1937 return IRQ_HANDLED; 1938 #endif 1939 1940 for_each_eth_queue(bp, i) { 1941 struct bnx2x_fastpath *fp = &bp->fp[i]; 1942 1943 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); 1944 if (status & mask) { 1945 /* Handle Rx or Tx according to SB id */ 1946 for_each_cos_in_tx_queue(fp, cos) 1947 prefetch(fp->txdata_ptr[cos]->tx_cons_sb); 1948 prefetch(&fp->sb_running_index[SM_RX_ID]); 1949 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); 1950 status &= ~mask; 1951 } 1952 } 1953 1954 if (CNIC_SUPPORT(bp)) { 1955 mask = 0x2; 1956 if (status & (mask | 0x1)) { 1957 struct cnic_ops *c_ops = NULL; 1958 1959 rcu_read_lock(); 1960 c_ops = rcu_dereference(bp->cnic_ops); 1961 if (c_ops && (bp->cnic_eth_dev.drv_state & 1962 CNIC_DRV_STATE_HANDLES_IRQ)) 1963 c_ops->cnic_handler(bp->cnic_data, NULL); 1964 rcu_read_unlock(); 1965 1966 status &= ~mask; 1967 } 1968 } 1969 1970 if (unlikely(status & 0x1)) { 1971 1972 /* schedule sp task to perform default status block work, ack 1973 * attentions and enable interrupts. 1974 */ 1975 bnx2x_schedule_sp_task(bp); 1976 1977 status &= ~0x1; 1978 if (!status) 1979 return IRQ_HANDLED; 1980 } 1981 1982 if (unlikely(status)) 1983 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1984 status); 1985 1986 return IRQ_HANDLED; 1987 } 1988 1989 /* Link */ 1990 1991 /* 1992 * General service functions 1993 */ 1994 1995 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1996 { 1997 u32 lock_status; 1998 u32 resource_bit = (1 << resource); 1999 int func = BP_FUNC(bp); 2000 u32 hw_lock_control_reg; 2001 int cnt; 2002 2003 /* Validating that the resource is within range */ 2004 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 2005 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 2006 resource, HW_LOCK_MAX_RESOURCE_VALUE); 2007 return -EINVAL; 2008 } 2009 2010 if (func <= 5) { 2011 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 2012 } else { 2013 hw_lock_control_reg = 2014 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 2015 } 2016 2017 /* Validating that the resource is not already taken */ 2018 lock_status = REG_RD(bp, hw_lock_control_reg); 2019 if (lock_status & resource_bit) { 2020 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 2021 lock_status, resource_bit); 2022 return -EEXIST; 2023 } 2024 2025 /* Try for 5 second every 5ms */ 2026 for (cnt = 0; cnt < 1000; cnt++) { 2027 /* Try to acquire the lock */ 2028 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 2029 lock_status = REG_RD(bp, hw_lock_control_reg); 2030 if (lock_status & resource_bit) 2031 return 0; 2032 2033 usleep_range(5000, 10000); 2034 } 2035 BNX2X_ERR("Timeout\n"); 2036 return -EAGAIN; 2037 } 2038 2039 int bnx2x_release_leader_lock(struct bnx2x *bp) 2040 { 2041 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 2042 } 2043 2044 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 2045 { 2046 u32 lock_status; 2047 u32 resource_bit = (1 << resource); 2048 int func = BP_FUNC(bp); 2049 u32 hw_lock_control_reg; 2050 2051 /* Validating that the resource is within range */ 2052 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 2053 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 2054 resource, HW_LOCK_MAX_RESOURCE_VALUE); 2055 return -EINVAL; 2056 } 2057 2058 if (func <= 5) { 2059 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 2060 } else { 2061 hw_lock_control_reg = 2062 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 2063 } 2064 2065 /* Validating that the resource is currently taken */ 2066 lock_status = REG_RD(bp, hw_lock_control_reg); 2067 if (!(lock_status & resource_bit)) { 2068 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", 2069 lock_status, resource_bit); 2070 return -EFAULT; 2071 } 2072 2073 REG_WR(bp, hw_lock_control_reg, resource_bit); 2074 return 0; 2075 } 2076 2077 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 2078 { 2079 /* The GPIO should be swapped if swap register is set and active */ 2080 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2081 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2082 int gpio_shift = gpio_num + 2083 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2084 u32 gpio_mask = (1 << gpio_shift); 2085 u32 gpio_reg; 2086 int value; 2087 2088 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2089 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2090 return -EINVAL; 2091 } 2092 2093 /* read GPIO value */ 2094 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2095 2096 /* get the requested pin value */ 2097 if ((gpio_reg & gpio_mask) == gpio_mask) 2098 value = 1; 2099 else 2100 value = 0; 2101 2102 return value; 2103 } 2104 2105 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2106 { 2107 /* The GPIO should be swapped if swap register is set and active */ 2108 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2109 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2110 int gpio_shift = gpio_num + 2111 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2112 u32 gpio_mask = (1 << gpio_shift); 2113 u32 gpio_reg; 2114 2115 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2116 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2117 return -EINVAL; 2118 } 2119 2120 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2121 /* read GPIO and mask except the float bits */ 2122 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2123 2124 switch (mode) { 2125 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2126 DP(NETIF_MSG_LINK, 2127 "Set GPIO %d (shift %d) -> output low\n", 2128 gpio_num, gpio_shift); 2129 /* clear FLOAT and set CLR */ 2130 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2131 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2132 break; 2133 2134 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2135 DP(NETIF_MSG_LINK, 2136 "Set GPIO %d (shift %d) -> output high\n", 2137 gpio_num, gpio_shift); 2138 /* clear FLOAT and set SET */ 2139 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2140 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2141 break; 2142 2143 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2144 DP(NETIF_MSG_LINK, 2145 "Set GPIO %d (shift %d) -> input\n", 2146 gpio_num, gpio_shift); 2147 /* set FLOAT */ 2148 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2149 break; 2150 2151 default: 2152 break; 2153 } 2154 2155 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2156 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2157 2158 return 0; 2159 } 2160 2161 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 2162 { 2163 u32 gpio_reg = 0; 2164 int rc = 0; 2165 2166 /* Any port swapping should be handled by caller. */ 2167 2168 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2169 /* read GPIO and mask except the float bits */ 2170 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2171 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2172 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2173 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2174 2175 switch (mode) { 2176 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2177 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2178 /* set CLR */ 2179 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2180 break; 2181 2182 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2183 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2184 /* set SET */ 2185 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2186 break; 2187 2188 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2189 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2190 /* set FLOAT */ 2191 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2192 break; 2193 2194 default: 2195 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2196 rc = -EINVAL; 2197 break; 2198 } 2199 2200 if (rc == 0) 2201 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2202 2203 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2204 2205 return rc; 2206 } 2207 2208 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2209 { 2210 /* The GPIO should be swapped if swap register is set and active */ 2211 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2212 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2213 int gpio_shift = gpio_num + 2214 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2215 u32 gpio_mask = (1 << gpio_shift); 2216 u32 gpio_reg; 2217 2218 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2219 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2220 return -EINVAL; 2221 } 2222 2223 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2224 /* read GPIO int */ 2225 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2226 2227 switch (mode) { 2228 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2229 DP(NETIF_MSG_LINK, 2230 "Clear GPIO INT %d (shift %d) -> output low\n", 2231 gpio_num, gpio_shift); 2232 /* clear SET and set CLR */ 2233 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2234 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2235 break; 2236 2237 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2238 DP(NETIF_MSG_LINK, 2239 "Set GPIO INT %d (shift %d) -> output high\n", 2240 gpio_num, gpio_shift); 2241 /* clear CLR and set SET */ 2242 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2243 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2244 break; 2245 2246 default: 2247 break; 2248 } 2249 2250 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2251 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2252 2253 return 0; 2254 } 2255 2256 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) 2257 { 2258 u32 spio_reg; 2259 2260 /* Only 2 SPIOs are configurable */ 2261 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 2262 BNX2X_ERR("Invalid SPIO 0x%x\n", spio); 2263 return -EINVAL; 2264 } 2265 2266 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2267 /* read SPIO and mask except the float bits */ 2268 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 2269 2270 switch (mode) { 2271 case MISC_SPIO_OUTPUT_LOW: 2272 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); 2273 /* clear FLOAT and set CLR */ 2274 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2275 spio_reg |= (spio << MISC_SPIO_CLR_POS); 2276 break; 2277 2278 case MISC_SPIO_OUTPUT_HIGH: 2279 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); 2280 /* clear FLOAT and set SET */ 2281 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2282 spio_reg |= (spio << MISC_SPIO_SET_POS); 2283 break; 2284 2285 case MISC_SPIO_INPUT_HI_Z: 2286 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); 2287 /* set FLOAT */ 2288 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 2289 break; 2290 2291 default: 2292 break; 2293 } 2294 2295 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2296 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2297 2298 return 0; 2299 } 2300 2301 void bnx2x_calc_fc_adv(struct bnx2x *bp) 2302 { 2303 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2304 2305 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2306 ADVERTISED_Pause); 2307 switch (bp->link_vars.ieee_fc & 2308 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2309 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2310 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2311 ADVERTISED_Pause); 2312 break; 2313 2314 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2315 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2316 break; 2317 2318 default: 2319 break; 2320 } 2321 } 2322 2323 static void bnx2x_set_requested_fc(struct bnx2x *bp) 2324 { 2325 /* Initialize link parameters structure variables 2326 * It is recommended to turn off RX FC for jumbo frames 2327 * for better performance 2328 */ 2329 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2330 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2331 else 2332 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2333 } 2334 2335 static void bnx2x_init_dropless_fc(struct bnx2x *bp) 2336 { 2337 u32 pause_enabled = 0; 2338 2339 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { 2340 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2341 pause_enabled = 1; 2342 2343 REG_WR(bp, BAR_USTRORM_INTMEM + 2344 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), 2345 pause_enabled); 2346 } 2347 2348 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", 2349 pause_enabled ? "enabled" : "disabled"); 2350 } 2351 2352 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2353 { 2354 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); 2355 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2356 2357 if (!BP_NOMCP(bp)) { 2358 bnx2x_set_requested_fc(bp); 2359 bnx2x_acquire_phy_lock(bp); 2360 2361 if (load_mode == LOAD_DIAG) { 2362 struct link_params *lp = &bp->link_params; 2363 lp->loopback_mode = LOOPBACK_XGXS; 2364 /* Prefer doing PHY loopback at highest speed */ 2365 if (lp->req_line_speed[cfx_idx] < SPEED_20000) { 2366 if (lp->speed_cap_mask[cfx_idx] & 2367 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 2368 lp->req_line_speed[cfx_idx] = 2369 SPEED_20000; 2370 else if (lp->speed_cap_mask[cfx_idx] & 2371 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2372 lp->req_line_speed[cfx_idx] = 2373 SPEED_10000; 2374 else 2375 lp->req_line_speed[cfx_idx] = 2376 SPEED_1000; 2377 } 2378 } 2379 2380 if (load_mode == LOAD_LOOPBACK_EXT) { 2381 struct link_params *lp = &bp->link_params; 2382 lp->loopback_mode = LOOPBACK_EXT; 2383 } 2384 2385 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2386 2387 bnx2x_release_phy_lock(bp); 2388 2389 bnx2x_init_dropless_fc(bp); 2390 2391 bnx2x_calc_fc_adv(bp); 2392 2393 if (bp->link_vars.link_up) { 2394 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2395 bnx2x_link_report(bp); 2396 } 2397 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2398 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2399 return rc; 2400 } 2401 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2402 return -EINVAL; 2403 } 2404 2405 void bnx2x_link_set(struct bnx2x *bp) 2406 { 2407 if (!BP_NOMCP(bp)) { 2408 bnx2x_acquire_phy_lock(bp); 2409 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2410 bnx2x_release_phy_lock(bp); 2411 2412 bnx2x_init_dropless_fc(bp); 2413 2414 bnx2x_calc_fc_adv(bp); 2415 } else 2416 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2417 } 2418 2419 static void bnx2x__link_reset(struct bnx2x *bp) 2420 { 2421 if (!BP_NOMCP(bp)) { 2422 bnx2x_acquire_phy_lock(bp); 2423 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); 2424 bnx2x_release_phy_lock(bp); 2425 } else 2426 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2427 } 2428 2429 void bnx2x_force_link_reset(struct bnx2x *bp) 2430 { 2431 bnx2x_acquire_phy_lock(bp); 2432 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2433 bnx2x_release_phy_lock(bp); 2434 } 2435 2436 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2437 { 2438 u8 rc = 0; 2439 2440 if (!BP_NOMCP(bp)) { 2441 bnx2x_acquire_phy_lock(bp); 2442 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2443 is_serdes); 2444 bnx2x_release_phy_lock(bp); 2445 } else 2446 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2447 2448 return rc; 2449 } 2450 2451 /* Calculates the sum of vn_min_rates. 2452 It's needed for further normalizing of the min_rates. 2453 Returns: 2454 sum of vn_min_rates. 2455 or 2456 0 - if all the min_rates are 0. 2457 In the later case fairness algorithm should be deactivated. 2458 If not all min_rates are zero then those that are zeroes will be set to 1. 2459 */ 2460 static void bnx2x_calc_vn_min(struct bnx2x *bp, 2461 struct cmng_init_input *input) 2462 { 2463 int all_zero = 1; 2464 int vn; 2465 2466 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2467 u32 vn_cfg = bp->mf_config[vn]; 2468 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2469 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2470 2471 /* Skip hidden vns */ 2472 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2473 vn_min_rate = 0; 2474 /* If min rate is zero - set it to 1 */ 2475 else if (!vn_min_rate) 2476 vn_min_rate = DEF_MIN_RATE; 2477 else 2478 all_zero = 0; 2479 2480 input->vnic_min_rate[vn] = vn_min_rate; 2481 } 2482 2483 /* if ETS or all min rates are zeros - disable fairness */ 2484 if (BNX2X_IS_ETS_ENABLED(bp)) { 2485 input->flags.cmng_enables &= 2486 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2487 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2488 } else if (all_zero) { 2489 input->flags.cmng_enables &= 2490 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2491 DP(NETIF_MSG_IFUP, 2492 "All MIN values are zeroes fairness will be disabled\n"); 2493 } else 2494 input->flags.cmng_enables |= 2495 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2496 } 2497 2498 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, 2499 struct cmng_init_input *input) 2500 { 2501 u16 vn_max_rate; 2502 u32 vn_cfg = bp->mf_config[vn]; 2503 2504 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2505 vn_max_rate = 0; 2506 else { 2507 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2508 2509 if (IS_MF_PERCENT_BW(bp)) { 2510 /* maxCfg in percents of linkspeed */ 2511 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2512 } else /* SD modes */ 2513 /* maxCfg is absolute in 100Mb units */ 2514 vn_max_rate = maxCfg * 100; 2515 } 2516 2517 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 2518 2519 input->vnic_max_rate[vn] = vn_max_rate; 2520 } 2521 2522 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2523 { 2524 if (CHIP_REV_IS_SLOW(bp)) 2525 return CMNG_FNS_NONE; 2526 if (IS_MF(bp)) 2527 return CMNG_FNS_MINMAX; 2528 2529 return CMNG_FNS_NONE; 2530 } 2531 2532 void bnx2x_read_mf_cfg(struct bnx2x *bp) 2533 { 2534 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2535 2536 if (BP_NOMCP(bp)) 2537 return; /* what should be the default value in this case */ 2538 2539 /* For 2 port configuration the absolute function number formula 2540 * is: 2541 * abs_func = 2 * vn + BP_PORT + BP_PATH 2542 * 2543 * and there are 4 functions per port 2544 * 2545 * For 4 port configuration it is 2546 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2547 * 2548 * and there are 2 functions per port 2549 */ 2550 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2551 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2552 2553 if (func >= E1H_FUNC_MAX) 2554 break; 2555 2556 bp->mf_config[vn] = 2557 MF_CFG_RD(bp, func_mf_config[func].config); 2558 } 2559 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2560 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); 2561 bp->flags |= MF_FUNC_DIS; 2562 } else { 2563 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2564 bp->flags &= ~MF_FUNC_DIS; 2565 } 2566 } 2567 2568 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2569 { 2570 struct cmng_init_input input; 2571 memset(&input, 0, sizeof(struct cmng_init_input)); 2572 2573 input.port_rate = bp->link_vars.line_speed; 2574 2575 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { 2576 int vn; 2577 2578 /* read mf conf from shmem */ 2579 if (read_cfg) 2580 bnx2x_read_mf_cfg(bp); 2581 2582 /* vn_weight_sum and enable fairness if not 0 */ 2583 bnx2x_calc_vn_min(bp, &input); 2584 2585 /* calculate and set min-max rate for each vn */ 2586 if (bp->port.pmf) 2587 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2588 bnx2x_calc_vn_max(bp, vn, &input); 2589 2590 /* always enable rate shaping and fairness */ 2591 input.flags.cmng_enables |= 2592 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2593 2594 bnx2x_init_cmng(&input, &bp->cmng); 2595 return; 2596 } 2597 2598 /* rate shaping and fairness are disabled */ 2599 DP(NETIF_MSG_IFUP, 2600 "rate shaping and fairness are disabled\n"); 2601 } 2602 2603 static void storm_memset_cmng(struct bnx2x *bp, 2604 struct cmng_init *cmng, 2605 u8 port) 2606 { 2607 int vn; 2608 size_t size = sizeof(struct cmng_struct_per_port); 2609 2610 u32 addr = BAR_XSTRORM_INTMEM + 2611 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 2612 2613 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); 2614 2615 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2616 int func = func_by_vn(bp, vn); 2617 2618 addr = BAR_XSTRORM_INTMEM + 2619 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); 2620 size = sizeof(struct rate_shaping_vars_per_vn); 2621 __storm_memset_struct(bp, addr, size, 2622 (u32 *)&cmng->vnic.vnic_max_rate[vn]); 2623 2624 addr = BAR_XSTRORM_INTMEM + 2625 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); 2626 size = sizeof(struct fairness_vars_per_vn); 2627 __storm_memset_struct(bp, addr, size, 2628 (u32 *)&cmng->vnic.vnic_min_rate[vn]); 2629 } 2630 } 2631 2632 /* init cmng mode in HW according to local configuration */ 2633 void bnx2x_set_local_cmng(struct bnx2x *bp) 2634 { 2635 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2636 2637 if (cmng_fns != CMNG_FNS_NONE) { 2638 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2639 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2640 } else { 2641 /* rate shaping and fairness are disabled */ 2642 DP(NETIF_MSG_IFUP, 2643 "single function mode without fairness\n"); 2644 } 2645 } 2646 2647 /* This function is called upon link interrupt */ 2648 static void bnx2x_link_attn(struct bnx2x *bp) 2649 { 2650 /* Make sure that we are synced with the current statistics */ 2651 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2652 2653 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2654 2655 bnx2x_init_dropless_fc(bp); 2656 2657 if (bp->link_vars.link_up) { 2658 2659 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2660 struct host_port_stats *pstats; 2661 2662 pstats = bnx2x_sp(bp, port_stats); 2663 /* reset old mac stats */ 2664 memset(&(pstats->mac_stx[0]), 0, 2665 sizeof(struct mac_stx)); 2666 } 2667 if (bp->state == BNX2X_STATE_OPEN) 2668 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2669 } 2670 2671 if (bp->link_vars.link_up && bp->link_vars.line_speed) 2672 bnx2x_set_local_cmng(bp); 2673 2674 __bnx2x_link_report(bp); 2675 2676 if (IS_MF(bp)) 2677 bnx2x_link_sync_notify(bp); 2678 } 2679 2680 void bnx2x__link_status_update(struct bnx2x *bp) 2681 { 2682 if (bp->state != BNX2X_STATE_OPEN) 2683 return; 2684 2685 /* read updated dcb configuration */ 2686 if (IS_PF(bp)) { 2687 bnx2x_dcbx_pmf_update(bp); 2688 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2689 if (bp->link_vars.link_up) 2690 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2691 else 2692 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2693 /* indicate link status */ 2694 bnx2x_link_report(bp); 2695 2696 } else { /* VF */ 2697 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | 2698 SUPPORTED_10baseT_Full | 2699 SUPPORTED_100baseT_Half | 2700 SUPPORTED_100baseT_Full | 2701 SUPPORTED_1000baseT_Full | 2702 SUPPORTED_2500baseX_Full | 2703 SUPPORTED_10000baseT_Full | 2704 SUPPORTED_TP | 2705 SUPPORTED_FIBRE | 2706 SUPPORTED_Autoneg | 2707 SUPPORTED_Pause | 2708 SUPPORTED_Asym_Pause); 2709 bp->port.advertising[0] = bp->port.supported[0]; 2710 2711 bp->link_params.bp = bp; 2712 bp->link_params.port = BP_PORT(bp); 2713 bp->link_params.req_duplex[0] = DUPLEX_FULL; 2714 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; 2715 bp->link_params.req_line_speed[0] = SPEED_10000; 2716 bp->link_params.speed_cap_mask[0] = 0x7f0000; 2717 bp->link_params.switch_cfg = SWITCH_CFG_10G; 2718 bp->link_vars.mac_type = MAC_TYPE_BMAC; 2719 bp->link_vars.line_speed = SPEED_10000; 2720 bp->link_vars.link_status = 2721 (LINK_STATUS_LINK_UP | 2722 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 2723 bp->link_vars.link_up = 1; 2724 bp->link_vars.duplex = DUPLEX_FULL; 2725 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; 2726 __bnx2x_link_report(bp); 2727 2728 bnx2x_sample_bulletin(bp); 2729 2730 /* if bulletin board did not have an update for link status 2731 * __bnx2x_link_report will report current status 2732 * but it will NOT duplicate report in case of already reported 2733 * during sampling bulletin board. 2734 */ 2735 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2736 } 2737 } 2738 2739 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, 2740 u16 vlan_val, u8 allowed_prio) 2741 { 2742 struct bnx2x_func_state_params func_params = {NULL}; 2743 struct bnx2x_func_afex_update_params *f_update_params = 2744 &func_params.params.afex_update; 2745 2746 func_params.f_obj = &bp->func_obj; 2747 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; 2748 2749 /* no need to wait for RAMROD completion, so don't 2750 * set RAMROD_COMP_WAIT flag 2751 */ 2752 2753 f_update_params->vif_id = vifid; 2754 f_update_params->afex_default_vlan = vlan_val; 2755 f_update_params->allowed_priorities = allowed_prio; 2756 2757 /* if ramrod can not be sent, response to MCP immediately */ 2758 if (bnx2x_func_state_change(bp, &func_params) < 0) 2759 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 2760 2761 return 0; 2762 } 2763 2764 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, 2765 u16 vif_index, u8 func_bit_map) 2766 { 2767 struct bnx2x_func_state_params func_params = {NULL}; 2768 struct bnx2x_func_afex_viflists_params *update_params = 2769 &func_params.params.afex_viflists; 2770 int rc; 2771 u32 drv_msg_code; 2772 2773 /* validate only LIST_SET and LIST_GET are received from switch */ 2774 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) 2775 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", 2776 cmd_type); 2777 2778 func_params.f_obj = &bp->func_obj; 2779 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; 2780 2781 /* set parameters according to cmd_type */ 2782 update_params->afex_vif_list_command = cmd_type; 2783 update_params->vif_list_index = vif_index; 2784 update_params->func_bit_map = 2785 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; 2786 update_params->func_to_clear = 0; 2787 drv_msg_code = 2788 (cmd_type == VIF_LIST_RULE_GET) ? 2789 DRV_MSG_CODE_AFEX_LISTGET_ACK : 2790 DRV_MSG_CODE_AFEX_LISTSET_ACK; 2791 2792 /* if ramrod can not be sent, respond to MCP immediately for 2793 * SET and GET requests (other are not triggered from MCP) 2794 */ 2795 rc = bnx2x_func_state_change(bp, &func_params); 2796 if (rc < 0) 2797 bnx2x_fw_command(bp, drv_msg_code, 0); 2798 2799 return 0; 2800 } 2801 2802 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) 2803 { 2804 struct afex_stats afex_stats; 2805 u32 func = BP_ABS_FUNC(bp); 2806 u32 mf_config; 2807 u16 vlan_val; 2808 u32 vlan_prio; 2809 u16 vif_id; 2810 u8 allowed_prio; 2811 u8 vlan_mode; 2812 u32 addr_to_write, vifid, addrs, stats_type, i; 2813 2814 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { 2815 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2816 DP(BNX2X_MSG_MCP, 2817 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); 2818 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); 2819 } 2820 2821 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { 2822 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2823 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); 2824 DP(BNX2X_MSG_MCP, 2825 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", 2826 vifid, addrs); 2827 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, 2828 addrs); 2829 } 2830 2831 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { 2832 addr_to_write = SHMEM2_RD(bp, 2833 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); 2834 stats_type = SHMEM2_RD(bp, 2835 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2836 2837 DP(BNX2X_MSG_MCP, 2838 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", 2839 addr_to_write); 2840 2841 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); 2842 2843 /* write response to scratchpad, for MCP */ 2844 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) 2845 REG_WR(bp, addr_to_write + i*sizeof(u32), 2846 *(((u32 *)(&afex_stats))+i)); 2847 2848 /* send ack message to MCP */ 2849 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); 2850 } 2851 2852 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { 2853 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); 2854 bp->mf_config[BP_VN(bp)] = mf_config; 2855 DP(BNX2X_MSG_MCP, 2856 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", 2857 mf_config); 2858 2859 /* if VIF_SET is "enabled" */ 2860 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { 2861 /* set rate limit directly to internal RAM */ 2862 struct cmng_init_input cmng_input; 2863 struct rate_shaping_vars_per_vn m_rs_vn; 2864 size_t size = sizeof(struct rate_shaping_vars_per_vn); 2865 u32 addr = BAR_XSTRORM_INTMEM + 2866 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); 2867 2868 bp->mf_config[BP_VN(bp)] = mf_config; 2869 2870 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); 2871 m_rs_vn.vn_counter.rate = 2872 cmng_input.vnic_max_rate[BP_VN(bp)]; 2873 m_rs_vn.vn_counter.quota = 2874 (m_rs_vn.vn_counter.rate * 2875 RS_PERIODIC_TIMEOUT_USEC) / 8; 2876 2877 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); 2878 2879 /* read relevant values from mf_cfg struct in shmem */ 2880 vif_id = 2881 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2882 FUNC_MF_CFG_E1HOV_TAG_MASK) >> 2883 FUNC_MF_CFG_E1HOV_TAG_SHIFT; 2884 vlan_val = 2885 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2886 FUNC_MF_CFG_AFEX_VLAN_MASK) >> 2887 FUNC_MF_CFG_AFEX_VLAN_SHIFT; 2888 vlan_prio = (mf_config & 2889 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 2890 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; 2891 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); 2892 vlan_mode = 2893 (MF_CFG_RD(bp, 2894 func_mf_config[func].afex_config) & 2895 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 2896 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; 2897 allowed_prio = 2898 (MF_CFG_RD(bp, 2899 func_mf_config[func].afex_config) & 2900 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 2901 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; 2902 2903 /* send ramrod to FW, return in case of failure */ 2904 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, 2905 allowed_prio)) 2906 return; 2907 2908 bp->afex_def_vlan_tag = vlan_val; 2909 bp->afex_vlan_mode = vlan_mode; 2910 } else { 2911 /* notify link down because BP->flags is disabled */ 2912 bnx2x_link_report(bp); 2913 2914 /* send INVALID VIF ramrod to FW */ 2915 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); 2916 2917 /* Reset the default afex VLAN */ 2918 bp->afex_def_vlan_tag = -1; 2919 } 2920 } 2921 } 2922 2923 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) 2924 { 2925 struct bnx2x_func_switch_update_params *switch_update_params; 2926 struct bnx2x_func_state_params func_params; 2927 2928 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); 2929 switch_update_params = &func_params.params.switch_update; 2930 func_params.f_obj = &bp->func_obj; 2931 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 2932 2933 /* Prepare parameters for function state transitions */ 2934 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 2935 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 2936 2937 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { 2938 int func = BP_ABS_FUNC(bp); 2939 u32 val; 2940 2941 /* Re-learn the S-tag from shmem */ 2942 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2943 FUNC_MF_CFG_E1HOV_TAG_MASK; 2944 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 2945 bp->mf_ov = val; 2946 } else { 2947 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); 2948 goto fail; 2949 } 2950 2951 /* Configure new S-tag in LLH */ 2952 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, 2953 bp->mf_ov); 2954 2955 /* Send Ramrod to update FW of change */ 2956 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, 2957 &switch_update_params->changes); 2958 switch_update_params->vlan = bp->mf_ov; 2959 2960 if (bnx2x_func_state_change(bp, &func_params) < 0) { 2961 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", 2962 bp->mf_ov); 2963 goto fail; 2964 } else { 2965 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", 2966 bp->mf_ov); 2967 } 2968 } else { 2969 goto fail; 2970 } 2971 2972 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); 2973 return; 2974 fail: 2975 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); 2976 } 2977 2978 static void bnx2x_pmf_update(struct bnx2x *bp) 2979 { 2980 int port = BP_PORT(bp); 2981 u32 val; 2982 2983 bp->port.pmf = 1; 2984 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2985 2986 /* 2987 * We need the mb() to ensure the ordering between the writing to 2988 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2989 */ 2990 smp_mb(); 2991 2992 /* queue a periodic task */ 2993 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2994 2995 bnx2x_dcbx_pmf_update(bp); 2996 2997 /* enable nig attention */ 2998 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 2999 if (bp->common.int_block == INT_BLOCK_HC) { 3000 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 3001 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 3002 } else if (!CHIP_IS_E1x(bp)) { 3003 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 3004 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 3005 } 3006 3007 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 3008 } 3009 3010 /* end of Link */ 3011 3012 /* slow path */ 3013 3014 /* 3015 * General service functions 3016 */ 3017 3018 /* send the MCP a request, block until there is a reply */ 3019 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 3020 { 3021 int mb_idx = BP_FW_MB_IDX(bp); 3022 u32 seq; 3023 u32 rc = 0; 3024 u32 cnt = 1; 3025 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 3026 3027 mutex_lock(&bp->fw_mb_mutex); 3028 seq = ++bp->fw_seq; 3029 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 3030 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 3031 3032 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 3033 (command | seq), param); 3034 3035 do { 3036 /* let the FW do it's magic ... */ 3037 msleep(delay); 3038 3039 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 3040 3041 /* Give the FW up to 5 second (500*10ms) */ 3042 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 3043 3044 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 3045 cnt*delay, rc, seq); 3046 3047 /* is this a reply to our command? */ 3048 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 3049 rc &= FW_MSG_CODE_MASK; 3050 else { 3051 /* FW BUG! */ 3052 BNX2X_ERR("FW failed to respond!\n"); 3053 bnx2x_fw_dump(bp); 3054 rc = 0; 3055 } 3056 mutex_unlock(&bp->fw_mb_mutex); 3057 3058 return rc; 3059 } 3060 3061 static void storm_memset_func_cfg(struct bnx2x *bp, 3062 struct tstorm_eth_function_common_config *tcfg, 3063 u16 abs_fid) 3064 { 3065 size_t size = sizeof(struct tstorm_eth_function_common_config); 3066 3067 u32 addr = BAR_TSTRORM_INTMEM + 3068 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 3069 3070 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 3071 } 3072 3073 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 3074 { 3075 if (CHIP_IS_E1x(bp)) { 3076 struct tstorm_eth_function_common_config tcfg = {0}; 3077 3078 storm_memset_func_cfg(bp, &tcfg, p->func_id); 3079 } 3080 3081 /* Enable the function in the FW */ 3082 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 3083 storm_memset_func_en(bp, p->func_id, 1); 3084 3085 /* spq */ 3086 if (p->spq_active) { 3087 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 3088 REG_WR(bp, XSEM_REG_FAST_MEMORY + 3089 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 3090 } 3091 } 3092 3093 /** 3094 * bnx2x_get_common_flags - Return common flags 3095 * 3096 * @bp: device handle 3097 * @fp: queue handle 3098 * @zero_stats: TRUE if statistics zeroing is needed 3099 * 3100 * Return the flags that are common for the Tx-only and not normal connections. 3101 */ 3102 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 3103 struct bnx2x_fastpath *fp, 3104 bool zero_stats) 3105 { 3106 unsigned long flags = 0; 3107 3108 /* PF driver will always initialize the Queue to an ACTIVE state */ 3109 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 3110 3111 /* tx only connections collect statistics (on the same index as the 3112 * parent connection). The statistics are zeroed when the parent 3113 * connection is initialized. 3114 */ 3115 3116 __set_bit(BNX2X_Q_FLG_STATS, &flags); 3117 if (zero_stats) 3118 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 3119 3120 if (bp->flags & TX_SWITCHING) 3121 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags); 3122 3123 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); 3124 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); 3125 3126 #ifdef BNX2X_STOP_ON_ERROR 3127 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); 3128 #endif 3129 3130 return flags; 3131 } 3132 3133 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 3134 struct bnx2x_fastpath *fp, 3135 bool leading) 3136 { 3137 unsigned long flags = 0; 3138 3139 /* calculate other queue flags */ 3140 if (IS_MF_SD(bp)) 3141 __set_bit(BNX2X_Q_FLG_OV, &flags); 3142 3143 if (IS_FCOE_FP(fp)) { 3144 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 3145 /* For FCoE - force usage of default priority (for afex) */ 3146 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); 3147 } 3148 3149 if (fp->mode != TPA_MODE_DISABLED) { 3150 __set_bit(BNX2X_Q_FLG_TPA, &flags); 3151 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 3152 if (fp->mode == TPA_MODE_GRO) 3153 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 3154 } 3155 3156 if (leading) { 3157 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 3158 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 3159 } 3160 3161 /* Always set HW VLAN stripping */ 3162 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 3163 3164 /* configure silent vlan removal */ 3165 if (IS_MF_AFEX(bp)) 3166 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); 3167 3168 return flags | bnx2x_get_common_flags(bp, fp, true); 3169 } 3170 3171 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 3172 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 3173 u8 cos) 3174 { 3175 gen_init->stat_id = bnx2x_stats_id(fp); 3176 gen_init->spcl_id = fp->cl_id; 3177 3178 /* Always use mini-jumbo MTU for FCoE L2 ring */ 3179 if (IS_FCOE_FP(fp)) 3180 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 3181 else 3182 gen_init->mtu = bp->dev->mtu; 3183 3184 gen_init->cos = cos; 3185 3186 gen_init->fp_hsi = ETH_FP_HSI_VERSION; 3187 } 3188 3189 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 3190 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 3191 struct bnx2x_rxq_setup_params *rxq_init) 3192 { 3193 u8 max_sge = 0; 3194 u16 sge_sz = 0; 3195 u16 tpa_agg_size = 0; 3196 3197 if (fp->mode != TPA_MODE_DISABLED) { 3198 pause->sge_th_lo = SGE_TH_LO(bp); 3199 pause->sge_th_hi = SGE_TH_HI(bp); 3200 3201 /* validate SGE ring has enough to cross high threshold */ 3202 WARN_ON(bp->dropless_fc && 3203 pause->sge_th_hi + FW_PREFETCH_CNT > 3204 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 3205 3206 tpa_agg_size = TPA_AGG_SIZE; 3207 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 3208 SGE_PAGE_SHIFT; 3209 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 3210 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 3211 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); 3212 } 3213 3214 /* pause - not for e1 */ 3215 if (!CHIP_IS_E1(bp)) { 3216 pause->bd_th_lo = BD_TH_LO(bp); 3217 pause->bd_th_hi = BD_TH_HI(bp); 3218 3219 pause->rcq_th_lo = RCQ_TH_LO(bp); 3220 pause->rcq_th_hi = RCQ_TH_HI(bp); 3221 /* 3222 * validate that rings have enough entries to cross 3223 * high thresholds 3224 */ 3225 WARN_ON(bp->dropless_fc && 3226 pause->bd_th_hi + FW_PREFETCH_CNT > 3227 bp->rx_ring_size); 3228 WARN_ON(bp->dropless_fc && 3229 pause->rcq_th_hi + FW_PREFETCH_CNT > 3230 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 3231 3232 pause->pri_map = 1; 3233 } 3234 3235 /* rxq setup */ 3236 rxq_init->dscr_map = fp->rx_desc_mapping; 3237 rxq_init->sge_map = fp->rx_sge_mapping; 3238 rxq_init->rcq_map = fp->rx_comp_mapping; 3239 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 3240 3241 /* This should be a maximum number of data bytes that may be 3242 * placed on the BD (not including paddings). 3243 */ 3244 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 3245 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 3246 3247 rxq_init->cl_qzone_id = fp->cl_qzone_id; 3248 rxq_init->tpa_agg_sz = tpa_agg_size; 3249 rxq_init->sge_buf_sz = sge_sz; 3250 rxq_init->max_sges_pkt = max_sge; 3251 rxq_init->rss_engine_id = BP_FUNC(bp); 3252 rxq_init->mcast_engine_id = BP_FUNC(bp); 3253 3254 /* Maximum number or simultaneous TPA aggregation for this Queue. 3255 * 3256 * For PF Clients it should be the maximum available number. 3257 * VF driver(s) may want to define it to a smaller value. 3258 */ 3259 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 3260 3261 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 3262 rxq_init->fw_sb_id = fp->fw_sb_id; 3263 3264 if (IS_FCOE_FP(fp)) 3265 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 3266 else 3267 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 3268 /* configure silent vlan removal 3269 * if multi function mode is afex, then mask default vlan 3270 */ 3271 if (IS_MF_AFEX(bp)) { 3272 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; 3273 rxq_init->silent_removal_mask = VLAN_VID_MASK; 3274 } 3275 } 3276 3277 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 3278 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 3279 u8 cos) 3280 { 3281 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; 3282 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 3283 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 3284 txq_init->fw_sb_id = fp->fw_sb_id; 3285 3286 /* 3287 * set the tss leading client id for TX classification == 3288 * leading RSS client id 3289 */ 3290 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 3291 3292 if (IS_FCOE_FP(fp)) { 3293 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 3294 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 3295 } 3296 } 3297 3298 static void bnx2x_pf_init(struct bnx2x *bp) 3299 { 3300 struct bnx2x_func_init_params func_init = {0}; 3301 struct event_ring_data eq_data = { {0} }; 3302 3303 if (!CHIP_IS_E1x(bp)) { 3304 /* reset IGU PF statistics: MSIX + ATTN */ 3305 /* PF */ 3306 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3307 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3308 (CHIP_MODE_IS_4_PORT(bp) ? 3309 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3310 /* ATTN */ 3311 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3312 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3313 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 3314 (CHIP_MODE_IS_4_PORT(bp) ? 3315 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3316 } 3317 3318 func_init.spq_active = true; 3319 func_init.pf_id = BP_FUNC(bp); 3320 func_init.func_id = BP_FUNC(bp); 3321 func_init.spq_map = bp->spq_mapping; 3322 func_init.spq_prod = bp->spq_prod_idx; 3323 3324 bnx2x_func_init(bp, &func_init); 3325 3326 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 3327 3328 /* 3329 * Congestion management values depend on the link rate 3330 * There is no active link so initial link rate is set to 10 Gbps. 3331 * When the link comes up The congestion management values are 3332 * re-calculated according to the actual link rate. 3333 */ 3334 bp->link_vars.line_speed = SPEED_10000; 3335 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 3336 3337 /* Only the PMF sets the HW */ 3338 if (bp->port.pmf) 3339 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3340 3341 /* init Event Queue - PCI bus guarantees correct endianity*/ 3342 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 3343 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 3344 eq_data.producer = bp->eq_prod; 3345 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 3346 eq_data.sb_id = DEF_SB_ID; 3347 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 3348 } 3349 3350 static void bnx2x_e1h_disable(struct bnx2x *bp) 3351 { 3352 int port = BP_PORT(bp); 3353 3354 bnx2x_tx_disable(bp); 3355 3356 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 3357 } 3358 3359 static void bnx2x_e1h_enable(struct bnx2x *bp) 3360 { 3361 int port = BP_PORT(bp); 3362 3363 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 3364 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); 3365 3366 /* Tx queue should be only re-enabled */ 3367 netif_tx_wake_all_queues(bp->dev); 3368 3369 /* 3370 * Should not call netif_carrier_on since it will be called if the link 3371 * is up when checking for link state 3372 */ 3373 } 3374 3375 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 3376 3377 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 3378 { 3379 struct eth_stats_info *ether_stat = 3380 &bp->slowpath->drv_info_to_mcp.ether_stat; 3381 struct bnx2x_vlan_mac_obj *mac_obj = 3382 &bp->sp_objs->mac_obj; 3383 int i; 3384 3385 strlcpy(ether_stat->version, DRV_MODULE_VERSION, 3386 ETH_STAT_INFO_VERSION_LEN); 3387 3388 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the 3389 * mac_local field in ether_stat struct. The base address is offset by 2 3390 * bytes to account for the field being 8 bytes but a mac address is 3391 * only 6 bytes. Likewise, the stride for the get_n_elements function is 3392 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes 3393 * allocated by the ether_stat struct, so the macs will land in their 3394 * proper positions. 3395 */ 3396 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) 3397 memset(ether_stat->mac_local + i, 0, 3398 sizeof(ether_stat->mac_local[0])); 3399 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, 3400 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 3401 ether_stat->mac_local + MAC_PAD, MAC_PAD, 3402 ETH_ALEN); 3403 ether_stat->mtu_size = bp->dev->mtu; 3404 if (bp->dev->features & NETIF_F_RXCSUM) 3405 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 3406 if (bp->dev->features & NETIF_F_TSO) 3407 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 3408 ether_stat->feature_flags |= bp->common.boot_mode; 3409 3410 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 3411 3412 ether_stat->txq_size = bp->tx_ring_size; 3413 ether_stat->rxq_size = bp->rx_ring_size; 3414 3415 #ifdef CONFIG_BNX2X_SRIOV 3416 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; 3417 #endif 3418 } 3419 3420 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 3421 { 3422 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3423 struct fcoe_stats_info *fcoe_stat = 3424 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 3425 3426 if (!CNIC_LOADED(bp)) 3427 return; 3428 3429 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); 3430 3431 fcoe_stat->qos_priority = 3432 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 3433 3434 /* insert FCoE stats from ramrod response */ 3435 if (!NO_FCOE(bp)) { 3436 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 3437 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3438 tstorm_queue_statistics; 3439 3440 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 3441 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3442 xstorm_queue_statistics; 3443 3444 struct fcoe_statistics_params *fw_fcoe_stat = 3445 &bp->fw_stats_data->fcoe; 3446 3447 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, 3448 fcoe_stat->rx_bytes_lo, 3449 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 3450 3451 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3452 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 3453 fcoe_stat->rx_bytes_lo, 3454 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 3455 3456 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3457 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 3458 fcoe_stat->rx_bytes_lo, 3459 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 3460 3461 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3462 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 3463 fcoe_stat->rx_bytes_lo, 3464 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 3465 3466 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3467 fcoe_stat->rx_frames_lo, 3468 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3469 3470 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3471 fcoe_stat->rx_frames_lo, 3472 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3473 3474 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3475 fcoe_stat->rx_frames_lo, 3476 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3477 3478 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3479 fcoe_stat->rx_frames_lo, 3480 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3481 3482 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, 3483 fcoe_stat->tx_bytes_lo, 3484 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3485 3486 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3487 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3488 fcoe_stat->tx_bytes_lo, 3489 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3490 3491 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3492 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3493 fcoe_stat->tx_bytes_lo, 3494 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3495 3496 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3497 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3498 fcoe_stat->tx_bytes_lo, 3499 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3500 3501 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3502 fcoe_stat->tx_frames_lo, 3503 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3504 3505 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3506 fcoe_stat->tx_frames_lo, 3507 fcoe_q_xstorm_stats->ucast_pkts_sent); 3508 3509 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3510 fcoe_stat->tx_frames_lo, 3511 fcoe_q_xstorm_stats->bcast_pkts_sent); 3512 3513 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3514 fcoe_stat->tx_frames_lo, 3515 fcoe_q_xstorm_stats->mcast_pkts_sent); 3516 } 3517 3518 /* ask L5 driver to add data to the struct */ 3519 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3520 } 3521 3522 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3523 { 3524 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3525 struct iscsi_stats_info *iscsi_stat = 3526 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3527 3528 if (!CNIC_LOADED(bp)) 3529 return; 3530 3531 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, 3532 ETH_ALEN); 3533 3534 iscsi_stat->qos_priority = 3535 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3536 3537 /* ask L5 driver to add data to the struct */ 3538 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3539 } 3540 3541 /* called due to MCP event (on pmf): 3542 * reread new bandwidth configuration 3543 * configure FW 3544 * notify others function about the change 3545 */ 3546 static void bnx2x_config_mf_bw(struct bnx2x *bp) 3547 { 3548 /* Workaround for MFW bug. 3549 * MFW is not supposed to generate BW attention in 3550 * single function mode. 3551 */ 3552 if (!IS_MF(bp)) { 3553 DP(BNX2X_MSG_MCP, 3554 "Ignoring MF BW config in single function mode\n"); 3555 return; 3556 } 3557 3558 if (bp->link_vars.link_up) { 3559 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3560 bnx2x_link_sync_notify(bp); 3561 } 3562 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3563 } 3564 3565 static void bnx2x_set_mf_bw(struct bnx2x *bp) 3566 { 3567 bnx2x_config_mf_bw(bp); 3568 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3569 } 3570 3571 static void bnx2x_handle_eee_event(struct bnx2x *bp) 3572 { 3573 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); 3574 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 3575 } 3576 3577 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20) 3578 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25) 3579 3580 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3581 { 3582 enum drv_info_opcode op_code; 3583 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3584 bool release = false; 3585 int wait; 3586 3587 /* if drv_info version supported by MFW doesn't match - send NACK */ 3588 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3589 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3590 return; 3591 } 3592 3593 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3594 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3595 3596 /* Must prevent other flows from accessing drv_info_to_mcp */ 3597 mutex_lock(&bp->drv_info_mutex); 3598 3599 memset(&bp->slowpath->drv_info_to_mcp, 0, 3600 sizeof(union drv_info_to_mcp)); 3601 3602 switch (op_code) { 3603 case ETH_STATS_OPCODE: 3604 bnx2x_drv_info_ether_stat(bp); 3605 break; 3606 case FCOE_STATS_OPCODE: 3607 bnx2x_drv_info_fcoe_stat(bp); 3608 break; 3609 case ISCSI_STATS_OPCODE: 3610 bnx2x_drv_info_iscsi_stat(bp); 3611 break; 3612 default: 3613 /* if op code isn't supported - send NACK */ 3614 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3615 goto out; 3616 } 3617 3618 /* if we got drv_info attn from MFW then these fields are defined in 3619 * shmem2 for sure 3620 */ 3621 SHMEM2_WR(bp, drv_info_host_addr_lo, 3622 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3623 SHMEM2_WR(bp, drv_info_host_addr_hi, 3624 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3625 3626 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3627 3628 /* Since possible management wants both this and get_driver_version 3629 * need to wait until management notifies us it finished utilizing 3630 * the buffer. 3631 */ 3632 if (!SHMEM2_HAS(bp, mfw_drv_indication)) { 3633 DP(BNX2X_MSG_MCP, "Management does not support indication\n"); 3634 } else if (!bp->drv_info_mng_owner) { 3635 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); 3636 3637 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { 3638 u32 indication = SHMEM2_RD(bp, mfw_drv_indication); 3639 3640 /* Management is done; need to clear indication */ 3641 if (indication & bit) { 3642 SHMEM2_WR(bp, mfw_drv_indication, 3643 indication & ~bit); 3644 release = true; 3645 break; 3646 } 3647 3648 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH); 3649 } 3650 } 3651 if (!release) { 3652 DP(BNX2X_MSG_MCP, "Management did not release indication\n"); 3653 bp->drv_info_mng_owner = true; 3654 } 3655 3656 out: 3657 mutex_unlock(&bp->drv_info_mutex); 3658 } 3659 3660 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format) 3661 { 3662 u8 vals[4]; 3663 int i = 0; 3664 3665 if (bnx2x_format) { 3666 i = sscanf(version, "1.%c%hhd.%hhd.%hhd", 3667 &vals[0], &vals[1], &vals[2], &vals[3]); 3668 if (i > 0) 3669 vals[0] -= '0'; 3670 } else { 3671 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd", 3672 &vals[0], &vals[1], &vals[2], &vals[3]); 3673 } 3674 3675 while (i < 4) 3676 vals[i++] = 0; 3677 3678 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; 3679 } 3680 3681 void bnx2x_update_mng_version(struct bnx2x *bp) 3682 { 3683 u32 iscsiver = DRV_VER_NOT_LOADED; 3684 u32 fcoever = DRV_VER_NOT_LOADED; 3685 u32 ethver = DRV_VER_NOT_LOADED; 3686 int idx = BP_FW_MB_IDX(bp); 3687 u8 *version; 3688 3689 if (!SHMEM2_HAS(bp, func_os_drv_ver)) 3690 return; 3691 3692 mutex_lock(&bp->drv_info_mutex); 3693 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */ 3694 if (bp->drv_info_mng_owner) 3695 goto out; 3696 3697 if (bp->state != BNX2X_STATE_OPEN) 3698 goto out; 3699 3700 /* Parse ethernet driver version */ 3701 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); 3702 if (!CNIC_LOADED(bp)) 3703 goto out; 3704 3705 /* Try getting storage driver version via cnic */ 3706 memset(&bp->slowpath->drv_info_to_mcp, 0, 3707 sizeof(union drv_info_to_mcp)); 3708 bnx2x_drv_info_iscsi_stat(bp); 3709 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; 3710 iscsiver = bnx2x_update_mng_version_utility(version, false); 3711 3712 memset(&bp->slowpath->drv_info_to_mcp, 0, 3713 sizeof(union drv_info_to_mcp)); 3714 bnx2x_drv_info_fcoe_stat(bp); 3715 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; 3716 fcoever = bnx2x_update_mng_version_utility(version, false); 3717 3718 out: 3719 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); 3720 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); 3721 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); 3722 3723 mutex_unlock(&bp->drv_info_mutex); 3724 3725 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", 3726 ethver, iscsiver, fcoever); 3727 } 3728 3729 void bnx2x_update_mfw_dump(struct bnx2x *bp) 3730 { 3731 u32 drv_ver; 3732 u32 valid_dump; 3733 3734 if (!SHMEM2_HAS(bp, drv_info)) 3735 return; 3736 3737 /* Update Driver load time, possibly broken in y2038 */ 3738 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); 3739 3740 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); 3741 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); 3742 3743 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); 3744 3745 /* Check & notify On-Chip dump. */ 3746 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); 3747 3748 if (valid_dump & FIRST_DUMP_VALID) 3749 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n"); 3750 3751 if (valid_dump & SECOND_DUMP_VALID) 3752 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n"); 3753 } 3754 3755 static void bnx2x_oem_event(struct bnx2x *bp, u32 event) 3756 { 3757 u32 cmd_ok, cmd_fail; 3758 3759 /* sanity */ 3760 if (event & DRV_STATUS_DCC_EVENT_MASK && 3761 event & DRV_STATUS_OEM_EVENT_MASK) { 3762 BNX2X_ERR("Received simultaneous events %08x\n", event); 3763 return; 3764 } 3765 3766 if (event & DRV_STATUS_DCC_EVENT_MASK) { 3767 cmd_fail = DRV_MSG_CODE_DCC_FAILURE; 3768 cmd_ok = DRV_MSG_CODE_DCC_OK; 3769 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ { 3770 cmd_fail = DRV_MSG_CODE_OEM_FAILURE; 3771 cmd_ok = DRV_MSG_CODE_OEM_OK; 3772 } 3773 3774 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); 3775 3776 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF | 3777 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { 3778 /* This is the only place besides the function initialization 3779 * where the bp->flags can change so it is done without any 3780 * locks 3781 */ 3782 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3783 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3784 bp->flags |= MF_FUNC_DIS; 3785 3786 bnx2x_e1h_disable(bp); 3787 } else { 3788 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3789 bp->flags &= ~MF_FUNC_DIS; 3790 3791 bnx2x_e1h_enable(bp); 3792 } 3793 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF | 3794 DRV_STATUS_OEM_DISABLE_ENABLE_PF); 3795 } 3796 3797 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | 3798 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) { 3799 bnx2x_config_mf_bw(bp); 3800 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | 3801 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION); 3802 } 3803 3804 /* Report results to MCP */ 3805 if (event) 3806 bnx2x_fw_command(bp, cmd_fail, 0); 3807 else 3808 bnx2x_fw_command(bp, cmd_ok, 0); 3809 } 3810 3811 /* must be called under the spq lock */ 3812 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3813 { 3814 struct eth_spe *next_spe = bp->spq_prod_bd; 3815 3816 if (bp->spq_prod_bd == bp->spq_last_bd) { 3817 bp->spq_prod_bd = bp->spq; 3818 bp->spq_prod_idx = 0; 3819 DP(BNX2X_MSG_SP, "end of spq\n"); 3820 } else { 3821 bp->spq_prod_bd++; 3822 bp->spq_prod_idx++; 3823 } 3824 return next_spe; 3825 } 3826 3827 /* must be called under the spq lock */ 3828 static void bnx2x_sp_prod_update(struct bnx2x *bp) 3829 { 3830 int func = BP_FUNC(bp); 3831 3832 /* 3833 * Make sure that BD data is updated before writing the producer: 3834 * BD data is written to the memory, the producer is read from the 3835 * memory, thus we need a full memory barrier to ensure the ordering. 3836 */ 3837 mb(); 3838 3839 REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3840 bp->spq_prod_idx); 3841 } 3842 3843 /** 3844 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3845 * 3846 * @cmd: command to check 3847 * @cmd_type: command type 3848 */ 3849 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3850 { 3851 if ((cmd_type == NONE_CONNECTION_TYPE) || 3852 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3853 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3854 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3855 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3856 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3857 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3858 return true; 3859 else 3860 return false; 3861 } 3862 3863 /** 3864 * bnx2x_sp_post - place a single command on an SP ring 3865 * 3866 * @bp: driver handle 3867 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3868 * @cid: SW CID the command is related to 3869 * @data_hi: command private data address (high 32 bits) 3870 * @data_lo: command private data address (low 32 bits) 3871 * @cmd_type: command type (e.g. NONE, ETH) 3872 * 3873 * SP data is handled as if it's always an address pair, thus data fields are 3874 * not swapped to little endian in upper functions. Instead this function swaps 3875 * data as if it's two u32 fields. 3876 */ 3877 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3878 u32 data_hi, u32 data_lo, int cmd_type) 3879 { 3880 struct eth_spe *spe; 3881 u16 type; 3882 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3883 3884 #ifdef BNX2X_STOP_ON_ERROR 3885 if (unlikely(bp->panic)) { 3886 BNX2X_ERR("Can't post SP when there is panic\n"); 3887 return -EIO; 3888 } 3889 #endif 3890 3891 spin_lock_bh(&bp->spq_lock); 3892 3893 if (common) { 3894 if (!atomic_read(&bp->eq_spq_left)) { 3895 BNX2X_ERR("BUG! EQ ring full!\n"); 3896 spin_unlock_bh(&bp->spq_lock); 3897 bnx2x_panic(); 3898 return -EBUSY; 3899 } 3900 } else if (!atomic_read(&bp->cq_spq_left)) { 3901 BNX2X_ERR("BUG! SPQ ring full!\n"); 3902 spin_unlock_bh(&bp->spq_lock); 3903 bnx2x_panic(); 3904 return -EBUSY; 3905 } 3906 3907 spe = bnx2x_sp_get_next(bp); 3908 3909 /* CID needs port number to be encoded int it */ 3910 spe->hdr.conn_and_cmd_data = 3911 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3912 HW_CID(bp, cid)); 3913 3914 /* In some cases, type may already contain the func-id 3915 * mainly in SRIOV related use cases, so we add it here only 3916 * if it's not already set. 3917 */ 3918 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) { 3919 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & 3920 SPE_HDR_CONN_TYPE; 3921 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3922 SPE_HDR_FUNCTION_ID); 3923 } else { 3924 type = cmd_type; 3925 } 3926 3927 spe->hdr.type = cpu_to_le16(type); 3928 3929 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3930 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3931 3932 /* 3933 * It's ok if the actual decrement is issued towards the memory 3934 * somewhere between the spin_lock and spin_unlock. Thus no 3935 * more explicit memory barrier is needed. 3936 */ 3937 if (common) 3938 atomic_dec(&bp->eq_spq_left); 3939 else 3940 atomic_dec(&bp->cq_spq_left); 3941 3942 DP(BNX2X_MSG_SP, 3943 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3944 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3945 (u32)(U64_LO(bp->spq_mapping) + 3946 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3947 HW_CID(bp, cid), data_hi, data_lo, type, 3948 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3949 3950 bnx2x_sp_prod_update(bp); 3951 spin_unlock_bh(&bp->spq_lock); 3952 return 0; 3953 } 3954 3955 /* acquire split MCP access lock register */ 3956 static int bnx2x_acquire_alr(struct bnx2x *bp) 3957 { 3958 u32 j, val; 3959 int rc = 0; 3960 3961 might_sleep(); 3962 for (j = 0; j < 1000; j++) { 3963 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); 3964 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); 3965 if (val & MCPR_ACCESS_LOCK_LOCK) 3966 break; 3967 3968 usleep_range(5000, 10000); 3969 } 3970 if (!(val & MCPR_ACCESS_LOCK_LOCK)) { 3971 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3972 rc = -EBUSY; 3973 } 3974 3975 return rc; 3976 } 3977 3978 /* release split MCP access lock register */ 3979 static void bnx2x_release_alr(struct bnx2x *bp) 3980 { 3981 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); 3982 } 3983 3984 #define BNX2X_DEF_SB_ATT_IDX 0x0001 3985 #define BNX2X_DEF_SB_IDX 0x0002 3986 3987 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3988 { 3989 struct host_sp_status_block *def_sb = bp->def_status_blk; 3990 u16 rc = 0; 3991 3992 barrier(); /* status block is written to by the chip */ 3993 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3994 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3995 rc |= BNX2X_DEF_SB_ATT_IDX; 3996 } 3997 3998 if (bp->def_idx != def_sb->sp_sb.running_index) { 3999 bp->def_idx = def_sb->sp_sb.running_index; 4000 rc |= BNX2X_DEF_SB_IDX; 4001 } 4002 4003 /* Do not reorder: indices reading should complete before handling */ 4004 barrier(); 4005 return rc; 4006 } 4007 4008 /* 4009 * slow path service functions 4010 */ 4011 4012 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 4013 { 4014 int port = BP_PORT(bp); 4015 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4016 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4017 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 4018 NIG_REG_MASK_INTERRUPT_PORT0; 4019 u32 aeu_mask; 4020 u32 nig_mask = 0; 4021 u32 reg_addr; 4022 4023 if (bp->attn_state & asserted) 4024 BNX2X_ERR("IGU ERROR\n"); 4025 4026 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4027 aeu_mask = REG_RD(bp, aeu_addr); 4028 4029 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 4030 aeu_mask, asserted); 4031 aeu_mask &= ~(asserted & 0x3ff); 4032 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4033 4034 REG_WR(bp, aeu_addr, aeu_mask); 4035 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4036 4037 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4038 bp->attn_state |= asserted; 4039 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4040 4041 if (asserted & ATTN_HARD_WIRED_MASK) { 4042 if (asserted & ATTN_NIG_FOR_FUNC) { 4043 4044 bnx2x_acquire_phy_lock(bp); 4045 4046 /* save nig interrupt mask */ 4047 nig_mask = REG_RD(bp, nig_int_mask_addr); 4048 4049 /* If nig_mask is not set, no need to call the update 4050 * function. 4051 */ 4052 if (nig_mask) { 4053 REG_WR(bp, nig_int_mask_addr, 0); 4054 4055 bnx2x_link_attn(bp); 4056 } 4057 4058 /* handle unicore attn? */ 4059 } 4060 if (asserted & ATTN_SW_TIMER_4_FUNC) 4061 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 4062 4063 if (asserted & GPIO_2_FUNC) 4064 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 4065 4066 if (asserted & GPIO_3_FUNC) 4067 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 4068 4069 if (asserted & GPIO_4_FUNC) 4070 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 4071 4072 if (port == 0) { 4073 if (asserted & ATTN_GENERAL_ATTN_1) { 4074 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 4075 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 4076 } 4077 if (asserted & ATTN_GENERAL_ATTN_2) { 4078 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 4079 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 4080 } 4081 if (asserted & ATTN_GENERAL_ATTN_3) { 4082 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 4083 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 4084 } 4085 } else { 4086 if (asserted & ATTN_GENERAL_ATTN_4) { 4087 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 4088 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 4089 } 4090 if (asserted & ATTN_GENERAL_ATTN_5) { 4091 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 4092 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 4093 } 4094 if (asserted & ATTN_GENERAL_ATTN_6) { 4095 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 4096 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 4097 } 4098 } 4099 4100 } /* if hardwired */ 4101 4102 if (bp->common.int_block == INT_BLOCK_HC) 4103 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4104 COMMAND_REG_ATTN_BITS_SET); 4105 else 4106 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 4107 4108 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 4109 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4110 REG_WR(bp, reg_addr, asserted); 4111 4112 /* now set back the mask */ 4113 if (asserted & ATTN_NIG_FOR_FUNC) { 4114 /* Verify that IGU ack through BAR was written before restoring 4115 * NIG mask. This loop should exit after 2-3 iterations max. 4116 */ 4117 if (bp->common.int_block != INT_BLOCK_HC) { 4118 u32 cnt = 0, igu_acked; 4119 do { 4120 igu_acked = REG_RD(bp, 4121 IGU_REG_ATTENTION_ACK_BITS); 4122 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 4123 (++cnt < MAX_IGU_ATTN_ACK_TO)); 4124 if (!igu_acked) 4125 DP(NETIF_MSG_HW, 4126 "Failed to verify IGU ack on time\n"); 4127 barrier(); 4128 } 4129 REG_WR(bp, nig_int_mask_addr, nig_mask); 4130 bnx2x_release_phy_lock(bp); 4131 } 4132 } 4133 4134 static void bnx2x_fan_failure(struct bnx2x *bp) 4135 { 4136 int port = BP_PORT(bp); 4137 u32 ext_phy_config; 4138 /* mark the failure */ 4139 ext_phy_config = 4140 SHMEM_RD(bp, 4141 dev_info.port_hw_config[port].external_phy_config); 4142 4143 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 4144 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 4145 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 4146 ext_phy_config); 4147 4148 /* log the failure */ 4149 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 4150 "Please contact OEM Support for assistance\n"); 4151 4152 /* Schedule device reset (unload) 4153 * This is due to some boards consuming sufficient power when driver is 4154 * up to overheat if fan fails. 4155 */ 4156 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); 4157 } 4158 4159 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 4160 { 4161 int port = BP_PORT(bp); 4162 int reg_offset; 4163 u32 val; 4164 4165 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4166 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 4167 4168 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 4169 4170 val = REG_RD(bp, reg_offset); 4171 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 4172 REG_WR(bp, reg_offset, val); 4173 4174 BNX2X_ERR("SPIO5 hw attention\n"); 4175 4176 /* Fan failure attention */ 4177 bnx2x_hw_reset_phy(&bp->link_params); 4178 bnx2x_fan_failure(bp); 4179 } 4180 4181 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 4182 bnx2x_acquire_phy_lock(bp); 4183 bnx2x_handle_module_detect_int(&bp->link_params); 4184 bnx2x_release_phy_lock(bp); 4185 } 4186 4187 if (attn & HW_INTERRUPT_ASSERT_SET_0) { 4188 4189 val = REG_RD(bp, reg_offset); 4190 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0); 4191 REG_WR(bp, reg_offset, val); 4192 4193 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 4194 (u32)(attn & HW_INTERRUPT_ASSERT_SET_0)); 4195 bnx2x_panic(); 4196 } 4197 } 4198 4199 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 4200 { 4201 u32 val; 4202 4203 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 4204 4205 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 4206 BNX2X_ERR("DB hw attention 0x%x\n", val); 4207 /* DORQ discard attention */ 4208 if (val & 0x2) 4209 BNX2X_ERR("FATAL error from DORQ\n"); 4210 } 4211 4212 if (attn & HW_INTERRUPT_ASSERT_SET_1) { 4213 4214 int port = BP_PORT(bp); 4215 int reg_offset; 4216 4217 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 4218 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 4219 4220 val = REG_RD(bp, reg_offset); 4221 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1); 4222 REG_WR(bp, reg_offset, val); 4223 4224 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 4225 (u32)(attn & HW_INTERRUPT_ASSERT_SET_1)); 4226 bnx2x_panic(); 4227 } 4228 } 4229 4230 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 4231 { 4232 u32 val; 4233 4234 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 4235 4236 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 4237 BNX2X_ERR("CFC hw attention 0x%x\n", val); 4238 /* CFC error attention */ 4239 if (val & 0x2) 4240 BNX2X_ERR("FATAL error from CFC\n"); 4241 } 4242 4243 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 4244 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 4245 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 4246 /* RQ_USDMDP_FIFO_OVERFLOW */ 4247 if (val & 0x18000) 4248 BNX2X_ERR("FATAL error from PXP\n"); 4249 4250 if (!CHIP_IS_E1x(bp)) { 4251 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 4252 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 4253 } 4254 } 4255 4256 if (attn & HW_INTERRUPT_ASSERT_SET_2) { 4257 4258 int port = BP_PORT(bp); 4259 int reg_offset; 4260 4261 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 4262 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 4263 4264 val = REG_RD(bp, reg_offset); 4265 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2); 4266 REG_WR(bp, reg_offset, val); 4267 4268 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 4269 (u32)(attn & HW_INTERRUPT_ASSERT_SET_2)); 4270 bnx2x_panic(); 4271 } 4272 } 4273 4274 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 4275 { 4276 u32 val; 4277 4278 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 4279 4280 if (attn & BNX2X_PMF_LINK_ASSERT) { 4281 int func = BP_FUNC(bp); 4282 4283 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 4284 bnx2x_read_mf_cfg(bp); 4285 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 4286 func_mf_config[BP_ABS_FUNC(bp)].config); 4287 val = SHMEM_RD(bp, 4288 func_mb[BP_FW_MB_IDX(bp)].drv_status); 4289 4290 if (val & (DRV_STATUS_DCC_EVENT_MASK | 4291 DRV_STATUS_OEM_EVENT_MASK)) 4292 bnx2x_oem_event(bp, 4293 (val & (DRV_STATUS_DCC_EVENT_MASK | 4294 DRV_STATUS_OEM_EVENT_MASK))); 4295 4296 if (val & DRV_STATUS_SET_MF_BW) 4297 bnx2x_set_mf_bw(bp); 4298 4299 if (val & DRV_STATUS_DRV_INFO_REQ) 4300 bnx2x_handle_drv_info_req(bp); 4301 4302 if (val & DRV_STATUS_VF_DISABLED) 4303 bnx2x_schedule_iov_task(bp, 4304 BNX2X_IOV_HANDLE_FLR); 4305 4306 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 4307 bnx2x_pmf_update(bp); 4308 4309 if (bp->port.pmf && 4310 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 4311 bp->dcbx_enabled > 0) 4312 /* start dcbx state machine */ 4313 bnx2x_dcbx_set_params(bp, 4314 BNX2X_DCBX_STATE_NEG_RECEIVED); 4315 if (val & DRV_STATUS_AFEX_EVENT_MASK) 4316 bnx2x_handle_afex_cmd(bp, 4317 val & DRV_STATUS_AFEX_EVENT_MASK); 4318 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 4319 bnx2x_handle_eee_event(bp); 4320 4321 if (val & DRV_STATUS_OEM_UPDATE_SVID) 4322 bnx2x_schedule_sp_rtnl(bp, 4323 BNX2X_SP_RTNL_UPDATE_SVID, 0); 4324 4325 if (bp->link_vars.periodic_flags & 4326 PERIODIC_FLAGS_LINK_EVENT) { 4327 /* sync with link */ 4328 bnx2x_acquire_phy_lock(bp); 4329 bp->link_vars.periodic_flags &= 4330 ~PERIODIC_FLAGS_LINK_EVENT; 4331 bnx2x_release_phy_lock(bp); 4332 if (IS_MF(bp)) 4333 bnx2x_link_sync_notify(bp); 4334 bnx2x_link_report(bp); 4335 } 4336 /* Always call it here: bnx2x_link_report() will 4337 * prevent the link indication duplication. 4338 */ 4339 bnx2x__link_status_update(bp); 4340 } else if (attn & BNX2X_MC_ASSERT_BITS) { 4341 4342 BNX2X_ERR("MC assert!\n"); 4343 bnx2x_mc_assert(bp); 4344 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 4345 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 4346 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 4347 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 4348 bnx2x_panic(); 4349 4350 } else if (attn & BNX2X_MCP_ASSERT) { 4351 4352 BNX2X_ERR("MCP assert!\n"); 4353 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 4354 bnx2x_fw_dump(bp); 4355 4356 } else 4357 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 4358 } 4359 4360 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 4361 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 4362 if (attn & BNX2X_GRC_TIMEOUT) { 4363 val = CHIP_IS_E1(bp) ? 0 : 4364 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 4365 BNX2X_ERR("GRC time-out 0x%08x\n", val); 4366 } 4367 if (attn & BNX2X_GRC_RSV) { 4368 val = CHIP_IS_E1(bp) ? 0 : 4369 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 4370 BNX2X_ERR("GRC reserved 0x%08x\n", val); 4371 } 4372 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 4373 } 4374 } 4375 4376 /* 4377 * Bits map: 4378 * 0-7 - Engine0 load counter. 4379 * 8-15 - Engine1 load counter. 4380 * 16 - Engine0 RESET_IN_PROGRESS bit. 4381 * 17 - Engine1 RESET_IN_PROGRESS bit. 4382 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 4383 * on the engine 4384 * 19 - Engine1 ONE_IS_LOADED. 4385 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 4386 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 4387 * just the one belonging to its engine). 4388 * 4389 */ 4390 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 4391 4392 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 4393 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 4394 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 4395 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 4396 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 4397 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 4398 #define BNX2X_GLOBAL_RESET_BIT 0x00040000 4399 4400 /* 4401 * Set the GLOBAL_RESET bit. 4402 * 4403 * Should be run under rtnl lock 4404 */ 4405 void bnx2x_set_reset_global(struct bnx2x *bp) 4406 { 4407 u32 val; 4408 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4409 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4410 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 4411 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4412 } 4413 4414 /* 4415 * Clear the GLOBAL_RESET bit. 4416 * 4417 * Should be run under rtnl lock 4418 */ 4419 static void bnx2x_clear_reset_global(struct bnx2x *bp) 4420 { 4421 u32 val; 4422 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4423 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4424 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 4425 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4426 } 4427 4428 /* 4429 * Checks the GLOBAL_RESET bit. 4430 * 4431 * should be run under rtnl lock 4432 */ 4433 static bool bnx2x_reset_is_global(struct bnx2x *bp) 4434 { 4435 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4436 4437 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 4438 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 4439 } 4440 4441 /* 4442 * Clear RESET_IN_PROGRESS bit for the current engine. 4443 * 4444 * Should be run under rtnl lock 4445 */ 4446 static void bnx2x_set_reset_done(struct bnx2x *bp) 4447 { 4448 u32 val; 4449 u32 bit = BP_PATH(bp) ? 4450 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4451 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4452 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4453 4454 /* Clear the bit */ 4455 val &= ~bit; 4456 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4457 4458 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4459 } 4460 4461 /* 4462 * Set RESET_IN_PROGRESS for the current engine. 4463 * 4464 * should be run under rtnl lock 4465 */ 4466 void bnx2x_set_reset_in_progress(struct bnx2x *bp) 4467 { 4468 u32 val; 4469 u32 bit = BP_PATH(bp) ? 4470 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4471 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4472 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4473 4474 /* Set the bit */ 4475 val |= bit; 4476 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4477 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4478 } 4479 4480 /* 4481 * Checks the RESET_IN_PROGRESS bit for the given engine. 4482 * should be run under rtnl lock 4483 */ 4484 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 4485 { 4486 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4487 u32 bit = engine ? 4488 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4489 4490 /* return false if bit is set */ 4491 return (val & bit) ? false : true; 4492 } 4493 4494 /* 4495 * set pf load for the current pf. 4496 * 4497 * should be run under rtnl lock 4498 */ 4499 void bnx2x_set_pf_load(struct bnx2x *bp) 4500 { 4501 u32 val1, val; 4502 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4503 BNX2X_PATH0_LOAD_CNT_MASK; 4504 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4505 BNX2X_PATH0_LOAD_CNT_SHIFT; 4506 4507 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4508 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4509 4510 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 4511 4512 /* get the current counter value */ 4513 val1 = (val & mask) >> shift; 4514 4515 /* set bit of that PF */ 4516 val1 |= (1 << bp->pf_num); 4517 4518 /* clear the old value */ 4519 val &= ~mask; 4520 4521 /* set the new one */ 4522 val |= ((val1 << shift) & mask); 4523 4524 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4525 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4526 } 4527 4528 /** 4529 * bnx2x_clear_pf_load - clear pf load mark 4530 * 4531 * @bp: driver handle 4532 * 4533 * Should be run under rtnl lock. 4534 * Decrements the load counter for the current engine. Returns 4535 * whether other functions are still loaded 4536 */ 4537 bool bnx2x_clear_pf_load(struct bnx2x *bp) 4538 { 4539 u32 val1, val; 4540 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4541 BNX2X_PATH0_LOAD_CNT_MASK; 4542 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4543 BNX2X_PATH0_LOAD_CNT_SHIFT; 4544 4545 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4546 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4547 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 4548 4549 /* get the current counter value */ 4550 val1 = (val & mask) >> shift; 4551 4552 /* clear bit of that PF */ 4553 val1 &= ~(1 << bp->pf_num); 4554 4555 /* clear the old value */ 4556 val &= ~mask; 4557 4558 /* set the new one */ 4559 val |= ((val1 << shift) & mask); 4560 4561 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4562 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4563 return val1 != 0; 4564 } 4565 4566 /* 4567 * Read the load status for the current engine. 4568 * 4569 * should be run under rtnl lock 4570 */ 4571 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 4572 { 4573 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 4574 BNX2X_PATH0_LOAD_CNT_MASK); 4575 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4576 BNX2X_PATH0_LOAD_CNT_SHIFT); 4577 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4578 4579 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 4580 4581 val = (val & mask) >> shift; 4582 4583 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 4584 engine, val); 4585 4586 return val != 0; 4587 } 4588 4589 static void _print_parity(struct bnx2x *bp, u32 reg) 4590 { 4591 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); 4592 } 4593 4594 static void _print_next_block(int idx, const char *blk) 4595 { 4596 pr_cont("%s%s", idx ? ", " : "", blk); 4597 } 4598 4599 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, 4600 int *par_num, bool print) 4601 { 4602 u32 cur_bit; 4603 bool res; 4604 int i; 4605 4606 res = false; 4607 4608 for (i = 0; sig; i++) { 4609 cur_bit = (0x1UL << i); 4610 if (sig & cur_bit) { 4611 res |= true; /* Each bit is real error! */ 4612 4613 if (print) { 4614 switch (cur_bit) { 4615 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4616 _print_next_block((*par_num)++, "BRB"); 4617 _print_parity(bp, 4618 BRB1_REG_BRB1_PRTY_STS); 4619 break; 4620 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4621 _print_next_block((*par_num)++, 4622 "PARSER"); 4623 _print_parity(bp, PRS_REG_PRS_PRTY_STS); 4624 break; 4625 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4626 _print_next_block((*par_num)++, "TSDM"); 4627 _print_parity(bp, 4628 TSDM_REG_TSDM_PRTY_STS); 4629 break; 4630 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4631 _print_next_block((*par_num)++, 4632 "SEARCHER"); 4633 _print_parity(bp, SRC_REG_SRC_PRTY_STS); 4634 break; 4635 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4636 _print_next_block((*par_num)++, "TCM"); 4637 _print_parity(bp, TCM_REG_TCM_PRTY_STS); 4638 break; 4639 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 4640 _print_next_block((*par_num)++, 4641 "TSEMI"); 4642 _print_parity(bp, 4643 TSEM_REG_TSEM_PRTY_STS_0); 4644 _print_parity(bp, 4645 TSEM_REG_TSEM_PRTY_STS_1); 4646 break; 4647 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4648 _print_next_block((*par_num)++, "XPB"); 4649 _print_parity(bp, GRCBASE_XPB + 4650 PB_REG_PB_PRTY_STS); 4651 break; 4652 } 4653 } 4654 4655 /* Clear the bit */ 4656 sig &= ~cur_bit; 4657 } 4658 } 4659 4660 return res; 4661 } 4662 4663 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, 4664 int *par_num, bool *global, 4665 bool print) 4666 { 4667 u32 cur_bit; 4668 bool res; 4669 int i; 4670 4671 res = false; 4672 4673 for (i = 0; sig; i++) { 4674 cur_bit = (0x1UL << i); 4675 if (sig & cur_bit) { 4676 res |= true; /* Each bit is real error! */ 4677 switch (cur_bit) { 4678 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4679 if (print) { 4680 _print_next_block((*par_num)++, "PBF"); 4681 _print_parity(bp, PBF_REG_PBF_PRTY_STS); 4682 } 4683 break; 4684 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4685 if (print) { 4686 _print_next_block((*par_num)++, "QM"); 4687 _print_parity(bp, QM_REG_QM_PRTY_STS); 4688 } 4689 break; 4690 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4691 if (print) { 4692 _print_next_block((*par_num)++, "TM"); 4693 _print_parity(bp, TM_REG_TM_PRTY_STS); 4694 } 4695 break; 4696 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4697 if (print) { 4698 _print_next_block((*par_num)++, "XSDM"); 4699 _print_parity(bp, 4700 XSDM_REG_XSDM_PRTY_STS); 4701 } 4702 break; 4703 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4704 if (print) { 4705 _print_next_block((*par_num)++, "XCM"); 4706 _print_parity(bp, XCM_REG_XCM_PRTY_STS); 4707 } 4708 break; 4709 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4710 if (print) { 4711 _print_next_block((*par_num)++, 4712 "XSEMI"); 4713 _print_parity(bp, 4714 XSEM_REG_XSEM_PRTY_STS_0); 4715 _print_parity(bp, 4716 XSEM_REG_XSEM_PRTY_STS_1); 4717 } 4718 break; 4719 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4720 if (print) { 4721 _print_next_block((*par_num)++, 4722 "DOORBELLQ"); 4723 _print_parity(bp, 4724 DORQ_REG_DORQ_PRTY_STS); 4725 } 4726 break; 4727 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4728 if (print) { 4729 _print_next_block((*par_num)++, "NIG"); 4730 if (CHIP_IS_E1x(bp)) { 4731 _print_parity(bp, 4732 NIG_REG_NIG_PRTY_STS); 4733 } else { 4734 _print_parity(bp, 4735 NIG_REG_NIG_PRTY_STS_0); 4736 _print_parity(bp, 4737 NIG_REG_NIG_PRTY_STS_1); 4738 } 4739 } 4740 break; 4741 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4742 if (print) 4743 _print_next_block((*par_num)++, 4744 "VAUX PCI CORE"); 4745 *global = true; 4746 break; 4747 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4748 if (print) { 4749 _print_next_block((*par_num)++, 4750 "DEBUG"); 4751 _print_parity(bp, DBG_REG_DBG_PRTY_STS); 4752 } 4753 break; 4754 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4755 if (print) { 4756 _print_next_block((*par_num)++, "USDM"); 4757 _print_parity(bp, 4758 USDM_REG_USDM_PRTY_STS); 4759 } 4760 break; 4761 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4762 if (print) { 4763 _print_next_block((*par_num)++, "UCM"); 4764 _print_parity(bp, UCM_REG_UCM_PRTY_STS); 4765 } 4766 break; 4767 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4768 if (print) { 4769 _print_next_block((*par_num)++, 4770 "USEMI"); 4771 _print_parity(bp, 4772 USEM_REG_USEM_PRTY_STS_0); 4773 _print_parity(bp, 4774 USEM_REG_USEM_PRTY_STS_1); 4775 } 4776 break; 4777 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4778 if (print) { 4779 _print_next_block((*par_num)++, "UPB"); 4780 _print_parity(bp, GRCBASE_UPB + 4781 PB_REG_PB_PRTY_STS); 4782 } 4783 break; 4784 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4785 if (print) { 4786 _print_next_block((*par_num)++, "CSDM"); 4787 _print_parity(bp, 4788 CSDM_REG_CSDM_PRTY_STS); 4789 } 4790 break; 4791 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4792 if (print) { 4793 _print_next_block((*par_num)++, "CCM"); 4794 _print_parity(bp, CCM_REG_CCM_PRTY_STS); 4795 } 4796 break; 4797 } 4798 4799 /* Clear the bit */ 4800 sig &= ~cur_bit; 4801 } 4802 } 4803 4804 return res; 4805 } 4806 4807 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, 4808 int *par_num, bool print) 4809 { 4810 u32 cur_bit; 4811 bool res; 4812 int i; 4813 4814 res = false; 4815 4816 for (i = 0; sig; i++) { 4817 cur_bit = (0x1UL << i); 4818 if (sig & cur_bit) { 4819 res = true; /* Each bit is real error! */ 4820 if (print) { 4821 switch (cur_bit) { 4822 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4823 _print_next_block((*par_num)++, 4824 "CSEMI"); 4825 _print_parity(bp, 4826 CSEM_REG_CSEM_PRTY_STS_0); 4827 _print_parity(bp, 4828 CSEM_REG_CSEM_PRTY_STS_1); 4829 break; 4830 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4831 _print_next_block((*par_num)++, "PXP"); 4832 _print_parity(bp, PXP_REG_PXP_PRTY_STS); 4833 _print_parity(bp, 4834 PXP2_REG_PXP2_PRTY_STS_0); 4835 _print_parity(bp, 4836 PXP2_REG_PXP2_PRTY_STS_1); 4837 break; 4838 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4839 _print_next_block((*par_num)++, 4840 "PXPPCICLOCKCLIENT"); 4841 break; 4842 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4843 _print_next_block((*par_num)++, "CFC"); 4844 _print_parity(bp, 4845 CFC_REG_CFC_PRTY_STS); 4846 break; 4847 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4848 _print_next_block((*par_num)++, "CDU"); 4849 _print_parity(bp, CDU_REG_CDU_PRTY_STS); 4850 break; 4851 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4852 _print_next_block((*par_num)++, "DMAE"); 4853 _print_parity(bp, 4854 DMAE_REG_DMAE_PRTY_STS); 4855 break; 4856 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4857 _print_next_block((*par_num)++, "IGU"); 4858 if (CHIP_IS_E1x(bp)) 4859 _print_parity(bp, 4860 HC_REG_HC_PRTY_STS); 4861 else 4862 _print_parity(bp, 4863 IGU_REG_IGU_PRTY_STS); 4864 break; 4865 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4866 _print_next_block((*par_num)++, "MISC"); 4867 _print_parity(bp, 4868 MISC_REG_MISC_PRTY_STS); 4869 break; 4870 } 4871 } 4872 4873 /* Clear the bit */ 4874 sig &= ~cur_bit; 4875 } 4876 } 4877 4878 return res; 4879 } 4880 4881 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, 4882 int *par_num, bool *global, 4883 bool print) 4884 { 4885 bool res = false; 4886 u32 cur_bit; 4887 int i; 4888 4889 for (i = 0; sig; i++) { 4890 cur_bit = (0x1UL << i); 4891 if (sig & cur_bit) { 4892 switch (cur_bit) { 4893 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4894 if (print) 4895 _print_next_block((*par_num)++, 4896 "MCP ROM"); 4897 *global = true; 4898 res = true; 4899 break; 4900 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4901 if (print) 4902 _print_next_block((*par_num)++, 4903 "MCP UMP RX"); 4904 *global = true; 4905 res = true; 4906 break; 4907 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4908 if (print) 4909 _print_next_block((*par_num)++, 4910 "MCP UMP TX"); 4911 *global = true; 4912 res = true; 4913 break; 4914 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4915 (*par_num)++; 4916 /* clear latched SCPAD PATIRY from MCP */ 4917 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 4918 1UL << 10); 4919 break; 4920 } 4921 4922 /* Clear the bit */ 4923 sig &= ~cur_bit; 4924 } 4925 } 4926 4927 return res; 4928 } 4929 4930 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, 4931 int *par_num, bool print) 4932 { 4933 u32 cur_bit; 4934 bool res; 4935 int i; 4936 4937 res = false; 4938 4939 for (i = 0; sig; i++) { 4940 cur_bit = (0x1UL << i); 4941 if (sig & cur_bit) { 4942 res = true; /* Each bit is real error! */ 4943 if (print) { 4944 switch (cur_bit) { 4945 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4946 _print_next_block((*par_num)++, 4947 "PGLUE_B"); 4948 _print_parity(bp, 4949 PGLUE_B_REG_PGLUE_B_PRTY_STS); 4950 break; 4951 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4952 _print_next_block((*par_num)++, "ATC"); 4953 _print_parity(bp, 4954 ATC_REG_ATC_PRTY_STS); 4955 break; 4956 } 4957 } 4958 /* Clear the bit */ 4959 sig &= ~cur_bit; 4960 } 4961 } 4962 4963 return res; 4964 } 4965 4966 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4967 u32 *sig) 4968 { 4969 bool res = false; 4970 4971 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4972 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4973 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4974 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4975 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4976 int par_num = 0; 4977 4978 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4979 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4980 sig[0] & HW_PRTY_ASSERT_SET_0, 4981 sig[1] & HW_PRTY_ASSERT_SET_1, 4982 sig[2] & HW_PRTY_ASSERT_SET_2, 4983 sig[3] & HW_PRTY_ASSERT_SET_3, 4984 sig[4] & HW_PRTY_ASSERT_SET_4); 4985 if (print) { 4986 if (((sig[0] & HW_PRTY_ASSERT_SET_0) || 4987 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4988 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4989 (sig[4] & HW_PRTY_ASSERT_SET_4)) || 4990 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) { 4991 netdev_err(bp->dev, 4992 "Parity errors detected in blocks: "); 4993 } else { 4994 print = false; 4995 } 4996 } 4997 res |= bnx2x_check_blocks_with_parity0(bp, 4998 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); 4999 res |= bnx2x_check_blocks_with_parity1(bp, 5000 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print); 5001 res |= bnx2x_check_blocks_with_parity2(bp, 5002 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print); 5003 res |= bnx2x_check_blocks_with_parity3(bp, 5004 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print); 5005 res |= bnx2x_check_blocks_with_parity4(bp, 5006 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print); 5007 5008 if (print) 5009 pr_cont("\n"); 5010 } 5011 5012 return res; 5013 } 5014 5015 /** 5016 * bnx2x_chk_parity_attn - checks for parity attentions. 5017 * 5018 * @bp: driver handle 5019 * @global: true if there was a global attention 5020 * @print: show parity attention in syslog 5021 */ 5022 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 5023 { 5024 struct attn_route attn = { {0} }; 5025 int port = BP_PORT(bp); 5026 5027 attn.sig[0] = REG_RD(bp, 5028 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 5029 port*4); 5030 attn.sig[1] = REG_RD(bp, 5031 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 5032 port*4); 5033 attn.sig[2] = REG_RD(bp, 5034 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 5035 port*4); 5036 attn.sig[3] = REG_RD(bp, 5037 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 5038 port*4); 5039 /* Since MCP attentions can't be disabled inside the block, we need to 5040 * read AEU registers to see whether they're currently disabled 5041 */ 5042 attn.sig[3] &= ((REG_RD(bp, 5043 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 5044 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) & 5045 MISC_AEU_ENABLE_MCP_PRTY_BITS) | 5046 ~MISC_AEU_ENABLE_MCP_PRTY_BITS); 5047 5048 if (!CHIP_IS_E1x(bp)) 5049 attn.sig[4] = REG_RD(bp, 5050 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 5051 port*4); 5052 5053 return bnx2x_parity_attn(bp, global, print, attn.sig); 5054 } 5055 5056 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 5057 { 5058 u32 val; 5059 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 5060 5061 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 5062 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 5063 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 5064 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 5065 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 5066 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 5067 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 5068 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 5069 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 5070 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 5071 if (val & 5072 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 5073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 5074 if (val & 5075 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 5076 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 5077 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 5078 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 5079 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 5080 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 5081 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 5082 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 5083 } 5084 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 5085 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 5086 BNX2X_ERR("ATC hw attention 0x%x\n", val); 5087 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 5088 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 5089 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 5090 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 5091 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 5092 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 5093 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 5094 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 5095 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 5096 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 5097 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 5098 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 5099 } 5100 5101 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 5102 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 5103 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 5104 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 5105 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 5106 } 5107 } 5108 5109 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 5110 { 5111 struct attn_route attn, *group_mask; 5112 int port = BP_PORT(bp); 5113 int index; 5114 u32 reg_addr; 5115 u32 val; 5116 u32 aeu_mask; 5117 bool global = false; 5118 5119 /* need to take HW lock because MCP or other port might also 5120 try to handle this event */ 5121 bnx2x_acquire_alr(bp); 5122 5123 if (bnx2x_chk_parity_attn(bp, &global, true)) { 5124 #ifndef BNX2X_STOP_ON_ERROR 5125 bp->recovery_state = BNX2X_RECOVERY_INIT; 5126 schedule_delayed_work(&bp->sp_rtnl_task, 0); 5127 /* Disable HW interrupts */ 5128 bnx2x_int_disable(bp); 5129 /* In case of parity errors don't handle attentions so that 5130 * other function would "see" parity errors. 5131 */ 5132 #else 5133 bnx2x_panic(); 5134 #endif 5135 bnx2x_release_alr(bp); 5136 return; 5137 } 5138 5139 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 5140 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 5141 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 5142 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 5143 if (!CHIP_IS_E1x(bp)) 5144 attn.sig[4] = 5145 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 5146 else 5147 attn.sig[4] = 0; 5148 5149 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 5150 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 5151 5152 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5153 if (deasserted & (1 << index)) { 5154 group_mask = &bp->attn_group[index]; 5155 5156 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 5157 index, 5158 group_mask->sig[0], group_mask->sig[1], 5159 group_mask->sig[2], group_mask->sig[3], 5160 group_mask->sig[4]); 5161 5162 bnx2x_attn_int_deasserted4(bp, 5163 attn.sig[4] & group_mask->sig[4]); 5164 bnx2x_attn_int_deasserted3(bp, 5165 attn.sig[3] & group_mask->sig[3]); 5166 bnx2x_attn_int_deasserted1(bp, 5167 attn.sig[1] & group_mask->sig[1]); 5168 bnx2x_attn_int_deasserted2(bp, 5169 attn.sig[2] & group_mask->sig[2]); 5170 bnx2x_attn_int_deasserted0(bp, 5171 attn.sig[0] & group_mask->sig[0]); 5172 } 5173 } 5174 5175 bnx2x_release_alr(bp); 5176 5177 if (bp->common.int_block == INT_BLOCK_HC) 5178 reg_addr = (HC_REG_COMMAND_REG + port*32 + 5179 COMMAND_REG_ATTN_BITS_CLR); 5180 else 5181 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 5182 5183 val = ~deasserted; 5184 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 5185 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 5186 REG_WR(bp, reg_addr, val); 5187 5188 if (~bp->attn_state & deasserted) 5189 BNX2X_ERR("IGU ERROR\n"); 5190 5191 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 5192 MISC_REG_AEU_MASK_ATTN_FUNC_0; 5193 5194 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 5195 aeu_mask = REG_RD(bp, reg_addr); 5196 5197 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 5198 aeu_mask, deasserted); 5199 aeu_mask |= (deasserted & 0x3ff); 5200 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 5201 5202 REG_WR(bp, reg_addr, aeu_mask); 5203 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 5204 5205 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 5206 bp->attn_state &= ~deasserted; 5207 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 5208 } 5209 5210 static void bnx2x_attn_int(struct bnx2x *bp) 5211 { 5212 /* read local copy of bits */ 5213 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 5214 attn_bits); 5215 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 5216 attn_bits_ack); 5217 u32 attn_state = bp->attn_state; 5218 5219 /* look for changed bits */ 5220 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 5221 u32 deasserted = ~attn_bits & attn_ack & attn_state; 5222 5223 DP(NETIF_MSG_HW, 5224 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 5225 attn_bits, attn_ack, asserted, deasserted); 5226 5227 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 5228 BNX2X_ERR("BAD attention state\n"); 5229 5230 /* handle bits that were raised */ 5231 if (asserted) 5232 bnx2x_attn_int_asserted(bp, asserted); 5233 5234 if (deasserted) 5235 bnx2x_attn_int_deasserted(bp, deasserted); 5236 } 5237 5238 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 5239 u16 index, u8 op, u8 update) 5240 { 5241 u32 igu_addr = bp->igu_base_addr; 5242 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 5243 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 5244 igu_addr); 5245 } 5246 5247 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 5248 { 5249 /* No memory barriers */ 5250 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 5251 } 5252 5253 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 5254 union event_ring_elem *elem) 5255 { 5256 u8 err = elem->message.error; 5257 5258 if (!bp->cnic_eth_dev.starting_cid || 5259 (cid < bp->cnic_eth_dev.starting_cid && 5260 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 5261 return 1; 5262 5263 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 5264 5265 if (unlikely(err)) { 5266 5267 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 5268 cid); 5269 bnx2x_panic_dump(bp, false); 5270 } 5271 bnx2x_cnic_cfc_comp(bp, cid, err); 5272 return 0; 5273 } 5274 5275 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 5276 { 5277 struct bnx2x_mcast_ramrod_params rparam; 5278 int rc; 5279 5280 memset(&rparam, 0, sizeof(rparam)); 5281 5282 rparam.mcast_obj = &bp->mcast_obj; 5283 5284 netif_addr_lock_bh(bp->dev); 5285 5286 /* Clear pending state for the last command */ 5287 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 5288 5289 /* If there are pending mcast commands - send them */ 5290 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 5291 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 5292 if (rc < 0) 5293 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 5294 rc); 5295 } 5296 5297 netif_addr_unlock_bh(bp->dev); 5298 } 5299 5300 static void bnx2x_handle_classification_eqe(struct bnx2x *bp, 5301 union event_ring_elem *elem) 5302 { 5303 unsigned long ramrod_flags = 0; 5304 int rc = 0; 5305 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); 5306 u32 cid = echo & BNX2X_SWCID_MASK; 5307 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 5308 5309 /* Always push next commands out, don't wait here */ 5310 __set_bit(RAMROD_CONT, &ramrod_flags); 5311 5312 switch (echo >> BNX2X_SWCID_SHIFT) { 5313 case BNX2X_FILTER_MAC_PENDING: 5314 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 5315 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) 5316 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 5317 else 5318 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; 5319 5320 break; 5321 case BNX2X_FILTER_VLAN_PENDING: 5322 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n"); 5323 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; 5324 break; 5325 case BNX2X_FILTER_MCAST_PENDING: 5326 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 5327 /* This is only relevant for 57710 where multicast MACs are 5328 * configured as unicast MACs using the same ramrod. 5329 */ 5330 bnx2x_handle_mcast_eqe(bp); 5331 return; 5332 default: 5333 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); 5334 return; 5335 } 5336 5337 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 5338 5339 if (rc < 0) 5340 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 5341 else if (rc > 0) 5342 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 5343 } 5344 5345 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 5346 5347 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 5348 { 5349 netif_addr_lock_bh(bp->dev); 5350 5351 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5352 5353 /* Send rx_mode command again if was requested */ 5354 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 5355 bnx2x_set_storm_rx_mode(bp); 5356 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 5357 &bp->sp_state)) 5358 bnx2x_set_iscsi_eth_rx_mode(bp, true); 5359 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 5360 &bp->sp_state)) 5361 bnx2x_set_iscsi_eth_rx_mode(bp, false); 5362 5363 netif_addr_unlock_bh(bp->dev); 5364 } 5365 5366 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, 5367 union event_ring_elem *elem) 5368 { 5369 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { 5370 DP(BNX2X_MSG_SP, 5371 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", 5372 elem->message.data.vif_list_event.func_bit_map); 5373 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, 5374 elem->message.data.vif_list_event.func_bit_map); 5375 } else if (elem->message.data.vif_list_event.echo == 5376 VIF_LIST_RULE_SET) { 5377 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); 5378 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); 5379 } 5380 } 5381 5382 /* called with rtnl_lock */ 5383 static void bnx2x_after_function_update(struct bnx2x *bp) 5384 { 5385 int q, rc; 5386 struct bnx2x_fastpath *fp; 5387 struct bnx2x_queue_state_params queue_params = {NULL}; 5388 struct bnx2x_queue_update_params *q_update_params = 5389 &queue_params.params.update; 5390 5391 /* Send Q update command with afex vlan removal values for all Qs */ 5392 queue_params.cmd = BNX2X_Q_CMD_UPDATE; 5393 5394 /* set silent vlan removal values according to vlan mode */ 5395 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 5396 &q_update_params->update_flags); 5397 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 5398 &q_update_params->update_flags); 5399 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5400 5401 /* in access mode mark mask and value are 0 to strip all vlans */ 5402 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { 5403 q_update_params->silent_removal_value = 0; 5404 q_update_params->silent_removal_mask = 0; 5405 } else { 5406 q_update_params->silent_removal_value = 5407 (bp->afex_def_vlan_tag & VLAN_VID_MASK); 5408 q_update_params->silent_removal_mask = VLAN_VID_MASK; 5409 } 5410 5411 for_each_eth_queue(bp, q) { 5412 /* Set the appropriate Queue object */ 5413 fp = &bp->fp[q]; 5414 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5415 5416 /* send the ramrod */ 5417 rc = bnx2x_queue_state_change(bp, &queue_params); 5418 if (rc < 0) 5419 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5420 q); 5421 } 5422 5423 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { 5424 fp = &bp->fp[FCOE_IDX(bp)]; 5425 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5426 5427 /* clear pending completion bit */ 5428 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5429 5430 /* mark latest Q bit */ 5431 smp_mb__before_atomic(); 5432 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 5433 smp_mb__after_atomic(); 5434 5435 /* send Q update ramrod for FCoE Q */ 5436 rc = bnx2x_queue_state_change(bp, &queue_params); 5437 if (rc < 0) 5438 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5439 q); 5440 } else { 5441 /* If no FCoE ring - ACK MCP now */ 5442 bnx2x_link_report(bp); 5443 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5444 } 5445 } 5446 5447 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 5448 struct bnx2x *bp, u32 cid) 5449 { 5450 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 5451 5452 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) 5453 return &bnx2x_fcoe_sp_obj(bp, q_obj); 5454 else 5455 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; 5456 } 5457 5458 static void bnx2x_eq_int(struct bnx2x *bp) 5459 { 5460 u16 hw_cons, sw_cons, sw_prod; 5461 union event_ring_elem *elem; 5462 u8 echo; 5463 u32 cid; 5464 u8 opcode; 5465 int rc, spqe_cnt = 0; 5466 struct bnx2x_queue_sp_obj *q_obj; 5467 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 5468 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 5469 5470 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 5471 5472 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 5473 * when we get the next-page we need to adjust so the loop 5474 * condition below will be met. The next element is the size of a 5475 * regular element and hence incrementing by 1 5476 */ 5477 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 5478 hw_cons++; 5479 5480 /* This function may never run in parallel with itself for a 5481 * specific bp, thus there is no need in "paired" read memory 5482 * barrier here. 5483 */ 5484 sw_cons = bp->eq_cons; 5485 sw_prod = bp->eq_prod; 5486 5487 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 5488 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 5489 5490 for (; sw_cons != hw_cons; 5491 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 5492 5493 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 5494 5495 rc = bnx2x_iov_eq_sp_event(bp, elem); 5496 if (!rc) { 5497 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", 5498 rc); 5499 goto next_spqe; 5500 } 5501 5502 opcode = elem->message.opcode; 5503 5504 /* handle eq element */ 5505 switch (opcode) { 5506 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 5507 bnx2x_vf_mbx_schedule(bp, 5508 &elem->message.data.vf_pf_event); 5509 continue; 5510 5511 case EVENT_RING_OPCODE_STAT_QUERY: 5512 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS), 5513 "got statistics comp event %d\n", 5514 bp->stats_comp++); 5515 /* nothing to do with stats comp */ 5516 goto next_spqe; 5517 5518 case EVENT_RING_OPCODE_CFC_DEL: 5519 /* handle according to cid range */ 5520 /* 5521 * we may want to verify here that the bp state is 5522 * HALTING 5523 */ 5524 5525 /* elem CID originates from FW; actually LE */ 5526 cid = SW_CID(elem->message.data.cfc_del_event.cid); 5527 5528 DP(BNX2X_MSG_SP, 5529 "got delete ramrod for MULTI[%d]\n", cid); 5530 5531 if (CNIC_LOADED(bp) && 5532 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 5533 goto next_spqe; 5534 5535 q_obj = bnx2x_cid_to_q_obj(bp, cid); 5536 5537 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 5538 break; 5539 5540 goto next_spqe; 5541 5542 case EVENT_RING_OPCODE_STOP_TRAFFIC: 5543 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 5544 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 5545 if (f_obj->complete_cmd(bp, f_obj, 5546 BNX2X_F_CMD_TX_STOP)) 5547 break; 5548 goto next_spqe; 5549 5550 case EVENT_RING_OPCODE_START_TRAFFIC: 5551 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 5552 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 5553 if (f_obj->complete_cmd(bp, f_obj, 5554 BNX2X_F_CMD_TX_START)) 5555 break; 5556 goto next_spqe; 5557 5558 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 5559 echo = elem->message.data.function_update_event.echo; 5560 if (echo == SWITCH_UPDATE) { 5561 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5562 "got FUNC_SWITCH_UPDATE ramrod\n"); 5563 if (f_obj->complete_cmd( 5564 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) 5565 break; 5566 5567 } else { 5568 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE; 5569 5570 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, 5571 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 5572 f_obj->complete_cmd(bp, f_obj, 5573 BNX2X_F_CMD_AFEX_UPDATE); 5574 5575 /* We will perform the Queues update from 5576 * sp_rtnl task as all Queue SP operations 5577 * should run under rtnl_lock. 5578 */ 5579 bnx2x_schedule_sp_rtnl(bp, cmd, 0); 5580 } 5581 5582 goto next_spqe; 5583 5584 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 5585 f_obj->complete_cmd(bp, f_obj, 5586 BNX2X_F_CMD_AFEX_VIFLISTS); 5587 bnx2x_after_afex_vif_lists(bp, elem); 5588 goto next_spqe; 5589 case EVENT_RING_OPCODE_FUNCTION_START: 5590 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5591 "got FUNC_START ramrod\n"); 5592 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 5593 break; 5594 5595 goto next_spqe; 5596 5597 case EVENT_RING_OPCODE_FUNCTION_STOP: 5598 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5599 "got FUNC_STOP ramrod\n"); 5600 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 5601 break; 5602 5603 goto next_spqe; 5604 5605 case EVENT_RING_OPCODE_SET_TIMESYNC: 5606 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, 5607 "got set_timesync ramrod completion\n"); 5608 if (f_obj->complete_cmd(bp, f_obj, 5609 BNX2X_F_CMD_SET_TIMESYNC)) 5610 break; 5611 goto next_spqe; 5612 } 5613 5614 switch (opcode | bp->state) { 5615 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5616 BNX2X_STATE_OPEN): 5617 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5618 BNX2X_STATE_OPENING_WAIT4_PORT): 5619 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5620 BNX2X_STATE_CLOSING_WAIT4_HALT): 5621 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 5622 SW_CID(elem->message.data.eth_event.echo)); 5623 rss_raw->clear_pending(rss_raw); 5624 break; 5625 5626 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 5627 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 5628 case (EVENT_RING_OPCODE_SET_MAC | 5629 BNX2X_STATE_CLOSING_WAIT4_HALT): 5630 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5631 BNX2X_STATE_OPEN): 5632 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5633 BNX2X_STATE_DIAG): 5634 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5635 BNX2X_STATE_CLOSING_WAIT4_HALT): 5636 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n"); 5637 bnx2x_handle_classification_eqe(bp, elem); 5638 break; 5639 5640 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5641 BNX2X_STATE_OPEN): 5642 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5643 BNX2X_STATE_DIAG): 5644 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5645 BNX2X_STATE_CLOSING_WAIT4_HALT): 5646 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 5647 bnx2x_handle_mcast_eqe(bp); 5648 break; 5649 5650 case (EVENT_RING_OPCODE_FILTERS_RULES | 5651 BNX2X_STATE_OPEN): 5652 case (EVENT_RING_OPCODE_FILTERS_RULES | 5653 BNX2X_STATE_DIAG): 5654 case (EVENT_RING_OPCODE_FILTERS_RULES | 5655 BNX2X_STATE_CLOSING_WAIT4_HALT): 5656 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 5657 bnx2x_handle_rx_mode_eqe(bp); 5658 break; 5659 default: 5660 /* unknown event log error and continue */ 5661 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 5662 elem->message.opcode, bp->state); 5663 } 5664 next_spqe: 5665 spqe_cnt++; 5666 } /* for */ 5667 5668 smp_mb__before_atomic(); 5669 atomic_add(spqe_cnt, &bp->eq_spq_left); 5670 5671 bp->eq_cons = sw_cons; 5672 bp->eq_prod = sw_prod; 5673 /* Make sure that above mem writes were issued towards the memory */ 5674 smp_wmb(); 5675 5676 /* update producer */ 5677 bnx2x_update_eq_prod(bp, bp->eq_prod); 5678 } 5679 5680 static void bnx2x_sp_task(struct work_struct *work) 5681 { 5682 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 5683 5684 DP(BNX2X_MSG_SP, "sp task invoked\n"); 5685 5686 /* make sure the atomic interrupt_occurred has been written */ 5687 smp_rmb(); 5688 if (atomic_read(&bp->interrupt_occurred)) { 5689 5690 /* what work needs to be performed? */ 5691 u16 status = bnx2x_update_dsb_idx(bp); 5692 5693 DP(BNX2X_MSG_SP, "status %x\n", status); 5694 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); 5695 atomic_set(&bp->interrupt_occurred, 0); 5696 5697 /* HW attentions */ 5698 if (status & BNX2X_DEF_SB_ATT_IDX) { 5699 bnx2x_attn_int(bp); 5700 status &= ~BNX2X_DEF_SB_ATT_IDX; 5701 } 5702 5703 /* SP events: STAT_QUERY and others */ 5704 if (status & BNX2X_DEF_SB_IDX) { 5705 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 5706 5707 if (FCOE_INIT(bp) && 5708 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 5709 /* Prevent local bottom-halves from running as 5710 * we are going to change the local NAPI list. 5711 */ 5712 local_bh_disable(); 5713 napi_schedule(&bnx2x_fcoe(bp, napi)); 5714 local_bh_enable(); 5715 } 5716 5717 /* Handle EQ completions */ 5718 bnx2x_eq_int(bp); 5719 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 5720 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 5721 5722 status &= ~BNX2X_DEF_SB_IDX; 5723 } 5724 5725 /* if status is non zero then perhaps something went wrong */ 5726 if (unlikely(status)) 5727 DP(BNX2X_MSG_SP, 5728 "got an unknown interrupt! (status 0x%x)\n", status); 5729 5730 /* ack status block only if something was actually handled */ 5731 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 5732 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 5733 } 5734 5735 /* afex - poll to check if VIFSET_ACK should be sent to MFW */ 5736 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, 5737 &bp->sp_state)) { 5738 bnx2x_link_report(bp); 5739 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5740 } 5741 } 5742 5743 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 5744 { 5745 struct net_device *dev = dev_instance; 5746 struct bnx2x *bp = netdev_priv(dev); 5747 5748 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 5749 IGU_INT_DISABLE, 0); 5750 5751 #ifdef BNX2X_STOP_ON_ERROR 5752 if (unlikely(bp->panic)) 5753 return IRQ_HANDLED; 5754 #endif 5755 5756 if (CNIC_LOADED(bp)) { 5757 struct cnic_ops *c_ops; 5758 5759 rcu_read_lock(); 5760 c_ops = rcu_dereference(bp->cnic_ops); 5761 if (c_ops) 5762 c_ops->cnic_handler(bp->cnic_data, NULL); 5763 rcu_read_unlock(); 5764 } 5765 5766 /* schedule sp task to perform default status block work, ack 5767 * attentions and enable interrupts. 5768 */ 5769 bnx2x_schedule_sp_task(bp); 5770 5771 return IRQ_HANDLED; 5772 } 5773 5774 /* end of slow path */ 5775 5776 void bnx2x_drv_pulse(struct bnx2x *bp) 5777 { 5778 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 5779 bp->fw_drv_pulse_wr_seq); 5780 } 5781 5782 static void bnx2x_timer(struct timer_list *t) 5783 { 5784 struct bnx2x *bp = from_timer(bp, t, timer); 5785 5786 if (!netif_running(bp->dev)) 5787 return; 5788 5789 if (IS_PF(bp) && 5790 !BP_NOMCP(bp)) { 5791 int mb_idx = BP_FW_MB_IDX(bp); 5792 u16 drv_pulse; 5793 u16 mcp_pulse; 5794 5795 ++bp->fw_drv_pulse_wr_seq; 5796 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 5797 drv_pulse = bp->fw_drv_pulse_wr_seq; 5798 bnx2x_drv_pulse(bp); 5799 5800 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 5801 MCP_PULSE_SEQ_MASK); 5802 /* The delta between driver pulse and mcp response 5803 * should not get too big. If the MFW is more than 5 pulses 5804 * behind, we should worry about it enough to generate an error 5805 * log. 5806 */ 5807 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) 5808 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 5809 drv_pulse, mcp_pulse); 5810 } 5811 5812 if (bp->state == BNX2X_STATE_OPEN) 5813 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 5814 5815 /* sample pf vf bulletin board for new posts from pf */ 5816 if (IS_VF(bp)) 5817 bnx2x_timer_sriov(bp); 5818 5819 mod_timer(&bp->timer, jiffies + bp->current_interval); 5820 } 5821 5822 /* end of Statistics */ 5823 5824 /* nic init */ 5825 5826 /* 5827 * nic init service functions 5828 */ 5829 5830 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 5831 { 5832 u32 i; 5833 if (!(len%4) && !(addr%4)) 5834 for (i = 0; i < len; i += 4) 5835 REG_WR(bp, addr + i, fill); 5836 else 5837 for (i = 0; i < len; i++) 5838 REG_WR8(bp, addr + i, fill); 5839 } 5840 5841 /* helper: writes FP SP data to FW - data_size in dwords */ 5842 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 5843 int fw_sb_id, 5844 u32 *sb_data_p, 5845 u32 data_size) 5846 { 5847 int index; 5848 for (index = 0; index < data_size; index++) 5849 REG_WR(bp, BAR_CSTRORM_INTMEM + 5850 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 5851 sizeof(u32)*index, 5852 *(sb_data_p + index)); 5853 } 5854 5855 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 5856 { 5857 u32 *sb_data_p; 5858 u32 data_size = 0; 5859 struct hc_status_block_data_e2 sb_data_e2; 5860 struct hc_status_block_data_e1x sb_data_e1x; 5861 5862 /* disable the function first */ 5863 if (!CHIP_IS_E1x(bp)) { 5864 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5865 sb_data_e2.common.state = SB_DISABLED; 5866 sb_data_e2.common.p_func.vf_valid = false; 5867 sb_data_p = (u32 *)&sb_data_e2; 5868 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5869 } else { 5870 memset(&sb_data_e1x, 0, 5871 sizeof(struct hc_status_block_data_e1x)); 5872 sb_data_e1x.common.state = SB_DISABLED; 5873 sb_data_e1x.common.p_func.vf_valid = false; 5874 sb_data_p = (u32 *)&sb_data_e1x; 5875 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5876 } 5877 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5878 5879 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5880 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 5881 CSTORM_STATUS_BLOCK_SIZE); 5882 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5883 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 5884 CSTORM_SYNC_BLOCK_SIZE); 5885 } 5886 5887 /* helper: writes SP SB data to FW */ 5888 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 5889 struct hc_sp_status_block_data *sp_sb_data) 5890 { 5891 int func = BP_FUNC(bp); 5892 int i; 5893 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 5894 REG_WR(bp, BAR_CSTRORM_INTMEM + 5895 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 5896 i*sizeof(u32), 5897 *((u32 *)sp_sb_data + i)); 5898 } 5899 5900 static void bnx2x_zero_sp_sb(struct bnx2x *bp) 5901 { 5902 int func = BP_FUNC(bp); 5903 struct hc_sp_status_block_data sp_sb_data; 5904 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5905 5906 sp_sb_data.state = SB_DISABLED; 5907 sp_sb_data.p_func.vf_valid = false; 5908 5909 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5910 5911 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5912 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 5913 CSTORM_SP_STATUS_BLOCK_SIZE); 5914 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5915 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 5916 CSTORM_SP_SYNC_BLOCK_SIZE); 5917 } 5918 5919 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 5920 int igu_sb_id, int igu_seg_id) 5921 { 5922 hc_sm->igu_sb_id = igu_sb_id; 5923 hc_sm->igu_seg_id = igu_seg_id; 5924 hc_sm->timer_value = 0xFF; 5925 hc_sm->time_to_expire = 0xFFFFFFFF; 5926 } 5927 5928 /* allocates state machine ids. */ 5929 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5930 { 5931 /* zero out state machine indices */ 5932 /* rx indices */ 5933 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5934 5935 /* tx indices */ 5936 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5937 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5938 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5939 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5940 5941 /* map indices */ 5942 /* rx indices */ 5943 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5944 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5945 5946 /* tx indices */ 5947 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5948 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5949 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5950 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5951 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5952 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5953 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5954 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5955 } 5956 5957 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5958 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5959 { 5960 int igu_seg_id; 5961 5962 struct hc_status_block_data_e2 sb_data_e2; 5963 struct hc_status_block_data_e1x sb_data_e1x; 5964 struct hc_status_block_sm *hc_sm_p; 5965 int data_size; 5966 u32 *sb_data_p; 5967 5968 if (CHIP_INT_MODE_IS_BC(bp)) 5969 igu_seg_id = HC_SEG_ACCESS_NORM; 5970 else 5971 igu_seg_id = IGU_SEG_ACCESS_NORM; 5972 5973 bnx2x_zero_fp_sb(bp, fw_sb_id); 5974 5975 if (!CHIP_IS_E1x(bp)) { 5976 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5977 sb_data_e2.common.state = SB_ENABLED; 5978 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5979 sb_data_e2.common.p_func.vf_id = vfid; 5980 sb_data_e2.common.p_func.vf_valid = vf_valid; 5981 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5982 sb_data_e2.common.same_igu_sb_1b = true; 5983 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5984 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5985 hc_sm_p = sb_data_e2.common.state_machine; 5986 sb_data_p = (u32 *)&sb_data_e2; 5987 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5988 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5989 } else { 5990 memset(&sb_data_e1x, 0, 5991 sizeof(struct hc_status_block_data_e1x)); 5992 sb_data_e1x.common.state = SB_ENABLED; 5993 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5994 sb_data_e1x.common.p_func.vf_id = 0xff; 5995 sb_data_e1x.common.p_func.vf_valid = false; 5996 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5997 sb_data_e1x.common.same_igu_sb_1b = true; 5998 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 5999 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 6000 hc_sm_p = sb_data_e1x.common.state_machine; 6001 sb_data_p = (u32 *)&sb_data_e1x; 6002 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 6003 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 6004 } 6005 6006 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 6007 igu_sb_id, igu_seg_id); 6008 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 6009 igu_sb_id, igu_seg_id); 6010 6011 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 6012 6013 /* write indices to HW - PCI guarantees endianity of regpairs */ 6014 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 6015 } 6016 6017 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 6018 u16 tx_usec, u16 rx_usec) 6019 { 6020 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 6021 false, rx_usec); 6022 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6023 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 6024 tx_usec); 6025 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6026 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 6027 tx_usec); 6028 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6029 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 6030 tx_usec); 6031 } 6032 6033 static void bnx2x_init_def_sb(struct bnx2x *bp) 6034 { 6035 struct host_sp_status_block *def_sb = bp->def_status_blk; 6036 dma_addr_t mapping = bp->def_status_blk_mapping; 6037 int igu_sp_sb_index; 6038 int igu_seg_id; 6039 int port = BP_PORT(bp); 6040 int func = BP_FUNC(bp); 6041 int reg_offset, reg_offset_en5; 6042 u64 section; 6043 int index; 6044 struct hc_sp_status_block_data sp_sb_data; 6045 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 6046 6047 if (CHIP_INT_MODE_IS_BC(bp)) { 6048 igu_sp_sb_index = DEF_SB_IGU_ID; 6049 igu_seg_id = HC_SEG_ACCESS_DEF; 6050 } else { 6051 igu_sp_sb_index = bp->igu_dsb_id; 6052 igu_seg_id = IGU_SEG_ACCESS_DEF; 6053 } 6054 6055 /* ATTN */ 6056 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 6057 atten_status_block); 6058 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 6059 6060 bp->attn_state = 0; 6061 6062 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6063 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6064 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 6065 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 6066 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 6067 int sindex; 6068 /* take care of sig[0]..sig[4] */ 6069 for (sindex = 0; sindex < 4; sindex++) 6070 bp->attn_group[index].sig[sindex] = 6071 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 6072 6073 if (!CHIP_IS_E1x(bp)) 6074 /* 6075 * enable5 is separate from the rest of the registers, 6076 * and therefore the address skip is 4 6077 * and not 16 between the different groups 6078 */ 6079 bp->attn_group[index].sig[4] = REG_RD(bp, 6080 reg_offset_en5 + 0x4*index); 6081 else 6082 bp->attn_group[index].sig[4] = 0; 6083 } 6084 6085 if (bp->common.int_block == INT_BLOCK_HC) { 6086 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 6087 HC_REG_ATTN_MSG0_ADDR_L); 6088 6089 REG_WR(bp, reg_offset, U64_LO(section)); 6090 REG_WR(bp, reg_offset + 4, U64_HI(section)); 6091 } else if (!CHIP_IS_E1x(bp)) { 6092 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 6093 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 6094 } 6095 6096 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 6097 sp_sb); 6098 6099 bnx2x_zero_sp_sb(bp); 6100 6101 /* PCI guarantees endianity of regpairs */ 6102 sp_sb_data.state = SB_ENABLED; 6103 sp_sb_data.host_sb_addr.lo = U64_LO(section); 6104 sp_sb_data.host_sb_addr.hi = U64_HI(section); 6105 sp_sb_data.igu_sb_id = igu_sp_sb_index; 6106 sp_sb_data.igu_seg_id = igu_seg_id; 6107 sp_sb_data.p_func.pf_id = func; 6108 sp_sb_data.p_func.vnic_id = BP_VN(bp); 6109 sp_sb_data.p_func.vf_id = 0xff; 6110 6111 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 6112 6113 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 6114 } 6115 6116 void bnx2x_update_coalesce(struct bnx2x *bp) 6117 { 6118 int i; 6119 6120 for_each_eth_queue(bp, i) 6121 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 6122 bp->tx_ticks, bp->rx_ticks); 6123 } 6124 6125 static void bnx2x_init_sp_ring(struct bnx2x *bp) 6126 { 6127 spin_lock_init(&bp->spq_lock); 6128 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 6129 6130 bp->spq_prod_idx = 0; 6131 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 6132 bp->spq_prod_bd = bp->spq; 6133 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 6134 } 6135 6136 static void bnx2x_init_eq_ring(struct bnx2x *bp) 6137 { 6138 int i; 6139 for (i = 1; i <= NUM_EQ_PAGES; i++) { 6140 union event_ring_elem *elem = 6141 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 6142 6143 elem->next_page.addr.hi = 6144 cpu_to_le32(U64_HI(bp->eq_mapping + 6145 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 6146 elem->next_page.addr.lo = 6147 cpu_to_le32(U64_LO(bp->eq_mapping + 6148 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 6149 } 6150 bp->eq_cons = 0; 6151 bp->eq_prod = NUM_EQ_DESC; 6152 bp->eq_cons_sb = BNX2X_EQ_INDEX; 6153 /* we want a warning message before it gets wrought... */ 6154 atomic_set(&bp->eq_spq_left, 6155 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 6156 } 6157 6158 /* called with netif_addr_lock_bh() */ 6159 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 6160 unsigned long rx_mode_flags, 6161 unsigned long rx_accept_flags, 6162 unsigned long tx_accept_flags, 6163 unsigned long ramrod_flags) 6164 { 6165 struct bnx2x_rx_mode_ramrod_params ramrod_param; 6166 int rc; 6167 6168 memset(&ramrod_param, 0, sizeof(ramrod_param)); 6169 6170 /* Prepare ramrod parameters */ 6171 ramrod_param.cid = 0; 6172 ramrod_param.cl_id = cl_id; 6173 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 6174 ramrod_param.func_id = BP_FUNC(bp); 6175 6176 ramrod_param.pstate = &bp->sp_state; 6177 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 6178 6179 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 6180 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 6181 6182 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 6183 6184 ramrod_param.ramrod_flags = ramrod_flags; 6185 ramrod_param.rx_mode_flags = rx_mode_flags; 6186 6187 ramrod_param.rx_accept_flags = rx_accept_flags; 6188 ramrod_param.tx_accept_flags = tx_accept_flags; 6189 6190 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 6191 if (rc < 0) { 6192 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 6193 return rc; 6194 } 6195 6196 return 0; 6197 } 6198 6199 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, 6200 unsigned long *rx_accept_flags, 6201 unsigned long *tx_accept_flags) 6202 { 6203 /* Clear the flags first */ 6204 *rx_accept_flags = 0; 6205 *tx_accept_flags = 0; 6206 6207 switch (rx_mode) { 6208 case BNX2X_RX_MODE_NONE: 6209 /* 6210 * 'drop all' supersedes any accept flags that may have been 6211 * passed to the function. 6212 */ 6213 break; 6214 case BNX2X_RX_MODE_NORMAL: 6215 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6216 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); 6217 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6218 6219 /* internal switching mode */ 6220 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6221 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); 6222 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6223 6224 if (bp->accept_any_vlan) { 6225 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6226 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6227 } 6228 6229 break; 6230 case BNX2X_RX_MODE_ALLMULTI: 6231 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6232 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 6233 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6234 6235 /* internal switching mode */ 6236 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6237 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 6238 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6239 6240 if (bp->accept_any_vlan) { 6241 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6242 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6243 } 6244 6245 break; 6246 case BNX2X_RX_MODE_PROMISC: 6247 /* According to definition of SI mode, iface in promisc mode 6248 * should receive matched and unmatched (in resolution of port) 6249 * unicast packets. 6250 */ 6251 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); 6252 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6253 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 6254 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6255 6256 /* internal switching mode */ 6257 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 6258 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6259 6260 if (IS_MF_SI(bp)) 6261 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); 6262 else 6263 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6264 6265 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6266 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6267 6268 break; 6269 default: 6270 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); 6271 return -EINVAL; 6272 } 6273 6274 return 0; 6275 } 6276 6277 /* called with netif_addr_lock_bh() */ 6278 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) 6279 { 6280 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 6281 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 6282 int rc; 6283 6284 if (!NO_FCOE(bp)) 6285 /* Configure rx_mode of FCoE Queue */ 6286 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 6287 6288 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, 6289 &tx_accept_flags); 6290 if (rc) 6291 return rc; 6292 6293 __set_bit(RAMROD_RX, &ramrod_flags); 6294 __set_bit(RAMROD_TX, &ramrod_flags); 6295 6296 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, 6297 rx_accept_flags, tx_accept_flags, 6298 ramrod_flags); 6299 } 6300 6301 static void bnx2x_init_internal_common(struct bnx2x *bp) 6302 { 6303 int i; 6304 6305 /* Zero this manually as its initialization is 6306 currently missing in the initTool */ 6307 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 6308 REG_WR(bp, BAR_USTRORM_INTMEM + 6309 USTORM_AGG_DATA_OFFSET + i * 4, 0); 6310 if (!CHIP_IS_E1x(bp)) { 6311 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 6312 CHIP_INT_MODE_IS_BC(bp) ? 6313 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 6314 } 6315 } 6316 6317 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 6318 { 6319 switch (load_code) { 6320 case FW_MSG_CODE_DRV_LOAD_COMMON: 6321 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 6322 bnx2x_init_internal_common(bp); 6323 fallthrough; 6324 6325 case FW_MSG_CODE_DRV_LOAD_PORT: 6326 /* nothing to do */ 6327 fallthrough; 6328 6329 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 6330 /* internal memory per function is 6331 initialized inside bnx2x_pf_init */ 6332 break; 6333 6334 default: 6335 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 6336 break; 6337 } 6338 } 6339 6340 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 6341 { 6342 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); 6343 } 6344 6345 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 6346 { 6347 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); 6348 } 6349 6350 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 6351 { 6352 if (CHIP_IS_E1x(fp->bp)) 6353 return BP_L_ID(fp->bp) + fp->index; 6354 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 6355 return bnx2x_fp_igu_sb_id(fp); 6356 } 6357 6358 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 6359 { 6360 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 6361 u8 cos; 6362 unsigned long q_type = 0; 6363 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 6364 fp->rx_queue = fp_idx; 6365 fp->cid = fp_idx; 6366 fp->cl_id = bnx2x_fp_cl_id(fp); 6367 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 6368 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 6369 /* qZone id equals to FW (per path) client id */ 6370 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 6371 6372 /* init shortcut */ 6373 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 6374 6375 /* Setup SB indices */ 6376 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 6377 6378 /* Configure Queue State object */ 6379 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 6380 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 6381 6382 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 6383 6384 /* init tx data */ 6385 for_each_cos_in_tx_queue(fp, cos) { 6386 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], 6387 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), 6388 FP_COS_TO_TXQ(fp, cos, bp), 6389 BNX2X_TX_SB_INDEX_BASE + cos, fp); 6390 cids[cos] = fp->txdata_ptr[cos]->cid; 6391 } 6392 6393 /* nothing more for vf to do here */ 6394 if (IS_VF(bp)) 6395 return; 6396 6397 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 6398 fp->fw_sb_id, fp->igu_sb_id); 6399 bnx2x_update_fpsb_idx(fp); 6400 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, 6401 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 6402 bnx2x_sp_mapping(bp, q_rdata), q_type); 6403 6404 /** 6405 * Configure classification DBs: Always enable Tx switching 6406 */ 6407 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 6408 6409 DP(NETIF_MSG_IFUP, 6410 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 6411 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 6412 fp->igu_sb_id); 6413 } 6414 6415 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 6416 { 6417 int i; 6418 6419 for (i = 1; i <= NUM_TX_RINGS; i++) { 6420 struct eth_tx_next_bd *tx_next_bd = 6421 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 6422 6423 tx_next_bd->addr_hi = 6424 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 6425 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6426 tx_next_bd->addr_lo = 6427 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 6428 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6429 } 6430 6431 *txdata->tx_cons_sb = cpu_to_le16(0); 6432 6433 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 6434 txdata->tx_db.data.zero_fill1 = 0; 6435 txdata->tx_db.data.prod = 0; 6436 6437 txdata->tx_pkt_prod = 0; 6438 txdata->tx_pkt_cons = 0; 6439 txdata->tx_bd_prod = 0; 6440 txdata->tx_bd_cons = 0; 6441 txdata->tx_pkt = 0; 6442 } 6443 6444 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) 6445 { 6446 int i; 6447 6448 for_each_tx_queue_cnic(bp, i) 6449 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); 6450 } 6451 6452 static void bnx2x_init_tx_rings(struct bnx2x *bp) 6453 { 6454 int i; 6455 u8 cos; 6456 6457 for_each_eth_queue(bp, i) 6458 for_each_cos_in_tx_queue(&bp->fp[i], cos) 6459 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); 6460 } 6461 6462 static void bnx2x_init_fcoe_fp(struct bnx2x *bp) 6463 { 6464 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 6465 unsigned long q_type = 0; 6466 6467 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 6468 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 6469 BNX2X_FCOE_ETH_CL_ID_IDX); 6470 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 6471 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 6472 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 6473 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 6474 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 6475 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 6476 fp); 6477 6478 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 6479 6480 /* qZone id equals to FW (per path) client id */ 6481 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 6482 /* init shortcut */ 6483 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 6484 bnx2x_rx_ustorm_prods_offset(fp); 6485 6486 /* Configure Queue State object */ 6487 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 6488 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 6489 6490 /* No multi-CoS for FCoE L2 client */ 6491 BUG_ON(fp->max_cos != 1); 6492 6493 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 6494 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 6495 bnx2x_sp_mapping(bp, q_rdata), q_type); 6496 6497 DP(NETIF_MSG_IFUP, 6498 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 6499 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 6500 fp->igu_sb_id); 6501 } 6502 6503 void bnx2x_nic_init_cnic(struct bnx2x *bp) 6504 { 6505 if (!NO_FCOE(bp)) 6506 bnx2x_init_fcoe_fp(bp); 6507 6508 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 6509 BNX2X_VF_ID_INVALID, false, 6510 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 6511 6512 /* ensure status block indices were read */ 6513 rmb(); 6514 bnx2x_init_rx_rings_cnic(bp); 6515 bnx2x_init_tx_rings_cnic(bp); 6516 6517 /* flush all */ 6518 mb(); 6519 } 6520 6521 void bnx2x_pre_irq_nic_init(struct bnx2x *bp) 6522 { 6523 int i; 6524 6525 /* Setup NIC internals and enable interrupts */ 6526 for_each_eth_queue(bp, i) 6527 bnx2x_init_eth_fp(bp, i); 6528 6529 /* ensure status block indices were read */ 6530 rmb(); 6531 bnx2x_init_rx_rings(bp); 6532 bnx2x_init_tx_rings(bp); 6533 6534 if (IS_PF(bp)) { 6535 /* Initialize MOD_ABS interrupts */ 6536 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 6537 bp->common.shmem_base, 6538 bp->common.shmem2_base, BP_PORT(bp)); 6539 6540 /* initialize the default status block and sp ring */ 6541 bnx2x_init_def_sb(bp); 6542 bnx2x_update_dsb_idx(bp); 6543 bnx2x_init_sp_ring(bp); 6544 } else { 6545 bnx2x_memset_stats(bp); 6546 } 6547 } 6548 6549 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) 6550 { 6551 bnx2x_init_eq_ring(bp); 6552 bnx2x_init_internal(bp, load_code); 6553 bnx2x_pf_init(bp); 6554 bnx2x_stats_init(bp); 6555 6556 /* flush all before enabling interrupts */ 6557 mb(); 6558 6559 bnx2x_int_enable(bp); 6560 6561 /* Check for SPIO5 */ 6562 bnx2x_attn_int_deasserted0(bp, 6563 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 6564 AEU_INPUTS_ATTN_BITS_SPIO5); 6565 } 6566 6567 /* gzip service functions */ 6568 static int bnx2x_gunzip_init(struct bnx2x *bp) 6569 { 6570 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 6571 &bp->gunzip_mapping, GFP_KERNEL); 6572 if (bp->gunzip_buf == NULL) 6573 goto gunzip_nomem1; 6574 6575 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 6576 if (bp->strm == NULL) 6577 goto gunzip_nomem2; 6578 6579 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 6580 if (bp->strm->workspace == NULL) 6581 goto gunzip_nomem3; 6582 6583 return 0; 6584 6585 gunzip_nomem3: 6586 kfree(bp->strm); 6587 bp->strm = NULL; 6588 6589 gunzip_nomem2: 6590 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6591 bp->gunzip_mapping); 6592 bp->gunzip_buf = NULL; 6593 6594 gunzip_nomem1: 6595 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 6596 return -ENOMEM; 6597 } 6598 6599 static void bnx2x_gunzip_end(struct bnx2x *bp) 6600 { 6601 if (bp->strm) { 6602 vfree(bp->strm->workspace); 6603 kfree(bp->strm); 6604 bp->strm = NULL; 6605 } 6606 6607 if (bp->gunzip_buf) { 6608 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6609 bp->gunzip_mapping); 6610 bp->gunzip_buf = NULL; 6611 } 6612 } 6613 6614 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 6615 { 6616 int n, rc; 6617 6618 /* check gzip header */ 6619 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 6620 BNX2X_ERR("Bad gzip header\n"); 6621 return -EINVAL; 6622 } 6623 6624 n = 10; 6625 6626 #define FNAME 0x8 6627 6628 if (zbuf[3] & FNAME) 6629 while ((zbuf[n++] != 0) && (n < len)); 6630 6631 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 6632 bp->strm->avail_in = len - n; 6633 bp->strm->next_out = bp->gunzip_buf; 6634 bp->strm->avail_out = FW_BUF_SIZE; 6635 6636 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 6637 if (rc != Z_OK) 6638 return rc; 6639 6640 rc = zlib_inflate(bp->strm, Z_FINISH); 6641 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 6642 netdev_err(bp->dev, "Firmware decompression error: %s\n", 6643 bp->strm->msg); 6644 6645 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 6646 if (bp->gunzip_outlen & 0x3) 6647 netdev_err(bp->dev, 6648 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 6649 bp->gunzip_outlen); 6650 bp->gunzip_outlen >>= 2; 6651 6652 zlib_inflateEnd(bp->strm); 6653 6654 if (rc == Z_STREAM_END) 6655 return 0; 6656 6657 return rc; 6658 } 6659 6660 /* nic load/unload */ 6661 6662 /* 6663 * General service functions 6664 */ 6665 6666 /* send a NIG loopback debug packet */ 6667 static void bnx2x_lb_pckt(struct bnx2x *bp) 6668 { 6669 u32 wb_write[3]; 6670 6671 /* Ethernet source and destination addresses */ 6672 wb_write[0] = 0x55555555; 6673 wb_write[1] = 0x55555555; 6674 wb_write[2] = 0x20; /* SOP */ 6675 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6676 6677 /* NON-IP protocol */ 6678 wb_write[0] = 0x09000000; 6679 wb_write[1] = 0x55555555; 6680 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 6681 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6682 } 6683 6684 /* some of the internal memories 6685 * are not directly readable from the driver 6686 * to test them we send debug packets 6687 */ 6688 static int bnx2x_int_mem_test(struct bnx2x *bp) 6689 { 6690 int factor; 6691 int count, i; 6692 u32 val = 0; 6693 6694 if (CHIP_REV_IS_FPGA(bp)) 6695 factor = 120; 6696 else if (CHIP_REV_IS_EMUL(bp)) 6697 factor = 200; 6698 else 6699 factor = 1; 6700 6701 /* Disable inputs of parser neighbor blocks */ 6702 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6703 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6704 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6705 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6706 6707 /* Write 0 to parser credits for CFC search request */ 6708 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6709 6710 /* send Ethernet packet */ 6711 bnx2x_lb_pckt(bp); 6712 6713 /* TODO do i reset NIG statistic? */ 6714 /* Wait until NIG register shows 1 packet of size 0x10 */ 6715 count = 1000 * factor; 6716 while (count) { 6717 6718 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6719 val = *bnx2x_sp(bp, wb_data[0]); 6720 if (val == 0x10) 6721 break; 6722 6723 usleep_range(10000, 20000); 6724 count--; 6725 } 6726 if (val != 0x10) { 6727 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6728 return -1; 6729 } 6730 6731 /* Wait until PRS register shows 1 packet */ 6732 count = 1000 * factor; 6733 while (count) { 6734 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6735 if (val == 1) 6736 break; 6737 6738 usleep_range(10000, 20000); 6739 count--; 6740 } 6741 if (val != 0x1) { 6742 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6743 return -2; 6744 } 6745 6746 /* Reset and init BRB, PRS */ 6747 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6748 msleep(50); 6749 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6750 msleep(50); 6751 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6752 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6753 6754 DP(NETIF_MSG_HW, "part2\n"); 6755 6756 /* Disable inputs of parser neighbor blocks */ 6757 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6758 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6759 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6760 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6761 6762 /* Write 0 to parser credits for CFC search request */ 6763 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6764 6765 /* send 10 Ethernet packets */ 6766 for (i = 0; i < 10; i++) 6767 bnx2x_lb_pckt(bp); 6768 6769 /* Wait until NIG register shows 10 + 1 6770 packets of size 11*0x10 = 0xb0 */ 6771 count = 1000 * factor; 6772 while (count) { 6773 6774 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6775 val = *bnx2x_sp(bp, wb_data[0]); 6776 if (val == 0xb0) 6777 break; 6778 6779 usleep_range(10000, 20000); 6780 count--; 6781 } 6782 if (val != 0xb0) { 6783 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6784 return -3; 6785 } 6786 6787 /* Wait until PRS register shows 2 packets */ 6788 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6789 if (val != 2) 6790 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6791 6792 /* Write 1 to parser credits for CFC search request */ 6793 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 6794 6795 /* Wait until PRS register shows 3 packets */ 6796 msleep(10 * factor); 6797 /* Wait until NIG register shows 1 packet of size 0x10 */ 6798 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6799 if (val != 3) 6800 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6801 6802 /* clear NIG EOP FIFO */ 6803 for (i = 0; i < 11; i++) 6804 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 6805 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 6806 if (val != 1) { 6807 BNX2X_ERR("clear of NIG failed\n"); 6808 return -4; 6809 } 6810 6811 /* Reset and init BRB, PRS, NIG */ 6812 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6813 msleep(50); 6814 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6815 msleep(50); 6816 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6817 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6818 if (!CNIC_SUPPORT(bp)) 6819 /* set NIC mode */ 6820 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6821 6822 /* Enable inputs of parser neighbor blocks */ 6823 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 6824 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 6825 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 6826 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 6827 6828 DP(NETIF_MSG_HW, "done\n"); 6829 6830 return 0; /* OK */ 6831 } 6832 6833 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 6834 { 6835 u32 val; 6836 6837 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6838 if (!CHIP_IS_E1x(bp)) 6839 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 6840 else 6841 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 6842 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6843 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6844 /* 6845 * mask read length error interrupts in brb for parser 6846 * (parsing unit and 'checksum and crc' unit) 6847 * these errors are legal (PU reads fixed length and CAC can cause 6848 * read length error on truncated packets) 6849 */ 6850 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 6851 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 6852 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 6853 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 6854 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 6855 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 6856 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 6857 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 6858 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 6859 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 6860 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 6861 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 6862 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 6863 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 6864 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 6865 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 6866 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 6867 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 6868 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 6869 6870 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 6871 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 6872 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; 6873 if (!CHIP_IS_E1x(bp)) 6874 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 6875 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; 6876 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); 6877 6878 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 6879 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 6880 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 6881 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 6882 6883 if (!CHIP_IS_E1x(bp)) 6884 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 6885 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 6886 6887 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 6888 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 6889 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 6890 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 6891 } 6892 6893 static void bnx2x_reset_common(struct bnx2x *bp) 6894 { 6895 u32 val = 0x1400; 6896 6897 /* reset_common */ 6898 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6899 0xd3ffff7f); 6900 6901 if (CHIP_IS_E3(bp)) { 6902 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6903 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6904 } 6905 6906 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 6907 } 6908 6909 static void bnx2x_setup_dmae(struct bnx2x *bp) 6910 { 6911 bp->dmae_ready = 0; 6912 spin_lock_init(&bp->dmae_lock); 6913 } 6914 6915 static void bnx2x_init_pxp(struct bnx2x *bp) 6916 { 6917 u16 devctl; 6918 int r_order, w_order; 6919 6920 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); 6921 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 6922 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 6923 if (bp->mrrs == -1) 6924 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 6925 else { 6926 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 6927 r_order = bp->mrrs; 6928 } 6929 6930 bnx2x_init_pxp_arb(bp, r_order, w_order); 6931 } 6932 6933 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 6934 { 6935 int is_required; 6936 u32 val; 6937 int port; 6938 6939 if (BP_NOMCP(bp)) 6940 return; 6941 6942 is_required = 0; 6943 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 6944 SHARED_HW_CFG_FAN_FAILURE_MASK; 6945 6946 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 6947 is_required = 1; 6948 6949 /* 6950 * The fan failure mechanism is usually related to the PHY type since 6951 * the power consumption of the board is affected by the PHY. Currently, 6952 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 6953 */ 6954 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 6955 for (port = PORT_0; port < PORT_MAX; port++) { 6956 is_required |= 6957 bnx2x_fan_failure_det_req( 6958 bp, 6959 bp->common.shmem_base, 6960 bp->common.shmem2_base, 6961 port); 6962 } 6963 6964 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 6965 6966 if (is_required == 0) 6967 return; 6968 6969 /* Fan failure is indicated by SPIO 5 */ 6970 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 6971 6972 /* set to active low mode */ 6973 val = REG_RD(bp, MISC_REG_SPIO_INT); 6974 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 6975 REG_WR(bp, MISC_REG_SPIO_INT, val); 6976 6977 /* enable interrupt to signal the IGU */ 6978 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6979 val |= MISC_SPIO_SPIO5; 6980 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 6981 } 6982 6983 void bnx2x_pf_disable(struct bnx2x *bp) 6984 { 6985 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 6986 val &= ~IGU_PF_CONF_FUNC_EN; 6987 6988 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 6989 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6990 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 6991 } 6992 6993 static void bnx2x__common_init_phy(struct bnx2x *bp) 6994 { 6995 u32 shmem_base[2], shmem2_base[2]; 6996 /* Avoid common init in case MFW supports LFA */ 6997 if (SHMEM2_RD(bp, size) > 6998 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 6999 return; 7000 shmem_base[0] = bp->common.shmem_base; 7001 shmem2_base[0] = bp->common.shmem2_base; 7002 if (!CHIP_IS_E1x(bp)) { 7003 shmem_base[1] = 7004 SHMEM2_RD(bp, other_shmem_base_addr); 7005 shmem2_base[1] = 7006 SHMEM2_RD(bp, other_shmem2_base_addr); 7007 } 7008 bnx2x_acquire_phy_lock(bp); 7009 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 7010 bp->common.chip_id); 7011 bnx2x_release_phy_lock(bp); 7012 } 7013 7014 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) 7015 { 7016 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); 7017 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); 7018 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); 7019 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); 7020 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); 7021 7022 /* make sure this value is 0 */ 7023 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 7024 7025 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); 7026 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); 7027 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); 7028 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); 7029 } 7030 7031 static void bnx2x_set_endianity(struct bnx2x *bp) 7032 { 7033 #ifdef __BIG_ENDIAN 7034 bnx2x_config_endianity(bp, 1); 7035 #else 7036 bnx2x_config_endianity(bp, 0); 7037 #endif 7038 } 7039 7040 static void bnx2x_reset_endianity(struct bnx2x *bp) 7041 { 7042 bnx2x_config_endianity(bp, 0); 7043 } 7044 7045 /** 7046 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 7047 * 7048 * @bp: driver handle 7049 */ 7050 static int bnx2x_init_hw_common(struct bnx2x *bp) 7051 { 7052 u32 val; 7053 7054 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); 7055 7056 /* 7057 * take the RESET lock to protect undi_unload flow from accessing 7058 * registers while we're resetting the chip 7059 */ 7060 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 7061 7062 bnx2x_reset_common(bp); 7063 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 7064 7065 val = 0xfffc; 7066 if (CHIP_IS_E3(bp)) { 7067 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 7068 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 7069 } 7070 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 7071 7072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 7073 7074 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 7075 7076 if (!CHIP_IS_E1x(bp)) { 7077 u8 abs_func_id; 7078 7079 /** 7080 * 4-port mode or 2-port mode we need to turn of master-enable 7081 * for everyone, after that, turn it back on for self. 7082 * so, we disregard multi-function or not, and always disable 7083 * for all functions on the given path, this means 0,2,4,6 for 7084 * path 0 and 1,3,5,7 for path 1 7085 */ 7086 for (abs_func_id = BP_PATH(bp); 7087 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 7088 if (abs_func_id == BP_ABS_FUNC(bp)) { 7089 REG_WR(bp, 7090 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 7091 1); 7092 continue; 7093 } 7094 7095 bnx2x_pretend_func(bp, abs_func_id); 7096 /* clear pf enable */ 7097 bnx2x_pf_disable(bp); 7098 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 7099 } 7100 } 7101 7102 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 7103 if (CHIP_IS_E1(bp)) { 7104 /* enable HW interrupt from PXP on USDM overflow 7105 bit 16 on INT_MASK_0 */ 7106 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 7107 } 7108 7109 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 7110 bnx2x_init_pxp(bp); 7111 bnx2x_set_endianity(bp); 7112 bnx2x_ilt_init_page_size(bp, INITOP_SET); 7113 7114 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 7115 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 7116 7117 /* let the HW do it's magic ... */ 7118 msleep(100); 7119 /* finish PXP init */ 7120 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 7121 if (val != 1) { 7122 BNX2X_ERR("PXP2 CFG failed\n"); 7123 return -EBUSY; 7124 } 7125 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 7126 if (val != 1) { 7127 BNX2X_ERR("PXP2 RD_INIT failed\n"); 7128 return -EBUSY; 7129 } 7130 7131 /* Timers bug workaround E2 only. We need to set the entire ILT to 7132 * have entries with value "0" and valid bit on. 7133 * This needs to be done by the first PF that is loaded in a path 7134 * (i.e. common phase) 7135 */ 7136 if (!CHIP_IS_E1x(bp)) { 7137 /* In E2 there is a bug in the timers block that can cause function 6 / 7 7138 * (i.e. vnic3) to start even if it is marked as "scan-off". 7139 * This occurs when a different function (func2,3) is being marked 7140 * as "scan-off". Real-life scenario for example: if a driver is being 7141 * load-unloaded while func6,7 are down. This will cause the timer to access 7142 * the ilt, translate to a logical address and send a request to read/write. 7143 * Since the ilt for the function that is down is not valid, this will cause 7144 * a translation error which is unrecoverable. 7145 * The Workaround is intended to make sure that when this happens nothing fatal 7146 * will occur. The workaround: 7147 * 1. First PF driver which loads on a path will: 7148 * a. After taking the chip out of reset, by using pretend, 7149 * it will write "0" to the following registers of 7150 * the other vnics. 7151 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 7152 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 7153 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 7154 * And for itself it will write '1' to 7155 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 7156 * dmae-operations (writing to pram for example.) 7157 * note: can be done for only function 6,7 but cleaner this 7158 * way. 7159 * b. Write zero+valid to the entire ILT. 7160 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 7161 * VNIC3 (of that port). The range allocated will be the 7162 * entire ILT. This is needed to prevent ILT range error. 7163 * 2. Any PF driver load flow: 7164 * a. ILT update with the physical addresses of the allocated 7165 * logical pages. 7166 * b. Wait 20msec. - note that this timeout is needed to make 7167 * sure there are no requests in one of the PXP internal 7168 * queues with "old" ILT addresses. 7169 * c. PF enable in the PGLC. 7170 * d. Clear the was_error of the PF in the PGLC. (could have 7171 * occurred while driver was down) 7172 * e. PF enable in the CFC (WEAK + STRONG) 7173 * f. Timers scan enable 7174 * 3. PF driver unload flow: 7175 * a. Clear the Timers scan_en. 7176 * b. Polling for scan_on=0 for that PF. 7177 * c. Clear the PF enable bit in the PXP. 7178 * d. Clear the PF enable in the CFC (WEAK + STRONG) 7179 * e. Write zero+valid to all ILT entries (The valid bit must 7180 * stay set) 7181 * f. If this is VNIC 3 of a port then also init 7182 * first_timers_ilt_entry to zero and last_timers_ilt_entry 7183 * to the last entry in the ILT. 7184 * 7185 * Notes: 7186 * Currently the PF error in the PGLC is non recoverable. 7187 * In the future the there will be a recovery routine for this error. 7188 * Currently attention is masked. 7189 * Having an MCP lock on the load/unload process does not guarantee that 7190 * there is no Timer disable during Func6/7 enable. This is because the 7191 * Timers scan is currently being cleared by the MCP on FLR. 7192 * Step 2.d can be done only for PF6/7 and the driver can also check if 7193 * there is error before clearing it. But the flow above is simpler and 7194 * more general. 7195 * All ILT entries are written by zero+valid and not just PF6/7 7196 * ILT entries since in the future the ILT entries allocation for 7197 * PF-s might be dynamic. 7198 */ 7199 struct ilt_client_info ilt_cli; 7200 struct bnx2x_ilt ilt; 7201 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7202 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 7203 7204 /* initialize dummy TM client */ 7205 ilt_cli.start = 0; 7206 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7207 ilt_cli.client_num = ILT_CLIENT_TM; 7208 7209 /* Step 1: set zeroes to all ilt page entries with valid bit on 7210 * Step 2: set the timers first/last ilt entry to point 7211 * to the entire range to prevent ILT range error for 3rd/4th 7212 * vnic (this code assumes existence of the vnic) 7213 * 7214 * both steps performed by call to bnx2x_ilt_client_init_op() 7215 * with dummy TM client 7216 * 7217 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 7218 * and his brother are split registers 7219 */ 7220 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 7221 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 7222 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 7223 7224 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 7225 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 7226 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 7227 } 7228 7229 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 7230 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 7231 7232 if (!CHIP_IS_E1x(bp)) { 7233 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 7234 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 7235 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 7236 7237 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 7238 7239 /* let the HW do it's magic ... */ 7240 do { 7241 msleep(200); 7242 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 7243 } while (factor-- && (val != 1)); 7244 7245 if (val != 1) { 7246 BNX2X_ERR("ATC_INIT failed\n"); 7247 return -EBUSY; 7248 } 7249 } 7250 7251 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 7252 7253 bnx2x_iov_init_dmae(bp); 7254 7255 /* clean the DMAE memory */ 7256 bp->dmae_ready = 1; 7257 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 7258 7259 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 7260 7261 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 7262 7263 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 7264 7265 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 7266 7267 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 7268 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 7269 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 7270 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 7271 7272 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 7273 7274 /* QM queues pointers table */ 7275 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 7276 7277 /* soft reset pulse */ 7278 REG_WR(bp, QM_REG_SOFT_RESET, 1); 7279 REG_WR(bp, QM_REG_SOFT_RESET, 0); 7280 7281 if (CNIC_SUPPORT(bp)) 7282 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 7283 7284 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 7285 7286 if (!CHIP_REV_IS_SLOW(bp)) 7287 /* enable hw interrupt from doorbell Q */ 7288 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 7289 7290 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 7291 7292 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 7293 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 7294 7295 if (!CHIP_IS_E1(bp)) 7296 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 7297 7298 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { 7299 if (IS_MF_AFEX(bp)) { 7300 /* configure that VNTag and VLAN headers must be 7301 * received in afex mode 7302 */ 7303 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); 7304 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); 7305 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 7306 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 7307 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); 7308 } else { 7309 /* Bit-map indicating which L2 hdrs may appear 7310 * after the basic Ethernet header 7311 */ 7312 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 7313 bp->path_has_ovlan ? 7 : 6); 7314 } 7315 } 7316 7317 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 7318 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 7319 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 7320 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 7321 7322 if (!CHIP_IS_E1x(bp)) { 7323 /* reset VFC memories */ 7324 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 7325 VFC_MEMORIES_RST_REG_CAM_RST | 7326 VFC_MEMORIES_RST_REG_RAM_RST); 7327 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 7328 VFC_MEMORIES_RST_REG_CAM_RST | 7329 VFC_MEMORIES_RST_REG_RAM_RST); 7330 7331 msleep(20); 7332 } 7333 7334 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 7335 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 7336 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 7337 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 7338 7339 /* sync semi rtc */ 7340 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 7341 0x80000000); 7342 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 7343 0x80000000); 7344 7345 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 7346 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 7347 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 7348 7349 if (!CHIP_IS_E1x(bp)) { 7350 if (IS_MF_AFEX(bp)) { 7351 /* configure that VNTag and VLAN headers must be 7352 * sent in afex mode 7353 */ 7354 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); 7355 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); 7356 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 7357 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 7358 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); 7359 } else { 7360 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 7361 bp->path_has_ovlan ? 7 : 6); 7362 } 7363 } 7364 7365 REG_WR(bp, SRC_REG_SOFT_RST, 1); 7366 7367 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 7368 7369 if (CNIC_SUPPORT(bp)) { 7370 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 7371 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 7372 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 7373 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 7374 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 7375 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 7376 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 7377 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 7378 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 7379 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 7380 } 7381 REG_WR(bp, SRC_REG_SOFT_RST, 0); 7382 7383 if (sizeof(union cdu_context) != 1024) 7384 /* we currently assume that a context is 1024 bytes */ 7385 dev_alert(&bp->pdev->dev, 7386 "please adjust the size of cdu_context(%ld)\n", 7387 (long)sizeof(union cdu_context)); 7388 7389 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 7390 val = (4 << 24) + (0 << 12) + 1024; 7391 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 7392 7393 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 7394 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 7395 /* enable context validation interrupt from CFC */ 7396 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 7397 7398 /* set the thresholds to prevent CFC/CDU race */ 7399 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 7400 7401 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 7402 7403 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 7404 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 7405 7406 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 7407 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 7408 7409 /* Reset PCIE errors for debug */ 7410 REG_WR(bp, 0x2814, 0xffffffff); 7411 REG_WR(bp, 0x3820, 0xffffffff); 7412 7413 if (!CHIP_IS_E1x(bp)) { 7414 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 7415 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 7416 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 7417 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 7418 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 7419 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 7420 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 7421 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 7422 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 7423 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 7424 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 7425 } 7426 7427 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 7428 if (!CHIP_IS_E1(bp)) { 7429 /* in E3 this done in per-port section */ 7430 if (!CHIP_IS_E3(bp)) 7431 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7432 } 7433 if (CHIP_IS_E1H(bp)) 7434 /* not applicable for E2 (and above ...) */ 7435 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 7436 7437 if (CHIP_REV_IS_SLOW(bp)) 7438 msleep(200); 7439 7440 /* finish CFC init */ 7441 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 7442 if (val != 1) { 7443 BNX2X_ERR("CFC LL_INIT failed\n"); 7444 return -EBUSY; 7445 } 7446 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 7447 if (val != 1) { 7448 BNX2X_ERR("CFC AC_INIT failed\n"); 7449 return -EBUSY; 7450 } 7451 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 7452 if (val != 1) { 7453 BNX2X_ERR("CFC CAM_INIT failed\n"); 7454 return -EBUSY; 7455 } 7456 REG_WR(bp, CFC_REG_DEBUG0, 0); 7457 7458 if (CHIP_IS_E1(bp)) { 7459 /* read NIG statistic 7460 to see if this is our first up since powerup */ 7461 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 7462 val = *bnx2x_sp(bp, wb_data[0]); 7463 7464 /* do internal memory self test */ 7465 if ((val == 0) && bnx2x_int_mem_test(bp)) { 7466 BNX2X_ERR("internal mem self test failed\n"); 7467 return -EBUSY; 7468 } 7469 } 7470 7471 bnx2x_setup_fan_failure_detection(bp); 7472 7473 /* clear PXP2 attentions */ 7474 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 7475 7476 bnx2x_enable_blocks_attention(bp); 7477 bnx2x_enable_blocks_parity(bp); 7478 7479 if (!BP_NOMCP(bp)) { 7480 if (CHIP_IS_E1x(bp)) 7481 bnx2x__common_init_phy(bp); 7482 } else 7483 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 7484 7485 if (SHMEM2_HAS(bp, netproc_fw_ver)) 7486 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); 7487 7488 return 0; 7489 } 7490 7491 /** 7492 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 7493 * 7494 * @bp: driver handle 7495 */ 7496 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 7497 { 7498 int rc = bnx2x_init_hw_common(bp); 7499 7500 if (rc) 7501 return rc; 7502 7503 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 7504 if (!BP_NOMCP(bp)) 7505 bnx2x__common_init_phy(bp); 7506 7507 return 0; 7508 } 7509 7510 static int bnx2x_init_hw_port(struct bnx2x *bp) 7511 { 7512 int port = BP_PORT(bp); 7513 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 7514 u32 low, high; 7515 u32 val, reg; 7516 7517 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 7518 7519 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7520 7521 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 7522 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7523 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7524 7525 /* Timers bug workaround: disables the pf_master bit in pglue at 7526 * common phase, we need to enable it here before any dmae access are 7527 * attempted. Therefore we manually added the enable-master to the 7528 * port phase (it also happens in the function phase) 7529 */ 7530 if (!CHIP_IS_E1x(bp)) 7531 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 7532 7533 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 7534 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 7535 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 7536 bnx2x_init_block(bp, BLOCK_QM, init_phase); 7537 7538 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 7539 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 7540 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 7541 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 7542 7543 /* QM cid (connection) count */ 7544 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 7545 7546 if (CNIC_SUPPORT(bp)) { 7547 bnx2x_init_block(bp, BLOCK_TM, init_phase); 7548 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 7549 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 7550 } 7551 7552 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 7553 7554 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 7555 7556 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 7557 7558 if (IS_MF(bp)) 7559 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 7560 else if (bp->dev->mtu > 4096) { 7561 if (bp->flags & ONE_PORT_FLAG) 7562 low = 160; 7563 else { 7564 val = bp->dev->mtu; 7565 /* (24*1024 + val*4)/256 */ 7566 low = 96 + (val/64) + 7567 ((val % 64) ? 1 : 0); 7568 } 7569 } else 7570 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 7571 high = low + 56; /* 14*1024/256 */ 7572 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 7573 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 7574 } 7575 7576 if (CHIP_MODE_IS_4_PORT(bp)) 7577 REG_WR(bp, (BP_PORT(bp) ? 7578 BRB1_REG_MAC_GUARANTIED_1 : 7579 BRB1_REG_MAC_GUARANTIED_0), 40); 7580 7581 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 7582 if (CHIP_IS_E3B0(bp)) { 7583 if (IS_MF_AFEX(bp)) { 7584 /* configure headers for AFEX mode */ 7585 REG_WR(bp, BP_PORT(bp) ? 7586 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7587 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 7588 REG_WR(bp, BP_PORT(bp) ? 7589 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 7590 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 7591 REG_WR(bp, BP_PORT(bp) ? 7592 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 7593 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 7594 } else { 7595 /* Ovlan exists only if we are in multi-function + 7596 * switch-dependent mode, in switch-independent there 7597 * is no ovlan headers 7598 */ 7599 REG_WR(bp, BP_PORT(bp) ? 7600 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7601 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 7602 (bp->path_has_ovlan ? 7 : 6)); 7603 } 7604 } 7605 7606 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 7607 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 7608 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 7609 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 7610 7611 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 7612 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 7613 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 7614 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 7615 7616 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 7617 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 7618 7619 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 7620 7621 if (CHIP_IS_E1x(bp)) { 7622 /* configure PBF to work without PAUSE mtu 9000 */ 7623 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 7624 7625 /* update threshold */ 7626 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 7627 /* update init credit */ 7628 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 7629 7630 /* probe changes */ 7631 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 7632 udelay(50); 7633 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 7634 } 7635 7636 if (CNIC_SUPPORT(bp)) 7637 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 7638 7639 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 7640 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 7641 7642 if (CHIP_IS_E1(bp)) { 7643 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7644 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7645 } 7646 bnx2x_init_block(bp, BLOCK_HC, init_phase); 7647 7648 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 7649 7650 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 7651 /* init aeu_mask_attn_func_0/1: 7652 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use 7653 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF 7654 * bits 4-7 are used for "per vn group attention" */ 7655 val = IS_MF(bp) ? 0xF7 : 0x7; 7656 /* Enable DCBX attention for all but E1 */ 7657 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 7658 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 7659 7660 /* SCPAD_PARITY should NOT trigger close the gates */ 7661 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; 7662 REG_WR(bp, reg, 7663 REG_RD(bp, reg) & 7664 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); 7665 7666 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; 7667 REG_WR(bp, reg, 7668 REG_RD(bp, reg) & 7669 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); 7670 7671 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7672 7673 if (!CHIP_IS_E1x(bp)) { 7674 /* Bit-map indicating which L2 hdrs may appear after the 7675 * basic Ethernet header 7676 */ 7677 if (IS_MF_AFEX(bp)) 7678 REG_WR(bp, BP_PORT(bp) ? 7679 NIG_REG_P1_HDRS_AFTER_BASIC : 7680 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 7681 else 7682 REG_WR(bp, BP_PORT(bp) ? 7683 NIG_REG_P1_HDRS_AFTER_BASIC : 7684 NIG_REG_P0_HDRS_AFTER_BASIC, 7685 IS_MF_SD(bp) ? 7 : 6); 7686 7687 if (CHIP_IS_E3(bp)) 7688 REG_WR(bp, BP_PORT(bp) ? 7689 NIG_REG_LLH1_MF_MODE : 7690 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7691 } 7692 if (!CHIP_IS_E3(bp)) 7693 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 7694 7695 if (!CHIP_IS_E1(bp)) { 7696 /* 0x2 disable mf_ov, 0x1 enable */ 7697 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 7698 (IS_MF_SD(bp) ? 0x1 : 0x2)); 7699 7700 if (!CHIP_IS_E1x(bp)) { 7701 val = 0; 7702 switch (bp->mf_mode) { 7703 case MULTI_FUNCTION_SD: 7704 val = 1; 7705 break; 7706 case MULTI_FUNCTION_SI: 7707 case MULTI_FUNCTION_AFEX: 7708 val = 2; 7709 break; 7710 } 7711 7712 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 7713 NIG_REG_LLH0_CLS_TYPE), val); 7714 } 7715 { 7716 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 7717 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 7718 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 7719 } 7720 } 7721 7722 /* If SPIO5 is set to generate interrupts, enable it for this port */ 7723 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 7724 if (val & MISC_SPIO_SPIO5) { 7725 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 7726 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 7727 val = REG_RD(bp, reg_addr); 7728 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 7729 REG_WR(bp, reg_addr, val); 7730 } 7731 7732 if (CHIP_IS_E3B0(bp)) 7733 bp->flags |= PTP_SUPPORTED; 7734 7735 return 0; 7736 } 7737 7738 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 7739 { 7740 int reg; 7741 u32 wb_write[2]; 7742 7743 if (CHIP_IS_E1(bp)) 7744 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 7745 else 7746 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 7747 7748 wb_write[0] = ONCHIP_ADDR1(addr); 7749 wb_write[1] = ONCHIP_ADDR2(addr); 7750 REG_WR_DMAE(bp, reg, wb_write, 2); 7751 } 7752 7753 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) 7754 { 7755 u32 data, ctl, cnt = 100; 7756 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 7757 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 7758 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 7759 u32 sb_bit = 1 << (idu_sb_id%32); 7760 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 7761 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 7762 7763 /* Not supported in BC mode */ 7764 if (CHIP_INT_MODE_IS_BC(bp)) 7765 return; 7766 7767 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 7768 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 7769 IGU_REGULAR_CLEANUP_SET | 7770 IGU_REGULAR_BCLEANUP; 7771 7772 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 7773 func_encode << IGU_CTRL_REG_FID_SHIFT | 7774 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 7775 7776 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7777 data, igu_addr_data); 7778 REG_WR(bp, igu_addr_data, data); 7779 barrier(); 7780 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7781 ctl, igu_addr_ctl); 7782 REG_WR(bp, igu_addr_ctl, ctl); 7783 barrier(); 7784 7785 /* wait for clean up to finish */ 7786 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) 7787 msleep(20); 7788 7789 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 7790 DP(NETIF_MSG_HW, 7791 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", 7792 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 7793 } 7794 } 7795 7796 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 7797 { 7798 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 7799 } 7800 7801 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 7802 { 7803 u32 i, base = FUNC_ILT_BASE(func); 7804 for (i = base; i < base + ILT_PER_FUNC; i++) 7805 bnx2x_ilt_wr(bp, i, 0); 7806 } 7807 7808 static void bnx2x_init_searcher(struct bnx2x *bp) 7809 { 7810 int port = BP_PORT(bp); 7811 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 7812 /* T1 hash bits value determines the T1 number of entries */ 7813 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 7814 } 7815 7816 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) 7817 { 7818 int rc; 7819 struct bnx2x_func_state_params func_params = {NULL}; 7820 struct bnx2x_func_switch_update_params *switch_update_params = 7821 &func_params.params.switch_update; 7822 7823 /* Prepare parameters for function state transitions */ 7824 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7825 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 7826 7827 func_params.f_obj = &bp->func_obj; 7828 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 7829 7830 /* Function parameters */ 7831 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 7832 &switch_update_params->changes); 7833 if (suspend) 7834 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, 7835 &switch_update_params->changes); 7836 7837 rc = bnx2x_func_state_change(bp, &func_params); 7838 7839 return rc; 7840 } 7841 7842 static int bnx2x_reset_nic_mode(struct bnx2x *bp) 7843 { 7844 int rc, i, port = BP_PORT(bp); 7845 int vlan_en = 0, mac_en[NUM_MACS]; 7846 7847 /* Close input from network */ 7848 if (bp->mf_mode == SINGLE_FUNCTION) { 7849 bnx2x_set_rx_filter(&bp->link_params, 0); 7850 } else { 7851 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : 7852 NIG_REG_LLH0_FUNC_EN); 7853 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7854 NIG_REG_LLH0_FUNC_EN, 0); 7855 for (i = 0; i < NUM_MACS; i++) { 7856 mac_en[i] = REG_RD(bp, port ? 7857 (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7858 4 * i) : 7859 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 7860 4 * i)); 7861 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7862 4 * i) : 7863 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); 7864 } 7865 } 7866 7867 /* Close BMC to host */ 7868 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7869 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); 7870 7871 /* Suspend Tx switching to the PF. Completion of this ramrod 7872 * further guarantees that all the packets of that PF / child 7873 * VFs in BRB were processed by the Parser, so it is safe to 7874 * change the NIC_MODE register. 7875 */ 7876 rc = bnx2x_func_switch_update(bp, 1); 7877 if (rc) { 7878 BNX2X_ERR("Can't suspend tx-switching!\n"); 7879 return rc; 7880 } 7881 7882 /* Change NIC_MODE register */ 7883 REG_WR(bp, PRS_REG_NIC_MODE, 0); 7884 7885 /* Open input from network */ 7886 if (bp->mf_mode == SINGLE_FUNCTION) { 7887 bnx2x_set_rx_filter(&bp->link_params, 1); 7888 } else { 7889 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7890 NIG_REG_LLH0_FUNC_EN, vlan_en); 7891 for (i = 0; i < NUM_MACS; i++) { 7892 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7893 4 * i) : 7894 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 7895 mac_en[i]); 7896 } 7897 } 7898 7899 /* Enable BMC to host */ 7900 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7901 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); 7902 7903 /* Resume Tx switching to the PF */ 7904 rc = bnx2x_func_switch_update(bp, 0); 7905 if (rc) { 7906 BNX2X_ERR("Can't resume tx-switching!\n"); 7907 return rc; 7908 } 7909 7910 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 7911 return 0; 7912 } 7913 7914 int bnx2x_init_hw_func_cnic(struct bnx2x *bp) 7915 { 7916 int rc; 7917 7918 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); 7919 7920 if (CONFIGURE_NIC_MODE(bp)) { 7921 /* Configure searcher as part of function hw init */ 7922 bnx2x_init_searcher(bp); 7923 7924 /* Reset NIC mode */ 7925 rc = bnx2x_reset_nic_mode(bp); 7926 if (rc) 7927 BNX2X_ERR("Can't change NIC mode!\n"); 7928 return rc; 7929 } 7930 7931 return 0; 7932 } 7933 7934 /* previous driver DMAE transaction may have occurred when pre-boot stage ended 7935 * and boot began, or when kdump kernel was loaded. Either case would invalidate 7936 * the addresses of the transaction, resulting in was-error bit set in the pci 7937 * causing all hw-to-host pcie transactions to timeout. If this happened we want 7938 * to clear the interrupt which detected this from the pglueb and the was done 7939 * bit 7940 */ 7941 static void bnx2x_clean_pglue_errors(struct bnx2x *bp) 7942 { 7943 if (!CHIP_IS_E1x(bp)) 7944 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 7945 1 << BP_ABS_FUNC(bp)); 7946 } 7947 7948 static int bnx2x_init_hw_func(struct bnx2x *bp) 7949 { 7950 int port = BP_PORT(bp); 7951 int func = BP_FUNC(bp); 7952 int init_phase = PHASE_PF0 + func; 7953 struct bnx2x_ilt *ilt = BP_ILT(bp); 7954 u16 cdu_ilt_start; 7955 u32 addr, val; 7956 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 7957 int i, main_mem_width, rc; 7958 7959 DP(NETIF_MSG_HW, "starting func init func %d\n", func); 7960 7961 /* FLR cleanup - hmmm */ 7962 if (!CHIP_IS_E1x(bp)) { 7963 rc = bnx2x_pf_flr_clnup(bp); 7964 if (rc) { 7965 bnx2x_fw_dump(bp); 7966 return rc; 7967 } 7968 } 7969 7970 /* set MSI reconfigure capability */ 7971 if (bp->common.int_block == INT_BLOCK_HC) { 7972 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 7973 val = REG_RD(bp, addr); 7974 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 7975 REG_WR(bp, addr, val); 7976 } 7977 7978 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7979 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7980 7981 ilt = BP_ILT(bp); 7982 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7983 7984 if (IS_SRIOV(bp)) 7985 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; 7986 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); 7987 7988 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes 7989 * those of the VFs, so start line should be reset 7990 */ 7991 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7992 for (i = 0; i < L2_ILT_LINES(bp); i++) { 7993 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; 7994 ilt->lines[cdu_ilt_start + i].page_mapping = 7995 bp->context[i].cxt_mapping; 7996 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; 7997 } 7998 7999 bnx2x_ilt_init_op(bp, INITOP_SET); 8000 8001 if (!CONFIGURE_NIC_MODE(bp)) { 8002 bnx2x_init_searcher(bp); 8003 REG_WR(bp, PRS_REG_NIC_MODE, 0); 8004 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 8005 } else { 8006 /* Set NIC mode */ 8007 REG_WR(bp, PRS_REG_NIC_MODE, 1); 8008 DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); 8009 } 8010 8011 if (!CHIP_IS_E1x(bp)) { 8012 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 8013 8014 /* Turn on a single ISR mode in IGU if driver is going to use 8015 * INT#x or MSI 8016 */ 8017 if (!(bp->flags & USING_MSIX_FLAG)) 8018 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 8019 /* 8020 * Timers workaround bug: function init part. 8021 * Need to wait 20msec after initializing ILT, 8022 * needed to make sure there are no requests in 8023 * one of the PXP internal queues with "old" ILT addresses 8024 */ 8025 msleep(20); 8026 /* 8027 * Master enable - Due to WB DMAE writes performed before this 8028 * register is re-initialized as part of the regular function 8029 * init 8030 */ 8031 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 8032 /* Enable the function in IGU */ 8033 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 8034 } 8035 8036 bp->dmae_ready = 1; 8037 8038 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 8039 8040 bnx2x_clean_pglue_errors(bp); 8041 8042 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 8043 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 8044 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 8045 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 8046 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 8047 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 8048 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 8049 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 8050 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 8051 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 8052 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 8053 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 8054 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 8055 8056 if (!CHIP_IS_E1x(bp)) 8057 REG_WR(bp, QM_REG_PF_EN, 1); 8058 8059 if (!CHIP_IS_E1x(bp)) { 8060 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8061 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8062 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8063 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8064 } 8065 bnx2x_init_block(bp, BLOCK_QM, init_phase); 8066 8067 bnx2x_init_block(bp, BLOCK_TM, init_phase); 8068 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 8069 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ 8070 8071 bnx2x_iov_init_dq(bp); 8072 8073 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 8074 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 8075 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 8076 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 8077 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 8078 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 8079 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 8080 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 8081 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 8082 if (!CHIP_IS_E1x(bp)) 8083 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 8084 8085 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 8086 8087 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 8088 8089 if (!CHIP_IS_E1x(bp)) 8090 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 8091 8092 if (IS_MF(bp)) { 8093 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { 8094 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); 8095 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, 8096 bp->mf_ov); 8097 } 8098 } 8099 8100 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 8101 8102 /* HC init per function */ 8103 if (bp->common.int_block == INT_BLOCK_HC) { 8104 if (CHIP_IS_E1H(bp)) { 8105 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8106 8107 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 8108 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 8109 } 8110 bnx2x_init_block(bp, BLOCK_HC, init_phase); 8111 8112 } else { 8113 int num_segs, sb_idx, prod_offset; 8114 8115 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8116 8117 if (!CHIP_IS_E1x(bp)) { 8118 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 8119 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 8120 } 8121 8122 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 8123 8124 if (!CHIP_IS_E1x(bp)) { 8125 int dsb_idx = 0; 8126 /** 8127 * Producer memory: 8128 * E2 mode: address 0-135 match to the mapping memory; 8129 * 136 - PF0 default prod; 137 - PF1 default prod; 8130 * 138 - PF2 default prod; 139 - PF3 default prod; 8131 * 140 - PF0 attn prod; 141 - PF1 attn prod; 8132 * 142 - PF2 attn prod; 143 - PF3 attn prod; 8133 * 144-147 reserved. 8134 * 8135 * E1.5 mode - In backward compatible mode; 8136 * for non default SB; each even line in the memory 8137 * holds the U producer and each odd line hold 8138 * the C producer. The first 128 producers are for 8139 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 8140 * producers are for the DSB for each PF. 8141 * Each PF has five segments: (the order inside each 8142 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 8143 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 8144 * 144-147 attn prods; 8145 */ 8146 /* non-default-status-blocks */ 8147 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 8148 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 8149 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 8150 prod_offset = (bp->igu_base_sb + sb_idx) * 8151 num_segs; 8152 8153 for (i = 0; i < num_segs; i++) { 8154 addr = IGU_REG_PROD_CONS_MEMORY + 8155 (prod_offset + i) * 4; 8156 REG_WR(bp, addr, 0); 8157 } 8158 /* send consumer update with value 0 */ 8159 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 8160 USTORM_ID, 0, IGU_INT_NOP, 1); 8161 bnx2x_igu_clear_sb(bp, 8162 bp->igu_base_sb + sb_idx); 8163 } 8164 8165 /* default-status-blocks */ 8166 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 8167 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 8168 8169 if (CHIP_MODE_IS_4_PORT(bp)) 8170 dsb_idx = BP_FUNC(bp); 8171 else 8172 dsb_idx = BP_VN(bp); 8173 8174 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 8175 IGU_BC_BASE_DSB_PROD + dsb_idx : 8176 IGU_NORM_BASE_DSB_PROD + dsb_idx); 8177 8178 /* 8179 * igu prods come in chunks of E1HVN_MAX (4) - 8180 * does not matters what is the current chip mode 8181 */ 8182 for (i = 0; i < (num_segs * E1HVN_MAX); 8183 i += E1HVN_MAX) { 8184 addr = IGU_REG_PROD_CONS_MEMORY + 8185 (prod_offset + i)*4; 8186 REG_WR(bp, addr, 0); 8187 } 8188 /* send consumer update with 0 */ 8189 if (CHIP_INT_MODE_IS_BC(bp)) { 8190 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8191 USTORM_ID, 0, IGU_INT_NOP, 1); 8192 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8193 CSTORM_ID, 0, IGU_INT_NOP, 1); 8194 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8195 XSTORM_ID, 0, IGU_INT_NOP, 1); 8196 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8197 TSTORM_ID, 0, IGU_INT_NOP, 1); 8198 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8199 ATTENTION_ID, 0, IGU_INT_NOP, 1); 8200 } else { 8201 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8202 USTORM_ID, 0, IGU_INT_NOP, 1); 8203 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8204 ATTENTION_ID, 0, IGU_INT_NOP, 1); 8205 } 8206 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 8207 8208 /* !!! These should become driver const once 8209 rf-tool supports split-68 const */ 8210 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 8211 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 8212 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 8213 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 8214 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 8215 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 8216 } 8217 } 8218 8219 /* Reset PCIE errors for debug */ 8220 REG_WR(bp, 0x2114, 0xffffffff); 8221 REG_WR(bp, 0x2120, 0xffffffff); 8222 8223 if (CHIP_IS_E1x(bp)) { 8224 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 8225 main_mem_base = HC_REG_MAIN_MEMORY + 8226 BP_PORT(bp) * (main_mem_size * 4); 8227 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 8228 main_mem_width = 8; 8229 8230 val = REG_RD(bp, main_mem_prty_clr); 8231 if (val) 8232 DP(NETIF_MSG_HW, 8233 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", 8234 val); 8235 8236 /* Clear "false" parity errors in MSI-X table */ 8237 for (i = main_mem_base; 8238 i < main_mem_base + main_mem_size * 4; 8239 i += main_mem_width) { 8240 bnx2x_read_dmae(bp, i, main_mem_width / 4); 8241 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 8242 i, main_mem_width / 4); 8243 } 8244 /* Clear HC parity attention */ 8245 REG_RD(bp, main_mem_prty_clr); 8246 } 8247 8248 #ifdef BNX2X_STOP_ON_ERROR 8249 /* Enable STORMs SP logging */ 8250 REG_WR8(bp, BAR_USTRORM_INTMEM + 8251 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8252 REG_WR8(bp, BAR_TSTRORM_INTMEM + 8253 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8254 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8255 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8256 REG_WR8(bp, BAR_XSTRORM_INTMEM + 8257 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8258 #endif 8259 8260 bnx2x_phy_probe(&bp->link_params); 8261 8262 return 0; 8263 } 8264 8265 void bnx2x_free_mem_cnic(struct bnx2x *bp) 8266 { 8267 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); 8268 8269 if (!CHIP_IS_E1x(bp)) 8270 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 8271 sizeof(struct host_hc_status_block_e2)); 8272 else 8273 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 8274 sizeof(struct host_hc_status_block_e1x)); 8275 8276 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 8277 } 8278 8279 void bnx2x_free_mem(struct bnx2x *bp) 8280 { 8281 int i; 8282 8283 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 8284 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 8285 8286 if (IS_VF(bp)) 8287 return; 8288 8289 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 8290 sizeof(struct host_sp_status_block)); 8291 8292 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 8293 sizeof(struct bnx2x_slowpath)); 8294 8295 for (i = 0; i < L2_ILT_LINES(bp); i++) 8296 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, 8297 bp->context[i].size); 8298 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 8299 8300 BNX2X_FREE(bp->ilt->lines); 8301 8302 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 8303 8304 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 8305 BCM_PAGE_SIZE * NUM_EQ_PAGES); 8306 8307 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 8308 8309 bnx2x_iov_free_mem(bp); 8310 } 8311 8312 int bnx2x_alloc_mem_cnic(struct bnx2x *bp) 8313 { 8314 if (!CHIP_IS_E1x(bp)) { 8315 /* size = the status block + ramrod buffers */ 8316 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, 8317 sizeof(struct host_hc_status_block_e2)); 8318 if (!bp->cnic_sb.e2_sb) 8319 goto alloc_mem_err; 8320 } else { 8321 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, 8322 sizeof(struct host_hc_status_block_e1x)); 8323 if (!bp->cnic_sb.e1x_sb) 8324 goto alloc_mem_err; 8325 } 8326 8327 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { 8328 /* allocate searcher T2 table, as it wasn't allocated before */ 8329 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); 8330 if (!bp->t2) 8331 goto alloc_mem_err; 8332 } 8333 8334 /* write address to which L5 should insert its values */ 8335 bp->cnic_eth_dev.addr_drv_info_to_mcp = 8336 &bp->slowpath->drv_info_to_mcp; 8337 8338 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) 8339 goto alloc_mem_err; 8340 8341 return 0; 8342 8343 alloc_mem_err: 8344 bnx2x_free_mem_cnic(bp); 8345 BNX2X_ERR("Can't allocate memory\n"); 8346 return -ENOMEM; 8347 } 8348 8349 int bnx2x_alloc_mem(struct bnx2x *bp) 8350 { 8351 int i, allocated, context_size; 8352 8353 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { 8354 /* allocate searcher T2 table */ 8355 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); 8356 if (!bp->t2) 8357 goto alloc_mem_err; 8358 } 8359 8360 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, 8361 sizeof(struct host_sp_status_block)); 8362 if (!bp->def_status_blk) 8363 goto alloc_mem_err; 8364 8365 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, 8366 sizeof(struct bnx2x_slowpath)); 8367 if (!bp->slowpath) 8368 goto alloc_mem_err; 8369 8370 /* Allocate memory for CDU context: 8371 * This memory is allocated separately and not in the generic ILT 8372 * functions because CDU differs in few aspects: 8373 * 1. There are multiple entities allocating memory for context - 8374 * 'regular' driver, CNIC and SRIOV driver. Each separately controls 8375 * its own ILT lines. 8376 * 2. Since CDU page-size is not a single 4KB page (which is the case 8377 * for the other ILT clients), to be efficient we want to support 8378 * allocation of sub-page-size in the last entry. 8379 * 3. Context pointers are used by the driver to pass to FW / update 8380 * the context (for the other ILT clients the pointers are used just to 8381 * free the memory during unload). 8382 */ 8383 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 8384 8385 for (i = 0, allocated = 0; allocated < context_size; i++) { 8386 bp->context[i].size = min(CDU_ILT_PAGE_SZ, 8387 (context_size - allocated)); 8388 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, 8389 bp->context[i].size); 8390 if (!bp->context[i].vcxt) 8391 goto alloc_mem_err; 8392 allocated += bp->context[i].size; 8393 } 8394 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), 8395 GFP_KERNEL); 8396 if (!bp->ilt->lines) 8397 goto alloc_mem_err; 8398 8399 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 8400 goto alloc_mem_err; 8401 8402 if (bnx2x_iov_alloc_mem(bp)) 8403 goto alloc_mem_err; 8404 8405 /* Slow path ring */ 8406 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); 8407 if (!bp->spq) 8408 goto alloc_mem_err; 8409 8410 /* EQ */ 8411 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, 8412 BCM_PAGE_SIZE * NUM_EQ_PAGES); 8413 if (!bp->eq_ring) 8414 goto alloc_mem_err; 8415 8416 return 0; 8417 8418 alloc_mem_err: 8419 bnx2x_free_mem(bp); 8420 BNX2X_ERR("Can't allocate memory\n"); 8421 return -ENOMEM; 8422 } 8423 8424 /* 8425 * Init service functions 8426 */ 8427 8428 int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac, 8429 struct bnx2x_vlan_mac_obj *obj, bool set, 8430 int mac_type, unsigned long *ramrod_flags) 8431 { 8432 int rc; 8433 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 8434 8435 memset(&ramrod_param, 0, sizeof(ramrod_param)); 8436 8437 /* Fill general parameters */ 8438 ramrod_param.vlan_mac_obj = obj; 8439 ramrod_param.ramrod_flags = *ramrod_flags; 8440 8441 /* Fill a user request section if needed */ 8442 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 8443 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 8444 8445 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 8446 8447 /* Set the command: ADD or DEL */ 8448 if (set) 8449 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 8450 else 8451 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 8452 } 8453 8454 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 8455 8456 if (rc == -EEXIST) { 8457 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 8458 /* do not treat adding same MAC as error */ 8459 rc = 0; 8460 } else if (rc < 0) 8461 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 8462 8463 return rc; 8464 } 8465 8466 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, 8467 struct bnx2x_vlan_mac_obj *obj, bool set, 8468 unsigned long *ramrod_flags) 8469 { 8470 int rc; 8471 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 8472 8473 memset(&ramrod_param, 0, sizeof(ramrod_param)); 8474 8475 /* Fill general parameters */ 8476 ramrod_param.vlan_mac_obj = obj; 8477 ramrod_param.ramrod_flags = *ramrod_flags; 8478 8479 /* Fill a user request section if needed */ 8480 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 8481 ramrod_param.user_req.u.vlan.vlan = vlan; 8482 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags); 8483 /* Set the command: ADD or DEL */ 8484 if (set) 8485 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 8486 else 8487 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 8488 } 8489 8490 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 8491 8492 if (rc == -EEXIST) { 8493 /* Do not treat adding same vlan as error. */ 8494 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 8495 rc = 0; 8496 } else if (rc < 0) { 8497 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del")); 8498 } 8499 8500 return rc; 8501 } 8502 8503 void bnx2x_clear_vlan_info(struct bnx2x *bp) 8504 { 8505 struct bnx2x_vlan_entry *vlan; 8506 8507 /* Mark that hw forgot all entries */ 8508 list_for_each_entry(vlan, &bp->vlan_reg, link) 8509 vlan->hw = false; 8510 8511 bp->vlan_cnt = 0; 8512 } 8513 8514 static int bnx2x_del_all_vlans(struct bnx2x *bp) 8515 { 8516 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; 8517 unsigned long ramrod_flags = 0, vlan_flags = 0; 8518 int rc; 8519 8520 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8521 __set_bit(BNX2X_VLAN, &vlan_flags); 8522 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags); 8523 if (rc) 8524 return rc; 8525 8526 bnx2x_clear_vlan_info(bp); 8527 8528 return 0; 8529 } 8530 8531 int bnx2x_del_all_macs(struct bnx2x *bp, 8532 struct bnx2x_vlan_mac_obj *mac_obj, 8533 int mac_type, bool wait_for_comp) 8534 { 8535 int rc; 8536 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 8537 8538 /* Wait for completion of requested */ 8539 if (wait_for_comp) 8540 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8541 8542 /* Set the mac type of addresses we want to clear */ 8543 __set_bit(mac_type, &vlan_mac_flags); 8544 8545 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 8546 if (rc < 0) 8547 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 8548 8549 return rc; 8550 } 8551 8552 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 8553 { 8554 if (IS_PF(bp)) { 8555 unsigned long ramrod_flags = 0; 8556 8557 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 8558 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8559 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, 8560 &bp->sp_objs->mac_obj, set, 8561 BNX2X_ETH_MAC, &ramrod_flags); 8562 } else { /* vf */ 8563 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, 8564 bp->fp->index, set); 8565 } 8566 } 8567 8568 int bnx2x_setup_leading(struct bnx2x *bp) 8569 { 8570 if (IS_PF(bp)) 8571 return bnx2x_setup_queue(bp, &bp->fp[0], true); 8572 else /* VF */ 8573 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); 8574 } 8575 8576 /** 8577 * bnx2x_set_int_mode - configure interrupt mode 8578 * 8579 * @bp: driver handle 8580 * 8581 * In case of MSI-X it will also try to enable MSI-X. 8582 */ 8583 int bnx2x_set_int_mode(struct bnx2x *bp) 8584 { 8585 int rc = 0; 8586 8587 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { 8588 BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); 8589 return -EINVAL; 8590 } 8591 8592 switch (int_mode) { 8593 case BNX2X_INT_MODE_MSIX: 8594 /* attempt to enable msix */ 8595 rc = bnx2x_enable_msix(bp); 8596 8597 /* msix attained */ 8598 if (!rc) 8599 return 0; 8600 8601 /* vfs use only msix */ 8602 if (rc && IS_VF(bp)) 8603 return rc; 8604 8605 /* failed to enable multiple MSI-X */ 8606 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", 8607 bp->num_queues, 8608 1 + bp->num_cnic_queues); 8609 8610 fallthrough; 8611 case BNX2X_INT_MODE_MSI: 8612 bnx2x_enable_msi(bp); 8613 8614 fallthrough; 8615 case BNX2X_INT_MODE_INTX: 8616 bp->num_ethernet_queues = 1; 8617 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 8618 BNX2X_DEV_INFO("set number of queues to 1\n"); 8619 break; 8620 default: 8621 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); 8622 return -EINVAL; 8623 } 8624 return 0; 8625 } 8626 8627 /* must be called prior to any HW initializations */ 8628 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 8629 { 8630 if (IS_SRIOV(bp)) 8631 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; 8632 return L2_ILT_LINES(bp); 8633 } 8634 8635 void bnx2x_ilt_set_info(struct bnx2x *bp) 8636 { 8637 struct ilt_client_info *ilt_client; 8638 struct bnx2x_ilt *ilt = BP_ILT(bp); 8639 u16 line = 0; 8640 8641 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 8642 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 8643 8644 /* CDU */ 8645 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 8646 ilt_client->client_num = ILT_CLIENT_CDU; 8647 ilt_client->page_size = CDU_ILT_PAGE_SZ; 8648 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 8649 ilt_client->start = line; 8650 line += bnx2x_cid_ilt_lines(bp); 8651 8652 if (CNIC_SUPPORT(bp)) 8653 line += CNIC_ILT_LINES; 8654 ilt_client->end = line - 1; 8655 8656 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8657 ilt_client->start, 8658 ilt_client->end, 8659 ilt_client->page_size, 8660 ilt_client->flags, 8661 ilog2(ilt_client->page_size >> 12)); 8662 8663 /* QM */ 8664 if (QM_INIT(bp->qm_cid_count)) { 8665 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 8666 ilt_client->client_num = ILT_CLIENT_QM; 8667 ilt_client->page_size = QM_ILT_PAGE_SZ; 8668 ilt_client->flags = 0; 8669 ilt_client->start = line; 8670 8671 /* 4 bytes for each cid */ 8672 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 8673 QM_ILT_PAGE_SZ); 8674 8675 ilt_client->end = line - 1; 8676 8677 DP(NETIF_MSG_IFUP, 8678 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8679 ilt_client->start, 8680 ilt_client->end, 8681 ilt_client->page_size, 8682 ilt_client->flags, 8683 ilog2(ilt_client->page_size >> 12)); 8684 } 8685 8686 if (CNIC_SUPPORT(bp)) { 8687 /* SRC */ 8688 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 8689 ilt_client->client_num = ILT_CLIENT_SRC; 8690 ilt_client->page_size = SRC_ILT_PAGE_SZ; 8691 ilt_client->flags = 0; 8692 ilt_client->start = line; 8693 line += SRC_ILT_LINES; 8694 ilt_client->end = line - 1; 8695 8696 DP(NETIF_MSG_IFUP, 8697 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8698 ilt_client->start, 8699 ilt_client->end, 8700 ilt_client->page_size, 8701 ilt_client->flags, 8702 ilog2(ilt_client->page_size >> 12)); 8703 8704 /* TM */ 8705 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 8706 ilt_client->client_num = ILT_CLIENT_TM; 8707 ilt_client->page_size = TM_ILT_PAGE_SZ; 8708 ilt_client->flags = 0; 8709 ilt_client->start = line; 8710 line += TM_ILT_LINES; 8711 ilt_client->end = line - 1; 8712 8713 DP(NETIF_MSG_IFUP, 8714 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8715 ilt_client->start, 8716 ilt_client->end, 8717 ilt_client->page_size, 8718 ilt_client->flags, 8719 ilog2(ilt_client->page_size >> 12)); 8720 } 8721 8722 BUG_ON(line > ILT_MAX_LINES); 8723 } 8724 8725 /** 8726 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 8727 * 8728 * @bp: driver handle 8729 * @fp: pointer to fastpath 8730 * @init_params: pointer to parameters structure 8731 * 8732 * parameters configured: 8733 * - HC configuration 8734 * - Queue's CDU context 8735 */ 8736 static void bnx2x_pf_q_prep_init(struct bnx2x *bp, 8737 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 8738 { 8739 u8 cos; 8740 int cxt_index, cxt_offset; 8741 8742 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 8743 if (!IS_FCOE_FP(fp)) { 8744 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 8745 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 8746 8747 /* If HC is supported, enable host coalescing in the transition 8748 * to INIT state. 8749 */ 8750 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 8751 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 8752 8753 /* HC rate */ 8754 init_params->rx.hc_rate = bp->rx_ticks ? 8755 (1000000 / bp->rx_ticks) : 0; 8756 init_params->tx.hc_rate = bp->tx_ticks ? 8757 (1000000 / bp->tx_ticks) : 0; 8758 8759 /* FW SB ID */ 8760 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 8761 fp->fw_sb_id; 8762 8763 /* 8764 * CQ index among the SB indices: FCoE clients uses the default 8765 * SB, therefore it's different. 8766 */ 8767 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 8768 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 8769 } 8770 8771 /* set maximum number of COSs supported by this queue */ 8772 init_params->max_cos = fp->max_cos; 8773 8774 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", 8775 fp->index, init_params->max_cos); 8776 8777 /* set the context pointers queue object */ 8778 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 8779 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; 8780 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * 8781 ILT_PAGE_CIDS); 8782 init_params->cxts[cos] = 8783 &bp->context[cxt_index].vcxt[cxt_offset].eth; 8784 } 8785 } 8786 8787 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8788 struct bnx2x_queue_state_params *q_params, 8789 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 8790 int tx_index, bool leading) 8791 { 8792 memset(tx_only_params, 0, sizeof(*tx_only_params)); 8793 8794 /* Set the command */ 8795 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 8796 8797 /* Set tx-only QUEUE flags: don't zero statistics */ 8798 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 8799 8800 /* choose the index of the cid to send the slow path on */ 8801 tx_only_params->cid_index = tx_index; 8802 8803 /* Set general TX_ONLY_SETUP parameters */ 8804 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 8805 8806 /* Set Tx TX_ONLY_SETUP parameters */ 8807 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 8808 8809 DP(NETIF_MSG_IFUP, 8810 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", 8811 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 8812 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 8813 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 8814 8815 /* send the ramrod */ 8816 return bnx2x_queue_state_change(bp, q_params); 8817 } 8818 8819 /** 8820 * bnx2x_setup_queue - setup queue 8821 * 8822 * @bp: driver handle 8823 * @fp: pointer to fastpath 8824 * @leading: is leading 8825 * 8826 * This function performs 2 steps in a Queue state machine 8827 * actually: 1) RESET->INIT 2) INIT->SETUP 8828 */ 8829 8830 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8831 bool leading) 8832 { 8833 struct bnx2x_queue_state_params q_params = {NULL}; 8834 struct bnx2x_queue_setup_params *setup_params = 8835 &q_params.params.setup; 8836 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 8837 &q_params.params.tx_only; 8838 int rc; 8839 u8 tx_index; 8840 8841 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); 8842 8843 /* reset IGU state skip FCoE L2 queue */ 8844 if (!IS_FCOE_FP(fp)) 8845 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 8846 IGU_INT_ENABLE, 0); 8847 8848 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8849 /* We want to wait for completion in this context */ 8850 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8851 8852 /* Prepare the INIT parameters */ 8853 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 8854 8855 /* Set the command */ 8856 q_params.cmd = BNX2X_Q_CMD_INIT; 8857 8858 /* Change the state to INIT */ 8859 rc = bnx2x_queue_state_change(bp, &q_params); 8860 if (rc) { 8861 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 8862 return rc; 8863 } 8864 8865 DP(NETIF_MSG_IFUP, "init complete\n"); 8866 8867 /* Now move the Queue to the SETUP state... */ 8868 memset(setup_params, 0, sizeof(*setup_params)); 8869 8870 /* Set QUEUE flags */ 8871 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 8872 8873 /* Set general SETUP parameters */ 8874 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 8875 FIRST_TX_COS_INDEX); 8876 8877 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 8878 &setup_params->rxq_params); 8879 8880 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 8881 FIRST_TX_COS_INDEX); 8882 8883 /* Set the command */ 8884 q_params.cmd = BNX2X_Q_CMD_SETUP; 8885 8886 if (IS_FCOE_FP(fp)) 8887 bp->fcoe_init = true; 8888 8889 /* Change the state to SETUP */ 8890 rc = bnx2x_queue_state_change(bp, &q_params); 8891 if (rc) { 8892 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 8893 return rc; 8894 } 8895 8896 /* loop through the relevant tx-only indices */ 8897 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8898 tx_index < fp->max_cos; 8899 tx_index++) { 8900 8901 /* prepare and send tx-only ramrod*/ 8902 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 8903 tx_only_params, tx_index, leading); 8904 if (rc) { 8905 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 8906 fp->index, tx_index); 8907 return rc; 8908 } 8909 } 8910 8911 return rc; 8912 } 8913 8914 static int bnx2x_stop_queue(struct bnx2x *bp, int index) 8915 { 8916 struct bnx2x_fastpath *fp = &bp->fp[index]; 8917 struct bnx2x_fp_txdata *txdata; 8918 struct bnx2x_queue_state_params q_params = {NULL}; 8919 int rc, tx_index; 8920 8921 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); 8922 8923 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8924 /* We want to wait for completion in this context */ 8925 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8926 8927 /* close tx-only connections */ 8928 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8929 tx_index < fp->max_cos; 8930 tx_index++){ 8931 8932 /* ascertain this is a normal queue*/ 8933 txdata = fp->txdata_ptr[tx_index]; 8934 8935 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", 8936 txdata->txq_index); 8937 8938 /* send halt terminate on tx-only connection */ 8939 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8940 memset(&q_params.params.terminate, 0, 8941 sizeof(q_params.params.terminate)); 8942 q_params.params.terminate.cid_index = tx_index; 8943 8944 rc = bnx2x_queue_state_change(bp, &q_params); 8945 if (rc) 8946 return rc; 8947 8948 /* send halt terminate on tx-only connection */ 8949 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8950 memset(&q_params.params.cfc_del, 0, 8951 sizeof(q_params.params.cfc_del)); 8952 q_params.params.cfc_del.cid_index = tx_index; 8953 rc = bnx2x_queue_state_change(bp, &q_params); 8954 if (rc) 8955 return rc; 8956 } 8957 /* Stop the primary connection: */ 8958 /* ...halt the connection */ 8959 q_params.cmd = BNX2X_Q_CMD_HALT; 8960 rc = bnx2x_queue_state_change(bp, &q_params); 8961 if (rc) 8962 return rc; 8963 8964 /* ...terminate the connection */ 8965 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8966 memset(&q_params.params.terminate, 0, 8967 sizeof(q_params.params.terminate)); 8968 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 8969 rc = bnx2x_queue_state_change(bp, &q_params); 8970 if (rc) 8971 return rc; 8972 /* ...delete cfc entry */ 8973 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8974 memset(&q_params.params.cfc_del, 0, 8975 sizeof(q_params.params.cfc_del)); 8976 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 8977 return bnx2x_queue_state_change(bp, &q_params); 8978 } 8979 8980 static void bnx2x_reset_func(struct bnx2x *bp) 8981 { 8982 int port = BP_PORT(bp); 8983 int func = BP_FUNC(bp); 8984 int i; 8985 8986 /* Disable the function in the FW */ 8987 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 8988 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 8989 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 8990 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 8991 8992 /* FP SBs */ 8993 for_each_eth_queue(bp, i) { 8994 struct bnx2x_fastpath *fp = &bp->fp[i]; 8995 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8996 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 8997 SB_DISABLED); 8998 } 8999 9000 if (CNIC_LOADED(bp)) 9001 /* CNIC SB */ 9002 REG_WR8(bp, BAR_CSTRORM_INTMEM + 9003 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET 9004 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); 9005 9006 /* SP SB */ 9007 REG_WR8(bp, BAR_CSTRORM_INTMEM + 9008 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 9009 SB_DISABLED); 9010 9011 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 9012 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 9013 0); 9014 9015 /* Configure IGU */ 9016 if (bp->common.int_block == INT_BLOCK_HC) { 9017 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 9018 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 9019 } else { 9020 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 9021 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 9022 } 9023 9024 if (CNIC_LOADED(bp)) { 9025 /* Disable Timer scan */ 9026 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 9027 /* 9028 * Wait for at least 10ms and up to 2 second for the timers 9029 * scan to complete 9030 */ 9031 for (i = 0; i < 200; i++) { 9032 usleep_range(10000, 20000); 9033 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 9034 break; 9035 } 9036 } 9037 /* Clear ILT */ 9038 bnx2x_clear_func_ilt(bp, func); 9039 9040 /* Timers workaround bug for E2: if this is vnic-3, 9041 * we need to set the entire ilt range for this timers. 9042 */ 9043 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 9044 struct ilt_client_info ilt_cli; 9045 /* use dummy TM client */ 9046 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 9047 ilt_cli.start = 0; 9048 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 9049 ilt_cli.client_num = ILT_CLIENT_TM; 9050 9051 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 9052 } 9053 9054 /* this assumes that reset_port() called before reset_func()*/ 9055 if (!CHIP_IS_E1x(bp)) 9056 bnx2x_pf_disable(bp); 9057 9058 bp->dmae_ready = 0; 9059 } 9060 9061 static void bnx2x_reset_port(struct bnx2x *bp) 9062 { 9063 int port = BP_PORT(bp); 9064 u32 val; 9065 9066 /* Reset physical Link */ 9067 bnx2x__link_reset(bp); 9068 9069 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 9070 9071 /* Do not rcv packets to BRB */ 9072 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 9073 /* Do not direct rcv packets that are not for MCP to the BRB */ 9074 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 9075 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 9076 9077 /* Configure AEU */ 9078 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 9079 9080 msleep(100); 9081 /* Check for BRB port occupancy */ 9082 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 9083 if (val) 9084 DP(NETIF_MSG_IFDOWN, 9085 "BRB1 is not empty %d blocks are occupied\n", val); 9086 9087 /* TODO: Close Doorbell port? */ 9088 } 9089 9090 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 9091 { 9092 struct bnx2x_func_state_params func_params = {NULL}; 9093 9094 /* Prepare parameters for function state transitions */ 9095 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 9096 9097 func_params.f_obj = &bp->func_obj; 9098 func_params.cmd = BNX2X_F_CMD_HW_RESET; 9099 9100 func_params.params.hw_init.load_phase = load_code; 9101 9102 return bnx2x_func_state_change(bp, &func_params); 9103 } 9104 9105 static int bnx2x_func_stop(struct bnx2x *bp) 9106 { 9107 struct bnx2x_func_state_params func_params = {NULL}; 9108 int rc; 9109 9110 /* Prepare parameters for function state transitions */ 9111 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 9112 func_params.f_obj = &bp->func_obj; 9113 func_params.cmd = BNX2X_F_CMD_STOP; 9114 9115 /* 9116 * Try to stop the function the 'good way'. If fails (in case 9117 * of a parity error during bnx2x_chip_cleanup()) and we are 9118 * not in a debug mode, perform a state transaction in order to 9119 * enable further HW_RESET transaction. 9120 */ 9121 rc = bnx2x_func_state_change(bp, &func_params); 9122 if (rc) { 9123 #ifdef BNX2X_STOP_ON_ERROR 9124 return rc; 9125 #else 9126 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); 9127 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 9128 return bnx2x_func_state_change(bp, &func_params); 9129 #endif 9130 } 9131 9132 return 0; 9133 } 9134 9135 /** 9136 * bnx2x_send_unload_req - request unload mode from the MCP. 9137 * 9138 * @bp: driver handle 9139 * @unload_mode: requested function's unload mode 9140 * 9141 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 9142 */ 9143 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 9144 { 9145 u32 reset_code = 0; 9146 int port = BP_PORT(bp); 9147 9148 /* Select the UNLOAD request mode */ 9149 if (unload_mode == UNLOAD_NORMAL) 9150 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 9151 9152 else if (bp->flags & NO_WOL_FLAG) 9153 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 9154 9155 else if (bp->wol) { 9156 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 9157 const u8 *mac_addr = bp->dev->dev_addr; 9158 struct pci_dev *pdev = bp->pdev; 9159 u32 val; 9160 u16 pmc; 9161 9162 /* The mac address is written to entries 1-4 to 9163 * preserve entry 0 which is used by the PMF 9164 */ 9165 u8 entry = (BP_VN(bp) + 1)*8; 9166 9167 val = (mac_addr[0] << 8) | mac_addr[1]; 9168 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 9169 9170 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 9171 (mac_addr[4] << 8) | mac_addr[5]; 9172 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 9173 9174 /* Enable the PME and clear the status */ 9175 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); 9176 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 9177 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); 9178 9179 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 9180 9181 } else 9182 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 9183 9184 /* Send the request to the MCP */ 9185 if (!BP_NOMCP(bp)) 9186 reset_code = bnx2x_fw_command(bp, reset_code, 0); 9187 else { 9188 int path = BP_PATH(bp); 9189 9190 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", 9191 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], 9192 bnx2x_load_count[path][2]); 9193 bnx2x_load_count[path][0]--; 9194 bnx2x_load_count[path][1 + port]--; 9195 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", 9196 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], 9197 bnx2x_load_count[path][2]); 9198 if (bnx2x_load_count[path][0] == 0) 9199 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 9200 else if (bnx2x_load_count[path][1 + port] == 0) 9201 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 9202 else 9203 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 9204 } 9205 9206 return reset_code; 9207 } 9208 9209 /** 9210 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 9211 * 9212 * @bp: driver handle 9213 * @keep_link: true iff link should be kept up 9214 */ 9215 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) 9216 { 9217 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 9218 9219 /* Report UNLOAD_DONE to MCP */ 9220 if (!BP_NOMCP(bp)) 9221 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 9222 } 9223 9224 static int bnx2x_func_wait_started(struct bnx2x *bp) 9225 { 9226 int tout = 50; 9227 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 9228 9229 if (!bp->port.pmf) 9230 return 0; 9231 9232 /* 9233 * (assumption: No Attention from MCP at this stage) 9234 * PMF probably in the middle of TX disable/enable transaction 9235 * 1. Sync IRS for default SB 9236 * 2. Sync SP queue - this guarantees us that attention handling started 9237 * 3. Wait, that TX disable/enable transaction completes 9238 * 9239 * 1+2 guarantee that if DCBx attention was scheduled it already changed 9240 * pending bit of transaction from STARTED-->TX_STOPPED, if we already 9241 * received completion for the transaction the state is TX_STOPPED. 9242 * State will return to STARTED after completion of TX_STOPPED-->STARTED 9243 * transaction. 9244 */ 9245 9246 /* make sure default SB ISR is done */ 9247 if (msix) 9248 synchronize_irq(bp->msix_table[0].vector); 9249 else 9250 synchronize_irq(bp->pdev->irq); 9251 9252 flush_workqueue(bnx2x_wq); 9253 flush_workqueue(bnx2x_iov_wq); 9254 9255 while (bnx2x_func_get_state(bp, &bp->func_obj) != 9256 BNX2X_F_STATE_STARTED && tout--) 9257 msleep(20); 9258 9259 if (bnx2x_func_get_state(bp, &bp->func_obj) != 9260 BNX2X_F_STATE_STARTED) { 9261 #ifdef BNX2X_STOP_ON_ERROR 9262 BNX2X_ERR("Wrong function state\n"); 9263 return -EBUSY; 9264 #else 9265 /* 9266 * Failed to complete the transaction in a "good way" 9267 * Force both transactions with CLR bit 9268 */ 9269 struct bnx2x_func_state_params func_params = {NULL}; 9270 9271 DP(NETIF_MSG_IFDOWN, 9272 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); 9273 9274 func_params.f_obj = &bp->func_obj; 9275 __set_bit(RAMROD_DRV_CLR_ONLY, 9276 &func_params.ramrod_flags); 9277 9278 /* STARTED-->TX_ST0PPED */ 9279 func_params.cmd = BNX2X_F_CMD_TX_STOP; 9280 bnx2x_func_state_change(bp, &func_params); 9281 9282 /* TX_ST0PPED-->STARTED */ 9283 func_params.cmd = BNX2X_F_CMD_TX_START; 9284 return bnx2x_func_state_change(bp, &func_params); 9285 #endif 9286 } 9287 9288 return 0; 9289 } 9290 9291 static void bnx2x_disable_ptp(struct bnx2x *bp) 9292 { 9293 int port = BP_PORT(bp); 9294 9295 /* Disable sending PTP packets to host */ 9296 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 9297 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); 9298 9299 /* Reset PTP event detection rules */ 9300 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 9301 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); 9302 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 9303 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); 9304 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 9305 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); 9306 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 9307 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); 9308 9309 /* Disable the PTP feature */ 9310 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : 9311 NIG_REG_P0_PTP_EN, 0x0); 9312 } 9313 9314 /* Called during unload, to stop PTP-related stuff */ 9315 static void bnx2x_stop_ptp(struct bnx2x *bp) 9316 { 9317 /* Cancel PTP work queue. Should be done after the Tx queues are 9318 * drained to prevent additional scheduling. 9319 */ 9320 cancel_work_sync(&bp->ptp_task); 9321 9322 if (bp->ptp_tx_skb) { 9323 dev_kfree_skb_any(bp->ptp_tx_skb); 9324 bp->ptp_tx_skb = NULL; 9325 } 9326 9327 /* Disable PTP in HW */ 9328 bnx2x_disable_ptp(bp); 9329 9330 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); 9331 } 9332 9333 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) 9334 { 9335 int port = BP_PORT(bp); 9336 int i, rc = 0; 9337 u8 cos; 9338 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 9339 u32 reset_code; 9340 9341 /* Wait until tx fastpath tasks complete */ 9342 for_each_tx_queue(bp, i) { 9343 struct bnx2x_fastpath *fp = &bp->fp[i]; 9344 9345 for_each_cos_in_tx_queue(fp, cos) 9346 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); 9347 #ifdef BNX2X_STOP_ON_ERROR 9348 if (rc) 9349 return; 9350 #endif 9351 } 9352 9353 /* Give HW time to discard old tx messages */ 9354 usleep_range(1000, 2000); 9355 9356 /* Clean all ETH MACs */ 9357 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, 9358 false); 9359 if (rc < 0) 9360 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 9361 9362 /* Clean up UC list */ 9363 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, 9364 true); 9365 if (rc < 0) 9366 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", 9367 rc); 9368 9369 /* The whole *vlan_obj structure may be not initialized if VLAN 9370 * filtering offload is not supported by hardware. Currently this is 9371 * true for all hardware covered by CHIP_IS_E1x(). 9372 */ 9373 if (!CHIP_IS_E1x(bp)) { 9374 /* Remove all currently configured VLANs */ 9375 rc = bnx2x_del_all_vlans(bp); 9376 if (rc < 0) 9377 BNX2X_ERR("Failed to delete all VLANs\n"); 9378 } 9379 9380 /* Disable LLH */ 9381 if (!CHIP_IS_E1(bp)) 9382 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 9383 9384 /* Set "drop all" (stop Rx). 9385 * We need to take a netif_addr_lock() here in order to prevent 9386 * a race between the completion code and this code. 9387 */ 9388 netif_addr_lock_bh(bp->dev); 9389 /* Schedule the rx_mode command */ 9390 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 9391 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 9392 else if (bp->slowpath) 9393 bnx2x_set_storm_rx_mode(bp); 9394 9395 /* Cleanup multicast configuration */ 9396 rparam.mcast_obj = &bp->mcast_obj; 9397 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 9398 if (rc < 0) 9399 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 9400 9401 netif_addr_unlock_bh(bp->dev); 9402 9403 bnx2x_iov_chip_cleanup(bp); 9404 9405 /* 9406 * Send the UNLOAD_REQUEST to the MCP. This will return if 9407 * this function should perform FUNC, PORT or COMMON HW 9408 * reset. 9409 */ 9410 reset_code = bnx2x_send_unload_req(bp, unload_mode); 9411 9412 /* 9413 * (assumption: No Attention from MCP at this stage) 9414 * PMF probably in the middle of TX disable/enable transaction 9415 */ 9416 rc = bnx2x_func_wait_started(bp); 9417 if (rc) { 9418 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 9419 #ifdef BNX2X_STOP_ON_ERROR 9420 return; 9421 #endif 9422 } 9423 9424 /* Close multi and leading connections 9425 * Completions for ramrods are collected in a synchronous way 9426 */ 9427 for_each_eth_queue(bp, i) 9428 if (bnx2x_stop_queue(bp, i)) 9429 #ifdef BNX2X_STOP_ON_ERROR 9430 return; 9431 #else 9432 goto unload_error; 9433 #endif 9434 9435 if (CNIC_LOADED(bp)) { 9436 for_each_cnic_queue(bp, i) 9437 if (bnx2x_stop_queue(bp, i)) 9438 #ifdef BNX2X_STOP_ON_ERROR 9439 return; 9440 #else 9441 goto unload_error; 9442 #endif 9443 } 9444 9445 /* If SP settings didn't get completed so far - something 9446 * very wrong has happen. 9447 */ 9448 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 9449 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 9450 9451 #ifndef BNX2X_STOP_ON_ERROR 9452 unload_error: 9453 #endif 9454 rc = bnx2x_func_stop(bp); 9455 if (rc) { 9456 BNX2X_ERR("Function stop failed!\n"); 9457 #ifdef BNX2X_STOP_ON_ERROR 9458 return; 9459 #endif 9460 } 9461 9462 /* stop_ptp should be after the Tx queues are drained to prevent 9463 * scheduling to the cancelled PTP work queue. It should also be after 9464 * function stop ramrod is sent, since as part of this ramrod FW access 9465 * PTP registers. 9466 */ 9467 if (bp->flags & PTP_SUPPORTED) { 9468 bnx2x_stop_ptp(bp); 9469 if (bp->ptp_clock) { 9470 ptp_clock_unregister(bp->ptp_clock); 9471 bp->ptp_clock = NULL; 9472 } 9473 } 9474 9475 /* Disable HW interrupts, NAPI */ 9476 bnx2x_netif_stop(bp, 1); 9477 /* Delete all NAPI objects */ 9478 bnx2x_del_all_napi(bp); 9479 if (CNIC_LOADED(bp)) 9480 bnx2x_del_all_napi_cnic(bp); 9481 9482 /* Release IRQs */ 9483 bnx2x_free_irq(bp); 9484 9485 /* Reset the chip, unless PCI function is offline. If we reach this 9486 * point following a PCI error handling, it means device is really 9487 * in a bad state and we're about to remove it, so reset the chip 9488 * is not a good idea. 9489 */ 9490 if (!pci_channel_offline(bp->pdev)) { 9491 rc = bnx2x_reset_hw(bp, reset_code); 9492 if (rc) 9493 BNX2X_ERR("HW_RESET failed\n"); 9494 } 9495 9496 /* Report UNLOAD_DONE to MCP */ 9497 bnx2x_send_unload_done(bp, keep_link); 9498 } 9499 9500 void bnx2x_disable_close_the_gate(struct bnx2x *bp) 9501 { 9502 u32 val; 9503 9504 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); 9505 9506 if (CHIP_IS_E1(bp)) { 9507 int port = BP_PORT(bp); 9508 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 9509 MISC_REG_AEU_MASK_ATTN_FUNC_0; 9510 9511 val = REG_RD(bp, addr); 9512 val &= ~(0x300); 9513 REG_WR(bp, addr, val); 9514 } else { 9515 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 9516 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 9517 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 9518 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 9519 } 9520 } 9521 9522 /* Close gates #2, #3 and #4: */ 9523 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 9524 { 9525 u32 val; 9526 9527 /* Gates #2 and #4a are closed/opened for "not E1" only */ 9528 if (!CHIP_IS_E1(bp)) { 9529 /* #4 */ 9530 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 9531 /* #2 */ 9532 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 9533 } 9534 9535 /* #3 */ 9536 if (CHIP_IS_E1x(bp)) { 9537 /* Prevent interrupts from HC on both ports */ 9538 val = REG_RD(bp, HC_REG_CONFIG_1); 9539 REG_WR(bp, HC_REG_CONFIG_1, 9540 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 9541 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 9542 9543 val = REG_RD(bp, HC_REG_CONFIG_0); 9544 REG_WR(bp, HC_REG_CONFIG_0, 9545 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 9546 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 9547 } else { 9548 /* Prevent incoming interrupts in IGU */ 9549 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9550 9551 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 9552 (!close) ? 9553 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 9554 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 9555 } 9556 9557 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", 9558 close ? "closing" : "opening"); 9559 } 9560 9561 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 9562 9563 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 9564 { 9565 /* Do some magic... */ 9566 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 9567 *magic_val = val & SHARED_MF_CLP_MAGIC; 9568 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 9569 } 9570 9571 /** 9572 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 9573 * 9574 * @bp: driver handle 9575 * @magic_val: old value of the `magic' bit. 9576 */ 9577 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 9578 { 9579 /* Restore the `magic' bit value... */ 9580 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 9581 MF_CFG_WR(bp, shared_mf_config.clp_mb, 9582 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 9583 } 9584 9585 /** 9586 * bnx2x_reset_mcp_prep - prepare for MCP reset. 9587 * 9588 * @bp: driver handle 9589 * @magic_val: old value of 'magic' bit. 9590 * 9591 * Takes care of CLP configurations. 9592 */ 9593 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 9594 { 9595 u32 shmem; 9596 u32 validity_offset; 9597 9598 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); 9599 9600 /* Set `magic' bit in order to save MF config */ 9601 if (!CHIP_IS_E1(bp)) 9602 bnx2x_clp_reset_prep(bp, magic_val); 9603 9604 /* Get shmem offset */ 9605 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9606 validity_offset = 9607 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); 9608 9609 /* Clear validity map flags */ 9610 if (shmem > 0) 9611 REG_WR(bp, shmem + validity_offset, 0); 9612 } 9613 9614 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 9615 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 9616 9617 /** 9618 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 9619 * 9620 * @bp: driver handle 9621 */ 9622 static void bnx2x_mcp_wait_one(struct bnx2x *bp) 9623 { 9624 /* special handling for emulation and FPGA, 9625 wait 10 times longer */ 9626 if (CHIP_REV_IS_SLOW(bp)) 9627 msleep(MCP_ONE_TIMEOUT*10); 9628 else 9629 msleep(MCP_ONE_TIMEOUT); 9630 } 9631 9632 /* 9633 * initializes bp->common.shmem_base and waits for validity signature to appear 9634 */ 9635 static int bnx2x_init_shmem(struct bnx2x *bp) 9636 { 9637 int cnt = 0; 9638 u32 val = 0; 9639 9640 do { 9641 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9642 9643 /* If we read all 0xFFs, means we are in PCI error state and 9644 * should bail out to avoid crashes on adapter's FW reads. 9645 */ 9646 if (bp->common.shmem_base == 0xFFFFFFFF) { 9647 bp->flags |= NO_MCP_FLAG; 9648 return -ENODEV; 9649 } 9650 9651 if (bp->common.shmem_base) { 9652 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 9653 if (val & SHR_MEM_VALIDITY_MB) 9654 return 0; 9655 } 9656 9657 bnx2x_mcp_wait_one(bp); 9658 9659 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 9660 9661 BNX2X_ERR("BAD MCP validity signature\n"); 9662 9663 return -ENODEV; 9664 } 9665 9666 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 9667 { 9668 int rc = bnx2x_init_shmem(bp); 9669 9670 /* Restore the `magic' bit value */ 9671 if (!CHIP_IS_E1(bp)) 9672 bnx2x_clp_reset_done(bp, magic_val); 9673 9674 return rc; 9675 } 9676 9677 static void bnx2x_pxp_prep(struct bnx2x *bp) 9678 { 9679 if (!CHIP_IS_E1(bp)) { 9680 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 9681 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 9682 } 9683 } 9684 9685 /* 9686 * Reset the whole chip except for: 9687 * - PCIE core 9688 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 9689 * one reset bit) 9690 * - IGU 9691 * - MISC (including AEU) 9692 * - GRC 9693 * - RBCN, RBCP 9694 */ 9695 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 9696 { 9697 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 9698 u32 global_bits2, stay_reset2; 9699 9700 /* 9701 * Bits that have to be set in reset_mask2 if we want to reset 'global' 9702 * (per chip) blocks. 9703 */ 9704 global_bits2 = 9705 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 9706 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 9707 9708 /* Don't reset the following blocks. 9709 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 9710 * reset, as in 4 port device they might still be owned 9711 * by the MCP (there is only one leader per path). 9712 */ 9713 not_reset_mask1 = 9714 MISC_REGISTERS_RESET_REG_1_RST_HC | 9715 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 9716 MISC_REGISTERS_RESET_REG_1_RST_PXP; 9717 9718 not_reset_mask2 = 9719 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 9720 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 9721 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 9722 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 9723 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 9724 MISC_REGISTERS_RESET_REG_2_RST_GRC | 9725 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 9726 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 9727 MISC_REGISTERS_RESET_REG_2_RST_ATC | 9728 MISC_REGISTERS_RESET_REG_2_PGLC | 9729 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 9730 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 9731 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 9732 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 9733 MISC_REGISTERS_RESET_REG_2_UMAC0 | 9734 MISC_REGISTERS_RESET_REG_2_UMAC1; 9735 9736 /* 9737 * Keep the following blocks in reset: 9738 * - all xxMACs are handled by the bnx2x_link code. 9739 */ 9740 stay_reset2 = 9741 MISC_REGISTERS_RESET_REG_2_XMAC | 9742 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 9743 9744 /* Full reset masks according to the chip */ 9745 reset_mask1 = 0xffffffff; 9746 9747 if (CHIP_IS_E1(bp)) 9748 reset_mask2 = 0xffff; 9749 else if (CHIP_IS_E1H(bp)) 9750 reset_mask2 = 0x1ffff; 9751 else if (CHIP_IS_E2(bp)) 9752 reset_mask2 = 0xfffff; 9753 else /* CHIP_IS_E3 */ 9754 reset_mask2 = 0x3ffffff; 9755 9756 /* Don't reset global blocks unless we need to */ 9757 if (!global) 9758 reset_mask2 &= ~global_bits2; 9759 9760 /* 9761 * In case of attention in the QM, we need to reset PXP 9762 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 9763 * because otherwise QM reset would release 'close the gates' shortly 9764 * before resetting the PXP, then the PSWRQ would send a write 9765 * request to PGLUE. Then when PXP is reset, PGLUE would try to 9766 * read the payload data from PSWWR, but PSWWR would not 9767 * respond. The write queue in PGLUE would stuck, dmae commands 9768 * would not return. Therefore it's important to reset the second 9769 * reset register (containing the 9770 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 9771 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 9772 * bit). 9773 */ 9774 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 9775 reset_mask2 & (~not_reset_mask2)); 9776 9777 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 9778 reset_mask1 & (~not_reset_mask1)); 9779 9780 barrier(); 9781 9782 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 9783 reset_mask2 & (~stay_reset2)); 9784 9785 barrier(); 9786 9787 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 9788 } 9789 9790 /** 9791 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 9792 * It should get cleared in no more than 1s. 9793 * 9794 * @bp: driver handle 9795 * 9796 * It should get cleared in no more than 1s. Returns 0 if 9797 * pending writes bit gets cleared. 9798 */ 9799 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 9800 { 9801 u32 cnt = 1000; 9802 u32 pend_bits = 0; 9803 9804 do { 9805 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 9806 9807 if (pend_bits == 0) 9808 break; 9809 9810 usleep_range(1000, 2000); 9811 } while (cnt-- > 0); 9812 9813 if (cnt <= 0) { 9814 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 9815 pend_bits); 9816 return -EBUSY; 9817 } 9818 9819 return 0; 9820 } 9821 9822 static int bnx2x_process_kill(struct bnx2x *bp, bool global) 9823 { 9824 int cnt = 1000; 9825 u32 val = 0; 9826 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 9827 u32 tags_63_32 = 0; 9828 9829 /* Empty the Tetris buffer, wait for 1s */ 9830 do { 9831 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 9832 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 9833 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 9834 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 9835 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 9836 if (CHIP_IS_E3(bp)) 9837 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); 9838 9839 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 9840 ((port_is_idle_0 & 0x1) == 0x1) && 9841 ((port_is_idle_1 & 0x1) == 0x1) && 9842 (pgl_exp_rom2 == 0xffffffff) && 9843 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) 9844 break; 9845 usleep_range(1000, 2000); 9846 } while (cnt-- > 0); 9847 9848 if (cnt <= 0) { 9849 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); 9850 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 9851 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 9852 pgl_exp_rom2); 9853 return -EAGAIN; 9854 } 9855 9856 barrier(); 9857 9858 /* Close gates #2, #3 and #4 */ 9859 bnx2x_set_234_gates(bp, true); 9860 9861 /* Poll for IGU VQs for 57712 and newer chips */ 9862 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 9863 return -EAGAIN; 9864 9865 /* TBD: Indicate that "process kill" is in progress to MCP */ 9866 9867 /* Clear "unprepared" bit */ 9868 REG_WR(bp, MISC_REG_UNPREPARED, 0); 9869 barrier(); 9870 9871 /* Wait for 1ms to empty GLUE and PCI-E core queues, 9872 * PSWHST, GRC and PSWRD Tetris buffer. 9873 */ 9874 usleep_range(1000, 2000); 9875 9876 /* Prepare to chip reset: */ 9877 /* MCP */ 9878 if (global) 9879 bnx2x_reset_mcp_prep(bp, &val); 9880 9881 /* PXP */ 9882 bnx2x_pxp_prep(bp); 9883 barrier(); 9884 9885 /* reset the chip */ 9886 bnx2x_process_kill_chip_reset(bp, global); 9887 barrier(); 9888 9889 /* clear errors in PGB */ 9890 if (!CHIP_IS_E1x(bp)) 9891 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); 9892 9893 /* Recover after reset: */ 9894 /* MCP */ 9895 if (global && bnx2x_reset_mcp_comp(bp, val)) 9896 return -EAGAIN; 9897 9898 /* TBD: Add resetting the NO_MCP mode DB here */ 9899 9900 /* Open the gates #2, #3 and #4 */ 9901 bnx2x_set_234_gates(bp, false); 9902 9903 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 9904 * reset state, re-enable attentions. */ 9905 9906 return 0; 9907 } 9908 9909 static int bnx2x_leader_reset(struct bnx2x *bp) 9910 { 9911 int rc = 0; 9912 bool global = bnx2x_reset_is_global(bp); 9913 u32 load_code; 9914 9915 /* if not going to reset MCP - load "fake" driver to reset HW while 9916 * driver is owner of the HW 9917 */ 9918 if (!global && !BP_NOMCP(bp)) { 9919 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 9920 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 9921 if (!load_code) { 9922 BNX2X_ERR("MCP response failure, aborting\n"); 9923 rc = -EAGAIN; 9924 goto exit_leader_reset; 9925 } 9926 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 9927 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 9928 BNX2X_ERR("MCP unexpected resp, aborting\n"); 9929 rc = -EAGAIN; 9930 goto exit_leader_reset2; 9931 } 9932 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 9933 if (!load_code) { 9934 BNX2X_ERR("MCP response failure, aborting\n"); 9935 rc = -EAGAIN; 9936 goto exit_leader_reset2; 9937 } 9938 } 9939 9940 /* Try to recover after the failure */ 9941 if (bnx2x_process_kill(bp, global)) { 9942 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", 9943 BP_PATH(bp)); 9944 rc = -EAGAIN; 9945 goto exit_leader_reset2; 9946 } 9947 9948 /* 9949 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 9950 * state. 9951 */ 9952 bnx2x_set_reset_done(bp); 9953 if (global) 9954 bnx2x_clear_reset_global(bp); 9955 9956 exit_leader_reset2: 9957 /* unload "fake driver" if it was loaded */ 9958 if (!global && !BP_NOMCP(bp)) { 9959 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 9960 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 9961 } 9962 exit_leader_reset: 9963 bp->is_leader = 0; 9964 bnx2x_release_leader_lock(bp); 9965 smp_mb(); 9966 return rc; 9967 } 9968 9969 static void bnx2x_recovery_failed(struct bnx2x *bp) 9970 { 9971 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 9972 9973 /* Disconnect this device */ 9974 netif_device_detach(bp->dev); 9975 9976 /* 9977 * Block ifup for all function on this engine until "process kill" 9978 * or power cycle. 9979 */ 9980 bnx2x_set_reset_in_progress(bp); 9981 9982 /* Shut down the power */ 9983 bnx2x_set_power_state(bp, PCI_D3hot); 9984 9985 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9986 9987 smp_mb(); 9988 } 9989 9990 /* 9991 * Assumption: runs under rtnl lock. This together with the fact 9992 * that it's called only from bnx2x_sp_rtnl() ensure that it 9993 * will never be called when netif_running(bp->dev) is false. 9994 */ 9995 static void bnx2x_parity_recover(struct bnx2x *bp) 9996 { 9997 u32 error_recovered, error_unrecovered; 9998 bool is_parity, global = false; 9999 #ifdef CONFIG_BNX2X_SRIOV 10000 int vf_idx; 10001 10002 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { 10003 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 10004 10005 if (vf) 10006 vf->state = VF_LOST; 10007 } 10008 #endif 10009 DP(NETIF_MSG_HW, "Handling parity\n"); 10010 while (1) { 10011 switch (bp->recovery_state) { 10012 case BNX2X_RECOVERY_INIT: 10013 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 10014 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 10015 WARN_ON(!is_parity); 10016 10017 /* Try to get a LEADER_LOCK HW lock */ 10018 if (bnx2x_trylock_leader_lock(bp)) { 10019 bnx2x_set_reset_in_progress(bp); 10020 /* 10021 * Check if there is a global attention and if 10022 * there was a global attention, set the global 10023 * reset bit. 10024 */ 10025 10026 if (global) 10027 bnx2x_set_reset_global(bp); 10028 10029 bp->is_leader = 1; 10030 } 10031 10032 /* Stop the driver */ 10033 /* If interface has been removed - break */ 10034 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) 10035 return; 10036 10037 bp->recovery_state = BNX2X_RECOVERY_WAIT; 10038 10039 /* Ensure "is_leader", MCP command sequence and 10040 * "recovery_state" update values are seen on other 10041 * CPUs. 10042 */ 10043 smp_mb(); 10044 break; 10045 10046 case BNX2X_RECOVERY_WAIT: 10047 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 10048 if (bp->is_leader) { 10049 int other_engine = BP_PATH(bp) ? 0 : 1; 10050 bool other_load_status = 10051 bnx2x_get_load_status(bp, other_engine); 10052 bool load_status = 10053 bnx2x_get_load_status(bp, BP_PATH(bp)); 10054 global = bnx2x_reset_is_global(bp); 10055 10056 /* 10057 * In case of a parity in a global block, let 10058 * the first leader that performs a 10059 * leader_reset() reset the global blocks in 10060 * order to clear global attentions. Otherwise 10061 * the gates will remain closed for that 10062 * engine. 10063 */ 10064 if (load_status || 10065 (global && other_load_status)) { 10066 /* Wait until all other functions get 10067 * down. 10068 */ 10069 schedule_delayed_work(&bp->sp_rtnl_task, 10070 HZ/10); 10071 return; 10072 } else { 10073 /* If all other functions got down - 10074 * try to bring the chip back to 10075 * normal. In any case it's an exit 10076 * point for a leader. 10077 */ 10078 if (bnx2x_leader_reset(bp)) { 10079 bnx2x_recovery_failed(bp); 10080 return; 10081 } 10082 10083 /* If we are here, means that the 10084 * leader has succeeded and doesn't 10085 * want to be a leader any more. Try 10086 * to continue as a none-leader. 10087 */ 10088 break; 10089 } 10090 } else { /* non-leader */ 10091 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 10092 /* Try to get a LEADER_LOCK HW lock as 10093 * long as a former leader may have 10094 * been unloaded by the user or 10095 * released a leadership by another 10096 * reason. 10097 */ 10098 if (bnx2x_trylock_leader_lock(bp)) { 10099 /* I'm a leader now! Restart a 10100 * switch case. 10101 */ 10102 bp->is_leader = 1; 10103 break; 10104 } 10105 10106 schedule_delayed_work(&bp->sp_rtnl_task, 10107 HZ/10); 10108 return; 10109 10110 } else { 10111 /* 10112 * If there was a global attention, wait 10113 * for it to be cleared. 10114 */ 10115 if (bnx2x_reset_is_global(bp)) { 10116 schedule_delayed_work( 10117 &bp->sp_rtnl_task, 10118 HZ/10); 10119 return; 10120 } 10121 10122 error_recovered = 10123 bp->eth_stats.recoverable_error; 10124 error_unrecovered = 10125 bp->eth_stats.unrecoverable_error; 10126 bp->recovery_state = 10127 BNX2X_RECOVERY_NIC_LOADING; 10128 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 10129 error_unrecovered++; 10130 netdev_err(bp->dev, 10131 "Recovery failed. Power cycle needed\n"); 10132 /* Disconnect this device */ 10133 netif_device_detach(bp->dev); 10134 /* Shut down the power */ 10135 bnx2x_set_power_state( 10136 bp, PCI_D3hot); 10137 smp_mb(); 10138 } else { 10139 bp->recovery_state = 10140 BNX2X_RECOVERY_DONE; 10141 error_recovered++; 10142 smp_mb(); 10143 } 10144 bp->eth_stats.recoverable_error = 10145 error_recovered; 10146 bp->eth_stats.unrecoverable_error = 10147 error_unrecovered; 10148 10149 return; 10150 } 10151 } 10152 default: 10153 return; 10154 } 10155 } 10156 } 10157 10158 static int bnx2x_udp_port_update(struct bnx2x *bp) 10159 { 10160 struct bnx2x_func_switch_update_params *switch_update_params; 10161 struct bnx2x_func_state_params func_params = {NULL}; 10162 u16 vxlan_port = 0, geneve_port = 0; 10163 int rc; 10164 10165 switch_update_params = &func_params.params.switch_update; 10166 10167 /* Prepare parameters for function state transitions */ 10168 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 10169 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 10170 10171 func_params.f_obj = &bp->func_obj; 10172 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 10173 10174 /* Function parameters */ 10175 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, 10176 &switch_update_params->changes); 10177 10178 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) { 10179 geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; 10180 switch_update_params->geneve_dst_port = geneve_port; 10181 } 10182 10183 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) { 10184 vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; 10185 switch_update_params->vxlan_dst_port = vxlan_port; 10186 } 10187 10188 /* Re-enable inner-rss for the offloaded UDP tunnels */ 10189 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS, 10190 &switch_update_params->changes); 10191 10192 rc = bnx2x_func_state_change(bp, &func_params); 10193 if (rc) 10194 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n", 10195 vxlan_port, geneve_port, rc); 10196 else 10197 DP(BNX2X_MSG_SP, 10198 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n", 10199 vxlan_port, geneve_port); 10200 10201 return rc; 10202 } 10203 10204 static int bnx2x_udp_tunnel_sync(struct net_device *netdev, unsigned int table) 10205 { 10206 struct bnx2x *bp = netdev_priv(netdev); 10207 struct udp_tunnel_info ti; 10208 10209 udp_tunnel_nic_get_port(netdev, table, 0, &ti); 10210 bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port); 10211 10212 return bnx2x_udp_port_update(bp); 10213 } 10214 10215 static const struct udp_tunnel_nic_info bnx2x_udp_tunnels = { 10216 .sync_table = bnx2x_udp_tunnel_sync, 10217 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 10218 UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 10219 .tables = { 10220 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 10221 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 10222 }, 10223 }; 10224 10225 static int bnx2x_close(struct net_device *dev); 10226 10227 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 10228 * scheduled on a general queue in order to prevent a dead lock. 10229 */ 10230 static void bnx2x_sp_rtnl_task(struct work_struct *work) 10231 { 10232 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 10233 10234 rtnl_lock(); 10235 10236 if (!netif_running(bp->dev)) { 10237 rtnl_unlock(); 10238 return; 10239 } 10240 10241 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 10242 #ifdef BNX2X_STOP_ON_ERROR 10243 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 10244 "you will need to reboot when done\n"); 10245 goto sp_rtnl_not_reset; 10246 #endif 10247 /* 10248 * Clear all pending SP commands as we are going to reset the 10249 * function anyway. 10250 */ 10251 bp->sp_rtnl_state = 0; 10252 smp_mb(); 10253 10254 bnx2x_parity_recover(bp); 10255 10256 rtnl_unlock(); 10257 return; 10258 } 10259 10260 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 10261 #ifdef BNX2X_STOP_ON_ERROR 10262 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 10263 "you will need to reboot when done\n"); 10264 goto sp_rtnl_not_reset; 10265 #endif 10266 10267 /* 10268 * Clear all pending SP commands as we are going to reset the 10269 * function anyway. 10270 */ 10271 bp->sp_rtnl_state = 0; 10272 smp_mb(); 10273 10274 /* Immediately indicate link as down */ 10275 bp->link_vars.link_up = 0; 10276 bp->force_link_down = true; 10277 netif_carrier_off(bp->dev); 10278 BNX2X_ERR("Indicating link is down due to Tx-timeout\n"); 10279 10280 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 10281 /* When ret value shows failure of allocation failure, 10282 * the nic is rebooted again. If open still fails, a error 10283 * message to notify the user. 10284 */ 10285 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) { 10286 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 10287 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 10288 BNX2X_ERR("Open the NIC fails again!\n"); 10289 } 10290 rtnl_unlock(); 10291 return; 10292 } 10293 #ifdef BNX2X_STOP_ON_ERROR 10294 sp_rtnl_not_reset: 10295 #endif 10296 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 10297 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 10298 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) 10299 bnx2x_after_function_update(bp); 10300 /* 10301 * in case of fan failure we need to reset id if the "stop on error" 10302 * debug flag is set, since we trying to prevent permanent overheating 10303 * damage 10304 */ 10305 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 10306 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); 10307 netif_device_detach(bp->dev); 10308 bnx2x_close(bp->dev); 10309 rtnl_unlock(); 10310 return; 10311 } 10312 10313 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { 10314 DP(BNX2X_MSG_SP, 10315 "sending set mcast vf pf channel message from rtnl sp-task\n"); 10316 bnx2x_vfpf_set_mcast(bp->dev); 10317 } 10318 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 10319 &bp->sp_rtnl_state)){ 10320 if (netif_carrier_ok(bp->dev)) { 10321 bnx2x_tx_disable(bp); 10322 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); 10323 } 10324 } 10325 10326 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { 10327 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); 10328 bnx2x_set_rx_mode_inner(bp); 10329 } 10330 10331 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, 10332 &bp->sp_rtnl_state)) 10333 bnx2x_pf_set_vfs_vlan(bp); 10334 10335 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { 10336 bnx2x_dcbx_stop_hw_tx(bp); 10337 bnx2x_dcbx_resume_hw_tx(bp); 10338 } 10339 10340 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION, 10341 &bp->sp_rtnl_state)) 10342 bnx2x_update_mng_version(bp); 10343 10344 if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state)) 10345 bnx2x_handle_update_svid_cmd(bp); 10346 10347 /* work which needs rtnl lock not-taken (as it takes the lock itself and 10348 * can be called from other contexts as well) 10349 */ 10350 rtnl_unlock(); 10351 10352 /* enable SR-IOV if applicable */ 10353 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, 10354 &bp->sp_rtnl_state)) { 10355 bnx2x_disable_sriov(bp); 10356 bnx2x_enable_sriov(bp); 10357 } 10358 } 10359 10360 static void bnx2x_period_task(struct work_struct *work) 10361 { 10362 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 10363 10364 if (!netif_running(bp->dev)) 10365 goto period_task_exit; 10366 10367 if (CHIP_REV_IS_SLOW(bp)) { 10368 BNX2X_ERR("period task called on emulation, ignoring\n"); 10369 goto period_task_exit; 10370 } 10371 10372 bnx2x_acquire_phy_lock(bp); 10373 /* 10374 * The barrier is needed to ensure the ordering between the writing to 10375 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 10376 * the reading here. 10377 */ 10378 smp_mb(); 10379 if (bp->port.pmf) { 10380 bnx2x_period_func(&bp->link_params, &bp->link_vars); 10381 10382 /* Re-queue task in 1 sec */ 10383 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 10384 } 10385 10386 bnx2x_release_phy_lock(bp); 10387 period_task_exit: 10388 return; 10389 } 10390 10391 /* 10392 * Init service functions 10393 */ 10394 10395 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 10396 { 10397 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 10398 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 10399 return base + (BP_ABS_FUNC(bp)) * stride; 10400 } 10401 10402 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, 10403 u8 port, u32 reset_reg, 10404 struct bnx2x_mac_vals *vals) 10405 { 10406 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 10407 u32 base_addr; 10408 10409 if (!(mask & reset_reg)) 10410 return false; 10411 10412 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port); 10413 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 10414 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; 10415 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); 10416 REG_WR(bp, vals->umac_addr[port], 0); 10417 10418 return true; 10419 } 10420 10421 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, 10422 struct bnx2x_mac_vals *vals) 10423 { 10424 u32 val, base_addr, offset, mask, reset_reg; 10425 bool mac_stopped = false; 10426 u8 port = BP_PORT(bp); 10427 10428 /* reset addresses as they also mark which values were changed */ 10429 memset(vals, 0, sizeof(*vals)); 10430 10431 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); 10432 10433 if (!CHIP_IS_E3(bp)) { 10434 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 10435 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 10436 if ((mask & reset_reg) && val) { 10437 u32 wb_data[2]; 10438 BNX2X_DEV_INFO("Disable bmac Rx\n"); 10439 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM 10440 : NIG_REG_INGRESS_BMAC0_MEM; 10441 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL 10442 : BIGMAC_REGISTER_BMAC_CONTROL; 10443 10444 /* 10445 * use rd/wr since we cannot use dmae. This is safe 10446 * since MCP won't access the bus due to the request 10447 * to unload, and no function on the path can be 10448 * loaded at this time. 10449 */ 10450 wb_data[0] = REG_RD(bp, base_addr + offset); 10451 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); 10452 vals->bmac_addr = base_addr + offset; 10453 vals->bmac_val[0] = wb_data[0]; 10454 vals->bmac_val[1] = wb_data[1]; 10455 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 10456 REG_WR(bp, vals->bmac_addr, wb_data[0]); 10457 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); 10458 } 10459 BNX2X_DEV_INFO("Disable emac Rx\n"); 10460 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; 10461 vals->emac_val = REG_RD(bp, vals->emac_addr); 10462 REG_WR(bp, vals->emac_addr, 0); 10463 mac_stopped = true; 10464 } else { 10465 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 10466 BNX2X_DEV_INFO("Disable xmac Rx\n"); 10467 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 10468 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); 10469 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 10470 val & ~(1 << 1)); 10471 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 10472 val | (1 << 1)); 10473 vals->xmac_addr = base_addr + XMAC_REG_CTRL; 10474 vals->xmac_val = REG_RD(bp, vals->xmac_addr); 10475 REG_WR(bp, vals->xmac_addr, 0); 10476 mac_stopped = true; 10477 } 10478 10479 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, 10480 reset_reg, vals); 10481 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, 10482 reset_reg, vals); 10483 } 10484 10485 if (mac_stopped) 10486 msleep(20); 10487 } 10488 10489 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 10490 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \ 10491 0x1848 + ((f) << 4)) 10492 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) 10493 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 10494 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 10495 10496 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07) 10497 #define BCM_5710_UNDI_FW_MF_MINOR (0x08) 10498 #define BCM_5710_UNDI_FW_MF_VERS (0x05) 10499 10500 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) 10501 { 10502 /* UNDI marks its presence in DORQ - 10503 * it initializes CID offset for normal bell to 0x7 10504 */ 10505 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & 10506 MISC_REGISTERS_RESET_REG_1_RST_DORQ)) 10507 return false; 10508 10509 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { 10510 BNX2X_DEV_INFO("UNDI previously loaded\n"); 10511 return true; 10512 } 10513 10514 return false; 10515 } 10516 10517 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) 10518 { 10519 u16 rcq, bd; 10520 u32 addr, tmp_reg; 10521 10522 if (BP_FUNC(bp) < 2) 10523 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); 10524 else 10525 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); 10526 10527 tmp_reg = REG_RD(bp, addr); 10528 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; 10529 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; 10530 10531 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); 10532 REG_WR(bp, addr, tmp_reg); 10533 10534 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", 10535 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); 10536 } 10537 10538 static int bnx2x_prev_mcp_done(struct bnx2x *bp) 10539 { 10540 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 10541 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 10542 if (!rc) { 10543 BNX2X_ERR("MCP response failure, aborting\n"); 10544 return -EBUSY; 10545 } 10546 10547 return 0; 10548 } 10549 10550 static struct bnx2x_prev_path_list * 10551 bnx2x_prev_path_get_entry(struct bnx2x *bp) 10552 { 10553 struct bnx2x_prev_path_list *tmp_list; 10554 10555 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) 10556 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && 10557 bp->pdev->bus->number == tmp_list->bus && 10558 BP_PATH(bp) == tmp_list->path) 10559 return tmp_list; 10560 10561 return NULL; 10562 } 10563 10564 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) 10565 { 10566 struct bnx2x_prev_path_list *tmp_list; 10567 int rc; 10568 10569 rc = down_interruptible(&bnx2x_prev_sem); 10570 if (rc) { 10571 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10572 return rc; 10573 } 10574 10575 tmp_list = bnx2x_prev_path_get_entry(bp); 10576 if (tmp_list) { 10577 tmp_list->aer = 1; 10578 rc = 0; 10579 } else { 10580 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", 10581 BP_PATH(bp)); 10582 } 10583 10584 up(&bnx2x_prev_sem); 10585 10586 return rc; 10587 } 10588 10589 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) 10590 { 10591 struct bnx2x_prev_path_list *tmp_list; 10592 bool rc = false; 10593 10594 if (down_trylock(&bnx2x_prev_sem)) 10595 return false; 10596 10597 tmp_list = bnx2x_prev_path_get_entry(bp); 10598 if (tmp_list) { 10599 if (tmp_list->aer) { 10600 DP(NETIF_MSG_HW, "Path %d was marked by AER\n", 10601 BP_PATH(bp)); 10602 } else { 10603 rc = true; 10604 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", 10605 BP_PATH(bp)); 10606 } 10607 } 10608 10609 up(&bnx2x_prev_sem); 10610 10611 return rc; 10612 } 10613 10614 bool bnx2x_port_after_undi(struct bnx2x *bp) 10615 { 10616 struct bnx2x_prev_path_list *entry; 10617 bool val; 10618 10619 down(&bnx2x_prev_sem); 10620 10621 entry = bnx2x_prev_path_get_entry(bp); 10622 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); 10623 10624 up(&bnx2x_prev_sem); 10625 10626 return val; 10627 } 10628 10629 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) 10630 { 10631 struct bnx2x_prev_path_list *tmp_list; 10632 int rc; 10633 10634 rc = down_interruptible(&bnx2x_prev_sem); 10635 if (rc) { 10636 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10637 return rc; 10638 } 10639 10640 /* Check whether the entry for this path already exists */ 10641 tmp_list = bnx2x_prev_path_get_entry(bp); 10642 if (tmp_list) { 10643 if (!tmp_list->aer) { 10644 BNX2X_ERR("Re-Marking the path.\n"); 10645 } else { 10646 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", 10647 BP_PATH(bp)); 10648 tmp_list->aer = 0; 10649 } 10650 up(&bnx2x_prev_sem); 10651 return 0; 10652 } 10653 up(&bnx2x_prev_sem); 10654 10655 /* Create an entry for this path and add it */ 10656 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); 10657 if (!tmp_list) { 10658 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); 10659 return -ENOMEM; 10660 } 10661 10662 tmp_list->bus = bp->pdev->bus->number; 10663 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); 10664 tmp_list->path = BP_PATH(bp); 10665 tmp_list->aer = 0; 10666 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; 10667 10668 rc = down_interruptible(&bnx2x_prev_sem); 10669 if (rc) { 10670 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10671 kfree(tmp_list); 10672 } else { 10673 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", 10674 BP_PATH(bp)); 10675 list_add(&tmp_list->list, &bnx2x_prev_list); 10676 up(&bnx2x_prev_sem); 10677 } 10678 10679 return rc; 10680 } 10681 10682 static int bnx2x_do_flr(struct bnx2x *bp) 10683 { 10684 struct pci_dev *dev = bp->pdev; 10685 10686 if (CHIP_IS_E1x(bp)) { 10687 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); 10688 return -EINVAL; 10689 } 10690 10691 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 10692 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 10693 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", 10694 bp->common.bc_ver); 10695 return -EINVAL; 10696 } 10697 10698 if (!pci_wait_for_pending_transaction(dev)) 10699 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 10700 10701 BNX2X_DEV_INFO("Initiating FLR\n"); 10702 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); 10703 10704 return 0; 10705 } 10706 10707 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) 10708 { 10709 int rc; 10710 10711 BNX2X_DEV_INFO("Uncommon unload Flow\n"); 10712 10713 /* Test if previous unload process was already finished for this path */ 10714 if (bnx2x_prev_is_path_marked(bp)) 10715 return bnx2x_prev_mcp_done(bp); 10716 10717 BNX2X_DEV_INFO("Path is unmarked\n"); 10718 10719 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ 10720 if (bnx2x_prev_is_after_undi(bp)) 10721 goto out; 10722 10723 /* If function has FLR capabilities, and existing FW version matches 10724 * the one required, then FLR will be sufficient to clean any residue 10725 * left by previous driver 10726 */ 10727 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); 10728 10729 if (!rc) { 10730 /* fw version is good */ 10731 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); 10732 rc = bnx2x_do_flr(bp); 10733 } 10734 10735 if (!rc) { 10736 /* FLR was performed */ 10737 BNX2X_DEV_INFO("FLR successful\n"); 10738 return 0; 10739 } 10740 10741 BNX2X_DEV_INFO("Could not FLR\n"); 10742 10743 out: 10744 /* Close the MCP request, return failure*/ 10745 rc = bnx2x_prev_mcp_done(bp); 10746 if (!rc) 10747 rc = BNX2X_PREV_WAIT_NEEDED; 10748 10749 return rc; 10750 } 10751 10752 static int bnx2x_prev_unload_common(struct bnx2x *bp) 10753 { 10754 u32 reset_reg, tmp_reg = 0, rc; 10755 bool prev_undi = false; 10756 struct bnx2x_mac_vals mac_vals; 10757 10758 /* It is possible a previous function received 'common' answer, 10759 * but hasn't loaded yet, therefore creating a scenario of 10760 * multiple functions receiving 'common' on the same path. 10761 */ 10762 BNX2X_DEV_INFO("Common unload Flow\n"); 10763 10764 memset(&mac_vals, 0, sizeof(mac_vals)); 10765 10766 if (bnx2x_prev_is_path_marked(bp)) 10767 return bnx2x_prev_mcp_done(bp); 10768 10769 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 10770 10771 /* Reset should be performed after BRB is emptied */ 10772 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 10773 u32 timer_count = 1000; 10774 10775 /* Close the MAC Rx to prevent BRB from filling up */ 10776 bnx2x_prev_unload_close_mac(bp, &mac_vals); 10777 10778 /* close LLH filters for both ports towards the BRB */ 10779 bnx2x_set_rx_filter(&bp->link_params, 0); 10780 bp->link_params.port ^= 1; 10781 bnx2x_set_rx_filter(&bp->link_params, 0); 10782 bp->link_params.port ^= 1; 10783 10784 /* Check if the UNDI driver was previously loaded */ 10785 if (bnx2x_prev_is_after_undi(bp)) { 10786 prev_undi = true; 10787 /* clear the UNDI indication */ 10788 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 10789 /* clear possible idle check errors */ 10790 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); 10791 } 10792 if (!CHIP_IS_E1x(bp)) 10793 /* block FW from writing to host */ 10794 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 10795 10796 /* wait until BRB is empty */ 10797 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10798 while (timer_count) { 10799 u32 prev_brb = tmp_reg; 10800 10801 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10802 if (!tmp_reg) 10803 break; 10804 10805 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); 10806 10807 /* reset timer as long as BRB actually gets emptied */ 10808 if (prev_brb > tmp_reg) 10809 timer_count = 1000; 10810 else 10811 timer_count--; 10812 10813 /* If UNDI resides in memory, manually increment it */ 10814 if (prev_undi) 10815 bnx2x_prev_unload_undi_inc(bp, 1); 10816 10817 udelay(10); 10818 } 10819 10820 if (!timer_count) 10821 BNX2X_ERR("Failed to empty BRB, hope for the best\n"); 10822 } 10823 10824 /* No packets are in the pipeline, path is ready for reset */ 10825 bnx2x_reset_common(bp); 10826 10827 if (mac_vals.xmac_addr) 10828 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); 10829 if (mac_vals.umac_addr[0]) 10830 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); 10831 if (mac_vals.umac_addr[1]) 10832 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); 10833 if (mac_vals.emac_addr) 10834 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); 10835 if (mac_vals.bmac_addr) { 10836 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); 10837 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); 10838 } 10839 10840 rc = bnx2x_prev_mark_path(bp, prev_undi); 10841 if (rc) { 10842 bnx2x_prev_mcp_done(bp); 10843 return rc; 10844 } 10845 10846 return bnx2x_prev_mcp_done(bp); 10847 } 10848 10849 static int bnx2x_prev_unload(struct bnx2x *bp) 10850 { 10851 int time_counter = 10; 10852 u32 rc, fw, hw_lock_reg, hw_lock_val; 10853 BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); 10854 10855 /* clear hw from errors which may have resulted from an interrupted 10856 * dmae transaction. 10857 */ 10858 bnx2x_clean_pglue_errors(bp); 10859 10860 /* Release previously held locks */ 10861 hw_lock_reg = (BP_FUNC(bp) <= 5) ? 10862 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : 10863 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); 10864 10865 hw_lock_val = REG_RD(bp, hw_lock_reg); 10866 if (hw_lock_val) { 10867 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 10868 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); 10869 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 10870 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); 10871 } 10872 10873 BNX2X_DEV_INFO("Release Previously held hw lock\n"); 10874 REG_WR(bp, hw_lock_reg, 0xffffffff); 10875 } else 10876 BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); 10877 10878 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { 10879 BNX2X_DEV_INFO("Release previously held alr\n"); 10880 bnx2x_release_alr(bp); 10881 } 10882 10883 do { 10884 int aer = 0; 10885 /* Lock MCP using an unload request */ 10886 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 10887 if (!fw) { 10888 BNX2X_ERR("MCP response failure, aborting\n"); 10889 rc = -EBUSY; 10890 break; 10891 } 10892 10893 rc = down_interruptible(&bnx2x_prev_sem); 10894 if (rc) { 10895 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", 10896 rc); 10897 } else { 10898 /* If Path is marked by EEH, ignore unload status */ 10899 aer = !!(bnx2x_prev_path_get_entry(bp) && 10900 bnx2x_prev_path_get_entry(bp)->aer); 10901 up(&bnx2x_prev_sem); 10902 } 10903 10904 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { 10905 rc = bnx2x_prev_unload_common(bp); 10906 break; 10907 } 10908 10909 /* non-common reply from MCP might require looping */ 10910 rc = bnx2x_prev_unload_uncommon(bp); 10911 if (rc != BNX2X_PREV_WAIT_NEEDED) 10912 break; 10913 10914 msleep(20); 10915 } while (--time_counter); 10916 10917 if (!time_counter || rc) { 10918 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n"); 10919 rc = -EPROBE_DEFER; 10920 } 10921 10922 /* Mark function if its port was used to boot from SAN */ 10923 if (bnx2x_port_after_undi(bp)) 10924 bp->link_params.feature_config_flags |= 10925 FEATURE_CONFIG_BOOT_FROM_SAN; 10926 10927 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); 10928 10929 return rc; 10930 } 10931 10932 static void bnx2x_get_common_hwinfo(struct bnx2x *bp) 10933 { 10934 u32 val, val2, val3, val4, id, boot_mode; 10935 u16 pmc; 10936 10937 /* Get the chip revision id and number. */ 10938 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 10939 val = REG_RD(bp, MISC_REG_CHIP_NUM); 10940 id = ((val & 0xffff) << 16); 10941 val = REG_RD(bp, MISC_REG_CHIP_REV); 10942 id |= ((val & 0xf) << 12); 10943 10944 /* Metal is read from PCI regs, but we can't access >=0x400 from 10945 * the configuration space (so we need to reg_rd) 10946 */ 10947 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); 10948 id |= (((val >> 24) & 0xf) << 4); 10949 val = REG_RD(bp, MISC_REG_BOND_ID); 10950 id |= (val & 0xf); 10951 bp->common.chip_id = id; 10952 10953 /* force 57811 according to MISC register */ 10954 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 10955 if (CHIP_IS_57810(bp)) 10956 bp->common.chip_id = (CHIP_NUM_57811 << 16) | 10957 (bp->common.chip_id & 0x0000FFFF); 10958 else if (CHIP_IS_57810_MF(bp)) 10959 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | 10960 (bp->common.chip_id & 0x0000FFFF); 10961 bp->common.chip_id |= 0x1; 10962 } 10963 10964 /* Set doorbell size */ 10965 bp->db_size = (1 << BNX2X_DB_SHIFT); 10966 10967 if (!CHIP_IS_E1x(bp)) { 10968 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 10969 if ((val & 1) == 0) 10970 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 10971 else 10972 val = (val >> 1) & 1; 10973 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 10974 "2_PORT_MODE"); 10975 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 10976 CHIP_2_PORT_MODE; 10977 10978 if (CHIP_MODE_IS_4_PORT(bp)) 10979 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 10980 else 10981 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 10982 } else { 10983 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 10984 bp->pfid = bp->pf_num; /* 0..7 */ 10985 } 10986 10987 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); 10988 10989 bp->link_params.chip_id = bp->common.chip_id; 10990 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 10991 10992 val = (REG_RD(bp, 0x2874) & 0x55); 10993 if ((bp->common.chip_id & 0x1) || 10994 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 10995 bp->flags |= ONE_PORT_FLAG; 10996 BNX2X_DEV_INFO("single port device\n"); 10997 } 10998 10999 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 11000 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 11001 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 11002 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 11003 bp->common.flash_size, bp->common.flash_size); 11004 11005 bnx2x_init_shmem(bp); 11006 11007 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 11008 MISC_REG_GENERIC_CR_1 : 11009 MISC_REG_GENERIC_CR_0)); 11010 11011 bp->link_params.shmem_base = bp->common.shmem_base; 11012 bp->link_params.shmem2_base = bp->common.shmem2_base; 11013 if (SHMEM2_RD(bp, size) > 11014 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 11015 bp->link_params.lfa_base = 11016 REG_RD(bp, bp->common.shmem2_base + 11017 (u32)offsetof(struct shmem2_region, 11018 lfa_host_addr[BP_PORT(bp)])); 11019 else 11020 bp->link_params.lfa_base = 0; 11021 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 11022 bp->common.shmem_base, bp->common.shmem2_base); 11023 11024 if (!bp->common.shmem_base) { 11025 BNX2X_DEV_INFO("MCP not active\n"); 11026 bp->flags |= NO_MCP_FLAG; 11027 return; 11028 } 11029 11030 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 11031 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 11032 11033 bp->link_params.hw_led_mode = ((bp->common.hw_config & 11034 SHARED_HW_CFG_LED_MODE_MASK) >> 11035 SHARED_HW_CFG_LED_MODE_SHIFT); 11036 11037 bp->link_params.feature_config_flags = 0; 11038 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 11039 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 11040 bp->link_params.feature_config_flags |= 11041 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 11042 else 11043 bp->link_params.feature_config_flags &= 11044 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 11045 11046 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 11047 bp->common.bc_ver = val; 11048 BNX2X_DEV_INFO("bc_ver %X\n", val); 11049 if (val < BNX2X_BC_VER) { 11050 /* for now only warn 11051 * later we might need to enforce this */ 11052 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", 11053 BNX2X_BC_VER, val); 11054 } 11055 bp->link_params.feature_config_flags |= 11056 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 11057 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 11058 11059 bp->link_params.feature_config_flags |= 11060 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 11061 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 11062 bp->link_params.feature_config_flags |= 11063 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? 11064 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; 11065 bp->link_params.feature_config_flags |= 11066 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 11067 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 11068 11069 bp->link_params.feature_config_flags |= 11070 (val >= REQ_BC_VER_4_MT_SUPPORTED) ? 11071 FEATURE_CONFIG_MT_SUPPORT : 0; 11072 11073 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 11074 BC_SUPPORTS_PFC_STATS : 0; 11075 11076 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? 11077 BC_SUPPORTS_FCOE_FEATURES : 0; 11078 11079 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? 11080 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; 11081 11082 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? 11083 BC_SUPPORTS_RMMOD_CMD : 0; 11084 11085 boot_mode = SHMEM_RD(bp, 11086 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 11087 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 11088 switch (boot_mode) { 11089 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 11090 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 11091 break; 11092 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 11093 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 11094 break; 11095 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 11096 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 11097 break; 11098 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 11099 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 11100 break; 11101 } 11102 11103 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); 11104 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 11105 11106 BNX2X_DEV_INFO("%sWoL capable\n", 11107 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 11108 11109 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 11110 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 11111 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 11112 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 11113 11114 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 11115 val, val2, val3, val4); 11116 } 11117 11118 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 11119 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 11120 11121 static int bnx2x_get_igu_cam_info(struct bnx2x *bp) 11122 { 11123 int pfid = BP_FUNC(bp); 11124 int igu_sb_id; 11125 u32 val; 11126 u8 fid, igu_sb_cnt = 0; 11127 11128 bp->igu_base_sb = 0xff; 11129 if (CHIP_INT_MODE_IS_BC(bp)) { 11130 int vn = BP_VN(bp); 11131 igu_sb_cnt = bp->igu_sb_cnt; 11132 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 11133 FP_SB_MAX_E1x; 11134 11135 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 11136 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 11137 11138 return 0; 11139 } 11140 11141 /* IGU in normal mode - read CAM */ 11142 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 11143 igu_sb_id++) { 11144 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 11145 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 11146 continue; 11147 fid = IGU_FID(val); 11148 if ((fid & IGU_FID_ENCODE_IS_PF)) { 11149 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 11150 continue; 11151 if (IGU_VEC(val) == 0) 11152 /* default status block */ 11153 bp->igu_dsb_id = igu_sb_id; 11154 else { 11155 if (bp->igu_base_sb == 0xff) 11156 bp->igu_base_sb = igu_sb_id; 11157 igu_sb_cnt++; 11158 } 11159 } 11160 } 11161 11162 #ifdef CONFIG_PCI_MSI 11163 /* Due to new PF resource allocation by MFW T7.4 and above, it's 11164 * optional that number of CAM entries will not be equal to the value 11165 * advertised in PCI. 11166 * Driver should use the minimal value of both as the actual status 11167 * block count 11168 */ 11169 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); 11170 #endif 11171 11172 if (igu_sb_cnt == 0) { 11173 BNX2X_ERR("CAM configuration error\n"); 11174 return -EINVAL; 11175 } 11176 11177 return 0; 11178 } 11179 11180 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) 11181 { 11182 int cfg_size = 0, idx, port = BP_PORT(bp); 11183 11184 /* Aggregation of supported attributes of all external phys */ 11185 bp->port.supported[0] = 0; 11186 bp->port.supported[1] = 0; 11187 switch (bp->link_params.num_phys) { 11188 case 1: 11189 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 11190 cfg_size = 1; 11191 break; 11192 case 2: 11193 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 11194 cfg_size = 1; 11195 break; 11196 case 3: 11197 if (bp->link_params.multi_phy_config & 11198 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 11199 bp->port.supported[1] = 11200 bp->link_params.phy[EXT_PHY1].supported; 11201 bp->port.supported[0] = 11202 bp->link_params.phy[EXT_PHY2].supported; 11203 } else { 11204 bp->port.supported[0] = 11205 bp->link_params.phy[EXT_PHY1].supported; 11206 bp->port.supported[1] = 11207 bp->link_params.phy[EXT_PHY2].supported; 11208 } 11209 cfg_size = 2; 11210 break; 11211 } 11212 11213 if (!(bp->port.supported[0] || bp->port.supported[1])) { 11214 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", 11215 SHMEM_RD(bp, 11216 dev_info.port_hw_config[port].external_phy_config), 11217 SHMEM_RD(bp, 11218 dev_info.port_hw_config[port].external_phy_config2)); 11219 return; 11220 } 11221 11222 if (CHIP_IS_E3(bp)) 11223 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 11224 else { 11225 switch (switch_cfg) { 11226 case SWITCH_CFG_1G: 11227 bp->port.phy_addr = REG_RD( 11228 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 11229 break; 11230 case SWITCH_CFG_10G: 11231 bp->port.phy_addr = REG_RD( 11232 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 11233 break; 11234 default: 11235 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 11236 bp->port.link_config[0]); 11237 return; 11238 } 11239 } 11240 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 11241 /* mask what we support according to speed_cap_mask per configuration */ 11242 for (idx = 0; idx < cfg_size; idx++) { 11243 if (!(bp->link_params.speed_cap_mask[idx] & 11244 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 11245 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 11246 11247 if (!(bp->link_params.speed_cap_mask[idx] & 11248 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 11249 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 11250 11251 if (!(bp->link_params.speed_cap_mask[idx] & 11252 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 11253 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 11254 11255 if (!(bp->link_params.speed_cap_mask[idx] & 11256 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 11257 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 11258 11259 if (!(bp->link_params.speed_cap_mask[idx] & 11260 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 11261 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 11262 SUPPORTED_1000baseT_Full); 11263 11264 if (!(bp->link_params.speed_cap_mask[idx] & 11265 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 11266 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 11267 11268 if (!(bp->link_params.speed_cap_mask[idx] & 11269 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 11270 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 11271 11272 if (!(bp->link_params.speed_cap_mask[idx] & 11273 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 11274 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; 11275 } 11276 11277 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 11278 bp->port.supported[1]); 11279 } 11280 11281 static void bnx2x_link_settings_requested(struct bnx2x *bp) 11282 { 11283 u32 link_config, idx, cfg_size = 0; 11284 bp->port.advertising[0] = 0; 11285 bp->port.advertising[1] = 0; 11286 switch (bp->link_params.num_phys) { 11287 case 1: 11288 case 2: 11289 cfg_size = 1; 11290 break; 11291 case 3: 11292 cfg_size = 2; 11293 break; 11294 } 11295 for (idx = 0; idx < cfg_size; idx++) { 11296 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 11297 link_config = bp->port.link_config[idx]; 11298 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 11299 case PORT_FEATURE_LINK_SPEED_AUTO: 11300 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 11301 bp->link_params.req_line_speed[idx] = 11302 SPEED_AUTO_NEG; 11303 bp->port.advertising[idx] |= 11304 bp->port.supported[idx]; 11305 if (bp->link_params.phy[EXT_PHY1].type == 11306 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 11307 bp->port.advertising[idx] |= 11308 (SUPPORTED_100baseT_Half | 11309 SUPPORTED_100baseT_Full); 11310 } else { 11311 /* force 10G, no AN */ 11312 bp->link_params.req_line_speed[idx] = 11313 SPEED_10000; 11314 bp->port.advertising[idx] |= 11315 (ADVERTISED_10000baseT_Full | 11316 ADVERTISED_FIBRE); 11317 continue; 11318 } 11319 break; 11320 11321 case PORT_FEATURE_LINK_SPEED_10M_FULL: 11322 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 11323 bp->link_params.req_line_speed[idx] = 11324 SPEED_10; 11325 bp->port.advertising[idx] |= 11326 (ADVERTISED_10baseT_Full | 11327 ADVERTISED_TP); 11328 } else { 11329 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11330 link_config, 11331 bp->link_params.speed_cap_mask[idx]); 11332 return; 11333 } 11334 break; 11335 11336 case PORT_FEATURE_LINK_SPEED_10M_HALF: 11337 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 11338 bp->link_params.req_line_speed[idx] = 11339 SPEED_10; 11340 bp->link_params.req_duplex[idx] = 11341 DUPLEX_HALF; 11342 bp->port.advertising[idx] |= 11343 (ADVERTISED_10baseT_Half | 11344 ADVERTISED_TP); 11345 } else { 11346 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11347 link_config, 11348 bp->link_params.speed_cap_mask[idx]); 11349 return; 11350 } 11351 break; 11352 11353 case PORT_FEATURE_LINK_SPEED_100M_FULL: 11354 if (bp->port.supported[idx] & 11355 SUPPORTED_100baseT_Full) { 11356 bp->link_params.req_line_speed[idx] = 11357 SPEED_100; 11358 bp->port.advertising[idx] |= 11359 (ADVERTISED_100baseT_Full | 11360 ADVERTISED_TP); 11361 } else { 11362 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11363 link_config, 11364 bp->link_params.speed_cap_mask[idx]); 11365 return; 11366 } 11367 break; 11368 11369 case PORT_FEATURE_LINK_SPEED_100M_HALF: 11370 if (bp->port.supported[idx] & 11371 SUPPORTED_100baseT_Half) { 11372 bp->link_params.req_line_speed[idx] = 11373 SPEED_100; 11374 bp->link_params.req_duplex[idx] = 11375 DUPLEX_HALF; 11376 bp->port.advertising[idx] |= 11377 (ADVERTISED_100baseT_Half | 11378 ADVERTISED_TP); 11379 } else { 11380 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11381 link_config, 11382 bp->link_params.speed_cap_mask[idx]); 11383 return; 11384 } 11385 break; 11386 11387 case PORT_FEATURE_LINK_SPEED_1G: 11388 if (bp->port.supported[idx] & 11389 SUPPORTED_1000baseT_Full) { 11390 bp->link_params.req_line_speed[idx] = 11391 SPEED_1000; 11392 bp->port.advertising[idx] |= 11393 (ADVERTISED_1000baseT_Full | 11394 ADVERTISED_TP); 11395 } else if (bp->port.supported[idx] & 11396 SUPPORTED_1000baseKX_Full) { 11397 bp->link_params.req_line_speed[idx] = 11398 SPEED_1000; 11399 bp->port.advertising[idx] |= 11400 ADVERTISED_1000baseKX_Full; 11401 } else { 11402 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11403 link_config, 11404 bp->link_params.speed_cap_mask[idx]); 11405 return; 11406 } 11407 break; 11408 11409 case PORT_FEATURE_LINK_SPEED_2_5G: 11410 if (bp->port.supported[idx] & 11411 SUPPORTED_2500baseX_Full) { 11412 bp->link_params.req_line_speed[idx] = 11413 SPEED_2500; 11414 bp->port.advertising[idx] |= 11415 (ADVERTISED_2500baseX_Full | 11416 ADVERTISED_TP); 11417 } else { 11418 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11419 link_config, 11420 bp->link_params.speed_cap_mask[idx]); 11421 return; 11422 } 11423 break; 11424 11425 case PORT_FEATURE_LINK_SPEED_10G_CX4: 11426 if (bp->port.supported[idx] & 11427 SUPPORTED_10000baseT_Full) { 11428 bp->link_params.req_line_speed[idx] = 11429 SPEED_10000; 11430 bp->port.advertising[idx] |= 11431 (ADVERTISED_10000baseT_Full | 11432 ADVERTISED_FIBRE); 11433 } else if (bp->port.supported[idx] & 11434 SUPPORTED_10000baseKR_Full) { 11435 bp->link_params.req_line_speed[idx] = 11436 SPEED_10000; 11437 bp->port.advertising[idx] |= 11438 (ADVERTISED_10000baseKR_Full | 11439 ADVERTISED_FIBRE); 11440 } else { 11441 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11442 link_config, 11443 bp->link_params.speed_cap_mask[idx]); 11444 return; 11445 } 11446 break; 11447 case PORT_FEATURE_LINK_SPEED_20G: 11448 bp->link_params.req_line_speed[idx] = SPEED_20000; 11449 11450 break; 11451 default: 11452 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", 11453 link_config); 11454 bp->link_params.req_line_speed[idx] = 11455 SPEED_AUTO_NEG; 11456 bp->port.advertising[idx] = 11457 bp->port.supported[idx]; 11458 break; 11459 } 11460 11461 bp->link_params.req_flow_ctrl[idx] = (link_config & 11462 PORT_FEATURE_FLOW_CONTROL_MASK); 11463 if (bp->link_params.req_flow_ctrl[idx] == 11464 BNX2X_FLOW_CTRL_AUTO) { 11465 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) 11466 bp->link_params.req_flow_ctrl[idx] = 11467 BNX2X_FLOW_CTRL_NONE; 11468 else 11469 bnx2x_set_requested_fc(bp); 11470 } 11471 11472 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", 11473 bp->link_params.req_line_speed[idx], 11474 bp->link_params.req_duplex[idx], 11475 bp->link_params.req_flow_ctrl[idx], 11476 bp->port.advertising[idx]); 11477 } 11478 } 11479 11480 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 11481 { 11482 __be16 mac_hi_be = cpu_to_be16(mac_hi); 11483 __be32 mac_lo_be = cpu_to_be32(mac_lo); 11484 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); 11485 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); 11486 } 11487 11488 static void bnx2x_get_port_hwinfo(struct bnx2x *bp) 11489 { 11490 int port = BP_PORT(bp); 11491 u32 config; 11492 u32 ext_phy_type, ext_phy_config, eee_mode; 11493 11494 bp->link_params.bp = bp; 11495 bp->link_params.port = port; 11496 11497 bp->link_params.lane_config = 11498 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 11499 11500 bp->link_params.speed_cap_mask[0] = 11501 SHMEM_RD(bp, 11502 dev_info.port_hw_config[port].speed_capability_mask) & 11503 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 11504 bp->link_params.speed_cap_mask[1] = 11505 SHMEM_RD(bp, 11506 dev_info.port_hw_config[port].speed_capability_mask2) & 11507 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 11508 bp->port.link_config[0] = 11509 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 11510 11511 bp->port.link_config[1] = 11512 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 11513 11514 bp->link_params.multi_phy_config = 11515 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 11516 /* If the device is capable of WoL, set the default state according 11517 * to the HW 11518 */ 11519 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 11520 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 11521 (config & PORT_FEATURE_WOL_ENABLED)); 11522 11523 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 11524 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) 11525 bp->flags |= NO_ISCSI_FLAG; 11526 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 11527 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) 11528 bp->flags |= NO_FCOE_FLAG; 11529 11530 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", 11531 bp->link_params.lane_config, 11532 bp->link_params.speed_cap_mask[0], 11533 bp->port.link_config[0]); 11534 11535 bp->link_params.switch_cfg = (bp->port.link_config[0] & 11536 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11537 bnx2x_phy_probe(&bp->link_params); 11538 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 11539 11540 bnx2x_link_settings_requested(bp); 11541 11542 /* 11543 * If connected directly, work with the internal PHY, otherwise, work 11544 * with the external PHY 11545 */ 11546 ext_phy_config = 11547 SHMEM_RD(bp, 11548 dev_info.port_hw_config[port].external_phy_config); 11549 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 11550 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 11551 bp->mdio.prtad = bp->port.phy_addr; 11552 11553 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 11554 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 11555 bp->mdio.prtad = 11556 XGXS_EXT_PHY_ADDR(ext_phy_config); 11557 11558 /* Configure link feature according to nvram value */ 11559 eee_mode = (((SHMEM_RD(bp, dev_info. 11560 port_feature_config[port].eee_power_mode)) & 11561 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 11562 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 11563 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 11564 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | 11565 EEE_MODE_ENABLE_LPI | 11566 EEE_MODE_OUTPUT_TIME; 11567 } else { 11568 bp->link_params.eee_mode = 0; 11569 } 11570 } 11571 11572 void bnx2x_get_iscsi_info(struct bnx2x *bp) 11573 { 11574 u32 no_flags = NO_ISCSI_FLAG; 11575 int port = BP_PORT(bp); 11576 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 11577 drv_lic_key[port].max_iscsi_conn); 11578 11579 if (!CNIC_SUPPORT(bp)) { 11580 bp->flags |= no_flags; 11581 return; 11582 } 11583 11584 /* Get the number of maximum allowed iSCSI connections */ 11585 bp->cnic_eth_dev.max_iscsi_conn = 11586 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 11587 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 11588 11589 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 11590 bp->cnic_eth_dev.max_iscsi_conn); 11591 11592 /* 11593 * If maximum allowed number of connections is zero - 11594 * disable the feature. 11595 */ 11596 if (!bp->cnic_eth_dev.max_iscsi_conn) 11597 bp->flags |= no_flags; 11598 } 11599 11600 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) 11601 { 11602 /* Port info */ 11603 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 11604 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); 11605 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 11606 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); 11607 11608 /* Node info */ 11609 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 11610 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); 11611 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 11612 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); 11613 } 11614 11615 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) 11616 { 11617 u8 count = 0; 11618 11619 if (IS_MF(bp)) { 11620 u8 fid; 11621 11622 /* iterate over absolute function ids for this path: */ 11623 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { 11624 if (IS_MF_SD(bp)) { 11625 u32 cfg = MF_CFG_RD(bp, 11626 func_mf_config[fid].config); 11627 11628 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && 11629 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == 11630 FUNC_MF_CFG_PROTOCOL_FCOE)) 11631 count++; 11632 } else { 11633 u32 cfg = MF_CFG_RD(bp, 11634 func_ext_config[fid]. 11635 func_cfg); 11636 11637 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && 11638 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) 11639 count++; 11640 } 11641 } 11642 } else { /* SF */ 11643 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; 11644 11645 for (port = 0; port < port_cnt; port++) { 11646 u32 lic = SHMEM_RD(bp, 11647 drv_lic_key[port].max_fcoe_conn) ^ 11648 FW_ENCODE_32BIT_PATTERN; 11649 if (lic) 11650 count++; 11651 } 11652 } 11653 11654 return count; 11655 } 11656 11657 static void bnx2x_get_fcoe_info(struct bnx2x *bp) 11658 { 11659 int port = BP_PORT(bp); 11660 int func = BP_ABS_FUNC(bp); 11661 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 11662 drv_lic_key[port].max_fcoe_conn); 11663 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); 11664 11665 if (!CNIC_SUPPORT(bp)) { 11666 bp->flags |= NO_FCOE_FLAG; 11667 return; 11668 } 11669 11670 /* Get the number of maximum allowed FCoE connections */ 11671 bp->cnic_eth_dev.max_fcoe_conn = 11672 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 11673 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 11674 11675 /* Calculate the number of maximum allowed FCoE tasks */ 11676 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; 11677 11678 /* check if FCoE resources must be shared between different functions */ 11679 if (num_fcoe_func) 11680 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; 11681 11682 /* Read the WWN: */ 11683 if (!IS_MF(bp)) { 11684 /* Port info */ 11685 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 11686 SHMEM_RD(bp, 11687 dev_info.port_hw_config[port]. 11688 fcoe_wwn_port_name_upper); 11689 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 11690 SHMEM_RD(bp, 11691 dev_info.port_hw_config[port]. 11692 fcoe_wwn_port_name_lower); 11693 11694 /* Node info */ 11695 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 11696 SHMEM_RD(bp, 11697 dev_info.port_hw_config[port]. 11698 fcoe_wwn_node_name_upper); 11699 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 11700 SHMEM_RD(bp, 11701 dev_info.port_hw_config[port]. 11702 fcoe_wwn_node_name_lower); 11703 } else if (!IS_MF_SD(bp)) { 11704 /* Read the WWN info only if the FCoE feature is enabled for 11705 * this function. 11706 */ 11707 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) 11708 bnx2x_get_ext_wwn_info(bp, func); 11709 } else { 11710 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) 11711 bnx2x_get_ext_wwn_info(bp, func); 11712 } 11713 11714 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 11715 11716 /* 11717 * If maximum allowed number of connections is zero - 11718 * disable the feature. 11719 */ 11720 if (!bp->cnic_eth_dev.max_fcoe_conn) { 11721 bp->flags |= NO_FCOE_FLAG; 11722 eth_zero_addr(bp->fip_mac); 11723 } 11724 } 11725 11726 static void bnx2x_get_cnic_info(struct bnx2x *bp) 11727 { 11728 /* 11729 * iSCSI may be dynamically disabled but reading 11730 * info here we will decrease memory usage by driver 11731 * if the feature is disabled for good 11732 */ 11733 bnx2x_get_iscsi_info(bp); 11734 bnx2x_get_fcoe_info(bp); 11735 } 11736 11737 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) 11738 { 11739 u32 val, val2; 11740 int func = BP_ABS_FUNC(bp); 11741 int port = BP_PORT(bp); 11742 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 11743 u8 *fip_mac = bp->fip_mac; 11744 11745 if (IS_MF(bp)) { 11746 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 11747 * FCoE MAC then the appropriate feature should be disabled. 11748 * In non SD mode features configuration comes from struct 11749 * func_ext_config. 11750 */ 11751 if (!IS_MF_SD(bp)) { 11752 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 11753 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 11754 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11755 iscsi_mac_addr_upper); 11756 val = MF_CFG_RD(bp, func_ext_config[func]. 11757 iscsi_mac_addr_lower); 11758 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11759 BNX2X_DEV_INFO 11760 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11761 } else { 11762 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11763 } 11764 11765 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 11766 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11767 fcoe_mac_addr_upper); 11768 val = MF_CFG_RD(bp, func_ext_config[func]. 11769 fcoe_mac_addr_lower); 11770 bnx2x_set_mac_buf(fip_mac, val, val2); 11771 BNX2X_DEV_INFO 11772 ("Read FCoE L2 MAC: %pM\n", fip_mac); 11773 } else { 11774 bp->flags |= NO_FCOE_FLAG; 11775 } 11776 11777 bp->mf_ext_config = cfg; 11778 11779 } else { /* SD MODE */ 11780 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { 11781 /* use primary mac as iscsi mac */ 11782 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 11783 11784 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 11785 BNX2X_DEV_INFO 11786 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11787 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { 11788 /* use primary mac as fip mac */ 11789 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 11790 BNX2X_DEV_INFO("SD FCoE MODE\n"); 11791 BNX2X_DEV_INFO 11792 ("Read FIP MAC: %pM\n", fip_mac); 11793 } 11794 } 11795 11796 /* If this is a storage-only interface, use SAN mac as 11797 * primary MAC. Notice that for SD this is already the case, 11798 * as the SAN mac was copied from the primary MAC. 11799 */ 11800 if (IS_MF_FCOE_AFEX(bp)) 11801 eth_hw_addr_set(bp->dev, fip_mac); 11802 } else { 11803 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11804 iscsi_mac_upper); 11805 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11806 iscsi_mac_lower); 11807 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11808 11809 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11810 fcoe_fip_mac_upper); 11811 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11812 fcoe_fip_mac_lower); 11813 bnx2x_set_mac_buf(fip_mac, val, val2); 11814 } 11815 11816 /* Disable iSCSI OOO if MAC configuration is invalid. */ 11817 if (!is_valid_ether_addr(iscsi_mac)) { 11818 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11819 eth_zero_addr(iscsi_mac); 11820 } 11821 11822 /* Disable FCoE if MAC configuration is invalid. */ 11823 if (!is_valid_ether_addr(fip_mac)) { 11824 bp->flags |= NO_FCOE_FLAG; 11825 eth_zero_addr(bp->fip_mac); 11826 } 11827 } 11828 11829 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) 11830 { 11831 u32 val, val2; 11832 int func = BP_ABS_FUNC(bp); 11833 int port = BP_PORT(bp); 11834 u8 addr[ETH_ALEN] = {}; 11835 11836 /* Zero primary MAC configuration */ 11837 eth_hw_addr_set(bp->dev, addr); 11838 11839 if (BP_NOMCP(bp)) { 11840 BNX2X_ERROR("warning: random MAC workaround active\n"); 11841 eth_hw_addr_random(bp->dev); 11842 } else if (IS_MF(bp)) { 11843 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 11844 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 11845 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 11846 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) { 11847 bnx2x_set_mac_buf(addr, val, val2); 11848 eth_hw_addr_set(bp->dev, addr); 11849 } 11850 11851 if (CNIC_SUPPORT(bp)) 11852 bnx2x_get_cnic_mac_hwinfo(bp); 11853 } else { 11854 /* in SF read MACs from port configuration */ 11855 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 11856 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 11857 bnx2x_set_mac_buf(addr, val, val2); 11858 eth_hw_addr_set(bp->dev, addr); 11859 11860 if (CNIC_SUPPORT(bp)) 11861 bnx2x_get_cnic_mac_hwinfo(bp); 11862 } 11863 11864 if (!BP_NOMCP(bp)) { 11865 /* Read physical port identifier from shmem */ 11866 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 11867 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 11868 bnx2x_set_mac_buf(bp->phys_port_id, val, val2); 11869 bp->flags |= HAS_PHYS_PORT_ID; 11870 } 11871 11872 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 11873 11874 if (!is_valid_ether_addr(bp->dev->dev_addr)) 11875 dev_err(&bp->pdev->dev, 11876 "bad Ethernet MAC address configuration: %pM\n" 11877 "change it manually before bringing up the appropriate network interface\n", 11878 bp->dev->dev_addr); 11879 } 11880 11881 static bool bnx2x_get_dropless_info(struct bnx2x *bp) 11882 { 11883 int tmp; 11884 u32 cfg; 11885 11886 if (IS_VF(bp)) 11887 return false; 11888 11889 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { 11890 /* Take function: tmp = func */ 11891 tmp = BP_ABS_FUNC(bp); 11892 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); 11893 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); 11894 } else { 11895 /* Take port: tmp = port */ 11896 tmp = BP_PORT(bp); 11897 cfg = SHMEM_RD(bp, 11898 dev_info.port_hw_config[tmp].generic_features); 11899 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); 11900 } 11901 return cfg; 11902 } 11903 11904 static void validate_set_si_mode(struct bnx2x *bp) 11905 { 11906 u8 func = BP_ABS_FUNC(bp); 11907 u32 val; 11908 11909 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 11910 11911 /* check for legal mac (upper bytes) */ 11912 if (val != 0xffff) { 11913 bp->mf_mode = MULTI_FUNCTION_SI; 11914 bp->mf_config[BP_VN(bp)] = 11915 MF_CFG_RD(bp, func_mf_config[func].config); 11916 } else 11917 BNX2X_DEV_INFO("illegal MAC address for SI\n"); 11918 } 11919 11920 static int bnx2x_get_hwinfo(struct bnx2x *bp) 11921 { 11922 int /*abs*/func = BP_ABS_FUNC(bp); 11923 int vn; 11924 u32 val = 0, val2 = 0; 11925 int rc = 0; 11926 11927 /* Validate that chip access is feasible */ 11928 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { 11929 dev_err(&bp->pdev->dev, 11930 "Chip read returns all Fs. Preventing probe from continuing\n"); 11931 return -EINVAL; 11932 } 11933 11934 bnx2x_get_common_hwinfo(bp); 11935 11936 /* 11937 * initialize IGU parameters 11938 */ 11939 if (CHIP_IS_E1x(bp)) { 11940 bp->common.int_block = INT_BLOCK_HC; 11941 11942 bp->igu_dsb_id = DEF_SB_IGU_ID; 11943 bp->igu_base_sb = 0; 11944 } else { 11945 bp->common.int_block = INT_BLOCK_IGU; 11946 11947 /* do not allow device reset during IGU info processing */ 11948 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11949 11950 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 11951 11952 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11953 int tout = 5000; 11954 11955 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 11956 11957 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 11958 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 11959 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 11960 11961 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11962 tout--; 11963 usleep_range(1000, 2000); 11964 } 11965 11966 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11967 dev_err(&bp->pdev->dev, 11968 "FORCING Normal Mode failed!!!\n"); 11969 bnx2x_release_hw_lock(bp, 11970 HW_LOCK_RESOURCE_RESET); 11971 return -EPERM; 11972 } 11973 } 11974 11975 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11976 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 11977 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 11978 } else 11979 BNX2X_DEV_INFO("IGU Normal Mode\n"); 11980 11981 rc = bnx2x_get_igu_cam_info(bp); 11982 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11983 if (rc) 11984 return rc; 11985 } 11986 11987 /* 11988 * set base FW non-default (fast path) status block id, this value is 11989 * used to initialize the fw_sb_id saved on the fp/queue structure to 11990 * determine the id used by the FW. 11991 */ 11992 if (CHIP_IS_E1x(bp)) 11993 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 11994 else /* 11995 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 11996 * the same queue are indicated on the same IGU SB). So we prefer 11997 * FW and IGU SBs to be the same value. 11998 */ 11999 bp->base_fw_ndsb = bp->igu_base_sb; 12000 12001 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 12002 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 12003 bp->igu_sb_cnt, bp->base_fw_ndsb); 12004 12005 /* 12006 * Initialize MF configuration 12007 */ 12008 bp->mf_ov = 0; 12009 bp->mf_mode = 0; 12010 bp->mf_sub_mode = 0; 12011 vn = BP_VN(bp); 12012 12013 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 12014 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 12015 bp->common.shmem2_base, SHMEM2_RD(bp, size), 12016 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 12017 12018 if (SHMEM2_HAS(bp, mf_cfg_addr)) 12019 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 12020 else 12021 bp->common.mf_cfg_base = bp->common.shmem_base + 12022 offsetof(struct shmem_region, func_mb) + 12023 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 12024 /* 12025 * get mf configuration: 12026 * 1. Existence of MF configuration 12027 * 2. MAC address must be legal (check only upper bytes) 12028 * for Switch-Independent mode; 12029 * OVLAN must be legal for Switch-Dependent mode 12030 * 3. SF_MODE configures specific MF mode 12031 */ 12032 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 12033 /* get mf configuration */ 12034 val = SHMEM_RD(bp, 12035 dev_info.shared_feature_config.config); 12036 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 12037 12038 switch (val) { 12039 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 12040 validate_set_si_mode(bp); 12041 break; 12042 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 12043 if ((!CHIP_IS_E1x(bp)) && 12044 (MF_CFG_RD(bp, func_mf_config[func]. 12045 mac_upper) != 0xffff) && 12046 (SHMEM2_HAS(bp, 12047 afex_driver_support))) { 12048 bp->mf_mode = MULTI_FUNCTION_AFEX; 12049 bp->mf_config[vn] = MF_CFG_RD(bp, 12050 func_mf_config[func].config); 12051 } else { 12052 BNX2X_DEV_INFO("can not configure afex mode\n"); 12053 } 12054 break; 12055 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 12056 /* get OV configuration */ 12057 val = MF_CFG_RD(bp, 12058 func_mf_config[FUNC_0].e1hov_tag); 12059 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 12060 12061 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 12062 bp->mf_mode = MULTI_FUNCTION_SD; 12063 bp->mf_config[vn] = MF_CFG_RD(bp, 12064 func_mf_config[func].config); 12065 } else 12066 BNX2X_DEV_INFO("illegal OV for SD\n"); 12067 break; 12068 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE: 12069 bp->mf_mode = MULTI_FUNCTION_SD; 12070 bp->mf_sub_mode = SUB_MF_MODE_BD; 12071 bp->mf_config[vn] = 12072 MF_CFG_RD(bp, 12073 func_mf_config[func].config); 12074 12075 if (SHMEM2_HAS(bp, mtu_size)) { 12076 int mtu_idx = BP_FW_MB_IDX(bp); 12077 u16 mtu_size; 12078 u32 mtu; 12079 12080 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); 12081 mtu_size = (u16)mtu; 12082 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n", 12083 mtu_size, mtu); 12084 12085 /* if valid: update device mtu */ 12086 if ((mtu_size >= ETH_MIN_PACKET_SIZE) && 12087 (mtu_size <= 12088 ETH_MAX_JUMBO_PACKET_SIZE)) 12089 bp->dev->mtu = mtu_size; 12090 } 12091 break; 12092 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE: 12093 bp->mf_mode = MULTI_FUNCTION_SD; 12094 bp->mf_sub_mode = SUB_MF_MODE_UFP; 12095 bp->mf_config[vn] = 12096 MF_CFG_RD(bp, 12097 func_mf_config[func].config); 12098 break; 12099 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: 12100 bp->mf_config[vn] = 0; 12101 break; 12102 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE: 12103 val2 = SHMEM_RD(bp, 12104 dev_info.shared_hw_config.config_3); 12105 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK; 12106 switch (val2) { 12107 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5: 12108 validate_set_si_mode(bp); 12109 bp->mf_sub_mode = 12110 SUB_MF_MODE_NPAR1_DOT_5; 12111 break; 12112 default: 12113 /* Unknown configuration */ 12114 bp->mf_config[vn] = 0; 12115 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", 12116 val); 12117 } 12118 break; 12119 default: 12120 /* Unknown configuration: reset mf_config */ 12121 bp->mf_config[vn] = 0; 12122 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); 12123 } 12124 } 12125 12126 BNX2X_DEV_INFO("%s function mode\n", 12127 IS_MF(bp) ? "multi" : "single"); 12128 12129 switch (bp->mf_mode) { 12130 case MULTI_FUNCTION_SD: 12131 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 12132 FUNC_MF_CFG_E1HOV_TAG_MASK; 12133 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 12134 bp->mf_ov = val; 12135 bp->path_has_ovlan = true; 12136 12137 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", 12138 func, bp->mf_ov, bp->mf_ov); 12139 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || 12140 (bp->mf_sub_mode == SUB_MF_MODE_BD)) { 12141 dev_err(&bp->pdev->dev, 12142 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n", 12143 func); 12144 bp->path_has_ovlan = true; 12145 } else { 12146 dev_err(&bp->pdev->dev, 12147 "No valid MF OV for func %d, aborting\n", 12148 func); 12149 return -EPERM; 12150 } 12151 break; 12152 case MULTI_FUNCTION_AFEX: 12153 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); 12154 break; 12155 case MULTI_FUNCTION_SI: 12156 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", 12157 func); 12158 break; 12159 default: 12160 if (vn) { 12161 dev_err(&bp->pdev->dev, 12162 "VN %d is in a single function mode, aborting\n", 12163 vn); 12164 return -EPERM; 12165 } 12166 break; 12167 } 12168 12169 /* check if other port on the path needs ovlan: 12170 * Since MF configuration is shared between ports 12171 * Possible mixed modes are only 12172 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 12173 */ 12174 if (CHIP_MODE_IS_4_PORT(bp) && 12175 !bp->path_has_ovlan && 12176 !IS_MF(bp) && 12177 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 12178 u8 other_port = !BP_PORT(bp); 12179 u8 other_func = BP_PATH(bp) + 2*other_port; 12180 val = MF_CFG_RD(bp, 12181 func_mf_config[other_func].e1hov_tag); 12182 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 12183 bp->path_has_ovlan = true; 12184 } 12185 } 12186 12187 /* adjust igu_sb_cnt to MF for E1H */ 12188 if (CHIP_IS_E1H(bp) && IS_MF(bp)) 12189 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); 12190 12191 /* port info */ 12192 bnx2x_get_port_hwinfo(bp); 12193 12194 /* Get MAC addresses */ 12195 bnx2x_get_mac_hwinfo(bp); 12196 12197 bnx2x_get_cnic_info(bp); 12198 12199 return rc; 12200 } 12201 12202 static void bnx2x_read_fwinfo(struct bnx2x *bp) 12203 { 12204 char str_id[VENDOR_ID_LEN + 1]; 12205 unsigned int vpd_len, kw_len; 12206 u8 *vpd_data; 12207 int rodi; 12208 12209 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 12210 12211 vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len); 12212 if (IS_ERR(vpd_data)) 12213 return; 12214 12215 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, 12216 PCI_VPD_RO_KEYWORD_MFR_ID, &kw_len); 12217 if (rodi < 0 || kw_len != VENDOR_ID_LEN) 12218 goto out_not_found; 12219 12220 /* vendor specific info */ 12221 snprintf(str_id, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 12222 if (!strncasecmp(str_id, &vpd_data[rodi], VENDOR_ID_LEN)) { 12223 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, 12224 PCI_VPD_RO_KEYWORD_VENDOR0, 12225 &kw_len); 12226 if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) { 12227 memcpy(bp->fw_ver, &vpd_data[rodi], kw_len); 12228 bp->fw_ver[kw_len] = ' '; 12229 } 12230 } 12231 out_not_found: 12232 kfree(vpd_data); 12233 } 12234 12235 static void bnx2x_set_modes_bitmap(struct bnx2x *bp) 12236 { 12237 u32 flags = 0; 12238 12239 if (CHIP_REV_IS_FPGA(bp)) 12240 SET_FLAGS(flags, MODE_FPGA); 12241 else if (CHIP_REV_IS_EMUL(bp)) 12242 SET_FLAGS(flags, MODE_EMUL); 12243 else 12244 SET_FLAGS(flags, MODE_ASIC); 12245 12246 if (CHIP_MODE_IS_4_PORT(bp)) 12247 SET_FLAGS(flags, MODE_PORT4); 12248 else 12249 SET_FLAGS(flags, MODE_PORT2); 12250 12251 if (CHIP_IS_E2(bp)) 12252 SET_FLAGS(flags, MODE_E2); 12253 else if (CHIP_IS_E3(bp)) { 12254 SET_FLAGS(flags, MODE_E3); 12255 if (CHIP_REV(bp) == CHIP_REV_Ax) 12256 SET_FLAGS(flags, MODE_E3_A0); 12257 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 12258 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 12259 } 12260 12261 if (IS_MF(bp)) { 12262 SET_FLAGS(flags, MODE_MF); 12263 switch (bp->mf_mode) { 12264 case MULTI_FUNCTION_SD: 12265 SET_FLAGS(flags, MODE_MF_SD); 12266 break; 12267 case MULTI_FUNCTION_SI: 12268 SET_FLAGS(flags, MODE_MF_SI); 12269 break; 12270 case MULTI_FUNCTION_AFEX: 12271 SET_FLAGS(flags, MODE_MF_AFEX); 12272 break; 12273 } 12274 } else 12275 SET_FLAGS(flags, MODE_SF); 12276 12277 #if defined(__LITTLE_ENDIAN) 12278 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 12279 #else /*(__BIG_ENDIAN)*/ 12280 SET_FLAGS(flags, MODE_BIG_ENDIAN); 12281 #endif 12282 INIT_MODE_FLAGS(bp) = flags; 12283 } 12284 12285 static int bnx2x_init_bp(struct bnx2x *bp) 12286 { 12287 int func; 12288 int rc; 12289 12290 mutex_init(&bp->port.phy_mutex); 12291 mutex_init(&bp->fw_mb_mutex); 12292 mutex_init(&bp->drv_info_mutex); 12293 sema_init(&bp->stats_lock, 1); 12294 bp->drv_info_mng_owner = false; 12295 INIT_LIST_HEAD(&bp->vlan_reg); 12296 12297 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 12298 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 12299 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 12300 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); 12301 if (IS_PF(bp)) { 12302 rc = bnx2x_get_hwinfo(bp); 12303 if (rc) 12304 return rc; 12305 } else { 12306 static const u8 zero_addr[ETH_ALEN] = {}; 12307 12308 eth_hw_addr_set(bp->dev, zero_addr); 12309 } 12310 12311 bnx2x_set_modes_bitmap(bp); 12312 12313 rc = bnx2x_alloc_mem_bp(bp); 12314 if (rc) 12315 return rc; 12316 12317 bnx2x_read_fwinfo(bp); 12318 12319 if (IS_PF(bp)) { 12320 rc = bnx2x_init_firmware(bp); 12321 12322 if (rc) { 12323 bnx2x_free_mem_bp(bp); 12324 return rc; 12325 } 12326 } 12327 12328 func = BP_FUNC(bp); 12329 12330 /* need to reset chip if undi was active */ 12331 if (IS_PF(bp) && !BP_NOMCP(bp)) { 12332 /* init fw_seq */ 12333 bp->fw_seq = 12334 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 12335 DRV_MSG_SEQ_NUMBER_MASK; 12336 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 12337 12338 rc = bnx2x_prev_unload(bp); 12339 if (rc) { 12340 bnx2x_release_firmware(bp); 12341 bnx2x_free_mem_bp(bp); 12342 return rc; 12343 } 12344 } 12345 12346 if (CHIP_REV_IS_FPGA(bp)) 12347 dev_err(&bp->pdev->dev, "FPGA detected\n"); 12348 12349 if (BP_NOMCP(bp) && (func == 0)) 12350 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); 12351 12352 bp->disable_tpa = disable_tpa; 12353 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); 12354 /* Reduce memory usage in kdump environment by disabling TPA */ 12355 bp->disable_tpa |= is_kdump_kernel(); 12356 12357 /* Set TPA flags */ 12358 if (bp->disable_tpa) { 12359 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 12360 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 12361 } 12362 12363 if (CHIP_IS_E1(bp)) 12364 bp->dropless_fc = false; 12365 else 12366 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); 12367 12368 bp->mrrs = mrrs; 12369 12370 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; 12371 if (IS_VF(bp)) 12372 bp->rx_ring_size = MAX_RX_AVAIL; 12373 12374 /* make sure that the numbers are in the right granularity */ 12375 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 12376 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 12377 12378 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 12379 12380 timer_setup(&bp->timer, bnx2x_timer, 0); 12381 bp->timer.expires = jiffies + bp->current_interval; 12382 12383 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && 12384 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && 12385 SHMEM2_HAS(bp, dcbx_en) && 12386 SHMEM2_RD(bp, dcbx_lldp_params_offset) && 12387 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) && 12388 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) { 12389 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 12390 bnx2x_dcbx_init_params(bp); 12391 } else { 12392 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); 12393 } 12394 12395 if (CHIP_IS_E1x(bp)) 12396 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 12397 else 12398 bp->cnic_base_cl_id = FP_SB_MAX_E2; 12399 12400 /* multiple tx priority */ 12401 if (IS_VF(bp)) 12402 bp->max_cos = 1; 12403 else if (CHIP_IS_E1x(bp)) 12404 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 12405 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 12406 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 12407 else if (CHIP_IS_E3B0(bp)) 12408 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 12409 else 12410 BNX2X_ERR("unknown chip %x revision %x\n", 12411 CHIP_NUM(bp), CHIP_REV(bp)); 12412 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); 12413 12414 /* We need at least one default status block for slow-path events, 12415 * second status block for the L2 queue, and a third status block for 12416 * CNIC if supported. 12417 */ 12418 if (IS_VF(bp)) 12419 bp->min_msix_vec_cnt = 1; 12420 else if (CNIC_SUPPORT(bp)) 12421 bp->min_msix_vec_cnt = 3; 12422 else /* PF w/o cnic */ 12423 bp->min_msix_vec_cnt = 2; 12424 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); 12425 12426 bp->dump_preset_idx = 1; 12427 12428 return rc; 12429 } 12430 12431 /**************************************************************************** 12432 * General service functions 12433 ****************************************************************************/ 12434 12435 /* 12436 * net_device service functions 12437 */ 12438 12439 /* called with rtnl_lock */ 12440 static int bnx2x_open(struct net_device *dev) 12441 { 12442 struct bnx2x *bp = netdev_priv(dev); 12443 int rc; 12444 12445 bp->stats_init = true; 12446 12447 netif_carrier_off(dev); 12448 12449 bnx2x_set_power_state(bp, PCI_D0); 12450 12451 /* If parity had happen during the unload, then attentions 12452 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 12453 * want the first function loaded on the current engine to 12454 * complete the recovery. 12455 * Parity recovery is only relevant for PF driver. 12456 */ 12457 if (IS_PF(bp)) { 12458 int other_engine = BP_PATH(bp) ? 0 : 1; 12459 bool other_load_status, load_status; 12460 bool global = false; 12461 12462 other_load_status = bnx2x_get_load_status(bp, other_engine); 12463 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 12464 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 12465 bnx2x_chk_parity_attn(bp, &global, true)) { 12466 do { 12467 /* If there are attentions and they are in a 12468 * global blocks, set the GLOBAL_RESET bit 12469 * regardless whether it will be this function 12470 * that will complete the recovery or not. 12471 */ 12472 if (global) 12473 bnx2x_set_reset_global(bp); 12474 12475 /* Only the first function on the current 12476 * engine should try to recover in open. In case 12477 * of attentions in global blocks only the first 12478 * in the chip should try to recover. 12479 */ 12480 if ((!load_status && 12481 (!global || !other_load_status)) && 12482 bnx2x_trylock_leader_lock(bp) && 12483 !bnx2x_leader_reset(bp)) { 12484 netdev_info(bp->dev, 12485 "Recovered in open\n"); 12486 break; 12487 } 12488 12489 /* recovery has failed... */ 12490 bnx2x_set_power_state(bp, PCI_D3hot); 12491 bp->recovery_state = BNX2X_RECOVERY_FAILED; 12492 12493 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" 12494 "If you still see this message after a few retries then power cycle is required.\n"); 12495 12496 return -EAGAIN; 12497 } while (0); 12498 } 12499 } 12500 12501 bp->recovery_state = BNX2X_RECOVERY_DONE; 12502 rc = bnx2x_nic_load(bp, LOAD_OPEN); 12503 if (rc) 12504 return rc; 12505 12506 return 0; 12507 } 12508 12509 /* called with rtnl_lock */ 12510 static int bnx2x_close(struct net_device *dev) 12511 { 12512 struct bnx2x *bp = netdev_priv(dev); 12513 12514 /* Unload the driver, release IRQs */ 12515 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); 12516 12517 return 0; 12518 } 12519 12520 struct bnx2x_mcast_list_elem_group 12521 { 12522 struct list_head mcast_group_link; 12523 struct bnx2x_mcast_list_elem mcast_elems[]; 12524 }; 12525 12526 #define MCAST_ELEMS_PER_PG \ 12527 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \ 12528 sizeof(struct bnx2x_mcast_list_elem)) 12529 12530 static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list) 12531 { 12532 struct bnx2x_mcast_list_elem_group *current_mcast_group; 12533 12534 while (!list_empty(mcast_group_list)) { 12535 current_mcast_group = list_first_entry(mcast_group_list, 12536 struct bnx2x_mcast_list_elem_group, 12537 mcast_group_link); 12538 list_del(¤t_mcast_group->mcast_group_link); 12539 free_page((unsigned long)current_mcast_group); 12540 } 12541 } 12542 12543 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 12544 struct bnx2x_mcast_ramrod_params *p, 12545 struct list_head *mcast_group_list) 12546 { 12547 struct bnx2x_mcast_list_elem *mc_mac; 12548 struct netdev_hw_addr *ha; 12549 struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL; 12550 int mc_count = netdev_mc_count(bp->dev); 12551 int offset = 0; 12552 12553 INIT_LIST_HEAD(&p->mcast_list); 12554 netdev_for_each_mc_addr(ha, bp->dev) { 12555 if (!offset) { 12556 current_mcast_group = 12557 (struct bnx2x_mcast_list_elem_group *) 12558 __get_free_page(GFP_ATOMIC); 12559 if (!current_mcast_group) { 12560 bnx2x_free_mcast_macs_list(mcast_group_list); 12561 BNX2X_ERR("Failed to allocate mc MAC list\n"); 12562 return -ENOMEM; 12563 } 12564 list_add(¤t_mcast_group->mcast_group_link, 12565 mcast_group_list); 12566 } 12567 mc_mac = ¤t_mcast_group->mcast_elems[offset]; 12568 mc_mac->mac = bnx2x_mc_addr(ha); 12569 list_add_tail(&mc_mac->link, &p->mcast_list); 12570 offset++; 12571 if (offset == MCAST_ELEMS_PER_PG) 12572 offset = 0; 12573 } 12574 p->mcast_list_len = mc_count; 12575 return 0; 12576 } 12577 12578 /** 12579 * bnx2x_set_uc_list - configure a new unicast MACs list. 12580 * 12581 * @bp: driver handle 12582 * 12583 * We will use zero (0) as a MAC type for these MACs. 12584 */ 12585 static int bnx2x_set_uc_list(struct bnx2x *bp) 12586 { 12587 int rc; 12588 struct net_device *dev = bp->dev; 12589 struct netdev_hw_addr *ha; 12590 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; 12591 unsigned long ramrod_flags = 0; 12592 12593 /* First schedule a cleanup up of old configuration */ 12594 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 12595 if (rc < 0) { 12596 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 12597 return rc; 12598 } 12599 12600 netdev_for_each_uc_addr(ha, dev) { 12601 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 12602 BNX2X_UC_LIST_MAC, &ramrod_flags); 12603 if (rc == -EEXIST) { 12604 DP(BNX2X_MSG_SP, 12605 "Failed to schedule ADD operations: %d\n", rc); 12606 /* do not treat adding same MAC as error */ 12607 rc = 0; 12608 12609 } else if (rc < 0) { 12610 12611 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 12612 rc); 12613 return rc; 12614 } 12615 } 12616 12617 /* Execute the pending commands */ 12618 __set_bit(RAMROD_CONT, &ramrod_flags); 12619 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 12620 BNX2X_UC_LIST_MAC, &ramrod_flags); 12621 } 12622 12623 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp) 12624 { 12625 LIST_HEAD(mcast_group_list); 12626 struct net_device *dev = bp->dev; 12627 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 12628 int rc = 0; 12629 12630 rparam.mcast_obj = &bp->mcast_obj; 12631 12632 /* first, clear all configured multicast MACs */ 12633 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 12634 if (rc < 0) { 12635 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); 12636 return rc; 12637 } 12638 12639 /* then, configure a new MACs list */ 12640 if (netdev_mc_count(dev)) { 12641 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); 12642 if (rc) 12643 return rc; 12644 12645 /* Now add the new MACs */ 12646 rc = bnx2x_config_mcast(bp, &rparam, 12647 BNX2X_MCAST_CMD_ADD); 12648 if (rc < 0) 12649 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 12650 rc); 12651 12652 bnx2x_free_mcast_macs_list(&mcast_group_list); 12653 } 12654 12655 return rc; 12656 } 12657 12658 static int bnx2x_set_mc_list(struct bnx2x *bp) 12659 { 12660 LIST_HEAD(mcast_group_list); 12661 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 12662 struct net_device *dev = bp->dev; 12663 int rc = 0; 12664 12665 /* On older adapters, we need to flush and re-add filters */ 12666 if (CHIP_IS_E1x(bp)) 12667 return bnx2x_set_mc_list_e1x(bp); 12668 12669 rparam.mcast_obj = &bp->mcast_obj; 12670 12671 if (netdev_mc_count(dev)) { 12672 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); 12673 if (rc) 12674 return rc; 12675 12676 /* Override the curently configured set of mc filters */ 12677 rc = bnx2x_config_mcast(bp, &rparam, 12678 BNX2X_MCAST_CMD_SET); 12679 if (rc < 0) 12680 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 12681 rc); 12682 12683 bnx2x_free_mcast_macs_list(&mcast_group_list); 12684 } else { 12685 /* If no mc addresses are required, flush the configuration */ 12686 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 12687 if (rc < 0) 12688 BNX2X_ERR("Failed to clear multicast configuration %d\n", 12689 rc); 12690 } 12691 12692 return rc; 12693 } 12694 12695 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 12696 static void bnx2x_set_rx_mode(struct net_device *dev) 12697 { 12698 struct bnx2x *bp = netdev_priv(dev); 12699 12700 if (bp->state != BNX2X_STATE_OPEN) { 12701 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 12702 return; 12703 } else { 12704 /* Schedule an SP task to handle rest of change */ 12705 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, 12706 NETIF_MSG_IFUP); 12707 } 12708 } 12709 12710 void bnx2x_set_rx_mode_inner(struct bnx2x *bp) 12711 { 12712 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 12713 12714 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 12715 12716 netif_addr_lock_bh(bp->dev); 12717 12718 if (bp->dev->flags & IFF_PROMISC) { 12719 rx_mode = BNX2X_RX_MODE_PROMISC; 12720 } else if ((bp->dev->flags & IFF_ALLMULTI) || 12721 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && 12722 CHIP_IS_E1(bp))) { 12723 rx_mode = BNX2X_RX_MODE_ALLMULTI; 12724 } else { 12725 if (IS_PF(bp)) { 12726 /* some multicasts */ 12727 if (bnx2x_set_mc_list(bp) < 0) 12728 rx_mode = BNX2X_RX_MODE_ALLMULTI; 12729 12730 /* release bh lock, as bnx2x_set_uc_list might sleep */ 12731 netif_addr_unlock_bh(bp->dev); 12732 if (bnx2x_set_uc_list(bp) < 0) 12733 rx_mode = BNX2X_RX_MODE_PROMISC; 12734 netif_addr_lock_bh(bp->dev); 12735 } else { 12736 /* configuring mcast to a vf involves sleeping (when we 12737 * wait for the pf's response). 12738 */ 12739 bnx2x_schedule_sp_rtnl(bp, 12740 BNX2X_SP_RTNL_VFPF_MCAST, 0); 12741 } 12742 } 12743 12744 bp->rx_mode = rx_mode; 12745 /* handle ISCSI SD mode */ 12746 if (IS_MF_ISCSI_ONLY(bp)) 12747 bp->rx_mode = BNX2X_RX_MODE_NONE; 12748 12749 /* Schedule the rx_mode command */ 12750 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 12751 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 12752 netif_addr_unlock_bh(bp->dev); 12753 return; 12754 } 12755 12756 if (IS_PF(bp)) { 12757 bnx2x_set_storm_rx_mode(bp); 12758 netif_addr_unlock_bh(bp->dev); 12759 } else { 12760 /* VF will need to request the PF to make this change, and so 12761 * the VF needs to release the bottom-half lock prior to the 12762 * request (as it will likely require sleep on the VF side) 12763 */ 12764 netif_addr_unlock_bh(bp->dev); 12765 bnx2x_vfpf_storm_rx_mode(bp); 12766 } 12767 } 12768 12769 /* called with rtnl_lock */ 12770 static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 12771 int devad, u16 addr) 12772 { 12773 struct bnx2x *bp = netdev_priv(netdev); 12774 u16 value; 12775 int rc; 12776 12777 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 12778 prtad, devad, addr); 12779 12780 /* The HW expects different devad if CL22 is used */ 12781 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 12782 12783 bnx2x_acquire_phy_lock(bp); 12784 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 12785 bnx2x_release_phy_lock(bp); 12786 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 12787 12788 if (!rc) 12789 rc = value; 12790 return rc; 12791 } 12792 12793 /* called with rtnl_lock */ 12794 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 12795 u16 addr, u16 value) 12796 { 12797 struct bnx2x *bp = netdev_priv(netdev); 12798 int rc; 12799 12800 DP(NETIF_MSG_LINK, 12801 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", 12802 prtad, devad, addr, value); 12803 12804 /* The HW expects different devad if CL22 is used */ 12805 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 12806 12807 bnx2x_acquire_phy_lock(bp); 12808 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 12809 bnx2x_release_phy_lock(bp); 12810 return rc; 12811 } 12812 12813 /* called with rtnl_lock */ 12814 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 12815 { 12816 struct bnx2x *bp = netdev_priv(dev); 12817 struct mii_ioctl_data *mdio = if_mii(ifr); 12818 12819 if (!netif_running(dev)) 12820 return -EAGAIN; 12821 12822 switch (cmd) { 12823 case SIOCSHWTSTAMP: 12824 return bnx2x_hwtstamp_ioctl(bp, ifr); 12825 default: 12826 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 12827 mdio->phy_id, mdio->reg_num, mdio->val_in); 12828 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 12829 } 12830 } 12831 12832 static int bnx2x_validate_addr(struct net_device *dev) 12833 { 12834 struct bnx2x *bp = netdev_priv(dev); 12835 12836 /* query the bulletin board for mac address configured by the PF */ 12837 if (IS_VF(bp)) 12838 bnx2x_sample_bulletin(bp); 12839 12840 if (!is_valid_ether_addr(dev->dev_addr)) { 12841 BNX2X_ERR("Non-valid Ethernet address\n"); 12842 return -EADDRNOTAVAIL; 12843 } 12844 return 0; 12845 } 12846 12847 static int bnx2x_get_phys_port_id(struct net_device *netdev, 12848 struct netdev_phys_item_id *ppid) 12849 { 12850 struct bnx2x *bp = netdev_priv(netdev); 12851 12852 if (!(bp->flags & HAS_PHYS_PORT_ID)) 12853 return -EOPNOTSUPP; 12854 12855 ppid->id_len = sizeof(bp->phys_port_id); 12856 memcpy(ppid->id, bp->phys_port_id, ppid->id_len); 12857 12858 return 0; 12859 } 12860 12861 static netdev_features_t bnx2x_features_check(struct sk_buff *skb, 12862 struct net_device *dev, 12863 netdev_features_t features) 12864 { 12865 /* 12866 * A skb with gso_size + header length > 9700 will cause a 12867 * firmware panic. Drop GSO support. 12868 * 12869 * Eventually the upper layer should not pass these packets down. 12870 * 12871 * For speed, if the gso_size is <= 9000, assume there will 12872 * not be 700 bytes of headers and pass it through. Only do a 12873 * full (slow) validation if the gso_size is > 9000. 12874 * 12875 * (Due to the way SKB_BY_FRAGS works this will also do a full 12876 * validation in that case.) 12877 */ 12878 if (unlikely(skb_is_gso(skb) && 12879 (skb_shinfo(skb)->gso_size > 9000) && 12880 !skb_gso_validate_mac_len(skb, 9700))) 12881 features &= ~NETIF_F_GSO_MASK; 12882 12883 features = vlan_features_check(skb, features); 12884 return vxlan_features_check(skb, features); 12885 } 12886 12887 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) 12888 { 12889 int rc; 12890 12891 if (IS_PF(bp)) { 12892 unsigned long ramrod_flags = 0; 12893 12894 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 12895 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, 12896 add, &ramrod_flags); 12897 } else { 12898 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); 12899 } 12900 12901 return rc; 12902 } 12903 12904 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp) 12905 { 12906 struct bnx2x_vlan_entry *vlan; 12907 int rc = 0; 12908 12909 /* Configure all non-configured entries */ 12910 list_for_each_entry(vlan, &bp->vlan_reg, link) { 12911 if (vlan->hw) 12912 continue; 12913 12914 if (bp->vlan_cnt >= bp->vlan_credit) 12915 return -ENOBUFS; 12916 12917 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); 12918 if (rc) { 12919 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid); 12920 return rc; 12921 } 12922 12923 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid); 12924 vlan->hw = true; 12925 bp->vlan_cnt++; 12926 } 12927 12928 return 0; 12929 } 12930 12931 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode) 12932 { 12933 bool need_accept_any_vlan; 12934 12935 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp); 12936 12937 if (bp->accept_any_vlan != need_accept_any_vlan) { 12938 bp->accept_any_vlan = need_accept_any_vlan; 12939 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n", 12940 bp->accept_any_vlan ? "raised" : "cleared"); 12941 if (set_rx_mode) { 12942 if (IS_PF(bp)) 12943 bnx2x_set_rx_mode_inner(bp); 12944 else 12945 bnx2x_vfpf_storm_rx_mode(bp); 12946 } 12947 } 12948 } 12949 12950 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) 12951 { 12952 /* Don't set rx mode here. Our caller will do it. */ 12953 bnx2x_vlan_configure(bp, false); 12954 12955 return 0; 12956 } 12957 12958 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 12959 { 12960 struct bnx2x *bp = netdev_priv(dev); 12961 struct bnx2x_vlan_entry *vlan; 12962 12963 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid); 12964 12965 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL); 12966 if (!vlan) 12967 return -ENOMEM; 12968 12969 vlan->vid = vid; 12970 vlan->hw = false; 12971 list_add_tail(&vlan->link, &bp->vlan_reg); 12972 12973 if (netif_running(dev)) 12974 bnx2x_vlan_configure(bp, true); 12975 12976 return 0; 12977 } 12978 12979 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 12980 { 12981 struct bnx2x *bp = netdev_priv(dev); 12982 struct bnx2x_vlan_entry *vlan; 12983 bool found = false; 12984 int rc = 0; 12985 12986 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid); 12987 12988 list_for_each_entry(vlan, &bp->vlan_reg, link) 12989 if (vlan->vid == vid) { 12990 found = true; 12991 break; 12992 } 12993 12994 if (!found) { 12995 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid); 12996 return -EINVAL; 12997 } 12998 12999 if (netif_running(dev) && vlan->hw) { 13000 rc = __bnx2x_vlan_configure_vid(bp, vid, false); 13001 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid); 13002 bp->vlan_cnt--; 13003 } 13004 13005 list_del(&vlan->link); 13006 kfree(vlan); 13007 13008 if (netif_running(dev)) 13009 bnx2x_vlan_configure(bp, true); 13010 13011 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc); 13012 13013 return rc; 13014 } 13015 13016 static const struct net_device_ops bnx2x_netdev_ops = { 13017 .ndo_open = bnx2x_open, 13018 .ndo_stop = bnx2x_close, 13019 .ndo_start_xmit = bnx2x_start_xmit, 13020 .ndo_select_queue = bnx2x_select_queue, 13021 .ndo_set_rx_mode = bnx2x_set_rx_mode, 13022 .ndo_set_mac_address = bnx2x_change_mac_addr, 13023 .ndo_validate_addr = bnx2x_validate_addr, 13024 .ndo_eth_ioctl = bnx2x_ioctl, 13025 .ndo_change_mtu = bnx2x_change_mtu, 13026 .ndo_fix_features = bnx2x_fix_features, 13027 .ndo_set_features = bnx2x_set_features, 13028 .ndo_tx_timeout = bnx2x_tx_timeout, 13029 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid, 13030 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid, 13031 .ndo_setup_tc = __bnx2x_setup_tc, 13032 #ifdef CONFIG_BNX2X_SRIOV 13033 .ndo_set_vf_mac = bnx2x_set_vf_mac, 13034 .ndo_set_vf_vlan = bnx2x_set_vf_vlan, 13035 .ndo_get_vf_config = bnx2x_get_vf_config, 13036 .ndo_set_vf_spoofchk = bnx2x_set_vf_spoofchk, 13037 #endif 13038 #ifdef NETDEV_FCOE_WWNN 13039 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 13040 #endif 13041 13042 .ndo_get_phys_port_id = bnx2x_get_phys_port_id, 13043 .ndo_set_vf_link_state = bnx2x_set_vf_link_state, 13044 .ndo_features_check = bnx2x_features_check, 13045 }; 13046 13047 static int bnx2x_set_coherency_mask(struct bnx2x *bp) 13048 { 13049 struct device *dev = &bp->pdev->dev; 13050 13051 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 && 13052 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) { 13053 dev_err(dev, "System does not support DMA, aborting\n"); 13054 return -EIO; 13055 } 13056 13057 return 0; 13058 } 13059 13060 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp) 13061 { 13062 if (bp->flags & AER_ENABLED) { 13063 pci_disable_pcie_error_reporting(bp->pdev); 13064 bp->flags &= ~AER_ENABLED; 13065 } 13066 } 13067 13068 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, 13069 struct net_device *dev, unsigned long board_type) 13070 { 13071 int rc; 13072 u32 pci_cfg_dword; 13073 bool chip_is_e1x = (board_type == BCM57710 || 13074 board_type == BCM57711 || 13075 board_type == BCM57711E); 13076 13077 SET_NETDEV_DEV(dev, &pdev->dev); 13078 13079 bp->dev = dev; 13080 bp->pdev = pdev; 13081 13082 rc = pci_enable_device(pdev); 13083 if (rc) { 13084 dev_err(&bp->pdev->dev, 13085 "Cannot enable PCI device, aborting\n"); 13086 goto err_out; 13087 } 13088 13089 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 13090 dev_err(&bp->pdev->dev, 13091 "Cannot find PCI device base address, aborting\n"); 13092 rc = -ENODEV; 13093 goto err_out_disable; 13094 } 13095 13096 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 13097 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); 13098 rc = -ENODEV; 13099 goto err_out_disable; 13100 } 13101 13102 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); 13103 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == 13104 PCICFG_REVESION_ID_ERROR_VAL) { 13105 pr_err("PCI device error, probably due to fan failure, aborting\n"); 13106 rc = -ENODEV; 13107 goto err_out_disable; 13108 } 13109 13110 if (atomic_read(&pdev->enable_cnt) == 1) { 13111 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 13112 if (rc) { 13113 dev_err(&bp->pdev->dev, 13114 "Cannot obtain PCI resources, aborting\n"); 13115 goto err_out_disable; 13116 } 13117 13118 pci_set_master(pdev); 13119 pci_save_state(pdev); 13120 } 13121 13122 if (IS_PF(bp)) { 13123 if (!pdev->pm_cap) { 13124 dev_err(&bp->pdev->dev, 13125 "Cannot find power management capability, aborting\n"); 13126 rc = -EIO; 13127 goto err_out_release; 13128 } 13129 } 13130 13131 if (!pci_is_pcie(pdev)) { 13132 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 13133 rc = -EIO; 13134 goto err_out_release; 13135 } 13136 13137 rc = bnx2x_set_coherency_mask(bp); 13138 if (rc) 13139 goto err_out_release; 13140 13141 dev->mem_start = pci_resource_start(pdev, 0); 13142 dev->base_addr = dev->mem_start; 13143 dev->mem_end = pci_resource_end(pdev, 0); 13144 13145 dev->irq = pdev->irq; 13146 13147 bp->regview = pci_ioremap_bar(pdev, 0); 13148 if (!bp->regview) { 13149 dev_err(&bp->pdev->dev, 13150 "Cannot map register space, aborting\n"); 13151 rc = -ENOMEM; 13152 goto err_out_release; 13153 } 13154 13155 /* In E1/E1H use pci device function given by kernel. 13156 * In E2/E3 read physical function from ME register since these chips 13157 * support Physical Device Assignment where kernel BDF maybe arbitrary 13158 * (depending on hypervisor). 13159 */ 13160 if (chip_is_e1x) { 13161 bp->pf_num = PCI_FUNC(pdev->devfn); 13162 } else { 13163 /* chip is E2/3*/ 13164 pci_read_config_dword(bp->pdev, 13165 PCICFG_ME_REGISTER, &pci_cfg_dword); 13166 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 13167 ME_REG_ABS_PF_NUM_SHIFT); 13168 } 13169 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); 13170 13171 /* clean indirect addresses */ 13172 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 13173 PCICFG_VENDOR_ID_OFFSET); 13174 13175 /* Set PCIe reset type to fundamental for EEH recovery */ 13176 pdev->needs_freset = 1; 13177 13178 /* AER (Advanced Error reporting) configuration */ 13179 rc = pci_enable_pcie_error_reporting(pdev); 13180 if (!rc) 13181 bp->flags |= AER_ENABLED; 13182 else 13183 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc); 13184 13185 /* 13186 * Clean the following indirect addresses for all functions since it 13187 * is not used by the driver. 13188 */ 13189 if (IS_PF(bp)) { 13190 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 13191 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 13192 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 13193 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 13194 13195 if (chip_is_e1x) { 13196 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 13197 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 13198 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 13199 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 13200 } 13201 13202 /* Enable internal target-read (in case we are probed after PF 13203 * FLR). Must be done prior to any BAR read access. Only for 13204 * 57712 and up 13205 */ 13206 if (!chip_is_e1x) 13207 REG_WR(bp, 13208 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 13209 } 13210 13211 dev->watchdog_timeo = TX_TIMEOUT; 13212 13213 dev->netdev_ops = &bnx2x_netdev_ops; 13214 bnx2x_set_ethtool_ops(bp, dev); 13215 13216 dev->priv_flags |= IFF_UNICAST_FLT; 13217 13218 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 13219 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 13220 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW | 13221 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; 13222 if (!chip_is_e1x) { 13223 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | 13224 NETIF_F_GSO_IPXIP4 | 13225 NETIF_F_GSO_UDP_TUNNEL | 13226 NETIF_F_GSO_UDP_TUNNEL_CSUM | 13227 NETIF_F_GSO_PARTIAL; 13228 13229 dev->hw_enc_features = 13230 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 13231 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 13232 NETIF_F_GSO_IPXIP4 | 13233 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | 13234 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | 13235 NETIF_F_GSO_PARTIAL; 13236 13237 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM | 13238 NETIF_F_GSO_UDP_TUNNEL_CSUM; 13239 13240 if (IS_PF(bp)) 13241 dev->udp_tunnel_nic_info = &bnx2x_udp_tunnels; 13242 } 13243 13244 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 13245 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 13246 13247 if (IS_PF(bp)) { 13248 if (chip_is_e1x) 13249 bp->accept_any_vlan = true; 13250 else 13251 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13252 } 13253 /* For VF we'll know whether to enable VLAN filtering after 13254 * getting a response to CHANNEL_TLV_ACQUIRE from PF. 13255 */ 13256 13257 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; 13258 dev->features |= NETIF_F_HIGHDMA; 13259 if (dev->features & NETIF_F_LRO) 13260 dev->features &= ~NETIF_F_GRO_HW; 13261 13262 /* Add Loopback capability to the device */ 13263 dev->hw_features |= NETIF_F_LOOPBACK; 13264 13265 #ifdef BCM_DCBNL 13266 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 13267 #endif 13268 13269 /* MTU range, 46 - 9600 */ 13270 dev->min_mtu = ETH_MIN_PACKET_SIZE; 13271 dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE; 13272 13273 /* get_port_hwinfo() will set prtad and mmds properly */ 13274 bp->mdio.prtad = MDIO_PRTAD_NONE; 13275 bp->mdio.mmds = 0; 13276 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 13277 bp->mdio.dev = dev; 13278 bp->mdio.mdio_read = bnx2x_mdio_read; 13279 bp->mdio.mdio_write = bnx2x_mdio_write; 13280 13281 return 0; 13282 13283 err_out_release: 13284 if (atomic_read(&pdev->enable_cnt) == 1) 13285 pci_release_regions(pdev); 13286 13287 err_out_disable: 13288 pci_disable_device(pdev); 13289 13290 err_out: 13291 return rc; 13292 } 13293 13294 static int bnx2x_check_firmware(struct bnx2x *bp) 13295 { 13296 const struct firmware *firmware = bp->firmware; 13297 struct bnx2x_fw_file_hdr *fw_hdr; 13298 struct bnx2x_fw_file_section *sections; 13299 u32 offset, len, num_ops; 13300 __be16 *ops_offsets; 13301 int i; 13302 const u8 *fw_ver; 13303 13304 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { 13305 BNX2X_ERR("Wrong FW size\n"); 13306 return -EINVAL; 13307 } 13308 13309 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 13310 sections = (struct bnx2x_fw_file_section *)fw_hdr; 13311 13312 /* Make sure none of the offsets and sizes make us read beyond 13313 * the end of the firmware data */ 13314 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 13315 offset = be32_to_cpu(sections[i].offset); 13316 len = be32_to_cpu(sections[i].len); 13317 if (offset + len > firmware->size) { 13318 BNX2X_ERR("Section %d length is out of bounds\n", i); 13319 return -EINVAL; 13320 } 13321 } 13322 13323 /* Likewise for the init_ops offsets */ 13324 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 13325 ops_offsets = (__force __be16 *)(firmware->data + offset); 13326 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 13327 13328 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 13329 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 13330 BNX2X_ERR("Section offset %d is out of bounds\n", i); 13331 return -EINVAL; 13332 } 13333 } 13334 13335 /* Check FW version */ 13336 offset = be32_to_cpu(fw_hdr->fw_version.offset); 13337 fw_ver = firmware->data + offset; 13338 if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor || 13339 fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) { 13340 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 13341 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], 13342 bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng); 13343 return -EINVAL; 13344 } 13345 13346 return 0; 13347 } 13348 13349 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 13350 { 13351 const __be32 *source = (const __be32 *)_source; 13352 u32 *target = (u32 *)_target; 13353 u32 i; 13354 13355 for (i = 0; i < n/4; i++) 13356 target[i] = be32_to_cpu(source[i]); 13357 } 13358 13359 /* 13360 Ops array is stored in the following format: 13361 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 13362 */ 13363 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 13364 { 13365 const __be32 *source = (const __be32 *)_source; 13366 struct raw_op *target = (struct raw_op *)_target; 13367 u32 i, j, tmp; 13368 13369 for (i = 0, j = 0; i < n/8; i++, j += 2) { 13370 tmp = be32_to_cpu(source[j]); 13371 target[i].op = (tmp >> 24) & 0xff; 13372 target[i].offset = tmp & 0xffffff; 13373 target[i].raw_data = be32_to_cpu(source[j + 1]); 13374 } 13375 } 13376 13377 /* IRO array is stored in the following format: 13378 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 13379 */ 13380 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 13381 { 13382 const __be32 *source = (const __be32 *)_source; 13383 struct iro *target = (struct iro *)_target; 13384 u32 i, j, tmp; 13385 13386 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 13387 target[i].base = be32_to_cpu(source[j]); 13388 j++; 13389 tmp = be32_to_cpu(source[j]); 13390 target[i].m1 = (tmp >> 16) & 0xffff; 13391 target[i].m2 = tmp & 0xffff; 13392 j++; 13393 tmp = be32_to_cpu(source[j]); 13394 target[i].m3 = (tmp >> 16) & 0xffff; 13395 target[i].size = tmp & 0xffff; 13396 j++; 13397 } 13398 } 13399 13400 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 13401 { 13402 const __be16 *source = (const __be16 *)_source; 13403 u16 *target = (u16 *)_target; 13404 u32 i; 13405 13406 for (i = 0; i < n/2; i++) 13407 target[i] = be16_to_cpu(source[i]); 13408 } 13409 13410 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 13411 do { \ 13412 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 13413 bp->arr = kmalloc(len, GFP_KERNEL); \ 13414 if (!bp->arr) \ 13415 goto lbl; \ 13416 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 13417 (u8 *)bp->arr, len); \ 13418 } while (0) 13419 13420 int bnx2x_init_firmware(struct bnx2x *bp) 13421 { 13422 const char *fw_file_name, *fw_file_name_v15; 13423 struct bnx2x_fw_file_hdr *fw_hdr; 13424 int rc; 13425 13426 if (bp->firmware) 13427 return 0; 13428 13429 if (CHIP_IS_E1(bp)) { 13430 fw_file_name = FW_FILE_NAME_E1; 13431 fw_file_name_v15 = FW_FILE_NAME_E1_V15; 13432 } else if (CHIP_IS_E1H(bp)) { 13433 fw_file_name = FW_FILE_NAME_E1H; 13434 fw_file_name_v15 = FW_FILE_NAME_E1H_V15; 13435 } else if (!CHIP_IS_E1x(bp)) { 13436 fw_file_name = FW_FILE_NAME_E2; 13437 fw_file_name_v15 = FW_FILE_NAME_E2_V15; 13438 } else { 13439 BNX2X_ERR("Unsupported chip revision\n"); 13440 return -EINVAL; 13441 } 13442 13443 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 13444 13445 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 13446 if (rc) { 13447 BNX2X_DEV_INFO("Trying to load older fw %s\n", fw_file_name_v15); 13448 13449 /* try to load prev version */ 13450 rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev); 13451 13452 if (rc) 13453 goto request_firmware_exit; 13454 13455 bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15; 13456 } else { 13457 bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI; 13458 bp->fw_rev = BCM_5710_FW_REVISION_VERSION; 13459 } 13460 13461 bp->fw_major = BCM_5710_FW_MAJOR_VERSION; 13462 bp->fw_minor = BCM_5710_FW_MINOR_VERSION; 13463 bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION; 13464 13465 rc = bnx2x_check_firmware(bp); 13466 if (rc) { 13467 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 13468 goto request_firmware_exit; 13469 } 13470 13471 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 13472 13473 /* Initialize the pointers to the init arrays */ 13474 /* Blob */ 13475 rc = -ENOMEM; 13476 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 13477 13478 /* Opcodes */ 13479 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 13480 13481 /* Offsets */ 13482 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 13483 be16_to_cpu_n); 13484 13485 /* STORMs firmware */ 13486 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13487 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 13488 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 13489 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 13490 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13491 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 13492 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 13493 be32_to_cpu(fw_hdr->usem_pram_data.offset); 13494 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13495 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 13496 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 13497 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 13498 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13499 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 13500 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 13501 be32_to_cpu(fw_hdr->csem_pram_data.offset); 13502 /* IRO */ 13503 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 13504 13505 return 0; 13506 13507 iro_alloc_err: 13508 kfree(bp->init_ops_offsets); 13509 init_offsets_alloc_err: 13510 kfree(bp->init_ops); 13511 init_ops_alloc_err: 13512 kfree(bp->init_data); 13513 request_firmware_exit: 13514 release_firmware(bp->firmware); 13515 bp->firmware = NULL; 13516 13517 return rc; 13518 } 13519 13520 void bnx2x_release_firmware(struct bnx2x *bp) 13521 { 13522 kfree(bp->init_ops_offsets); 13523 kfree(bp->init_ops); 13524 kfree(bp->init_data); 13525 release_firmware(bp->firmware); 13526 bp->firmware = NULL; 13527 } 13528 13529 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 13530 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 13531 .init_hw_cmn = bnx2x_init_hw_common, 13532 .init_hw_port = bnx2x_init_hw_port, 13533 .init_hw_func = bnx2x_init_hw_func, 13534 13535 .reset_hw_cmn = bnx2x_reset_common, 13536 .reset_hw_port = bnx2x_reset_port, 13537 .reset_hw_func = bnx2x_reset_func, 13538 13539 .gunzip_init = bnx2x_gunzip_init, 13540 .gunzip_end = bnx2x_gunzip_end, 13541 13542 .init_fw = bnx2x_init_firmware, 13543 .release_fw = bnx2x_release_firmware, 13544 }; 13545 13546 void bnx2x__init_func_obj(struct bnx2x *bp) 13547 { 13548 /* Prepare DMAE related driver resources */ 13549 bnx2x_setup_dmae(bp); 13550 13551 bnx2x_init_func_obj(bp, &bp->func_obj, 13552 bnx2x_sp(bp, func_rdata), 13553 bnx2x_sp_mapping(bp, func_rdata), 13554 bnx2x_sp(bp, func_afex_rdata), 13555 bnx2x_sp_mapping(bp, func_afex_rdata), 13556 &bnx2x_func_sp_drv); 13557 } 13558 13559 /* must be called after sriov-enable */ 13560 static int bnx2x_set_qm_cid_count(struct bnx2x *bp) 13561 { 13562 int cid_count = BNX2X_L2_MAX_CID(bp); 13563 13564 if (IS_SRIOV(bp)) 13565 cid_count += BNX2X_VF_CIDS; 13566 13567 if (CNIC_SUPPORT(bp)) 13568 cid_count += CNIC_CID_MAX; 13569 13570 return roundup(cid_count, QM_CID_ROUND); 13571 } 13572 13573 /** 13574 * bnx2x_get_num_non_def_sbs - return the number of none default SBs 13575 * @pdev: pci device 13576 * @cnic_cnt: count 13577 * 13578 */ 13579 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) 13580 { 13581 int index; 13582 u16 control = 0; 13583 13584 /* 13585 * If MSI-X is not supported - return number of SBs needed to support 13586 * one fast path queue: one FP queue + SB for CNIC 13587 */ 13588 if (!pdev->msix_cap) { 13589 dev_info(&pdev->dev, "no msix capability found\n"); 13590 return 1 + cnic_cnt; 13591 } 13592 dev_info(&pdev->dev, "msix capability found\n"); 13593 13594 /* 13595 * The value in the PCI configuration space is the index of the last 13596 * entry, namely one less than the actual size of the table, which is 13597 * exactly what we want to return from this function: number of all SBs 13598 * without the default SB. 13599 * For VFs there is no default SB, then we return (index+1). 13600 */ 13601 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); 13602 13603 index = control & PCI_MSIX_FLAGS_QSIZE; 13604 13605 return index; 13606 } 13607 13608 static int set_max_cos_est(int chip_id) 13609 { 13610 switch (chip_id) { 13611 case BCM57710: 13612 case BCM57711: 13613 case BCM57711E: 13614 return BNX2X_MULTI_TX_COS_E1X; 13615 case BCM57712: 13616 case BCM57712_MF: 13617 return BNX2X_MULTI_TX_COS_E2_E3A0; 13618 case BCM57800: 13619 case BCM57800_MF: 13620 case BCM57810: 13621 case BCM57810_MF: 13622 case BCM57840_4_10: 13623 case BCM57840_2_20: 13624 case BCM57840_O: 13625 case BCM57840_MFO: 13626 case BCM57840_MF: 13627 case BCM57811: 13628 case BCM57811_MF: 13629 return BNX2X_MULTI_TX_COS_E3B0; 13630 case BCM57712_VF: 13631 case BCM57800_VF: 13632 case BCM57810_VF: 13633 case BCM57840_VF: 13634 case BCM57811_VF: 13635 return 1; 13636 default: 13637 pr_err("Unknown board_type (%d), aborting\n", chip_id); 13638 return -ENODEV; 13639 } 13640 } 13641 13642 static int set_is_vf(int chip_id) 13643 { 13644 switch (chip_id) { 13645 case BCM57712_VF: 13646 case BCM57800_VF: 13647 case BCM57810_VF: 13648 case BCM57840_VF: 13649 case BCM57811_VF: 13650 return true; 13651 default: 13652 return false; 13653 } 13654 } 13655 13656 /* nig_tsgen registers relative address */ 13657 #define tsgen_ctrl 0x0 13658 #define tsgen_freecount 0x10 13659 #define tsgen_synctime_t0 0x20 13660 #define tsgen_offset_t0 0x28 13661 #define tsgen_drift_t0 0x30 13662 #define tsgen_synctime_t1 0x58 13663 #define tsgen_offset_t1 0x60 13664 #define tsgen_drift_t1 0x68 13665 13666 /* FW workaround for setting drift */ 13667 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, 13668 int best_val, int best_period) 13669 { 13670 struct bnx2x_func_state_params func_params = {NULL}; 13671 struct bnx2x_func_set_timesync_params *set_timesync_params = 13672 &func_params.params.set_timesync; 13673 13674 /* Prepare parameters for function state transitions */ 13675 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 13676 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 13677 13678 func_params.f_obj = &bp->func_obj; 13679 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; 13680 13681 /* Function parameters */ 13682 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; 13683 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; 13684 set_timesync_params->add_sub_drift_adjust_value = 13685 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE; 13686 set_timesync_params->drift_adjust_value = best_val; 13687 set_timesync_params->drift_adjust_period = best_period; 13688 13689 return bnx2x_func_state_change(bp, &func_params); 13690 } 13691 13692 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 13693 { 13694 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13695 int rc; 13696 int drift_dir = 1; 13697 int val, period, period1, period2, dif, dif1, dif2; 13698 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; 13699 13700 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb); 13701 13702 if (!netif_running(bp->dev)) { 13703 DP(BNX2X_MSG_PTP, 13704 "PTP adjfreq called while the interface is down\n"); 13705 return -ENETDOWN; 13706 } 13707 13708 if (ppb < 0) { 13709 ppb = -ppb; 13710 drift_dir = 0; 13711 } 13712 13713 if (ppb == 0) { 13714 best_val = 1; 13715 best_period = 0x1FFFFFF; 13716 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) { 13717 best_val = 31; 13718 best_period = 1; 13719 } else { 13720 /* Changed not to allow val = 8, 16, 24 as these values 13721 * are not supported in workaround. 13722 */ 13723 for (val = 0; val <= 31; val++) { 13724 if ((val & 0x7) == 0) 13725 continue; 13726 period1 = val * 1000000 / ppb; 13727 period2 = period1 + 1; 13728 if (period1 != 0) 13729 dif1 = ppb - (val * 1000000 / period1); 13730 else 13731 dif1 = BNX2X_MAX_PHC_DRIFT; 13732 if (dif1 < 0) 13733 dif1 = -dif1; 13734 dif2 = ppb - (val * 1000000 / period2); 13735 if (dif2 < 0) 13736 dif2 = -dif2; 13737 dif = (dif1 < dif2) ? dif1 : dif2; 13738 period = (dif1 < dif2) ? period1 : period2; 13739 if (dif < best_dif) { 13740 best_dif = dif; 13741 best_val = val; 13742 best_period = period; 13743 } 13744 } 13745 } 13746 13747 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, 13748 best_period); 13749 if (rc) { 13750 BNX2X_ERR("Failed to set drift\n"); 13751 return -EFAULT; 13752 } 13753 13754 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, 13755 best_period); 13756 13757 return 0; 13758 } 13759 13760 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 13761 { 13762 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13763 13764 if (!netif_running(bp->dev)) { 13765 DP(BNX2X_MSG_PTP, 13766 "PTP adjtime called while the interface is down\n"); 13767 return -ENETDOWN; 13768 } 13769 13770 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); 13771 13772 timecounter_adjtime(&bp->timecounter, delta); 13773 13774 return 0; 13775 } 13776 13777 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 13778 { 13779 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13780 u64 ns; 13781 13782 if (!netif_running(bp->dev)) { 13783 DP(BNX2X_MSG_PTP, 13784 "PTP gettime called while the interface is down\n"); 13785 return -ENETDOWN; 13786 } 13787 13788 ns = timecounter_read(&bp->timecounter); 13789 13790 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); 13791 13792 *ts = ns_to_timespec64(ns); 13793 13794 return 0; 13795 } 13796 13797 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp, 13798 const struct timespec64 *ts) 13799 { 13800 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13801 u64 ns; 13802 13803 if (!netif_running(bp->dev)) { 13804 DP(BNX2X_MSG_PTP, 13805 "PTP settime called while the interface is down\n"); 13806 return -ENETDOWN; 13807 } 13808 13809 ns = timespec64_to_ns(ts); 13810 13811 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); 13812 13813 /* Re-init the timecounter */ 13814 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); 13815 13816 return 0; 13817 } 13818 13819 /* Enable (or disable) ancillary features of the phc subsystem */ 13820 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp, 13821 struct ptp_clock_request *rq, int on) 13822 { 13823 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13824 13825 BNX2X_ERR("PHC ancillary features are not supported\n"); 13826 return -ENOTSUPP; 13827 } 13828 13829 void bnx2x_register_phc(struct bnx2x *bp) 13830 { 13831 /* Fill the ptp_clock_info struct and register PTP clock*/ 13832 bp->ptp_clock_info.owner = THIS_MODULE; 13833 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); 13834 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ 13835 bp->ptp_clock_info.n_alarm = 0; 13836 bp->ptp_clock_info.n_ext_ts = 0; 13837 bp->ptp_clock_info.n_per_out = 0; 13838 bp->ptp_clock_info.pps = 0; 13839 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; 13840 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; 13841 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; 13842 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; 13843 bp->ptp_clock_info.enable = bnx2x_ptp_enable; 13844 13845 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); 13846 if (IS_ERR(bp->ptp_clock)) { 13847 bp->ptp_clock = NULL; 13848 BNX2X_ERR("PTP clock registration failed\n"); 13849 } 13850 } 13851 13852 static int bnx2x_init_one(struct pci_dev *pdev, 13853 const struct pci_device_id *ent) 13854 { 13855 struct net_device *dev = NULL; 13856 struct bnx2x *bp; 13857 int rc, max_non_def_sbs; 13858 int rx_count, tx_count, rss_count, doorbell_size; 13859 int max_cos_est; 13860 bool is_vf; 13861 int cnic_cnt; 13862 13863 /* Management FW 'remembers' living interfaces. Allow it some time 13864 * to forget previously living interfaces, allowing a proper re-load. 13865 */ 13866 if (is_kdump_kernel()) { 13867 ktime_t now = ktime_get_boottime(); 13868 ktime_t fw_ready_time = ktime_set(5, 0); 13869 13870 if (ktime_before(now, fw_ready_time)) 13871 msleep(ktime_ms_delta(fw_ready_time, now)); 13872 } 13873 13874 /* An estimated maximum supported CoS number according to the chip 13875 * version. 13876 * We will try to roughly estimate the maximum number of CoSes this chip 13877 * may support in order to minimize the memory allocated for Tx 13878 * netdev_queue's. This number will be accurately calculated during the 13879 * initialization of bp->max_cos based on the chip versions AND chip 13880 * revision in the bnx2x_init_bp(). 13881 */ 13882 max_cos_est = set_max_cos_est(ent->driver_data); 13883 if (max_cos_est < 0) 13884 return max_cos_est; 13885 is_vf = set_is_vf(ent->driver_data); 13886 cnic_cnt = is_vf ? 0 : 1; 13887 13888 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); 13889 13890 /* add another SB for VF as it has no default SB */ 13891 max_non_def_sbs += is_vf ? 1 : 0; 13892 13893 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 13894 rss_count = max_non_def_sbs - cnic_cnt; 13895 13896 if (rss_count < 1) 13897 return -EINVAL; 13898 13899 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 13900 rx_count = rss_count + cnic_cnt; 13901 13902 /* Maximum number of netdev Tx queues: 13903 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 13904 */ 13905 tx_count = rss_count * max_cos_est + cnic_cnt; 13906 13907 /* dev zeroed in init_etherdev */ 13908 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 13909 if (!dev) 13910 return -ENOMEM; 13911 13912 bp = netdev_priv(dev); 13913 13914 bp->flags = 0; 13915 if (is_vf) 13916 bp->flags |= IS_VF_FLAG; 13917 13918 bp->igu_sb_cnt = max_non_def_sbs; 13919 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; 13920 bp->msg_enable = debug; 13921 bp->cnic_support = cnic_cnt; 13922 bp->cnic_probe = bnx2x_cnic_probe; 13923 13924 pci_set_drvdata(pdev, dev); 13925 13926 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); 13927 if (rc < 0) { 13928 free_netdev(dev); 13929 return rc; 13930 } 13931 13932 BNX2X_DEV_INFO("This is a %s function\n", 13933 IS_PF(bp) ? "physical" : "virtual"); 13934 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); 13935 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); 13936 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", 13937 tx_count, rx_count); 13938 13939 rc = bnx2x_init_bp(bp); 13940 if (rc) 13941 goto init_one_exit; 13942 13943 /* Map doorbells here as we need the real value of bp->max_cos which 13944 * is initialized in bnx2x_init_bp() to determine the number of 13945 * l2 connections. 13946 */ 13947 if (IS_VF(bp)) { 13948 bp->doorbells = bnx2x_vf_doorbells(bp); 13949 rc = bnx2x_vf_pci_alloc(bp); 13950 if (rc) 13951 goto init_one_freemem; 13952 } else { 13953 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); 13954 if (doorbell_size > pci_resource_len(pdev, 2)) { 13955 dev_err(&bp->pdev->dev, 13956 "Cannot map doorbells, bar size too small, aborting\n"); 13957 rc = -ENOMEM; 13958 goto init_one_freemem; 13959 } 13960 bp->doorbells = ioremap(pci_resource_start(pdev, 2), 13961 doorbell_size); 13962 } 13963 if (!bp->doorbells) { 13964 dev_err(&bp->pdev->dev, 13965 "Cannot map doorbell space, aborting\n"); 13966 rc = -ENOMEM; 13967 goto init_one_freemem; 13968 } 13969 13970 if (IS_VF(bp)) { 13971 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); 13972 if (rc) 13973 goto init_one_freemem; 13974 13975 #ifdef CONFIG_BNX2X_SRIOV 13976 /* VF with OLD Hypervisor or old PF do not support filtering */ 13977 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { 13978 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13979 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13980 } 13981 #endif 13982 } 13983 13984 /* Enable SRIOV if capability found in configuration space */ 13985 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); 13986 if (rc) 13987 goto init_one_freemem; 13988 13989 /* calc qm_cid_count */ 13990 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 13991 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); 13992 13993 /* disable FCOE L2 queue for E1x*/ 13994 if (CHIP_IS_E1x(bp)) 13995 bp->flags |= NO_FCOE_FLAG; 13996 13997 /* Set bp->num_queues for MSI-X mode*/ 13998 bnx2x_set_num_queues(bp); 13999 14000 /* Configure interrupt mode: try to enable MSI-X/MSI if 14001 * needed. 14002 */ 14003 rc = bnx2x_set_int_mode(bp); 14004 if (rc) { 14005 dev_err(&pdev->dev, "Cannot set interrupts\n"); 14006 goto init_one_freemem; 14007 } 14008 BNX2X_DEV_INFO("set interrupts successfully\n"); 14009 14010 /* register the net device */ 14011 rc = register_netdev(dev); 14012 if (rc) { 14013 dev_err(&pdev->dev, "Cannot register net device\n"); 14014 goto init_one_freemem; 14015 } 14016 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); 14017 14018 if (!NO_FCOE(bp)) { 14019 /* Add storage MAC address */ 14020 rtnl_lock(); 14021 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 14022 rtnl_unlock(); 14023 } 14024 BNX2X_DEV_INFO( 14025 "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n", 14026 board_info[ent->driver_data].name, 14027 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 14028 dev->base_addr, bp->pdev->irq, dev->dev_addr); 14029 pcie_print_link_status(bp->pdev); 14030 14031 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) 14032 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); 14033 14034 return 0; 14035 14036 init_one_freemem: 14037 bnx2x_release_firmware(bp); 14038 bnx2x_free_mem_bp(bp); 14039 14040 init_one_exit: 14041 bnx2x_disable_pcie_error_reporting(bp); 14042 14043 if (bp->regview) 14044 iounmap(bp->regview); 14045 14046 if (IS_PF(bp) && bp->doorbells) 14047 iounmap(bp->doorbells); 14048 14049 free_netdev(dev); 14050 14051 if (atomic_read(&pdev->enable_cnt) == 1) 14052 pci_release_regions(pdev); 14053 14054 pci_disable_device(pdev); 14055 14056 return rc; 14057 } 14058 14059 static void __bnx2x_remove(struct pci_dev *pdev, 14060 struct net_device *dev, 14061 struct bnx2x *bp, 14062 bool remove_netdev) 14063 { 14064 /* Delete storage MAC address */ 14065 if (!NO_FCOE(bp)) { 14066 rtnl_lock(); 14067 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 14068 rtnl_unlock(); 14069 } 14070 14071 #ifdef BCM_DCBNL 14072 /* Delete app tlvs from dcbnl */ 14073 bnx2x_dcbnl_update_applist(bp, true); 14074 #endif 14075 14076 if (IS_PF(bp) && 14077 !BP_NOMCP(bp) && 14078 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) 14079 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); 14080 14081 /* Close the interface - either directly or implicitly */ 14082 if (remove_netdev) { 14083 unregister_netdev(dev); 14084 } else { 14085 rtnl_lock(); 14086 dev_close(dev); 14087 rtnl_unlock(); 14088 } 14089 14090 bnx2x_iov_remove_one(bp); 14091 14092 /* Power on: we can't let PCI layer write to us while we are in D3 */ 14093 if (IS_PF(bp)) { 14094 bnx2x_set_power_state(bp, PCI_D0); 14095 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); 14096 14097 /* Set endianity registers to reset values in case next driver 14098 * boots in different endianty environment. 14099 */ 14100 bnx2x_reset_endianity(bp); 14101 } 14102 14103 /* Disable MSI/MSI-X */ 14104 bnx2x_disable_msi(bp); 14105 14106 /* Power off */ 14107 if (IS_PF(bp)) 14108 bnx2x_set_power_state(bp, PCI_D3hot); 14109 14110 /* Make sure RESET task is not scheduled before continuing */ 14111 cancel_delayed_work_sync(&bp->sp_rtnl_task); 14112 14113 /* send message via vfpf channel to release the resources of this vf */ 14114 if (IS_VF(bp)) 14115 bnx2x_vfpf_release(bp); 14116 14117 /* Assumes no further PCIe PM changes will occur */ 14118 if (system_state == SYSTEM_POWER_OFF) { 14119 pci_wake_from_d3(pdev, bp->wol); 14120 pci_set_power_state(pdev, PCI_D3hot); 14121 } 14122 14123 bnx2x_disable_pcie_error_reporting(bp); 14124 if (remove_netdev) { 14125 if (bp->regview) 14126 iounmap(bp->regview); 14127 14128 /* For vfs, doorbells are part of the regview and were unmapped 14129 * along with it. FW is only loaded by PF. 14130 */ 14131 if (IS_PF(bp)) { 14132 if (bp->doorbells) 14133 iounmap(bp->doorbells); 14134 14135 bnx2x_release_firmware(bp); 14136 } else { 14137 bnx2x_vf_pci_dealloc(bp); 14138 } 14139 bnx2x_free_mem_bp(bp); 14140 14141 free_netdev(dev); 14142 14143 if (atomic_read(&pdev->enable_cnt) == 1) 14144 pci_release_regions(pdev); 14145 14146 pci_disable_device(pdev); 14147 } 14148 } 14149 14150 static void bnx2x_remove_one(struct pci_dev *pdev) 14151 { 14152 struct net_device *dev = pci_get_drvdata(pdev); 14153 struct bnx2x *bp; 14154 14155 if (!dev) { 14156 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 14157 return; 14158 } 14159 bp = netdev_priv(dev); 14160 14161 __bnx2x_remove(pdev, dev, bp, true); 14162 } 14163 14164 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 14165 { 14166 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; 14167 14168 bp->rx_mode = BNX2X_RX_MODE_NONE; 14169 14170 if (CNIC_LOADED(bp)) 14171 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 14172 14173 /* Stop Tx */ 14174 bnx2x_tx_disable(bp); 14175 /* Delete all NAPI objects */ 14176 bnx2x_del_all_napi(bp); 14177 if (CNIC_LOADED(bp)) 14178 bnx2x_del_all_napi_cnic(bp); 14179 netdev_reset_tc(bp->dev); 14180 14181 del_timer_sync(&bp->timer); 14182 cancel_delayed_work_sync(&bp->sp_task); 14183 cancel_delayed_work_sync(&bp->period_task); 14184 14185 if (!down_timeout(&bp->stats_lock, HZ / 10)) { 14186 bp->stats_state = STATS_STATE_DISABLED; 14187 up(&bp->stats_lock); 14188 } 14189 14190 bnx2x_save_statistics(bp); 14191 14192 netif_carrier_off(bp->dev); 14193 14194 return 0; 14195 } 14196 14197 /** 14198 * bnx2x_io_error_detected - called when PCI error is detected 14199 * @pdev: Pointer to PCI device 14200 * @state: The current pci connection state 14201 * 14202 * This function is called after a PCI bus error affecting 14203 * this device has been detected. 14204 */ 14205 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 14206 pci_channel_state_t state) 14207 { 14208 struct net_device *dev = pci_get_drvdata(pdev); 14209 struct bnx2x *bp = netdev_priv(dev); 14210 14211 rtnl_lock(); 14212 14213 BNX2X_ERR("IO error detected\n"); 14214 14215 netif_device_detach(dev); 14216 14217 if (state == pci_channel_io_perm_failure) { 14218 rtnl_unlock(); 14219 return PCI_ERS_RESULT_DISCONNECT; 14220 } 14221 14222 if (netif_running(dev)) 14223 bnx2x_eeh_nic_unload(bp); 14224 14225 bnx2x_prev_path_mark_eeh(bp); 14226 14227 pci_disable_device(pdev); 14228 14229 rtnl_unlock(); 14230 14231 /* Request a slot reset */ 14232 return PCI_ERS_RESULT_NEED_RESET; 14233 } 14234 14235 /** 14236 * bnx2x_io_slot_reset - called after the PCI bus has been reset 14237 * @pdev: Pointer to PCI device 14238 * 14239 * Restart the card from scratch, as if from a cold-boot. 14240 */ 14241 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 14242 { 14243 struct net_device *dev = pci_get_drvdata(pdev); 14244 struct bnx2x *bp = netdev_priv(dev); 14245 int i; 14246 14247 rtnl_lock(); 14248 BNX2X_ERR("IO slot reset initializing...\n"); 14249 if (pci_enable_device(pdev)) { 14250 dev_err(&pdev->dev, 14251 "Cannot re-enable PCI device after reset\n"); 14252 rtnl_unlock(); 14253 return PCI_ERS_RESULT_DISCONNECT; 14254 } 14255 14256 pci_set_master(pdev); 14257 pci_restore_state(pdev); 14258 pci_save_state(pdev); 14259 14260 if (netif_running(dev)) 14261 bnx2x_set_power_state(bp, PCI_D0); 14262 14263 if (netif_running(dev)) { 14264 BNX2X_ERR("IO slot reset --> driver unload\n"); 14265 14266 /* MCP should have been reset; Need to wait for validity */ 14267 if (bnx2x_init_shmem(bp)) { 14268 rtnl_unlock(); 14269 return PCI_ERS_RESULT_DISCONNECT; 14270 } 14271 14272 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { 14273 u32 v; 14274 14275 v = SHMEM2_RD(bp, 14276 drv_capabilities_flag[BP_FW_MB_IDX(bp)]); 14277 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], 14278 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); 14279 } 14280 bnx2x_drain_tx_queues(bp); 14281 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); 14282 bnx2x_netif_stop(bp, 1); 14283 bnx2x_free_irq(bp); 14284 14285 /* Report UNLOAD_DONE to MCP */ 14286 bnx2x_send_unload_done(bp, true); 14287 14288 bp->sp_state = 0; 14289 bp->port.pmf = 0; 14290 14291 bnx2x_prev_unload(bp); 14292 14293 /* We should have reseted the engine, so It's fair to 14294 * assume the FW will no longer write to the bnx2x driver. 14295 */ 14296 bnx2x_squeeze_objects(bp); 14297 bnx2x_free_skbs(bp); 14298 for_each_rx_queue(bp, i) 14299 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 14300 bnx2x_free_fp_mem(bp); 14301 bnx2x_free_mem(bp); 14302 14303 bp->state = BNX2X_STATE_CLOSED; 14304 } 14305 14306 rtnl_unlock(); 14307 14308 return PCI_ERS_RESULT_RECOVERED; 14309 } 14310 14311 /** 14312 * bnx2x_io_resume - called when traffic can start flowing again 14313 * @pdev: Pointer to PCI device 14314 * 14315 * This callback is called when the error recovery driver tells us that 14316 * its OK to resume normal operation. 14317 */ 14318 static void bnx2x_io_resume(struct pci_dev *pdev) 14319 { 14320 struct net_device *dev = pci_get_drvdata(pdev); 14321 struct bnx2x *bp = netdev_priv(dev); 14322 14323 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 14324 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); 14325 return; 14326 } 14327 14328 rtnl_lock(); 14329 14330 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 14331 DRV_MSG_SEQ_NUMBER_MASK; 14332 14333 if (netif_running(dev)) 14334 bnx2x_nic_load(bp, LOAD_NORMAL); 14335 14336 netif_device_attach(dev); 14337 14338 rtnl_unlock(); 14339 } 14340 14341 static const struct pci_error_handlers bnx2x_err_handler = { 14342 .error_detected = bnx2x_io_error_detected, 14343 .slot_reset = bnx2x_io_slot_reset, 14344 .resume = bnx2x_io_resume, 14345 }; 14346 14347 static void bnx2x_shutdown(struct pci_dev *pdev) 14348 { 14349 struct net_device *dev = pci_get_drvdata(pdev); 14350 struct bnx2x *bp; 14351 14352 if (!dev) 14353 return; 14354 14355 bp = netdev_priv(dev); 14356 if (!bp) 14357 return; 14358 14359 rtnl_lock(); 14360 netif_device_detach(dev); 14361 rtnl_unlock(); 14362 14363 /* Don't remove the netdevice, as there are scenarios which will cause 14364 * the kernel to hang, e.g., when trying to remove bnx2i while the 14365 * rootfs is mounted from SAN. 14366 */ 14367 __bnx2x_remove(pdev, dev, bp, false); 14368 } 14369 14370 static struct pci_driver bnx2x_pci_driver = { 14371 .name = DRV_MODULE_NAME, 14372 .id_table = bnx2x_pci_tbl, 14373 .probe = bnx2x_init_one, 14374 .remove = bnx2x_remove_one, 14375 .driver.pm = &bnx2x_pm_ops, 14376 .err_handler = &bnx2x_err_handler, 14377 #ifdef CONFIG_BNX2X_SRIOV 14378 .sriov_configure = bnx2x_sriov_configure, 14379 #endif 14380 .shutdown = bnx2x_shutdown, 14381 }; 14382 14383 static int __init bnx2x_init(void) 14384 { 14385 int ret; 14386 14387 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 14388 if (bnx2x_wq == NULL) { 14389 pr_err("Cannot create workqueue\n"); 14390 return -ENOMEM; 14391 } 14392 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov"); 14393 if (!bnx2x_iov_wq) { 14394 pr_err("Cannot create iov workqueue\n"); 14395 destroy_workqueue(bnx2x_wq); 14396 return -ENOMEM; 14397 } 14398 14399 ret = pci_register_driver(&bnx2x_pci_driver); 14400 if (ret) { 14401 pr_err("Cannot register driver\n"); 14402 destroy_workqueue(bnx2x_wq); 14403 destroy_workqueue(bnx2x_iov_wq); 14404 } 14405 return ret; 14406 } 14407 14408 static void __exit bnx2x_cleanup(void) 14409 { 14410 struct list_head *pos, *q; 14411 14412 pci_unregister_driver(&bnx2x_pci_driver); 14413 14414 destroy_workqueue(bnx2x_wq); 14415 destroy_workqueue(bnx2x_iov_wq); 14416 14417 /* Free globally allocated resources */ 14418 list_for_each_safe(pos, q, &bnx2x_prev_list) { 14419 struct bnx2x_prev_path_list *tmp = 14420 list_entry(pos, struct bnx2x_prev_path_list, list); 14421 list_del(pos); 14422 kfree(tmp); 14423 } 14424 } 14425 14426 void bnx2x_notify_link_changed(struct bnx2x *bp) 14427 { 14428 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 14429 } 14430 14431 module_init(bnx2x_init); 14432 module_exit(bnx2x_cleanup); 14433 14434 /** 14435 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 14436 * @bp: driver handle 14437 * 14438 * This function will wait until the ramrod completion returns. 14439 * Return 0 if success, -ENODEV if ramrod doesn't return. 14440 */ 14441 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 14442 { 14443 unsigned long ramrod_flags = 0; 14444 14445 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 14446 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 14447 &bp->iscsi_l2_mac_obj, true, 14448 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 14449 } 14450 14451 /* count denotes the number of new completions we have seen */ 14452 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 14453 { 14454 struct eth_spe *spe; 14455 int cxt_index, cxt_offset; 14456 14457 #ifdef BNX2X_STOP_ON_ERROR 14458 if (unlikely(bp->panic)) 14459 return; 14460 #endif 14461 14462 spin_lock_bh(&bp->spq_lock); 14463 BUG_ON(bp->cnic_spq_pending < count); 14464 bp->cnic_spq_pending -= count; 14465 14466 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 14467 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 14468 & SPE_HDR_CONN_TYPE) >> 14469 SPE_HDR_CONN_TYPE_SHIFT; 14470 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 14471 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 14472 14473 /* Set validation for iSCSI L2 client before sending SETUP 14474 * ramrod 14475 */ 14476 if (type == ETH_CONNECTION_TYPE) { 14477 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { 14478 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / 14479 ILT_PAGE_CIDS; 14480 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - 14481 (cxt_index * ILT_PAGE_CIDS); 14482 bnx2x_set_ctx_validation(bp, 14483 &bp->context[cxt_index]. 14484 vcxt[cxt_offset].eth, 14485 BNX2X_ISCSI_ETH_CID(bp)); 14486 } 14487 } 14488 14489 /* 14490 * There may be not more than 8 L2, not more than 8 L5 SPEs 14491 * and in the air. We also check that number of outstanding 14492 * COMMON ramrods is not more than the EQ and SPQ can 14493 * accommodate. 14494 */ 14495 if (type == ETH_CONNECTION_TYPE) { 14496 if (!atomic_read(&bp->cq_spq_left)) 14497 break; 14498 else 14499 atomic_dec(&bp->cq_spq_left); 14500 } else if (type == NONE_CONNECTION_TYPE) { 14501 if (!atomic_read(&bp->eq_spq_left)) 14502 break; 14503 else 14504 atomic_dec(&bp->eq_spq_left); 14505 } else if ((type == ISCSI_CONNECTION_TYPE) || 14506 (type == FCOE_CONNECTION_TYPE)) { 14507 if (bp->cnic_spq_pending >= 14508 bp->cnic_eth_dev.max_kwqe_pending) 14509 break; 14510 else 14511 bp->cnic_spq_pending++; 14512 } else { 14513 BNX2X_ERR("Unknown SPE type: %d\n", type); 14514 bnx2x_panic(); 14515 break; 14516 } 14517 14518 spe = bnx2x_sp_get_next(bp); 14519 *spe = *bp->cnic_kwq_cons; 14520 14521 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", 14522 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 14523 14524 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 14525 bp->cnic_kwq_cons = bp->cnic_kwq; 14526 else 14527 bp->cnic_kwq_cons++; 14528 } 14529 bnx2x_sp_prod_update(bp); 14530 spin_unlock_bh(&bp->spq_lock); 14531 } 14532 14533 static int bnx2x_cnic_sp_queue(struct net_device *dev, 14534 struct kwqe_16 *kwqes[], u32 count) 14535 { 14536 struct bnx2x *bp = netdev_priv(dev); 14537 int i; 14538 14539 #ifdef BNX2X_STOP_ON_ERROR 14540 if (unlikely(bp->panic)) { 14541 BNX2X_ERR("Can't post to SP queue while panic\n"); 14542 return -EIO; 14543 } 14544 #endif 14545 14546 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 14547 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 14548 BNX2X_ERR("Handling parity error recovery. Try again later\n"); 14549 return -EAGAIN; 14550 } 14551 14552 spin_lock_bh(&bp->spq_lock); 14553 14554 for (i = 0; i < count; i++) { 14555 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 14556 14557 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 14558 break; 14559 14560 *bp->cnic_kwq_prod = *spe; 14561 14562 bp->cnic_kwq_pending++; 14563 14564 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", 14565 spe->hdr.conn_and_cmd_data, spe->hdr.type, 14566 spe->data.update_data_addr.hi, 14567 spe->data.update_data_addr.lo, 14568 bp->cnic_kwq_pending); 14569 14570 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 14571 bp->cnic_kwq_prod = bp->cnic_kwq; 14572 else 14573 bp->cnic_kwq_prod++; 14574 } 14575 14576 spin_unlock_bh(&bp->spq_lock); 14577 14578 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 14579 bnx2x_cnic_sp_post(bp, 0); 14580 14581 return i; 14582 } 14583 14584 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 14585 { 14586 struct cnic_ops *c_ops; 14587 int rc = 0; 14588 14589 mutex_lock(&bp->cnic_mutex); 14590 c_ops = rcu_dereference_protected(bp->cnic_ops, 14591 lockdep_is_held(&bp->cnic_mutex)); 14592 if (c_ops) 14593 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 14594 mutex_unlock(&bp->cnic_mutex); 14595 14596 return rc; 14597 } 14598 14599 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 14600 { 14601 struct cnic_ops *c_ops; 14602 int rc = 0; 14603 14604 rcu_read_lock(); 14605 c_ops = rcu_dereference(bp->cnic_ops); 14606 if (c_ops) 14607 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 14608 rcu_read_unlock(); 14609 14610 return rc; 14611 } 14612 14613 /* 14614 * for commands that have no data 14615 */ 14616 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 14617 { 14618 struct cnic_ctl_info ctl = {0}; 14619 14620 ctl.cmd = cmd; 14621 14622 return bnx2x_cnic_ctl_send(bp, &ctl); 14623 } 14624 14625 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 14626 { 14627 struct cnic_ctl_info ctl = {0}; 14628 14629 /* first we tell CNIC and only then we count this as a completion */ 14630 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 14631 ctl.data.comp.cid = cid; 14632 ctl.data.comp.error = err; 14633 14634 bnx2x_cnic_ctl_send_bh(bp, &ctl); 14635 bnx2x_cnic_sp_post(bp, 0); 14636 } 14637 14638 /* Called with netif_addr_lock_bh() taken. 14639 * Sets an rx_mode config for an iSCSI ETH client. 14640 * Doesn't block. 14641 * Completion should be checked outside. 14642 */ 14643 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 14644 { 14645 unsigned long accept_flags = 0, ramrod_flags = 0; 14646 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 14647 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 14648 14649 if (start) { 14650 /* Start accepting on iSCSI L2 ring. Accept all multicasts 14651 * because it's the only way for UIO Queue to accept 14652 * multicasts (in non-promiscuous mode only one Queue per 14653 * function will receive multicast packets (leading in our 14654 * case). 14655 */ 14656 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 14657 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 14658 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 14659 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 14660 14661 /* Clear STOP_PENDING bit if START is requested */ 14662 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 14663 14664 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 14665 } else 14666 /* Clear START_PENDING bit if STOP is requested */ 14667 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 14668 14669 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 14670 set_bit(sched_state, &bp->sp_state); 14671 else { 14672 __set_bit(RAMROD_RX, &ramrod_flags); 14673 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 14674 ramrod_flags); 14675 } 14676 } 14677 14678 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 14679 { 14680 struct bnx2x *bp = netdev_priv(dev); 14681 int rc = 0; 14682 14683 switch (ctl->cmd) { 14684 case DRV_CTL_CTXTBL_WR_CMD: { 14685 u32 index = ctl->data.io.offset; 14686 dma_addr_t addr = ctl->data.io.dma_addr; 14687 14688 bnx2x_ilt_wr(bp, index, addr); 14689 break; 14690 } 14691 14692 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 14693 int count = ctl->data.credit.credit_count; 14694 14695 bnx2x_cnic_sp_post(bp, count); 14696 break; 14697 } 14698 14699 /* rtnl_lock is held. */ 14700 case DRV_CTL_START_L2_CMD: { 14701 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14702 unsigned long sp_bits = 0; 14703 14704 /* Configure the iSCSI classification object */ 14705 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 14706 cp->iscsi_l2_client_id, 14707 cp->iscsi_l2_cid, BP_FUNC(bp), 14708 bnx2x_sp(bp, mac_rdata), 14709 bnx2x_sp_mapping(bp, mac_rdata), 14710 BNX2X_FILTER_MAC_PENDING, 14711 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 14712 &bp->macs_pool); 14713 14714 /* Set iSCSI MAC address */ 14715 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 14716 if (rc) 14717 break; 14718 14719 barrier(); 14720 14721 /* Start accepting on iSCSI L2 ring */ 14722 14723 netif_addr_lock_bh(dev); 14724 bnx2x_set_iscsi_eth_rx_mode(bp, true); 14725 netif_addr_unlock_bh(dev); 14726 14727 /* bits to wait on */ 14728 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 14729 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 14730 14731 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 14732 BNX2X_ERR("rx_mode completion timed out!\n"); 14733 14734 break; 14735 } 14736 14737 /* rtnl_lock is held. */ 14738 case DRV_CTL_STOP_L2_CMD: { 14739 unsigned long sp_bits = 0; 14740 14741 /* Stop accepting on iSCSI L2 ring */ 14742 netif_addr_lock_bh(dev); 14743 bnx2x_set_iscsi_eth_rx_mode(bp, false); 14744 netif_addr_unlock_bh(dev); 14745 14746 /* bits to wait on */ 14747 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 14748 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 14749 14750 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 14751 BNX2X_ERR("rx_mode completion timed out!\n"); 14752 14753 barrier(); 14754 14755 /* Unset iSCSI L2 MAC */ 14756 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 14757 BNX2X_ISCSI_ETH_MAC, true); 14758 break; 14759 } 14760 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 14761 int count = ctl->data.credit.credit_count; 14762 14763 smp_mb__before_atomic(); 14764 atomic_add(count, &bp->cq_spq_left); 14765 smp_mb__after_atomic(); 14766 break; 14767 } 14768 case DRV_CTL_ULP_REGISTER_CMD: { 14769 int ulp_type = ctl->data.register_data.ulp_type; 14770 14771 if (CHIP_IS_E3(bp)) { 14772 int idx = BP_FW_MB_IDX(bp); 14773 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 14774 int path = BP_PATH(bp); 14775 int port = BP_PORT(bp); 14776 int i; 14777 u32 scratch_offset; 14778 u32 *host_addr; 14779 14780 /* first write capability to shmem2 */ 14781 if (ulp_type == CNIC_ULP_ISCSI) 14782 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 14783 else if (ulp_type == CNIC_ULP_FCOE) 14784 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 14785 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 14786 14787 if ((ulp_type != CNIC_ULP_FCOE) || 14788 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || 14789 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) 14790 break; 14791 14792 /* if reached here - should write fcoe capabilities */ 14793 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); 14794 if (!scratch_offset) 14795 break; 14796 scratch_offset += offsetof(struct glob_ncsi_oem_data, 14797 fcoe_features[path][port]); 14798 host_addr = (u32 *) &(ctl->data.register_data. 14799 fcoe_features); 14800 for (i = 0; i < sizeof(struct fcoe_capabilities); 14801 i += 4) 14802 REG_WR(bp, scratch_offset + i, 14803 *(host_addr + i/4)); 14804 } 14805 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14806 break; 14807 } 14808 14809 case DRV_CTL_ULP_UNREGISTER_CMD: { 14810 int ulp_type = ctl->data.ulp_type; 14811 14812 if (CHIP_IS_E3(bp)) { 14813 int idx = BP_FW_MB_IDX(bp); 14814 u32 cap; 14815 14816 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 14817 if (ulp_type == CNIC_ULP_ISCSI) 14818 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 14819 else if (ulp_type == CNIC_ULP_FCOE) 14820 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 14821 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 14822 } 14823 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14824 break; 14825 } 14826 14827 default: 14828 BNX2X_ERR("unknown command %x\n", ctl->cmd); 14829 rc = -EINVAL; 14830 } 14831 14832 /* For storage-only interfaces, change driver state */ 14833 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { 14834 switch (ctl->drv_state) { 14835 case DRV_NOP: 14836 break; 14837 case DRV_ACTIVE: 14838 bnx2x_set_os_driver_state(bp, 14839 OS_DRIVER_STATE_ACTIVE); 14840 break; 14841 case DRV_INACTIVE: 14842 bnx2x_set_os_driver_state(bp, 14843 OS_DRIVER_STATE_DISABLED); 14844 break; 14845 case DRV_UNLOADED: 14846 bnx2x_set_os_driver_state(bp, 14847 OS_DRIVER_STATE_NOT_LOADED); 14848 break; 14849 default: 14850 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state); 14851 } 14852 } 14853 14854 return rc; 14855 } 14856 14857 static int bnx2x_get_fc_npiv(struct net_device *dev, 14858 struct cnic_fc_npiv_tbl *cnic_tbl) 14859 { 14860 struct bnx2x *bp = netdev_priv(dev); 14861 struct bdn_fc_npiv_tbl *tbl = NULL; 14862 u32 offset, entries; 14863 int rc = -EINVAL; 14864 int i; 14865 14866 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) 14867 goto out; 14868 14869 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n"); 14870 14871 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL); 14872 if (!tbl) { 14873 BNX2X_ERR("Failed to allocate fc_npiv table\n"); 14874 goto out; 14875 } 14876 14877 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); 14878 if (!offset) { 14879 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n"); 14880 goto out; 14881 } 14882 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset); 14883 14884 /* Read the table contents from nvram */ 14885 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { 14886 BNX2X_ERR("Failed to read FC-NPIV table\n"); 14887 goto out; 14888 } 14889 14890 /* Since bnx2x_nvram_read() returns data in be32, we need to convert 14891 * the number of entries back to cpu endianness. 14892 */ 14893 entries = tbl->fc_npiv_cfg.num_of_npiv; 14894 entries = (__force u32)be32_to_cpu((__force __be32)entries); 14895 tbl->fc_npiv_cfg.num_of_npiv = entries; 14896 14897 if (!tbl->fc_npiv_cfg.num_of_npiv) { 14898 DP(BNX2X_MSG_MCP, 14899 "No FC-NPIV table [valid, simply not present]\n"); 14900 goto out; 14901 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) { 14902 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", 14903 tbl->fc_npiv_cfg.num_of_npiv); 14904 goto out; 14905 } else { 14906 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n", 14907 tbl->fc_npiv_cfg.num_of_npiv); 14908 } 14909 14910 /* Copy the data into cnic-provided struct */ 14911 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; 14912 for (i = 0; i < cnic_tbl->count; i++) { 14913 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8); 14914 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8); 14915 } 14916 14917 rc = 0; 14918 out: 14919 kfree(tbl); 14920 return rc; 14921 } 14922 14923 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 14924 { 14925 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14926 14927 if (bp->flags & USING_MSIX_FLAG) { 14928 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 14929 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 14930 cp->irq_arr[0].vector = bp->msix_table[1].vector; 14931 } else { 14932 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 14933 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 14934 } 14935 if (!CHIP_IS_E1x(bp)) 14936 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 14937 else 14938 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 14939 14940 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 14941 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 14942 cp->irq_arr[1].status_blk = bp->def_status_blk; 14943 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 14944 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 14945 14946 cp->num_irq = 2; 14947 } 14948 14949 void bnx2x_setup_cnic_info(struct bnx2x *bp) 14950 { 14951 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14952 14953 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 14954 bnx2x_cid_ilt_lines(bp); 14955 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 14956 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 14957 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 14958 14959 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", 14960 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, 14961 cp->iscsi_l2_cid); 14962 14963 if (NO_ISCSI_OOO(bp)) 14964 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 14965 } 14966 14967 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 14968 void *data) 14969 { 14970 struct bnx2x *bp = netdev_priv(dev); 14971 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14972 int rc; 14973 14974 DP(NETIF_MSG_IFUP, "Register_cnic called\n"); 14975 14976 if (ops == NULL) { 14977 BNX2X_ERR("NULL ops received\n"); 14978 return -EINVAL; 14979 } 14980 14981 if (!CNIC_SUPPORT(bp)) { 14982 BNX2X_ERR("Can't register CNIC when not supported\n"); 14983 return -EOPNOTSUPP; 14984 } 14985 14986 if (!CNIC_LOADED(bp)) { 14987 rc = bnx2x_load_cnic(bp); 14988 if (rc) { 14989 BNX2X_ERR("CNIC-related load failed\n"); 14990 return rc; 14991 } 14992 } 14993 14994 bp->cnic_enabled = true; 14995 14996 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 14997 if (!bp->cnic_kwq) 14998 return -ENOMEM; 14999 15000 bp->cnic_kwq_cons = bp->cnic_kwq; 15001 bp->cnic_kwq_prod = bp->cnic_kwq; 15002 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 15003 15004 bp->cnic_spq_pending = 0; 15005 bp->cnic_kwq_pending = 0; 15006 15007 bp->cnic_data = data; 15008 15009 cp->num_irq = 0; 15010 cp->drv_state |= CNIC_DRV_STATE_REGD; 15011 cp->iro_arr = bp->iro_arr; 15012 15013 bnx2x_setup_cnic_irq_info(bp); 15014 15015 rcu_assign_pointer(bp->cnic_ops, ops); 15016 15017 /* Schedule driver to read CNIC driver versions */ 15018 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 15019 15020 return 0; 15021 } 15022 15023 static int bnx2x_unregister_cnic(struct net_device *dev) 15024 { 15025 struct bnx2x *bp = netdev_priv(dev); 15026 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 15027 15028 mutex_lock(&bp->cnic_mutex); 15029 cp->drv_state = 0; 15030 RCU_INIT_POINTER(bp->cnic_ops, NULL); 15031 mutex_unlock(&bp->cnic_mutex); 15032 synchronize_rcu(); 15033 bp->cnic_enabled = false; 15034 kfree(bp->cnic_kwq); 15035 bp->cnic_kwq = NULL; 15036 15037 return 0; 15038 } 15039 15040 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 15041 { 15042 struct bnx2x *bp = netdev_priv(dev); 15043 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 15044 15045 /* If both iSCSI and FCoE are disabled - return NULL in 15046 * order to indicate CNIC that it should not try to work 15047 * with this device. 15048 */ 15049 if (NO_ISCSI(bp) && NO_FCOE(bp)) 15050 return NULL; 15051 15052 cp->drv_owner = THIS_MODULE; 15053 cp->chip_id = CHIP_ID(bp); 15054 cp->pdev = bp->pdev; 15055 cp->io_base = bp->regview; 15056 cp->io_base2 = bp->doorbells; 15057 cp->max_kwqe_pending = 8; 15058 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 15059 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 15060 bnx2x_cid_ilt_lines(bp); 15061 cp->ctx_tbl_len = CNIC_ILT_LINES; 15062 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 15063 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 15064 cp->drv_ctl = bnx2x_drv_ctl; 15065 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv; 15066 cp->drv_register_cnic = bnx2x_register_cnic; 15067 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 15068 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 15069 cp->iscsi_l2_client_id = 15070 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 15071 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 15072 15073 if (NO_ISCSI_OOO(bp)) 15074 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 15075 15076 if (NO_ISCSI(bp)) 15077 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 15078 15079 if (NO_FCOE(bp)) 15080 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 15081 15082 BNX2X_DEV_INFO( 15083 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", 15084 cp->ctx_blk_size, 15085 cp->ctx_tbl_offset, 15086 cp->ctx_tbl_len, 15087 cp->starting_cid); 15088 return cp; 15089 } 15090 15091 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 15092 { 15093 struct bnx2x *bp = fp->bp; 15094 u32 offset = BAR_USTRORM_INTMEM; 15095 15096 if (IS_VF(bp)) 15097 return bnx2x_vf_ustorm_prods_offset(bp, fp); 15098 else if (!CHIP_IS_E1x(bp)) 15099 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 15100 else 15101 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 15102 15103 return offset; 15104 } 15105 15106 /* called only on E1H or E2. 15107 * When pretending to be PF, the pretend value is the function number 0...7 15108 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 15109 * combination 15110 */ 15111 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) 15112 { 15113 u32 pretend_reg; 15114 15115 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) 15116 return -1; 15117 15118 /* get my own pretend register */ 15119 pretend_reg = bnx2x_get_pretend_reg(bp); 15120 REG_WR(bp, pretend_reg, pretend_func_val); 15121 REG_RD(bp, pretend_reg); 15122 return 0; 15123 } 15124 15125 static void bnx2x_ptp_task(struct work_struct *work) 15126 { 15127 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); 15128 int port = BP_PORT(bp); 15129 u32 val_seq; 15130 u64 timestamp, ns; 15131 struct skb_shared_hwtstamps shhwtstamps; 15132 bool bail = true; 15133 int i; 15134 15135 /* FW may take a while to complete timestamping; try a bit and if it's 15136 * still not complete, may indicate an error state - bail out then. 15137 */ 15138 for (i = 0; i < 10; i++) { 15139 /* Read Tx timestamp registers */ 15140 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15141 NIG_REG_P0_TLLH_PTP_BUF_SEQID); 15142 if (val_seq & 0x10000) { 15143 bail = false; 15144 break; 15145 } 15146 msleep(1 << i); 15147 } 15148 15149 if (!bail) { 15150 /* There is a valid timestamp value */ 15151 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : 15152 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB); 15153 timestamp <<= 32; 15154 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : 15155 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); 15156 /* Reset timestamp register to allow new timestamp */ 15157 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15158 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); 15159 ns = timecounter_cyc2time(&bp->timecounter, timestamp); 15160 15161 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 15162 shhwtstamps.hwtstamp = ns_to_ktime(ns); 15163 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); 15164 15165 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", 15166 timestamp, ns); 15167 } else { 15168 DP(BNX2X_MSG_PTP, 15169 "Tx timestamp is not recorded (register read=%u)\n", 15170 val_seq); 15171 bp->eth_stats.ptp_skip_tx_ts++; 15172 } 15173 15174 dev_kfree_skb_any(bp->ptp_tx_skb); 15175 bp->ptp_tx_skb = NULL; 15176 } 15177 15178 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) 15179 { 15180 int port = BP_PORT(bp); 15181 u64 timestamp, ns; 15182 15183 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : 15184 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB); 15185 timestamp <<= 32; 15186 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : 15187 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB); 15188 15189 /* Reset timestamp register to allow new timestamp */ 15190 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : 15191 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); 15192 15193 ns = timecounter_cyc2time(&bp->timecounter, timestamp); 15194 15195 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 15196 15197 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", 15198 timestamp, ns); 15199 } 15200 15201 /* Read the PHC */ 15202 static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc) 15203 { 15204 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); 15205 int port = BP_PORT(bp); 15206 u32 wb_data[2]; 15207 u64 phc_cycles; 15208 15209 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : 15210 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); 15211 phc_cycles = wb_data[1]; 15212 phc_cycles = (phc_cycles << 32) + wb_data[0]; 15213 15214 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); 15215 15216 return phc_cycles; 15217 } 15218 15219 static void bnx2x_init_cyclecounter(struct bnx2x *bp) 15220 { 15221 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); 15222 bp->cyclecounter.read = bnx2x_cyclecounter_read; 15223 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); 15224 bp->cyclecounter.shift = 0; 15225 bp->cyclecounter.mult = 1; 15226 } 15227 15228 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) 15229 { 15230 struct bnx2x_func_state_params func_params = {NULL}; 15231 struct bnx2x_func_set_timesync_params *set_timesync_params = 15232 &func_params.params.set_timesync; 15233 15234 /* Prepare parameters for function state transitions */ 15235 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 15236 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 15237 15238 func_params.f_obj = &bp->func_obj; 15239 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; 15240 15241 /* Function parameters */ 15242 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; 15243 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; 15244 15245 return bnx2x_func_state_change(bp, &func_params); 15246 } 15247 15248 static int bnx2x_enable_ptp_packets(struct bnx2x *bp) 15249 { 15250 struct bnx2x_queue_state_params q_params; 15251 int rc, i; 15252 15253 /* send queue update ramrod to enable PTP packets */ 15254 memset(&q_params, 0, sizeof(q_params)); 15255 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 15256 q_params.cmd = BNX2X_Q_CMD_UPDATE; 15257 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, 15258 &q_params.params.update.update_flags); 15259 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS, 15260 &q_params.params.update.update_flags); 15261 15262 /* send the ramrod on all the queues of the PF */ 15263 for_each_eth_queue(bp, i) { 15264 struct bnx2x_fastpath *fp = &bp->fp[i]; 15265 15266 /* Set the appropriate Queue object */ 15267 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 15268 15269 /* Update the Queue state */ 15270 rc = bnx2x_queue_state_change(bp, &q_params); 15271 if (rc) { 15272 BNX2X_ERR("Failed to enable PTP packets\n"); 15273 return rc; 15274 } 15275 } 15276 15277 return 0; 15278 } 15279 15280 #define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5 15281 #define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB 15282 #define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) 15283 #define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) 15284 #define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE) 15285 #define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE) 15286 #define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA) 15287 #define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE) 15288 #define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF) 15289 #define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF) 15290 #define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) 15291 #define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) 15292 15293 int bnx2x_configure_ptp_filters(struct bnx2x *bp) 15294 { 15295 int port = BP_PORT(bp); 15296 u32 param, rule; 15297 int rc; 15298 15299 if (!bp->hwtstamp_ioctl_called) 15300 return 0; 15301 15302 param = port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 15303 NIG_REG_P0_TLLH_PTP_PARAM_MASK; 15304 rule = port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 15305 NIG_REG_P0_TLLH_PTP_RULE_MASK; 15306 switch (bp->tx_type) { 15307 case HWTSTAMP_TX_ON: 15308 bp->flags |= TX_TIMESTAMPING_EN; 15309 REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK); 15310 REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK); 15311 break; 15312 case HWTSTAMP_TX_ONESTEP_SYNC: 15313 case HWTSTAMP_TX_ONESTEP_P2P: 15314 BNX2X_ERR("One-step timestamping is not supported\n"); 15315 return -ERANGE; 15316 } 15317 15318 param = port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 15319 NIG_REG_P0_LLH_PTP_PARAM_MASK; 15320 rule = port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 15321 NIG_REG_P0_LLH_PTP_RULE_MASK; 15322 switch (bp->rx_filter) { 15323 case HWTSTAMP_FILTER_NONE: 15324 break; 15325 case HWTSTAMP_FILTER_ALL: 15326 case HWTSTAMP_FILTER_SOME: 15327 case HWTSTAMP_FILTER_NTP_ALL: 15328 bp->rx_filter = HWTSTAMP_FILTER_NONE; 15329 break; 15330 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 15331 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 15332 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 15333 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 15334 /* Initialize PTP detection for UDP/IPv4 events */ 15335 REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK); 15336 REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK); 15337 break; 15338 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 15339 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 15340 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 15341 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 15342 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ 15343 REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK); 15344 REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK); 15345 break; 15346 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 15347 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 15348 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 15349 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 15350 /* Initialize PTP detection L2 events */ 15351 REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK); 15352 REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK); 15353 15354 break; 15355 case HWTSTAMP_FILTER_PTP_V2_EVENT: 15356 case HWTSTAMP_FILTER_PTP_V2_SYNC: 15357 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 15358 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 15359 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ 15360 REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK); 15361 REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK); 15362 break; 15363 } 15364 15365 /* Indicate to FW that this PF expects recorded PTP packets */ 15366 rc = bnx2x_enable_ptp_packets(bp); 15367 if (rc) 15368 return rc; 15369 15370 /* Enable sending PTP packets to host */ 15371 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 15372 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); 15373 15374 return 0; 15375 } 15376 15377 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) 15378 { 15379 struct hwtstamp_config config; 15380 int rc; 15381 15382 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n"); 15383 15384 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 15385 return -EFAULT; 15386 15387 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", 15388 config.tx_type, config.rx_filter); 15389 15390 bp->hwtstamp_ioctl_called = true; 15391 bp->tx_type = config.tx_type; 15392 bp->rx_filter = config.rx_filter; 15393 15394 rc = bnx2x_configure_ptp_filters(bp); 15395 if (rc) 15396 return rc; 15397 15398 config.rx_filter = bp->rx_filter; 15399 15400 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 15401 -EFAULT : 0; 15402 } 15403 15404 /* Configures HW for PTP */ 15405 static int bnx2x_configure_ptp(struct bnx2x *bp) 15406 { 15407 int rc, port = BP_PORT(bp); 15408 u32 wb_data[2]; 15409 15410 /* Reset PTP event detection rules - will be configured in the IOCTL */ 15411 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 15412 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); 15413 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 15414 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); 15415 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 15416 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); 15417 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 15418 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); 15419 15420 /* Disable PTP packets to host - will be configured in the IOCTL*/ 15421 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 15422 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); 15423 15424 /* Enable the PTP feature */ 15425 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : 15426 NIG_REG_P0_PTP_EN, 0x3F); 15427 15428 /* Enable the free-running counter */ 15429 wb_data[0] = 0; 15430 wb_data[1] = 0; 15431 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); 15432 15433 /* Reset drift register (offset register is not reset) */ 15434 rc = bnx2x_send_reset_timesync_ramrod(bp); 15435 if (rc) { 15436 BNX2X_ERR("Failed to reset PHC drift register\n"); 15437 return -EFAULT; 15438 } 15439 15440 /* Reset possibly old timestamps */ 15441 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : 15442 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); 15443 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15444 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); 15445 15446 return 0; 15447 } 15448 15449 /* Called during load, to initialize PTP-related stuff */ 15450 void bnx2x_init_ptp(struct bnx2x *bp) 15451 { 15452 int rc; 15453 15454 /* Configure PTP in HW */ 15455 rc = bnx2x_configure_ptp(bp); 15456 if (rc) { 15457 BNX2X_ERR("Stopping PTP initialization\n"); 15458 return; 15459 } 15460 15461 /* Init work queue for Tx timestamping */ 15462 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); 15463 15464 /* Init cyclecounter and timecounter. This is done only in the first 15465 * load. If done in every load, PTP application will fail when doing 15466 * unload / load (e.g. MTU change) while it is running. 15467 */ 15468 if (!bp->timecounter_init_done) { 15469 bnx2x_init_cyclecounter(bp); 15470 timecounter_init(&bp->timecounter, &bp->cyclecounter, 15471 ktime_to_ns(ktime_get_real())); 15472 bp->timecounter_init_done = true; 15473 } 15474 15475 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); 15476 } 15477