1 /* bnx2x_ethtool.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/ethtool.h> 21 #include <linux/netdevice.h> 22 #include <linux/types.h> 23 #include <linux/sched.h> 24 #include <linux/crc32.h> 25 #include "bnx2x.h" 26 #include "bnx2x_cmn.h" 27 #include "bnx2x_dump.h" 28 #include "bnx2x_init.h" 29 30 /* Note: in the format strings below %s is replaced by the queue-name which is 31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33 */ 34 #define MAX_QUEUE_NAME_LEN 4 35 static const struct { 36 long offset; 37 int size; 38 char string[ETH_GSTRING_LEN]; 39 } bnx2x_q_stats_arr[] = { 40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42 8, "[%s]: rx_ucast_packets" }, 43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44 8, "[%s]: rx_mcast_packets" }, 45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46 8, "[%s]: rx_bcast_packets" }, 47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48 { Q_STATS_OFFSET32(rx_err_discard_pkt), 49 4, "[%s]: rx_phy_ip_err_discards"}, 50 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51 4, "[%s]: rx_skb_alloc_discard" }, 52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56 8, "[%s]: tx_ucast_packets" }, 57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58 8, "[%s]: tx_mcast_packets" }, 59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60 8, "[%s]: tx_bcast_packets" }, 61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62 8, "[%s]: tpa_aggregations" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64 8, "[%s]: tpa_aggregated_frames"}, 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67 4, "[%s]: driver_filtered_tx_pkt" } 68 }; 69 70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71 72 static const struct { 73 long offset; 74 int size; 75 u32 flags; 76 #define STATS_FLAGS_PORT 1 77 #define STATS_FLAGS_FUNC 2 78 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79 char string[ETH_GSTRING_LEN]; 80 } bnx2x_stats_arr[] = { 81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83 { STATS_OFFSET32(error_bytes_received_hi), 84 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85 { STATS_OFFSET32(total_unicast_packets_received_hi), 86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87 { STATS_OFFSET32(total_multicast_packets_received_hi), 88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89 { STATS_OFFSET32(total_broadcast_packets_received_hi), 90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100 8, STATS_FLAGS_PORT, "rx_fragments" }, 101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103 { STATS_OFFSET32(no_buff_discard_hi), 104 8, STATS_FLAGS_BOTH, "rx_discards" }, 105 { STATS_OFFSET32(mac_filter_discard), 106 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107 { STATS_OFFSET32(mf_tag_discard), 108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 109 { STATS_OFFSET32(pfc_frames_received_hi), 110 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 111 { STATS_OFFSET32(pfc_frames_sent_hi), 112 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113 { STATS_OFFSET32(brb_drop_hi), 114 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115 { STATS_OFFSET32(brb_truncate_hi), 116 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117 { STATS_OFFSET32(pause_frames_received_hi), 118 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121 { STATS_OFFSET32(nig_timer_max), 122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125 { STATS_OFFSET32(rx_skb_alloc_failed), 126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127 { STATS_OFFSET32(hw_csum_err), 128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129 130 { STATS_OFFSET32(total_bytes_transmitted_hi), 131 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149 8, STATS_FLAGS_PORT, "tx_deferred" }, 150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170 { STATS_OFFSET32(pause_frames_sent_hi), 171 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172 { STATS_OFFSET32(total_tpa_aggregations_hi), 173 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176 { STATS_OFFSET32(total_tpa_bytes_hi), 177 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 178 { STATS_OFFSET32(recoverable_error), 179 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 180 { STATS_OFFSET32(unrecoverable_error), 181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182 { STATS_OFFSET32(driver_filtered_tx_pkt), 183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184 { STATS_OFFSET32(eee_tx_lpi), 185 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186 }; 187 188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 189 190 static int bnx2x_get_port_type(struct bnx2x *bp) 191 { 192 int port_type; 193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194 switch (bp->link_params.phy[phy_idx].media_type) { 195 case ETH_PHY_SFPP_10G_FIBER: 196 case ETH_PHY_SFP_1G_FIBER: 197 case ETH_PHY_XFP_FIBER: 198 case ETH_PHY_KR: 199 case ETH_PHY_CX4: 200 port_type = PORT_FIBRE; 201 break; 202 case ETH_PHY_DA_TWINAX: 203 port_type = PORT_DA; 204 break; 205 case ETH_PHY_BASE_T: 206 port_type = PORT_TP; 207 break; 208 case ETH_PHY_NOT_PRESENT: 209 port_type = PORT_NONE; 210 break; 211 case ETH_PHY_UNSPECIFIED: 212 default: 213 port_type = PORT_OTHER; 214 break; 215 } 216 return port_type; 217 } 218 219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 220 { 221 struct bnx2x *bp = netdev_priv(dev); 222 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 223 224 /* Dual Media boards present all available port types */ 225 cmd->supported = bp->port.supported[cfg_idx] | 226 (bp->port.supported[cfg_idx ^ 1] & 227 (SUPPORTED_TP | SUPPORTED_FIBRE)); 228 cmd->advertising = bp->port.advertising[cfg_idx]; 229 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 230 ETH_PHY_SFP_1G_FIBER) { 231 cmd->supported &= ~(SUPPORTED_10000baseT_Full); 232 cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 233 } 234 235 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 236 !(bp->flags & MF_FUNC_DIS)) { 237 cmd->duplex = bp->link_vars.duplex; 238 239 if (IS_MF(bp) && !BP_NOMCP(bp)) 240 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 241 else 242 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 243 } else { 244 cmd->duplex = DUPLEX_UNKNOWN; 245 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 246 } 247 248 cmd->port = bnx2x_get_port_type(bp); 249 250 cmd->phy_address = bp->mdio.prtad; 251 cmd->transceiver = XCVR_INTERNAL; 252 253 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 254 cmd->autoneg = AUTONEG_ENABLE; 255 else 256 cmd->autoneg = AUTONEG_DISABLE; 257 258 /* Publish LP advertised speeds and FC */ 259 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 260 u32 status = bp->link_vars.link_status; 261 262 cmd->lp_advertising |= ADVERTISED_Autoneg; 263 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 264 cmd->lp_advertising |= ADVERTISED_Pause; 265 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 266 cmd->lp_advertising |= ADVERTISED_Asym_Pause; 267 268 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 269 cmd->lp_advertising |= ADVERTISED_10baseT_Half; 270 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 271 cmd->lp_advertising |= ADVERTISED_10baseT_Full; 272 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 273 cmd->lp_advertising |= ADVERTISED_100baseT_Half; 274 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 275 cmd->lp_advertising |= ADVERTISED_100baseT_Full; 276 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 277 cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 278 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 279 cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 280 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 281 cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 282 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 283 cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 284 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 285 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 286 } 287 288 cmd->maxtxpkt = 0; 289 cmd->maxrxpkt = 0; 290 291 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 292 " supported 0x%x advertising 0x%x speed %u\n" 293 " duplex %d port %d phy_address %d transceiver %d\n" 294 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 295 cmd->cmd, cmd->supported, cmd->advertising, 296 ethtool_cmd_speed(cmd), 297 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 298 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 299 300 return 0; 301 } 302 303 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 304 { 305 struct bnx2x *bp = netdev_priv(dev); 306 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 307 u32 speed, phy_idx; 308 309 if (IS_MF_SD(bp)) 310 return 0; 311 312 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 313 " supported 0x%x advertising 0x%x speed %u\n" 314 " duplex %d port %d phy_address %d transceiver %d\n" 315 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 316 cmd->cmd, cmd->supported, cmd->advertising, 317 ethtool_cmd_speed(cmd), 318 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 319 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 320 321 speed = ethtool_cmd_speed(cmd); 322 323 /* If received a request for an unknown duplex, assume full*/ 324 if (cmd->duplex == DUPLEX_UNKNOWN) 325 cmd->duplex = DUPLEX_FULL; 326 327 if (IS_MF_SI(bp)) { 328 u32 part; 329 u32 line_speed = bp->link_vars.line_speed; 330 331 /* use 10G if no link detected */ 332 if (!line_speed) 333 line_speed = 10000; 334 335 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 336 DP(BNX2X_MSG_ETHTOOL, 337 "To set speed BC %X or higher is required, please upgrade BC\n", 338 REQ_BC_VER_4_SET_MF_BW); 339 return -EINVAL; 340 } 341 342 part = (speed * 100) / line_speed; 343 344 if (line_speed < speed || !part) { 345 DP(BNX2X_MSG_ETHTOOL, 346 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 347 return -EINVAL; 348 } 349 350 if (bp->state != BNX2X_STATE_OPEN) 351 /* store value for following "load" */ 352 bp->pending_max = part; 353 else 354 bnx2x_update_max_mf_config(bp, part); 355 356 return 0; 357 } 358 359 cfg_idx = bnx2x_get_link_cfg_idx(bp); 360 old_multi_phy_config = bp->link_params.multi_phy_config; 361 switch (cmd->port) { 362 case PORT_TP: 363 if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 364 break; /* no port change */ 365 366 if (!(bp->port.supported[0] & SUPPORTED_TP || 367 bp->port.supported[1] & SUPPORTED_TP)) { 368 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 369 return -EINVAL; 370 } 371 bp->link_params.multi_phy_config &= 372 ~PORT_HW_CFG_PHY_SELECTION_MASK; 373 if (bp->link_params.multi_phy_config & 374 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 375 bp->link_params.multi_phy_config |= 376 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 377 else 378 bp->link_params.multi_phy_config |= 379 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 380 break; 381 case PORT_FIBRE: 382 case PORT_DA: 383 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 384 break; /* no port change */ 385 386 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 387 bp->port.supported[1] & SUPPORTED_FIBRE)) { 388 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 389 return -EINVAL; 390 } 391 bp->link_params.multi_phy_config &= 392 ~PORT_HW_CFG_PHY_SELECTION_MASK; 393 if (bp->link_params.multi_phy_config & 394 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 395 bp->link_params.multi_phy_config |= 396 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 397 else 398 bp->link_params.multi_phy_config |= 399 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 400 break; 401 default: 402 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 403 return -EINVAL; 404 } 405 /* Save new config in case command complete successfully */ 406 new_multi_phy_config = bp->link_params.multi_phy_config; 407 /* Get the new cfg_idx */ 408 cfg_idx = bnx2x_get_link_cfg_idx(bp); 409 /* Restore old config in case command failed */ 410 bp->link_params.multi_phy_config = old_multi_phy_config; 411 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 412 413 if (cmd->autoneg == AUTONEG_ENABLE) { 414 u32 an_supported_speed = bp->port.supported[cfg_idx]; 415 if (bp->link_params.phy[EXT_PHY1].type == 416 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 417 an_supported_speed |= (SUPPORTED_100baseT_Half | 418 SUPPORTED_100baseT_Full); 419 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 420 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 421 return -EINVAL; 422 } 423 424 /* advertise the requested speed and duplex if supported */ 425 if (cmd->advertising & ~an_supported_speed) { 426 DP(BNX2X_MSG_ETHTOOL, 427 "Advertisement parameters are not supported\n"); 428 return -EINVAL; 429 } 430 431 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 432 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 433 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 434 cmd->advertising); 435 if (cmd->advertising) { 436 437 bp->link_params.speed_cap_mask[cfg_idx] = 0; 438 if (cmd->advertising & ADVERTISED_10baseT_Half) { 439 bp->link_params.speed_cap_mask[cfg_idx] |= 440 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 441 } 442 if (cmd->advertising & ADVERTISED_10baseT_Full) 443 bp->link_params.speed_cap_mask[cfg_idx] |= 444 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 445 446 if (cmd->advertising & ADVERTISED_100baseT_Full) 447 bp->link_params.speed_cap_mask[cfg_idx] |= 448 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 449 450 if (cmd->advertising & ADVERTISED_100baseT_Half) { 451 bp->link_params.speed_cap_mask[cfg_idx] |= 452 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 453 } 454 if (cmd->advertising & ADVERTISED_1000baseT_Half) { 455 bp->link_params.speed_cap_mask[cfg_idx] |= 456 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 457 } 458 if (cmd->advertising & (ADVERTISED_1000baseT_Full | 459 ADVERTISED_1000baseKX_Full)) 460 bp->link_params.speed_cap_mask[cfg_idx] |= 461 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 462 463 if (cmd->advertising & (ADVERTISED_10000baseT_Full | 464 ADVERTISED_10000baseKX4_Full | 465 ADVERTISED_10000baseKR_Full)) 466 bp->link_params.speed_cap_mask[cfg_idx] |= 467 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 468 469 if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 470 bp->link_params.speed_cap_mask[cfg_idx] |= 471 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 472 } 473 } else { /* forced speed */ 474 /* advertise the requested speed and duplex if supported */ 475 switch (speed) { 476 case SPEED_10: 477 if (cmd->duplex == DUPLEX_FULL) { 478 if (!(bp->port.supported[cfg_idx] & 479 SUPPORTED_10baseT_Full)) { 480 DP(BNX2X_MSG_ETHTOOL, 481 "10M full not supported\n"); 482 return -EINVAL; 483 } 484 485 advertising = (ADVERTISED_10baseT_Full | 486 ADVERTISED_TP); 487 } else { 488 if (!(bp->port.supported[cfg_idx] & 489 SUPPORTED_10baseT_Half)) { 490 DP(BNX2X_MSG_ETHTOOL, 491 "10M half not supported\n"); 492 return -EINVAL; 493 } 494 495 advertising = (ADVERTISED_10baseT_Half | 496 ADVERTISED_TP); 497 } 498 break; 499 500 case SPEED_100: 501 if (cmd->duplex == DUPLEX_FULL) { 502 if (!(bp->port.supported[cfg_idx] & 503 SUPPORTED_100baseT_Full)) { 504 DP(BNX2X_MSG_ETHTOOL, 505 "100M full not supported\n"); 506 return -EINVAL; 507 } 508 509 advertising = (ADVERTISED_100baseT_Full | 510 ADVERTISED_TP); 511 } else { 512 if (!(bp->port.supported[cfg_idx] & 513 SUPPORTED_100baseT_Half)) { 514 DP(BNX2X_MSG_ETHTOOL, 515 "100M half not supported\n"); 516 return -EINVAL; 517 } 518 519 advertising = (ADVERTISED_100baseT_Half | 520 ADVERTISED_TP); 521 } 522 break; 523 524 case SPEED_1000: 525 if (cmd->duplex != DUPLEX_FULL) { 526 DP(BNX2X_MSG_ETHTOOL, 527 "1G half not supported\n"); 528 return -EINVAL; 529 } 530 531 if (!(bp->port.supported[cfg_idx] & 532 SUPPORTED_1000baseT_Full)) { 533 DP(BNX2X_MSG_ETHTOOL, 534 "1G full not supported\n"); 535 return -EINVAL; 536 } 537 538 advertising = (ADVERTISED_1000baseT_Full | 539 ADVERTISED_TP); 540 break; 541 542 case SPEED_2500: 543 if (cmd->duplex != DUPLEX_FULL) { 544 DP(BNX2X_MSG_ETHTOOL, 545 "2.5G half not supported\n"); 546 return -EINVAL; 547 } 548 549 if (!(bp->port.supported[cfg_idx] 550 & SUPPORTED_2500baseX_Full)) { 551 DP(BNX2X_MSG_ETHTOOL, 552 "2.5G full not supported\n"); 553 return -EINVAL; 554 } 555 556 advertising = (ADVERTISED_2500baseX_Full | 557 ADVERTISED_TP); 558 break; 559 560 case SPEED_10000: 561 if (cmd->duplex != DUPLEX_FULL) { 562 DP(BNX2X_MSG_ETHTOOL, 563 "10G half not supported\n"); 564 return -EINVAL; 565 } 566 phy_idx = bnx2x_get_cur_phy_idx(bp); 567 if (!(bp->port.supported[cfg_idx] 568 & SUPPORTED_10000baseT_Full) || 569 (bp->link_params.phy[phy_idx].media_type == 570 ETH_PHY_SFP_1G_FIBER)) { 571 DP(BNX2X_MSG_ETHTOOL, 572 "10G full not supported\n"); 573 return -EINVAL; 574 } 575 576 advertising = (ADVERTISED_10000baseT_Full | 577 ADVERTISED_FIBRE); 578 break; 579 580 default: 581 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 582 return -EINVAL; 583 } 584 585 bp->link_params.req_line_speed[cfg_idx] = speed; 586 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 587 bp->port.advertising[cfg_idx] = advertising; 588 } 589 590 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 591 " req_duplex %d advertising 0x%x\n", 592 bp->link_params.req_line_speed[cfg_idx], 593 bp->link_params.req_duplex[cfg_idx], 594 bp->port.advertising[cfg_idx]); 595 596 /* Set new config */ 597 bp->link_params.multi_phy_config = new_multi_phy_config; 598 if (netif_running(dev)) { 599 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 600 bnx2x_link_set(bp); 601 } 602 603 return 0; 604 } 605 606 #define DUMP_ALL_PRESETS 0x1FFF 607 #define DUMP_MAX_PRESETS 13 608 609 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 610 { 611 if (CHIP_IS_E1(bp)) 612 return dump_num_registers[0][preset-1]; 613 else if (CHIP_IS_E1H(bp)) 614 return dump_num_registers[1][preset-1]; 615 else if (CHIP_IS_E2(bp)) 616 return dump_num_registers[2][preset-1]; 617 else if (CHIP_IS_E3A0(bp)) 618 return dump_num_registers[3][preset-1]; 619 else if (CHIP_IS_E3B0(bp)) 620 return dump_num_registers[4][preset-1]; 621 else 622 return 0; 623 } 624 625 static int __bnx2x_get_regs_len(struct bnx2x *bp) 626 { 627 u32 preset_idx; 628 int regdump_len = 0; 629 630 /* Calculate the total preset regs length */ 631 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 632 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 633 634 return regdump_len; 635 } 636 637 static int bnx2x_get_regs_len(struct net_device *dev) 638 { 639 struct bnx2x *bp = netdev_priv(dev); 640 int regdump_len = 0; 641 642 regdump_len = __bnx2x_get_regs_len(bp); 643 regdump_len *= 4; 644 regdump_len += sizeof(struct dump_header); 645 646 return regdump_len; 647 } 648 649 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 650 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 651 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 652 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 653 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 654 655 #define IS_REG_IN_PRESET(presets, idx) \ 656 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 657 658 /******* Paged registers info selectors ********/ 659 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 660 { 661 if (CHIP_IS_E2(bp)) 662 return page_vals_e2; 663 else if (CHIP_IS_E3(bp)) 664 return page_vals_e3; 665 else 666 return NULL; 667 } 668 669 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 670 { 671 if (CHIP_IS_E2(bp)) 672 return PAGE_MODE_VALUES_E2; 673 else if (CHIP_IS_E3(bp)) 674 return PAGE_MODE_VALUES_E3; 675 else 676 return 0; 677 } 678 679 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 680 { 681 if (CHIP_IS_E2(bp)) 682 return page_write_regs_e2; 683 else if (CHIP_IS_E3(bp)) 684 return page_write_regs_e3; 685 else 686 return NULL; 687 } 688 689 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 690 { 691 if (CHIP_IS_E2(bp)) 692 return PAGE_WRITE_REGS_E2; 693 else if (CHIP_IS_E3(bp)) 694 return PAGE_WRITE_REGS_E3; 695 else 696 return 0; 697 } 698 699 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 700 { 701 if (CHIP_IS_E2(bp)) 702 return page_read_regs_e2; 703 else if (CHIP_IS_E3(bp)) 704 return page_read_regs_e3; 705 else 706 return NULL; 707 } 708 709 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 710 { 711 if (CHIP_IS_E2(bp)) 712 return PAGE_READ_REGS_E2; 713 else if (CHIP_IS_E3(bp)) 714 return PAGE_READ_REGS_E3; 715 else 716 return 0; 717 } 718 719 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 720 const struct reg_addr *reg_info) 721 { 722 if (CHIP_IS_E1(bp)) 723 return IS_E1_REG(reg_info->chips); 724 else if (CHIP_IS_E1H(bp)) 725 return IS_E1H_REG(reg_info->chips); 726 else if (CHIP_IS_E2(bp)) 727 return IS_E2_REG(reg_info->chips); 728 else if (CHIP_IS_E3A0(bp)) 729 return IS_E3A0_REG(reg_info->chips); 730 else if (CHIP_IS_E3B0(bp)) 731 return IS_E3B0_REG(reg_info->chips); 732 else 733 return false; 734 } 735 736 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 737 const struct wreg_addr *wreg_info) 738 { 739 if (CHIP_IS_E1(bp)) 740 return IS_E1_REG(wreg_info->chips); 741 else if (CHIP_IS_E1H(bp)) 742 return IS_E1H_REG(wreg_info->chips); 743 else if (CHIP_IS_E2(bp)) 744 return IS_E2_REG(wreg_info->chips); 745 else if (CHIP_IS_E3A0(bp)) 746 return IS_E3A0_REG(wreg_info->chips); 747 else if (CHIP_IS_E3B0(bp)) 748 return IS_E3B0_REG(wreg_info->chips); 749 else 750 return false; 751 } 752 753 /** 754 * bnx2x_read_pages_regs - read "paged" registers 755 * 756 * @bp device handle 757 * @p output buffer 758 * 759 * Reads "paged" memories: memories that may only be read by first writing to a 760 * specific address ("write address") and then reading from a specific address 761 * ("read address"). There may be more than one write address per "page" and 762 * more than one read address per write address. 763 */ 764 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 765 { 766 u32 i, j, k, n; 767 768 /* addresses of the paged registers */ 769 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 770 /* number of paged registers */ 771 int num_pages = __bnx2x_get_page_reg_num(bp); 772 /* write addresses */ 773 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 774 /* number of write addresses */ 775 int write_num = __bnx2x_get_page_write_num(bp); 776 /* read addresses info */ 777 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 778 /* number of read addresses */ 779 int read_num = __bnx2x_get_page_read_num(bp); 780 u32 addr, size; 781 782 for (i = 0; i < num_pages; i++) { 783 for (j = 0; j < write_num; j++) { 784 REG_WR(bp, write_addr[j], page_addr[i]); 785 786 for (k = 0; k < read_num; k++) { 787 if (IS_REG_IN_PRESET(read_addr[k].presets, 788 preset)) { 789 size = read_addr[k].size; 790 for (n = 0; n < size; n++) { 791 addr = read_addr[k].addr + n*4; 792 *p++ = REG_RD(bp, addr); 793 } 794 } 795 } 796 } 797 } 798 } 799 800 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 801 { 802 u32 i, j, addr; 803 const struct wreg_addr *wreg_addr_p = NULL; 804 805 if (CHIP_IS_E1(bp)) 806 wreg_addr_p = &wreg_addr_e1; 807 else if (CHIP_IS_E1H(bp)) 808 wreg_addr_p = &wreg_addr_e1h; 809 else if (CHIP_IS_E2(bp)) 810 wreg_addr_p = &wreg_addr_e2; 811 else if (CHIP_IS_E3A0(bp)) 812 wreg_addr_p = &wreg_addr_e3; 813 else if (CHIP_IS_E3B0(bp)) 814 wreg_addr_p = &wreg_addr_e3b0; 815 816 /* Read the idle_chk registers */ 817 for (i = 0; i < IDLE_REGS_COUNT; i++) { 818 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 819 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 820 for (j = 0; j < idle_reg_addrs[i].size; j++) 821 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 822 } 823 } 824 825 /* Read the regular registers */ 826 for (i = 0; i < REGS_COUNT; i++) { 827 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 828 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 829 for (j = 0; j < reg_addrs[i].size; j++) 830 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 831 } 832 } 833 834 /* Read the CAM registers */ 835 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 836 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 837 for (i = 0; i < wreg_addr_p->size; i++) { 838 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 839 840 /* In case of wreg_addr register, read additional 841 registers from read_regs array 842 */ 843 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 844 addr = *(wreg_addr_p->read_regs); 845 *p++ = REG_RD(bp, addr + j*4); 846 } 847 } 848 } 849 850 /* Paged registers are supported in E2 & E3 only */ 851 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 852 /* Read "paged" registers */ 853 bnx2x_read_pages_regs(bp, p, preset); 854 } 855 856 return 0; 857 } 858 859 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 860 { 861 u32 preset_idx; 862 863 /* Read all registers, by reading all preset registers */ 864 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 865 /* Skip presets with IOR */ 866 if ((preset_idx == 2) || 867 (preset_idx == 5) || 868 (preset_idx == 8) || 869 (preset_idx == 11)) 870 continue; 871 __bnx2x_get_preset_regs(bp, p, preset_idx); 872 p += __bnx2x_get_preset_regs_len(bp, preset_idx); 873 } 874 } 875 876 static void bnx2x_get_regs(struct net_device *dev, 877 struct ethtool_regs *regs, void *_p) 878 { 879 u32 *p = _p; 880 struct bnx2x *bp = netdev_priv(dev); 881 struct dump_header dump_hdr = {0}; 882 883 regs->version = 2; 884 memset(p, 0, regs->len); 885 886 if (!netif_running(bp->dev)) 887 return; 888 889 /* Disable parity attentions as long as following dump may 890 * cause false alarms by reading never written registers. We 891 * will re-enable parity attentions right after the dump. 892 */ 893 894 bnx2x_disable_blocks_parity(bp); 895 896 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 897 dump_hdr.preset = DUMP_ALL_PRESETS; 898 dump_hdr.version = BNX2X_DUMP_VERSION; 899 900 /* dump_meta_data presents OR of CHIP and PATH. */ 901 if (CHIP_IS_E1(bp)) { 902 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 903 } else if (CHIP_IS_E1H(bp)) { 904 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 905 } else if (CHIP_IS_E2(bp)) { 906 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 907 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 908 } else if (CHIP_IS_E3A0(bp)) { 909 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 910 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 911 } else if (CHIP_IS_E3B0(bp)) { 912 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 913 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 914 } 915 916 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 917 p += dump_hdr.header_size + 1; 918 919 /* Actually read the registers */ 920 __bnx2x_get_regs(bp, p); 921 922 /* Re-enable parity attentions */ 923 bnx2x_clear_blocks_parity(bp); 924 bnx2x_enable_blocks_parity(bp); 925 } 926 927 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 928 { 929 struct bnx2x *bp = netdev_priv(dev); 930 int regdump_len = 0; 931 932 regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 933 regdump_len *= 4; 934 regdump_len += sizeof(struct dump_header); 935 936 return regdump_len; 937 } 938 939 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 940 { 941 struct bnx2x *bp = netdev_priv(dev); 942 943 /* Use the ethtool_dump "flag" field as the dump preset index */ 944 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 945 return -EINVAL; 946 947 bp->dump_preset_idx = val->flag; 948 return 0; 949 } 950 951 static int bnx2x_get_dump_flag(struct net_device *dev, 952 struct ethtool_dump *dump) 953 { 954 struct bnx2x *bp = netdev_priv(dev); 955 956 dump->version = BNX2X_DUMP_VERSION; 957 dump->flag = bp->dump_preset_idx; 958 /* Calculate the requested preset idx length */ 959 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 960 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 961 bp->dump_preset_idx, dump->len); 962 return 0; 963 } 964 965 static int bnx2x_get_dump_data(struct net_device *dev, 966 struct ethtool_dump *dump, 967 void *buffer) 968 { 969 u32 *p = buffer; 970 struct bnx2x *bp = netdev_priv(dev); 971 struct dump_header dump_hdr = {0}; 972 973 /* Disable parity attentions as long as following dump may 974 * cause false alarms by reading never written registers. We 975 * will re-enable parity attentions right after the dump. 976 */ 977 978 bnx2x_disable_blocks_parity(bp); 979 980 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 981 dump_hdr.preset = bp->dump_preset_idx; 982 dump_hdr.version = BNX2X_DUMP_VERSION; 983 984 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 985 986 /* dump_meta_data presents OR of CHIP and PATH. */ 987 if (CHIP_IS_E1(bp)) { 988 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 989 } else if (CHIP_IS_E1H(bp)) { 990 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 991 } else if (CHIP_IS_E2(bp)) { 992 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 993 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 994 } else if (CHIP_IS_E3A0(bp)) { 995 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 996 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 997 } else if (CHIP_IS_E3B0(bp)) { 998 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 999 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1000 } 1001 1002 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1003 p += dump_hdr.header_size + 1; 1004 1005 /* Actually read the registers */ 1006 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1007 1008 /* Re-enable parity attentions */ 1009 bnx2x_clear_blocks_parity(bp); 1010 bnx2x_enable_blocks_parity(bp); 1011 1012 return 0; 1013 } 1014 1015 static void bnx2x_get_drvinfo(struct net_device *dev, 1016 struct ethtool_drvinfo *info) 1017 { 1018 struct bnx2x *bp = netdev_priv(dev); 1019 1020 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1021 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1022 1023 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 1024 1025 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1026 info->n_stats = BNX2X_NUM_STATS; 1027 info->testinfo_len = BNX2X_NUM_TESTS(bp); 1028 info->eedump_len = bp->common.flash_size; 1029 info->regdump_len = bnx2x_get_regs_len(dev); 1030 } 1031 1032 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1033 { 1034 struct bnx2x *bp = netdev_priv(dev); 1035 1036 if (bp->flags & NO_WOL_FLAG) { 1037 wol->supported = 0; 1038 wol->wolopts = 0; 1039 } else { 1040 wol->supported = WAKE_MAGIC; 1041 if (bp->wol) 1042 wol->wolopts = WAKE_MAGIC; 1043 else 1044 wol->wolopts = 0; 1045 } 1046 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1047 } 1048 1049 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1050 { 1051 struct bnx2x *bp = netdev_priv(dev); 1052 1053 if (wol->wolopts & ~WAKE_MAGIC) { 1054 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1055 return -EINVAL; 1056 } 1057 1058 if (wol->wolopts & WAKE_MAGIC) { 1059 if (bp->flags & NO_WOL_FLAG) { 1060 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1061 return -EINVAL; 1062 } 1063 bp->wol = 1; 1064 } else 1065 bp->wol = 0; 1066 1067 return 0; 1068 } 1069 1070 static u32 bnx2x_get_msglevel(struct net_device *dev) 1071 { 1072 struct bnx2x *bp = netdev_priv(dev); 1073 1074 return bp->msg_enable; 1075 } 1076 1077 static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1078 { 1079 struct bnx2x *bp = netdev_priv(dev); 1080 1081 if (capable(CAP_NET_ADMIN)) { 1082 /* dump MCP trace */ 1083 if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1084 bnx2x_fw_dump_lvl(bp, KERN_INFO); 1085 bp->msg_enable = level; 1086 } 1087 } 1088 1089 static int bnx2x_nway_reset(struct net_device *dev) 1090 { 1091 struct bnx2x *bp = netdev_priv(dev); 1092 1093 if (!bp->port.pmf) 1094 return 0; 1095 1096 if (netif_running(dev)) { 1097 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1098 bnx2x_force_link_reset(bp); 1099 bnx2x_link_set(bp); 1100 } 1101 1102 return 0; 1103 } 1104 1105 static u32 bnx2x_get_link(struct net_device *dev) 1106 { 1107 struct bnx2x *bp = netdev_priv(dev); 1108 1109 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1110 return 0; 1111 1112 return bp->link_vars.link_up; 1113 } 1114 1115 static int bnx2x_get_eeprom_len(struct net_device *dev) 1116 { 1117 struct bnx2x *bp = netdev_priv(dev); 1118 1119 return bp->common.flash_size; 1120 } 1121 1122 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1123 * had we done things the other way around, if two pfs from the same port would 1124 * attempt to access nvram at the same time, we could run into a scenario such 1125 * as: 1126 * pf A takes the port lock. 1127 * pf B succeeds in taking the same lock since they are from the same port. 1128 * pf A takes the per pf misc lock. Performs eeprom access. 1129 * pf A finishes. Unlocks the per pf misc lock. 1130 * Pf B takes the lock and proceeds to perform it's own access. 1131 * pf A unlocks the per port lock, while pf B is still working (!). 1132 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1133 * access corrupted by pf B) 1134 */ 1135 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1136 { 1137 int port = BP_PORT(bp); 1138 int count, i; 1139 u32 val; 1140 1141 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1142 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1143 1144 /* adjust timeout for emulation/FPGA */ 1145 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1146 if (CHIP_REV_IS_SLOW(bp)) 1147 count *= 100; 1148 1149 /* request access to nvram interface */ 1150 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1151 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1152 1153 for (i = 0; i < count*10; i++) { 1154 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1155 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1156 break; 1157 1158 udelay(5); 1159 } 1160 1161 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1162 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1163 "cannot get access to nvram interface\n"); 1164 return -EBUSY; 1165 } 1166 1167 return 0; 1168 } 1169 1170 static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1171 { 1172 int port = BP_PORT(bp); 1173 int count, i; 1174 u32 val; 1175 1176 /* adjust timeout for emulation/FPGA */ 1177 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1178 if (CHIP_REV_IS_SLOW(bp)) 1179 count *= 100; 1180 1181 /* relinquish nvram interface */ 1182 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1183 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1184 1185 for (i = 0; i < count*10; i++) { 1186 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1187 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1188 break; 1189 1190 udelay(5); 1191 } 1192 1193 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1194 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1195 "cannot free access to nvram interface\n"); 1196 return -EBUSY; 1197 } 1198 1199 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1200 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1201 return 0; 1202 } 1203 1204 static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1205 { 1206 u32 val; 1207 1208 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1209 1210 /* enable both bits, even on read */ 1211 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1212 (val | MCPR_NVM_ACCESS_ENABLE_EN | 1213 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1214 } 1215 1216 static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1217 { 1218 u32 val; 1219 1220 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1221 1222 /* disable both bits, even after read */ 1223 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1224 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1225 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1226 } 1227 1228 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1229 u32 cmd_flags) 1230 { 1231 int count, i, rc; 1232 u32 val; 1233 1234 /* build the command word */ 1235 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1236 1237 /* need to clear DONE bit separately */ 1238 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1239 1240 /* address of the NVRAM to read from */ 1241 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1242 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1243 1244 /* issue a read command */ 1245 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1246 1247 /* adjust timeout for emulation/FPGA */ 1248 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1249 if (CHIP_REV_IS_SLOW(bp)) 1250 count *= 100; 1251 1252 /* wait for completion */ 1253 *ret_val = 0; 1254 rc = -EBUSY; 1255 for (i = 0; i < count; i++) { 1256 udelay(5); 1257 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1258 1259 if (val & MCPR_NVM_COMMAND_DONE) { 1260 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1261 /* we read nvram data in cpu order 1262 * but ethtool sees it as an array of bytes 1263 * converting to big-endian will do the work 1264 */ 1265 *ret_val = cpu_to_be32(val); 1266 rc = 0; 1267 break; 1268 } 1269 } 1270 if (rc == -EBUSY) 1271 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1272 "nvram read timeout expired\n"); 1273 return rc; 1274 } 1275 1276 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1277 int buf_size) 1278 { 1279 int rc; 1280 u32 cmd_flags; 1281 __be32 val; 1282 1283 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1284 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1285 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1286 offset, buf_size); 1287 return -EINVAL; 1288 } 1289 1290 if (offset + buf_size > bp->common.flash_size) { 1291 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1292 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1293 offset, buf_size, bp->common.flash_size); 1294 return -EINVAL; 1295 } 1296 1297 /* request access to nvram interface */ 1298 rc = bnx2x_acquire_nvram_lock(bp); 1299 if (rc) 1300 return rc; 1301 1302 /* enable access to nvram interface */ 1303 bnx2x_enable_nvram_access(bp); 1304 1305 /* read the first word(s) */ 1306 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1307 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1308 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1309 memcpy(ret_buf, &val, 4); 1310 1311 /* advance to the next dword */ 1312 offset += sizeof(u32); 1313 ret_buf += sizeof(u32); 1314 buf_size -= sizeof(u32); 1315 cmd_flags = 0; 1316 } 1317 1318 if (rc == 0) { 1319 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1320 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1321 memcpy(ret_buf, &val, 4); 1322 } 1323 1324 /* disable access to nvram interface */ 1325 bnx2x_disable_nvram_access(bp); 1326 bnx2x_release_nvram_lock(bp); 1327 1328 return rc; 1329 } 1330 1331 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 1332 int buf_size) 1333 { 1334 int rc; 1335 1336 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 1337 1338 if (!rc) { 1339 __be32 *be = (__be32 *)buf; 1340 1341 while ((buf_size -= 4) >= 0) 1342 *buf++ = be32_to_cpu(*be++); 1343 } 1344 1345 return rc; 1346 } 1347 1348 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 1349 { 1350 int rc = 1; 1351 u16 pm = 0; 1352 struct net_device *dev = pci_get_drvdata(bp->pdev); 1353 1354 if (bp->pdev->pm_cap) 1355 rc = pci_read_config_word(bp->pdev, 1356 bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 1357 1358 if ((rc && !netif_running(dev)) || 1359 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 1360 return false; 1361 1362 return true; 1363 } 1364 1365 static int bnx2x_get_eeprom(struct net_device *dev, 1366 struct ethtool_eeprom *eeprom, u8 *eebuf) 1367 { 1368 struct bnx2x *bp = netdev_priv(dev); 1369 1370 if (!bnx2x_is_nvm_accessible(bp)) { 1371 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1372 "cannot access eeprom when the interface is down\n"); 1373 return -EAGAIN; 1374 } 1375 1376 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1377 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1378 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1379 eeprom->len, eeprom->len); 1380 1381 /* parameters already validated in ethtool_get_eeprom */ 1382 1383 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1384 } 1385 1386 static int bnx2x_get_module_eeprom(struct net_device *dev, 1387 struct ethtool_eeprom *ee, 1388 u8 *data) 1389 { 1390 struct bnx2x *bp = netdev_priv(dev); 1391 int rc = -EINVAL, phy_idx; 1392 u8 *user_data = data; 1393 unsigned int start_addr = ee->offset, xfer_size = 0; 1394 1395 if (!bnx2x_is_nvm_accessible(bp)) { 1396 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1397 "cannot access eeprom when the interface is down\n"); 1398 return -EAGAIN; 1399 } 1400 1401 phy_idx = bnx2x_get_cur_phy_idx(bp); 1402 1403 /* Read A0 section */ 1404 if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1405 /* Limit transfer size to the A0 section boundary */ 1406 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1407 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1408 else 1409 xfer_size = ee->len; 1410 bnx2x_acquire_phy_lock(bp); 1411 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1412 &bp->link_params, 1413 I2C_DEV_ADDR_A0, 1414 start_addr, 1415 xfer_size, 1416 user_data); 1417 bnx2x_release_phy_lock(bp); 1418 if (rc) { 1419 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1420 1421 return -EINVAL; 1422 } 1423 user_data += xfer_size; 1424 start_addr += xfer_size; 1425 } 1426 1427 /* Read A2 section */ 1428 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1429 (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1430 xfer_size = ee->len - xfer_size; 1431 /* Limit transfer size to the A2 section boundary */ 1432 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1433 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1434 start_addr -= ETH_MODULE_SFF_8079_LEN; 1435 bnx2x_acquire_phy_lock(bp); 1436 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1437 &bp->link_params, 1438 I2C_DEV_ADDR_A2, 1439 start_addr, 1440 xfer_size, 1441 user_data); 1442 bnx2x_release_phy_lock(bp); 1443 if (rc) { 1444 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1445 return -EINVAL; 1446 } 1447 } 1448 return rc; 1449 } 1450 1451 static int bnx2x_get_module_info(struct net_device *dev, 1452 struct ethtool_modinfo *modinfo) 1453 { 1454 struct bnx2x *bp = netdev_priv(dev); 1455 int phy_idx, rc; 1456 u8 sff8472_comp, diag_type; 1457 1458 if (!bnx2x_is_nvm_accessible(bp)) { 1459 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1460 "cannot access eeprom when the interface is down\n"); 1461 return -EAGAIN; 1462 } 1463 phy_idx = bnx2x_get_cur_phy_idx(bp); 1464 bnx2x_acquire_phy_lock(bp); 1465 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1466 &bp->link_params, 1467 I2C_DEV_ADDR_A0, 1468 SFP_EEPROM_SFF_8472_COMP_ADDR, 1469 SFP_EEPROM_SFF_8472_COMP_SIZE, 1470 &sff8472_comp); 1471 bnx2x_release_phy_lock(bp); 1472 if (rc) { 1473 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1474 return -EINVAL; 1475 } 1476 1477 bnx2x_acquire_phy_lock(bp); 1478 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1479 &bp->link_params, 1480 I2C_DEV_ADDR_A0, 1481 SFP_EEPROM_DIAG_TYPE_ADDR, 1482 SFP_EEPROM_DIAG_TYPE_SIZE, 1483 &diag_type); 1484 bnx2x_release_phy_lock(bp); 1485 if (rc) { 1486 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1487 return -EINVAL; 1488 } 1489 1490 if (!sff8472_comp || 1491 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 1492 modinfo->type = ETH_MODULE_SFF_8079; 1493 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1494 } else { 1495 modinfo->type = ETH_MODULE_SFF_8472; 1496 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1497 } 1498 return 0; 1499 } 1500 1501 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1502 u32 cmd_flags) 1503 { 1504 int count, i, rc; 1505 1506 /* build the command word */ 1507 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1508 1509 /* need to clear DONE bit separately */ 1510 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1511 1512 /* write the data */ 1513 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1514 1515 /* address of the NVRAM to write to */ 1516 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1517 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1518 1519 /* issue the write command */ 1520 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1521 1522 /* adjust timeout for emulation/FPGA */ 1523 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1524 if (CHIP_REV_IS_SLOW(bp)) 1525 count *= 100; 1526 1527 /* wait for completion */ 1528 rc = -EBUSY; 1529 for (i = 0; i < count; i++) { 1530 udelay(5); 1531 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1532 if (val & MCPR_NVM_COMMAND_DONE) { 1533 rc = 0; 1534 break; 1535 } 1536 } 1537 1538 if (rc == -EBUSY) 1539 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1540 "nvram write timeout expired\n"); 1541 return rc; 1542 } 1543 1544 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1545 1546 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1547 int buf_size) 1548 { 1549 int rc; 1550 u32 cmd_flags, align_offset, val; 1551 __be32 val_be; 1552 1553 if (offset + buf_size > bp->common.flash_size) { 1554 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1555 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1556 offset, buf_size, bp->common.flash_size); 1557 return -EINVAL; 1558 } 1559 1560 /* request access to nvram interface */ 1561 rc = bnx2x_acquire_nvram_lock(bp); 1562 if (rc) 1563 return rc; 1564 1565 /* enable access to nvram interface */ 1566 bnx2x_enable_nvram_access(bp); 1567 1568 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1569 align_offset = (offset & ~0x03); 1570 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1571 1572 if (rc == 0) { 1573 /* nvram data is returned as an array of bytes 1574 * convert it back to cpu order 1575 */ 1576 val = be32_to_cpu(val_be); 1577 1578 val &= ~le32_to_cpu((__force __le32) 1579 (0xff << BYTE_OFFSET(offset))); 1580 val |= le32_to_cpu((__force __le32) 1581 (*data_buf << BYTE_OFFSET(offset))); 1582 1583 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1584 cmd_flags); 1585 } 1586 1587 /* disable access to nvram interface */ 1588 bnx2x_disable_nvram_access(bp); 1589 bnx2x_release_nvram_lock(bp); 1590 1591 return rc; 1592 } 1593 1594 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1595 int buf_size) 1596 { 1597 int rc; 1598 u32 cmd_flags; 1599 u32 val; 1600 u32 written_so_far; 1601 1602 if (buf_size == 1) /* ethtool */ 1603 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1604 1605 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1606 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1607 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1608 offset, buf_size); 1609 return -EINVAL; 1610 } 1611 1612 if (offset + buf_size > bp->common.flash_size) { 1613 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1614 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1615 offset, buf_size, bp->common.flash_size); 1616 return -EINVAL; 1617 } 1618 1619 /* request access to nvram interface */ 1620 rc = bnx2x_acquire_nvram_lock(bp); 1621 if (rc) 1622 return rc; 1623 1624 /* enable access to nvram interface */ 1625 bnx2x_enable_nvram_access(bp); 1626 1627 written_so_far = 0; 1628 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1629 while ((written_so_far < buf_size) && (rc == 0)) { 1630 if (written_so_far == (buf_size - sizeof(u32))) 1631 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1632 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1633 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1634 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1635 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1636 1637 memcpy(&val, data_buf, 4); 1638 1639 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1640 1641 /* advance to the next dword */ 1642 offset += sizeof(u32); 1643 data_buf += sizeof(u32); 1644 written_so_far += sizeof(u32); 1645 cmd_flags = 0; 1646 } 1647 1648 /* disable access to nvram interface */ 1649 bnx2x_disable_nvram_access(bp); 1650 bnx2x_release_nvram_lock(bp); 1651 1652 return rc; 1653 } 1654 1655 static int bnx2x_set_eeprom(struct net_device *dev, 1656 struct ethtool_eeprom *eeprom, u8 *eebuf) 1657 { 1658 struct bnx2x *bp = netdev_priv(dev); 1659 int port = BP_PORT(bp); 1660 int rc = 0; 1661 u32 ext_phy_config; 1662 1663 if (!bnx2x_is_nvm_accessible(bp)) { 1664 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1665 "cannot access eeprom when the interface is down\n"); 1666 return -EAGAIN; 1667 } 1668 1669 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1670 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1671 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1672 eeprom->len, eeprom->len); 1673 1674 /* parameters already validated in ethtool_set_eeprom */ 1675 1676 /* PHY eeprom can be accessed only by the PMF */ 1677 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1678 !bp->port.pmf) { 1679 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1680 "wrong magic or interface is not pmf\n"); 1681 return -EINVAL; 1682 } 1683 1684 ext_phy_config = 1685 SHMEM_RD(bp, 1686 dev_info.port_hw_config[port].external_phy_config); 1687 1688 if (eeprom->magic == 0x50485950) { 1689 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1690 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1691 1692 bnx2x_acquire_phy_lock(bp); 1693 rc |= bnx2x_link_reset(&bp->link_params, 1694 &bp->link_vars, 0); 1695 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1696 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1697 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1698 MISC_REGISTERS_GPIO_HIGH, port); 1699 bnx2x_release_phy_lock(bp); 1700 bnx2x_link_report(bp); 1701 1702 } else if (eeprom->magic == 0x50485952) { 1703 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1704 if (bp->state == BNX2X_STATE_OPEN) { 1705 bnx2x_acquire_phy_lock(bp); 1706 rc |= bnx2x_link_reset(&bp->link_params, 1707 &bp->link_vars, 1); 1708 1709 rc |= bnx2x_phy_init(&bp->link_params, 1710 &bp->link_vars); 1711 bnx2x_release_phy_lock(bp); 1712 bnx2x_calc_fc_adv(bp); 1713 } 1714 } else if (eeprom->magic == 0x53985943) { 1715 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1716 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1717 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1718 1719 /* DSP Remove Download Mode */ 1720 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1721 MISC_REGISTERS_GPIO_LOW, port); 1722 1723 bnx2x_acquire_phy_lock(bp); 1724 1725 bnx2x_sfx7101_sp_sw_reset(bp, 1726 &bp->link_params.phy[EXT_PHY1]); 1727 1728 /* wait 0.5 sec to allow it to run */ 1729 msleep(500); 1730 bnx2x_ext_phy_hw_reset(bp, port); 1731 msleep(500); 1732 bnx2x_release_phy_lock(bp); 1733 } 1734 } else 1735 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1736 1737 return rc; 1738 } 1739 1740 static int bnx2x_get_coalesce(struct net_device *dev, 1741 struct ethtool_coalesce *coal) 1742 { 1743 struct bnx2x *bp = netdev_priv(dev); 1744 1745 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1746 1747 coal->rx_coalesce_usecs = bp->rx_ticks; 1748 coal->tx_coalesce_usecs = bp->tx_ticks; 1749 1750 return 0; 1751 } 1752 1753 static int bnx2x_set_coalesce(struct net_device *dev, 1754 struct ethtool_coalesce *coal) 1755 { 1756 struct bnx2x *bp = netdev_priv(dev); 1757 1758 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1759 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1760 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1761 1762 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1763 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1764 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1765 1766 if (netif_running(dev)) 1767 bnx2x_update_coalesce(bp); 1768 1769 return 0; 1770 } 1771 1772 static void bnx2x_get_ringparam(struct net_device *dev, 1773 struct ethtool_ringparam *ering) 1774 { 1775 struct bnx2x *bp = netdev_priv(dev); 1776 1777 ering->rx_max_pending = MAX_RX_AVAIL; 1778 1779 if (bp->rx_ring_size) 1780 ering->rx_pending = bp->rx_ring_size; 1781 else 1782 ering->rx_pending = MAX_RX_AVAIL; 1783 1784 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1785 ering->tx_pending = bp->tx_ring_size; 1786 } 1787 1788 static int bnx2x_set_ringparam(struct net_device *dev, 1789 struct ethtool_ringparam *ering) 1790 { 1791 struct bnx2x *bp = netdev_priv(dev); 1792 1793 DP(BNX2X_MSG_ETHTOOL, 1794 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 1795 ering->rx_pending, ering->tx_pending); 1796 1797 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1798 DP(BNX2X_MSG_ETHTOOL, 1799 "Handling parity error recovery. Try again later\n"); 1800 return -EAGAIN; 1801 } 1802 1803 if ((ering->rx_pending > MAX_RX_AVAIL) || 1804 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1805 MIN_RX_SIZE_TPA)) || 1806 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 1807 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 1808 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1809 return -EINVAL; 1810 } 1811 1812 bp->rx_ring_size = ering->rx_pending; 1813 bp->tx_ring_size = ering->tx_pending; 1814 1815 return bnx2x_reload_if_running(dev); 1816 } 1817 1818 static void bnx2x_get_pauseparam(struct net_device *dev, 1819 struct ethtool_pauseparam *epause) 1820 { 1821 struct bnx2x *bp = netdev_priv(dev); 1822 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1823 int cfg_reg; 1824 1825 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1826 BNX2X_FLOW_CTRL_AUTO); 1827 1828 if (!epause->autoneg) 1829 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1830 else 1831 cfg_reg = bp->link_params.req_fc_auto_adv; 1832 1833 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1834 BNX2X_FLOW_CTRL_RX); 1835 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1836 BNX2X_FLOW_CTRL_TX); 1837 1838 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1839 " autoneg %d rx_pause %d tx_pause %d\n", 1840 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1841 } 1842 1843 static int bnx2x_set_pauseparam(struct net_device *dev, 1844 struct ethtool_pauseparam *epause) 1845 { 1846 struct bnx2x *bp = netdev_priv(dev); 1847 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1848 if (IS_MF(bp)) 1849 return 0; 1850 1851 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1852 " autoneg %d rx_pause %d tx_pause %d\n", 1853 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1854 1855 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1856 1857 if (epause->rx_pause) 1858 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1859 1860 if (epause->tx_pause) 1861 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1862 1863 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1864 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1865 1866 if (epause->autoneg) { 1867 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1868 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1869 return -EINVAL; 1870 } 1871 1872 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1873 bp->link_params.req_flow_ctrl[cfg_idx] = 1874 BNX2X_FLOW_CTRL_AUTO; 1875 } 1876 bp->link_params.req_fc_auto_adv = 0; 1877 if (epause->rx_pause) 1878 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 1879 1880 if (epause->tx_pause) 1881 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1882 1883 if (!bp->link_params.req_fc_auto_adv) 1884 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1885 } 1886 1887 DP(BNX2X_MSG_ETHTOOL, 1888 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1889 1890 if (netif_running(dev)) { 1891 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1892 bnx2x_link_set(bp); 1893 } 1894 1895 return 0; 1896 } 1897 1898 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1899 "register_test (offline) ", 1900 "memory_test (offline) ", 1901 "int_loopback_test (offline)", 1902 "ext_loopback_test (offline)", 1903 "nvram_test (online) ", 1904 "interrupt_test (online) ", 1905 "link_test (online) " 1906 }; 1907 1908 enum { 1909 BNX2X_PRI_FLAG_ISCSI, 1910 BNX2X_PRI_FLAG_FCOE, 1911 BNX2X_PRI_FLAG_STORAGE, 1912 BNX2X_PRI_FLAG_LEN, 1913 }; 1914 1915 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 1916 "iSCSI offload support", 1917 "FCoE offload support", 1918 "Storage only interface" 1919 }; 1920 1921 static u32 bnx2x_eee_to_adv(u32 eee_adv) 1922 { 1923 u32 modes = 0; 1924 1925 if (eee_adv & SHMEM_EEE_100M_ADV) 1926 modes |= ADVERTISED_100baseT_Full; 1927 if (eee_adv & SHMEM_EEE_1G_ADV) 1928 modes |= ADVERTISED_1000baseT_Full; 1929 if (eee_adv & SHMEM_EEE_10G_ADV) 1930 modes |= ADVERTISED_10000baseT_Full; 1931 1932 return modes; 1933 } 1934 1935 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1936 { 1937 u32 eee_adv = 0; 1938 if (modes & ADVERTISED_100baseT_Full) 1939 eee_adv |= SHMEM_EEE_100M_ADV; 1940 if (modes & ADVERTISED_1000baseT_Full) 1941 eee_adv |= SHMEM_EEE_1G_ADV; 1942 if (modes & ADVERTISED_10000baseT_Full) 1943 eee_adv |= SHMEM_EEE_10G_ADV; 1944 1945 return eee_adv << shift; 1946 } 1947 1948 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1949 { 1950 struct bnx2x *bp = netdev_priv(dev); 1951 u32 eee_cfg; 1952 1953 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1954 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1955 return -EOPNOTSUPP; 1956 } 1957 1958 eee_cfg = bp->link_vars.eee_status; 1959 1960 edata->supported = 1961 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 1962 SHMEM_EEE_SUPPORTED_SHIFT); 1963 1964 edata->advertised = 1965 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 1966 SHMEM_EEE_ADV_STATUS_SHIFT); 1967 edata->lp_advertised = 1968 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 1969 SHMEM_EEE_LP_ADV_STATUS_SHIFT); 1970 1971 /* SHMEM value is in 16u units --> Convert to 1u units. */ 1972 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 1973 1974 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 1975 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 1976 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 1977 1978 return 0; 1979 } 1980 1981 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 1982 { 1983 struct bnx2x *bp = netdev_priv(dev); 1984 u32 eee_cfg; 1985 u32 advertised; 1986 1987 if (IS_MF(bp)) 1988 return 0; 1989 1990 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1991 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1992 return -EOPNOTSUPP; 1993 } 1994 1995 eee_cfg = bp->link_vars.eee_status; 1996 1997 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 1998 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 1999 return -EOPNOTSUPP; 2000 } 2001 2002 advertised = bnx2x_adv_to_eee(edata->advertised, 2003 SHMEM_EEE_ADV_STATUS_SHIFT); 2004 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2005 DP(BNX2X_MSG_ETHTOOL, 2006 "Direct manipulation of EEE advertisement is not supported\n"); 2007 return -EINVAL; 2008 } 2009 2010 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2011 DP(BNX2X_MSG_ETHTOOL, 2012 "Maximal Tx Lpi timer supported is %x(u)\n", 2013 EEE_MODE_TIMER_MASK); 2014 return -EINVAL; 2015 } 2016 if (edata->tx_lpi_enabled && 2017 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2018 DP(BNX2X_MSG_ETHTOOL, 2019 "Minimal Tx Lpi timer supported is %d(u)\n", 2020 EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2021 return -EINVAL; 2022 } 2023 2024 /* All is well; Apply changes*/ 2025 if (edata->eee_enabled) 2026 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2027 else 2028 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2029 2030 if (edata->tx_lpi_enabled) 2031 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2032 else 2033 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2034 2035 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2036 bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2037 EEE_MODE_TIMER_MASK) | 2038 EEE_MODE_OVERRIDE_NVRAM | 2039 EEE_MODE_OUTPUT_TIME; 2040 2041 /* Restart link to propagate changes */ 2042 if (netif_running(dev)) { 2043 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2044 bnx2x_force_link_reset(bp); 2045 bnx2x_link_set(bp); 2046 } 2047 2048 return 0; 2049 } 2050 2051 enum { 2052 BNX2X_CHIP_E1_OFST = 0, 2053 BNX2X_CHIP_E1H_OFST, 2054 BNX2X_CHIP_E2_OFST, 2055 BNX2X_CHIP_E3_OFST, 2056 BNX2X_CHIP_E3B0_OFST, 2057 BNX2X_CHIP_MAX_OFST 2058 }; 2059 2060 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2061 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2062 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2063 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2064 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2065 2066 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2067 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2068 2069 static int bnx2x_test_registers(struct bnx2x *bp) 2070 { 2071 int idx, i, rc = -ENODEV; 2072 u32 wr_val = 0, hw; 2073 int port = BP_PORT(bp); 2074 static const struct { 2075 u32 hw; 2076 u32 offset0; 2077 u32 offset1; 2078 u32 mask; 2079 } reg_tbl[] = { 2080 /* 0 */ { BNX2X_CHIP_MASK_ALL, 2081 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2082 { BNX2X_CHIP_MASK_ALL, 2083 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2084 { BNX2X_CHIP_MASK_E1X, 2085 HC_REG_AGG_INT_0, 4, 0x000003ff }, 2086 { BNX2X_CHIP_MASK_ALL, 2087 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2088 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2089 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2090 { BNX2X_CHIP_MASK_E3B0, 2091 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2092 { BNX2X_CHIP_MASK_ALL, 2093 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2094 { BNX2X_CHIP_MASK_ALL, 2095 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2096 { BNX2X_CHIP_MASK_ALL, 2097 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2098 { BNX2X_CHIP_MASK_ALL, 2099 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2100 /* 10 */ { BNX2X_CHIP_MASK_ALL, 2101 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2102 { BNX2X_CHIP_MASK_ALL, 2103 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2104 { BNX2X_CHIP_MASK_ALL, 2105 QM_REG_CONNNUM_0, 4, 0x000fffff }, 2106 { BNX2X_CHIP_MASK_ALL, 2107 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2108 { BNX2X_CHIP_MASK_ALL, 2109 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2110 { BNX2X_CHIP_MASK_ALL, 2111 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2112 { BNX2X_CHIP_MASK_ALL, 2113 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2114 { BNX2X_CHIP_MASK_ALL, 2115 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2116 { BNX2X_CHIP_MASK_ALL, 2117 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2118 { BNX2X_CHIP_MASK_ALL, 2119 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2120 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2121 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2122 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2123 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2124 { BNX2X_CHIP_MASK_ALL, 2125 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2126 { BNX2X_CHIP_MASK_ALL, 2127 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2128 { BNX2X_CHIP_MASK_ALL, 2129 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2130 { BNX2X_CHIP_MASK_ALL, 2131 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2132 { BNX2X_CHIP_MASK_ALL, 2133 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2134 { BNX2X_CHIP_MASK_ALL, 2135 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2136 { BNX2X_CHIP_MASK_ALL, 2137 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2138 { BNX2X_CHIP_MASK_ALL, 2139 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2140 /* 30 */ { BNX2X_CHIP_MASK_ALL, 2141 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2142 { BNX2X_CHIP_MASK_ALL, 2143 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2144 { BNX2X_CHIP_MASK_ALL, 2145 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2146 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2147 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2148 { BNX2X_CHIP_MASK_ALL, 2149 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2150 { BNX2X_CHIP_MASK_ALL, 2151 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2152 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2153 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2154 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2155 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2156 2157 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2158 }; 2159 2160 if (!bnx2x_is_nvm_accessible(bp)) { 2161 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2162 "cannot access eeprom when the interface is down\n"); 2163 return rc; 2164 } 2165 2166 if (CHIP_IS_E1(bp)) 2167 hw = BNX2X_CHIP_MASK_E1; 2168 else if (CHIP_IS_E1H(bp)) 2169 hw = BNX2X_CHIP_MASK_E1H; 2170 else if (CHIP_IS_E2(bp)) 2171 hw = BNX2X_CHIP_MASK_E2; 2172 else if (CHIP_IS_E3B0(bp)) 2173 hw = BNX2X_CHIP_MASK_E3B0; 2174 else /* e3 A0 */ 2175 hw = BNX2X_CHIP_MASK_E3; 2176 2177 /* Repeat the test twice: 2178 * First by writing 0x00000000, second by writing 0xffffffff 2179 */ 2180 for (idx = 0; idx < 2; idx++) { 2181 2182 switch (idx) { 2183 case 0: 2184 wr_val = 0; 2185 break; 2186 case 1: 2187 wr_val = 0xffffffff; 2188 break; 2189 } 2190 2191 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2192 u32 offset, mask, save_val, val; 2193 if (!(hw & reg_tbl[i].hw)) 2194 continue; 2195 2196 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2197 mask = reg_tbl[i].mask; 2198 2199 save_val = REG_RD(bp, offset); 2200 2201 REG_WR(bp, offset, wr_val & mask); 2202 2203 val = REG_RD(bp, offset); 2204 2205 /* Restore the original register's value */ 2206 REG_WR(bp, offset, save_val); 2207 2208 /* verify value is as expected */ 2209 if ((val & mask) != (wr_val & mask)) { 2210 DP(BNX2X_MSG_ETHTOOL, 2211 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2212 offset, val, wr_val, mask); 2213 goto test_reg_exit; 2214 } 2215 } 2216 } 2217 2218 rc = 0; 2219 2220 test_reg_exit: 2221 return rc; 2222 } 2223 2224 static int bnx2x_test_memory(struct bnx2x *bp) 2225 { 2226 int i, j, rc = -ENODEV; 2227 u32 val, index; 2228 static const struct { 2229 u32 offset; 2230 int size; 2231 } mem_tbl[] = { 2232 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2233 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2234 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2235 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2236 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2237 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2238 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2239 2240 { 0xffffffff, 0 } 2241 }; 2242 2243 static const struct { 2244 char *name; 2245 u32 offset; 2246 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2247 } prty_tbl[] = { 2248 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2249 {0x3ffc0, 0, 0, 0} }, 2250 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2251 {0x2, 0x2, 0, 0} }, 2252 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2253 {0, 0, 0, 0} }, 2254 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2255 {0x3ffc0, 0, 0, 0} }, 2256 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2257 {0x3ffc0, 0, 0, 0} }, 2258 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2259 {0x3ffc1, 0, 0, 0} }, 2260 2261 { NULL, 0xffffffff, {0, 0, 0, 0} } 2262 }; 2263 2264 if (!bnx2x_is_nvm_accessible(bp)) { 2265 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2266 "cannot access eeprom when the interface is down\n"); 2267 return rc; 2268 } 2269 2270 if (CHIP_IS_E1(bp)) 2271 index = BNX2X_CHIP_E1_OFST; 2272 else if (CHIP_IS_E1H(bp)) 2273 index = BNX2X_CHIP_E1H_OFST; 2274 else if (CHIP_IS_E2(bp)) 2275 index = BNX2X_CHIP_E2_OFST; 2276 else /* e3 */ 2277 index = BNX2X_CHIP_E3_OFST; 2278 2279 /* pre-Check the parity status */ 2280 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2281 val = REG_RD(bp, prty_tbl[i].offset); 2282 if (val & ~(prty_tbl[i].hw_mask[index])) { 2283 DP(BNX2X_MSG_ETHTOOL, 2284 "%s is 0x%x\n", prty_tbl[i].name, val); 2285 goto test_mem_exit; 2286 } 2287 } 2288 2289 /* Go through all the memories */ 2290 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2291 for (j = 0; j < mem_tbl[i].size; j++) 2292 REG_RD(bp, mem_tbl[i].offset + j*4); 2293 2294 /* Check the parity status */ 2295 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2296 val = REG_RD(bp, prty_tbl[i].offset); 2297 if (val & ~(prty_tbl[i].hw_mask[index])) { 2298 DP(BNX2X_MSG_ETHTOOL, 2299 "%s is 0x%x\n", prty_tbl[i].name, val); 2300 goto test_mem_exit; 2301 } 2302 } 2303 2304 rc = 0; 2305 2306 test_mem_exit: 2307 return rc; 2308 } 2309 2310 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2311 { 2312 int cnt = 1400; 2313 2314 if (link_up) { 2315 while (bnx2x_link_test(bp, is_serdes) && cnt--) 2316 msleep(20); 2317 2318 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 2319 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 2320 2321 cnt = 1400; 2322 while (!bp->link_vars.link_up && cnt--) 2323 msleep(20); 2324 2325 if (cnt <= 0 && !bp->link_vars.link_up) 2326 DP(BNX2X_MSG_ETHTOOL, 2327 "Timeout waiting for link init\n"); 2328 } 2329 } 2330 2331 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2332 { 2333 unsigned int pkt_size, num_pkts, i; 2334 struct sk_buff *skb; 2335 unsigned char *packet; 2336 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2337 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 2338 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2339 u16 tx_start_idx, tx_idx; 2340 u16 rx_start_idx, rx_idx; 2341 u16 pkt_prod, bd_prod; 2342 struct sw_tx_bd *tx_buf; 2343 struct eth_tx_start_bd *tx_start_bd; 2344 dma_addr_t mapping; 2345 union eth_rx_cqe *cqe; 2346 u8 cqe_fp_flags, cqe_fp_type; 2347 struct sw_rx_bd *rx_buf; 2348 u16 len; 2349 int rc = -ENODEV; 2350 u8 *data; 2351 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 2352 txdata->txq_index); 2353 2354 /* check the loopback mode */ 2355 switch (loopback_mode) { 2356 case BNX2X_PHY_LOOPBACK: 2357 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 2358 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2359 return -EINVAL; 2360 } 2361 break; 2362 case BNX2X_MAC_LOOPBACK: 2363 if (CHIP_IS_E3(bp)) { 2364 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2365 if (bp->port.supported[cfg_idx] & 2366 (SUPPORTED_10000baseT_Full | 2367 SUPPORTED_20000baseMLD2_Full | 2368 SUPPORTED_20000baseKR2_Full)) 2369 bp->link_params.loopback_mode = LOOPBACK_XMAC; 2370 else 2371 bp->link_params.loopback_mode = LOOPBACK_UMAC; 2372 } else 2373 bp->link_params.loopback_mode = LOOPBACK_BMAC; 2374 2375 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2376 break; 2377 case BNX2X_EXT_LOOPBACK: 2378 if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 2379 DP(BNX2X_MSG_ETHTOOL, 2380 "Can't configure external loopback\n"); 2381 return -EINVAL; 2382 } 2383 break; 2384 default: 2385 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2386 return -EINVAL; 2387 } 2388 2389 /* prepare the loopback packet */ 2390 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2391 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2392 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2393 if (!skb) { 2394 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2395 rc = -ENOMEM; 2396 goto test_loopback_exit; 2397 } 2398 packet = skb_put(skb, pkt_size); 2399 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2400 memset(packet + ETH_ALEN, 0, ETH_ALEN); 2401 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2402 for (i = ETH_HLEN; i < pkt_size; i++) 2403 packet[i] = (unsigned char) (i & 0xff); 2404 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2405 skb_headlen(skb), DMA_TO_DEVICE); 2406 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2407 rc = -ENOMEM; 2408 dev_kfree_skb(skb); 2409 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2410 goto test_loopback_exit; 2411 } 2412 2413 /* send the loopback packet */ 2414 num_pkts = 0; 2415 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2416 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2417 2418 netdev_tx_sent_queue(txq, skb->len); 2419 2420 pkt_prod = txdata->tx_pkt_prod++; 2421 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2422 tx_buf->first_bd = txdata->tx_bd_prod; 2423 tx_buf->skb = skb; 2424 tx_buf->flags = 0; 2425 2426 bd_prod = TX_BD(txdata->tx_bd_prod); 2427 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2428 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2429 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2430 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2431 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2432 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2433 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2434 SET_FLAG(tx_start_bd->general_data, 2435 ETH_TX_START_BD_HDR_NBDS, 2436 1); 2437 SET_FLAG(tx_start_bd->general_data, 2438 ETH_TX_START_BD_PARSE_NBDS, 2439 0); 2440 2441 /* turn on parsing and get a BD */ 2442 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2443 2444 if (CHIP_IS_E1x(bp)) { 2445 u16 global_data = 0; 2446 struct eth_tx_parse_bd_e1x *pbd_e1x = 2447 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2448 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2449 SET_FLAG(global_data, 2450 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2451 pbd_e1x->global_data = cpu_to_le16(global_data); 2452 } else { 2453 u32 parsing_data = 0; 2454 struct eth_tx_parse_bd_e2 *pbd_e2 = 2455 &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2456 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2457 SET_FLAG(parsing_data, 2458 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2459 pbd_e2->parsing_data = cpu_to_le32(parsing_data); 2460 } 2461 wmb(); 2462 2463 txdata->tx_db.data.prod += 2; 2464 barrier(); 2465 DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2466 2467 mmiowb(); 2468 barrier(); 2469 2470 num_pkts++; 2471 txdata->tx_bd_prod += 2; /* start + pbd */ 2472 2473 udelay(100); 2474 2475 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2476 if (tx_idx != tx_start_idx + num_pkts) 2477 goto test_loopback_exit; 2478 2479 /* Unlike HC IGU won't generate an interrupt for status block 2480 * updates that have been performed while interrupts were 2481 * disabled. 2482 */ 2483 if (bp->common.int_block == INT_BLOCK_IGU) { 2484 /* Disable local BHes to prevent a dead-lock situation between 2485 * sch_direct_xmit() and bnx2x_run_loopback() (calling 2486 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2487 */ 2488 local_bh_disable(); 2489 bnx2x_tx_int(bp, txdata); 2490 local_bh_enable(); 2491 } 2492 2493 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2494 if (rx_idx != rx_start_idx + num_pkts) 2495 goto test_loopback_exit; 2496 2497 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2498 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2499 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2500 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2501 goto test_loopback_rx_exit; 2502 2503 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2504 if (len != pkt_size) 2505 goto test_loopback_rx_exit; 2506 2507 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2508 dma_sync_single_for_cpu(&bp->pdev->dev, 2509 dma_unmap_addr(rx_buf, mapping), 2510 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2511 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2512 for (i = ETH_HLEN; i < pkt_size; i++) 2513 if (*(data + i) != (unsigned char) (i & 0xff)) 2514 goto test_loopback_rx_exit; 2515 2516 rc = 0; 2517 2518 test_loopback_rx_exit: 2519 2520 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2521 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2522 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2523 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2524 2525 /* Update producers */ 2526 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2527 fp_rx->rx_sge_prod); 2528 2529 test_loopback_exit: 2530 bp->link_params.loopback_mode = LOOPBACK_NONE; 2531 2532 return rc; 2533 } 2534 2535 static int bnx2x_test_loopback(struct bnx2x *bp) 2536 { 2537 int rc = 0, res; 2538 2539 if (BP_NOMCP(bp)) 2540 return rc; 2541 2542 if (!netif_running(bp->dev)) 2543 return BNX2X_LOOPBACK_FAILED; 2544 2545 bnx2x_netif_stop(bp, 1); 2546 bnx2x_acquire_phy_lock(bp); 2547 2548 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2549 if (res) { 2550 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2551 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2552 } 2553 2554 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2555 if (res) { 2556 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2557 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2558 } 2559 2560 bnx2x_release_phy_lock(bp); 2561 bnx2x_netif_start(bp); 2562 2563 return rc; 2564 } 2565 2566 static int bnx2x_test_ext_loopback(struct bnx2x *bp) 2567 { 2568 int rc; 2569 u8 is_serdes = 2570 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2571 2572 if (BP_NOMCP(bp)) 2573 return -ENODEV; 2574 2575 if (!netif_running(bp->dev)) 2576 return BNX2X_EXT_LOOPBACK_FAILED; 2577 2578 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2579 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 2580 if (rc) { 2581 DP(BNX2X_MSG_ETHTOOL, 2582 "Can't perform self-test, nic_load (for external lb) failed\n"); 2583 return -ENODEV; 2584 } 2585 bnx2x_wait_for_link(bp, 1, is_serdes); 2586 2587 bnx2x_netif_stop(bp, 1); 2588 2589 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 2590 if (rc) 2591 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 2592 2593 bnx2x_netif_start(bp); 2594 2595 return rc; 2596 } 2597 2598 struct code_entry { 2599 u32 sram_start_addr; 2600 u32 code_attribute; 2601 #define CODE_IMAGE_TYPE_MASK 0xf0800003 2602 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2603 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2604 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2605 u32 nvm_start_addr; 2606 }; 2607 2608 #define CODE_ENTRY_MAX 16 2609 #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2610 #define MAX_IMAGES_IN_EXTENDED_DIR 64 2611 #define NVRAM_DIR_OFFSET 0x14 2612 2613 #define EXTENDED_DIR_EXISTS(code) \ 2614 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2615 (code & CODE_IMAGE_LENGTH_MASK) != 0) 2616 2617 #define CRC32_RESIDUAL 0xdebb20e3 2618 #define CRC_BUFF_SIZE 256 2619 2620 static int bnx2x_nvram_crc(struct bnx2x *bp, 2621 int offset, 2622 int size, 2623 u8 *buff) 2624 { 2625 u32 crc = ~0; 2626 int rc = 0, done = 0; 2627 2628 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2629 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2630 2631 while (done < size) { 2632 int count = min_t(int, size - done, CRC_BUFF_SIZE); 2633 2634 rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2635 2636 if (rc) 2637 return rc; 2638 2639 crc = crc32_le(crc, buff, count); 2640 done += count; 2641 } 2642 2643 if (crc != CRC32_RESIDUAL) 2644 rc = -EINVAL; 2645 2646 return rc; 2647 } 2648 2649 static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2650 struct code_entry *entry, 2651 u8 *buff) 2652 { 2653 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2654 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2655 int rc; 2656 2657 /* Zero-length images and AFEX profiles do not have CRC */ 2658 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2659 return 0; 2660 2661 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2662 if (rc) 2663 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2664 "image %x has failed crc test (rc %d)\n", type, rc); 2665 2666 return rc; 2667 } 2668 2669 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2670 { 2671 int rc; 2672 struct code_entry entry; 2673 2674 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2675 if (rc) 2676 return rc; 2677 2678 return bnx2x_test_nvram_dir(bp, &entry, buff); 2679 } 2680 2681 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2682 { 2683 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2684 struct code_entry entry; 2685 int i; 2686 2687 rc = bnx2x_nvram_read32(bp, 2688 dir_offset + 2689 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2690 (u32 *)&entry, sizeof(entry)); 2691 if (rc) 2692 return rc; 2693 2694 if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2695 return 0; 2696 2697 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2698 &cnt, sizeof(u32)); 2699 if (rc) 2700 return rc; 2701 2702 dir_offset = entry.nvm_start_addr + 8; 2703 2704 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2705 rc = bnx2x_test_dir_entry(bp, dir_offset + 2706 sizeof(struct code_entry) * i, 2707 buff); 2708 if (rc) 2709 return rc; 2710 } 2711 2712 return 0; 2713 } 2714 2715 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2716 { 2717 u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2718 int i; 2719 2720 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2721 2722 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2723 rc = bnx2x_test_dir_entry(bp, dir_offset + 2724 sizeof(struct code_entry) * i, 2725 buff); 2726 if (rc) 2727 return rc; 2728 } 2729 2730 return bnx2x_test_nvram_ext_dirs(bp, buff); 2731 } 2732 2733 struct crc_pair { 2734 int offset; 2735 int size; 2736 }; 2737 2738 static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2739 const struct crc_pair *nvram_tbl, u8 *buf) 2740 { 2741 int i; 2742 2743 for (i = 0; nvram_tbl[i].size; i++) { 2744 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2745 nvram_tbl[i].size, buf); 2746 if (rc) { 2747 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2748 "nvram_tbl[%d] has failed crc test (rc %d)\n", 2749 i, rc); 2750 return rc; 2751 } 2752 } 2753 2754 return 0; 2755 } 2756 2757 static int bnx2x_test_nvram(struct bnx2x *bp) 2758 { 2759 const struct crc_pair nvram_tbl[] = { 2760 { 0, 0x14 }, /* bootstrap */ 2761 { 0x14, 0xec }, /* dir */ 2762 { 0x100, 0x350 }, /* manuf_info */ 2763 { 0x450, 0xf0 }, /* feature_info */ 2764 { 0x640, 0x64 }, /* upgrade_key_info */ 2765 { 0x708, 0x70 }, /* manuf_key_info */ 2766 { 0, 0 } 2767 }; 2768 const struct crc_pair nvram_tbl2[] = { 2769 { 0x7e8, 0x350 }, /* manuf_info2 */ 2770 { 0xb38, 0xf0 }, /* feature_info */ 2771 { 0, 0 } 2772 }; 2773 2774 u8 *buf; 2775 int rc; 2776 u32 magic; 2777 2778 if (BP_NOMCP(bp)) 2779 return 0; 2780 2781 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2782 if (!buf) { 2783 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2784 rc = -ENOMEM; 2785 goto test_nvram_exit; 2786 } 2787 2788 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2789 if (rc) { 2790 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2791 "magic value read (rc %d)\n", rc); 2792 goto test_nvram_exit; 2793 } 2794 2795 if (magic != 0x669955aa) { 2796 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2797 "wrong magic value (0x%08x)\n", magic); 2798 rc = -ENODEV; 2799 goto test_nvram_exit; 2800 } 2801 2802 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2803 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2804 if (rc) 2805 goto test_nvram_exit; 2806 2807 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2808 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2809 SHARED_HW_CFG_HIDE_PORT1; 2810 2811 if (!hide) { 2812 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2813 "Port 1 CRC test-set\n"); 2814 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2815 if (rc) 2816 goto test_nvram_exit; 2817 } 2818 } 2819 2820 rc = bnx2x_test_nvram_dirs(bp, buf); 2821 2822 test_nvram_exit: 2823 kfree(buf); 2824 return rc; 2825 } 2826 2827 /* Send an EMPTY ramrod on the first queue */ 2828 static int bnx2x_test_intr(struct bnx2x *bp) 2829 { 2830 struct bnx2x_queue_state_params params = {NULL}; 2831 2832 if (!netif_running(bp->dev)) { 2833 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2834 "cannot access eeprom when the interface is down\n"); 2835 return -ENODEV; 2836 } 2837 2838 params.q_obj = &bp->sp_objs->q_obj; 2839 params.cmd = BNX2X_Q_CMD_EMPTY; 2840 2841 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2842 2843 return bnx2x_queue_state_change(bp, ¶ms); 2844 } 2845 2846 static void bnx2x_self_test(struct net_device *dev, 2847 struct ethtool_test *etest, u64 *buf) 2848 { 2849 struct bnx2x *bp = netdev_priv(dev); 2850 u8 is_serdes, link_up; 2851 int rc, cnt = 0; 2852 2853 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2854 netdev_err(bp->dev, 2855 "Handling parity error recovery. Try again later\n"); 2856 etest->flags |= ETH_TEST_FL_FAILED; 2857 return; 2858 } 2859 2860 DP(BNX2X_MSG_ETHTOOL, 2861 "Self-test command parameters: offline = %d, external_lb = %d\n", 2862 (etest->flags & ETH_TEST_FL_OFFLINE), 2863 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2864 2865 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2866 2867 if (!netif_running(dev)) { 2868 DP(BNX2X_MSG_ETHTOOL, 2869 "Can't perform self-test when interface is down\n"); 2870 return; 2871 } 2872 2873 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2874 link_up = bp->link_vars.link_up; 2875 /* offline tests are not supported in MF mode */ 2876 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2877 int port = BP_PORT(bp); 2878 u32 val; 2879 2880 /* save current value of input enable for TX port IF */ 2881 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2882 /* disable input for TX port IF */ 2883 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2884 2885 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2886 rc = bnx2x_nic_load(bp, LOAD_DIAG); 2887 if (rc) { 2888 etest->flags |= ETH_TEST_FL_FAILED; 2889 DP(BNX2X_MSG_ETHTOOL, 2890 "Can't perform self-test, nic_load (for offline) failed\n"); 2891 return; 2892 } 2893 2894 /* wait until link state is restored */ 2895 bnx2x_wait_for_link(bp, 1, is_serdes); 2896 2897 if (bnx2x_test_registers(bp) != 0) { 2898 buf[0] = 1; 2899 etest->flags |= ETH_TEST_FL_FAILED; 2900 } 2901 if (bnx2x_test_memory(bp) != 0) { 2902 buf[1] = 1; 2903 etest->flags |= ETH_TEST_FL_FAILED; 2904 } 2905 2906 buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2907 if (buf[2] != 0) 2908 etest->flags |= ETH_TEST_FL_FAILED; 2909 2910 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 2911 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 2912 if (buf[3] != 0) 2913 etest->flags |= ETH_TEST_FL_FAILED; 2914 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 2915 } 2916 2917 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2918 2919 /* restore input for TX port IF */ 2920 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2921 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2922 if (rc) { 2923 etest->flags |= ETH_TEST_FL_FAILED; 2924 DP(BNX2X_MSG_ETHTOOL, 2925 "Can't perform self-test, nic_load (for online) failed\n"); 2926 return; 2927 } 2928 /* wait until link state is restored */ 2929 bnx2x_wait_for_link(bp, link_up, is_serdes); 2930 } 2931 if (bnx2x_test_nvram(bp) != 0) { 2932 if (!IS_MF(bp)) 2933 buf[4] = 1; 2934 else 2935 buf[0] = 1; 2936 etest->flags |= ETH_TEST_FL_FAILED; 2937 } 2938 if (bnx2x_test_intr(bp) != 0) { 2939 if (!IS_MF(bp)) 2940 buf[5] = 1; 2941 else 2942 buf[1] = 1; 2943 etest->flags |= ETH_TEST_FL_FAILED; 2944 } 2945 2946 if (link_up) { 2947 cnt = 100; 2948 while (bnx2x_link_test(bp, is_serdes) && --cnt) 2949 msleep(20); 2950 } 2951 2952 if (!cnt) { 2953 if (!IS_MF(bp)) 2954 buf[6] = 1; 2955 else 2956 buf[2] = 1; 2957 etest->flags |= ETH_TEST_FL_FAILED; 2958 } 2959 } 2960 2961 #define IS_PORT_STAT(i) \ 2962 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2963 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2964 #define IS_MF_MODE_STAT(bp) \ 2965 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2966 2967 /* ethtool statistics are displayed for all regular ethernet queues and the 2968 * fcoe L2 queue if not disabled 2969 */ 2970 static int bnx2x_num_stat_queues(struct bnx2x *bp) 2971 { 2972 return BNX2X_NUM_ETH_QUEUES(bp); 2973 } 2974 2975 static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2976 { 2977 struct bnx2x *bp = netdev_priv(dev); 2978 int i, num_strings = 0; 2979 2980 switch (stringset) { 2981 case ETH_SS_STATS: 2982 if (is_multi(bp)) { 2983 num_strings = bnx2x_num_stat_queues(bp) * 2984 BNX2X_NUM_Q_STATS; 2985 } else 2986 num_strings = 0; 2987 if (IS_MF_MODE_STAT(bp)) { 2988 for (i = 0; i < BNX2X_NUM_STATS; i++) 2989 if (IS_FUNC_STAT(i)) 2990 num_strings++; 2991 } else 2992 num_strings += BNX2X_NUM_STATS; 2993 2994 return num_strings; 2995 2996 case ETH_SS_TEST: 2997 return BNX2X_NUM_TESTS(bp); 2998 2999 case ETH_SS_PRIV_FLAGS: 3000 return BNX2X_PRI_FLAG_LEN; 3001 3002 default: 3003 return -EINVAL; 3004 } 3005 } 3006 3007 static u32 bnx2x_get_private_flags(struct net_device *dev) 3008 { 3009 struct bnx2x *bp = netdev_priv(dev); 3010 u32 flags = 0; 3011 3012 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 3013 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 3014 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 3015 3016 return flags; 3017 } 3018 3019 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3020 { 3021 struct bnx2x *bp = netdev_priv(dev); 3022 int i, j, k, start; 3023 char queue_name[MAX_QUEUE_NAME_LEN+1]; 3024 3025 switch (stringset) { 3026 case ETH_SS_STATS: 3027 k = 0; 3028 if (is_multi(bp)) { 3029 for_each_eth_queue(bp, i) { 3030 memset(queue_name, 0, sizeof(queue_name)); 3031 sprintf(queue_name, "%d", i); 3032 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3033 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3034 ETH_GSTRING_LEN, 3035 bnx2x_q_stats_arr[j].string, 3036 queue_name); 3037 k += BNX2X_NUM_Q_STATS; 3038 } 3039 } 3040 3041 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3042 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 3043 continue; 3044 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3045 bnx2x_stats_arr[i].string); 3046 j++; 3047 } 3048 3049 break; 3050 3051 case ETH_SS_TEST: 3052 /* First 4 tests cannot be done in MF mode */ 3053 if (!IS_MF(bp)) 3054 start = 0; 3055 else 3056 start = 4; 3057 memcpy(buf, bnx2x_tests_str_arr + start, 3058 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 3059 break; 3060 3061 case ETH_SS_PRIV_FLAGS: 3062 memcpy(buf, bnx2x_private_arr, 3063 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 3064 break; 3065 } 3066 } 3067 3068 static void bnx2x_get_ethtool_stats(struct net_device *dev, 3069 struct ethtool_stats *stats, u64 *buf) 3070 { 3071 struct bnx2x *bp = netdev_priv(dev); 3072 u32 *hw_stats, *offset; 3073 int i, j, k = 0; 3074 3075 if (is_multi(bp)) { 3076 for_each_eth_queue(bp, i) { 3077 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3078 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3079 if (bnx2x_q_stats_arr[j].size == 0) { 3080 /* skip this counter */ 3081 buf[k + j] = 0; 3082 continue; 3083 } 3084 offset = (hw_stats + 3085 bnx2x_q_stats_arr[j].offset); 3086 if (bnx2x_q_stats_arr[j].size == 4) { 3087 /* 4-byte counter */ 3088 buf[k + j] = (u64) *offset; 3089 continue; 3090 } 3091 /* 8-byte counter */ 3092 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3093 } 3094 k += BNX2X_NUM_Q_STATS; 3095 } 3096 } 3097 3098 hw_stats = (u32 *)&bp->eth_stats; 3099 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3100 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 3101 continue; 3102 if (bnx2x_stats_arr[i].size == 0) { 3103 /* skip this counter */ 3104 buf[k + j] = 0; 3105 j++; 3106 continue; 3107 } 3108 offset = (hw_stats + bnx2x_stats_arr[i].offset); 3109 if (bnx2x_stats_arr[i].size == 4) { 3110 /* 4-byte counter */ 3111 buf[k + j] = (u64) *offset; 3112 j++; 3113 continue; 3114 } 3115 /* 8-byte counter */ 3116 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3117 j++; 3118 } 3119 } 3120 3121 static int bnx2x_set_phys_id(struct net_device *dev, 3122 enum ethtool_phys_id_state state) 3123 { 3124 struct bnx2x *bp = netdev_priv(dev); 3125 3126 if (!bnx2x_is_nvm_accessible(bp)) { 3127 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 3128 "cannot access eeprom when the interface is down\n"); 3129 return -EAGAIN; 3130 } 3131 3132 switch (state) { 3133 case ETHTOOL_ID_ACTIVE: 3134 return 1; /* cycle on/off once per second */ 3135 3136 case ETHTOOL_ID_ON: 3137 bnx2x_acquire_phy_lock(bp); 3138 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3139 LED_MODE_ON, SPEED_1000); 3140 bnx2x_release_phy_lock(bp); 3141 break; 3142 3143 case ETHTOOL_ID_OFF: 3144 bnx2x_acquire_phy_lock(bp); 3145 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3146 LED_MODE_FRONT_PANEL_OFF, 0); 3147 bnx2x_release_phy_lock(bp); 3148 break; 3149 3150 case ETHTOOL_ID_INACTIVE: 3151 bnx2x_acquire_phy_lock(bp); 3152 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3153 LED_MODE_OPER, 3154 bp->link_vars.line_speed); 3155 bnx2x_release_phy_lock(bp); 3156 } 3157 3158 return 0; 3159 } 3160 3161 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3162 { 3163 switch (info->flow_type) { 3164 case TCP_V4_FLOW: 3165 case TCP_V6_FLOW: 3166 info->data = RXH_IP_SRC | RXH_IP_DST | 3167 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3168 break; 3169 case UDP_V4_FLOW: 3170 if (bp->rss_conf_obj.udp_rss_v4) 3171 info->data = RXH_IP_SRC | RXH_IP_DST | 3172 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3173 else 3174 info->data = RXH_IP_SRC | RXH_IP_DST; 3175 break; 3176 case UDP_V6_FLOW: 3177 if (bp->rss_conf_obj.udp_rss_v6) 3178 info->data = RXH_IP_SRC | RXH_IP_DST | 3179 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3180 else 3181 info->data = RXH_IP_SRC | RXH_IP_DST; 3182 break; 3183 case IPV4_FLOW: 3184 case IPV6_FLOW: 3185 info->data = RXH_IP_SRC | RXH_IP_DST; 3186 break; 3187 default: 3188 info->data = 0; 3189 break; 3190 } 3191 3192 return 0; 3193 } 3194 3195 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3196 u32 *rules __always_unused) 3197 { 3198 struct bnx2x *bp = netdev_priv(dev); 3199 3200 switch (info->cmd) { 3201 case ETHTOOL_GRXRINGS: 3202 info->data = BNX2X_NUM_ETH_QUEUES(bp); 3203 return 0; 3204 case ETHTOOL_GRXFH: 3205 return bnx2x_get_rss_flags(bp, info); 3206 default: 3207 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3208 return -EOPNOTSUPP; 3209 } 3210 } 3211 3212 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3213 { 3214 int udp_rss_requested; 3215 3216 DP(BNX2X_MSG_ETHTOOL, 3217 "Set rss flags command parameters: flow type = %d, data = %llu\n", 3218 info->flow_type, info->data); 3219 3220 switch (info->flow_type) { 3221 case TCP_V4_FLOW: 3222 case TCP_V6_FLOW: 3223 /* For TCP only 4-tupple hash is supported */ 3224 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 3225 RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 3226 DP(BNX2X_MSG_ETHTOOL, 3227 "Command parameters not supported\n"); 3228 return -EINVAL; 3229 } 3230 return 0; 3231 3232 case UDP_V4_FLOW: 3233 case UDP_V6_FLOW: 3234 /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 3235 if (info->data == (RXH_IP_SRC | RXH_IP_DST | 3236 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3237 udp_rss_requested = 1; 3238 else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 3239 udp_rss_requested = 0; 3240 else 3241 return -EINVAL; 3242 if ((info->flow_type == UDP_V4_FLOW) && 3243 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 3244 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 3245 DP(BNX2X_MSG_ETHTOOL, 3246 "rss re-configured, UDP 4-tupple %s\n", 3247 udp_rss_requested ? "enabled" : "disabled"); 3248 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3249 } else if ((info->flow_type == UDP_V6_FLOW) && 3250 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 3251 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 3252 DP(BNX2X_MSG_ETHTOOL, 3253 "rss re-configured, UDP 4-tupple %s\n", 3254 udp_rss_requested ? "enabled" : "disabled"); 3255 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3256 } 3257 return 0; 3258 3259 case IPV4_FLOW: 3260 case IPV6_FLOW: 3261 /* For IP only 2-tupple hash is supported */ 3262 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 3263 DP(BNX2X_MSG_ETHTOOL, 3264 "Command parameters not supported\n"); 3265 return -EINVAL; 3266 } 3267 return 0; 3268 3269 case SCTP_V4_FLOW: 3270 case AH_ESP_V4_FLOW: 3271 case AH_V4_FLOW: 3272 case ESP_V4_FLOW: 3273 case SCTP_V6_FLOW: 3274 case AH_ESP_V6_FLOW: 3275 case AH_V6_FLOW: 3276 case ESP_V6_FLOW: 3277 case IP_USER_FLOW: 3278 case ETHER_FLOW: 3279 /* RSS is not supported for these protocols */ 3280 if (info->data) { 3281 DP(BNX2X_MSG_ETHTOOL, 3282 "Command parameters not supported\n"); 3283 return -EINVAL; 3284 } 3285 return 0; 3286 3287 default: 3288 return -EINVAL; 3289 } 3290 } 3291 3292 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 3293 { 3294 struct bnx2x *bp = netdev_priv(dev); 3295 3296 switch (info->cmd) { 3297 case ETHTOOL_SRXFH: 3298 return bnx2x_set_rss_flags(bp, info); 3299 default: 3300 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3301 return -EOPNOTSUPP; 3302 } 3303 } 3304 3305 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3306 { 3307 return T_ETH_INDIRECTION_TABLE_SIZE; 3308 } 3309 3310 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 3311 { 3312 struct bnx2x *bp = netdev_priv(dev); 3313 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3314 size_t i; 3315 3316 /* Get the current configuration of the RSS indirection table */ 3317 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3318 3319 /* 3320 * We can't use a memcpy() as an internal storage of an 3321 * indirection table is a u8 array while indir->ring_index 3322 * points to an array of u32. 3323 * 3324 * Indirection table contains the FW Client IDs, so we need to 3325 * align the returned table to the Client ID of the leading RSS 3326 * queue. 3327 */ 3328 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 3329 indir[i] = ind_table[i] - bp->fp->cl_id; 3330 3331 return 0; 3332 } 3333 3334 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 3335 { 3336 struct bnx2x *bp = netdev_priv(dev); 3337 size_t i; 3338 3339 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3340 /* 3341 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 3342 * as an internal storage of an indirection table is a u8 array 3343 * while indir->ring_index points to an array of u32. 3344 * 3345 * Indirection table contains the FW Client IDs, so we need to 3346 * align the received table to the Client ID of the leading RSS 3347 * queue 3348 */ 3349 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3350 } 3351 3352 return bnx2x_config_rss_eth(bp, false); 3353 } 3354 3355 /** 3356 * bnx2x_get_channels - gets the number of RSS queues. 3357 * 3358 * @dev: net device 3359 * @channels: returns the number of max / current queues 3360 */ 3361 static void bnx2x_get_channels(struct net_device *dev, 3362 struct ethtool_channels *channels) 3363 { 3364 struct bnx2x *bp = netdev_priv(dev); 3365 3366 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 3367 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 3368 } 3369 3370 /** 3371 * bnx2x_change_num_queues - change the number of RSS queues. 3372 * 3373 * @bp: bnx2x private structure 3374 * 3375 * Re-configure interrupt mode to get the new number of MSI-X 3376 * vectors and re-add NAPI objects. 3377 */ 3378 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 3379 { 3380 bnx2x_disable_msi(bp); 3381 bp->num_ethernet_queues = num_rss; 3382 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 3383 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 3384 bnx2x_set_int_mode(bp); 3385 } 3386 3387 /** 3388 * bnx2x_set_channels - sets the number of RSS queues. 3389 * 3390 * @dev: net device 3391 * @channels: includes the number of queues requested 3392 */ 3393 static int bnx2x_set_channels(struct net_device *dev, 3394 struct ethtool_channels *channels) 3395 { 3396 struct bnx2x *bp = netdev_priv(dev); 3397 3398 DP(BNX2X_MSG_ETHTOOL, 3399 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 3400 channels->rx_count, channels->tx_count, channels->other_count, 3401 channels->combined_count); 3402 3403 /* We don't support separate rx / tx channels. 3404 * We don't allow setting 'other' channels. 3405 */ 3406 if (channels->rx_count || channels->tx_count || channels->other_count 3407 || (channels->combined_count == 0) || 3408 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 3409 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 3410 return -EINVAL; 3411 } 3412 3413 /* Check if there was a change in the active parameters */ 3414 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 3415 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 3416 return 0; 3417 } 3418 3419 /* Set the requested number of queues in bp context. 3420 * Note that the actual number of queues created during load may be 3421 * less than requested if memory is low. 3422 */ 3423 if (unlikely(!netif_running(dev))) { 3424 bnx2x_change_num_queues(bp, channels->combined_count); 3425 return 0; 3426 } 3427 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 3428 bnx2x_change_num_queues(bp, channels->combined_count); 3429 return bnx2x_nic_load(bp, LOAD_NORMAL); 3430 } 3431 3432 static const struct ethtool_ops bnx2x_ethtool_ops = { 3433 .get_settings = bnx2x_get_settings, 3434 .set_settings = bnx2x_set_settings, 3435 .get_drvinfo = bnx2x_get_drvinfo, 3436 .get_regs_len = bnx2x_get_regs_len, 3437 .get_regs = bnx2x_get_regs, 3438 .get_dump_flag = bnx2x_get_dump_flag, 3439 .get_dump_data = bnx2x_get_dump_data, 3440 .set_dump = bnx2x_set_dump, 3441 .get_wol = bnx2x_get_wol, 3442 .set_wol = bnx2x_set_wol, 3443 .get_msglevel = bnx2x_get_msglevel, 3444 .set_msglevel = bnx2x_set_msglevel, 3445 .nway_reset = bnx2x_nway_reset, 3446 .get_link = bnx2x_get_link, 3447 .get_eeprom_len = bnx2x_get_eeprom_len, 3448 .get_eeprom = bnx2x_get_eeprom, 3449 .set_eeprom = bnx2x_set_eeprom, 3450 .get_coalesce = bnx2x_get_coalesce, 3451 .set_coalesce = bnx2x_set_coalesce, 3452 .get_ringparam = bnx2x_get_ringparam, 3453 .set_ringparam = bnx2x_set_ringparam, 3454 .get_pauseparam = bnx2x_get_pauseparam, 3455 .set_pauseparam = bnx2x_set_pauseparam, 3456 .self_test = bnx2x_self_test, 3457 .get_sset_count = bnx2x_get_sset_count, 3458 .get_priv_flags = bnx2x_get_private_flags, 3459 .get_strings = bnx2x_get_strings, 3460 .set_phys_id = bnx2x_set_phys_id, 3461 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3462 .get_rxnfc = bnx2x_get_rxnfc, 3463 .set_rxnfc = bnx2x_set_rxnfc, 3464 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3465 .get_rxfh_indir = bnx2x_get_rxfh_indir, 3466 .set_rxfh_indir = bnx2x_set_rxfh_indir, 3467 .get_channels = bnx2x_get_channels, 3468 .set_channels = bnx2x_set_channels, 3469 .get_module_info = bnx2x_get_module_info, 3470 .get_module_eeprom = bnx2x_get_module_eeprom, 3471 .get_eee = bnx2x_get_eee, 3472 .set_eee = bnx2x_set_eee, 3473 .get_ts_info = ethtool_op_get_ts_info, 3474 }; 3475 3476 static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3477 .get_settings = bnx2x_get_settings, 3478 .set_settings = bnx2x_set_settings, 3479 .get_drvinfo = bnx2x_get_drvinfo, 3480 .get_msglevel = bnx2x_get_msglevel, 3481 .set_msglevel = bnx2x_set_msglevel, 3482 .get_link = bnx2x_get_link, 3483 .get_coalesce = bnx2x_get_coalesce, 3484 .get_ringparam = bnx2x_get_ringparam, 3485 .set_ringparam = bnx2x_set_ringparam, 3486 .get_sset_count = bnx2x_get_sset_count, 3487 .get_strings = bnx2x_get_strings, 3488 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3489 .get_rxnfc = bnx2x_get_rxnfc, 3490 .set_rxnfc = bnx2x_set_rxnfc, 3491 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3492 .get_rxfh_indir = bnx2x_get_rxfh_indir, 3493 .set_rxfh_indir = bnx2x_set_rxfh_indir, 3494 .get_channels = bnx2x_get_channels, 3495 .set_channels = bnx2x_set_channels, 3496 }; 3497 3498 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3499 { 3500 if (IS_PF(bp)) 3501 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 3502 else /* vf */ 3503 SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops); 3504 } 3505