1 /* bnx2x_ethtool.c: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/ethtool.h> 21 #include <linux/netdevice.h> 22 #include <linux/types.h> 23 #include <linux/sched.h> 24 #include <linux/crc32.h> 25 #include "bnx2x.h" 26 #include "bnx2x_cmn.h" 27 #include "bnx2x_dump.h" 28 #include "bnx2x_init.h" 29 30 /* Note: in the format strings below %s is replaced by the queue-name which is 31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33 */ 34 #define MAX_QUEUE_NAME_LEN 4 35 static const struct { 36 long offset; 37 int size; 38 char string[ETH_GSTRING_LEN]; 39 } bnx2x_q_stats_arr[] = { 40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42 8, "[%s]: rx_ucast_packets" }, 43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44 8, "[%s]: rx_mcast_packets" }, 45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46 8, "[%s]: rx_bcast_packets" }, 47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48 { Q_STATS_OFFSET32(rx_err_discard_pkt), 49 4, "[%s]: rx_phy_ip_err_discards"}, 50 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51 4, "[%s]: rx_skb_alloc_discard" }, 52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56 8, "[%s]: tx_ucast_packets" }, 57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58 8, "[%s]: tx_mcast_packets" }, 59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60 8, "[%s]: tx_bcast_packets" }, 61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62 8, "[%s]: tpa_aggregations" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64 8, "[%s]: tpa_aggregated_frames"}, 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67 4, "[%s]: driver_filtered_tx_pkt" } 68 }; 69 70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71 72 static const struct { 73 long offset; 74 int size; 75 u32 flags; 76 #define STATS_FLAGS_PORT 1 77 #define STATS_FLAGS_FUNC 2 78 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79 char string[ETH_GSTRING_LEN]; 80 } bnx2x_stats_arr[] = { 81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83 { STATS_OFFSET32(error_bytes_received_hi), 84 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85 { STATS_OFFSET32(total_unicast_packets_received_hi), 86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87 { STATS_OFFSET32(total_multicast_packets_received_hi), 88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89 { STATS_OFFSET32(total_broadcast_packets_received_hi), 90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100 8, STATS_FLAGS_PORT, "rx_fragments" }, 101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103 { STATS_OFFSET32(no_buff_discard_hi), 104 8, STATS_FLAGS_BOTH, "rx_discards" }, 105 { STATS_OFFSET32(mac_filter_discard), 106 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107 { STATS_OFFSET32(mf_tag_discard), 108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 109 { STATS_OFFSET32(pfc_frames_received_hi), 110 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 111 { STATS_OFFSET32(pfc_frames_sent_hi), 112 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113 { STATS_OFFSET32(brb_drop_hi), 114 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115 { STATS_OFFSET32(brb_truncate_hi), 116 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117 { STATS_OFFSET32(pause_frames_received_hi), 118 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121 { STATS_OFFSET32(nig_timer_max), 122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125 { STATS_OFFSET32(rx_skb_alloc_failed), 126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127 { STATS_OFFSET32(hw_csum_err), 128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129 130 { STATS_OFFSET32(total_bytes_transmitted_hi), 131 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149 8, STATS_FLAGS_PORT, "tx_deferred" }, 150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170 { STATS_OFFSET32(pause_frames_sent_hi), 171 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172 { STATS_OFFSET32(total_tpa_aggregations_hi), 173 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176 { STATS_OFFSET32(total_tpa_bytes_hi), 177 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 178 { STATS_OFFSET32(recoverable_error), 179 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 180 { STATS_OFFSET32(unrecoverable_error), 181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182 { STATS_OFFSET32(driver_filtered_tx_pkt), 183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184 { STATS_OFFSET32(eee_tx_lpi), 185 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186 }; 187 188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 189 190 static int bnx2x_get_port_type(struct bnx2x *bp) 191 { 192 int port_type; 193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194 switch (bp->link_params.phy[phy_idx].media_type) { 195 case ETH_PHY_SFPP_10G_FIBER: 196 case ETH_PHY_SFP_1G_FIBER: 197 case ETH_PHY_XFP_FIBER: 198 case ETH_PHY_KR: 199 case ETH_PHY_CX4: 200 port_type = PORT_FIBRE; 201 break; 202 case ETH_PHY_DA_TWINAX: 203 port_type = PORT_DA; 204 break; 205 case ETH_PHY_BASE_T: 206 port_type = PORT_TP; 207 break; 208 case ETH_PHY_NOT_PRESENT: 209 port_type = PORT_NONE; 210 break; 211 case ETH_PHY_UNSPECIFIED: 212 default: 213 port_type = PORT_OTHER; 214 break; 215 } 216 return port_type; 217 } 218 219 static int bnx2x_get_vf_settings(struct net_device *dev, 220 struct ethtool_cmd *cmd) 221 { 222 struct bnx2x *bp = netdev_priv(dev); 223 224 if (bp->state == BNX2X_STATE_OPEN) { 225 if (test_bit(BNX2X_LINK_REPORT_FD, 226 &bp->vf_link_vars.link_report_flags)) 227 cmd->duplex = DUPLEX_FULL; 228 else 229 cmd->duplex = DUPLEX_HALF; 230 231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed); 232 } else { 233 cmd->duplex = DUPLEX_UNKNOWN; 234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 235 } 236 237 cmd->port = PORT_OTHER; 238 cmd->phy_address = 0; 239 cmd->transceiver = XCVR_INTERNAL; 240 cmd->autoneg = AUTONEG_DISABLE; 241 cmd->maxtxpkt = 0; 242 cmd->maxrxpkt = 0; 243 244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 245 " supported 0x%x advertising 0x%x speed %u\n" 246 " duplex %d port %d phy_address %d transceiver %d\n" 247 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 248 cmd->cmd, cmd->supported, cmd->advertising, 249 ethtool_cmd_speed(cmd), 250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 252 253 return 0; 254 } 255 256 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 257 { 258 struct bnx2x *bp = netdev_priv(dev); 259 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 260 261 /* Dual Media boards present all available port types */ 262 cmd->supported = bp->port.supported[cfg_idx] | 263 (bp->port.supported[cfg_idx ^ 1] & 264 (SUPPORTED_TP | SUPPORTED_FIBRE)); 265 cmd->advertising = bp->port.advertising[cfg_idx]; 266 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 267 ETH_PHY_SFP_1G_FIBER) { 268 cmd->supported &= ~(SUPPORTED_10000baseT_Full); 269 cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 270 } 271 272 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 273 !(bp->flags & MF_FUNC_DIS)) { 274 cmd->duplex = bp->link_vars.duplex; 275 276 if (IS_MF(bp) && !BP_NOMCP(bp)) 277 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 278 else 279 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 280 } else { 281 cmd->duplex = DUPLEX_UNKNOWN; 282 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 283 } 284 285 cmd->port = bnx2x_get_port_type(bp); 286 287 cmd->phy_address = bp->mdio.prtad; 288 cmd->transceiver = XCVR_INTERNAL; 289 290 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 291 cmd->autoneg = AUTONEG_ENABLE; 292 else 293 cmd->autoneg = AUTONEG_DISABLE; 294 295 /* Publish LP advertised speeds and FC */ 296 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 297 u32 status = bp->link_vars.link_status; 298 299 cmd->lp_advertising |= ADVERTISED_Autoneg; 300 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 301 cmd->lp_advertising |= ADVERTISED_Pause; 302 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 303 cmd->lp_advertising |= ADVERTISED_Asym_Pause; 304 305 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 306 cmd->lp_advertising |= ADVERTISED_10baseT_Half; 307 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 308 cmd->lp_advertising |= ADVERTISED_10baseT_Full; 309 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 310 cmd->lp_advertising |= ADVERTISED_100baseT_Half; 311 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 312 cmd->lp_advertising |= ADVERTISED_100baseT_Full; 313 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 314 cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 315 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 316 cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 317 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 318 cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 319 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 320 cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 321 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 322 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 323 } 324 325 cmd->maxtxpkt = 0; 326 cmd->maxrxpkt = 0; 327 328 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 329 " supported 0x%x advertising 0x%x speed %u\n" 330 " duplex %d port %d phy_address %d transceiver %d\n" 331 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 332 cmd->cmd, cmd->supported, cmd->advertising, 333 ethtool_cmd_speed(cmd), 334 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 335 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 336 337 return 0; 338 } 339 340 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 341 { 342 struct bnx2x *bp = netdev_priv(dev); 343 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 344 u32 speed, phy_idx; 345 346 if (IS_MF_SD(bp)) 347 return 0; 348 349 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 350 " supported 0x%x advertising 0x%x speed %u\n" 351 " duplex %d port %d phy_address %d transceiver %d\n" 352 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 353 cmd->cmd, cmd->supported, cmd->advertising, 354 ethtool_cmd_speed(cmd), 355 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 356 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 357 358 speed = ethtool_cmd_speed(cmd); 359 360 /* If received a request for an unknown duplex, assume full*/ 361 if (cmd->duplex == DUPLEX_UNKNOWN) 362 cmd->duplex = DUPLEX_FULL; 363 364 if (IS_MF_SI(bp)) { 365 u32 part; 366 u32 line_speed = bp->link_vars.line_speed; 367 368 /* use 10G if no link detected */ 369 if (!line_speed) 370 line_speed = 10000; 371 372 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 373 DP(BNX2X_MSG_ETHTOOL, 374 "To set speed BC %X or higher is required, please upgrade BC\n", 375 REQ_BC_VER_4_SET_MF_BW); 376 return -EINVAL; 377 } 378 379 part = (speed * 100) / line_speed; 380 381 if (line_speed < speed || !part) { 382 DP(BNX2X_MSG_ETHTOOL, 383 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 384 return -EINVAL; 385 } 386 387 if (bp->state != BNX2X_STATE_OPEN) 388 /* store value for following "load" */ 389 bp->pending_max = part; 390 else 391 bnx2x_update_max_mf_config(bp, part); 392 393 return 0; 394 } 395 396 cfg_idx = bnx2x_get_link_cfg_idx(bp); 397 old_multi_phy_config = bp->link_params.multi_phy_config; 398 if (cmd->port != bnx2x_get_port_type(bp)) { 399 switch (cmd->port) { 400 case PORT_TP: 401 if (!(bp->port.supported[0] & SUPPORTED_TP || 402 bp->port.supported[1] & SUPPORTED_TP)) { 403 DP(BNX2X_MSG_ETHTOOL, 404 "Unsupported port type\n"); 405 return -EINVAL; 406 } 407 bp->link_params.multi_phy_config &= 408 ~PORT_HW_CFG_PHY_SELECTION_MASK; 409 if (bp->link_params.multi_phy_config & 410 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 411 bp->link_params.multi_phy_config |= 412 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 413 else 414 bp->link_params.multi_phy_config |= 415 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 416 break; 417 case PORT_FIBRE: 418 case PORT_DA: 419 case PORT_NONE: 420 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 421 bp->port.supported[1] & SUPPORTED_FIBRE)) { 422 DP(BNX2X_MSG_ETHTOOL, 423 "Unsupported port type\n"); 424 return -EINVAL; 425 } 426 bp->link_params.multi_phy_config &= 427 ~PORT_HW_CFG_PHY_SELECTION_MASK; 428 if (bp->link_params.multi_phy_config & 429 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 430 bp->link_params.multi_phy_config |= 431 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 432 else 433 bp->link_params.multi_phy_config |= 434 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 435 break; 436 default: 437 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 438 return -EINVAL; 439 } 440 } 441 /* Save new config in case command complete successfully */ 442 new_multi_phy_config = bp->link_params.multi_phy_config; 443 /* Get the new cfg_idx */ 444 cfg_idx = bnx2x_get_link_cfg_idx(bp); 445 /* Restore old config in case command failed */ 446 bp->link_params.multi_phy_config = old_multi_phy_config; 447 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 448 449 if (cmd->autoneg == AUTONEG_ENABLE) { 450 u32 an_supported_speed = bp->port.supported[cfg_idx]; 451 if (bp->link_params.phy[EXT_PHY1].type == 452 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 453 an_supported_speed |= (SUPPORTED_100baseT_Half | 454 SUPPORTED_100baseT_Full); 455 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 456 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 457 return -EINVAL; 458 } 459 460 /* advertise the requested speed and duplex if supported */ 461 if (cmd->advertising & ~an_supported_speed) { 462 DP(BNX2X_MSG_ETHTOOL, 463 "Advertisement parameters are not supported\n"); 464 return -EINVAL; 465 } 466 467 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 468 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 469 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 470 cmd->advertising); 471 if (cmd->advertising) { 472 473 bp->link_params.speed_cap_mask[cfg_idx] = 0; 474 if (cmd->advertising & ADVERTISED_10baseT_Half) { 475 bp->link_params.speed_cap_mask[cfg_idx] |= 476 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 477 } 478 if (cmd->advertising & ADVERTISED_10baseT_Full) 479 bp->link_params.speed_cap_mask[cfg_idx] |= 480 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 481 482 if (cmd->advertising & ADVERTISED_100baseT_Full) 483 bp->link_params.speed_cap_mask[cfg_idx] |= 484 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 485 486 if (cmd->advertising & ADVERTISED_100baseT_Half) { 487 bp->link_params.speed_cap_mask[cfg_idx] |= 488 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 489 } 490 if (cmd->advertising & ADVERTISED_1000baseT_Half) { 491 bp->link_params.speed_cap_mask[cfg_idx] |= 492 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 493 } 494 if (cmd->advertising & (ADVERTISED_1000baseT_Full | 495 ADVERTISED_1000baseKX_Full)) 496 bp->link_params.speed_cap_mask[cfg_idx] |= 497 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 498 499 if (cmd->advertising & (ADVERTISED_10000baseT_Full | 500 ADVERTISED_10000baseKX4_Full | 501 ADVERTISED_10000baseKR_Full)) 502 bp->link_params.speed_cap_mask[cfg_idx] |= 503 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 504 505 if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 506 bp->link_params.speed_cap_mask[cfg_idx] |= 507 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 508 } 509 } else { /* forced speed */ 510 /* advertise the requested speed and duplex if supported */ 511 switch (speed) { 512 case SPEED_10: 513 if (cmd->duplex == DUPLEX_FULL) { 514 if (!(bp->port.supported[cfg_idx] & 515 SUPPORTED_10baseT_Full)) { 516 DP(BNX2X_MSG_ETHTOOL, 517 "10M full not supported\n"); 518 return -EINVAL; 519 } 520 521 advertising = (ADVERTISED_10baseT_Full | 522 ADVERTISED_TP); 523 } else { 524 if (!(bp->port.supported[cfg_idx] & 525 SUPPORTED_10baseT_Half)) { 526 DP(BNX2X_MSG_ETHTOOL, 527 "10M half not supported\n"); 528 return -EINVAL; 529 } 530 531 advertising = (ADVERTISED_10baseT_Half | 532 ADVERTISED_TP); 533 } 534 break; 535 536 case SPEED_100: 537 if (cmd->duplex == DUPLEX_FULL) { 538 if (!(bp->port.supported[cfg_idx] & 539 SUPPORTED_100baseT_Full)) { 540 DP(BNX2X_MSG_ETHTOOL, 541 "100M full not supported\n"); 542 return -EINVAL; 543 } 544 545 advertising = (ADVERTISED_100baseT_Full | 546 ADVERTISED_TP); 547 } else { 548 if (!(bp->port.supported[cfg_idx] & 549 SUPPORTED_100baseT_Half)) { 550 DP(BNX2X_MSG_ETHTOOL, 551 "100M half not supported\n"); 552 return -EINVAL; 553 } 554 555 advertising = (ADVERTISED_100baseT_Half | 556 ADVERTISED_TP); 557 } 558 break; 559 560 case SPEED_1000: 561 if (cmd->duplex != DUPLEX_FULL) { 562 DP(BNX2X_MSG_ETHTOOL, 563 "1G half not supported\n"); 564 return -EINVAL; 565 } 566 567 if (!(bp->port.supported[cfg_idx] & 568 SUPPORTED_1000baseT_Full)) { 569 DP(BNX2X_MSG_ETHTOOL, 570 "1G full not supported\n"); 571 return -EINVAL; 572 } 573 574 advertising = (ADVERTISED_1000baseT_Full | 575 ADVERTISED_TP); 576 break; 577 578 case SPEED_2500: 579 if (cmd->duplex != DUPLEX_FULL) { 580 DP(BNX2X_MSG_ETHTOOL, 581 "2.5G half not supported\n"); 582 return -EINVAL; 583 } 584 585 if (!(bp->port.supported[cfg_idx] 586 & SUPPORTED_2500baseX_Full)) { 587 DP(BNX2X_MSG_ETHTOOL, 588 "2.5G full not supported\n"); 589 return -EINVAL; 590 } 591 592 advertising = (ADVERTISED_2500baseX_Full | 593 ADVERTISED_TP); 594 break; 595 596 case SPEED_10000: 597 if (cmd->duplex != DUPLEX_FULL) { 598 DP(BNX2X_MSG_ETHTOOL, 599 "10G half not supported\n"); 600 return -EINVAL; 601 } 602 phy_idx = bnx2x_get_cur_phy_idx(bp); 603 if (!(bp->port.supported[cfg_idx] 604 & SUPPORTED_10000baseT_Full) || 605 (bp->link_params.phy[phy_idx].media_type == 606 ETH_PHY_SFP_1G_FIBER)) { 607 DP(BNX2X_MSG_ETHTOOL, 608 "10G full not supported\n"); 609 return -EINVAL; 610 } 611 612 advertising = (ADVERTISED_10000baseT_Full | 613 ADVERTISED_FIBRE); 614 break; 615 616 default: 617 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 618 return -EINVAL; 619 } 620 621 bp->link_params.req_line_speed[cfg_idx] = speed; 622 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 623 bp->port.advertising[cfg_idx] = advertising; 624 } 625 626 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 627 " req_duplex %d advertising 0x%x\n", 628 bp->link_params.req_line_speed[cfg_idx], 629 bp->link_params.req_duplex[cfg_idx], 630 bp->port.advertising[cfg_idx]); 631 632 /* Set new config */ 633 bp->link_params.multi_phy_config = new_multi_phy_config; 634 if (netif_running(dev)) { 635 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 636 bnx2x_link_set(bp); 637 } 638 639 return 0; 640 } 641 642 #define DUMP_ALL_PRESETS 0x1FFF 643 #define DUMP_MAX_PRESETS 13 644 645 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 646 { 647 if (CHIP_IS_E1(bp)) 648 return dump_num_registers[0][preset-1]; 649 else if (CHIP_IS_E1H(bp)) 650 return dump_num_registers[1][preset-1]; 651 else if (CHIP_IS_E2(bp)) 652 return dump_num_registers[2][preset-1]; 653 else if (CHIP_IS_E3A0(bp)) 654 return dump_num_registers[3][preset-1]; 655 else if (CHIP_IS_E3B0(bp)) 656 return dump_num_registers[4][preset-1]; 657 else 658 return 0; 659 } 660 661 static int __bnx2x_get_regs_len(struct bnx2x *bp) 662 { 663 u32 preset_idx; 664 int regdump_len = 0; 665 666 /* Calculate the total preset regs length */ 667 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 668 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 669 670 return regdump_len; 671 } 672 673 static int bnx2x_get_regs_len(struct net_device *dev) 674 { 675 struct bnx2x *bp = netdev_priv(dev); 676 int regdump_len = 0; 677 678 if (IS_VF(bp)) 679 return 0; 680 681 regdump_len = __bnx2x_get_regs_len(bp); 682 regdump_len *= 4; 683 regdump_len += sizeof(struct dump_header); 684 685 return regdump_len; 686 } 687 688 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 689 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 690 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 691 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 692 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 693 694 #define IS_REG_IN_PRESET(presets, idx) \ 695 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 696 697 /******* Paged registers info selectors ********/ 698 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 699 { 700 if (CHIP_IS_E2(bp)) 701 return page_vals_e2; 702 else if (CHIP_IS_E3(bp)) 703 return page_vals_e3; 704 else 705 return NULL; 706 } 707 708 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 709 { 710 if (CHIP_IS_E2(bp)) 711 return PAGE_MODE_VALUES_E2; 712 else if (CHIP_IS_E3(bp)) 713 return PAGE_MODE_VALUES_E3; 714 else 715 return 0; 716 } 717 718 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 719 { 720 if (CHIP_IS_E2(bp)) 721 return page_write_regs_e2; 722 else if (CHIP_IS_E3(bp)) 723 return page_write_regs_e3; 724 else 725 return NULL; 726 } 727 728 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 729 { 730 if (CHIP_IS_E2(bp)) 731 return PAGE_WRITE_REGS_E2; 732 else if (CHIP_IS_E3(bp)) 733 return PAGE_WRITE_REGS_E3; 734 else 735 return 0; 736 } 737 738 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 739 { 740 if (CHIP_IS_E2(bp)) 741 return page_read_regs_e2; 742 else if (CHIP_IS_E3(bp)) 743 return page_read_regs_e3; 744 else 745 return NULL; 746 } 747 748 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 749 { 750 if (CHIP_IS_E2(bp)) 751 return PAGE_READ_REGS_E2; 752 else if (CHIP_IS_E3(bp)) 753 return PAGE_READ_REGS_E3; 754 else 755 return 0; 756 } 757 758 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 759 const struct reg_addr *reg_info) 760 { 761 if (CHIP_IS_E1(bp)) 762 return IS_E1_REG(reg_info->chips); 763 else if (CHIP_IS_E1H(bp)) 764 return IS_E1H_REG(reg_info->chips); 765 else if (CHIP_IS_E2(bp)) 766 return IS_E2_REG(reg_info->chips); 767 else if (CHIP_IS_E3A0(bp)) 768 return IS_E3A0_REG(reg_info->chips); 769 else if (CHIP_IS_E3B0(bp)) 770 return IS_E3B0_REG(reg_info->chips); 771 else 772 return false; 773 } 774 775 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 776 const struct wreg_addr *wreg_info) 777 { 778 if (CHIP_IS_E1(bp)) 779 return IS_E1_REG(wreg_info->chips); 780 else if (CHIP_IS_E1H(bp)) 781 return IS_E1H_REG(wreg_info->chips); 782 else if (CHIP_IS_E2(bp)) 783 return IS_E2_REG(wreg_info->chips); 784 else if (CHIP_IS_E3A0(bp)) 785 return IS_E3A0_REG(wreg_info->chips); 786 else if (CHIP_IS_E3B0(bp)) 787 return IS_E3B0_REG(wreg_info->chips); 788 else 789 return false; 790 } 791 792 /** 793 * bnx2x_read_pages_regs - read "paged" registers 794 * 795 * @bp device handle 796 * @p output buffer 797 * 798 * Reads "paged" memories: memories that may only be read by first writing to a 799 * specific address ("write address") and then reading from a specific address 800 * ("read address"). There may be more than one write address per "page" and 801 * more than one read address per write address. 802 */ 803 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 804 { 805 u32 i, j, k, n; 806 807 /* addresses of the paged registers */ 808 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 809 /* number of paged registers */ 810 int num_pages = __bnx2x_get_page_reg_num(bp); 811 /* write addresses */ 812 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 813 /* number of write addresses */ 814 int write_num = __bnx2x_get_page_write_num(bp); 815 /* read addresses info */ 816 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 817 /* number of read addresses */ 818 int read_num = __bnx2x_get_page_read_num(bp); 819 u32 addr, size; 820 821 for (i = 0; i < num_pages; i++) { 822 for (j = 0; j < write_num; j++) { 823 REG_WR(bp, write_addr[j], page_addr[i]); 824 825 for (k = 0; k < read_num; k++) { 826 if (IS_REG_IN_PRESET(read_addr[k].presets, 827 preset)) { 828 size = read_addr[k].size; 829 for (n = 0; n < size; n++) { 830 addr = read_addr[k].addr + n*4; 831 *p++ = REG_RD(bp, addr); 832 } 833 } 834 } 835 } 836 } 837 } 838 839 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 840 { 841 u32 i, j, addr; 842 const struct wreg_addr *wreg_addr_p = NULL; 843 844 if (CHIP_IS_E1(bp)) 845 wreg_addr_p = &wreg_addr_e1; 846 else if (CHIP_IS_E1H(bp)) 847 wreg_addr_p = &wreg_addr_e1h; 848 else if (CHIP_IS_E2(bp)) 849 wreg_addr_p = &wreg_addr_e2; 850 else if (CHIP_IS_E3A0(bp)) 851 wreg_addr_p = &wreg_addr_e3; 852 else if (CHIP_IS_E3B0(bp)) 853 wreg_addr_p = &wreg_addr_e3b0; 854 855 /* Read the idle_chk registers */ 856 for (i = 0; i < IDLE_REGS_COUNT; i++) { 857 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 858 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 859 for (j = 0; j < idle_reg_addrs[i].size; j++) 860 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 861 } 862 } 863 864 /* Read the regular registers */ 865 for (i = 0; i < REGS_COUNT; i++) { 866 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 867 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 868 for (j = 0; j < reg_addrs[i].size; j++) 869 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 870 } 871 } 872 873 /* Read the CAM registers */ 874 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 875 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 876 for (i = 0; i < wreg_addr_p->size; i++) { 877 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 878 879 /* In case of wreg_addr register, read additional 880 registers from read_regs array 881 */ 882 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 883 addr = *(wreg_addr_p->read_regs); 884 *p++ = REG_RD(bp, addr + j*4); 885 } 886 } 887 } 888 889 /* Paged registers are supported in E2 & E3 only */ 890 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 891 /* Read "paged" registers */ 892 bnx2x_read_pages_regs(bp, p, preset); 893 } 894 895 return 0; 896 } 897 898 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 899 { 900 u32 preset_idx; 901 902 /* Read all registers, by reading all preset registers */ 903 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 904 /* Skip presets with IOR */ 905 if ((preset_idx == 2) || 906 (preset_idx == 5) || 907 (preset_idx == 8) || 908 (preset_idx == 11)) 909 continue; 910 __bnx2x_get_preset_regs(bp, p, preset_idx); 911 p += __bnx2x_get_preset_regs_len(bp, preset_idx); 912 } 913 } 914 915 static void bnx2x_get_regs(struct net_device *dev, 916 struct ethtool_regs *regs, void *_p) 917 { 918 u32 *p = _p; 919 struct bnx2x *bp = netdev_priv(dev); 920 struct dump_header dump_hdr = {0}; 921 922 regs->version = 2; 923 memset(p, 0, regs->len); 924 925 if (!netif_running(bp->dev)) 926 return; 927 928 /* Disable parity attentions as long as following dump may 929 * cause false alarms by reading never written registers. We 930 * will re-enable parity attentions right after the dump. 931 */ 932 933 bnx2x_disable_blocks_parity(bp); 934 935 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 936 dump_hdr.preset = DUMP_ALL_PRESETS; 937 dump_hdr.version = BNX2X_DUMP_VERSION; 938 939 /* dump_meta_data presents OR of CHIP and PATH. */ 940 if (CHIP_IS_E1(bp)) { 941 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 942 } else if (CHIP_IS_E1H(bp)) { 943 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 944 } else if (CHIP_IS_E2(bp)) { 945 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 946 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 947 } else if (CHIP_IS_E3A0(bp)) { 948 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 949 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 950 } else if (CHIP_IS_E3B0(bp)) { 951 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 952 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 953 } 954 955 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 956 p += dump_hdr.header_size + 1; 957 958 /* Actually read the registers */ 959 __bnx2x_get_regs(bp, p); 960 961 /* Re-enable parity attentions */ 962 bnx2x_clear_blocks_parity(bp); 963 bnx2x_enable_blocks_parity(bp); 964 } 965 966 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 967 { 968 struct bnx2x *bp = netdev_priv(dev); 969 int regdump_len = 0; 970 971 regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 972 regdump_len *= 4; 973 regdump_len += sizeof(struct dump_header); 974 975 return regdump_len; 976 } 977 978 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 979 { 980 struct bnx2x *bp = netdev_priv(dev); 981 982 /* Use the ethtool_dump "flag" field as the dump preset index */ 983 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 984 return -EINVAL; 985 986 bp->dump_preset_idx = val->flag; 987 return 0; 988 } 989 990 static int bnx2x_get_dump_flag(struct net_device *dev, 991 struct ethtool_dump *dump) 992 { 993 struct bnx2x *bp = netdev_priv(dev); 994 995 dump->version = BNX2X_DUMP_VERSION; 996 dump->flag = bp->dump_preset_idx; 997 /* Calculate the requested preset idx length */ 998 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 999 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 1000 bp->dump_preset_idx, dump->len); 1001 return 0; 1002 } 1003 1004 static int bnx2x_get_dump_data(struct net_device *dev, 1005 struct ethtool_dump *dump, 1006 void *buffer) 1007 { 1008 u32 *p = buffer; 1009 struct bnx2x *bp = netdev_priv(dev); 1010 struct dump_header dump_hdr = {0}; 1011 1012 /* Disable parity attentions as long as following dump may 1013 * cause false alarms by reading never written registers. We 1014 * will re-enable parity attentions right after the dump. 1015 */ 1016 1017 bnx2x_disable_blocks_parity(bp); 1018 1019 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 1020 dump_hdr.preset = bp->dump_preset_idx; 1021 dump_hdr.version = BNX2X_DUMP_VERSION; 1022 1023 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 1024 1025 /* dump_meta_data presents OR of CHIP and PATH. */ 1026 if (CHIP_IS_E1(bp)) { 1027 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 1028 } else if (CHIP_IS_E1H(bp)) { 1029 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 1030 } else if (CHIP_IS_E2(bp)) { 1031 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 1032 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1033 } else if (CHIP_IS_E3A0(bp)) { 1034 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 1035 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1036 } else if (CHIP_IS_E3B0(bp)) { 1037 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 1038 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1039 } 1040 1041 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1042 p += dump_hdr.header_size + 1; 1043 1044 /* Actually read the registers */ 1045 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1046 1047 /* Re-enable parity attentions */ 1048 bnx2x_clear_blocks_parity(bp); 1049 bnx2x_enable_blocks_parity(bp); 1050 1051 return 0; 1052 } 1053 1054 static void bnx2x_get_drvinfo(struct net_device *dev, 1055 struct ethtool_drvinfo *info) 1056 { 1057 struct bnx2x *bp = netdev_priv(dev); 1058 1059 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1060 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1061 1062 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 1063 1064 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1065 info->n_stats = BNX2X_NUM_STATS; 1066 info->testinfo_len = BNX2X_NUM_TESTS(bp); 1067 info->eedump_len = bp->common.flash_size; 1068 info->regdump_len = bnx2x_get_regs_len(dev); 1069 } 1070 1071 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1072 { 1073 struct bnx2x *bp = netdev_priv(dev); 1074 1075 if (bp->flags & NO_WOL_FLAG) { 1076 wol->supported = 0; 1077 wol->wolopts = 0; 1078 } else { 1079 wol->supported = WAKE_MAGIC; 1080 if (bp->wol) 1081 wol->wolopts = WAKE_MAGIC; 1082 else 1083 wol->wolopts = 0; 1084 } 1085 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1086 } 1087 1088 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1089 { 1090 struct bnx2x *bp = netdev_priv(dev); 1091 1092 if (wol->wolopts & ~WAKE_MAGIC) { 1093 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1094 return -EINVAL; 1095 } 1096 1097 if (wol->wolopts & WAKE_MAGIC) { 1098 if (bp->flags & NO_WOL_FLAG) { 1099 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1100 return -EINVAL; 1101 } 1102 bp->wol = 1; 1103 } else 1104 bp->wol = 0; 1105 1106 return 0; 1107 } 1108 1109 static u32 bnx2x_get_msglevel(struct net_device *dev) 1110 { 1111 struct bnx2x *bp = netdev_priv(dev); 1112 1113 return bp->msg_enable; 1114 } 1115 1116 static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1117 { 1118 struct bnx2x *bp = netdev_priv(dev); 1119 1120 if (capable(CAP_NET_ADMIN)) { 1121 /* dump MCP trace */ 1122 if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1123 bnx2x_fw_dump_lvl(bp, KERN_INFO); 1124 bp->msg_enable = level; 1125 } 1126 } 1127 1128 static int bnx2x_nway_reset(struct net_device *dev) 1129 { 1130 struct bnx2x *bp = netdev_priv(dev); 1131 1132 if (!bp->port.pmf) 1133 return 0; 1134 1135 if (netif_running(dev)) { 1136 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1137 bnx2x_force_link_reset(bp); 1138 bnx2x_link_set(bp); 1139 } 1140 1141 return 0; 1142 } 1143 1144 static u32 bnx2x_get_link(struct net_device *dev) 1145 { 1146 struct bnx2x *bp = netdev_priv(dev); 1147 1148 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1149 return 0; 1150 1151 if (IS_VF(bp)) 1152 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1153 &bp->vf_link_vars.link_report_flags); 1154 1155 return bp->link_vars.link_up; 1156 } 1157 1158 static int bnx2x_get_eeprom_len(struct net_device *dev) 1159 { 1160 struct bnx2x *bp = netdev_priv(dev); 1161 1162 return bp->common.flash_size; 1163 } 1164 1165 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1166 * had we done things the other way around, if two pfs from the same port would 1167 * attempt to access nvram at the same time, we could run into a scenario such 1168 * as: 1169 * pf A takes the port lock. 1170 * pf B succeeds in taking the same lock since they are from the same port. 1171 * pf A takes the per pf misc lock. Performs eeprom access. 1172 * pf A finishes. Unlocks the per pf misc lock. 1173 * Pf B takes the lock and proceeds to perform it's own access. 1174 * pf A unlocks the per port lock, while pf B is still working (!). 1175 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1176 * access corrupted by pf B) 1177 */ 1178 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1179 { 1180 int port = BP_PORT(bp); 1181 int count, i; 1182 u32 val; 1183 1184 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1185 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1186 1187 /* adjust timeout for emulation/FPGA */ 1188 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1189 if (CHIP_REV_IS_SLOW(bp)) 1190 count *= 100; 1191 1192 /* request access to nvram interface */ 1193 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1194 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1195 1196 for (i = 0; i < count*10; i++) { 1197 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1198 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1199 break; 1200 1201 udelay(5); 1202 } 1203 1204 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1205 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1206 "cannot get access to nvram interface\n"); 1207 return -EBUSY; 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1214 { 1215 int port = BP_PORT(bp); 1216 int count, i; 1217 u32 val; 1218 1219 /* adjust timeout for emulation/FPGA */ 1220 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1221 if (CHIP_REV_IS_SLOW(bp)) 1222 count *= 100; 1223 1224 /* relinquish nvram interface */ 1225 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1226 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1227 1228 for (i = 0; i < count*10; i++) { 1229 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1230 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1231 break; 1232 1233 udelay(5); 1234 } 1235 1236 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1237 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1238 "cannot free access to nvram interface\n"); 1239 return -EBUSY; 1240 } 1241 1242 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1243 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1244 return 0; 1245 } 1246 1247 static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1248 { 1249 u32 val; 1250 1251 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1252 1253 /* enable both bits, even on read */ 1254 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1255 (val | MCPR_NVM_ACCESS_ENABLE_EN | 1256 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1257 } 1258 1259 static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1260 { 1261 u32 val; 1262 1263 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1264 1265 /* disable both bits, even after read */ 1266 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1267 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1268 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1269 } 1270 1271 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1272 u32 cmd_flags) 1273 { 1274 int count, i, rc; 1275 u32 val; 1276 1277 /* build the command word */ 1278 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1279 1280 /* need to clear DONE bit separately */ 1281 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1282 1283 /* address of the NVRAM to read from */ 1284 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1285 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1286 1287 /* issue a read command */ 1288 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1289 1290 /* adjust timeout for emulation/FPGA */ 1291 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1292 if (CHIP_REV_IS_SLOW(bp)) 1293 count *= 100; 1294 1295 /* wait for completion */ 1296 *ret_val = 0; 1297 rc = -EBUSY; 1298 for (i = 0; i < count; i++) { 1299 udelay(5); 1300 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1301 1302 if (val & MCPR_NVM_COMMAND_DONE) { 1303 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1304 /* we read nvram data in cpu order 1305 * but ethtool sees it as an array of bytes 1306 * converting to big-endian will do the work 1307 */ 1308 *ret_val = cpu_to_be32(val); 1309 rc = 0; 1310 break; 1311 } 1312 } 1313 if (rc == -EBUSY) 1314 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1315 "nvram read timeout expired\n"); 1316 return rc; 1317 } 1318 1319 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1320 int buf_size) 1321 { 1322 int rc; 1323 u32 cmd_flags; 1324 __be32 val; 1325 1326 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1328 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1329 offset, buf_size); 1330 return -EINVAL; 1331 } 1332 1333 if (offset + buf_size > bp->common.flash_size) { 1334 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1335 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1336 offset, buf_size, bp->common.flash_size); 1337 return -EINVAL; 1338 } 1339 1340 /* request access to nvram interface */ 1341 rc = bnx2x_acquire_nvram_lock(bp); 1342 if (rc) 1343 return rc; 1344 1345 /* enable access to nvram interface */ 1346 bnx2x_enable_nvram_access(bp); 1347 1348 /* read the first word(s) */ 1349 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1350 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1351 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1352 memcpy(ret_buf, &val, 4); 1353 1354 /* advance to the next dword */ 1355 offset += sizeof(u32); 1356 ret_buf += sizeof(u32); 1357 buf_size -= sizeof(u32); 1358 cmd_flags = 0; 1359 } 1360 1361 if (rc == 0) { 1362 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1363 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1364 memcpy(ret_buf, &val, 4); 1365 } 1366 1367 /* disable access to nvram interface */ 1368 bnx2x_disable_nvram_access(bp); 1369 bnx2x_release_nvram_lock(bp); 1370 1371 return rc; 1372 } 1373 1374 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 1375 int buf_size) 1376 { 1377 int rc; 1378 1379 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 1380 1381 if (!rc) { 1382 __be32 *be = (__be32 *)buf; 1383 1384 while ((buf_size -= 4) >= 0) 1385 *buf++ = be32_to_cpu(*be++); 1386 } 1387 1388 return rc; 1389 } 1390 1391 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 1392 { 1393 int rc = 1; 1394 u16 pm = 0; 1395 struct net_device *dev = pci_get_drvdata(bp->pdev); 1396 1397 if (bp->pdev->pm_cap) 1398 rc = pci_read_config_word(bp->pdev, 1399 bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 1400 1401 if ((rc && !netif_running(dev)) || 1402 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 1403 return false; 1404 1405 return true; 1406 } 1407 1408 static int bnx2x_get_eeprom(struct net_device *dev, 1409 struct ethtool_eeprom *eeprom, u8 *eebuf) 1410 { 1411 struct bnx2x *bp = netdev_priv(dev); 1412 1413 if (!bnx2x_is_nvm_accessible(bp)) { 1414 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1415 "cannot access eeprom when the interface is down\n"); 1416 return -EAGAIN; 1417 } 1418 1419 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1420 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1421 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1422 eeprom->len, eeprom->len); 1423 1424 /* parameters already validated in ethtool_get_eeprom */ 1425 1426 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1427 } 1428 1429 static int bnx2x_get_module_eeprom(struct net_device *dev, 1430 struct ethtool_eeprom *ee, 1431 u8 *data) 1432 { 1433 struct bnx2x *bp = netdev_priv(dev); 1434 int rc = -EINVAL, phy_idx; 1435 u8 *user_data = data; 1436 unsigned int start_addr = ee->offset, xfer_size = 0; 1437 1438 if (!bnx2x_is_nvm_accessible(bp)) { 1439 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1440 "cannot access eeprom when the interface is down\n"); 1441 return -EAGAIN; 1442 } 1443 1444 phy_idx = bnx2x_get_cur_phy_idx(bp); 1445 1446 /* Read A0 section */ 1447 if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1448 /* Limit transfer size to the A0 section boundary */ 1449 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1450 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1451 else 1452 xfer_size = ee->len; 1453 bnx2x_acquire_phy_lock(bp); 1454 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1455 &bp->link_params, 1456 I2C_DEV_ADDR_A0, 1457 start_addr, 1458 xfer_size, 1459 user_data); 1460 bnx2x_release_phy_lock(bp); 1461 if (rc) { 1462 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1463 1464 return -EINVAL; 1465 } 1466 user_data += xfer_size; 1467 start_addr += xfer_size; 1468 } 1469 1470 /* Read A2 section */ 1471 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1472 (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1473 xfer_size = ee->len - xfer_size; 1474 /* Limit transfer size to the A2 section boundary */ 1475 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1476 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1477 start_addr -= ETH_MODULE_SFF_8079_LEN; 1478 bnx2x_acquire_phy_lock(bp); 1479 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1480 &bp->link_params, 1481 I2C_DEV_ADDR_A2, 1482 start_addr, 1483 xfer_size, 1484 user_data); 1485 bnx2x_release_phy_lock(bp); 1486 if (rc) { 1487 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1488 return -EINVAL; 1489 } 1490 } 1491 return rc; 1492 } 1493 1494 static int bnx2x_get_module_info(struct net_device *dev, 1495 struct ethtool_modinfo *modinfo) 1496 { 1497 struct bnx2x *bp = netdev_priv(dev); 1498 int phy_idx, rc; 1499 u8 sff8472_comp, diag_type; 1500 1501 if (!bnx2x_is_nvm_accessible(bp)) { 1502 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1503 "cannot access eeprom when the interface is down\n"); 1504 return -EAGAIN; 1505 } 1506 phy_idx = bnx2x_get_cur_phy_idx(bp); 1507 bnx2x_acquire_phy_lock(bp); 1508 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1509 &bp->link_params, 1510 I2C_DEV_ADDR_A0, 1511 SFP_EEPROM_SFF_8472_COMP_ADDR, 1512 SFP_EEPROM_SFF_8472_COMP_SIZE, 1513 &sff8472_comp); 1514 bnx2x_release_phy_lock(bp); 1515 if (rc) { 1516 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1517 return -EINVAL; 1518 } 1519 1520 bnx2x_acquire_phy_lock(bp); 1521 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1522 &bp->link_params, 1523 I2C_DEV_ADDR_A0, 1524 SFP_EEPROM_DIAG_TYPE_ADDR, 1525 SFP_EEPROM_DIAG_TYPE_SIZE, 1526 &diag_type); 1527 bnx2x_release_phy_lock(bp); 1528 if (rc) { 1529 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1530 return -EINVAL; 1531 } 1532 1533 if (!sff8472_comp || 1534 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 1535 modinfo->type = ETH_MODULE_SFF_8079; 1536 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1537 } else { 1538 modinfo->type = ETH_MODULE_SFF_8472; 1539 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1540 } 1541 return 0; 1542 } 1543 1544 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1545 u32 cmd_flags) 1546 { 1547 int count, i, rc; 1548 1549 /* build the command word */ 1550 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1551 1552 /* need to clear DONE bit separately */ 1553 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1554 1555 /* write the data */ 1556 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1557 1558 /* address of the NVRAM to write to */ 1559 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1560 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1561 1562 /* issue the write command */ 1563 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1564 1565 /* adjust timeout for emulation/FPGA */ 1566 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1567 if (CHIP_REV_IS_SLOW(bp)) 1568 count *= 100; 1569 1570 /* wait for completion */ 1571 rc = -EBUSY; 1572 for (i = 0; i < count; i++) { 1573 udelay(5); 1574 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1575 if (val & MCPR_NVM_COMMAND_DONE) { 1576 rc = 0; 1577 break; 1578 } 1579 } 1580 1581 if (rc == -EBUSY) 1582 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1583 "nvram write timeout expired\n"); 1584 return rc; 1585 } 1586 1587 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1588 1589 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1590 int buf_size) 1591 { 1592 int rc; 1593 u32 cmd_flags, align_offset, val; 1594 __be32 val_be; 1595 1596 if (offset + buf_size > bp->common.flash_size) { 1597 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1598 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1599 offset, buf_size, bp->common.flash_size); 1600 return -EINVAL; 1601 } 1602 1603 /* request access to nvram interface */ 1604 rc = bnx2x_acquire_nvram_lock(bp); 1605 if (rc) 1606 return rc; 1607 1608 /* enable access to nvram interface */ 1609 bnx2x_enable_nvram_access(bp); 1610 1611 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1612 align_offset = (offset & ~0x03); 1613 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1614 1615 if (rc == 0) { 1616 /* nvram data is returned as an array of bytes 1617 * convert it back to cpu order 1618 */ 1619 val = be32_to_cpu(val_be); 1620 1621 val &= ~le32_to_cpu((__force __le32) 1622 (0xff << BYTE_OFFSET(offset))); 1623 val |= le32_to_cpu((__force __le32) 1624 (*data_buf << BYTE_OFFSET(offset))); 1625 1626 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1627 cmd_flags); 1628 } 1629 1630 /* disable access to nvram interface */ 1631 bnx2x_disable_nvram_access(bp); 1632 bnx2x_release_nvram_lock(bp); 1633 1634 return rc; 1635 } 1636 1637 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1638 int buf_size) 1639 { 1640 int rc; 1641 u32 cmd_flags; 1642 u32 val; 1643 u32 written_so_far; 1644 1645 if (buf_size == 1) /* ethtool */ 1646 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1647 1648 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1649 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1650 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1651 offset, buf_size); 1652 return -EINVAL; 1653 } 1654 1655 if (offset + buf_size > bp->common.flash_size) { 1656 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1657 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1658 offset, buf_size, bp->common.flash_size); 1659 return -EINVAL; 1660 } 1661 1662 /* request access to nvram interface */ 1663 rc = bnx2x_acquire_nvram_lock(bp); 1664 if (rc) 1665 return rc; 1666 1667 /* enable access to nvram interface */ 1668 bnx2x_enable_nvram_access(bp); 1669 1670 written_so_far = 0; 1671 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1672 while ((written_so_far < buf_size) && (rc == 0)) { 1673 if (written_so_far == (buf_size - sizeof(u32))) 1674 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1675 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1676 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1677 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1678 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1679 1680 memcpy(&val, data_buf, 4); 1681 1682 /* Notice unlike bnx2x_nvram_read_dword() this will not 1683 * change val using be32_to_cpu(), which causes data to flip 1684 * if the eeprom is read and then written back. This is due 1685 * to tools utilizing this functionality that would break 1686 * if this would be resolved. 1687 */ 1688 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1689 1690 /* advance to the next dword */ 1691 offset += sizeof(u32); 1692 data_buf += sizeof(u32); 1693 written_so_far += sizeof(u32); 1694 cmd_flags = 0; 1695 } 1696 1697 /* disable access to nvram interface */ 1698 bnx2x_disable_nvram_access(bp); 1699 bnx2x_release_nvram_lock(bp); 1700 1701 return rc; 1702 } 1703 1704 static int bnx2x_set_eeprom(struct net_device *dev, 1705 struct ethtool_eeprom *eeprom, u8 *eebuf) 1706 { 1707 struct bnx2x *bp = netdev_priv(dev); 1708 int port = BP_PORT(bp); 1709 int rc = 0; 1710 u32 ext_phy_config; 1711 1712 if (!bnx2x_is_nvm_accessible(bp)) { 1713 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1714 "cannot access eeprom when the interface is down\n"); 1715 return -EAGAIN; 1716 } 1717 1718 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1719 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1720 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1721 eeprom->len, eeprom->len); 1722 1723 /* parameters already validated in ethtool_set_eeprom */ 1724 1725 /* PHY eeprom can be accessed only by the PMF */ 1726 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1727 !bp->port.pmf) { 1728 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1729 "wrong magic or interface is not pmf\n"); 1730 return -EINVAL; 1731 } 1732 1733 ext_phy_config = 1734 SHMEM_RD(bp, 1735 dev_info.port_hw_config[port].external_phy_config); 1736 1737 if (eeprom->magic == 0x50485950) { 1738 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1739 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1740 1741 bnx2x_acquire_phy_lock(bp); 1742 rc |= bnx2x_link_reset(&bp->link_params, 1743 &bp->link_vars, 0); 1744 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1745 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1746 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1747 MISC_REGISTERS_GPIO_HIGH, port); 1748 bnx2x_release_phy_lock(bp); 1749 bnx2x_link_report(bp); 1750 1751 } else if (eeprom->magic == 0x50485952) { 1752 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1753 if (bp->state == BNX2X_STATE_OPEN) { 1754 bnx2x_acquire_phy_lock(bp); 1755 rc |= bnx2x_link_reset(&bp->link_params, 1756 &bp->link_vars, 1); 1757 1758 rc |= bnx2x_phy_init(&bp->link_params, 1759 &bp->link_vars); 1760 bnx2x_release_phy_lock(bp); 1761 bnx2x_calc_fc_adv(bp); 1762 } 1763 } else if (eeprom->magic == 0x53985943) { 1764 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1765 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1766 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1767 1768 /* DSP Remove Download Mode */ 1769 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1770 MISC_REGISTERS_GPIO_LOW, port); 1771 1772 bnx2x_acquire_phy_lock(bp); 1773 1774 bnx2x_sfx7101_sp_sw_reset(bp, 1775 &bp->link_params.phy[EXT_PHY1]); 1776 1777 /* wait 0.5 sec to allow it to run */ 1778 msleep(500); 1779 bnx2x_ext_phy_hw_reset(bp, port); 1780 msleep(500); 1781 bnx2x_release_phy_lock(bp); 1782 } 1783 } else 1784 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1785 1786 return rc; 1787 } 1788 1789 static int bnx2x_get_coalesce(struct net_device *dev, 1790 struct ethtool_coalesce *coal) 1791 { 1792 struct bnx2x *bp = netdev_priv(dev); 1793 1794 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1795 1796 coal->rx_coalesce_usecs = bp->rx_ticks; 1797 coal->tx_coalesce_usecs = bp->tx_ticks; 1798 1799 return 0; 1800 } 1801 1802 static int bnx2x_set_coalesce(struct net_device *dev, 1803 struct ethtool_coalesce *coal) 1804 { 1805 struct bnx2x *bp = netdev_priv(dev); 1806 1807 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1808 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1809 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1810 1811 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1812 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1813 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1814 1815 if (netif_running(dev)) 1816 bnx2x_update_coalesce(bp); 1817 1818 return 0; 1819 } 1820 1821 static void bnx2x_get_ringparam(struct net_device *dev, 1822 struct ethtool_ringparam *ering) 1823 { 1824 struct bnx2x *bp = netdev_priv(dev); 1825 1826 ering->rx_max_pending = MAX_RX_AVAIL; 1827 1828 if (bp->rx_ring_size) 1829 ering->rx_pending = bp->rx_ring_size; 1830 else 1831 ering->rx_pending = MAX_RX_AVAIL; 1832 1833 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1834 ering->tx_pending = bp->tx_ring_size; 1835 } 1836 1837 static int bnx2x_set_ringparam(struct net_device *dev, 1838 struct ethtool_ringparam *ering) 1839 { 1840 struct bnx2x *bp = netdev_priv(dev); 1841 1842 DP(BNX2X_MSG_ETHTOOL, 1843 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 1844 ering->rx_pending, ering->tx_pending); 1845 1846 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1847 DP(BNX2X_MSG_ETHTOOL, 1848 "Handling parity error recovery. Try again later\n"); 1849 return -EAGAIN; 1850 } 1851 1852 if ((ering->rx_pending > MAX_RX_AVAIL) || 1853 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1854 MIN_RX_SIZE_TPA)) || 1855 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 1856 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 1857 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1858 return -EINVAL; 1859 } 1860 1861 bp->rx_ring_size = ering->rx_pending; 1862 bp->tx_ring_size = ering->tx_pending; 1863 1864 return bnx2x_reload_if_running(dev); 1865 } 1866 1867 static void bnx2x_get_pauseparam(struct net_device *dev, 1868 struct ethtool_pauseparam *epause) 1869 { 1870 struct bnx2x *bp = netdev_priv(dev); 1871 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1872 int cfg_reg; 1873 1874 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1875 BNX2X_FLOW_CTRL_AUTO); 1876 1877 if (!epause->autoneg) 1878 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1879 else 1880 cfg_reg = bp->link_params.req_fc_auto_adv; 1881 1882 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1883 BNX2X_FLOW_CTRL_RX); 1884 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1885 BNX2X_FLOW_CTRL_TX); 1886 1887 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1888 " autoneg %d rx_pause %d tx_pause %d\n", 1889 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1890 } 1891 1892 static int bnx2x_set_pauseparam(struct net_device *dev, 1893 struct ethtool_pauseparam *epause) 1894 { 1895 struct bnx2x *bp = netdev_priv(dev); 1896 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1897 if (IS_MF(bp)) 1898 return 0; 1899 1900 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1901 " autoneg %d rx_pause %d tx_pause %d\n", 1902 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1903 1904 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1905 1906 if (epause->rx_pause) 1907 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1908 1909 if (epause->tx_pause) 1910 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1911 1912 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1913 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1914 1915 if (epause->autoneg) { 1916 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1917 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1918 return -EINVAL; 1919 } 1920 1921 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1922 bp->link_params.req_flow_ctrl[cfg_idx] = 1923 BNX2X_FLOW_CTRL_AUTO; 1924 } 1925 bp->link_params.req_fc_auto_adv = 0; 1926 if (epause->rx_pause) 1927 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 1928 1929 if (epause->tx_pause) 1930 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1931 1932 if (!bp->link_params.req_fc_auto_adv) 1933 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1934 } 1935 1936 DP(BNX2X_MSG_ETHTOOL, 1937 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1938 1939 if (netif_running(dev)) { 1940 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1941 bnx2x_link_set(bp); 1942 } 1943 1944 return 0; 1945 } 1946 1947 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1948 "register_test (offline) ", 1949 "memory_test (offline) ", 1950 "int_loopback_test (offline)", 1951 "ext_loopback_test (offline)", 1952 "nvram_test (online) ", 1953 "interrupt_test (online) ", 1954 "link_test (online) " 1955 }; 1956 1957 enum { 1958 BNX2X_PRI_FLAG_ISCSI, 1959 BNX2X_PRI_FLAG_FCOE, 1960 BNX2X_PRI_FLAG_STORAGE, 1961 BNX2X_PRI_FLAG_LEN, 1962 }; 1963 1964 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 1965 "iSCSI offload support", 1966 "FCoE offload support", 1967 "Storage only interface" 1968 }; 1969 1970 static u32 bnx2x_eee_to_adv(u32 eee_adv) 1971 { 1972 u32 modes = 0; 1973 1974 if (eee_adv & SHMEM_EEE_100M_ADV) 1975 modes |= ADVERTISED_100baseT_Full; 1976 if (eee_adv & SHMEM_EEE_1G_ADV) 1977 modes |= ADVERTISED_1000baseT_Full; 1978 if (eee_adv & SHMEM_EEE_10G_ADV) 1979 modes |= ADVERTISED_10000baseT_Full; 1980 1981 return modes; 1982 } 1983 1984 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1985 { 1986 u32 eee_adv = 0; 1987 if (modes & ADVERTISED_100baseT_Full) 1988 eee_adv |= SHMEM_EEE_100M_ADV; 1989 if (modes & ADVERTISED_1000baseT_Full) 1990 eee_adv |= SHMEM_EEE_1G_ADV; 1991 if (modes & ADVERTISED_10000baseT_Full) 1992 eee_adv |= SHMEM_EEE_10G_ADV; 1993 1994 return eee_adv << shift; 1995 } 1996 1997 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1998 { 1999 struct bnx2x *bp = netdev_priv(dev); 2000 u32 eee_cfg; 2001 2002 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2003 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2004 return -EOPNOTSUPP; 2005 } 2006 2007 eee_cfg = bp->link_vars.eee_status; 2008 2009 edata->supported = 2010 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2011 SHMEM_EEE_SUPPORTED_SHIFT); 2012 2013 edata->advertised = 2014 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2015 SHMEM_EEE_ADV_STATUS_SHIFT); 2016 edata->lp_advertised = 2017 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2018 SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2019 2020 /* SHMEM value is in 16u units --> Convert to 1u units. */ 2021 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2022 2023 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2024 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2025 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2026 2027 return 0; 2028 } 2029 2030 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2031 { 2032 struct bnx2x *bp = netdev_priv(dev); 2033 u32 eee_cfg; 2034 u32 advertised; 2035 2036 if (IS_MF(bp)) 2037 return 0; 2038 2039 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2040 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2041 return -EOPNOTSUPP; 2042 } 2043 2044 eee_cfg = bp->link_vars.eee_status; 2045 2046 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2047 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2048 return -EOPNOTSUPP; 2049 } 2050 2051 advertised = bnx2x_adv_to_eee(edata->advertised, 2052 SHMEM_EEE_ADV_STATUS_SHIFT); 2053 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2054 DP(BNX2X_MSG_ETHTOOL, 2055 "Direct manipulation of EEE advertisement is not supported\n"); 2056 return -EINVAL; 2057 } 2058 2059 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2060 DP(BNX2X_MSG_ETHTOOL, 2061 "Maximal Tx Lpi timer supported is %x(u)\n", 2062 EEE_MODE_TIMER_MASK); 2063 return -EINVAL; 2064 } 2065 if (edata->tx_lpi_enabled && 2066 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2067 DP(BNX2X_MSG_ETHTOOL, 2068 "Minimal Tx Lpi timer supported is %d(u)\n", 2069 EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2070 return -EINVAL; 2071 } 2072 2073 /* All is well; Apply changes*/ 2074 if (edata->eee_enabled) 2075 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2076 else 2077 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2078 2079 if (edata->tx_lpi_enabled) 2080 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2081 else 2082 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2083 2084 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2085 bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2086 EEE_MODE_TIMER_MASK) | 2087 EEE_MODE_OVERRIDE_NVRAM | 2088 EEE_MODE_OUTPUT_TIME; 2089 2090 /* Restart link to propagate changes */ 2091 if (netif_running(dev)) { 2092 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2093 bnx2x_force_link_reset(bp); 2094 bnx2x_link_set(bp); 2095 } 2096 2097 return 0; 2098 } 2099 2100 enum { 2101 BNX2X_CHIP_E1_OFST = 0, 2102 BNX2X_CHIP_E1H_OFST, 2103 BNX2X_CHIP_E2_OFST, 2104 BNX2X_CHIP_E3_OFST, 2105 BNX2X_CHIP_E3B0_OFST, 2106 BNX2X_CHIP_MAX_OFST 2107 }; 2108 2109 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2110 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2111 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2112 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2113 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2114 2115 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2116 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2117 2118 static int bnx2x_test_registers(struct bnx2x *bp) 2119 { 2120 int idx, i, rc = -ENODEV; 2121 u32 wr_val = 0, hw; 2122 int port = BP_PORT(bp); 2123 static const struct { 2124 u32 hw; 2125 u32 offset0; 2126 u32 offset1; 2127 u32 mask; 2128 } reg_tbl[] = { 2129 /* 0 */ { BNX2X_CHIP_MASK_ALL, 2130 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2131 { BNX2X_CHIP_MASK_ALL, 2132 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2133 { BNX2X_CHIP_MASK_E1X, 2134 HC_REG_AGG_INT_0, 4, 0x000003ff }, 2135 { BNX2X_CHIP_MASK_ALL, 2136 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2137 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2138 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2139 { BNX2X_CHIP_MASK_E3B0, 2140 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2141 { BNX2X_CHIP_MASK_ALL, 2142 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2143 { BNX2X_CHIP_MASK_ALL, 2144 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2145 { BNX2X_CHIP_MASK_ALL, 2146 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2147 { BNX2X_CHIP_MASK_ALL, 2148 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2149 /* 10 */ { BNX2X_CHIP_MASK_ALL, 2150 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2151 { BNX2X_CHIP_MASK_ALL, 2152 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2153 { BNX2X_CHIP_MASK_ALL, 2154 QM_REG_CONNNUM_0, 4, 0x000fffff }, 2155 { BNX2X_CHIP_MASK_ALL, 2156 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2157 { BNX2X_CHIP_MASK_ALL, 2158 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2159 { BNX2X_CHIP_MASK_ALL, 2160 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2161 { BNX2X_CHIP_MASK_ALL, 2162 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2163 { BNX2X_CHIP_MASK_ALL, 2164 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2165 { BNX2X_CHIP_MASK_ALL, 2166 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2167 { BNX2X_CHIP_MASK_ALL, 2168 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2169 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2170 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2171 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2172 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2173 { BNX2X_CHIP_MASK_ALL, 2174 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2175 { BNX2X_CHIP_MASK_ALL, 2176 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2177 { BNX2X_CHIP_MASK_ALL, 2178 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2179 { BNX2X_CHIP_MASK_ALL, 2180 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2181 { BNX2X_CHIP_MASK_ALL, 2182 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2183 { BNX2X_CHIP_MASK_ALL, 2184 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2185 { BNX2X_CHIP_MASK_ALL, 2186 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2187 { BNX2X_CHIP_MASK_ALL, 2188 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2189 /* 30 */ { BNX2X_CHIP_MASK_ALL, 2190 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2191 { BNX2X_CHIP_MASK_ALL, 2192 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2193 { BNX2X_CHIP_MASK_ALL, 2194 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2195 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2196 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2197 { BNX2X_CHIP_MASK_ALL, 2198 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2199 { BNX2X_CHIP_MASK_ALL, 2200 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2201 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2202 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2203 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2204 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2205 2206 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2207 }; 2208 2209 if (!bnx2x_is_nvm_accessible(bp)) { 2210 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2211 "cannot access eeprom when the interface is down\n"); 2212 return rc; 2213 } 2214 2215 if (CHIP_IS_E1(bp)) 2216 hw = BNX2X_CHIP_MASK_E1; 2217 else if (CHIP_IS_E1H(bp)) 2218 hw = BNX2X_CHIP_MASK_E1H; 2219 else if (CHIP_IS_E2(bp)) 2220 hw = BNX2X_CHIP_MASK_E2; 2221 else if (CHIP_IS_E3B0(bp)) 2222 hw = BNX2X_CHIP_MASK_E3B0; 2223 else /* e3 A0 */ 2224 hw = BNX2X_CHIP_MASK_E3; 2225 2226 /* Repeat the test twice: 2227 * First by writing 0x00000000, second by writing 0xffffffff 2228 */ 2229 for (idx = 0; idx < 2; idx++) { 2230 2231 switch (idx) { 2232 case 0: 2233 wr_val = 0; 2234 break; 2235 case 1: 2236 wr_val = 0xffffffff; 2237 break; 2238 } 2239 2240 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2241 u32 offset, mask, save_val, val; 2242 if (!(hw & reg_tbl[i].hw)) 2243 continue; 2244 2245 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2246 mask = reg_tbl[i].mask; 2247 2248 save_val = REG_RD(bp, offset); 2249 2250 REG_WR(bp, offset, wr_val & mask); 2251 2252 val = REG_RD(bp, offset); 2253 2254 /* Restore the original register's value */ 2255 REG_WR(bp, offset, save_val); 2256 2257 /* verify value is as expected */ 2258 if ((val & mask) != (wr_val & mask)) { 2259 DP(BNX2X_MSG_ETHTOOL, 2260 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2261 offset, val, wr_val, mask); 2262 goto test_reg_exit; 2263 } 2264 } 2265 } 2266 2267 rc = 0; 2268 2269 test_reg_exit: 2270 return rc; 2271 } 2272 2273 static int bnx2x_test_memory(struct bnx2x *bp) 2274 { 2275 int i, j, rc = -ENODEV; 2276 u32 val, index; 2277 static const struct { 2278 u32 offset; 2279 int size; 2280 } mem_tbl[] = { 2281 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2282 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2283 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2284 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2285 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2286 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2287 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2288 2289 { 0xffffffff, 0 } 2290 }; 2291 2292 static const struct { 2293 char *name; 2294 u32 offset; 2295 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2296 } prty_tbl[] = { 2297 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2298 {0x3ffc0, 0, 0, 0} }, 2299 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2300 {0x2, 0x2, 0, 0} }, 2301 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2302 {0, 0, 0, 0} }, 2303 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2304 {0x3ffc0, 0, 0, 0} }, 2305 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2306 {0x3ffc0, 0, 0, 0} }, 2307 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2308 {0x3ffc1, 0, 0, 0} }, 2309 2310 { NULL, 0xffffffff, {0, 0, 0, 0} } 2311 }; 2312 2313 if (!bnx2x_is_nvm_accessible(bp)) { 2314 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2315 "cannot access eeprom when the interface is down\n"); 2316 return rc; 2317 } 2318 2319 if (CHIP_IS_E1(bp)) 2320 index = BNX2X_CHIP_E1_OFST; 2321 else if (CHIP_IS_E1H(bp)) 2322 index = BNX2X_CHIP_E1H_OFST; 2323 else if (CHIP_IS_E2(bp)) 2324 index = BNX2X_CHIP_E2_OFST; 2325 else /* e3 */ 2326 index = BNX2X_CHIP_E3_OFST; 2327 2328 /* pre-Check the parity status */ 2329 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2330 val = REG_RD(bp, prty_tbl[i].offset); 2331 if (val & ~(prty_tbl[i].hw_mask[index])) { 2332 DP(BNX2X_MSG_ETHTOOL, 2333 "%s is 0x%x\n", prty_tbl[i].name, val); 2334 goto test_mem_exit; 2335 } 2336 } 2337 2338 /* Go through all the memories */ 2339 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2340 for (j = 0; j < mem_tbl[i].size; j++) 2341 REG_RD(bp, mem_tbl[i].offset + j*4); 2342 2343 /* Check the parity status */ 2344 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2345 val = REG_RD(bp, prty_tbl[i].offset); 2346 if (val & ~(prty_tbl[i].hw_mask[index])) { 2347 DP(BNX2X_MSG_ETHTOOL, 2348 "%s is 0x%x\n", prty_tbl[i].name, val); 2349 goto test_mem_exit; 2350 } 2351 } 2352 2353 rc = 0; 2354 2355 test_mem_exit: 2356 return rc; 2357 } 2358 2359 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2360 { 2361 int cnt = 1400; 2362 2363 if (link_up) { 2364 while (bnx2x_link_test(bp, is_serdes) && cnt--) 2365 msleep(20); 2366 2367 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 2368 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 2369 2370 cnt = 1400; 2371 while (!bp->link_vars.link_up && cnt--) 2372 msleep(20); 2373 2374 if (cnt <= 0 && !bp->link_vars.link_up) 2375 DP(BNX2X_MSG_ETHTOOL, 2376 "Timeout waiting for link init\n"); 2377 } 2378 } 2379 2380 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2381 { 2382 unsigned int pkt_size, num_pkts, i; 2383 struct sk_buff *skb; 2384 unsigned char *packet; 2385 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2386 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 2387 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2388 u16 tx_start_idx, tx_idx; 2389 u16 rx_start_idx, rx_idx; 2390 u16 pkt_prod, bd_prod; 2391 struct sw_tx_bd *tx_buf; 2392 struct eth_tx_start_bd *tx_start_bd; 2393 dma_addr_t mapping; 2394 union eth_rx_cqe *cqe; 2395 u8 cqe_fp_flags, cqe_fp_type; 2396 struct sw_rx_bd *rx_buf; 2397 u16 len; 2398 int rc = -ENODEV; 2399 u8 *data; 2400 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 2401 txdata->txq_index); 2402 2403 /* check the loopback mode */ 2404 switch (loopback_mode) { 2405 case BNX2X_PHY_LOOPBACK: 2406 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 2407 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2408 return -EINVAL; 2409 } 2410 break; 2411 case BNX2X_MAC_LOOPBACK: 2412 if (CHIP_IS_E3(bp)) { 2413 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2414 if (bp->port.supported[cfg_idx] & 2415 (SUPPORTED_10000baseT_Full | 2416 SUPPORTED_20000baseMLD2_Full | 2417 SUPPORTED_20000baseKR2_Full)) 2418 bp->link_params.loopback_mode = LOOPBACK_XMAC; 2419 else 2420 bp->link_params.loopback_mode = LOOPBACK_UMAC; 2421 } else 2422 bp->link_params.loopback_mode = LOOPBACK_BMAC; 2423 2424 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2425 break; 2426 case BNX2X_EXT_LOOPBACK: 2427 if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 2428 DP(BNX2X_MSG_ETHTOOL, 2429 "Can't configure external loopback\n"); 2430 return -EINVAL; 2431 } 2432 break; 2433 default: 2434 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2435 return -EINVAL; 2436 } 2437 2438 /* prepare the loopback packet */ 2439 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2440 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2441 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2442 if (!skb) { 2443 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2444 rc = -ENOMEM; 2445 goto test_loopback_exit; 2446 } 2447 packet = skb_put(skb, pkt_size); 2448 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2449 memset(packet + ETH_ALEN, 0, ETH_ALEN); 2450 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2451 for (i = ETH_HLEN; i < pkt_size; i++) 2452 packet[i] = (unsigned char) (i & 0xff); 2453 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2454 skb_headlen(skb), DMA_TO_DEVICE); 2455 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2456 rc = -ENOMEM; 2457 dev_kfree_skb(skb); 2458 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2459 goto test_loopback_exit; 2460 } 2461 2462 /* send the loopback packet */ 2463 num_pkts = 0; 2464 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2465 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2466 2467 netdev_tx_sent_queue(txq, skb->len); 2468 2469 pkt_prod = txdata->tx_pkt_prod++; 2470 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2471 tx_buf->first_bd = txdata->tx_bd_prod; 2472 tx_buf->skb = skb; 2473 tx_buf->flags = 0; 2474 2475 bd_prod = TX_BD(txdata->tx_bd_prod); 2476 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2477 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2478 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2479 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2480 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2481 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2482 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2483 SET_FLAG(tx_start_bd->general_data, 2484 ETH_TX_START_BD_HDR_NBDS, 2485 1); 2486 SET_FLAG(tx_start_bd->general_data, 2487 ETH_TX_START_BD_PARSE_NBDS, 2488 0); 2489 2490 /* turn on parsing and get a BD */ 2491 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2492 2493 if (CHIP_IS_E1x(bp)) { 2494 u16 global_data = 0; 2495 struct eth_tx_parse_bd_e1x *pbd_e1x = 2496 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2497 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2498 SET_FLAG(global_data, 2499 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2500 pbd_e1x->global_data = cpu_to_le16(global_data); 2501 } else { 2502 u32 parsing_data = 0; 2503 struct eth_tx_parse_bd_e2 *pbd_e2 = 2504 &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2505 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2506 SET_FLAG(parsing_data, 2507 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2508 pbd_e2->parsing_data = cpu_to_le32(parsing_data); 2509 } 2510 wmb(); 2511 2512 txdata->tx_db.data.prod += 2; 2513 barrier(); 2514 DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2515 2516 mmiowb(); 2517 barrier(); 2518 2519 num_pkts++; 2520 txdata->tx_bd_prod += 2; /* start + pbd */ 2521 2522 udelay(100); 2523 2524 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2525 if (tx_idx != tx_start_idx + num_pkts) 2526 goto test_loopback_exit; 2527 2528 /* Unlike HC IGU won't generate an interrupt for status block 2529 * updates that have been performed while interrupts were 2530 * disabled. 2531 */ 2532 if (bp->common.int_block == INT_BLOCK_IGU) { 2533 /* Disable local BHes to prevent a dead-lock situation between 2534 * sch_direct_xmit() and bnx2x_run_loopback() (calling 2535 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2536 */ 2537 local_bh_disable(); 2538 bnx2x_tx_int(bp, txdata); 2539 local_bh_enable(); 2540 } 2541 2542 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2543 if (rx_idx != rx_start_idx + num_pkts) 2544 goto test_loopback_exit; 2545 2546 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2547 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2548 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2549 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2550 goto test_loopback_rx_exit; 2551 2552 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2553 if (len != pkt_size) 2554 goto test_loopback_rx_exit; 2555 2556 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2557 dma_sync_single_for_cpu(&bp->pdev->dev, 2558 dma_unmap_addr(rx_buf, mapping), 2559 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2560 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2561 for (i = ETH_HLEN; i < pkt_size; i++) 2562 if (*(data + i) != (unsigned char) (i & 0xff)) 2563 goto test_loopback_rx_exit; 2564 2565 rc = 0; 2566 2567 test_loopback_rx_exit: 2568 2569 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2570 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2571 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2572 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2573 2574 /* Update producers */ 2575 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2576 fp_rx->rx_sge_prod); 2577 2578 test_loopback_exit: 2579 bp->link_params.loopback_mode = LOOPBACK_NONE; 2580 2581 return rc; 2582 } 2583 2584 static int bnx2x_test_loopback(struct bnx2x *bp) 2585 { 2586 int rc = 0, res; 2587 2588 if (BP_NOMCP(bp)) 2589 return rc; 2590 2591 if (!netif_running(bp->dev)) 2592 return BNX2X_LOOPBACK_FAILED; 2593 2594 bnx2x_netif_stop(bp, 1); 2595 bnx2x_acquire_phy_lock(bp); 2596 2597 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2598 if (res) { 2599 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2600 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2601 } 2602 2603 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2604 if (res) { 2605 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2606 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2607 } 2608 2609 bnx2x_release_phy_lock(bp); 2610 bnx2x_netif_start(bp); 2611 2612 return rc; 2613 } 2614 2615 static int bnx2x_test_ext_loopback(struct bnx2x *bp) 2616 { 2617 int rc; 2618 u8 is_serdes = 2619 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2620 2621 if (BP_NOMCP(bp)) 2622 return -ENODEV; 2623 2624 if (!netif_running(bp->dev)) 2625 return BNX2X_EXT_LOOPBACK_FAILED; 2626 2627 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2628 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 2629 if (rc) { 2630 DP(BNX2X_MSG_ETHTOOL, 2631 "Can't perform self-test, nic_load (for external lb) failed\n"); 2632 return -ENODEV; 2633 } 2634 bnx2x_wait_for_link(bp, 1, is_serdes); 2635 2636 bnx2x_netif_stop(bp, 1); 2637 2638 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 2639 if (rc) 2640 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 2641 2642 bnx2x_netif_start(bp); 2643 2644 return rc; 2645 } 2646 2647 struct code_entry { 2648 u32 sram_start_addr; 2649 u32 code_attribute; 2650 #define CODE_IMAGE_TYPE_MASK 0xf0800003 2651 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2652 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2653 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2654 u32 nvm_start_addr; 2655 }; 2656 2657 #define CODE_ENTRY_MAX 16 2658 #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2659 #define MAX_IMAGES_IN_EXTENDED_DIR 64 2660 #define NVRAM_DIR_OFFSET 0x14 2661 2662 #define EXTENDED_DIR_EXISTS(code) \ 2663 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2664 (code & CODE_IMAGE_LENGTH_MASK) != 0) 2665 2666 #define CRC32_RESIDUAL 0xdebb20e3 2667 #define CRC_BUFF_SIZE 256 2668 2669 static int bnx2x_nvram_crc(struct bnx2x *bp, 2670 int offset, 2671 int size, 2672 u8 *buff) 2673 { 2674 u32 crc = ~0; 2675 int rc = 0, done = 0; 2676 2677 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2678 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2679 2680 while (done < size) { 2681 int count = min_t(int, size - done, CRC_BUFF_SIZE); 2682 2683 rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2684 2685 if (rc) 2686 return rc; 2687 2688 crc = crc32_le(crc, buff, count); 2689 done += count; 2690 } 2691 2692 if (crc != CRC32_RESIDUAL) 2693 rc = -EINVAL; 2694 2695 return rc; 2696 } 2697 2698 static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2699 struct code_entry *entry, 2700 u8 *buff) 2701 { 2702 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2703 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2704 int rc; 2705 2706 /* Zero-length images and AFEX profiles do not have CRC */ 2707 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2708 return 0; 2709 2710 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2711 if (rc) 2712 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2713 "image %x has failed crc test (rc %d)\n", type, rc); 2714 2715 return rc; 2716 } 2717 2718 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2719 { 2720 int rc; 2721 struct code_entry entry; 2722 2723 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2724 if (rc) 2725 return rc; 2726 2727 return bnx2x_test_nvram_dir(bp, &entry, buff); 2728 } 2729 2730 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2731 { 2732 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2733 struct code_entry entry; 2734 int i; 2735 2736 rc = bnx2x_nvram_read32(bp, 2737 dir_offset + 2738 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2739 (u32 *)&entry, sizeof(entry)); 2740 if (rc) 2741 return rc; 2742 2743 if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2744 return 0; 2745 2746 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2747 &cnt, sizeof(u32)); 2748 if (rc) 2749 return rc; 2750 2751 dir_offset = entry.nvm_start_addr + 8; 2752 2753 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2754 rc = bnx2x_test_dir_entry(bp, dir_offset + 2755 sizeof(struct code_entry) * i, 2756 buff); 2757 if (rc) 2758 return rc; 2759 } 2760 2761 return 0; 2762 } 2763 2764 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2765 { 2766 u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2767 int i; 2768 2769 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2770 2771 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2772 rc = bnx2x_test_dir_entry(bp, dir_offset + 2773 sizeof(struct code_entry) * i, 2774 buff); 2775 if (rc) 2776 return rc; 2777 } 2778 2779 return bnx2x_test_nvram_ext_dirs(bp, buff); 2780 } 2781 2782 struct crc_pair { 2783 int offset; 2784 int size; 2785 }; 2786 2787 static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2788 const struct crc_pair *nvram_tbl, u8 *buf) 2789 { 2790 int i; 2791 2792 for (i = 0; nvram_tbl[i].size; i++) { 2793 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2794 nvram_tbl[i].size, buf); 2795 if (rc) { 2796 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2797 "nvram_tbl[%d] has failed crc test (rc %d)\n", 2798 i, rc); 2799 return rc; 2800 } 2801 } 2802 2803 return 0; 2804 } 2805 2806 static int bnx2x_test_nvram(struct bnx2x *bp) 2807 { 2808 const struct crc_pair nvram_tbl[] = { 2809 { 0, 0x14 }, /* bootstrap */ 2810 { 0x14, 0xec }, /* dir */ 2811 { 0x100, 0x350 }, /* manuf_info */ 2812 { 0x450, 0xf0 }, /* feature_info */ 2813 { 0x640, 0x64 }, /* upgrade_key_info */ 2814 { 0x708, 0x70 }, /* manuf_key_info */ 2815 { 0, 0 } 2816 }; 2817 const struct crc_pair nvram_tbl2[] = { 2818 { 0x7e8, 0x350 }, /* manuf_info2 */ 2819 { 0xb38, 0xf0 }, /* feature_info */ 2820 { 0, 0 } 2821 }; 2822 2823 u8 *buf; 2824 int rc; 2825 u32 magic; 2826 2827 if (BP_NOMCP(bp)) 2828 return 0; 2829 2830 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2831 if (!buf) { 2832 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2833 rc = -ENOMEM; 2834 goto test_nvram_exit; 2835 } 2836 2837 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2838 if (rc) { 2839 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2840 "magic value read (rc %d)\n", rc); 2841 goto test_nvram_exit; 2842 } 2843 2844 if (magic != 0x669955aa) { 2845 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2846 "wrong magic value (0x%08x)\n", magic); 2847 rc = -ENODEV; 2848 goto test_nvram_exit; 2849 } 2850 2851 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2852 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2853 if (rc) 2854 goto test_nvram_exit; 2855 2856 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2857 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2858 SHARED_HW_CFG_HIDE_PORT1; 2859 2860 if (!hide) { 2861 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2862 "Port 1 CRC test-set\n"); 2863 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2864 if (rc) 2865 goto test_nvram_exit; 2866 } 2867 } 2868 2869 rc = bnx2x_test_nvram_dirs(bp, buf); 2870 2871 test_nvram_exit: 2872 kfree(buf); 2873 return rc; 2874 } 2875 2876 /* Send an EMPTY ramrod on the first queue */ 2877 static int bnx2x_test_intr(struct bnx2x *bp) 2878 { 2879 struct bnx2x_queue_state_params params = {NULL}; 2880 2881 if (!netif_running(bp->dev)) { 2882 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2883 "cannot access eeprom when the interface is down\n"); 2884 return -ENODEV; 2885 } 2886 2887 params.q_obj = &bp->sp_objs->q_obj; 2888 params.cmd = BNX2X_Q_CMD_EMPTY; 2889 2890 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2891 2892 return bnx2x_queue_state_change(bp, ¶ms); 2893 } 2894 2895 static void bnx2x_self_test(struct net_device *dev, 2896 struct ethtool_test *etest, u64 *buf) 2897 { 2898 struct bnx2x *bp = netdev_priv(dev); 2899 u8 is_serdes, link_up; 2900 int rc, cnt = 0; 2901 2902 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2903 netdev_err(bp->dev, 2904 "Handling parity error recovery. Try again later\n"); 2905 etest->flags |= ETH_TEST_FL_FAILED; 2906 return; 2907 } 2908 2909 DP(BNX2X_MSG_ETHTOOL, 2910 "Self-test command parameters: offline = %d, external_lb = %d\n", 2911 (etest->flags & ETH_TEST_FL_OFFLINE), 2912 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2913 2914 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2915 2916 if (bnx2x_test_nvram(bp) != 0) { 2917 if (!IS_MF(bp)) 2918 buf[4] = 1; 2919 else 2920 buf[0] = 1; 2921 etest->flags |= ETH_TEST_FL_FAILED; 2922 } 2923 2924 if (!netif_running(dev)) { 2925 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2926 return; 2927 } 2928 2929 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2930 link_up = bp->link_vars.link_up; 2931 /* offline tests are not supported in MF mode */ 2932 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2933 int port = BP_PORT(bp); 2934 u32 val; 2935 2936 /* save current value of input enable for TX port IF */ 2937 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2938 /* disable input for TX port IF */ 2939 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2940 2941 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2942 rc = bnx2x_nic_load(bp, LOAD_DIAG); 2943 if (rc) { 2944 etest->flags |= ETH_TEST_FL_FAILED; 2945 DP(BNX2X_MSG_ETHTOOL, 2946 "Can't perform self-test, nic_load (for offline) failed\n"); 2947 return; 2948 } 2949 2950 /* wait until link state is restored */ 2951 bnx2x_wait_for_link(bp, 1, is_serdes); 2952 2953 if (bnx2x_test_registers(bp) != 0) { 2954 buf[0] = 1; 2955 etest->flags |= ETH_TEST_FL_FAILED; 2956 } 2957 if (bnx2x_test_memory(bp) != 0) { 2958 buf[1] = 1; 2959 etest->flags |= ETH_TEST_FL_FAILED; 2960 } 2961 2962 buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2963 if (buf[2] != 0) 2964 etest->flags |= ETH_TEST_FL_FAILED; 2965 2966 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 2967 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 2968 if (buf[3] != 0) 2969 etest->flags |= ETH_TEST_FL_FAILED; 2970 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 2971 } 2972 2973 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2974 2975 /* restore input for TX port IF */ 2976 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2977 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2978 if (rc) { 2979 etest->flags |= ETH_TEST_FL_FAILED; 2980 DP(BNX2X_MSG_ETHTOOL, 2981 "Can't perform self-test, nic_load (for online) failed\n"); 2982 return; 2983 } 2984 /* wait until link state is restored */ 2985 bnx2x_wait_for_link(bp, link_up, is_serdes); 2986 } 2987 2988 if (bnx2x_test_intr(bp) != 0) { 2989 if (!IS_MF(bp)) 2990 buf[5] = 1; 2991 else 2992 buf[1] = 1; 2993 etest->flags |= ETH_TEST_FL_FAILED; 2994 } 2995 2996 if (link_up) { 2997 cnt = 100; 2998 while (bnx2x_link_test(bp, is_serdes) && --cnt) 2999 msleep(20); 3000 } 3001 3002 if (!cnt) { 3003 if (!IS_MF(bp)) 3004 buf[6] = 1; 3005 else 3006 buf[2] = 1; 3007 etest->flags |= ETH_TEST_FL_FAILED; 3008 } 3009 } 3010 3011 #define IS_PORT_STAT(i) \ 3012 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 3013 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 3014 #define HIDE_PORT_STAT(bp) \ 3015 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \ 3016 IS_VF(bp)) 3017 3018 /* ethtool statistics are displayed for all regular ethernet queues and the 3019 * fcoe L2 queue if not disabled 3020 */ 3021 static int bnx2x_num_stat_queues(struct bnx2x *bp) 3022 { 3023 return BNX2X_NUM_ETH_QUEUES(bp); 3024 } 3025 3026 static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3027 { 3028 struct bnx2x *bp = netdev_priv(dev); 3029 int i, num_strings = 0; 3030 3031 switch (stringset) { 3032 case ETH_SS_STATS: 3033 if (is_multi(bp)) { 3034 num_strings = bnx2x_num_stat_queues(bp) * 3035 BNX2X_NUM_Q_STATS; 3036 } else 3037 num_strings = 0; 3038 if (HIDE_PORT_STAT(bp)) { 3039 for (i = 0; i < BNX2X_NUM_STATS; i++) 3040 if (IS_FUNC_STAT(i)) 3041 num_strings++; 3042 } else 3043 num_strings += BNX2X_NUM_STATS; 3044 3045 return num_strings; 3046 3047 case ETH_SS_TEST: 3048 return BNX2X_NUM_TESTS(bp); 3049 3050 case ETH_SS_PRIV_FLAGS: 3051 return BNX2X_PRI_FLAG_LEN; 3052 3053 default: 3054 return -EINVAL; 3055 } 3056 } 3057 3058 static u32 bnx2x_get_private_flags(struct net_device *dev) 3059 { 3060 struct bnx2x *bp = netdev_priv(dev); 3061 u32 flags = 0; 3062 3063 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 3064 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 3065 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 3066 3067 return flags; 3068 } 3069 3070 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3071 { 3072 struct bnx2x *bp = netdev_priv(dev); 3073 int i, j, k, start; 3074 char queue_name[MAX_QUEUE_NAME_LEN+1]; 3075 3076 switch (stringset) { 3077 case ETH_SS_STATS: 3078 k = 0; 3079 if (is_multi(bp)) { 3080 for_each_eth_queue(bp, i) { 3081 memset(queue_name, 0, sizeof(queue_name)); 3082 sprintf(queue_name, "%d", i); 3083 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3084 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3085 ETH_GSTRING_LEN, 3086 bnx2x_q_stats_arr[j].string, 3087 queue_name); 3088 k += BNX2X_NUM_Q_STATS; 3089 } 3090 } 3091 3092 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3093 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3094 continue; 3095 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3096 bnx2x_stats_arr[i].string); 3097 j++; 3098 } 3099 3100 break; 3101 3102 case ETH_SS_TEST: 3103 /* First 4 tests cannot be done in MF mode */ 3104 if (!IS_MF(bp)) 3105 start = 0; 3106 else 3107 start = 4; 3108 memcpy(buf, bnx2x_tests_str_arr + start, 3109 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 3110 break; 3111 3112 case ETH_SS_PRIV_FLAGS: 3113 memcpy(buf, bnx2x_private_arr, 3114 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 3115 break; 3116 } 3117 } 3118 3119 static void bnx2x_get_ethtool_stats(struct net_device *dev, 3120 struct ethtool_stats *stats, u64 *buf) 3121 { 3122 struct bnx2x *bp = netdev_priv(dev); 3123 u32 *hw_stats, *offset; 3124 int i, j, k = 0; 3125 3126 if (is_multi(bp)) { 3127 for_each_eth_queue(bp, i) { 3128 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3129 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3130 if (bnx2x_q_stats_arr[j].size == 0) { 3131 /* skip this counter */ 3132 buf[k + j] = 0; 3133 continue; 3134 } 3135 offset = (hw_stats + 3136 bnx2x_q_stats_arr[j].offset); 3137 if (bnx2x_q_stats_arr[j].size == 4) { 3138 /* 4-byte counter */ 3139 buf[k + j] = (u64) *offset; 3140 continue; 3141 } 3142 /* 8-byte counter */ 3143 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3144 } 3145 k += BNX2X_NUM_Q_STATS; 3146 } 3147 } 3148 3149 hw_stats = (u32 *)&bp->eth_stats; 3150 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3151 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3152 continue; 3153 if (bnx2x_stats_arr[i].size == 0) { 3154 /* skip this counter */ 3155 buf[k + j] = 0; 3156 j++; 3157 continue; 3158 } 3159 offset = (hw_stats + bnx2x_stats_arr[i].offset); 3160 if (bnx2x_stats_arr[i].size == 4) { 3161 /* 4-byte counter */ 3162 buf[k + j] = (u64) *offset; 3163 j++; 3164 continue; 3165 } 3166 /* 8-byte counter */ 3167 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3168 j++; 3169 } 3170 } 3171 3172 static int bnx2x_set_phys_id(struct net_device *dev, 3173 enum ethtool_phys_id_state state) 3174 { 3175 struct bnx2x *bp = netdev_priv(dev); 3176 3177 if (!bnx2x_is_nvm_accessible(bp)) { 3178 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 3179 "cannot access eeprom when the interface is down\n"); 3180 return -EAGAIN; 3181 } 3182 3183 switch (state) { 3184 case ETHTOOL_ID_ACTIVE: 3185 return 1; /* cycle on/off once per second */ 3186 3187 case ETHTOOL_ID_ON: 3188 bnx2x_acquire_phy_lock(bp); 3189 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3190 LED_MODE_ON, SPEED_1000); 3191 bnx2x_release_phy_lock(bp); 3192 break; 3193 3194 case ETHTOOL_ID_OFF: 3195 bnx2x_acquire_phy_lock(bp); 3196 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3197 LED_MODE_FRONT_PANEL_OFF, 0); 3198 bnx2x_release_phy_lock(bp); 3199 break; 3200 3201 case ETHTOOL_ID_INACTIVE: 3202 bnx2x_acquire_phy_lock(bp); 3203 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3204 LED_MODE_OPER, 3205 bp->link_vars.line_speed); 3206 bnx2x_release_phy_lock(bp); 3207 } 3208 3209 return 0; 3210 } 3211 3212 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3213 { 3214 switch (info->flow_type) { 3215 case TCP_V4_FLOW: 3216 case TCP_V6_FLOW: 3217 info->data = RXH_IP_SRC | RXH_IP_DST | 3218 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3219 break; 3220 case UDP_V4_FLOW: 3221 if (bp->rss_conf_obj.udp_rss_v4) 3222 info->data = RXH_IP_SRC | RXH_IP_DST | 3223 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3224 else 3225 info->data = RXH_IP_SRC | RXH_IP_DST; 3226 break; 3227 case UDP_V6_FLOW: 3228 if (bp->rss_conf_obj.udp_rss_v6) 3229 info->data = RXH_IP_SRC | RXH_IP_DST | 3230 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3231 else 3232 info->data = RXH_IP_SRC | RXH_IP_DST; 3233 break; 3234 case IPV4_FLOW: 3235 case IPV6_FLOW: 3236 info->data = RXH_IP_SRC | RXH_IP_DST; 3237 break; 3238 default: 3239 info->data = 0; 3240 break; 3241 } 3242 3243 return 0; 3244 } 3245 3246 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3247 u32 *rules __always_unused) 3248 { 3249 struct bnx2x *bp = netdev_priv(dev); 3250 3251 switch (info->cmd) { 3252 case ETHTOOL_GRXRINGS: 3253 info->data = BNX2X_NUM_ETH_QUEUES(bp); 3254 return 0; 3255 case ETHTOOL_GRXFH: 3256 return bnx2x_get_rss_flags(bp, info); 3257 default: 3258 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3259 return -EOPNOTSUPP; 3260 } 3261 } 3262 3263 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3264 { 3265 int udp_rss_requested; 3266 3267 DP(BNX2X_MSG_ETHTOOL, 3268 "Set rss flags command parameters: flow type = %d, data = %llu\n", 3269 info->flow_type, info->data); 3270 3271 switch (info->flow_type) { 3272 case TCP_V4_FLOW: 3273 case TCP_V6_FLOW: 3274 /* For TCP only 4-tupple hash is supported */ 3275 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 3276 RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 3277 DP(BNX2X_MSG_ETHTOOL, 3278 "Command parameters not supported\n"); 3279 return -EINVAL; 3280 } 3281 return 0; 3282 3283 case UDP_V4_FLOW: 3284 case UDP_V6_FLOW: 3285 /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 3286 if (info->data == (RXH_IP_SRC | RXH_IP_DST | 3287 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3288 udp_rss_requested = 1; 3289 else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 3290 udp_rss_requested = 0; 3291 else 3292 return -EINVAL; 3293 if ((info->flow_type == UDP_V4_FLOW) && 3294 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 3295 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 3296 DP(BNX2X_MSG_ETHTOOL, 3297 "rss re-configured, UDP 4-tupple %s\n", 3298 udp_rss_requested ? "enabled" : "disabled"); 3299 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3300 } else if ((info->flow_type == UDP_V6_FLOW) && 3301 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 3302 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 3303 DP(BNX2X_MSG_ETHTOOL, 3304 "rss re-configured, UDP 4-tupple %s\n", 3305 udp_rss_requested ? "enabled" : "disabled"); 3306 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3307 } 3308 return 0; 3309 3310 case IPV4_FLOW: 3311 case IPV6_FLOW: 3312 /* For IP only 2-tupple hash is supported */ 3313 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 3314 DP(BNX2X_MSG_ETHTOOL, 3315 "Command parameters not supported\n"); 3316 return -EINVAL; 3317 } 3318 return 0; 3319 3320 case SCTP_V4_FLOW: 3321 case AH_ESP_V4_FLOW: 3322 case AH_V4_FLOW: 3323 case ESP_V4_FLOW: 3324 case SCTP_V6_FLOW: 3325 case AH_ESP_V6_FLOW: 3326 case AH_V6_FLOW: 3327 case ESP_V6_FLOW: 3328 case IP_USER_FLOW: 3329 case ETHER_FLOW: 3330 /* RSS is not supported for these protocols */ 3331 if (info->data) { 3332 DP(BNX2X_MSG_ETHTOOL, 3333 "Command parameters not supported\n"); 3334 return -EINVAL; 3335 } 3336 return 0; 3337 3338 default: 3339 return -EINVAL; 3340 } 3341 } 3342 3343 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 3344 { 3345 struct bnx2x *bp = netdev_priv(dev); 3346 3347 switch (info->cmd) { 3348 case ETHTOOL_SRXFH: 3349 return bnx2x_set_rss_flags(bp, info); 3350 default: 3351 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3352 return -EOPNOTSUPP; 3353 } 3354 } 3355 3356 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3357 { 3358 return T_ETH_INDIRECTION_TABLE_SIZE; 3359 } 3360 3361 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3362 u8 *hfunc) 3363 { 3364 struct bnx2x *bp = netdev_priv(dev); 3365 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3366 size_t i; 3367 3368 if (hfunc) 3369 *hfunc = ETH_RSS_HASH_TOP; 3370 if (!indir) 3371 return 0; 3372 3373 /* Get the current configuration of the RSS indirection table */ 3374 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3375 3376 /* 3377 * We can't use a memcpy() as an internal storage of an 3378 * indirection table is a u8 array while indir->ring_index 3379 * points to an array of u32. 3380 * 3381 * Indirection table contains the FW Client IDs, so we need to 3382 * align the returned table to the Client ID of the leading RSS 3383 * queue. 3384 */ 3385 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 3386 indir[i] = ind_table[i] - bp->fp->cl_id; 3387 3388 return 0; 3389 } 3390 3391 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3392 const u8 *key, const u8 hfunc) 3393 { 3394 struct bnx2x *bp = netdev_priv(dev); 3395 size_t i; 3396 3397 /* We require at least one supported parameter to be changed and no 3398 * change in any of the unsupported parameters 3399 */ 3400 if (key || 3401 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3402 return -EOPNOTSUPP; 3403 3404 if (!indir) 3405 return 0; 3406 3407 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3408 /* 3409 * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3410 * as an internal storage of an indirection table is a u8 array 3411 * while indir->ring_index points to an array of u32. 3412 * 3413 * Indirection table contains the FW Client IDs, so we need to 3414 * align the received table to the Client ID of the leading RSS 3415 * queue 3416 */ 3417 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3418 } 3419 3420 return bnx2x_config_rss_eth(bp, false); 3421 } 3422 3423 /** 3424 * bnx2x_get_channels - gets the number of RSS queues. 3425 * 3426 * @dev: net device 3427 * @channels: returns the number of max / current queues 3428 */ 3429 static void bnx2x_get_channels(struct net_device *dev, 3430 struct ethtool_channels *channels) 3431 { 3432 struct bnx2x *bp = netdev_priv(dev); 3433 3434 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 3435 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 3436 } 3437 3438 /** 3439 * bnx2x_change_num_queues - change the number of RSS queues. 3440 * 3441 * @bp: bnx2x private structure 3442 * 3443 * Re-configure interrupt mode to get the new number of MSI-X 3444 * vectors and re-add NAPI objects. 3445 */ 3446 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 3447 { 3448 bnx2x_disable_msi(bp); 3449 bp->num_ethernet_queues = num_rss; 3450 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 3451 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 3452 bnx2x_set_int_mode(bp); 3453 } 3454 3455 /** 3456 * bnx2x_set_channels - sets the number of RSS queues. 3457 * 3458 * @dev: net device 3459 * @channels: includes the number of queues requested 3460 */ 3461 static int bnx2x_set_channels(struct net_device *dev, 3462 struct ethtool_channels *channels) 3463 { 3464 struct bnx2x *bp = netdev_priv(dev); 3465 3466 DP(BNX2X_MSG_ETHTOOL, 3467 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 3468 channels->rx_count, channels->tx_count, channels->other_count, 3469 channels->combined_count); 3470 3471 /* We don't support separate rx / tx channels. 3472 * We don't allow setting 'other' channels. 3473 */ 3474 if (channels->rx_count || channels->tx_count || channels->other_count 3475 || (channels->combined_count == 0) || 3476 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 3477 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 3478 return -EINVAL; 3479 } 3480 3481 /* Check if there was a change in the active parameters */ 3482 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 3483 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 3484 return 0; 3485 } 3486 3487 /* Set the requested number of queues in bp context. 3488 * Note that the actual number of queues created during load may be 3489 * less than requested if memory is low. 3490 */ 3491 if (unlikely(!netif_running(dev))) { 3492 bnx2x_change_num_queues(bp, channels->combined_count); 3493 return 0; 3494 } 3495 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 3496 bnx2x_change_num_queues(bp, channels->combined_count); 3497 return bnx2x_nic_load(bp, LOAD_NORMAL); 3498 } 3499 3500 static int bnx2x_get_ts_info(struct net_device *dev, 3501 struct ethtool_ts_info *info) 3502 { 3503 struct bnx2x *bp = netdev_priv(dev); 3504 3505 if (bp->flags & PTP_SUPPORTED) { 3506 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3507 SOF_TIMESTAMPING_RX_SOFTWARE | 3508 SOF_TIMESTAMPING_SOFTWARE | 3509 SOF_TIMESTAMPING_TX_HARDWARE | 3510 SOF_TIMESTAMPING_RX_HARDWARE | 3511 SOF_TIMESTAMPING_RAW_HARDWARE; 3512 3513 if (bp->ptp_clock) 3514 info->phc_index = ptp_clock_index(bp->ptp_clock); 3515 else 3516 info->phc_index = -1; 3517 3518 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3519 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3520 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3521 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3522 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3523 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 3524 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 3525 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 3526 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 3527 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 3528 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 3529 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 3530 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 3531 3532 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3533 3534 return 0; 3535 } 3536 3537 return ethtool_op_get_ts_info(dev, info); 3538 } 3539 3540 static const struct ethtool_ops bnx2x_ethtool_ops = { 3541 .get_settings = bnx2x_get_settings, 3542 .set_settings = bnx2x_set_settings, 3543 .get_drvinfo = bnx2x_get_drvinfo, 3544 .get_regs_len = bnx2x_get_regs_len, 3545 .get_regs = bnx2x_get_regs, 3546 .get_dump_flag = bnx2x_get_dump_flag, 3547 .get_dump_data = bnx2x_get_dump_data, 3548 .set_dump = bnx2x_set_dump, 3549 .get_wol = bnx2x_get_wol, 3550 .set_wol = bnx2x_set_wol, 3551 .get_msglevel = bnx2x_get_msglevel, 3552 .set_msglevel = bnx2x_set_msglevel, 3553 .nway_reset = bnx2x_nway_reset, 3554 .get_link = bnx2x_get_link, 3555 .get_eeprom_len = bnx2x_get_eeprom_len, 3556 .get_eeprom = bnx2x_get_eeprom, 3557 .set_eeprom = bnx2x_set_eeprom, 3558 .get_coalesce = bnx2x_get_coalesce, 3559 .set_coalesce = bnx2x_set_coalesce, 3560 .get_ringparam = bnx2x_get_ringparam, 3561 .set_ringparam = bnx2x_set_ringparam, 3562 .get_pauseparam = bnx2x_get_pauseparam, 3563 .set_pauseparam = bnx2x_set_pauseparam, 3564 .self_test = bnx2x_self_test, 3565 .get_sset_count = bnx2x_get_sset_count, 3566 .get_priv_flags = bnx2x_get_private_flags, 3567 .get_strings = bnx2x_get_strings, 3568 .set_phys_id = bnx2x_set_phys_id, 3569 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3570 .get_rxnfc = bnx2x_get_rxnfc, 3571 .set_rxnfc = bnx2x_set_rxnfc, 3572 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3573 .get_rxfh = bnx2x_get_rxfh, 3574 .set_rxfh = bnx2x_set_rxfh, 3575 .get_channels = bnx2x_get_channels, 3576 .set_channels = bnx2x_set_channels, 3577 .get_module_info = bnx2x_get_module_info, 3578 .get_module_eeprom = bnx2x_get_module_eeprom, 3579 .get_eee = bnx2x_get_eee, 3580 .set_eee = bnx2x_set_eee, 3581 .get_ts_info = bnx2x_get_ts_info, 3582 }; 3583 3584 static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3585 .get_settings = bnx2x_get_vf_settings, 3586 .get_drvinfo = bnx2x_get_drvinfo, 3587 .get_msglevel = bnx2x_get_msglevel, 3588 .set_msglevel = bnx2x_set_msglevel, 3589 .get_link = bnx2x_get_link, 3590 .get_coalesce = bnx2x_get_coalesce, 3591 .get_ringparam = bnx2x_get_ringparam, 3592 .set_ringparam = bnx2x_set_ringparam, 3593 .get_sset_count = bnx2x_get_sset_count, 3594 .get_strings = bnx2x_get_strings, 3595 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3596 .get_rxnfc = bnx2x_get_rxnfc, 3597 .set_rxnfc = bnx2x_set_rxnfc, 3598 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3599 .get_rxfh = bnx2x_get_rxfh, 3600 .set_rxfh = bnx2x_set_rxfh, 3601 .get_channels = bnx2x_get_channels, 3602 .set_channels = bnx2x_set_channels, 3603 }; 3604 3605 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3606 { 3607 netdev->ethtool_ops = (IS_PF(bp)) ? 3608 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3609 } 3610