1 /* bnx2x_ethtool.c: QLogic Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  * Copyright (c) 2014 QLogic Corporation
5  * All rights reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12  * Written by: Eliezer Tamir
13  * Based on code from Michael Chan's bnx2 driver
14  * UDP CSUM errata workaround by Arik Gendelman
15  * Slowpath and fastpath rework by Vladislav Zolotarov
16  * Statistics and Link management by Yitchak Gertner
17  *
18  */
19 
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 
22 #include <linux/ethtool.h>
23 #include <linux/netdevice.h>
24 #include <linux/types.h>
25 #include <linux/sched.h>
26 #include <linux/crc32.h>
27 #include "bnx2x.h"
28 #include "bnx2x_cmn.h"
29 #include "bnx2x_dump.h"
30 #include "bnx2x_init.h"
31 
32 /* Note: in the format strings below %s is replaced by the queue-name which is
33  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
34  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
35  */
36 #define MAX_QUEUE_NAME_LEN	4
37 static const struct {
38 	long offset;
39 	int size;
40 	char string[ETH_GSTRING_LEN];
41 } bnx2x_q_stats_arr[] = {
42 /* 1 */	{ Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
43 	{ Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 						8, "[%s]: rx_ucast_packets" },
45 	{ Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 						8, "[%s]: rx_mcast_packets" },
47 	{ Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 						8, "[%s]: rx_bcast_packets" },
49 	{ Q_STATS_OFFSET32(no_buff_discard_hi),	8, "[%s]: rx_discards" },
50 	{ Q_STATS_OFFSET32(rx_err_discard_pkt),
51 					 4, "[%s]: rx_phy_ip_err_discards"},
52 	{ Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 					 4, "[%s]: rx_skb_alloc_discard" },
54 	{ Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
55 	{ Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
56 	{ Q_STATS_OFFSET32(total_bytes_transmitted_hi),	8, "[%s]: tx_bytes" },
57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
58 						8, "[%s]: tx_ucast_packets" },
59 	{ Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 						8, "[%s]: tx_mcast_packets" },
61 	{ Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
62 						8, "[%s]: tx_bcast_packets" },
63 	{ Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 						8, "[%s]: tpa_aggregations" },
65 	{ Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 					8, "[%s]: tpa_aggregated_frames"},
67 	{ Q_STATS_OFFSET32(total_tpa_bytes_hi),	8, "[%s]: tpa_bytes"},
68 	{ Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 					4, "[%s]: driver_filtered_tx_pkt" }
70 };
71 
72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
73 
74 static const struct {
75 	long offset;
76 	int size;
77 	bool is_port_stat;
78 	char string[ETH_GSTRING_LEN];
79 } bnx2x_stats_arr[] = {
80 /* 1 */	{ STATS_OFFSET32(total_bytes_received_hi),
81 				8, false, "rx_bytes" },
82 	{ STATS_OFFSET32(error_bytes_received_hi),
83 				8, false, "rx_error_bytes" },
84 	{ STATS_OFFSET32(total_unicast_packets_received_hi),
85 				8, false, "rx_ucast_packets" },
86 	{ STATS_OFFSET32(total_multicast_packets_received_hi),
87 				8, false, "rx_mcast_packets" },
88 	{ STATS_OFFSET32(total_broadcast_packets_received_hi),
89 				8, false, "rx_bcast_packets" },
90 	{ STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
91 				8, true, "rx_crc_errors" },
92 	{ STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
93 				8, true, "rx_align_errors" },
94 	{ STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
95 				8, true, "rx_undersize_packets" },
96 	{ STATS_OFFSET32(etherstatsoverrsizepkts_hi),
97 				8, true, "rx_oversize_packets" },
98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
99 				8, true, "rx_fragments" },
100 	{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
101 				8, true, "rx_jabbers" },
102 	{ STATS_OFFSET32(no_buff_discard_hi),
103 				8, false, "rx_discards" },
104 	{ STATS_OFFSET32(mac_filter_discard),
105 				4, true, "rx_filtered_packets" },
106 	{ STATS_OFFSET32(mf_tag_discard),
107 				4, true, "rx_mf_tag_discard" },
108 	{ STATS_OFFSET32(pfc_frames_received_hi),
109 				8, true, "pfc_frames_received" },
110 	{ STATS_OFFSET32(pfc_frames_sent_hi),
111 				8, true, "pfc_frames_sent" },
112 	{ STATS_OFFSET32(brb_drop_hi),
113 				8, true, "rx_brb_discard" },
114 	{ STATS_OFFSET32(brb_truncate_hi),
115 				8, true, "rx_brb_truncate" },
116 	{ STATS_OFFSET32(pause_frames_received_hi),
117 				8, true, "rx_pause_frames" },
118 	{ STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
119 				8, true, "rx_mac_ctrl_frames" },
120 	{ STATS_OFFSET32(nig_timer_max),
121 				4, true, "rx_constant_pause_events" },
122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
123 				4, false, "rx_phy_ip_err_discards"},
124 	{ STATS_OFFSET32(rx_skb_alloc_failed),
125 				4, false, "rx_skb_alloc_discard" },
126 	{ STATS_OFFSET32(hw_csum_err),
127 				4, false, "rx_csum_offload_errors" },
128 	{ STATS_OFFSET32(driver_xoff),
129 				4, false, "tx_exhaustion_events" },
130 	{ STATS_OFFSET32(total_bytes_transmitted_hi),
131 				8, false, "tx_bytes" },
132 	{ STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 				8, true, "tx_error_bytes" },
134 	{ STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 				8, false, "tx_ucast_packets" },
136 	{ STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 				8, false, "tx_mcast_packets" },
138 	{ STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 				8, false, "tx_bcast_packets" },
140 	{ STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 				8, true, "tx_mac_errors" },
142 	{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 				8, true, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 				8, true, "tx_single_collisions" },
146 	{ STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 				8, true, "tx_multi_collisions" },
148 	{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 				8, true, "tx_deferred" },
150 	{ STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 				8, true, "tx_excess_collisions" },
152 	{ STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 				8, true, "tx_late_collisions" },
154 	{ STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 				8, true, "tx_total_collisions" },
156 	{ STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 				8, true, "tx_64_byte_packets" },
158 	{ STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 				8, true, "tx_65_to_127_byte_packets" },
160 	{ STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 				8, true, "tx_128_to_255_byte_packets" },
162 	{ STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 				8, true, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 				8, true, "tx_512_to_1023_byte_packets" },
166 	{ STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 				8, true, "tx_1024_to_1522_byte_packets" },
168 	{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 				8, true, "tx_1523_to_9022_byte_packets" },
170 	{ STATS_OFFSET32(pause_frames_sent_hi),
171 				8, true, "tx_pause_frames" },
172 	{ STATS_OFFSET32(total_tpa_aggregations_hi),
173 				8, false, "tpa_aggregations" },
174 	{ STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 				8, false, "tpa_aggregated_frames"},
176 	{ STATS_OFFSET32(total_tpa_bytes_hi),
177 				8, false, "tpa_bytes"},
178 	{ STATS_OFFSET32(recoverable_error),
179 				4, false, "recoverable_errors" },
180 	{ STATS_OFFSET32(unrecoverable_error),
181 				4, false, "unrecoverable_errors" },
182 	{ STATS_OFFSET32(driver_filtered_tx_pkt),
183 				4, false, "driver_filtered_tx_pkt" },
184 	{ STATS_OFFSET32(eee_tx_lpi),
185 				4, true, "Tx LPI entry count"}
186 };
187 
188 #define BNX2X_NUM_STATS		ARRAY_SIZE(bnx2x_stats_arr)
189 
190 static int bnx2x_get_port_type(struct bnx2x *bp)
191 {
192 	int port_type;
193 	u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 	switch (bp->link_params.phy[phy_idx].media_type) {
195 	case ETH_PHY_SFPP_10G_FIBER:
196 	case ETH_PHY_SFP_1G_FIBER:
197 	case ETH_PHY_XFP_FIBER:
198 	case ETH_PHY_KR:
199 	case ETH_PHY_CX4:
200 		port_type = PORT_FIBRE;
201 		break;
202 	case ETH_PHY_DA_TWINAX:
203 		port_type = PORT_DA;
204 		break;
205 	case ETH_PHY_BASE_T:
206 		port_type = PORT_TP;
207 		break;
208 	case ETH_PHY_NOT_PRESENT:
209 		port_type = PORT_NONE;
210 		break;
211 	case ETH_PHY_UNSPECIFIED:
212 	default:
213 		port_type = PORT_OTHER;
214 		break;
215 	}
216 	return port_type;
217 }
218 
219 static int bnx2x_get_vf_link_ksettings(struct net_device *dev,
220 				       struct ethtool_link_ksettings *cmd)
221 {
222 	struct bnx2x *bp = netdev_priv(dev);
223 	u32 supported, advertising;
224 
225 	ethtool_convert_link_mode_to_legacy_u32(&supported,
226 						cmd->link_modes.supported);
227 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
228 						cmd->link_modes.advertising);
229 
230 	if (bp->state == BNX2X_STATE_OPEN) {
231 		if (test_bit(BNX2X_LINK_REPORT_FD,
232 			     &bp->vf_link_vars.link_report_flags))
233 			cmd->base.duplex = DUPLEX_FULL;
234 		else
235 			cmd->base.duplex = DUPLEX_HALF;
236 
237 		cmd->base.speed = bp->vf_link_vars.line_speed;
238 	} else {
239 		cmd->base.duplex = DUPLEX_UNKNOWN;
240 		cmd->base.speed = SPEED_UNKNOWN;
241 	}
242 
243 	cmd->base.port		= PORT_OTHER;
244 	cmd->base.phy_address	= 0;
245 	cmd->base.autoneg	= AUTONEG_DISABLE;
246 
247 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
248 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
249 	   "  duplex %d  port %d  phy_address %d\n"
250 	   "  autoneg %d\n",
251 	   cmd->base.cmd, supported, advertising,
252 	   cmd->base.speed,
253 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
254 	   cmd->base.autoneg);
255 
256 	return 0;
257 }
258 
259 static int bnx2x_get_link_ksettings(struct net_device *dev,
260 				    struct ethtool_link_ksettings *cmd)
261 {
262 	struct bnx2x *bp = netdev_priv(dev);
263 	int cfg_idx = bnx2x_get_link_cfg_idx(bp);
264 	u32 media_type;
265 	u32 supported, advertising, lp_advertising;
266 
267 	ethtool_convert_link_mode_to_legacy_u32(&lp_advertising,
268 						cmd->link_modes.lp_advertising);
269 
270 	/* Dual Media boards present all available port types */
271 	supported = bp->port.supported[cfg_idx] |
272 		(bp->port.supported[cfg_idx ^ 1] &
273 		 (SUPPORTED_TP | SUPPORTED_FIBRE));
274 	advertising = bp->port.advertising[cfg_idx];
275 	media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
276 	if (media_type == ETH_PHY_SFP_1G_FIBER) {
277 		supported &= ~(SUPPORTED_10000baseT_Full);
278 		advertising &= ~(ADVERTISED_10000baseT_Full);
279 	}
280 
281 	if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
282 	    !(bp->flags & MF_FUNC_DIS)) {
283 		cmd->base.duplex = bp->link_vars.duplex;
284 
285 		if (IS_MF(bp) && !BP_NOMCP(bp))
286 			cmd->base.speed = bnx2x_get_mf_speed(bp);
287 		else
288 			cmd->base.speed = bp->link_vars.line_speed;
289 	} else {
290 		cmd->base.duplex = DUPLEX_UNKNOWN;
291 		cmd->base.speed = SPEED_UNKNOWN;
292 	}
293 
294 	cmd->base.port = bnx2x_get_port_type(bp);
295 
296 	cmd->base.phy_address = bp->mdio.prtad;
297 
298 	if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
299 		cmd->base.autoneg = AUTONEG_ENABLE;
300 	else
301 		cmd->base.autoneg = AUTONEG_DISABLE;
302 
303 	/* Publish LP advertised speeds and FC */
304 	if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
305 		u32 status = bp->link_vars.link_status;
306 
307 		lp_advertising |= ADVERTISED_Autoneg;
308 		if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
309 			lp_advertising |= ADVERTISED_Pause;
310 		if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
311 			lp_advertising |= ADVERTISED_Asym_Pause;
312 
313 		if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
314 			lp_advertising |= ADVERTISED_10baseT_Half;
315 		if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
316 			lp_advertising |= ADVERTISED_10baseT_Full;
317 		if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
318 			lp_advertising |= ADVERTISED_100baseT_Half;
319 		if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
320 			lp_advertising |= ADVERTISED_100baseT_Full;
321 		if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
322 			lp_advertising |= ADVERTISED_1000baseT_Half;
323 		if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
324 			if (media_type == ETH_PHY_KR) {
325 				lp_advertising |=
326 					ADVERTISED_1000baseKX_Full;
327 			} else {
328 				lp_advertising |=
329 					ADVERTISED_1000baseT_Full;
330 			}
331 		}
332 		if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
333 			lp_advertising |= ADVERTISED_2500baseX_Full;
334 		if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
335 			if (media_type == ETH_PHY_KR) {
336 				lp_advertising |=
337 					ADVERTISED_10000baseKR_Full;
338 			} else {
339 				lp_advertising |=
340 					ADVERTISED_10000baseT_Full;
341 			}
342 		}
343 		if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
344 			lp_advertising |= ADVERTISED_20000baseKR2_Full;
345 	}
346 
347 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
348 						supported);
349 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
350 						advertising);
351 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
352 						lp_advertising);
353 
354 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
355 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
356 	   "  duplex %d  port %d  phy_address %d\n"
357 	   "  autoneg %d\n",
358 	   cmd->base.cmd, supported, advertising,
359 	   cmd->base.speed,
360 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
361 	   cmd->base.autoneg);
362 
363 	return 0;
364 }
365 
366 static int bnx2x_set_link_ksettings(struct net_device *dev,
367 				    const struct ethtool_link_ksettings *cmd)
368 {
369 	struct bnx2x *bp = netdev_priv(dev);
370 	u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
371 	u32 speed, phy_idx;
372 	u32 supported;
373 	u8 duplex = cmd->base.duplex;
374 
375 	ethtool_convert_link_mode_to_legacy_u32(&supported,
376 						cmd->link_modes.supported);
377 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
378 						cmd->link_modes.advertising);
379 
380 	if (IS_MF_SD(bp))
381 		return 0;
382 
383 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
384 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
385 	   "  duplex %d  port %d  phy_address %d\n"
386 	   "  autoneg %d\n",
387 	   cmd->base.cmd, supported, advertising,
388 	   cmd->base.speed,
389 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
390 	   cmd->base.autoneg);
391 
392 	speed = cmd->base.speed;
393 
394 	/* If received a request for an unknown duplex, assume full*/
395 	if (duplex == DUPLEX_UNKNOWN)
396 		duplex = DUPLEX_FULL;
397 
398 	if (IS_MF_SI(bp)) {
399 		u32 part;
400 		u32 line_speed = bp->link_vars.line_speed;
401 
402 		/* use 10G if no link detected */
403 		if (!line_speed)
404 			line_speed = 10000;
405 
406 		if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
407 			DP(BNX2X_MSG_ETHTOOL,
408 			   "To set speed BC %X or higher is required, please upgrade BC\n",
409 			   REQ_BC_VER_4_SET_MF_BW);
410 			return -EINVAL;
411 		}
412 
413 		part = (speed * 100) / line_speed;
414 
415 		if (line_speed < speed || !part) {
416 			DP(BNX2X_MSG_ETHTOOL,
417 			   "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
418 			return -EINVAL;
419 		}
420 
421 		if (bp->state != BNX2X_STATE_OPEN)
422 			/* store value for following "load" */
423 			bp->pending_max = part;
424 		else
425 			bnx2x_update_max_mf_config(bp, part);
426 
427 		return 0;
428 	}
429 
430 	cfg_idx = bnx2x_get_link_cfg_idx(bp);
431 	old_multi_phy_config = bp->link_params.multi_phy_config;
432 	if (cmd->base.port != bnx2x_get_port_type(bp)) {
433 		switch (cmd->base.port) {
434 		case PORT_TP:
435 			if (!(bp->port.supported[0] & SUPPORTED_TP ||
436 			      bp->port.supported[1] & SUPPORTED_TP)) {
437 				DP(BNX2X_MSG_ETHTOOL,
438 				   "Unsupported port type\n");
439 				return -EINVAL;
440 			}
441 			bp->link_params.multi_phy_config &=
442 				~PORT_HW_CFG_PHY_SELECTION_MASK;
443 			if (bp->link_params.multi_phy_config &
444 			    PORT_HW_CFG_PHY_SWAPPED_ENABLED)
445 				bp->link_params.multi_phy_config |=
446 				PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
447 			else
448 				bp->link_params.multi_phy_config |=
449 				PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
450 			break;
451 		case PORT_FIBRE:
452 		case PORT_DA:
453 		case PORT_NONE:
454 			if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
455 			      bp->port.supported[1] & SUPPORTED_FIBRE)) {
456 				DP(BNX2X_MSG_ETHTOOL,
457 				   "Unsupported port type\n");
458 				return -EINVAL;
459 			}
460 			bp->link_params.multi_phy_config &=
461 				~PORT_HW_CFG_PHY_SELECTION_MASK;
462 			if (bp->link_params.multi_phy_config &
463 			    PORT_HW_CFG_PHY_SWAPPED_ENABLED)
464 				bp->link_params.multi_phy_config |=
465 				PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
466 			else
467 				bp->link_params.multi_phy_config |=
468 				PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
469 			break;
470 		default:
471 			DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
472 			return -EINVAL;
473 		}
474 	}
475 	/* Save new config in case command complete successfully */
476 	new_multi_phy_config = bp->link_params.multi_phy_config;
477 	/* Get the new cfg_idx */
478 	cfg_idx = bnx2x_get_link_cfg_idx(bp);
479 	/* Restore old config in case command failed */
480 	bp->link_params.multi_phy_config = old_multi_phy_config;
481 	DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
482 
483 	if (cmd->base.autoneg == AUTONEG_ENABLE) {
484 		u32 an_supported_speed = bp->port.supported[cfg_idx];
485 		if (bp->link_params.phy[EXT_PHY1].type ==
486 		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
487 			an_supported_speed |= (SUPPORTED_100baseT_Half |
488 					       SUPPORTED_100baseT_Full);
489 		if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
490 			DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
491 			return -EINVAL;
492 		}
493 
494 		/* advertise the requested speed and duplex if supported */
495 		if (advertising & ~an_supported_speed) {
496 			DP(BNX2X_MSG_ETHTOOL,
497 			   "Advertisement parameters are not supported\n");
498 			return -EINVAL;
499 		}
500 
501 		bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
502 		bp->link_params.req_duplex[cfg_idx] = duplex;
503 		bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
504 					 advertising);
505 		if (advertising) {
506 
507 			bp->link_params.speed_cap_mask[cfg_idx] = 0;
508 			if (advertising & ADVERTISED_10baseT_Half) {
509 				bp->link_params.speed_cap_mask[cfg_idx] |=
510 				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
511 			}
512 			if (advertising & ADVERTISED_10baseT_Full)
513 				bp->link_params.speed_cap_mask[cfg_idx] |=
514 				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
515 
516 			if (advertising & ADVERTISED_100baseT_Full)
517 				bp->link_params.speed_cap_mask[cfg_idx] |=
518 				PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
519 
520 			if (advertising & ADVERTISED_100baseT_Half) {
521 				bp->link_params.speed_cap_mask[cfg_idx] |=
522 				     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
523 			}
524 			if (advertising & ADVERTISED_1000baseT_Half) {
525 				bp->link_params.speed_cap_mask[cfg_idx] |=
526 					PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
527 			}
528 			if (advertising & (ADVERTISED_1000baseT_Full |
529 						ADVERTISED_1000baseKX_Full))
530 				bp->link_params.speed_cap_mask[cfg_idx] |=
531 					PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
532 
533 			if (advertising & (ADVERTISED_10000baseT_Full |
534 						ADVERTISED_10000baseKX4_Full |
535 						ADVERTISED_10000baseKR_Full))
536 				bp->link_params.speed_cap_mask[cfg_idx] |=
537 					PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
538 
539 			if (advertising & ADVERTISED_20000baseKR2_Full)
540 				bp->link_params.speed_cap_mask[cfg_idx] |=
541 					PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
542 		}
543 	} else { /* forced speed */
544 		/* advertise the requested speed and duplex if supported */
545 		switch (speed) {
546 		case SPEED_10:
547 			if (duplex == DUPLEX_FULL) {
548 				if (!(bp->port.supported[cfg_idx] &
549 				      SUPPORTED_10baseT_Full)) {
550 					DP(BNX2X_MSG_ETHTOOL,
551 					   "10M full not supported\n");
552 					return -EINVAL;
553 				}
554 
555 				advertising = (ADVERTISED_10baseT_Full |
556 					       ADVERTISED_TP);
557 			} else {
558 				if (!(bp->port.supported[cfg_idx] &
559 				      SUPPORTED_10baseT_Half)) {
560 					DP(BNX2X_MSG_ETHTOOL,
561 					   "10M half not supported\n");
562 					return -EINVAL;
563 				}
564 
565 				advertising = (ADVERTISED_10baseT_Half |
566 					       ADVERTISED_TP);
567 			}
568 			break;
569 
570 		case SPEED_100:
571 			if (duplex == DUPLEX_FULL) {
572 				if (!(bp->port.supported[cfg_idx] &
573 						SUPPORTED_100baseT_Full)) {
574 					DP(BNX2X_MSG_ETHTOOL,
575 					   "100M full not supported\n");
576 					return -EINVAL;
577 				}
578 
579 				advertising = (ADVERTISED_100baseT_Full |
580 					       ADVERTISED_TP);
581 			} else {
582 				if (!(bp->port.supported[cfg_idx] &
583 						SUPPORTED_100baseT_Half)) {
584 					DP(BNX2X_MSG_ETHTOOL,
585 					   "100M half not supported\n");
586 					return -EINVAL;
587 				}
588 
589 				advertising = (ADVERTISED_100baseT_Half |
590 					       ADVERTISED_TP);
591 			}
592 			break;
593 
594 		case SPEED_1000:
595 			if (duplex != DUPLEX_FULL) {
596 				DP(BNX2X_MSG_ETHTOOL,
597 				   "1G half not supported\n");
598 				return -EINVAL;
599 			}
600 
601 			if (bp->port.supported[cfg_idx] &
602 			     SUPPORTED_1000baseT_Full) {
603 				advertising = (ADVERTISED_1000baseT_Full |
604 					       ADVERTISED_TP);
605 
606 			} else if (bp->port.supported[cfg_idx] &
607 				   SUPPORTED_1000baseKX_Full) {
608 				advertising = ADVERTISED_1000baseKX_Full;
609 			} else {
610 				DP(BNX2X_MSG_ETHTOOL,
611 				   "1G full not supported\n");
612 				return -EINVAL;
613 			}
614 
615 			break;
616 
617 		case SPEED_2500:
618 			if (duplex != DUPLEX_FULL) {
619 				DP(BNX2X_MSG_ETHTOOL,
620 				   "2.5G half not supported\n");
621 				return -EINVAL;
622 			}
623 
624 			if (!(bp->port.supported[cfg_idx]
625 			      & SUPPORTED_2500baseX_Full)) {
626 				DP(BNX2X_MSG_ETHTOOL,
627 				   "2.5G full not supported\n");
628 				return -EINVAL;
629 			}
630 
631 			advertising = (ADVERTISED_2500baseX_Full |
632 				       ADVERTISED_TP);
633 			break;
634 
635 		case SPEED_10000:
636 			if (duplex != DUPLEX_FULL) {
637 				DP(BNX2X_MSG_ETHTOOL,
638 				   "10G half not supported\n");
639 				return -EINVAL;
640 			}
641 			phy_idx = bnx2x_get_cur_phy_idx(bp);
642 			if ((bp->port.supported[cfg_idx] &
643 			     SUPPORTED_10000baseT_Full) &&
644 			    (bp->link_params.phy[phy_idx].media_type !=
645 			     ETH_PHY_SFP_1G_FIBER)) {
646 				advertising = (ADVERTISED_10000baseT_Full |
647 					       ADVERTISED_FIBRE);
648 			} else if (bp->port.supported[cfg_idx] &
649 			       SUPPORTED_10000baseKR_Full) {
650 				advertising = (ADVERTISED_10000baseKR_Full |
651 					       ADVERTISED_FIBRE);
652 			} else {
653 				DP(BNX2X_MSG_ETHTOOL,
654 				   "10G full not supported\n");
655 				return -EINVAL;
656 			}
657 
658 			break;
659 
660 		default:
661 			DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
662 			return -EINVAL;
663 		}
664 
665 		bp->link_params.req_line_speed[cfg_idx] = speed;
666 		bp->link_params.req_duplex[cfg_idx] = duplex;
667 		bp->port.advertising[cfg_idx] = advertising;
668 	}
669 
670 	DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
671 	   "  req_duplex %d  advertising 0x%x\n",
672 	   bp->link_params.req_line_speed[cfg_idx],
673 	   bp->link_params.req_duplex[cfg_idx],
674 	   bp->port.advertising[cfg_idx]);
675 
676 	/* Set new config */
677 	bp->link_params.multi_phy_config = new_multi_phy_config;
678 	if (netif_running(dev)) {
679 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
680 		bnx2x_force_link_reset(bp);
681 		bnx2x_link_set(bp);
682 	}
683 
684 	return 0;
685 }
686 
687 #define DUMP_ALL_PRESETS		0x1FFF
688 #define DUMP_MAX_PRESETS		13
689 
690 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
691 {
692 	if (CHIP_IS_E1(bp))
693 		return dump_num_registers[0][preset-1];
694 	else if (CHIP_IS_E1H(bp))
695 		return dump_num_registers[1][preset-1];
696 	else if (CHIP_IS_E2(bp))
697 		return dump_num_registers[2][preset-1];
698 	else if (CHIP_IS_E3A0(bp))
699 		return dump_num_registers[3][preset-1];
700 	else if (CHIP_IS_E3B0(bp))
701 		return dump_num_registers[4][preset-1];
702 	else
703 		return 0;
704 }
705 
706 static int __bnx2x_get_regs_len(struct bnx2x *bp)
707 {
708 	u32 preset_idx;
709 	int regdump_len = 0;
710 
711 	/* Calculate the total preset regs length */
712 	for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
713 		regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
714 
715 	return regdump_len;
716 }
717 
718 static int bnx2x_get_regs_len(struct net_device *dev)
719 {
720 	struct bnx2x *bp = netdev_priv(dev);
721 	int regdump_len = 0;
722 
723 	if (IS_VF(bp))
724 		return 0;
725 
726 	regdump_len = __bnx2x_get_regs_len(bp);
727 	regdump_len *= 4;
728 	regdump_len += sizeof(struct dump_header);
729 
730 	return regdump_len;
731 }
732 
733 #define IS_E1_REG(chips)	((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
734 #define IS_E1H_REG(chips)	((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
735 #define IS_E2_REG(chips)	((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
736 #define IS_E3A0_REG(chips)	((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
737 #define IS_E3B0_REG(chips)	((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
738 
739 #define IS_REG_IN_PRESET(presets, idx)  \
740 		((presets & (1 << (idx-1))) == (1 << (idx-1)))
741 
742 /******* Paged registers info selectors ********/
743 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
744 {
745 	if (CHIP_IS_E2(bp))
746 		return page_vals_e2;
747 	else if (CHIP_IS_E3(bp))
748 		return page_vals_e3;
749 	else
750 		return NULL;
751 }
752 
753 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
754 {
755 	if (CHIP_IS_E2(bp))
756 		return PAGE_MODE_VALUES_E2;
757 	else if (CHIP_IS_E3(bp))
758 		return PAGE_MODE_VALUES_E3;
759 	else
760 		return 0;
761 }
762 
763 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
764 {
765 	if (CHIP_IS_E2(bp))
766 		return page_write_regs_e2;
767 	else if (CHIP_IS_E3(bp))
768 		return page_write_regs_e3;
769 	else
770 		return NULL;
771 }
772 
773 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
774 {
775 	if (CHIP_IS_E2(bp))
776 		return PAGE_WRITE_REGS_E2;
777 	else if (CHIP_IS_E3(bp))
778 		return PAGE_WRITE_REGS_E3;
779 	else
780 		return 0;
781 }
782 
783 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
784 {
785 	if (CHIP_IS_E2(bp))
786 		return page_read_regs_e2;
787 	else if (CHIP_IS_E3(bp))
788 		return page_read_regs_e3;
789 	else
790 		return NULL;
791 }
792 
793 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
794 {
795 	if (CHIP_IS_E2(bp))
796 		return PAGE_READ_REGS_E2;
797 	else if (CHIP_IS_E3(bp))
798 		return PAGE_READ_REGS_E3;
799 	else
800 		return 0;
801 }
802 
803 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
804 				       const struct reg_addr *reg_info)
805 {
806 	if (CHIP_IS_E1(bp))
807 		return IS_E1_REG(reg_info->chips);
808 	else if (CHIP_IS_E1H(bp))
809 		return IS_E1H_REG(reg_info->chips);
810 	else if (CHIP_IS_E2(bp))
811 		return IS_E2_REG(reg_info->chips);
812 	else if (CHIP_IS_E3A0(bp))
813 		return IS_E3A0_REG(reg_info->chips);
814 	else if (CHIP_IS_E3B0(bp))
815 		return IS_E3B0_REG(reg_info->chips);
816 	else
817 		return false;
818 }
819 
820 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
821 	const struct wreg_addr *wreg_info)
822 {
823 	if (CHIP_IS_E1(bp))
824 		return IS_E1_REG(wreg_info->chips);
825 	else if (CHIP_IS_E1H(bp))
826 		return IS_E1H_REG(wreg_info->chips);
827 	else if (CHIP_IS_E2(bp))
828 		return IS_E2_REG(wreg_info->chips);
829 	else if (CHIP_IS_E3A0(bp))
830 		return IS_E3A0_REG(wreg_info->chips);
831 	else if (CHIP_IS_E3B0(bp))
832 		return IS_E3B0_REG(wreg_info->chips);
833 	else
834 		return false;
835 }
836 
837 /**
838  * bnx2x_read_pages_regs - read "paged" registers
839  *
840  * @bp		device handle
841  * @p		output buffer
842  *
843  * Reads "paged" memories: memories that may only be read by first writing to a
844  * specific address ("write address") and then reading from a specific address
845  * ("read address"). There may be more than one write address per "page" and
846  * more than one read address per write address.
847  */
848 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
849 {
850 	u32 i, j, k, n;
851 
852 	/* addresses of the paged registers */
853 	const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
854 	/* number of paged registers */
855 	int num_pages = __bnx2x_get_page_reg_num(bp);
856 	/* write addresses */
857 	const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
858 	/* number of write addresses */
859 	int write_num = __bnx2x_get_page_write_num(bp);
860 	/* read addresses info */
861 	const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
862 	/* number of read addresses */
863 	int read_num = __bnx2x_get_page_read_num(bp);
864 	u32 addr, size;
865 
866 	for (i = 0; i < num_pages; i++) {
867 		for (j = 0; j < write_num; j++) {
868 			REG_WR(bp, write_addr[j], page_addr[i]);
869 
870 			for (k = 0; k < read_num; k++) {
871 				if (IS_REG_IN_PRESET(read_addr[k].presets,
872 						     preset)) {
873 					size = read_addr[k].size;
874 					for (n = 0; n < size; n++) {
875 						addr = read_addr[k].addr + n*4;
876 						*p++ = REG_RD(bp, addr);
877 					}
878 				}
879 			}
880 		}
881 	}
882 }
883 
884 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
885 {
886 	u32 i, j, addr;
887 	const struct wreg_addr *wreg_addr_p = NULL;
888 
889 	if (CHIP_IS_E1(bp))
890 		wreg_addr_p = &wreg_addr_e1;
891 	else if (CHIP_IS_E1H(bp))
892 		wreg_addr_p = &wreg_addr_e1h;
893 	else if (CHIP_IS_E2(bp))
894 		wreg_addr_p = &wreg_addr_e2;
895 	else if (CHIP_IS_E3A0(bp))
896 		wreg_addr_p = &wreg_addr_e3;
897 	else if (CHIP_IS_E3B0(bp))
898 		wreg_addr_p = &wreg_addr_e3b0;
899 
900 	/* Read the idle_chk registers */
901 	for (i = 0; i < IDLE_REGS_COUNT; i++) {
902 		if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
903 		    IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
904 			for (j = 0; j < idle_reg_addrs[i].size; j++)
905 				*p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
906 		}
907 	}
908 
909 	/* Read the regular registers */
910 	for (i = 0; i < REGS_COUNT; i++) {
911 		if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
912 		    IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
913 			for (j = 0; j < reg_addrs[i].size; j++)
914 				*p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
915 		}
916 	}
917 
918 	/* Read the CAM registers */
919 	if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
920 	    IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
921 		for (i = 0; i < wreg_addr_p->size; i++) {
922 			*p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
923 
924 			/* In case of wreg_addr register, read additional
925 			   registers from read_regs array
926 			*/
927 			for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
928 				addr = *(wreg_addr_p->read_regs);
929 				*p++ = REG_RD(bp, addr + j*4);
930 			}
931 		}
932 	}
933 
934 	/* Paged registers are supported in E2 & E3 only */
935 	if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
936 		/* Read "paged" registers */
937 		bnx2x_read_pages_regs(bp, p, preset);
938 	}
939 
940 	return 0;
941 }
942 
943 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
944 {
945 	u32 preset_idx;
946 
947 	/* Read all registers, by reading all preset registers */
948 	for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
949 		/* Skip presets with IOR */
950 		if ((preset_idx == 2) ||
951 		    (preset_idx == 5) ||
952 		    (preset_idx == 8) ||
953 		    (preset_idx == 11))
954 			continue;
955 		__bnx2x_get_preset_regs(bp, p, preset_idx);
956 		p += __bnx2x_get_preset_regs_len(bp, preset_idx);
957 	}
958 }
959 
960 static void bnx2x_get_regs(struct net_device *dev,
961 			   struct ethtool_regs *regs, void *_p)
962 {
963 	u32 *p = _p;
964 	struct bnx2x *bp = netdev_priv(dev);
965 	struct dump_header dump_hdr = {0};
966 
967 	regs->version = 2;
968 	memset(p, 0, regs->len);
969 
970 	if (!netif_running(bp->dev))
971 		return;
972 
973 	/* Disable parity attentions as long as following dump may
974 	 * cause false alarms by reading never written registers. We
975 	 * will re-enable parity attentions right after the dump.
976 	 */
977 
978 	bnx2x_disable_blocks_parity(bp);
979 
980 	dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
981 	dump_hdr.preset = DUMP_ALL_PRESETS;
982 	dump_hdr.version = BNX2X_DUMP_VERSION;
983 
984 	/* dump_meta_data presents OR of CHIP and PATH. */
985 	if (CHIP_IS_E1(bp)) {
986 		dump_hdr.dump_meta_data = DUMP_CHIP_E1;
987 	} else if (CHIP_IS_E1H(bp)) {
988 		dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
989 	} else if (CHIP_IS_E2(bp)) {
990 		dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
991 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
992 	} else if (CHIP_IS_E3A0(bp)) {
993 		dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
994 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
995 	} else if (CHIP_IS_E3B0(bp)) {
996 		dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
997 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
998 	}
999 
1000 	memcpy(p, &dump_hdr, sizeof(struct dump_header));
1001 	p += dump_hdr.header_size + 1;
1002 
1003 	/* This isn't really an error, but since attention handling is going
1004 	 * to print the GRC timeouts using this macro, we use the same.
1005 	 */
1006 	BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
1007 
1008 	/* Actually read the registers */
1009 	__bnx2x_get_regs(bp, p);
1010 
1011 	/* Re-enable parity attentions */
1012 	bnx2x_clear_blocks_parity(bp);
1013 	bnx2x_enable_blocks_parity(bp);
1014 }
1015 
1016 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
1017 {
1018 	struct bnx2x *bp = netdev_priv(dev);
1019 	int regdump_len = 0;
1020 
1021 	regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1022 	regdump_len *= 4;
1023 	regdump_len += sizeof(struct dump_header);
1024 
1025 	return regdump_len;
1026 }
1027 
1028 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1029 {
1030 	struct bnx2x *bp = netdev_priv(dev);
1031 
1032 	/* Use the ethtool_dump "flag" field as the dump preset index */
1033 	if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1034 		return -EINVAL;
1035 
1036 	bp->dump_preset_idx = val->flag;
1037 	return 0;
1038 }
1039 
1040 static int bnx2x_get_dump_flag(struct net_device *dev,
1041 			       struct ethtool_dump *dump)
1042 {
1043 	struct bnx2x *bp = netdev_priv(dev);
1044 
1045 	dump->version = BNX2X_DUMP_VERSION;
1046 	dump->flag = bp->dump_preset_idx;
1047 	/* Calculate the requested preset idx length */
1048 	dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1049 	DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1050 	   bp->dump_preset_idx, dump->len);
1051 	return 0;
1052 }
1053 
1054 static int bnx2x_get_dump_data(struct net_device *dev,
1055 			       struct ethtool_dump *dump,
1056 			       void *buffer)
1057 {
1058 	u32 *p = buffer;
1059 	struct bnx2x *bp = netdev_priv(dev);
1060 	struct dump_header dump_hdr = {0};
1061 
1062 	/* Disable parity attentions as long as following dump may
1063 	 * cause false alarms by reading never written registers. We
1064 	 * will re-enable parity attentions right after the dump.
1065 	 */
1066 
1067 	bnx2x_disable_blocks_parity(bp);
1068 
1069 	dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1070 	dump_hdr.preset = bp->dump_preset_idx;
1071 	dump_hdr.version = BNX2X_DUMP_VERSION;
1072 
1073 	DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1074 
1075 	/* dump_meta_data presents OR of CHIP and PATH. */
1076 	if (CHIP_IS_E1(bp)) {
1077 		dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1078 	} else if (CHIP_IS_E1H(bp)) {
1079 		dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1080 	} else if (CHIP_IS_E2(bp)) {
1081 		dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1082 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1083 	} else if (CHIP_IS_E3A0(bp)) {
1084 		dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1085 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1086 	} else if (CHIP_IS_E3B0(bp)) {
1087 		dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1088 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1089 	}
1090 
1091 	memcpy(p, &dump_hdr, sizeof(struct dump_header));
1092 	p += dump_hdr.header_size + 1;
1093 
1094 	/* Actually read the registers */
1095 	__bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1096 
1097 	/* Re-enable parity attentions */
1098 	bnx2x_clear_blocks_parity(bp);
1099 	bnx2x_enable_blocks_parity(bp);
1100 
1101 	return 0;
1102 }
1103 
1104 static void bnx2x_get_drvinfo(struct net_device *dev,
1105 			      struct ethtool_drvinfo *info)
1106 {
1107 	struct bnx2x *bp = netdev_priv(dev);
1108 
1109 	strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1110 	strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1111 
1112 	bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1113 
1114 	strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1115 }
1116 
1117 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1118 {
1119 	struct bnx2x *bp = netdev_priv(dev);
1120 
1121 	if (bp->flags & NO_WOL_FLAG) {
1122 		wol->supported = 0;
1123 		wol->wolopts = 0;
1124 	} else {
1125 		wol->supported = WAKE_MAGIC;
1126 		if (bp->wol)
1127 			wol->wolopts = WAKE_MAGIC;
1128 		else
1129 			wol->wolopts = 0;
1130 	}
1131 	memset(&wol->sopass, 0, sizeof(wol->sopass));
1132 }
1133 
1134 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1135 {
1136 	struct bnx2x *bp = netdev_priv(dev);
1137 
1138 	if (wol->wolopts & ~WAKE_MAGIC) {
1139 		DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1140 		return -EINVAL;
1141 	}
1142 
1143 	if (wol->wolopts & WAKE_MAGIC) {
1144 		if (bp->flags & NO_WOL_FLAG) {
1145 			DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1146 			return -EINVAL;
1147 		}
1148 		bp->wol = 1;
1149 	} else
1150 		bp->wol = 0;
1151 
1152 	if (SHMEM2_HAS(bp, curr_cfg))
1153 		SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1154 
1155 	return 0;
1156 }
1157 
1158 static u32 bnx2x_get_msglevel(struct net_device *dev)
1159 {
1160 	struct bnx2x *bp = netdev_priv(dev);
1161 
1162 	return bp->msg_enable;
1163 }
1164 
1165 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1166 {
1167 	struct bnx2x *bp = netdev_priv(dev);
1168 
1169 	if (capable(CAP_NET_ADMIN)) {
1170 		/* dump MCP trace */
1171 		if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1172 			bnx2x_fw_dump_lvl(bp, KERN_INFO);
1173 		bp->msg_enable = level;
1174 	}
1175 }
1176 
1177 static int bnx2x_nway_reset(struct net_device *dev)
1178 {
1179 	struct bnx2x *bp = netdev_priv(dev);
1180 
1181 	if (!bp->port.pmf)
1182 		return 0;
1183 
1184 	if (netif_running(dev)) {
1185 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1186 		bnx2x_force_link_reset(bp);
1187 		bnx2x_link_set(bp);
1188 	}
1189 
1190 	return 0;
1191 }
1192 
1193 static u32 bnx2x_get_link(struct net_device *dev)
1194 {
1195 	struct bnx2x *bp = netdev_priv(dev);
1196 
1197 	if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1198 		return 0;
1199 
1200 	if (IS_VF(bp))
1201 		return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1202 				 &bp->vf_link_vars.link_report_flags);
1203 
1204 	return bp->link_vars.link_up;
1205 }
1206 
1207 static int bnx2x_get_eeprom_len(struct net_device *dev)
1208 {
1209 	struct bnx2x *bp = netdev_priv(dev);
1210 
1211 	return bp->common.flash_size;
1212 }
1213 
1214 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1215  * had we done things the other way around, if two pfs from the same port would
1216  * attempt to access nvram at the same time, we could run into a scenario such
1217  * as:
1218  * pf A takes the port lock.
1219  * pf B succeeds in taking the same lock since they are from the same port.
1220  * pf A takes the per pf misc lock. Performs eeprom access.
1221  * pf A finishes. Unlocks the per pf misc lock.
1222  * Pf B takes the lock and proceeds to perform it's own access.
1223  * pf A unlocks the per port lock, while pf B is still working (!).
1224  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1225  * access corrupted by pf B)
1226  */
1227 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1228 {
1229 	int port = BP_PORT(bp);
1230 	int count, i;
1231 	u32 val;
1232 
1233 	/* acquire HW lock: protect against other PFs in PF Direct Assignment */
1234 	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1235 
1236 	/* adjust timeout for emulation/FPGA */
1237 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1238 	if (CHIP_REV_IS_SLOW(bp))
1239 		count *= 100;
1240 
1241 	/* request access to nvram interface */
1242 	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1243 	       (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1244 
1245 	for (i = 0; i < count*10; i++) {
1246 		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1247 		if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1248 			break;
1249 
1250 		udelay(5);
1251 	}
1252 
1253 	if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1254 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1255 		   "cannot get access to nvram interface\n");
1256 		bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1257 		return -EBUSY;
1258 	}
1259 
1260 	return 0;
1261 }
1262 
1263 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1264 {
1265 	int port = BP_PORT(bp);
1266 	int count, i;
1267 	u32 val;
1268 
1269 	/* adjust timeout for emulation/FPGA */
1270 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1271 	if (CHIP_REV_IS_SLOW(bp))
1272 		count *= 100;
1273 
1274 	/* relinquish nvram interface */
1275 	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1276 	       (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1277 
1278 	for (i = 0; i < count*10; i++) {
1279 		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1280 		if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1281 			break;
1282 
1283 		udelay(5);
1284 	}
1285 
1286 	if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1287 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1288 		   "cannot free access to nvram interface\n");
1289 		return -EBUSY;
1290 	}
1291 
1292 	/* release HW lock: protect against other PFs in PF Direct Assignment */
1293 	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1294 	return 0;
1295 }
1296 
1297 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1298 {
1299 	u32 val;
1300 
1301 	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1302 
1303 	/* enable both bits, even on read */
1304 	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1305 	       (val | MCPR_NVM_ACCESS_ENABLE_EN |
1306 		      MCPR_NVM_ACCESS_ENABLE_WR_EN));
1307 }
1308 
1309 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1310 {
1311 	u32 val;
1312 
1313 	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1314 
1315 	/* disable both bits, even after read */
1316 	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1317 	       (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1318 			MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1319 }
1320 
1321 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1322 				  u32 cmd_flags)
1323 {
1324 	int count, i, rc;
1325 	u32 val;
1326 
1327 	/* build the command word */
1328 	cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1329 
1330 	/* need to clear DONE bit separately */
1331 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1332 
1333 	/* address of the NVRAM to read from */
1334 	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1335 	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1336 
1337 	/* issue a read command */
1338 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1339 
1340 	/* adjust timeout for emulation/FPGA */
1341 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1342 	if (CHIP_REV_IS_SLOW(bp))
1343 		count *= 100;
1344 
1345 	/* wait for completion */
1346 	*ret_val = 0;
1347 	rc = -EBUSY;
1348 	for (i = 0; i < count; i++) {
1349 		udelay(5);
1350 		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1351 
1352 		if (val & MCPR_NVM_COMMAND_DONE) {
1353 			val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1354 			/* we read nvram data in cpu order
1355 			 * but ethtool sees it as an array of bytes
1356 			 * converting to big-endian will do the work
1357 			 */
1358 			*ret_val = cpu_to_be32(val);
1359 			rc = 0;
1360 			break;
1361 		}
1362 	}
1363 	if (rc == -EBUSY)
1364 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1365 		   "nvram read timeout expired\n");
1366 	return rc;
1367 }
1368 
1369 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1370 		     int buf_size)
1371 {
1372 	int rc;
1373 	u32 cmd_flags;
1374 	__be32 val;
1375 
1376 	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1377 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1378 		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1379 		   offset, buf_size);
1380 		return -EINVAL;
1381 	}
1382 
1383 	if (offset + buf_size > bp->common.flash_size) {
1384 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1385 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1386 		   offset, buf_size, bp->common.flash_size);
1387 		return -EINVAL;
1388 	}
1389 
1390 	/* request access to nvram interface */
1391 	rc = bnx2x_acquire_nvram_lock(bp);
1392 	if (rc)
1393 		return rc;
1394 
1395 	/* enable access to nvram interface */
1396 	bnx2x_enable_nvram_access(bp);
1397 
1398 	/* read the first word(s) */
1399 	cmd_flags = MCPR_NVM_COMMAND_FIRST;
1400 	while ((buf_size > sizeof(u32)) && (rc == 0)) {
1401 		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1402 		memcpy(ret_buf, &val, 4);
1403 
1404 		/* advance to the next dword */
1405 		offset += sizeof(u32);
1406 		ret_buf += sizeof(u32);
1407 		buf_size -= sizeof(u32);
1408 		cmd_flags = 0;
1409 	}
1410 
1411 	if (rc == 0) {
1412 		cmd_flags |= MCPR_NVM_COMMAND_LAST;
1413 		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1414 		memcpy(ret_buf, &val, 4);
1415 	}
1416 
1417 	/* disable access to nvram interface */
1418 	bnx2x_disable_nvram_access(bp);
1419 	bnx2x_release_nvram_lock(bp);
1420 
1421 	return rc;
1422 }
1423 
1424 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1425 			      int buf_size)
1426 {
1427 	int rc;
1428 
1429 	rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1430 
1431 	if (!rc) {
1432 		__be32 *be = (__be32 *)buf;
1433 
1434 		while ((buf_size -= 4) >= 0)
1435 			*buf++ = be32_to_cpu(*be++);
1436 	}
1437 
1438 	return rc;
1439 }
1440 
1441 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1442 {
1443 	int rc = 1;
1444 	u16 pm = 0;
1445 	struct net_device *dev = pci_get_drvdata(bp->pdev);
1446 
1447 	if (bp->pdev->pm_cap)
1448 		rc = pci_read_config_word(bp->pdev,
1449 					  bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1450 
1451 	if ((rc && !netif_running(dev)) ||
1452 	    (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1453 		return false;
1454 
1455 	return true;
1456 }
1457 
1458 static int bnx2x_get_eeprom(struct net_device *dev,
1459 			    struct ethtool_eeprom *eeprom, u8 *eebuf)
1460 {
1461 	struct bnx2x *bp = netdev_priv(dev);
1462 
1463 	if (!bnx2x_is_nvm_accessible(bp)) {
1464 		DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1465 		   "cannot access eeprom when the interface is down\n");
1466 		return -EAGAIN;
1467 	}
1468 
1469 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1470 	   "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1471 	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1472 	   eeprom->len, eeprom->len);
1473 
1474 	/* parameters already validated in ethtool_get_eeprom */
1475 
1476 	return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1477 }
1478 
1479 static int bnx2x_get_module_eeprom(struct net_device *dev,
1480 				   struct ethtool_eeprom *ee,
1481 				   u8 *data)
1482 {
1483 	struct bnx2x *bp = netdev_priv(dev);
1484 	int rc = -EINVAL, phy_idx;
1485 	u8 *user_data = data;
1486 	unsigned int start_addr = ee->offset, xfer_size = 0;
1487 
1488 	if (!bnx2x_is_nvm_accessible(bp)) {
1489 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1490 		   "cannot access eeprom when the interface is down\n");
1491 		return -EAGAIN;
1492 	}
1493 
1494 	phy_idx = bnx2x_get_cur_phy_idx(bp);
1495 
1496 	/* Read A0 section */
1497 	if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1498 		/* Limit transfer size to the A0 section boundary */
1499 		if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1500 			xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1501 		else
1502 			xfer_size = ee->len;
1503 		bnx2x_acquire_phy_lock(bp);
1504 		rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1505 						  &bp->link_params,
1506 						  I2C_DEV_ADDR_A0,
1507 						  start_addr,
1508 						  xfer_size,
1509 						  user_data);
1510 		bnx2x_release_phy_lock(bp);
1511 		if (rc) {
1512 			DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1513 
1514 			return -EINVAL;
1515 		}
1516 		user_data += xfer_size;
1517 		start_addr += xfer_size;
1518 	}
1519 
1520 	/* Read A2 section */
1521 	if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1522 	    (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1523 		xfer_size = ee->len - xfer_size;
1524 		/* Limit transfer size to the A2 section boundary */
1525 		if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1526 			xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1527 		start_addr -= ETH_MODULE_SFF_8079_LEN;
1528 		bnx2x_acquire_phy_lock(bp);
1529 		rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1530 						  &bp->link_params,
1531 						  I2C_DEV_ADDR_A2,
1532 						  start_addr,
1533 						  xfer_size,
1534 						  user_data);
1535 		bnx2x_release_phy_lock(bp);
1536 		if (rc) {
1537 			DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1538 			return -EINVAL;
1539 		}
1540 	}
1541 	return rc;
1542 }
1543 
1544 static int bnx2x_get_module_info(struct net_device *dev,
1545 				 struct ethtool_modinfo *modinfo)
1546 {
1547 	struct bnx2x *bp = netdev_priv(dev);
1548 	int phy_idx, rc;
1549 	u8 sff8472_comp, diag_type;
1550 
1551 	if (!bnx2x_is_nvm_accessible(bp)) {
1552 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1553 		   "cannot access eeprom when the interface is down\n");
1554 		return -EAGAIN;
1555 	}
1556 	phy_idx = bnx2x_get_cur_phy_idx(bp);
1557 	bnx2x_acquire_phy_lock(bp);
1558 	rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1559 					  &bp->link_params,
1560 					  I2C_DEV_ADDR_A0,
1561 					  SFP_EEPROM_SFF_8472_COMP_ADDR,
1562 					  SFP_EEPROM_SFF_8472_COMP_SIZE,
1563 					  &sff8472_comp);
1564 	bnx2x_release_phy_lock(bp);
1565 	if (rc) {
1566 		DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1567 		return -EINVAL;
1568 	}
1569 
1570 	bnx2x_acquire_phy_lock(bp);
1571 	rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1572 					  &bp->link_params,
1573 					  I2C_DEV_ADDR_A0,
1574 					  SFP_EEPROM_DIAG_TYPE_ADDR,
1575 					  SFP_EEPROM_DIAG_TYPE_SIZE,
1576 					  &diag_type);
1577 	bnx2x_release_phy_lock(bp);
1578 	if (rc) {
1579 		DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1580 		return -EINVAL;
1581 	}
1582 
1583 	if (!sff8472_comp ||
1584 	    (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1585 		modinfo->type = ETH_MODULE_SFF_8079;
1586 		modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1587 	} else {
1588 		modinfo->type = ETH_MODULE_SFF_8472;
1589 		modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1590 	}
1591 	return 0;
1592 }
1593 
1594 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1595 				   u32 cmd_flags)
1596 {
1597 	int count, i, rc;
1598 
1599 	/* build the command word */
1600 	cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1601 
1602 	/* need to clear DONE bit separately */
1603 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1604 
1605 	/* write the data */
1606 	REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1607 
1608 	/* address of the NVRAM to write to */
1609 	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1610 	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1611 
1612 	/* issue the write command */
1613 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1614 
1615 	/* adjust timeout for emulation/FPGA */
1616 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1617 	if (CHIP_REV_IS_SLOW(bp))
1618 		count *= 100;
1619 
1620 	/* wait for completion */
1621 	rc = -EBUSY;
1622 	for (i = 0; i < count; i++) {
1623 		udelay(5);
1624 		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1625 		if (val & MCPR_NVM_COMMAND_DONE) {
1626 			rc = 0;
1627 			break;
1628 		}
1629 	}
1630 
1631 	if (rc == -EBUSY)
1632 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1633 		   "nvram write timeout expired\n");
1634 	return rc;
1635 }
1636 
1637 #define BYTE_OFFSET(offset)		(8 * (offset & 0x03))
1638 
1639 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1640 			      int buf_size)
1641 {
1642 	int rc;
1643 	u32 cmd_flags, align_offset, val;
1644 	__be32 val_be;
1645 
1646 	if (offset + buf_size > bp->common.flash_size) {
1647 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1648 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1649 		   offset, buf_size, bp->common.flash_size);
1650 		return -EINVAL;
1651 	}
1652 
1653 	/* request access to nvram interface */
1654 	rc = bnx2x_acquire_nvram_lock(bp);
1655 	if (rc)
1656 		return rc;
1657 
1658 	/* enable access to nvram interface */
1659 	bnx2x_enable_nvram_access(bp);
1660 
1661 	cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1662 	align_offset = (offset & ~0x03);
1663 	rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1664 
1665 	if (rc == 0) {
1666 		/* nvram data is returned as an array of bytes
1667 		 * convert it back to cpu order
1668 		 */
1669 		val = be32_to_cpu(val_be);
1670 
1671 		val &= ~le32_to_cpu((__force __le32)
1672 				    (0xff << BYTE_OFFSET(offset)));
1673 		val |= le32_to_cpu((__force __le32)
1674 				   (*data_buf << BYTE_OFFSET(offset)));
1675 
1676 		rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1677 					     cmd_flags);
1678 	}
1679 
1680 	/* disable access to nvram interface */
1681 	bnx2x_disable_nvram_access(bp);
1682 	bnx2x_release_nvram_lock(bp);
1683 
1684 	return rc;
1685 }
1686 
1687 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1688 			     int buf_size)
1689 {
1690 	int rc;
1691 	u32 cmd_flags;
1692 	u32 val;
1693 	u32 written_so_far;
1694 
1695 	if (buf_size == 1)	/* ethtool */
1696 		return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1697 
1698 	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1699 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1700 		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1701 		   offset, buf_size);
1702 		return -EINVAL;
1703 	}
1704 
1705 	if (offset + buf_size > bp->common.flash_size) {
1706 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1707 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1708 		   offset, buf_size, bp->common.flash_size);
1709 		return -EINVAL;
1710 	}
1711 
1712 	/* request access to nvram interface */
1713 	rc = bnx2x_acquire_nvram_lock(bp);
1714 	if (rc)
1715 		return rc;
1716 
1717 	/* enable access to nvram interface */
1718 	bnx2x_enable_nvram_access(bp);
1719 
1720 	written_so_far = 0;
1721 	cmd_flags = MCPR_NVM_COMMAND_FIRST;
1722 	while ((written_so_far < buf_size) && (rc == 0)) {
1723 		if (written_so_far == (buf_size - sizeof(u32)))
1724 			cmd_flags |= MCPR_NVM_COMMAND_LAST;
1725 		else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1726 			cmd_flags |= MCPR_NVM_COMMAND_LAST;
1727 		else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1728 			cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1729 
1730 		memcpy(&val, data_buf, 4);
1731 
1732 		/* Notice unlike bnx2x_nvram_read_dword() this will not
1733 		 * change val using be32_to_cpu(), which causes data to flip
1734 		 * if the eeprom is read and then written back. This is due
1735 		 * to tools utilizing this functionality that would break
1736 		 * if this would be resolved.
1737 		 */
1738 		rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1739 
1740 		/* advance to the next dword */
1741 		offset += sizeof(u32);
1742 		data_buf += sizeof(u32);
1743 		written_so_far += sizeof(u32);
1744 
1745 		/* At end of each 4Kb page, release nvram lock to allow MFW
1746 		 * chance to take it for its own use.
1747 		 */
1748 		if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1749 		    (written_so_far < buf_size)) {
1750 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1751 			   "Releasing NVM lock after offset 0x%x\n",
1752 			   (u32)(offset - sizeof(u32)));
1753 			bnx2x_release_nvram_lock(bp);
1754 			usleep_range(1000, 2000);
1755 			rc = bnx2x_acquire_nvram_lock(bp);
1756 			if (rc)
1757 				return rc;
1758 		}
1759 
1760 		cmd_flags = 0;
1761 	}
1762 
1763 	/* disable access to nvram interface */
1764 	bnx2x_disable_nvram_access(bp);
1765 	bnx2x_release_nvram_lock(bp);
1766 
1767 	return rc;
1768 }
1769 
1770 static int bnx2x_set_eeprom(struct net_device *dev,
1771 			    struct ethtool_eeprom *eeprom, u8 *eebuf)
1772 {
1773 	struct bnx2x *bp = netdev_priv(dev);
1774 	int port = BP_PORT(bp);
1775 	int rc = 0;
1776 	u32 ext_phy_config;
1777 
1778 	if (!bnx2x_is_nvm_accessible(bp)) {
1779 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1780 		   "cannot access eeprom when the interface is down\n");
1781 		return -EAGAIN;
1782 	}
1783 
1784 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1785 	   "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1786 	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1787 	   eeprom->len, eeprom->len);
1788 
1789 	/* parameters already validated in ethtool_set_eeprom */
1790 
1791 	/* PHY eeprom can be accessed only by the PMF */
1792 	if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1793 	    !bp->port.pmf) {
1794 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1795 		   "wrong magic or interface is not pmf\n");
1796 		return -EINVAL;
1797 	}
1798 
1799 	ext_phy_config =
1800 		SHMEM_RD(bp,
1801 			 dev_info.port_hw_config[port].external_phy_config);
1802 
1803 	if (eeprom->magic == 0x50485950) {
1804 		/* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1805 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1806 
1807 		bnx2x_acquire_phy_lock(bp);
1808 		rc |= bnx2x_link_reset(&bp->link_params,
1809 				       &bp->link_vars, 0);
1810 		if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1811 					PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1812 			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1813 				       MISC_REGISTERS_GPIO_HIGH, port);
1814 		bnx2x_release_phy_lock(bp);
1815 		bnx2x_link_report(bp);
1816 
1817 	} else if (eeprom->magic == 0x50485952) {
1818 		/* 'PHYR' (0x50485952): re-init link after FW upgrade */
1819 		if (bp->state == BNX2X_STATE_OPEN) {
1820 			bnx2x_acquire_phy_lock(bp);
1821 			rc |= bnx2x_link_reset(&bp->link_params,
1822 					       &bp->link_vars, 1);
1823 
1824 			rc |= bnx2x_phy_init(&bp->link_params,
1825 					     &bp->link_vars);
1826 			bnx2x_release_phy_lock(bp);
1827 			bnx2x_calc_fc_adv(bp);
1828 		}
1829 	} else if (eeprom->magic == 0x53985943) {
1830 		/* 'PHYC' (0x53985943): PHY FW upgrade completed */
1831 		if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1832 				       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1833 
1834 			/* DSP Remove Download Mode */
1835 			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1836 				       MISC_REGISTERS_GPIO_LOW, port);
1837 
1838 			bnx2x_acquire_phy_lock(bp);
1839 
1840 			bnx2x_sfx7101_sp_sw_reset(bp,
1841 						&bp->link_params.phy[EXT_PHY1]);
1842 
1843 			/* wait 0.5 sec to allow it to run */
1844 			msleep(500);
1845 			bnx2x_ext_phy_hw_reset(bp, port);
1846 			msleep(500);
1847 			bnx2x_release_phy_lock(bp);
1848 		}
1849 	} else
1850 		rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1851 
1852 	return rc;
1853 }
1854 
1855 static int bnx2x_get_coalesce(struct net_device *dev,
1856 			      struct ethtool_coalesce *coal)
1857 {
1858 	struct bnx2x *bp = netdev_priv(dev);
1859 
1860 	memset(coal, 0, sizeof(struct ethtool_coalesce));
1861 
1862 	coal->rx_coalesce_usecs = bp->rx_ticks;
1863 	coal->tx_coalesce_usecs = bp->tx_ticks;
1864 
1865 	return 0;
1866 }
1867 
1868 static int bnx2x_set_coalesce(struct net_device *dev,
1869 			      struct ethtool_coalesce *coal)
1870 {
1871 	struct bnx2x *bp = netdev_priv(dev);
1872 
1873 	bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1874 	if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1875 		bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1876 
1877 	bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1878 	if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1879 		bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1880 
1881 	if (netif_running(dev))
1882 		bnx2x_update_coalesce(bp);
1883 
1884 	return 0;
1885 }
1886 
1887 static void bnx2x_get_ringparam(struct net_device *dev,
1888 				struct ethtool_ringparam *ering)
1889 {
1890 	struct bnx2x *bp = netdev_priv(dev);
1891 
1892 	ering->rx_max_pending = MAX_RX_AVAIL;
1893 
1894 	/* If size isn't already set, we give an estimation of the number
1895 	 * of buffers we'll have. We're neglecting some possible conditions
1896 	 * [we couldn't know for certain at this point if number of queues
1897 	 * might shrink] but the number would be correct for the likely
1898 	 * scenario.
1899 	 */
1900 	if (bp->rx_ring_size)
1901 		ering->rx_pending = bp->rx_ring_size;
1902 	else if (BNX2X_NUM_RX_QUEUES(bp))
1903 		ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1904 	else
1905 		ering->rx_pending = MAX_RX_AVAIL;
1906 
1907 	ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1908 	ering->tx_pending = bp->tx_ring_size;
1909 }
1910 
1911 static int bnx2x_set_ringparam(struct net_device *dev,
1912 			       struct ethtool_ringparam *ering)
1913 {
1914 	struct bnx2x *bp = netdev_priv(dev);
1915 
1916 	DP(BNX2X_MSG_ETHTOOL,
1917 	   "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1918 	   ering->rx_pending, ering->tx_pending);
1919 
1920 	if (pci_num_vf(bp->pdev)) {
1921 		DP(BNX2X_MSG_IOV,
1922 		   "VFs are enabled, can not change ring parameters\n");
1923 		return -EPERM;
1924 	}
1925 
1926 	if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1927 		DP(BNX2X_MSG_ETHTOOL,
1928 		   "Handling parity error recovery. Try again later\n");
1929 		return -EAGAIN;
1930 	}
1931 
1932 	if ((ering->rx_pending > MAX_RX_AVAIL) ||
1933 	    (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1934 						    MIN_RX_SIZE_TPA)) ||
1935 	    (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1936 	    (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1937 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1938 		return -EINVAL;
1939 	}
1940 
1941 	bp->rx_ring_size = ering->rx_pending;
1942 	bp->tx_ring_size = ering->tx_pending;
1943 
1944 	return bnx2x_reload_if_running(dev);
1945 }
1946 
1947 static void bnx2x_get_pauseparam(struct net_device *dev,
1948 				 struct ethtool_pauseparam *epause)
1949 {
1950 	struct bnx2x *bp = netdev_priv(dev);
1951 	int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1952 	int cfg_reg;
1953 
1954 	epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1955 			   BNX2X_FLOW_CTRL_AUTO);
1956 
1957 	if (!epause->autoneg)
1958 		cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1959 	else
1960 		cfg_reg = bp->link_params.req_fc_auto_adv;
1961 
1962 	epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1963 			    BNX2X_FLOW_CTRL_RX);
1964 	epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1965 			    BNX2X_FLOW_CTRL_TX);
1966 
1967 	DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1968 	   "  autoneg %d  rx_pause %d  tx_pause %d\n",
1969 	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1970 }
1971 
1972 static int bnx2x_set_pauseparam(struct net_device *dev,
1973 				struct ethtool_pauseparam *epause)
1974 {
1975 	struct bnx2x *bp = netdev_priv(dev);
1976 	u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1977 	if (IS_MF(bp))
1978 		return 0;
1979 
1980 	DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1981 	   "  autoneg %d  rx_pause %d  tx_pause %d\n",
1982 	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1983 
1984 	bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1985 
1986 	if (epause->rx_pause)
1987 		bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1988 
1989 	if (epause->tx_pause)
1990 		bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1991 
1992 	if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1993 		bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1994 
1995 	if (epause->autoneg) {
1996 		if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1997 			DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1998 			return -EINVAL;
1999 		}
2000 
2001 		if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
2002 			bp->link_params.req_flow_ctrl[cfg_idx] =
2003 				BNX2X_FLOW_CTRL_AUTO;
2004 		}
2005 		bp->link_params.req_fc_auto_adv = 0;
2006 		if (epause->rx_pause)
2007 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
2008 
2009 		if (epause->tx_pause)
2010 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
2011 
2012 		if (!bp->link_params.req_fc_auto_adv)
2013 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
2014 	}
2015 
2016 	DP(BNX2X_MSG_ETHTOOL,
2017 	   "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
2018 
2019 	if (netif_running(dev)) {
2020 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2021 		bnx2x_force_link_reset(bp);
2022 		bnx2x_link_set(bp);
2023 	}
2024 
2025 	return 0;
2026 }
2027 
2028 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2029 	"register_test (offline)    ",
2030 	"memory_test (offline)      ",
2031 	"int_loopback_test (offline)",
2032 	"ext_loopback_test (offline)",
2033 	"nvram_test (online)        ",
2034 	"interrupt_test (online)    ",
2035 	"link_test (online)         "
2036 };
2037 
2038 enum {
2039 	BNX2X_PRI_FLAG_ISCSI,
2040 	BNX2X_PRI_FLAG_FCOE,
2041 	BNX2X_PRI_FLAG_STORAGE,
2042 	BNX2X_PRI_FLAG_LEN,
2043 };
2044 
2045 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2046 	"iSCSI offload support",
2047 	"FCoE offload support",
2048 	"Storage only interface"
2049 };
2050 
2051 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2052 {
2053 	u32 modes = 0;
2054 
2055 	if (eee_adv & SHMEM_EEE_100M_ADV)
2056 		modes |= ADVERTISED_100baseT_Full;
2057 	if (eee_adv & SHMEM_EEE_1G_ADV)
2058 		modes |= ADVERTISED_1000baseT_Full;
2059 	if (eee_adv & SHMEM_EEE_10G_ADV)
2060 		modes |= ADVERTISED_10000baseT_Full;
2061 
2062 	return modes;
2063 }
2064 
2065 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2066 {
2067 	u32 eee_adv = 0;
2068 	if (modes & ADVERTISED_100baseT_Full)
2069 		eee_adv |= SHMEM_EEE_100M_ADV;
2070 	if (modes & ADVERTISED_1000baseT_Full)
2071 		eee_adv |= SHMEM_EEE_1G_ADV;
2072 	if (modes & ADVERTISED_10000baseT_Full)
2073 		eee_adv |= SHMEM_EEE_10G_ADV;
2074 
2075 	return eee_adv << shift;
2076 }
2077 
2078 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2079 {
2080 	struct bnx2x *bp = netdev_priv(dev);
2081 	u32 eee_cfg;
2082 
2083 	if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2084 		DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2085 		return -EOPNOTSUPP;
2086 	}
2087 
2088 	eee_cfg = bp->link_vars.eee_status;
2089 
2090 	edata->supported =
2091 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2092 				 SHMEM_EEE_SUPPORTED_SHIFT);
2093 
2094 	edata->advertised =
2095 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2096 				 SHMEM_EEE_ADV_STATUS_SHIFT);
2097 	edata->lp_advertised =
2098 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2099 				 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2100 
2101 	/* SHMEM value is in 16u units --> Convert to 1u units. */
2102 	edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2103 
2104 	edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)	? 1 : 0;
2105 	edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)	? 1 : 0;
2106 	edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2107 
2108 	return 0;
2109 }
2110 
2111 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2112 {
2113 	struct bnx2x *bp = netdev_priv(dev);
2114 	u32 eee_cfg;
2115 	u32 advertised;
2116 
2117 	if (IS_MF(bp))
2118 		return 0;
2119 
2120 	if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2121 		DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2122 		return -EOPNOTSUPP;
2123 	}
2124 
2125 	eee_cfg = bp->link_vars.eee_status;
2126 
2127 	if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2128 		DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2129 		return -EOPNOTSUPP;
2130 	}
2131 
2132 	advertised = bnx2x_adv_to_eee(edata->advertised,
2133 				      SHMEM_EEE_ADV_STATUS_SHIFT);
2134 	if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2135 		DP(BNX2X_MSG_ETHTOOL,
2136 		   "Direct manipulation of EEE advertisement is not supported\n");
2137 		return -EINVAL;
2138 	}
2139 
2140 	if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2141 		DP(BNX2X_MSG_ETHTOOL,
2142 		   "Maximal Tx Lpi timer supported is %x(u)\n",
2143 		   EEE_MODE_TIMER_MASK);
2144 		return -EINVAL;
2145 	}
2146 	if (edata->tx_lpi_enabled &&
2147 	    (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2148 		DP(BNX2X_MSG_ETHTOOL,
2149 		   "Minimal Tx Lpi timer supported is %d(u)\n",
2150 		   EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2151 		return -EINVAL;
2152 	}
2153 
2154 	/* All is well; Apply changes*/
2155 	if (edata->eee_enabled)
2156 		bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2157 	else
2158 		bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2159 
2160 	if (edata->tx_lpi_enabled)
2161 		bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2162 	else
2163 		bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2164 
2165 	bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2166 	bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2167 				    EEE_MODE_TIMER_MASK) |
2168 				    EEE_MODE_OVERRIDE_NVRAM |
2169 				    EEE_MODE_OUTPUT_TIME;
2170 
2171 	/* Restart link to propagate changes */
2172 	if (netif_running(dev)) {
2173 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2174 		bnx2x_force_link_reset(bp);
2175 		bnx2x_link_set(bp);
2176 	}
2177 
2178 	return 0;
2179 }
2180 
2181 enum {
2182 	BNX2X_CHIP_E1_OFST = 0,
2183 	BNX2X_CHIP_E1H_OFST,
2184 	BNX2X_CHIP_E2_OFST,
2185 	BNX2X_CHIP_E3_OFST,
2186 	BNX2X_CHIP_E3B0_OFST,
2187 	BNX2X_CHIP_MAX_OFST
2188 };
2189 
2190 #define BNX2X_CHIP_MASK_E1	(1 << BNX2X_CHIP_E1_OFST)
2191 #define BNX2X_CHIP_MASK_E1H	(1 << BNX2X_CHIP_E1H_OFST)
2192 #define BNX2X_CHIP_MASK_E2	(1 << BNX2X_CHIP_E2_OFST)
2193 #define BNX2X_CHIP_MASK_E3	(1 << BNX2X_CHIP_E3_OFST)
2194 #define BNX2X_CHIP_MASK_E3B0	(1 << BNX2X_CHIP_E3B0_OFST)
2195 
2196 #define BNX2X_CHIP_MASK_ALL	((1 << BNX2X_CHIP_MAX_OFST) - 1)
2197 #define BNX2X_CHIP_MASK_E1X	(BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2198 
2199 static int bnx2x_test_registers(struct bnx2x *bp)
2200 {
2201 	int idx, i, rc = -ENODEV;
2202 	u32 wr_val = 0, hw;
2203 	int port = BP_PORT(bp);
2204 	static const struct {
2205 		u32 hw;
2206 		u32 offset0;
2207 		u32 offset1;
2208 		u32 mask;
2209 	} reg_tbl[] = {
2210 /* 0 */		{ BNX2X_CHIP_MASK_ALL,
2211 			BRB1_REG_PAUSE_LOW_THRESHOLD_0,	4, 0x000003ff },
2212 		{ BNX2X_CHIP_MASK_ALL,
2213 			DORQ_REG_DB_ADDR0,		4, 0xffffffff },
2214 		{ BNX2X_CHIP_MASK_E1X,
2215 			HC_REG_AGG_INT_0,		4, 0x000003ff },
2216 		{ BNX2X_CHIP_MASK_ALL,
2217 			PBF_REG_MAC_IF0_ENABLE,		4, 0x00000001 },
2218 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2219 			PBF_REG_P0_INIT_CRD,		4, 0x000007ff },
2220 		{ BNX2X_CHIP_MASK_E3B0,
2221 			PBF_REG_INIT_CRD_Q0,		4, 0x000007ff },
2222 		{ BNX2X_CHIP_MASK_ALL,
2223 			PRS_REG_CID_PORT_0,		4, 0x00ffffff },
2224 		{ BNX2X_CHIP_MASK_ALL,
2225 			PXP2_REG_PSWRQ_CDU0_L2P,	4, 0x000fffff },
2226 		{ BNX2X_CHIP_MASK_ALL,
2227 			PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2228 		{ BNX2X_CHIP_MASK_ALL,
2229 			PXP2_REG_PSWRQ_TM0_L2P,		4, 0x000fffff },
2230 /* 10 */	{ BNX2X_CHIP_MASK_ALL,
2231 			PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2232 		{ BNX2X_CHIP_MASK_ALL,
2233 			PXP2_REG_PSWRQ_TSDM0_L2P,	4, 0x000fffff },
2234 		{ BNX2X_CHIP_MASK_ALL,
2235 			QM_REG_CONNNUM_0,		4, 0x000fffff },
2236 		{ BNX2X_CHIP_MASK_ALL,
2237 			TM_REG_LIN0_MAX_ACTIVE_CID,	4, 0x0003ffff },
2238 		{ BNX2X_CHIP_MASK_ALL,
2239 			SRC_REG_KEYRSS0_0,		40, 0xffffffff },
2240 		{ BNX2X_CHIP_MASK_ALL,
2241 			SRC_REG_KEYRSS0_7,		40, 0xffffffff },
2242 		{ BNX2X_CHIP_MASK_ALL,
2243 			XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2244 		{ BNX2X_CHIP_MASK_ALL,
2245 			XCM_REG_WU_DA_CNT_CMD00,	4, 0x00000003 },
2246 		{ BNX2X_CHIP_MASK_ALL,
2247 			XCM_REG_GLB_DEL_ACK_MAX_CNT_0,	4, 0x000000ff },
2248 		{ BNX2X_CHIP_MASK_ALL,
2249 			NIG_REG_LLH0_T_BIT,		4, 0x00000001 },
2250 /* 20 */	{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2251 			NIG_REG_EMAC0_IN_EN,		4, 0x00000001 },
2252 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2253 			NIG_REG_BMAC0_IN_EN,		4, 0x00000001 },
2254 		{ BNX2X_CHIP_MASK_ALL,
2255 			NIG_REG_XCM0_OUT_EN,		4, 0x00000001 },
2256 		{ BNX2X_CHIP_MASK_ALL,
2257 			NIG_REG_BRB0_OUT_EN,		4, 0x00000001 },
2258 		{ BNX2X_CHIP_MASK_ALL,
2259 			NIG_REG_LLH0_XCM_MASK,		4, 0x00000007 },
2260 		{ BNX2X_CHIP_MASK_ALL,
2261 			NIG_REG_LLH0_ACPI_PAT_6_LEN,	68, 0x000000ff },
2262 		{ BNX2X_CHIP_MASK_ALL,
2263 			NIG_REG_LLH0_ACPI_PAT_0_CRC,	68, 0xffffffff },
2264 		{ BNX2X_CHIP_MASK_ALL,
2265 			NIG_REG_LLH0_DEST_MAC_0_0,	160, 0xffffffff },
2266 		{ BNX2X_CHIP_MASK_ALL,
2267 			NIG_REG_LLH0_DEST_IP_0_1,	160, 0xffffffff },
2268 		{ BNX2X_CHIP_MASK_ALL,
2269 			NIG_REG_LLH0_IPV4_IPV6_0,	160, 0x00000001 },
2270 /* 30 */	{ BNX2X_CHIP_MASK_ALL,
2271 			NIG_REG_LLH0_DEST_UDP_0,	160, 0x0000ffff },
2272 		{ BNX2X_CHIP_MASK_ALL,
2273 			NIG_REG_LLH0_DEST_TCP_0,	160, 0x0000ffff },
2274 		{ BNX2X_CHIP_MASK_ALL,
2275 			NIG_REG_LLH0_VLAN_ID_0,	160, 0x00000fff },
2276 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2277 			NIG_REG_XGXS_SERDES0_MODE_SEL,	4, 0x00000001 },
2278 		{ BNX2X_CHIP_MASK_ALL,
2279 			NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2280 		{ BNX2X_CHIP_MASK_ALL,
2281 			NIG_REG_STATUS_INTERRUPT_PORT0,	4, 0x07ffffff },
2282 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2283 			NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2284 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2285 			NIG_REG_SERDES0_CTRL_PHY_ADDR,	16, 0x0000001f },
2286 
2287 		{ BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2288 	};
2289 
2290 	if (!bnx2x_is_nvm_accessible(bp)) {
2291 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2292 		   "cannot access eeprom when the interface is down\n");
2293 		return rc;
2294 	}
2295 
2296 	if (CHIP_IS_E1(bp))
2297 		hw = BNX2X_CHIP_MASK_E1;
2298 	else if (CHIP_IS_E1H(bp))
2299 		hw = BNX2X_CHIP_MASK_E1H;
2300 	else if (CHIP_IS_E2(bp))
2301 		hw = BNX2X_CHIP_MASK_E2;
2302 	else if (CHIP_IS_E3B0(bp))
2303 		hw = BNX2X_CHIP_MASK_E3B0;
2304 	else /* e3 A0 */
2305 		hw = BNX2X_CHIP_MASK_E3;
2306 
2307 	/* Repeat the test twice:
2308 	 * First by writing 0x00000000, second by writing 0xffffffff
2309 	 */
2310 	for (idx = 0; idx < 2; idx++) {
2311 
2312 		switch (idx) {
2313 		case 0:
2314 			wr_val = 0;
2315 			break;
2316 		case 1:
2317 			wr_val = 0xffffffff;
2318 			break;
2319 		}
2320 
2321 		for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2322 			u32 offset, mask, save_val, val;
2323 			if (!(hw & reg_tbl[i].hw))
2324 				continue;
2325 
2326 			offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2327 			mask = reg_tbl[i].mask;
2328 
2329 			save_val = REG_RD(bp, offset);
2330 
2331 			REG_WR(bp, offset, wr_val & mask);
2332 
2333 			val = REG_RD(bp, offset);
2334 
2335 			/* Restore the original register's value */
2336 			REG_WR(bp, offset, save_val);
2337 
2338 			/* verify value is as expected */
2339 			if ((val & mask) != (wr_val & mask)) {
2340 				DP(BNX2X_MSG_ETHTOOL,
2341 				   "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2342 				   offset, val, wr_val, mask);
2343 				goto test_reg_exit;
2344 			}
2345 		}
2346 	}
2347 
2348 	rc = 0;
2349 
2350 test_reg_exit:
2351 	return rc;
2352 }
2353 
2354 static int bnx2x_test_memory(struct bnx2x *bp)
2355 {
2356 	int i, j, rc = -ENODEV;
2357 	u32 val, index;
2358 	static const struct {
2359 		u32 offset;
2360 		int size;
2361 	} mem_tbl[] = {
2362 		{ CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2363 		{ CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2364 		{ CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2365 		{ DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2366 		{ TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2367 		{ UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2368 		{ XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2369 
2370 		{ 0xffffffff, 0 }
2371 	};
2372 
2373 	static const struct {
2374 		char *name;
2375 		u32 offset;
2376 		u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2377 	} prty_tbl[] = {
2378 		{ "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2379 			{0x3ffc0, 0,   0, 0} },
2380 		{ "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2381 			{0x2,     0x2, 0, 0} },
2382 		{ "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2383 			{0,       0,   0, 0} },
2384 		{ "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2385 			{0x3ffc0, 0,   0, 0} },
2386 		{ "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2387 			{0x3ffc0, 0,   0, 0} },
2388 		{ "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2389 			{0x3ffc1, 0,   0, 0} },
2390 
2391 		{ NULL, 0xffffffff, {0, 0, 0, 0} }
2392 	};
2393 
2394 	if (!bnx2x_is_nvm_accessible(bp)) {
2395 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2396 		   "cannot access eeprom when the interface is down\n");
2397 		return rc;
2398 	}
2399 
2400 	if (CHIP_IS_E1(bp))
2401 		index = BNX2X_CHIP_E1_OFST;
2402 	else if (CHIP_IS_E1H(bp))
2403 		index = BNX2X_CHIP_E1H_OFST;
2404 	else if (CHIP_IS_E2(bp))
2405 		index = BNX2X_CHIP_E2_OFST;
2406 	else /* e3 */
2407 		index = BNX2X_CHIP_E3_OFST;
2408 
2409 	/* pre-Check the parity status */
2410 	for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2411 		val = REG_RD(bp, prty_tbl[i].offset);
2412 		if (val & ~(prty_tbl[i].hw_mask[index])) {
2413 			DP(BNX2X_MSG_ETHTOOL,
2414 			   "%s is 0x%x\n", prty_tbl[i].name, val);
2415 			goto test_mem_exit;
2416 		}
2417 	}
2418 
2419 	/* Go through all the memories */
2420 	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2421 		for (j = 0; j < mem_tbl[i].size; j++)
2422 			REG_RD(bp, mem_tbl[i].offset + j*4);
2423 
2424 	/* Check the parity status */
2425 	for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2426 		val = REG_RD(bp, prty_tbl[i].offset);
2427 		if (val & ~(prty_tbl[i].hw_mask[index])) {
2428 			DP(BNX2X_MSG_ETHTOOL,
2429 			   "%s is 0x%x\n", prty_tbl[i].name, val);
2430 			goto test_mem_exit;
2431 		}
2432 	}
2433 
2434 	rc = 0;
2435 
2436 test_mem_exit:
2437 	return rc;
2438 }
2439 
2440 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2441 {
2442 	int cnt = 1400;
2443 
2444 	if (link_up) {
2445 		while (bnx2x_link_test(bp, is_serdes) && cnt--)
2446 			msleep(20);
2447 
2448 		if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2449 			DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2450 
2451 		cnt = 1400;
2452 		while (!bp->link_vars.link_up && cnt--)
2453 			msleep(20);
2454 
2455 		if (cnt <= 0 && !bp->link_vars.link_up)
2456 			DP(BNX2X_MSG_ETHTOOL,
2457 			   "Timeout waiting for link init\n");
2458 	}
2459 }
2460 
2461 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2462 {
2463 	unsigned int pkt_size, num_pkts, i;
2464 	struct sk_buff *skb;
2465 	unsigned char *packet;
2466 	struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2467 	struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2468 	struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2469 	u16 tx_start_idx, tx_idx;
2470 	u16 rx_start_idx, rx_idx;
2471 	u16 pkt_prod, bd_prod;
2472 	struct sw_tx_bd *tx_buf;
2473 	struct eth_tx_start_bd *tx_start_bd;
2474 	dma_addr_t mapping;
2475 	union eth_rx_cqe *cqe;
2476 	u8 cqe_fp_flags, cqe_fp_type;
2477 	struct sw_rx_bd *rx_buf;
2478 	u16 len;
2479 	int rc = -ENODEV;
2480 	u8 *data;
2481 	struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2482 						       txdata->txq_index);
2483 
2484 	/* check the loopback mode */
2485 	switch (loopback_mode) {
2486 	case BNX2X_PHY_LOOPBACK:
2487 		if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2488 			DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2489 			return -EINVAL;
2490 		}
2491 		break;
2492 	case BNX2X_MAC_LOOPBACK:
2493 		if (CHIP_IS_E3(bp)) {
2494 			int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2495 			if (bp->port.supported[cfg_idx] &
2496 			    (SUPPORTED_10000baseT_Full |
2497 			     SUPPORTED_20000baseMLD2_Full |
2498 			     SUPPORTED_20000baseKR2_Full))
2499 				bp->link_params.loopback_mode = LOOPBACK_XMAC;
2500 			else
2501 				bp->link_params.loopback_mode = LOOPBACK_UMAC;
2502 		} else
2503 			bp->link_params.loopback_mode = LOOPBACK_BMAC;
2504 
2505 		bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2506 		break;
2507 	case BNX2X_EXT_LOOPBACK:
2508 		if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2509 			DP(BNX2X_MSG_ETHTOOL,
2510 			   "Can't configure external loopback\n");
2511 			return -EINVAL;
2512 		}
2513 		break;
2514 	default:
2515 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2516 		return -EINVAL;
2517 	}
2518 
2519 	/* prepare the loopback packet */
2520 	pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2521 		     bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2522 	skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2523 	if (!skb) {
2524 		DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2525 		rc = -ENOMEM;
2526 		goto test_loopback_exit;
2527 	}
2528 	packet = skb_put(skb, pkt_size);
2529 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2530 	eth_zero_addr(packet + ETH_ALEN);
2531 	memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2532 	for (i = ETH_HLEN; i < pkt_size; i++)
2533 		packet[i] = (unsigned char) (i & 0xff);
2534 	mapping = dma_map_single(&bp->pdev->dev, skb->data,
2535 				 skb_headlen(skb), DMA_TO_DEVICE);
2536 	if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2537 		rc = -ENOMEM;
2538 		dev_kfree_skb(skb);
2539 		DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2540 		goto test_loopback_exit;
2541 	}
2542 
2543 	/* send the loopback packet */
2544 	num_pkts = 0;
2545 	tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2546 	rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2547 
2548 	netdev_tx_sent_queue(txq, skb->len);
2549 
2550 	pkt_prod = txdata->tx_pkt_prod++;
2551 	tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2552 	tx_buf->first_bd = txdata->tx_bd_prod;
2553 	tx_buf->skb = skb;
2554 	tx_buf->flags = 0;
2555 
2556 	bd_prod = TX_BD(txdata->tx_bd_prod);
2557 	tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2558 	tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2559 	tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2560 	tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2561 	tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2562 	tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2563 	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2564 	SET_FLAG(tx_start_bd->general_data,
2565 		 ETH_TX_START_BD_HDR_NBDS,
2566 		 1);
2567 	SET_FLAG(tx_start_bd->general_data,
2568 		 ETH_TX_START_BD_PARSE_NBDS,
2569 		 0);
2570 
2571 	/* turn on parsing and get a BD */
2572 	bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2573 
2574 	if (CHIP_IS_E1x(bp)) {
2575 		u16 global_data = 0;
2576 		struct eth_tx_parse_bd_e1x  *pbd_e1x =
2577 			&txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2578 		memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2579 		SET_FLAG(global_data,
2580 			 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2581 		pbd_e1x->global_data = cpu_to_le16(global_data);
2582 	} else {
2583 		u32 parsing_data = 0;
2584 		struct eth_tx_parse_bd_e2  *pbd_e2 =
2585 			&txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2586 		memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2587 		SET_FLAG(parsing_data,
2588 			 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2589 		pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2590 	}
2591 	wmb();
2592 
2593 	txdata->tx_db.data.prod += 2;
2594 	barrier();
2595 	DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2596 
2597 	mmiowb();
2598 	barrier();
2599 
2600 	num_pkts++;
2601 	txdata->tx_bd_prod += 2; /* start + pbd */
2602 
2603 	udelay(100);
2604 
2605 	tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2606 	if (tx_idx != tx_start_idx + num_pkts)
2607 		goto test_loopback_exit;
2608 
2609 	/* Unlike HC IGU won't generate an interrupt for status block
2610 	 * updates that have been performed while interrupts were
2611 	 * disabled.
2612 	 */
2613 	if (bp->common.int_block == INT_BLOCK_IGU) {
2614 		/* Disable local BHes to prevent a dead-lock situation between
2615 		 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2616 		 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2617 		 */
2618 		local_bh_disable();
2619 		bnx2x_tx_int(bp, txdata);
2620 		local_bh_enable();
2621 	}
2622 
2623 	rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2624 	if (rx_idx != rx_start_idx + num_pkts)
2625 		goto test_loopback_exit;
2626 
2627 	cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2628 	cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2629 	cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2630 	if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2631 		goto test_loopback_rx_exit;
2632 
2633 	len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2634 	if (len != pkt_size)
2635 		goto test_loopback_rx_exit;
2636 
2637 	rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2638 	dma_sync_single_for_cpu(&bp->pdev->dev,
2639 				   dma_unmap_addr(rx_buf, mapping),
2640 				   fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2641 	data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2642 	for (i = ETH_HLEN; i < pkt_size; i++)
2643 		if (*(data + i) != (unsigned char) (i & 0xff))
2644 			goto test_loopback_rx_exit;
2645 
2646 	rc = 0;
2647 
2648 test_loopback_rx_exit:
2649 
2650 	fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2651 	fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2652 	fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2653 	fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2654 
2655 	/* Update producers */
2656 	bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2657 			     fp_rx->rx_sge_prod);
2658 
2659 test_loopback_exit:
2660 	bp->link_params.loopback_mode = LOOPBACK_NONE;
2661 
2662 	return rc;
2663 }
2664 
2665 static int bnx2x_test_loopback(struct bnx2x *bp)
2666 {
2667 	int rc = 0, res;
2668 
2669 	if (BP_NOMCP(bp))
2670 		return rc;
2671 
2672 	if (!netif_running(bp->dev))
2673 		return BNX2X_LOOPBACK_FAILED;
2674 
2675 	bnx2x_netif_stop(bp, 1);
2676 	bnx2x_acquire_phy_lock(bp);
2677 
2678 	res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2679 	if (res) {
2680 		DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2681 		rc |= BNX2X_PHY_LOOPBACK_FAILED;
2682 	}
2683 
2684 	res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2685 	if (res) {
2686 		DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2687 		rc |= BNX2X_MAC_LOOPBACK_FAILED;
2688 	}
2689 
2690 	bnx2x_release_phy_lock(bp);
2691 	bnx2x_netif_start(bp);
2692 
2693 	return rc;
2694 }
2695 
2696 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2697 {
2698 	int rc;
2699 	u8 is_serdes =
2700 		(bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2701 
2702 	if (BP_NOMCP(bp))
2703 		return -ENODEV;
2704 
2705 	if (!netif_running(bp->dev))
2706 		return BNX2X_EXT_LOOPBACK_FAILED;
2707 
2708 	bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2709 	rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2710 	if (rc) {
2711 		DP(BNX2X_MSG_ETHTOOL,
2712 		   "Can't perform self-test, nic_load (for external lb) failed\n");
2713 		return -ENODEV;
2714 	}
2715 	bnx2x_wait_for_link(bp, 1, is_serdes);
2716 
2717 	bnx2x_netif_stop(bp, 1);
2718 
2719 	rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2720 	if (rc)
2721 		DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2722 
2723 	bnx2x_netif_start(bp);
2724 
2725 	return rc;
2726 }
2727 
2728 struct code_entry {
2729 	u32 sram_start_addr;
2730 	u32 code_attribute;
2731 #define CODE_IMAGE_TYPE_MASK			0xf0800003
2732 #define CODE_IMAGE_VNTAG_PROFILES_DATA		0xd0000003
2733 #define CODE_IMAGE_LENGTH_MASK			0x007ffffc
2734 #define CODE_IMAGE_TYPE_EXTENDED_DIR		0xe0000000
2735 	u32 nvm_start_addr;
2736 };
2737 
2738 #define CODE_ENTRY_MAX			16
2739 #define CODE_ENTRY_EXTENDED_DIR_IDX	15
2740 #define MAX_IMAGES_IN_EXTENDED_DIR	64
2741 #define NVRAM_DIR_OFFSET		0x14
2742 
2743 #define EXTENDED_DIR_EXISTS(code)					  \
2744 	((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2745 	 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2746 
2747 #define CRC32_RESIDUAL			0xdebb20e3
2748 #define CRC_BUFF_SIZE			256
2749 
2750 static int bnx2x_nvram_crc(struct bnx2x *bp,
2751 			   int offset,
2752 			   int size,
2753 			   u8 *buff)
2754 {
2755 	u32 crc = ~0;
2756 	int rc = 0, done = 0;
2757 
2758 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2759 	   "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2760 
2761 	while (done < size) {
2762 		int count = min_t(int, size - done, CRC_BUFF_SIZE);
2763 
2764 		rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2765 
2766 		if (rc)
2767 			return rc;
2768 
2769 		crc = crc32_le(crc, buff, count);
2770 		done += count;
2771 	}
2772 
2773 	if (crc != CRC32_RESIDUAL)
2774 		rc = -EINVAL;
2775 
2776 	return rc;
2777 }
2778 
2779 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2780 				struct code_entry *entry,
2781 				u8 *buff)
2782 {
2783 	size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2784 	u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2785 	int rc;
2786 
2787 	/* Zero-length images and AFEX profiles do not have CRC */
2788 	if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2789 		return 0;
2790 
2791 	rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2792 	if (rc)
2793 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2794 		   "image %x has failed crc test (rc %d)\n", type, rc);
2795 
2796 	return rc;
2797 }
2798 
2799 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2800 {
2801 	int rc;
2802 	struct code_entry entry;
2803 
2804 	rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2805 	if (rc)
2806 		return rc;
2807 
2808 	return bnx2x_test_nvram_dir(bp, &entry, buff);
2809 }
2810 
2811 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2812 {
2813 	u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2814 	struct code_entry entry;
2815 	int i;
2816 
2817 	rc = bnx2x_nvram_read32(bp,
2818 				dir_offset +
2819 				sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2820 				(u32 *)&entry, sizeof(entry));
2821 	if (rc)
2822 		return rc;
2823 
2824 	if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2825 		return 0;
2826 
2827 	rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2828 				&cnt, sizeof(u32));
2829 	if (rc)
2830 		return rc;
2831 
2832 	dir_offset = entry.nvm_start_addr + 8;
2833 
2834 	for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2835 		rc = bnx2x_test_dir_entry(bp, dir_offset +
2836 					      sizeof(struct code_entry) * i,
2837 					  buff);
2838 		if (rc)
2839 			return rc;
2840 	}
2841 
2842 	return 0;
2843 }
2844 
2845 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2846 {
2847 	u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2848 	int i;
2849 
2850 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2851 
2852 	for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2853 		rc = bnx2x_test_dir_entry(bp, dir_offset +
2854 					      sizeof(struct code_entry) * i,
2855 					  buff);
2856 		if (rc)
2857 			return rc;
2858 	}
2859 
2860 	return bnx2x_test_nvram_ext_dirs(bp, buff);
2861 }
2862 
2863 struct crc_pair {
2864 	int offset;
2865 	int size;
2866 };
2867 
2868 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2869 				const struct crc_pair *nvram_tbl, u8 *buf)
2870 {
2871 	int i;
2872 
2873 	for (i = 0; nvram_tbl[i].size; i++) {
2874 		int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2875 					 nvram_tbl[i].size, buf);
2876 		if (rc) {
2877 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2878 			   "nvram_tbl[%d] has failed crc test (rc %d)\n",
2879 			   i, rc);
2880 			return rc;
2881 		}
2882 	}
2883 
2884 	return 0;
2885 }
2886 
2887 static int bnx2x_test_nvram(struct bnx2x *bp)
2888 {
2889 	static const struct crc_pair nvram_tbl[] = {
2890 		{     0,  0x14 }, /* bootstrap */
2891 		{  0x14,  0xec }, /* dir */
2892 		{ 0x100, 0x350 }, /* manuf_info */
2893 		{ 0x450,  0xf0 }, /* feature_info */
2894 		{ 0x640,  0x64 }, /* upgrade_key_info */
2895 		{ 0x708,  0x70 }, /* manuf_key_info */
2896 		{     0,     0 }
2897 	};
2898 	static const struct crc_pair nvram_tbl2[] = {
2899 		{ 0x7e8, 0x350 }, /* manuf_info2 */
2900 		{ 0xb38,  0xf0 }, /* feature_info */
2901 		{     0,     0 }
2902 	};
2903 
2904 	u8 *buf;
2905 	int rc;
2906 	u32 magic;
2907 
2908 	if (BP_NOMCP(bp))
2909 		return 0;
2910 
2911 	buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2912 	if (!buf) {
2913 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2914 		rc = -ENOMEM;
2915 		goto test_nvram_exit;
2916 	}
2917 
2918 	rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2919 	if (rc) {
2920 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2921 		   "magic value read (rc %d)\n", rc);
2922 		goto test_nvram_exit;
2923 	}
2924 
2925 	if (magic != 0x669955aa) {
2926 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2927 		   "wrong magic value (0x%08x)\n", magic);
2928 		rc = -ENODEV;
2929 		goto test_nvram_exit;
2930 	}
2931 
2932 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2933 	rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2934 	if (rc)
2935 		goto test_nvram_exit;
2936 
2937 	if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2938 		u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2939 			   SHARED_HW_CFG_HIDE_PORT1;
2940 
2941 		if (!hide) {
2942 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2943 			   "Port 1 CRC test-set\n");
2944 			rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2945 			if (rc)
2946 				goto test_nvram_exit;
2947 		}
2948 	}
2949 
2950 	rc = bnx2x_test_nvram_dirs(bp, buf);
2951 
2952 test_nvram_exit:
2953 	kfree(buf);
2954 	return rc;
2955 }
2956 
2957 /* Send an EMPTY ramrod on the first queue */
2958 static int bnx2x_test_intr(struct bnx2x *bp)
2959 {
2960 	struct bnx2x_queue_state_params params = {NULL};
2961 
2962 	if (!netif_running(bp->dev)) {
2963 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2964 		   "cannot access eeprom when the interface is down\n");
2965 		return -ENODEV;
2966 	}
2967 
2968 	params.q_obj = &bp->sp_objs->q_obj;
2969 	params.cmd = BNX2X_Q_CMD_EMPTY;
2970 
2971 	__set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2972 
2973 	return bnx2x_queue_state_change(bp, &params);
2974 }
2975 
2976 static void bnx2x_self_test(struct net_device *dev,
2977 			    struct ethtool_test *etest, u64 *buf)
2978 {
2979 	struct bnx2x *bp = netdev_priv(dev);
2980 	u8 is_serdes, link_up;
2981 	int rc, cnt = 0;
2982 
2983 	if (pci_num_vf(bp->pdev)) {
2984 		DP(BNX2X_MSG_IOV,
2985 		   "VFs are enabled, can not perform self test\n");
2986 		return;
2987 	}
2988 
2989 	if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2990 		netdev_err(bp->dev,
2991 			   "Handling parity error recovery. Try again later\n");
2992 		etest->flags |= ETH_TEST_FL_FAILED;
2993 		return;
2994 	}
2995 
2996 	DP(BNX2X_MSG_ETHTOOL,
2997 	   "Self-test command parameters: offline = %d, external_lb = %d\n",
2998 	   (etest->flags & ETH_TEST_FL_OFFLINE),
2999 	   (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
3000 
3001 	memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
3002 
3003 	if (bnx2x_test_nvram(bp) != 0) {
3004 		if (!IS_MF(bp))
3005 			buf[4] = 1;
3006 		else
3007 			buf[0] = 1;
3008 		etest->flags |= ETH_TEST_FL_FAILED;
3009 	}
3010 
3011 	if (!netif_running(dev)) {
3012 		DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
3013 		return;
3014 	}
3015 
3016 	is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
3017 	link_up = bp->link_vars.link_up;
3018 	/* offline tests are not supported in MF mode */
3019 	if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3020 		int port = BP_PORT(bp);
3021 		u32 val;
3022 
3023 		/* save current value of input enable for TX port IF */
3024 		val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3025 		/* disable input for TX port IF */
3026 		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3027 
3028 		bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3029 		rc = bnx2x_nic_load(bp, LOAD_DIAG);
3030 		if (rc) {
3031 			etest->flags |= ETH_TEST_FL_FAILED;
3032 			DP(BNX2X_MSG_ETHTOOL,
3033 			   "Can't perform self-test, nic_load (for offline) failed\n");
3034 			return;
3035 		}
3036 
3037 		/* wait until link state is restored */
3038 		bnx2x_wait_for_link(bp, 1, is_serdes);
3039 
3040 		if (bnx2x_test_registers(bp) != 0) {
3041 			buf[0] = 1;
3042 			etest->flags |= ETH_TEST_FL_FAILED;
3043 		}
3044 		if (bnx2x_test_memory(bp) != 0) {
3045 			buf[1] = 1;
3046 			etest->flags |= ETH_TEST_FL_FAILED;
3047 		}
3048 
3049 		buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3050 		if (buf[2] != 0)
3051 			etest->flags |= ETH_TEST_FL_FAILED;
3052 
3053 		if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3054 			buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3055 			if (buf[3] != 0)
3056 				etest->flags |= ETH_TEST_FL_FAILED;
3057 			etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3058 		}
3059 
3060 		bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3061 
3062 		/* restore input for TX port IF */
3063 		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3064 		rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3065 		if (rc) {
3066 			etest->flags |= ETH_TEST_FL_FAILED;
3067 			DP(BNX2X_MSG_ETHTOOL,
3068 			   "Can't perform self-test, nic_load (for online) failed\n");
3069 			return;
3070 		}
3071 		/* wait until link state is restored */
3072 		bnx2x_wait_for_link(bp, link_up, is_serdes);
3073 	}
3074 
3075 	if (bnx2x_test_intr(bp) != 0) {
3076 		if (!IS_MF(bp))
3077 			buf[5] = 1;
3078 		else
3079 			buf[1] = 1;
3080 		etest->flags |= ETH_TEST_FL_FAILED;
3081 	}
3082 
3083 	if (link_up) {
3084 		cnt = 100;
3085 		while (bnx2x_link_test(bp, is_serdes) && --cnt)
3086 			msleep(20);
3087 	}
3088 
3089 	if (!cnt) {
3090 		if (!IS_MF(bp))
3091 			buf[6] = 1;
3092 		else
3093 			buf[2] = 1;
3094 		etest->flags |= ETH_TEST_FL_FAILED;
3095 	}
3096 }
3097 
3098 #define IS_PORT_STAT(i)		(bnx2x_stats_arr[i].is_port_stat)
3099 #define HIDE_PORT_STAT(bp)	IS_VF(bp)
3100 
3101 /* ethtool statistics are displayed for all regular ethernet queues and the
3102  * fcoe L2 queue if not disabled
3103  */
3104 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3105 {
3106 	return BNX2X_NUM_ETH_QUEUES(bp);
3107 }
3108 
3109 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3110 {
3111 	struct bnx2x *bp = netdev_priv(dev);
3112 	int i, num_strings = 0;
3113 
3114 	switch (stringset) {
3115 	case ETH_SS_STATS:
3116 		if (is_multi(bp)) {
3117 			num_strings = bnx2x_num_stat_queues(bp) *
3118 				      BNX2X_NUM_Q_STATS;
3119 		} else
3120 			num_strings = 0;
3121 		if (HIDE_PORT_STAT(bp)) {
3122 			for (i = 0; i < BNX2X_NUM_STATS; i++)
3123 				if (!IS_PORT_STAT(i))
3124 					num_strings++;
3125 		} else
3126 			num_strings += BNX2X_NUM_STATS;
3127 
3128 		return num_strings;
3129 
3130 	case ETH_SS_TEST:
3131 		return BNX2X_NUM_TESTS(bp);
3132 
3133 	case ETH_SS_PRIV_FLAGS:
3134 		return BNX2X_PRI_FLAG_LEN;
3135 
3136 	default:
3137 		return -EINVAL;
3138 	}
3139 }
3140 
3141 static u32 bnx2x_get_private_flags(struct net_device *dev)
3142 {
3143 	struct bnx2x *bp = netdev_priv(dev);
3144 	u32 flags = 0;
3145 
3146 	flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3147 	flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3148 	flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3149 
3150 	return flags;
3151 }
3152 
3153 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3154 {
3155 	struct bnx2x *bp = netdev_priv(dev);
3156 	int i, j, k, start;
3157 	char queue_name[MAX_QUEUE_NAME_LEN+1];
3158 
3159 	switch (stringset) {
3160 	case ETH_SS_STATS:
3161 		k = 0;
3162 		if (is_multi(bp)) {
3163 			for_each_eth_queue(bp, i) {
3164 				memset(queue_name, 0, sizeof(queue_name));
3165 				snprintf(queue_name, sizeof(queue_name),
3166 					 "%d", i);
3167 				for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3168 					snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3169 						ETH_GSTRING_LEN,
3170 						bnx2x_q_stats_arr[j].string,
3171 						queue_name);
3172 				k += BNX2X_NUM_Q_STATS;
3173 			}
3174 		}
3175 
3176 		for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3177 			if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3178 				continue;
3179 			strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3180 				   bnx2x_stats_arr[i].string);
3181 			j++;
3182 		}
3183 
3184 		break;
3185 
3186 	case ETH_SS_TEST:
3187 		/* First 4 tests cannot be done in MF mode */
3188 		if (!IS_MF(bp))
3189 			start = 0;
3190 		else
3191 			start = 4;
3192 		memcpy(buf, bnx2x_tests_str_arr + start,
3193 		       ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3194 		break;
3195 
3196 	case ETH_SS_PRIV_FLAGS:
3197 		memcpy(buf, bnx2x_private_arr,
3198 		       ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3199 		break;
3200 	}
3201 }
3202 
3203 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3204 				    struct ethtool_stats *stats, u64 *buf)
3205 {
3206 	struct bnx2x *bp = netdev_priv(dev);
3207 	u32 *hw_stats, *offset;
3208 	int i, j, k = 0;
3209 
3210 	if (is_multi(bp)) {
3211 		for_each_eth_queue(bp, i) {
3212 			hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3213 			for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3214 				if (bnx2x_q_stats_arr[j].size == 0) {
3215 					/* skip this counter */
3216 					buf[k + j] = 0;
3217 					continue;
3218 				}
3219 				offset = (hw_stats +
3220 					  bnx2x_q_stats_arr[j].offset);
3221 				if (bnx2x_q_stats_arr[j].size == 4) {
3222 					/* 4-byte counter */
3223 					buf[k + j] = (u64) *offset;
3224 					continue;
3225 				}
3226 				/* 8-byte counter */
3227 				buf[k + j] = HILO_U64(*offset, *(offset + 1));
3228 			}
3229 			k += BNX2X_NUM_Q_STATS;
3230 		}
3231 	}
3232 
3233 	hw_stats = (u32 *)&bp->eth_stats;
3234 	for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3235 		if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3236 			continue;
3237 		if (bnx2x_stats_arr[i].size == 0) {
3238 			/* skip this counter */
3239 			buf[k + j] = 0;
3240 			j++;
3241 			continue;
3242 		}
3243 		offset = (hw_stats + bnx2x_stats_arr[i].offset);
3244 		if (bnx2x_stats_arr[i].size == 4) {
3245 			/* 4-byte counter */
3246 			buf[k + j] = (u64) *offset;
3247 			j++;
3248 			continue;
3249 		}
3250 		/* 8-byte counter */
3251 		buf[k + j] = HILO_U64(*offset, *(offset + 1));
3252 		j++;
3253 	}
3254 }
3255 
3256 static int bnx2x_set_phys_id(struct net_device *dev,
3257 			     enum ethtool_phys_id_state state)
3258 {
3259 	struct bnx2x *bp = netdev_priv(dev);
3260 
3261 	if (!bnx2x_is_nvm_accessible(bp)) {
3262 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3263 		   "cannot access eeprom when the interface is down\n");
3264 		return -EAGAIN;
3265 	}
3266 
3267 	switch (state) {
3268 	case ETHTOOL_ID_ACTIVE:
3269 		return 1;	/* cycle on/off once per second */
3270 
3271 	case ETHTOOL_ID_ON:
3272 		bnx2x_acquire_phy_lock(bp);
3273 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3274 			      LED_MODE_ON, SPEED_1000);
3275 		bnx2x_release_phy_lock(bp);
3276 		break;
3277 
3278 	case ETHTOOL_ID_OFF:
3279 		bnx2x_acquire_phy_lock(bp);
3280 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3281 			      LED_MODE_FRONT_PANEL_OFF, 0);
3282 		bnx2x_release_phy_lock(bp);
3283 		break;
3284 
3285 	case ETHTOOL_ID_INACTIVE:
3286 		bnx2x_acquire_phy_lock(bp);
3287 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3288 			      LED_MODE_OPER,
3289 			      bp->link_vars.line_speed);
3290 		bnx2x_release_phy_lock(bp);
3291 	}
3292 
3293 	return 0;
3294 }
3295 
3296 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3297 {
3298 	switch (info->flow_type) {
3299 	case TCP_V4_FLOW:
3300 	case TCP_V6_FLOW:
3301 		info->data = RXH_IP_SRC | RXH_IP_DST |
3302 			     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3303 		break;
3304 	case UDP_V4_FLOW:
3305 		if (bp->rss_conf_obj.udp_rss_v4)
3306 			info->data = RXH_IP_SRC | RXH_IP_DST |
3307 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3308 		else
3309 			info->data = RXH_IP_SRC | RXH_IP_DST;
3310 		break;
3311 	case UDP_V6_FLOW:
3312 		if (bp->rss_conf_obj.udp_rss_v6)
3313 			info->data = RXH_IP_SRC | RXH_IP_DST |
3314 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3315 		else
3316 			info->data = RXH_IP_SRC | RXH_IP_DST;
3317 		break;
3318 	case IPV4_FLOW:
3319 	case IPV6_FLOW:
3320 		info->data = RXH_IP_SRC | RXH_IP_DST;
3321 		break;
3322 	default:
3323 		info->data = 0;
3324 		break;
3325 	}
3326 
3327 	return 0;
3328 }
3329 
3330 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3331 			   u32 *rules __always_unused)
3332 {
3333 	struct bnx2x *bp = netdev_priv(dev);
3334 
3335 	switch (info->cmd) {
3336 	case ETHTOOL_GRXRINGS:
3337 		info->data = BNX2X_NUM_ETH_QUEUES(bp);
3338 		return 0;
3339 	case ETHTOOL_GRXFH:
3340 		return bnx2x_get_rss_flags(bp, info);
3341 	default:
3342 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3343 		return -EOPNOTSUPP;
3344 	}
3345 }
3346 
3347 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3348 {
3349 	int udp_rss_requested;
3350 
3351 	DP(BNX2X_MSG_ETHTOOL,
3352 	   "Set rss flags command parameters: flow type = %d, data = %llu\n",
3353 	   info->flow_type, info->data);
3354 
3355 	switch (info->flow_type) {
3356 	case TCP_V4_FLOW:
3357 	case TCP_V6_FLOW:
3358 		/* For TCP only 4-tupple hash is supported */
3359 		if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3360 				  RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3361 			DP(BNX2X_MSG_ETHTOOL,
3362 			   "Command parameters not supported\n");
3363 			return -EINVAL;
3364 		}
3365 		return 0;
3366 
3367 	case UDP_V4_FLOW:
3368 	case UDP_V6_FLOW:
3369 		/* For UDP either 2-tupple hash or 4-tupple hash is supported */
3370 		if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3371 				   RXH_L4_B_0_1 | RXH_L4_B_2_3))
3372 			udp_rss_requested = 1;
3373 		else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3374 			udp_rss_requested = 0;
3375 		else
3376 			return -EINVAL;
3377 
3378 		if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3379 			DP(BNX2X_MSG_ETHTOOL,
3380 			   "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3381 			return -EINVAL;
3382 		}
3383 
3384 		if ((info->flow_type == UDP_V4_FLOW) &&
3385 		    (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3386 			bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3387 			DP(BNX2X_MSG_ETHTOOL,
3388 			   "rss re-configured, UDP 4-tupple %s\n",
3389 			   udp_rss_requested ? "enabled" : "disabled");
3390 			return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3391 		} else if ((info->flow_type == UDP_V6_FLOW) &&
3392 			   (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3393 			bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3394 			DP(BNX2X_MSG_ETHTOOL,
3395 			   "rss re-configured, UDP 4-tupple %s\n",
3396 			   udp_rss_requested ? "enabled" : "disabled");
3397 			return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3398 		}
3399 		return 0;
3400 
3401 	case IPV4_FLOW:
3402 	case IPV6_FLOW:
3403 		/* For IP only 2-tupple hash is supported */
3404 		if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3405 			DP(BNX2X_MSG_ETHTOOL,
3406 			   "Command parameters not supported\n");
3407 			return -EINVAL;
3408 		}
3409 		return 0;
3410 
3411 	case SCTP_V4_FLOW:
3412 	case AH_ESP_V4_FLOW:
3413 	case AH_V4_FLOW:
3414 	case ESP_V4_FLOW:
3415 	case SCTP_V6_FLOW:
3416 	case AH_ESP_V6_FLOW:
3417 	case AH_V6_FLOW:
3418 	case ESP_V6_FLOW:
3419 	case IP_USER_FLOW:
3420 	case ETHER_FLOW:
3421 		/* RSS is not supported for these protocols */
3422 		if (info->data) {
3423 			DP(BNX2X_MSG_ETHTOOL,
3424 			   "Command parameters not supported\n");
3425 			return -EINVAL;
3426 		}
3427 		return 0;
3428 
3429 	default:
3430 		return -EINVAL;
3431 	}
3432 }
3433 
3434 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3435 {
3436 	struct bnx2x *bp = netdev_priv(dev);
3437 
3438 	switch (info->cmd) {
3439 	case ETHTOOL_SRXFH:
3440 		return bnx2x_set_rss_flags(bp, info);
3441 	default:
3442 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3443 		return -EOPNOTSUPP;
3444 	}
3445 }
3446 
3447 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3448 {
3449 	return T_ETH_INDIRECTION_TABLE_SIZE;
3450 }
3451 
3452 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3453 			  u8 *hfunc)
3454 {
3455 	struct bnx2x *bp = netdev_priv(dev);
3456 	u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3457 	size_t i;
3458 
3459 	if (hfunc)
3460 		*hfunc = ETH_RSS_HASH_TOP;
3461 	if (!indir)
3462 		return 0;
3463 
3464 	/* Get the current configuration of the RSS indirection table */
3465 	bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3466 
3467 	/*
3468 	 * We can't use a memcpy() as an internal storage of an
3469 	 * indirection table is a u8 array while indir->ring_index
3470 	 * points to an array of u32.
3471 	 *
3472 	 * Indirection table contains the FW Client IDs, so we need to
3473 	 * align the returned table to the Client ID of the leading RSS
3474 	 * queue.
3475 	 */
3476 	for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3477 		indir[i] = ind_table[i] - bp->fp->cl_id;
3478 
3479 	return 0;
3480 }
3481 
3482 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3483 			  const u8 *key, const u8 hfunc)
3484 {
3485 	struct bnx2x *bp = netdev_priv(dev);
3486 	size_t i;
3487 
3488 	/* We require at least one supported parameter to be changed and no
3489 	 * change in any of the unsupported parameters
3490 	 */
3491 	if (key ||
3492 	    (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3493 		return -EOPNOTSUPP;
3494 
3495 	if (!indir)
3496 		return 0;
3497 
3498 	for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3499 		/*
3500 		 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3501 		 * as an internal storage of an indirection table is a u8 array
3502 		 * while indir->ring_index points to an array of u32.
3503 		 *
3504 		 * Indirection table contains the FW Client IDs, so we need to
3505 		 * align the received table to the Client ID of the leading RSS
3506 		 * queue
3507 		 */
3508 		bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3509 	}
3510 
3511 	return bnx2x_config_rss_eth(bp, false);
3512 }
3513 
3514 /**
3515  * bnx2x_get_channels - gets the number of RSS queues.
3516  *
3517  * @dev:		net device
3518  * @channels:		returns the number of max / current queues
3519  */
3520 static void bnx2x_get_channels(struct net_device *dev,
3521 			       struct ethtool_channels *channels)
3522 {
3523 	struct bnx2x *bp = netdev_priv(dev);
3524 
3525 	channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3526 	channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3527 }
3528 
3529 /**
3530  * bnx2x_change_num_queues - change the number of RSS queues.
3531  *
3532  * @bp:			bnx2x private structure
3533  *
3534  * Re-configure interrupt mode to get the new number of MSI-X
3535  * vectors and re-add NAPI objects.
3536  */
3537 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3538 {
3539 	bnx2x_disable_msi(bp);
3540 	bp->num_ethernet_queues = num_rss;
3541 	bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3542 	BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3543 	bnx2x_set_int_mode(bp);
3544 }
3545 
3546 /**
3547  * bnx2x_set_channels - sets the number of RSS queues.
3548  *
3549  * @dev:		net device
3550  * @channels:		includes the number of queues requested
3551  */
3552 static int bnx2x_set_channels(struct net_device *dev,
3553 			      struct ethtool_channels *channels)
3554 {
3555 	struct bnx2x *bp = netdev_priv(dev);
3556 
3557 	DP(BNX2X_MSG_ETHTOOL,
3558 	   "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3559 	   channels->rx_count, channels->tx_count, channels->other_count,
3560 	   channels->combined_count);
3561 
3562 	if (pci_num_vf(bp->pdev)) {
3563 		DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3564 		return -EPERM;
3565 	}
3566 
3567 	/* We don't support separate rx / tx channels.
3568 	 * We don't allow setting 'other' channels.
3569 	 */
3570 	if (channels->rx_count || channels->tx_count || channels->other_count
3571 	    || (channels->combined_count == 0) ||
3572 	    (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3573 		DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3574 		return -EINVAL;
3575 	}
3576 
3577 	/* Check if there was a change in the active parameters */
3578 	if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3579 		DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3580 		return 0;
3581 	}
3582 
3583 	/* Set the requested number of queues in bp context.
3584 	 * Note that the actual number of queues created during load may be
3585 	 * less than requested if memory is low.
3586 	 */
3587 	if (unlikely(!netif_running(dev))) {
3588 		bnx2x_change_num_queues(bp, channels->combined_count);
3589 		return 0;
3590 	}
3591 	bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3592 	bnx2x_change_num_queues(bp, channels->combined_count);
3593 	return bnx2x_nic_load(bp, LOAD_NORMAL);
3594 }
3595 
3596 static int bnx2x_get_ts_info(struct net_device *dev,
3597 			     struct ethtool_ts_info *info)
3598 {
3599 	struct bnx2x *bp = netdev_priv(dev);
3600 
3601 	if (bp->flags & PTP_SUPPORTED) {
3602 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3603 					SOF_TIMESTAMPING_RX_SOFTWARE |
3604 					SOF_TIMESTAMPING_SOFTWARE |
3605 					SOF_TIMESTAMPING_TX_HARDWARE |
3606 					SOF_TIMESTAMPING_RX_HARDWARE |
3607 					SOF_TIMESTAMPING_RAW_HARDWARE;
3608 
3609 		if (bp->ptp_clock)
3610 			info->phc_index = ptp_clock_index(bp->ptp_clock);
3611 		else
3612 			info->phc_index = -1;
3613 
3614 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3615 				   (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3616 				   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3617 				   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3618 
3619 		info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3620 
3621 		return 0;
3622 	}
3623 
3624 	return ethtool_op_get_ts_info(dev, info);
3625 }
3626 
3627 static const struct ethtool_ops bnx2x_ethtool_ops = {
3628 	.get_drvinfo		= bnx2x_get_drvinfo,
3629 	.get_regs_len		= bnx2x_get_regs_len,
3630 	.get_regs		= bnx2x_get_regs,
3631 	.get_dump_flag		= bnx2x_get_dump_flag,
3632 	.get_dump_data		= bnx2x_get_dump_data,
3633 	.set_dump		= bnx2x_set_dump,
3634 	.get_wol		= bnx2x_get_wol,
3635 	.set_wol		= bnx2x_set_wol,
3636 	.get_msglevel		= bnx2x_get_msglevel,
3637 	.set_msglevel		= bnx2x_set_msglevel,
3638 	.nway_reset		= bnx2x_nway_reset,
3639 	.get_link		= bnx2x_get_link,
3640 	.get_eeprom_len		= bnx2x_get_eeprom_len,
3641 	.get_eeprom		= bnx2x_get_eeprom,
3642 	.set_eeprom		= bnx2x_set_eeprom,
3643 	.get_coalesce		= bnx2x_get_coalesce,
3644 	.set_coalesce		= bnx2x_set_coalesce,
3645 	.get_ringparam		= bnx2x_get_ringparam,
3646 	.set_ringparam		= bnx2x_set_ringparam,
3647 	.get_pauseparam		= bnx2x_get_pauseparam,
3648 	.set_pauseparam		= bnx2x_set_pauseparam,
3649 	.self_test		= bnx2x_self_test,
3650 	.get_sset_count		= bnx2x_get_sset_count,
3651 	.get_priv_flags		= bnx2x_get_private_flags,
3652 	.get_strings		= bnx2x_get_strings,
3653 	.set_phys_id		= bnx2x_set_phys_id,
3654 	.get_ethtool_stats	= bnx2x_get_ethtool_stats,
3655 	.get_rxnfc		= bnx2x_get_rxnfc,
3656 	.set_rxnfc		= bnx2x_set_rxnfc,
3657 	.get_rxfh_indir_size	= bnx2x_get_rxfh_indir_size,
3658 	.get_rxfh		= bnx2x_get_rxfh,
3659 	.set_rxfh		= bnx2x_set_rxfh,
3660 	.get_channels		= bnx2x_get_channels,
3661 	.set_channels		= bnx2x_set_channels,
3662 	.get_module_info	= bnx2x_get_module_info,
3663 	.get_module_eeprom	= bnx2x_get_module_eeprom,
3664 	.get_eee		= bnx2x_get_eee,
3665 	.set_eee		= bnx2x_set_eee,
3666 	.get_ts_info		= bnx2x_get_ts_info,
3667 	.get_link_ksettings	= bnx2x_get_link_ksettings,
3668 	.set_link_ksettings	= bnx2x_set_link_ksettings,
3669 };
3670 
3671 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3672 	.get_drvinfo		= bnx2x_get_drvinfo,
3673 	.get_msglevel		= bnx2x_get_msglevel,
3674 	.set_msglevel		= bnx2x_set_msglevel,
3675 	.get_link		= bnx2x_get_link,
3676 	.get_coalesce		= bnx2x_get_coalesce,
3677 	.get_ringparam		= bnx2x_get_ringparam,
3678 	.set_ringparam		= bnx2x_set_ringparam,
3679 	.get_sset_count		= bnx2x_get_sset_count,
3680 	.get_strings		= bnx2x_get_strings,
3681 	.get_ethtool_stats	= bnx2x_get_ethtool_stats,
3682 	.get_rxnfc		= bnx2x_get_rxnfc,
3683 	.set_rxnfc		= bnx2x_set_rxnfc,
3684 	.get_rxfh_indir_size	= bnx2x_get_rxfh_indir_size,
3685 	.get_rxfh		= bnx2x_get_rxfh,
3686 	.set_rxfh		= bnx2x_set_rxfh,
3687 	.get_channels		= bnx2x_get_channels,
3688 	.set_channels		= bnx2x_set_channels,
3689 	.get_link_ksettings	= bnx2x_get_vf_link_ksettings,
3690 };
3691 
3692 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3693 {
3694 	netdev->ethtool_ops = (IS_PF(bp)) ?
3695 		&bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3696 }
3697