1 /* bnx2x_ethtool.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/ethtool.h> 23 #include <linux/netdevice.h> 24 #include <linux/types.h> 25 #include <linux/sched.h> 26 #include <linux/crc32.h> 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 #include "bnx2x_dump.h" 30 #include "bnx2x_init.h" 31 32 /* Note: in the format strings below %s is replaced by the queue-name which is 33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35 */ 36 #define MAX_QUEUE_NAME_LEN 4 37 static const struct { 38 long offset; 39 int size; 40 char string[ETH_GSTRING_LEN]; 41 } bnx2x_q_stats_arr[] = { 42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44 8, "[%s]: rx_ucast_packets" }, 45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46 8, "[%s]: rx_mcast_packets" }, 47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48 8, "[%s]: rx_bcast_packets" }, 49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50 { Q_STATS_OFFSET32(rx_err_discard_pkt), 51 4, "[%s]: rx_phy_ip_err_discards"}, 52 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53 4, "[%s]: rx_skb_alloc_discard" }, 54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 55 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" }, 56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58 8, "[%s]: tx_ucast_packets" }, 59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60 8, "[%s]: tx_mcast_packets" }, 61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62 8, "[%s]: tx_bcast_packets" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64 8, "[%s]: tpa_aggregations" }, 65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66 8, "[%s]: tpa_aggregated_frames"}, 67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69 4, "[%s]: driver_filtered_tx_pkt" } 70 }; 71 72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73 74 static const struct { 75 long offset; 76 int size; 77 bool is_port_stat; 78 char string[ETH_GSTRING_LEN]; 79 } bnx2x_stats_arr[] = { 80 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 81 8, false, "rx_bytes" }, 82 { STATS_OFFSET32(error_bytes_received_hi), 83 8, false, "rx_error_bytes" }, 84 { STATS_OFFSET32(total_unicast_packets_received_hi), 85 8, false, "rx_ucast_packets" }, 86 { STATS_OFFSET32(total_multicast_packets_received_hi), 87 8, false, "rx_mcast_packets" }, 88 { STATS_OFFSET32(total_broadcast_packets_received_hi), 89 8, false, "rx_bcast_packets" }, 90 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 91 8, true, "rx_crc_errors" }, 92 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 93 8, true, "rx_align_errors" }, 94 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 95 8, true, "rx_undersize_packets" }, 96 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 97 8, true, "rx_oversize_packets" }, 98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 99 8, true, "rx_fragments" }, 100 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 101 8, true, "rx_jabbers" }, 102 { STATS_OFFSET32(no_buff_discard_hi), 103 8, false, "rx_discards" }, 104 { STATS_OFFSET32(mac_filter_discard), 105 4, true, "rx_filtered_packets" }, 106 { STATS_OFFSET32(mf_tag_discard), 107 4, true, "rx_mf_tag_discard" }, 108 { STATS_OFFSET32(pfc_frames_received_hi), 109 8, true, "pfc_frames_received" }, 110 { STATS_OFFSET32(pfc_frames_sent_hi), 111 8, true, "pfc_frames_sent" }, 112 { STATS_OFFSET32(brb_drop_hi), 113 8, true, "rx_brb_discard" }, 114 { STATS_OFFSET32(brb_truncate_hi), 115 8, true, "rx_brb_truncate" }, 116 { STATS_OFFSET32(pause_frames_received_hi), 117 8, true, "rx_pause_frames" }, 118 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 119 8, true, "rx_mac_ctrl_frames" }, 120 { STATS_OFFSET32(nig_timer_max), 121 4, true, "rx_constant_pause_events" }, 122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 123 4, false, "rx_phy_ip_err_discards"}, 124 { STATS_OFFSET32(rx_skb_alloc_failed), 125 4, false, "rx_skb_alloc_discard" }, 126 { STATS_OFFSET32(hw_csum_err), 127 4, false, "rx_csum_offload_errors" }, 128 { STATS_OFFSET32(driver_xoff), 129 4, false, "tx_exhaustion_events" }, 130 { STATS_OFFSET32(total_bytes_transmitted_hi), 131 8, false, "tx_bytes" }, 132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133 8, true, "tx_error_bytes" }, 134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135 8, false, "tx_ucast_packets" }, 136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137 8, false, "tx_mcast_packets" }, 138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139 8, false, "tx_bcast_packets" }, 140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141 8, true, "tx_mac_errors" }, 142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143 8, true, "tx_carrier_errors" }, 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145 8, true, "tx_single_collisions" }, 146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147 8, true, "tx_multi_collisions" }, 148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149 8, true, "tx_deferred" }, 150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151 8, true, "tx_excess_collisions" }, 152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153 8, true, "tx_late_collisions" }, 154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155 8, true, "tx_total_collisions" }, 156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157 8, true, "tx_64_byte_packets" }, 158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159 8, true, "tx_65_to_127_byte_packets" }, 160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161 8, true, "tx_128_to_255_byte_packets" }, 162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163 8, true, "tx_256_to_511_byte_packets" }, 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165 8, true, "tx_512_to_1023_byte_packets" }, 166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167 8, true, "tx_1024_to_1522_byte_packets" }, 168 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169 8, true, "tx_1523_to_9022_byte_packets" }, 170 { STATS_OFFSET32(pause_frames_sent_hi), 171 8, true, "tx_pause_frames" }, 172 { STATS_OFFSET32(total_tpa_aggregations_hi), 173 8, false, "tpa_aggregations" }, 174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175 8, false, "tpa_aggregated_frames"}, 176 { STATS_OFFSET32(total_tpa_bytes_hi), 177 8, false, "tpa_bytes"}, 178 { STATS_OFFSET32(recoverable_error), 179 4, false, "recoverable_errors" }, 180 { STATS_OFFSET32(unrecoverable_error), 181 4, false, "unrecoverable_errors" }, 182 { STATS_OFFSET32(driver_filtered_tx_pkt), 183 4, false, "driver_filtered_tx_pkt" }, 184 { STATS_OFFSET32(eee_tx_lpi), 185 4, true, "Tx LPI entry count"}, 186 { STATS_OFFSET32(ptp_skip_tx_ts), 187 4, false, "ptp_skipped_tx_tstamp" }, 188 }; 189 190 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 191 192 static int bnx2x_get_port_type(struct bnx2x *bp) 193 { 194 int port_type; 195 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 196 switch (bp->link_params.phy[phy_idx].media_type) { 197 case ETH_PHY_SFPP_10G_FIBER: 198 case ETH_PHY_SFP_1G_FIBER: 199 case ETH_PHY_XFP_FIBER: 200 case ETH_PHY_KR: 201 case ETH_PHY_CX4: 202 port_type = PORT_FIBRE; 203 break; 204 case ETH_PHY_DA_TWINAX: 205 port_type = PORT_DA; 206 break; 207 case ETH_PHY_BASE_T: 208 port_type = PORT_TP; 209 break; 210 case ETH_PHY_NOT_PRESENT: 211 port_type = PORT_NONE; 212 break; 213 case ETH_PHY_UNSPECIFIED: 214 default: 215 port_type = PORT_OTHER; 216 break; 217 } 218 return port_type; 219 } 220 221 static int bnx2x_get_vf_link_ksettings(struct net_device *dev, 222 struct ethtool_link_ksettings *cmd) 223 { 224 struct bnx2x *bp = netdev_priv(dev); 225 u32 supported, advertising; 226 227 ethtool_convert_link_mode_to_legacy_u32(&supported, 228 cmd->link_modes.supported); 229 ethtool_convert_link_mode_to_legacy_u32(&advertising, 230 cmd->link_modes.advertising); 231 232 if (bp->state == BNX2X_STATE_OPEN) { 233 if (test_bit(BNX2X_LINK_REPORT_FD, 234 &bp->vf_link_vars.link_report_flags)) 235 cmd->base.duplex = DUPLEX_FULL; 236 else 237 cmd->base.duplex = DUPLEX_HALF; 238 239 cmd->base.speed = bp->vf_link_vars.line_speed; 240 } else { 241 cmd->base.duplex = DUPLEX_UNKNOWN; 242 cmd->base.speed = SPEED_UNKNOWN; 243 } 244 245 cmd->base.port = PORT_OTHER; 246 cmd->base.phy_address = 0; 247 cmd->base.autoneg = AUTONEG_DISABLE; 248 249 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 250 " supported 0x%x advertising 0x%x speed %u\n" 251 " duplex %d port %d phy_address %d\n" 252 " autoneg %d\n", 253 cmd->base.cmd, supported, advertising, 254 cmd->base.speed, 255 cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 256 cmd->base.autoneg); 257 258 return 0; 259 } 260 261 static int bnx2x_get_link_ksettings(struct net_device *dev, 262 struct ethtool_link_ksettings *cmd) 263 { 264 struct bnx2x *bp = netdev_priv(dev); 265 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 266 u32 media_type; 267 u32 supported, advertising, lp_advertising; 268 269 ethtool_convert_link_mode_to_legacy_u32(&lp_advertising, 270 cmd->link_modes.lp_advertising); 271 272 /* Dual Media boards present all available port types */ 273 supported = bp->port.supported[cfg_idx] | 274 (bp->port.supported[cfg_idx ^ 1] & 275 (SUPPORTED_TP | SUPPORTED_FIBRE)); 276 advertising = bp->port.advertising[cfg_idx]; 277 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 278 if (media_type == ETH_PHY_SFP_1G_FIBER) { 279 supported &= ~(SUPPORTED_10000baseT_Full); 280 advertising &= ~(ADVERTISED_10000baseT_Full); 281 } 282 283 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 284 !(bp->flags & MF_FUNC_DIS)) { 285 cmd->base.duplex = bp->link_vars.duplex; 286 287 if (IS_MF(bp) && !BP_NOMCP(bp)) 288 cmd->base.speed = bnx2x_get_mf_speed(bp); 289 else 290 cmd->base.speed = bp->link_vars.line_speed; 291 } else { 292 cmd->base.duplex = DUPLEX_UNKNOWN; 293 cmd->base.speed = SPEED_UNKNOWN; 294 } 295 296 cmd->base.port = bnx2x_get_port_type(bp); 297 298 cmd->base.phy_address = bp->mdio.prtad; 299 300 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 301 cmd->base.autoneg = AUTONEG_ENABLE; 302 else 303 cmd->base.autoneg = AUTONEG_DISABLE; 304 305 /* Publish LP advertised speeds and FC */ 306 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 307 u32 status = bp->link_vars.link_status; 308 309 lp_advertising |= ADVERTISED_Autoneg; 310 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 311 lp_advertising |= ADVERTISED_Pause; 312 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 313 lp_advertising |= ADVERTISED_Asym_Pause; 314 315 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 316 lp_advertising |= ADVERTISED_10baseT_Half; 317 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 318 lp_advertising |= ADVERTISED_10baseT_Full; 319 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 320 lp_advertising |= ADVERTISED_100baseT_Half; 321 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 322 lp_advertising |= ADVERTISED_100baseT_Full; 323 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 324 lp_advertising |= ADVERTISED_1000baseT_Half; 325 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 326 if (media_type == ETH_PHY_KR) { 327 lp_advertising |= 328 ADVERTISED_1000baseKX_Full; 329 } else { 330 lp_advertising |= 331 ADVERTISED_1000baseT_Full; 332 } 333 } 334 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 335 lp_advertising |= ADVERTISED_2500baseX_Full; 336 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 337 if (media_type == ETH_PHY_KR) { 338 lp_advertising |= 339 ADVERTISED_10000baseKR_Full; 340 } else { 341 lp_advertising |= 342 ADVERTISED_10000baseT_Full; 343 } 344 } 345 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 346 lp_advertising |= ADVERTISED_20000baseKR2_Full; 347 } 348 349 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 350 supported); 351 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 352 advertising); 353 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 354 lp_advertising); 355 356 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 357 " supported 0x%x advertising 0x%x speed %u\n" 358 " duplex %d port %d phy_address %d\n" 359 " autoneg %d\n", 360 cmd->base.cmd, supported, advertising, 361 cmd->base.speed, 362 cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 363 cmd->base.autoneg); 364 365 return 0; 366 } 367 368 static int bnx2x_set_link_ksettings(struct net_device *dev, 369 const struct ethtool_link_ksettings *cmd) 370 { 371 struct bnx2x *bp = netdev_priv(dev); 372 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 373 u32 speed, phy_idx; 374 u32 supported; 375 u8 duplex = cmd->base.duplex; 376 377 ethtool_convert_link_mode_to_legacy_u32(&supported, 378 cmd->link_modes.supported); 379 ethtool_convert_link_mode_to_legacy_u32(&advertising, 380 cmd->link_modes.advertising); 381 382 if (IS_MF_SD(bp)) 383 return 0; 384 385 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 386 " supported 0x%x advertising 0x%x speed %u\n" 387 " duplex %d port %d phy_address %d\n" 388 " autoneg %d\n", 389 cmd->base.cmd, supported, advertising, 390 cmd->base.speed, 391 cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 392 cmd->base.autoneg); 393 394 speed = cmd->base.speed; 395 396 /* If received a request for an unknown duplex, assume full*/ 397 if (duplex == DUPLEX_UNKNOWN) 398 duplex = DUPLEX_FULL; 399 400 if (IS_MF_SI(bp)) { 401 u32 part; 402 u32 line_speed = bp->link_vars.line_speed; 403 404 /* use 10G if no link detected */ 405 if (!line_speed) 406 line_speed = 10000; 407 408 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 409 DP(BNX2X_MSG_ETHTOOL, 410 "To set speed BC %X or higher is required, please upgrade BC\n", 411 REQ_BC_VER_4_SET_MF_BW); 412 return -EINVAL; 413 } 414 415 part = (speed * 100) / line_speed; 416 417 if (line_speed < speed || !part) { 418 DP(BNX2X_MSG_ETHTOOL, 419 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 420 return -EINVAL; 421 } 422 423 if (bp->state != BNX2X_STATE_OPEN) 424 /* store value for following "load" */ 425 bp->pending_max = part; 426 else 427 bnx2x_update_max_mf_config(bp, part); 428 429 return 0; 430 } 431 432 cfg_idx = bnx2x_get_link_cfg_idx(bp); 433 old_multi_phy_config = bp->link_params.multi_phy_config; 434 if (cmd->base.port != bnx2x_get_port_type(bp)) { 435 switch (cmd->base.port) { 436 case PORT_TP: 437 if (!(bp->port.supported[0] & SUPPORTED_TP || 438 bp->port.supported[1] & SUPPORTED_TP)) { 439 DP(BNX2X_MSG_ETHTOOL, 440 "Unsupported port type\n"); 441 return -EINVAL; 442 } 443 bp->link_params.multi_phy_config &= 444 ~PORT_HW_CFG_PHY_SELECTION_MASK; 445 if (bp->link_params.multi_phy_config & 446 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 447 bp->link_params.multi_phy_config |= 448 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 449 else 450 bp->link_params.multi_phy_config |= 451 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 452 break; 453 case PORT_FIBRE: 454 case PORT_DA: 455 case PORT_NONE: 456 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 457 bp->port.supported[1] & SUPPORTED_FIBRE)) { 458 DP(BNX2X_MSG_ETHTOOL, 459 "Unsupported port type\n"); 460 return -EINVAL; 461 } 462 bp->link_params.multi_phy_config &= 463 ~PORT_HW_CFG_PHY_SELECTION_MASK; 464 if (bp->link_params.multi_phy_config & 465 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 466 bp->link_params.multi_phy_config |= 467 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 468 else 469 bp->link_params.multi_phy_config |= 470 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 471 break; 472 default: 473 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 474 return -EINVAL; 475 } 476 } 477 /* Save new config in case command complete successfully */ 478 new_multi_phy_config = bp->link_params.multi_phy_config; 479 /* Get the new cfg_idx */ 480 cfg_idx = bnx2x_get_link_cfg_idx(bp); 481 /* Restore old config in case command failed */ 482 bp->link_params.multi_phy_config = old_multi_phy_config; 483 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 484 485 if (cmd->base.autoneg == AUTONEG_ENABLE) { 486 u32 an_supported_speed = bp->port.supported[cfg_idx]; 487 if (bp->link_params.phy[EXT_PHY1].type == 488 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 489 an_supported_speed |= (SUPPORTED_100baseT_Half | 490 SUPPORTED_100baseT_Full); 491 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 492 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 493 return -EINVAL; 494 } 495 496 /* advertise the requested speed and duplex if supported */ 497 if (advertising & ~an_supported_speed) { 498 DP(BNX2X_MSG_ETHTOOL, 499 "Advertisement parameters are not supported\n"); 500 return -EINVAL; 501 } 502 503 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 504 bp->link_params.req_duplex[cfg_idx] = duplex; 505 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 506 advertising); 507 if (advertising) { 508 509 bp->link_params.speed_cap_mask[cfg_idx] = 0; 510 if (advertising & ADVERTISED_10baseT_Half) { 511 bp->link_params.speed_cap_mask[cfg_idx] |= 512 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 513 } 514 if (advertising & ADVERTISED_10baseT_Full) 515 bp->link_params.speed_cap_mask[cfg_idx] |= 516 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 517 518 if (advertising & ADVERTISED_100baseT_Full) 519 bp->link_params.speed_cap_mask[cfg_idx] |= 520 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 521 522 if (advertising & ADVERTISED_100baseT_Half) { 523 bp->link_params.speed_cap_mask[cfg_idx] |= 524 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 525 } 526 if (advertising & ADVERTISED_1000baseT_Half) { 527 bp->link_params.speed_cap_mask[cfg_idx] |= 528 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 529 } 530 if (advertising & (ADVERTISED_1000baseT_Full | 531 ADVERTISED_1000baseKX_Full)) 532 bp->link_params.speed_cap_mask[cfg_idx] |= 533 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 534 535 if (advertising & (ADVERTISED_10000baseT_Full | 536 ADVERTISED_10000baseKX4_Full | 537 ADVERTISED_10000baseKR_Full)) 538 bp->link_params.speed_cap_mask[cfg_idx] |= 539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 540 541 if (advertising & ADVERTISED_20000baseKR2_Full) 542 bp->link_params.speed_cap_mask[cfg_idx] |= 543 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 544 } 545 } else { /* forced speed */ 546 /* advertise the requested speed and duplex if supported */ 547 switch (speed) { 548 case SPEED_10: 549 if (duplex == DUPLEX_FULL) { 550 if (!(bp->port.supported[cfg_idx] & 551 SUPPORTED_10baseT_Full)) { 552 DP(BNX2X_MSG_ETHTOOL, 553 "10M full not supported\n"); 554 return -EINVAL; 555 } 556 557 advertising = (ADVERTISED_10baseT_Full | 558 ADVERTISED_TP); 559 } else { 560 if (!(bp->port.supported[cfg_idx] & 561 SUPPORTED_10baseT_Half)) { 562 DP(BNX2X_MSG_ETHTOOL, 563 "10M half not supported\n"); 564 return -EINVAL; 565 } 566 567 advertising = (ADVERTISED_10baseT_Half | 568 ADVERTISED_TP); 569 } 570 break; 571 572 case SPEED_100: 573 if (duplex == DUPLEX_FULL) { 574 if (!(bp->port.supported[cfg_idx] & 575 SUPPORTED_100baseT_Full)) { 576 DP(BNX2X_MSG_ETHTOOL, 577 "100M full not supported\n"); 578 return -EINVAL; 579 } 580 581 advertising = (ADVERTISED_100baseT_Full | 582 ADVERTISED_TP); 583 } else { 584 if (!(bp->port.supported[cfg_idx] & 585 SUPPORTED_100baseT_Half)) { 586 DP(BNX2X_MSG_ETHTOOL, 587 "100M half not supported\n"); 588 return -EINVAL; 589 } 590 591 advertising = (ADVERTISED_100baseT_Half | 592 ADVERTISED_TP); 593 } 594 break; 595 596 case SPEED_1000: 597 if (duplex != DUPLEX_FULL) { 598 DP(BNX2X_MSG_ETHTOOL, 599 "1G half not supported\n"); 600 return -EINVAL; 601 } 602 603 if (bp->port.supported[cfg_idx] & 604 SUPPORTED_1000baseT_Full) { 605 advertising = (ADVERTISED_1000baseT_Full | 606 ADVERTISED_TP); 607 608 } else if (bp->port.supported[cfg_idx] & 609 SUPPORTED_1000baseKX_Full) { 610 advertising = ADVERTISED_1000baseKX_Full; 611 } else { 612 DP(BNX2X_MSG_ETHTOOL, 613 "1G full not supported\n"); 614 return -EINVAL; 615 } 616 617 break; 618 619 case SPEED_2500: 620 if (duplex != DUPLEX_FULL) { 621 DP(BNX2X_MSG_ETHTOOL, 622 "2.5G half not supported\n"); 623 return -EINVAL; 624 } 625 626 if (!(bp->port.supported[cfg_idx] 627 & SUPPORTED_2500baseX_Full)) { 628 DP(BNX2X_MSG_ETHTOOL, 629 "2.5G full not supported\n"); 630 return -EINVAL; 631 } 632 633 advertising = (ADVERTISED_2500baseX_Full | 634 ADVERTISED_TP); 635 break; 636 637 case SPEED_10000: 638 if (duplex != DUPLEX_FULL) { 639 DP(BNX2X_MSG_ETHTOOL, 640 "10G half not supported\n"); 641 return -EINVAL; 642 } 643 phy_idx = bnx2x_get_cur_phy_idx(bp); 644 if ((bp->port.supported[cfg_idx] & 645 SUPPORTED_10000baseT_Full) && 646 (bp->link_params.phy[phy_idx].media_type != 647 ETH_PHY_SFP_1G_FIBER)) { 648 advertising = (ADVERTISED_10000baseT_Full | 649 ADVERTISED_FIBRE); 650 } else if (bp->port.supported[cfg_idx] & 651 SUPPORTED_10000baseKR_Full) { 652 advertising = (ADVERTISED_10000baseKR_Full | 653 ADVERTISED_FIBRE); 654 } else { 655 DP(BNX2X_MSG_ETHTOOL, 656 "10G full not supported\n"); 657 return -EINVAL; 658 } 659 660 break; 661 662 default: 663 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 664 return -EINVAL; 665 } 666 667 bp->link_params.req_line_speed[cfg_idx] = speed; 668 bp->link_params.req_duplex[cfg_idx] = duplex; 669 bp->port.advertising[cfg_idx] = advertising; 670 } 671 672 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 673 " req_duplex %d advertising 0x%x\n", 674 bp->link_params.req_line_speed[cfg_idx], 675 bp->link_params.req_duplex[cfg_idx], 676 bp->port.advertising[cfg_idx]); 677 678 /* Set new config */ 679 bp->link_params.multi_phy_config = new_multi_phy_config; 680 if (netif_running(dev)) { 681 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 682 bnx2x_force_link_reset(bp); 683 bnx2x_link_set(bp); 684 } 685 686 return 0; 687 } 688 689 #define DUMP_ALL_PRESETS 0x1FFF 690 #define DUMP_MAX_PRESETS 13 691 692 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 693 { 694 if (CHIP_IS_E1(bp)) 695 return dump_num_registers[0][preset-1]; 696 else if (CHIP_IS_E1H(bp)) 697 return dump_num_registers[1][preset-1]; 698 else if (CHIP_IS_E2(bp)) 699 return dump_num_registers[2][preset-1]; 700 else if (CHIP_IS_E3A0(bp)) 701 return dump_num_registers[3][preset-1]; 702 else if (CHIP_IS_E3B0(bp)) 703 return dump_num_registers[4][preset-1]; 704 else 705 return 0; 706 } 707 708 static int __bnx2x_get_regs_len(struct bnx2x *bp) 709 { 710 u32 preset_idx; 711 int regdump_len = 0; 712 713 /* Calculate the total preset regs length */ 714 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 715 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 716 717 return regdump_len; 718 } 719 720 static int bnx2x_get_regs_len(struct net_device *dev) 721 { 722 struct bnx2x *bp = netdev_priv(dev); 723 int regdump_len = 0; 724 725 if (IS_VF(bp)) 726 return 0; 727 728 regdump_len = __bnx2x_get_regs_len(bp); 729 regdump_len *= 4; 730 regdump_len += sizeof(struct dump_header); 731 732 return regdump_len; 733 } 734 735 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 736 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 737 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 738 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 739 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 740 741 #define IS_REG_IN_PRESET(presets, idx) \ 742 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 743 744 /******* Paged registers info selectors ********/ 745 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 746 { 747 if (CHIP_IS_E2(bp)) 748 return page_vals_e2; 749 else if (CHIP_IS_E3(bp)) 750 return page_vals_e3; 751 else 752 return NULL; 753 } 754 755 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 756 { 757 if (CHIP_IS_E2(bp)) 758 return PAGE_MODE_VALUES_E2; 759 else if (CHIP_IS_E3(bp)) 760 return PAGE_MODE_VALUES_E3; 761 else 762 return 0; 763 } 764 765 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 766 { 767 if (CHIP_IS_E2(bp)) 768 return page_write_regs_e2; 769 else if (CHIP_IS_E3(bp)) 770 return page_write_regs_e3; 771 else 772 return NULL; 773 } 774 775 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 776 { 777 if (CHIP_IS_E2(bp)) 778 return PAGE_WRITE_REGS_E2; 779 else if (CHIP_IS_E3(bp)) 780 return PAGE_WRITE_REGS_E3; 781 else 782 return 0; 783 } 784 785 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 786 { 787 if (CHIP_IS_E2(bp)) 788 return page_read_regs_e2; 789 else if (CHIP_IS_E3(bp)) 790 return page_read_regs_e3; 791 else 792 return NULL; 793 } 794 795 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 796 { 797 if (CHIP_IS_E2(bp)) 798 return PAGE_READ_REGS_E2; 799 else if (CHIP_IS_E3(bp)) 800 return PAGE_READ_REGS_E3; 801 else 802 return 0; 803 } 804 805 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 806 const struct reg_addr *reg_info) 807 { 808 if (CHIP_IS_E1(bp)) 809 return IS_E1_REG(reg_info->chips); 810 else if (CHIP_IS_E1H(bp)) 811 return IS_E1H_REG(reg_info->chips); 812 else if (CHIP_IS_E2(bp)) 813 return IS_E2_REG(reg_info->chips); 814 else if (CHIP_IS_E3A0(bp)) 815 return IS_E3A0_REG(reg_info->chips); 816 else if (CHIP_IS_E3B0(bp)) 817 return IS_E3B0_REG(reg_info->chips); 818 else 819 return false; 820 } 821 822 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 823 const struct wreg_addr *wreg_info) 824 { 825 if (CHIP_IS_E1(bp)) 826 return IS_E1_REG(wreg_info->chips); 827 else if (CHIP_IS_E1H(bp)) 828 return IS_E1H_REG(wreg_info->chips); 829 else if (CHIP_IS_E2(bp)) 830 return IS_E2_REG(wreg_info->chips); 831 else if (CHIP_IS_E3A0(bp)) 832 return IS_E3A0_REG(wreg_info->chips); 833 else if (CHIP_IS_E3B0(bp)) 834 return IS_E3B0_REG(wreg_info->chips); 835 else 836 return false; 837 } 838 839 /** 840 * bnx2x_read_pages_regs - read "paged" registers 841 * 842 * @bp device handle 843 * @p output buffer 844 * 845 * Reads "paged" memories: memories that may only be read by first writing to a 846 * specific address ("write address") and then reading from a specific address 847 * ("read address"). There may be more than one write address per "page" and 848 * more than one read address per write address. 849 */ 850 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 851 { 852 u32 i, j, k, n; 853 854 /* addresses of the paged registers */ 855 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 856 /* number of paged registers */ 857 int num_pages = __bnx2x_get_page_reg_num(bp); 858 /* write addresses */ 859 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 860 /* number of write addresses */ 861 int write_num = __bnx2x_get_page_write_num(bp); 862 /* read addresses info */ 863 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 864 /* number of read addresses */ 865 int read_num = __bnx2x_get_page_read_num(bp); 866 u32 addr, size; 867 868 for (i = 0; i < num_pages; i++) { 869 for (j = 0; j < write_num; j++) { 870 REG_WR(bp, write_addr[j], page_addr[i]); 871 872 for (k = 0; k < read_num; k++) { 873 if (IS_REG_IN_PRESET(read_addr[k].presets, 874 preset)) { 875 size = read_addr[k].size; 876 for (n = 0; n < size; n++) { 877 addr = read_addr[k].addr + n*4; 878 *p++ = REG_RD(bp, addr); 879 } 880 } 881 } 882 } 883 } 884 } 885 886 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 887 { 888 u32 i, j, addr; 889 const struct wreg_addr *wreg_addr_p = NULL; 890 891 if (CHIP_IS_E1(bp)) 892 wreg_addr_p = &wreg_addr_e1; 893 else if (CHIP_IS_E1H(bp)) 894 wreg_addr_p = &wreg_addr_e1h; 895 else if (CHIP_IS_E2(bp)) 896 wreg_addr_p = &wreg_addr_e2; 897 else if (CHIP_IS_E3A0(bp)) 898 wreg_addr_p = &wreg_addr_e3; 899 else if (CHIP_IS_E3B0(bp)) 900 wreg_addr_p = &wreg_addr_e3b0; 901 902 /* Read the idle_chk registers */ 903 for (i = 0; i < IDLE_REGS_COUNT; i++) { 904 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 905 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 906 for (j = 0; j < idle_reg_addrs[i].size; j++) 907 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 908 } 909 } 910 911 /* Read the regular registers */ 912 for (i = 0; i < REGS_COUNT; i++) { 913 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 914 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 915 for (j = 0; j < reg_addrs[i].size; j++) 916 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 917 } 918 } 919 920 /* Read the CAM registers */ 921 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 922 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 923 for (i = 0; i < wreg_addr_p->size; i++) { 924 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 925 926 /* In case of wreg_addr register, read additional 927 registers from read_regs array 928 */ 929 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 930 addr = *(wreg_addr_p->read_regs); 931 *p++ = REG_RD(bp, addr + j*4); 932 } 933 } 934 } 935 936 /* Paged registers are supported in E2 & E3 only */ 937 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 938 /* Read "paged" registers */ 939 bnx2x_read_pages_regs(bp, p, preset); 940 } 941 942 return 0; 943 } 944 945 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 946 { 947 u32 preset_idx; 948 949 /* Read all registers, by reading all preset registers */ 950 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 951 /* Skip presets with IOR */ 952 if ((preset_idx == 2) || 953 (preset_idx == 5) || 954 (preset_idx == 8) || 955 (preset_idx == 11)) 956 continue; 957 __bnx2x_get_preset_regs(bp, p, preset_idx); 958 p += __bnx2x_get_preset_regs_len(bp, preset_idx); 959 } 960 } 961 962 static void bnx2x_get_regs(struct net_device *dev, 963 struct ethtool_regs *regs, void *_p) 964 { 965 u32 *p = _p; 966 struct bnx2x *bp = netdev_priv(dev); 967 struct dump_header dump_hdr = {0}; 968 969 regs->version = 2; 970 memset(p, 0, regs->len); 971 972 if (!netif_running(bp->dev)) 973 return; 974 975 /* Disable parity attentions as long as following dump may 976 * cause false alarms by reading never written registers. We 977 * will re-enable parity attentions right after the dump. 978 */ 979 980 bnx2x_disable_blocks_parity(bp); 981 982 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 983 dump_hdr.preset = DUMP_ALL_PRESETS; 984 dump_hdr.version = BNX2X_DUMP_VERSION; 985 986 /* dump_meta_data presents OR of CHIP and PATH. */ 987 if (CHIP_IS_E1(bp)) { 988 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 989 } else if (CHIP_IS_E1H(bp)) { 990 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 991 } else if (CHIP_IS_E2(bp)) { 992 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 993 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 994 } else if (CHIP_IS_E3A0(bp)) { 995 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 996 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 997 } else if (CHIP_IS_E3B0(bp)) { 998 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 999 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1000 } 1001 1002 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1003 p += dump_hdr.header_size + 1; 1004 1005 /* This isn't really an error, but since attention handling is going 1006 * to print the GRC timeouts using this macro, we use the same. 1007 */ 1008 BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n"); 1009 1010 /* Actually read the registers */ 1011 __bnx2x_get_regs(bp, p); 1012 1013 /* Re-enable parity attentions */ 1014 bnx2x_clear_blocks_parity(bp); 1015 bnx2x_enable_blocks_parity(bp); 1016 } 1017 1018 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 1019 { 1020 struct bnx2x *bp = netdev_priv(dev); 1021 int regdump_len = 0; 1022 1023 regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 1024 regdump_len *= 4; 1025 regdump_len += sizeof(struct dump_header); 1026 1027 return regdump_len; 1028 } 1029 1030 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 1031 { 1032 struct bnx2x *bp = netdev_priv(dev); 1033 1034 /* Use the ethtool_dump "flag" field as the dump preset index */ 1035 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 1036 return -EINVAL; 1037 1038 bp->dump_preset_idx = val->flag; 1039 return 0; 1040 } 1041 1042 static int bnx2x_get_dump_flag(struct net_device *dev, 1043 struct ethtool_dump *dump) 1044 { 1045 struct bnx2x *bp = netdev_priv(dev); 1046 1047 dump->version = BNX2X_DUMP_VERSION; 1048 dump->flag = bp->dump_preset_idx; 1049 /* Calculate the requested preset idx length */ 1050 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 1051 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 1052 bp->dump_preset_idx, dump->len); 1053 return 0; 1054 } 1055 1056 static int bnx2x_get_dump_data(struct net_device *dev, 1057 struct ethtool_dump *dump, 1058 void *buffer) 1059 { 1060 u32 *p = buffer; 1061 struct bnx2x *bp = netdev_priv(dev); 1062 struct dump_header dump_hdr = {0}; 1063 1064 /* Disable parity attentions as long as following dump may 1065 * cause false alarms by reading never written registers. We 1066 * will re-enable parity attentions right after the dump. 1067 */ 1068 1069 bnx2x_disable_blocks_parity(bp); 1070 1071 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 1072 dump_hdr.preset = bp->dump_preset_idx; 1073 dump_hdr.version = BNX2X_DUMP_VERSION; 1074 1075 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 1076 1077 /* dump_meta_data presents OR of CHIP and PATH. */ 1078 if (CHIP_IS_E1(bp)) { 1079 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 1080 } else if (CHIP_IS_E1H(bp)) { 1081 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 1082 } else if (CHIP_IS_E2(bp)) { 1083 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 1084 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1085 } else if (CHIP_IS_E3A0(bp)) { 1086 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 1087 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1088 } else if (CHIP_IS_E3B0(bp)) { 1089 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 1090 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1091 } 1092 1093 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1094 p += dump_hdr.header_size + 1; 1095 1096 /* Actually read the registers */ 1097 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1098 1099 /* Re-enable parity attentions */ 1100 bnx2x_clear_blocks_parity(bp); 1101 bnx2x_enable_blocks_parity(bp); 1102 1103 return 0; 1104 } 1105 1106 static void bnx2x_get_drvinfo(struct net_device *dev, 1107 struct ethtool_drvinfo *info) 1108 { 1109 struct bnx2x *bp = netdev_priv(dev); 1110 char version[ETHTOOL_FWVERS_LEN]; 1111 int ext_dev_info_offset; 1112 u32 mbi; 1113 1114 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1115 1116 if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) { 1117 ext_dev_info_offset = SHMEM2_RD(bp, 1118 extended_dev_info_shared_addr); 1119 mbi = REG_RD(bp, ext_dev_info_offset + 1120 offsetof(struct extended_dev_info_shared_cfg, 1121 mbi_version)); 1122 if (mbi) { 1123 memset(version, 0, sizeof(version)); 1124 snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ", 1125 (mbi & 0xff000000) >> 24, 1126 (mbi & 0x00ff0000) >> 16, 1127 (mbi & 0x0000ff00) >> 8); 1128 strlcpy(info->fw_version, version, 1129 sizeof(info->fw_version)); 1130 } 1131 } 1132 1133 memset(version, 0, sizeof(version)); 1134 bnx2x_fill_fw_str(bp, version, ETHTOOL_FWVERS_LEN); 1135 strlcat(info->fw_version, version, sizeof(info->fw_version)); 1136 1137 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1138 } 1139 1140 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1141 { 1142 struct bnx2x *bp = netdev_priv(dev); 1143 1144 if (bp->flags & NO_WOL_FLAG) { 1145 wol->supported = 0; 1146 wol->wolopts = 0; 1147 } else { 1148 wol->supported = WAKE_MAGIC; 1149 if (bp->wol) 1150 wol->wolopts = WAKE_MAGIC; 1151 else 1152 wol->wolopts = 0; 1153 } 1154 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1155 } 1156 1157 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1158 { 1159 struct bnx2x *bp = netdev_priv(dev); 1160 1161 if (wol->wolopts & ~WAKE_MAGIC) { 1162 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1163 return -EINVAL; 1164 } 1165 1166 if (wol->wolopts & WAKE_MAGIC) { 1167 if (bp->flags & NO_WOL_FLAG) { 1168 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1169 return -EINVAL; 1170 } 1171 bp->wol = 1; 1172 } else 1173 bp->wol = 0; 1174 1175 if (SHMEM2_HAS(bp, curr_cfg)) 1176 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1177 1178 return 0; 1179 } 1180 1181 static u32 bnx2x_get_msglevel(struct net_device *dev) 1182 { 1183 struct bnx2x *bp = netdev_priv(dev); 1184 1185 return bp->msg_enable; 1186 } 1187 1188 static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1189 { 1190 struct bnx2x *bp = netdev_priv(dev); 1191 1192 if (capable(CAP_NET_ADMIN)) { 1193 /* dump MCP trace */ 1194 if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1195 bnx2x_fw_dump_lvl(bp, KERN_INFO); 1196 bp->msg_enable = level; 1197 } 1198 } 1199 1200 static int bnx2x_nway_reset(struct net_device *dev) 1201 { 1202 struct bnx2x *bp = netdev_priv(dev); 1203 1204 if (!bp->port.pmf) 1205 return 0; 1206 1207 if (netif_running(dev)) { 1208 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1209 bnx2x_force_link_reset(bp); 1210 bnx2x_link_set(bp); 1211 } 1212 1213 return 0; 1214 } 1215 1216 static u32 bnx2x_get_link(struct net_device *dev) 1217 { 1218 struct bnx2x *bp = netdev_priv(dev); 1219 1220 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1221 return 0; 1222 1223 if (IS_VF(bp)) 1224 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1225 &bp->vf_link_vars.link_report_flags); 1226 1227 return bp->link_vars.link_up; 1228 } 1229 1230 static int bnx2x_get_eeprom_len(struct net_device *dev) 1231 { 1232 struct bnx2x *bp = netdev_priv(dev); 1233 1234 return bp->common.flash_size; 1235 } 1236 1237 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1238 * had we done things the other way around, if two pfs from the same port would 1239 * attempt to access nvram at the same time, we could run into a scenario such 1240 * as: 1241 * pf A takes the port lock. 1242 * pf B succeeds in taking the same lock since they are from the same port. 1243 * pf A takes the per pf misc lock. Performs eeprom access. 1244 * pf A finishes. Unlocks the per pf misc lock. 1245 * Pf B takes the lock and proceeds to perform it's own access. 1246 * pf A unlocks the per port lock, while pf B is still working (!). 1247 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1248 * access corrupted by pf B) 1249 */ 1250 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1251 { 1252 int port = BP_PORT(bp); 1253 int count, i; 1254 u32 val; 1255 1256 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1257 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1258 1259 /* adjust timeout for emulation/FPGA */ 1260 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1261 if (CHIP_REV_IS_SLOW(bp)) 1262 count *= 100; 1263 1264 /* request access to nvram interface */ 1265 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1266 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1267 1268 for (i = 0; i < count*10; i++) { 1269 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1270 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1271 break; 1272 1273 udelay(5); 1274 } 1275 1276 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1277 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1278 "cannot get access to nvram interface\n"); 1279 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1280 return -EBUSY; 1281 } 1282 1283 return 0; 1284 } 1285 1286 static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1287 { 1288 int port = BP_PORT(bp); 1289 int count, i; 1290 u32 val; 1291 1292 /* adjust timeout for emulation/FPGA */ 1293 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1294 if (CHIP_REV_IS_SLOW(bp)) 1295 count *= 100; 1296 1297 /* relinquish nvram interface */ 1298 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1299 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1300 1301 for (i = 0; i < count*10; i++) { 1302 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1303 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1304 break; 1305 1306 udelay(5); 1307 } 1308 1309 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1310 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1311 "cannot free access to nvram interface\n"); 1312 return -EBUSY; 1313 } 1314 1315 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1316 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1317 return 0; 1318 } 1319 1320 static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1321 { 1322 u32 val; 1323 1324 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1325 1326 /* enable both bits, even on read */ 1327 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1328 (val | MCPR_NVM_ACCESS_ENABLE_EN | 1329 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1330 } 1331 1332 static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1333 { 1334 u32 val; 1335 1336 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1337 1338 /* disable both bits, even after read */ 1339 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1340 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1341 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1342 } 1343 1344 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1345 u32 cmd_flags) 1346 { 1347 int count, i, rc; 1348 u32 val; 1349 1350 /* build the command word */ 1351 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1352 1353 /* need to clear DONE bit separately */ 1354 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1355 1356 /* address of the NVRAM to read from */ 1357 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1358 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1359 1360 /* issue a read command */ 1361 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1362 1363 /* adjust timeout for emulation/FPGA */ 1364 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1365 if (CHIP_REV_IS_SLOW(bp)) 1366 count *= 100; 1367 1368 /* wait for completion */ 1369 *ret_val = 0; 1370 rc = -EBUSY; 1371 for (i = 0; i < count; i++) { 1372 udelay(5); 1373 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1374 1375 if (val & MCPR_NVM_COMMAND_DONE) { 1376 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1377 /* we read nvram data in cpu order 1378 * but ethtool sees it as an array of bytes 1379 * converting to big-endian will do the work 1380 */ 1381 *ret_val = cpu_to_be32(val); 1382 rc = 0; 1383 break; 1384 } 1385 } 1386 if (rc == -EBUSY) 1387 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1388 "nvram read timeout expired\n"); 1389 return rc; 1390 } 1391 1392 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1393 int buf_size) 1394 { 1395 int rc; 1396 u32 cmd_flags; 1397 __be32 val; 1398 1399 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1400 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1401 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1402 offset, buf_size); 1403 return -EINVAL; 1404 } 1405 1406 if (offset + buf_size > bp->common.flash_size) { 1407 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1408 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1409 offset, buf_size, bp->common.flash_size); 1410 return -EINVAL; 1411 } 1412 1413 /* request access to nvram interface */ 1414 rc = bnx2x_acquire_nvram_lock(bp); 1415 if (rc) 1416 return rc; 1417 1418 /* enable access to nvram interface */ 1419 bnx2x_enable_nvram_access(bp); 1420 1421 /* read the first word(s) */ 1422 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1423 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1424 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1425 memcpy(ret_buf, &val, 4); 1426 1427 /* advance to the next dword */ 1428 offset += sizeof(u32); 1429 ret_buf += sizeof(u32); 1430 buf_size -= sizeof(u32); 1431 cmd_flags = 0; 1432 } 1433 1434 if (rc == 0) { 1435 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1436 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1437 memcpy(ret_buf, &val, 4); 1438 } 1439 1440 /* disable access to nvram interface */ 1441 bnx2x_disable_nvram_access(bp); 1442 bnx2x_release_nvram_lock(bp); 1443 1444 return rc; 1445 } 1446 1447 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 1448 int buf_size) 1449 { 1450 int rc; 1451 1452 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 1453 1454 if (!rc) { 1455 __be32 *be = (__be32 *)buf; 1456 1457 while ((buf_size -= 4) >= 0) 1458 *buf++ = be32_to_cpu(*be++); 1459 } 1460 1461 return rc; 1462 } 1463 1464 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 1465 { 1466 int rc = 1; 1467 u16 pm = 0; 1468 struct net_device *dev = pci_get_drvdata(bp->pdev); 1469 1470 if (bp->pdev->pm_cap) 1471 rc = pci_read_config_word(bp->pdev, 1472 bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 1473 1474 if ((rc && !netif_running(dev)) || 1475 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 1476 return false; 1477 1478 return true; 1479 } 1480 1481 static int bnx2x_get_eeprom(struct net_device *dev, 1482 struct ethtool_eeprom *eeprom, u8 *eebuf) 1483 { 1484 struct bnx2x *bp = netdev_priv(dev); 1485 1486 if (!bnx2x_is_nvm_accessible(bp)) { 1487 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1488 "cannot access eeprom when the interface is down\n"); 1489 return -EAGAIN; 1490 } 1491 1492 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1493 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1494 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1495 eeprom->len, eeprom->len); 1496 1497 /* parameters already validated in ethtool_get_eeprom */ 1498 1499 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1500 } 1501 1502 static int bnx2x_get_module_eeprom(struct net_device *dev, 1503 struct ethtool_eeprom *ee, 1504 u8 *data) 1505 { 1506 struct bnx2x *bp = netdev_priv(dev); 1507 int rc = -EINVAL, phy_idx; 1508 u8 *user_data = data; 1509 unsigned int start_addr = ee->offset, xfer_size = 0; 1510 1511 if (!bnx2x_is_nvm_accessible(bp)) { 1512 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1513 "cannot access eeprom when the interface is down\n"); 1514 return -EAGAIN; 1515 } 1516 1517 phy_idx = bnx2x_get_cur_phy_idx(bp); 1518 1519 /* Read A0 section */ 1520 if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1521 /* Limit transfer size to the A0 section boundary */ 1522 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1523 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1524 else 1525 xfer_size = ee->len; 1526 bnx2x_acquire_phy_lock(bp); 1527 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1528 &bp->link_params, 1529 I2C_DEV_ADDR_A0, 1530 start_addr, 1531 xfer_size, 1532 user_data); 1533 bnx2x_release_phy_lock(bp); 1534 if (rc) { 1535 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1536 1537 return -EINVAL; 1538 } 1539 user_data += xfer_size; 1540 start_addr += xfer_size; 1541 } 1542 1543 /* Read A2 section */ 1544 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1545 (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1546 xfer_size = ee->len - xfer_size; 1547 /* Limit transfer size to the A2 section boundary */ 1548 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1549 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1550 start_addr -= ETH_MODULE_SFF_8079_LEN; 1551 bnx2x_acquire_phy_lock(bp); 1552 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1553 &bp->link_params, 1554 I2C_DEV_ADDR_A2, 1555 start_addr, 1556 xfer_size, 1557 user_data); 1558 bnx2x_release_phy_lock(bp); 1559 if (rc) { 1560 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1561 return -EINVAL; 1562 } 1563 } 1564 return rc; 1565 } 1566 1567 static int bnx2x_get_module_info(struct net_device *dev, 1568 struct ethtool_modinfo *modinfo) 1569 { 1570 struct bnx2x *bp = netdev_priv(dev); 1571 int phy_idx, rc; 1572 u8 sff8472_comp, diag_type; 1573 1574 if (!bnx2x_is_nvm_accessible(bp)) { 1575 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1576 "cannot access eeprom when the interface is down\n"); 1577 return -EAGAIN; 1578 } 1579 phy_idx = bnx2x_get_cur_phy_idx(bp); 1580 bnx2x_acquire_phy_lock(bp); 1581 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1582 &bp->link_params, 1583 I2C_DEV_ADDR_A0, 1584 SFP_EEPROM_SFF_8472_COMP_ADDR, 1585 SFP_EEPROM_SFF_8472_COMP_SIZE, 1586 &sff8472_comp); 1587 bnx2x_release_phy_lock(bp); 1588 if (rc) { 1589 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1590 return -EINVAL; 1591 } 1592 1593 bnx2x_acquire_phy_lock(bp); 1594 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1595 &bp->link_params, 1596 I2C_DEV_ADDR_A0, 1597 SFP_EEPROM_DIAG_TYPE_ADDR, 1598 SFP_EEPROM_DIAG_TYPE_SIZE, 1599 &diag_type); 1600 bnx2x_release_phy_lock(bp); 1601 if (rc) { 1602 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1603 return -EINVAL; 1604 } 1605 1606 if (!sff8472_comp || 1607 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) || 1608 !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) { 1609 modinfo->type = ETH_MODULE_SFF_8079; 1610 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1611 } else { 1612 modinfo->type = ETH_MODULE_SFF_8472; 1613 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1614 } 1615 return 0; 1616 } 1617 1618 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1619 u32 cmd_flags) 1620 { 1621 int count, i, rc; 1622 1623 /* build the command word */ 1624 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1625 1626 /* need to clear DONE bit separately */ 1627 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1628 1629 /* write the data */ 1630 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1631 1632 /* address of the NVRAM to write to */ 1633 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1634 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1635 1636 /* issue the write command */ 1637 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1638 1639 /* adjust timeout for emulation/FPGA */ 1640 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1641 if (CHIP_REV_IS_SLOW(bp)) 1642 count *= 100; 1643 1644 /* wait for completion */ 1645 rc = -EBUSY; 1646 for (i = 0; i < count; i++) { 1647 udelay(5); 1648 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1649 if (val & MCPR_NVM_COMMAND_DONE) { 1650 rc = 0; 1651 break; 1652 } 1653 } 1654 1655 if (rc == -EBUSY) 1656 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1657 "nvram write timeout expired\n"); 1658 return rc; 1659 } 1660 1661 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1662 1663 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1664 int buf_size) 1665 { 1666 int rc; 1667 u32 cmd_flags, align_offset, val; 1668 __be32 val_be; 1669 1670 if (offset + buf_size > bp->common.flash_size) { 1671 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1672 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1673 offset, buf_size, bp->common.flash_size); 1674 return -EINVAL; 1675 } 1676 1677 /* request access to nvram interface */ 1678 rc = bnx2x_acquire_nvram_lock(bp); 1679 if (rc) 1680 return rc; 1681 1682 /* enable access to nvram interface */ 1683 bnx2x_enable_nvram_access(bp); 1684 1685 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1686 align_offset = (offset & ~0x03); 1687 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1688 1689 if (rc == 0) { 1690 /* nvram data is returned as an array of bytes 1691 * convert it back to cpu order 1692 */ 1693 val = be32_to_cpu(val_be); 1694 1695 val &= ~le32_to_cpu((__force __le32) 1696 (0xff << BYTE_OFFSET(offset))); 1697 val |= le32_to_cpu((__force __le32) 1698 (*data_buf << BYTE_OFFSET(offset))); 1699 1700 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1701 cmd_flags); 1702 } 1703 1704 /* disable access to nvram interface */ 1705 bnx2x_disable_nvram_access(bp); 1706 bnx2x_release_nvram_lock(bp); 1707 1708 return rc; 1709 } 1710 1711 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1712 int buf_size) 1713 { 1714 int rc; 1715 u32 cmd_flags; 1716 u32 val; 1717 u32 written_so_far; 1718 1719 if (buf_size == 1) /* ethtool */ 1720 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1721 1722 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1723 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1724 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1725 offset, buf_size); 1726 return -EINVAL; 1727 } 1728 1729 if (offset + buf_size > bp->common.flash_size) { 1730 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1731 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1732 offset, buf_size, bp->common.flash_size); 1733 return -EINVAL; 1734 } 1735 1736 /* request access to nvram interface */ 1737 rc = bnx2x_acquire_nvram_lock(bp); 1738 if (rc) 1739 return rc; 1740 1741 /* enable access to nvram interface */ 1742 bnx2x_enable_nvram_access(bp); 1743 1744 written_so_far = 0; 1745 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1746 while ((written_so_far < buf_size) && (rc == 0)) { 1747 if (written_so_far == (buf_size - sizeof(u32))) 1748 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1749 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1750 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1751 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1752 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1753 1754 memcpy(&val, data_buf, 4); 1755 1756 /* Notice unlike bnx2x_nvram_read_dword() this will not 1757 * change val using be32_to_cpu(), which causes data to flip 1758 * if the eeprom is read and then written back. This is due 1759 * to tools utilizing this functionality that would break 1760 * if this would be resolved. 1761 */ 1762 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1763 1764 /* advance to the next dword */ 1765 offset += sizeof(u32); 1766 data_buf += sizeof(u32); 1767 written_so_far += sizeof(u32); 1768 1769 /* At end of each 4Kb page, release nvram lock to allow MFW 1770 * chance to take it for its own use. 1771 */ 1772 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) && 1773 (written_so_far < buf_size)) { 1774 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1775 "Releasing NVM lock after offset 0x%x\n", 1776 (u32)(offset - sizeof(u32))); 1777 bnx2x_release_nvram_lock(bp); 1778 usleep_range(1000, 2000); 1779 rc = bnx2x_acquire_nvram_lock(bp); 1780 if (rc) 1781 return rc; 1782 } 1783 1784 cmd_flags = 0; 1785 } 1786 1787 /* disable access to nvram interface */ 1788 bnx2x_disable_nvram_access(bp); 1789 bnx2x_release_nvram_lock(bp); 1790 1791 return rc; 1792 } 1793 1794 static int bnx2x_set_eeprom(struct net_device *dev, 1795 struct ethtool_eeprom *eeprom, u8 *eebuf) 1796 { 1797 struct bnx2x *bp = netdev_priv(dev); 1798 int port = BP_PORT(bp); 1799 int rc = 0; 1800 u32 ext_phy_config; 1801 1802 if (!bnx2x_is_nvm_accessible(bp)) { 1803 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1804 "cannot access eeprom when the interface is down\n"); 1805 return -EAGAIN; 1806 } 1807 1808 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1809 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1810 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1811 eeprom->len, eeprom->len); 1812 1813 /* parameters already validated in ethtool_set_eeprom */ 1814 1815 /* PHY eeprom can be accessed only by the PMF */ 1816 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1817 !bp->port.pmf) { 1818 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1819 "wrong magic or interface is not pmf\n"); 1820 return -EINVAL; 1821 } 1822 1823 ext_phy_config = 1824 SHMEM_RD(bp, 1825 dev_info.port_hw_config[port].external_phy_config); 1826 1827 if (eeprom->magic == 0x50485950) { 1828 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1829 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1830 1831 bnx2x_acquire_phy_lock(bp); 1832 rc |= bnx2x_link_reset(&bp->link_params, 1833 &bp->link_vars, 0); 1834 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1835 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1836 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1837 MISC_REGISTERS_GPIO_HIGH, port); 1838 bnx2x_release_phy_lock(bp); 1839 bnx2x_link_report(bp); 1840 1841 } else if (eeprom->magic == 0x50485952) { 1842 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1843 if (bp->state == BNX2X_STATE_OPEN) { 1844 bnx2x_acquire_phy_lock(bp); 1845 rc |= bnx2x_link_reset(&bp->link_params, 1846 &bp->link_vars, 1); 1847 1848 rc |= bnx2x_phy_init(&bp->link_params, 1849 &bp->link_vars); 1850 bnx2x_release_phy_lock(bp); 1851 bnx2x_calc_fc_adv(bp); 1852 } 1853 } else if (eeprom->magic == 0x53985943) { 1854 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1855 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1856 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1857 1858 /* DSP Remove Download Mode */ 1859 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1860 MISC_REGISTERS_GPIO_LOW, port); 1861 1862 bnx2x_acquire_phy_lock(bp); 1863 1864 bnx2x_sfx7101_sp_sw_reset(bp, 1865 &bp->link_params.phy[EXT_PHY1]); 1866 1867 /* wait 0.5 sec to allow it to run */ 1868 msleep(500); 1869 bnx2x_ext_phy_hw_reset(bp, port); 1870 msleep(500); 1871 bnx2x_release_phy_lock(bp); 1872 } 1873 } else 1874 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1875 1876 return rc; 1877 } 1878 1879 static int bnx2x_get_coalesce(struct net_device *dev, 1880 struct ethtool_coalesce *coal) 1881 { 1882 struct bnx2x *bp = netdev_priv(dev); 1883 1884 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1885 1886 coal->rx_coalesce_usecs = bp->rx_ticks; 1887 coal->tx_coalesce_usecs = bp->tx_ticks; 1888 1889 return 0; 1890 } 1891 1892 static int bnx2x_set_coalesce(struct net_device *dev, 1893 struct ethtool_coalesce *coal) 1894 { 1895 struct bnx2x *bp = netdev_priv(dev); 1896 1897 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1898 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1899 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1900 1901 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1902 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1903 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1904 1905 if (netif_running(dev)) 1906 bnx2x_update_coalesce(bp); 1907 1908 return 0; 1909 } 1910 1911 static void bnx2x_get_ringparam(struct net_device *dev, 1912 struct ethtool_ringparam *ering) 1913 { 1914 struct bnx2x *bp = netdev_priv(dev); 1915 1916 ering->rx_max_pending = MAX_RX_AVAIL; 1917 1918 /* If size isn't already set, we give an estimation of the number 1919 * of buffers we'll have. We're neglecting some possible conditions 1920 * [we couldn't know for certain at this point if number of queues 1921 * might shrink] but the number would be correct for the likely 1922 * scenario. 1923 */ 1924 if (bp->rx_ring_size) 1925 ering->rx_pending = bp->rx_ring_size; 1926 else if (BNX2X_NUM_RX_QUEUES(bp)) 1927 ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp); 1928 else 1929 ering->rx_pending = MAX_RX_AVAIL; 1930 1931 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1932 ering->tx_pending = bp->tx_ring_size; 1933 } 1934 1935 static int bnx2x_set_ringparam(struct net_device *dev, 1936 struct ethtool_ringparam *ering) 1937 { 1938 struct bnx2x *bp = netdev_priv(dev); 1939 1940 DP(BNX2X_MSG_ETHTOOL, 1941 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 1942 ering->rx_pending, ering->tx_pending); 1943 1944 if (pci_num_vf(bp->pdev)) { 1945 DP(BNX2X_MSG_IOV, 1946 "VFs are enabled, can not change ring parameters\n"); 1947 return -EPERM; 1948 } 1949 1950 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1951 DP(BNX2X_MSG_ETHTOOL, 1952 "Handling parity error recovery. Try again later\n"); 1953 return -EAGAIN; 1954 } 1955 1956 if ((ering->rx_pending > MAX_RX_AVAIL) || 1957 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1958 MIN_RX_SIZE_TPA)) || 1959 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 1960 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 1961 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1962 return -EINVAL; 1963 } 1964 1965 bp->rx_ring_size = ering->rx_pending; 1966 bp->tx_ring_size = ering->tx_pending; 1967 1968 return bnx2x_reload_if_running(dev); 1969 } 1970 1971 static void bnx2x_get_pauseparam(struct net_device *dev, 1972 struct ethtool_pauseparam *epause) 1973 { 1974 struct bnx2x *bp = netdev_priv(dev); 1975 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1976 int cfg_reg; 1977 1978 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1979 BNX2X_FLOW_CTRL_AUTO); 1980 1981 if (!epause->autoneg) 1982 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1983 else 1984 cfg_reg = bp->link_params.req_fc_auto_adv; 1985 1986 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1987 BNX2X_FLOW_CTRL_RX); 1988 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1989 BNX2X_FLOW_CTRL_TX); 1990 1991 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1992 " autoneg %d rx_pause %d tx_pause %d\n", 1993 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1994 } 1995 1996 static int bnx2x_set_pauseparam(struct net_device *dev, 1997 struct ethtool_pauseparam *epause) 1998 { 1999 struct bnx2x *bp = netdev_priv(dev); 2000 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2001 if (IS_MF(bp)) 2002 return 0; 2003 2004 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 2005 " autoneg %d rx_pause %d tx_pause %d\n", 2006 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 2007 2008 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 2009 2010 if (epause->rx_pause) 2011 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 2012 2013 if (epause->tx_pause) 2014 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 2015 2016 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 2017 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 2018 2019 if (epause->autoneg) { 2020 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 2021 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 2022 return -EINVAL; 2023 } 2024 2025 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 2026 bp->link_params.req_flow_ctrl[cfg_idx] = 2027 BNX2X_FLOW_CTRL_AUTO; 2028 } 2029 bp->link_params.req_fc_auto_adv = 0; 2030 if (epause->rx_pause) 2031 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 2032 2033 if (epause->tx_pause) 2034 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 2035 2036 if (!bp->link_params.req_fc_auto_adv) 2037 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 2038 } 2039 2040 DP(BNX2X_MSG_ETHTOOL, 2041 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 2042 2043 if (netif_running(dev)) { 2044 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2045 bnx2x_force_link_reset(bp); 2046 bnx2x_link_set(bp); 2047 } 2048 2049 return 0; 2050 } 2051 2052 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 2053 "register_test (offline) ", 2054 "memory_test (offline) ", 2055 "int_loopback_test (offline)", 2056 "ext_loopback_test (offline)", 2057 "nvram_test (online) ", 2058 "interrupt_test (online) ", 2059 "link_test (online) " 2060 }; 2061 2062 enum { 2063 BNX2X_PRI_FLAG_ISCSI, 2064 BNX2X_PRI_FLAG_FCOE, 2065 BNX2X_PRI_FLAG_STORAGE, 2066 BNX2X_PRI_FLAG_LEN, 2067 }; 2068 2069 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 2070 "iSCSI offload support", 2071 "FCoE offload support", 2072 "Storage only interface" 2073 }; 2074 2075 static u32 bnx2x_eee_to_adv(u32 eee_adv) 2076 { 2077 u32 modes = 0; 2078 2079 if (eee_adv & SHMEM_EEE_100M_ADV) 2080 modes |= ADVERTISED_100baseT_Full; 2081 if (eee_adv & SHMEM_EEE_1G_ADV) 2082 modes |= ADVERTISED_1000baseT_Full; 2083 if (eee_adv & SHMEM_EEE_10G_ADV) 2084 modes |= ADVERTISED_10000baseT_Full; 2085 2086 return modes; 2087 } 2088 2089 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2090 { 2091 u32 eee_adv = 0; 2092 if (modes & ADVERTISED_100baseT_Full) 2093 eee_adv |= SHMEM_EEE_100M_ADV; 2094 if (modes & ADVERTISED_1000baseT_Full) 2095 eee_adv |= SHMEM_EEE_1G_ADV; 2096 if (modes & ADVERTISED_10000baseT_Full) 2097 eee_adv |= SHMEM_EEE_10G_ADV; 2098 2099 return eee_adv << shift; 2100 } 2101 2102 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2103 { 2104 struct bnx2x *bp = netdev_priv(dev); 2105 u32 eee_cfg; 2106 2107 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2108 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2109 return -EOPNOTSUPP; 2110 } 2111 2112 eee_cfg = bp->link_vars.eee_status; 2113 2114 edata->supported = 2115 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2116 SHMEM_EEE_SUPPORTED_SHIFT); 2117 2118 edata->advertised = 2119 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2120 SHMEM_EEE_ADV_STATUS_SHIFT); 2121 edata->lp_advertised = 2122 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2123 SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2124 2125 /* SHMEM value is in 16u units --> Convert to 1u units. */ 2126 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2127 2128 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2129 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2130 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2131 2132 return 0; 2133 } 2134 2135 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2136 { 2137 struct bnx2x *bp = netdev_priv(dev); 2138 u32 eee_cfg; 2139 u32 advertised; 2140 2141 if (IS_MF(bp)) 2142 return 0; 2143 2144 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2145 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2146 return -EOPNOTSUPP; 2147 } 2148 2149 eee_cfg = bp->link_vars.eee_status; 2150 2151 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2152 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2153 return -EOPNOTSUPP; 2154 } 2155 2156 advertised = bnx2x_adv_to_eee(edata->advertised, 2157 SHMEM_EEE_ADV_STATUS_SHIFT); 2158 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2159 DP(BNX2X_MSG_ETHTOOL, 2160 "Direct manipulation of EEE advertisement is not supported\n"); 2161 return -EINVAL; 2162 } 2163 2164 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2165 DP(BNX2X_MSG_ETHTOOL, 2166 "Maximal Tx Lpi timer supported is %x(u)\n", 2167 EEE_MODE_TIMER_MASK); 2168 return -EINVAL; 2169 } 2170 if (edata->tx_lpi_enabled && 2171 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2172 DP(BNX2X_MSG_ETHTOOL, 2173 "Minimal Tx Lpi timer supported is %d(u)\n", 2174 EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2175 return -EINVAL; 2176 } 2177 2178 /* All is well; Apply changes*/ 2179 if (edata->eee_enabled) 2180 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2181 else 2182 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2183 2184 if (edata->tx_lpi_enabled) 2185 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2186 else 2187 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2188 2189 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2190 bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2191 EEE_MODE_TIMER_MASK) | 2192 EEE_MODE_OVERRIDE_NVRAM | 2193 EEE_MODE_OUTPUT_TIME; 2194 2195 /* Restart link to propagate changes */ 2196 if (netif_running(dev)) { 2197 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2198 bnx2x_force_link_reset(bp); 2199 bnx2x_link_set(bp); 2200 } 2201 2202 return 0; 2203 } 2204 2205 enum { 2206 BNX2X_CHIP_E1_OFST = 0, 2207 BNX2X_CHIP_E1H_OFST, 2208 BNX2X_CHIP_E2_OFST, 2209 BNX2X_CHIP_E3_OFST, 2210 BNX2X_CHIP_E3B0_OFST, 2211 BNX2X_CHIP_MAX_OFST 2212 }; 2213 2214 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2215 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2216 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2217 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2218 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2219 2220 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2221 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2222 2223 static int bnx2x_test_registers(struct bnx2x *bp) 2224 { 2225 int idx, i, rc = -ENODEV; 2226 u32 wr_val = 0, hw; 2227 int port = BP_PORT(bp); 2228 static const struct { 2229 u32 hw; 2230 u32 offset0; 2231 u32 offset1; 2232 u32 mask; 2233 } reg_tbl[] = { 2234 /* 0 */ { BNX2X_CHIP_MASK_ALL, 2235 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2236 { BNX2X_CHIP_MASK_ALL, 2237 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2238 { BNX2X_CHIP_MASK_E1X, 2239 HC_REG_AGG_INT_0, 4, 0x000003ff }, 2240 { BNX2X_CHIP_MASK_ALL, 2241 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2242 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2243 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2244 { BNX2X_CHIP_MASK_E3B0, 2245 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2246 { BNX2X_CHIP_MASK_ALL, 2247 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2248 { BNX2X_CHIP_MASK_ALL, 2249 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2250 { BNX2X_CHIP_MASK_ALL, 2251 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2252 { BNX2X_CHIP_MASK_ALL, 2253 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2254 /* 10 */ { BNX2X_CHIP_MASK_ALL, 2255 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2256 { BNX2X_CHIP_MASK_ALL, 2257 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2258 { BNX2X_CHIP_MASK_ALL, 2259 QM_REG_CONNNUM_0, 4, 0x000fffff }, 2260 { BNX2X_CHIP_MASK_ALL, 2261 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2262 { BNX2X_CHIP_MASK_ALL, 2263 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2264 { BNX2X_CHIP_MASK_ALL, 2265 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2266 { BNX2X_CHIP_MASK_ALL, 2267 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2268 { BNX2X_CHIP_MASK_ALL, 2269 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2270 { BNX2X_CHIP_MASK_ALL, 2271 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2272 { BNX2X_CHIP_MASK_ALL, 2273 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2274 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2275 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2276 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2277 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2278 { BNX2X_CHIP_MASK_ALL, 2279 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2280 { BNX2X_CHIP_MASK_ALL, 2281 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2282 { BNX2X_CHIP_MASK_ALL, 2283 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2284 { BNX2X_CHIP_MASK_ALL, 2285 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2286 { BNX2X_CHIP_MASK_ALL, 2287 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2288 { BNX2X_CHIP_MASK_ALL, 2289 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2290 { BNX2X_CHIP_MASK_ALL, 2291 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2292 { BNX2X_CHIP_MASK_ALL, 2293 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2294 /* 30 */ { BNX2X_CHIP_MASK_ALL, 2295 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2296 { BNX2X_CHIP_MASK_ALL, 2297 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2298 { BNX2X_CHIP_MASK_ALL, 2299 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2300 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2301 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2302 { BNX2X_CHIP_MASK_ALL, 2303 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2304 { BNX2X_CHIP_MASK_ALL, 2305 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2306 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2307 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2308 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2309 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2310 2311 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2312 }; 2313 2314 if (!bnx2x_is_nvm_accessible(bp)) { 2315 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2316 "cannot access eeprom when the interface is down\n"); 2317 return rc; 2318 } 2319 2320 if (CHIP_IS_E1(bp)) 2321 hw = BNX2X_CHIP_MASK_E1; 2322 else if (CHIP_IS_E1H(bp)) 2323 hw = BNX2X_CHIP_MASK_E1H; 2324 else if (CHIP_IS_E2(bp)) 2325 hw = BNX2X_CHIP_MASK_E2; 2326 else if (CHIP_IS_E3B0(bp)) 2327 hw = BNX2X_CHIP_MASK_E3B0; 2328 else /* e3 A0 */ 2329 hw = BNX2X_CHIP_MASK_E3; 2330 2331 /* Repeat the test twice: 2332 * First by writing 0x00000000, second by writing 0xffffffff 2333 */ 2334 for (idx = 0; idx < 2; idx++) { 2335 2336 switch (idx) { 2337 case 0: 2338 wr_val = 0; 2339 break; 2340 case 1: 2341 wr_val = 0xffffffff; 2342 break; 2343 } 2344 2345 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2346 u32 offset, mask, save_val, val; 2347 if (!(hw & reg_tbl[i].hw)) 2348 continue; 2349 2350 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2351 mask = reg_tbl[i].mask; 2352 2353 save_val = REG_RD(bp, offset); 2354 2355 REG_WR(bp, offset, wr_val & mask); 2356 2357 val = REG_RD(bp, offset); 2358 2359 /* Restore the original register's value */ 2360 REG_WR(bp, offset, save_val); 2361 2362 /* verify value is as expected */ 2363 if ((val & mask) != (wr_val & mask)) { 2364 DP(BNX2X_MSG_ETHTOOL, 2365 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2366 offset, val, wr_val, mask); 2367 goto test_reg_exit; 2368 } 2369 } 2370 } 2371 2372 rc = 0; 2373 2374 test_reg_exit: 2375 return rc; 2376 } 2377 2378 static int bnx2x_test_memory(struct bnx2x *bp) 2379 { 2380 int i, j, rc = -ENODEV; 2381 u32 val, index; 2382 static const struct { 2383 u32 offset; 2384 int size; 2385 } mem_tbl[] = { 2386 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2387 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2388 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2389 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2390 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2391 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2392 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2393 2394 { 0xffffffff, 0 } 2395 }; 2396 2397 static const struct { 2398 char *name; 2399 u32 offset; 2400 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2401 } prty_tbl[] = { 2402 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2403 {0x3ffc0, 0, 0, 0} }, 2404 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2405 {0x2, 0x2, 0, 0} }, 2406 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2407 {0, 0, 0, 0} }, 2408 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2409 {0x3ffc0, 0, 0, 0} }, 2410 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2411 {0x3ffc0, 0, 0, 0} }, 2412 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2413 {0x3ffc1, 0, 0, 0} }, 2414 2415 { NULL, 0xffffffff, {0, 0, 0, 0} } 2416 }; 2417 2418 if (!bnx2x_is_nvm_accessible(bp)) { 2419 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2420 "cannot access eeprom when the interface is down\n"); 2421 return rc; 2422 } 2423 2424 if (CHIP_IS_E1(bp)) 2425 index = BNX2X_CHIP_E1_OFST; 2426 else if (CHIP_IS_E1H(bp)) 2427 index = BNX2X_CHIP_E1H_OFST; 2428 else if (CHIP_IS_E2(bp)) 2429 index = BNX2X_CHIP_E2_OFST; 2430 else /* e3 */ 2431 index = BNX2X_CHIP_E3_OFST; 2432 2433 /* pre-Check the parity status */ 2434 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2435 val = REG_RD(bp, prty_tbl[i].offset); 2436 if (val & ~(prty_tbl[i].hw_mask[index])) { 2437 DP(BNX2X_MSG_ETHTOOL, 2438 "%s is 0x%x\n", prty_tbl[i].name, val); 2439 goto test_mem_exit; 2440 } 2441 } 2442 2443 /* Go through all the memories */ 2444 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2445 for (j = 0; j < mem_tbl[i].size; j++) 2446 REG_RD(bp, mem_tbl[i].offset + j*4); 2447 2448 /* Check the parity status */ 2449 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2450 val = REG_RD(bp, prty_tbl[i].offset); 2451 if (val & ~(prty_tbl[i].hw_mask[index])) { 2452 DP(BNX2X_MSG_ETHTOOL, 2453 "%s is 0x%x\n", prty_tbl[i].name, val); 2454 goto test_mem_exit; 2455 } 2456 } 2457 2458 rc = 0; 2459 2460 test_mem_exit: 2461 return rc; 2462 } 2463 2464 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2465 { 2466 int cnt = 1400; 2467 2468 if (link_up) { 2469 while (bnx2x_link_test(bp, is_serdes) && cnt--) 2470 msleep(20); 2471 2472 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 2473 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 2474 2475 cnt = 1400; 2476 while (!bp->link_vars.link_up && cnt--) 2477 msleep(20); 2478 2479 if (cnt <= 0 && !bp->link_vars.link_up) 2480 DP(BNX2X_MSG_ETHTOOL, 2481 "Timeout waiting for link init\n"); 2482 } 2483 } 2484 2485 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2486 { 2487 unsigned int pkt_size, num_pkts, i; 2488 struct sk_buff *skb; 2489 unsigned char *packet; 2490 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2491 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 2492 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2493 u16 tx_start_idx, tx_idx; 2494 u16 rx_start_idx, rx_idx; 2495 u16 pkt_prod, bd_prod; 2496 struct sw_tx_bd *tx_buf; 2497 struct eth_tx_start_bd *tx_start_bd; 2498 dma_addr_t mapping; 2499 union eth_rx_cqe *cqe; 2500 u8 cqe_fp_flags, cqe_fp_type; 2501 struct sw_rx_bd *rx_buf; 2502 u16 len; 2503 int rc = -ENODEV; 2504 u8 *data; 2505 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 2506 txdata->txq_index); 2507 2508 /* check the loopback mode */ 2509 switch (loopback_mode) { 2510 case BNX2X_PHY_LOOPBACK: 2511 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 2512 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2513 return -EINVAL; 2514 } 2515 break; 2516 case BNX2X_MAC_LOOPBACK: 2517 if (CHIP_IS_E3(bp)) { 2518 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2519 if (bp->port.supported[cfg_idx] & 2520 (SUPPORTED_10000baseT_Full | 2521 SUPPORTED_20000baseMLD2_Full | 2522 SUPPORTED_20000baseKR2_Full)) 2523 bp->link_params.loopback_mode = LOOPBACK_XMAC; 2524 else 2525 bp->link_params.loopback_mode = LOOPBACK_UMAC; 2526 } else 2527 bp->link_params.loopback_mode = LOOPBACK_BMAC; 2528 2529 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2530 break; 2531 case BNX2X_EXT_LOOPBACK: 2532 if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 2533 DP(BNX2X_MSG_ETHTOOL, 2534 "Can't configure external loopback\n"); 2535 return -EINVAL; 2536 } 2537 break; 2538 default: 2539 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2540 return -EINVAL; 2541 } 2542 2543 /* prepare the loopback packet */ 2544 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2545 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2546 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2547 if (!skb) { 2548 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2549 rc = -ENOMEM; 2550 goto test_loopback_exit; 2551 } 2552 packet = skb_put(skb, pkt_size); 2553 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2554 eth_zero_addr(packet + ETH_ALEN); 2555 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2556 for (i = ETH_HLEN; i < pkt_size; i++) 2557 packet[i] = (unsigned char) (i & 0xff); 2558 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2559 skb_headlen(skb), DMA_TO_DEVICE); 2560 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2561 rc = -ENOMEM; 2562 dev_kfree_skb(skb); 2563 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2564 goto test_loopback_exit; 2565 } 2566 2567 /* send the loopback packet */ 2568 num_pkts = 0; 2569 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2570 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2571 2572 netdev_tx_sent_queue(txq, skb->len); 2573 2574 pkt_prod = txdata->tx_pkt_prod++; 2575 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2576 tx_buf->first_bd = txdata->tx_bd_prod; 2577 tx_buf->skb = skb; 2578 tx_buf->flags = 0; 2579 2580 bd_prod = TX_BD(txdata->tx_bd_prod); 2581 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2582 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2583 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2584 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2585 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2586 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2587 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2588 SET_FLAG(tx_start_bd->general_data, 2589 ETH_TX_START_BD_HDR_NBDS, 2590 1); 2591 SET_FLAG(tx_start_bd->general_data, 2592 ETH_TX_START_BD_PARSE_NBDS, 2593 0); 2594 2595 /* turn on parsing and get a BD */ 2596 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2597 2598 if (CHIP_IS_E1x(bp)) { 2599 u16 global_data = 0; 2600 struct eth_tx_parse_bd_e1x *pbd_e1x = 2601 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2602 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2603 SET_FLAG(global_data, 2604 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2605 pbd_e1x->global_data = cpu_to_le16(global_data); 2606 } else { 2607 u32 parsing_data = 0; 2608 struct eth_tx_parse_bd_e2 *pbd_e2 = 2609 &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2610 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2611 SET_FLAG(parsing_data, 2612 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2613 pbd_e2->parsing_data = cpu_to_le32(parsing_data); 2614 } 2615 wmb(); 2616 2617 txdata->tx_db.data.prod += 2; 2618 /* make sure descriptor update is observed by the HW */ 2619 wmb(); 2620 DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw); 2621 2622 barrier(); 2623 2624 num_pkts++; 2625 txdata->tx_bd_prod += 2; /* start + pbd */ 2626 2627 udelay(100); 2628 2629 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2630 if (tx_idx != tx_start_idx + num_pkts) 2631 goto test_loopback_exit; 2632 2633 /* Unlike HC IGU won't generate an interrupt for status block 2634 * updates that have been performed while interrupts were 2635 * disabled. 2636 */ 2637 if (bp->common.int_block == INT_BLOCK_IGU) { 2638 /* Disable local BHes to prevent a dead-lock situation between 2639 * sch_direct_xmit() and bnx2x_run_loopback() (calling 2640 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2641 */ 2642 local_bh_disable(); 2643 bnx2x_tx_int(bp, txdata); 2644 local_bh_enable(); 2645 } 2646 2647 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2648 if (rx_idx != rx_start_idx + num_pkts) 2649 goto test_loopback_exit; 2650 2651 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2652 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2653 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2654 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2655 goto test_loopback_rx_exit; 2656 2657 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2658 if (len != pkt_size) 2659 goto test_loopback_rx_exit; 2660 2661 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2662 dma_sync_single_for_cpu(&bp->pdev->dev, 2663 dma_unmap_addr(rx_buf, mapping), 2664 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2665 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2666 for (i = ETH_HLEN; i < pkt_size; i++) 2667 if (*(data + i) != (unsigned char) (i & 0xff)) 2668 goto test_loopback_rx_exit; 2669 2670 rc = 0; 2671 2672 test_loopback_rx_exit: 2673 2674 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2675 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2676 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2677 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2678 2679 /* Update producers */ 2680 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2681 fp_rx->rx_sge_prod); 2682 2683 test_loopback_exit: 2684 bp->link_params.loopback_mode = LOOPBACK_NONE; 2685 2686 return rc; 2687 } 2688 2689 static int bnx2x_test_loopback(struct bnx2x *bp) 2690 { 2691 int rc = 0, res; 2692 2693 if (BP_NOMCP(bp)) 2694 return rc; 2695 2696 if (!netif_running(bp->dev)) 2697 return BNX2X_LOOPBACK_FAILED; 2698 2699 bnx2x_netif_stop(bp, 1); 2700 bnx2x_acquire_phy_lock(bp); 2701 2702 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2703 if (res) { 2704 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2705 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2706 } 2707 2708 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2709 if (res) { 2710 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2711 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2712 } 2713 2714 bnx2x_release_phy_lock(bp); 2715 bnx2x_netif_start(bp); 2716 2717 return rc; 2718 } 2719 2720 static int bnx2x_test_ext_loopback(struct bnx2x *bp) 2721 { 2722 int rc; 2723 u8 is_serdes = 2724 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2725 2726 if (BP_NOMCP(bp)) 2727 return -ENODEV; 2728 2729 if (!netif_running(bp->dev)) 2730 return BNX2X_EXT_LOOPBACK_FAILED; 2731 2732 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2733 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 2734 if (rc) { 2735 DP(BNX2X_MSG_ETHTOOL, 2736 "Can't perform self-test, nic_load (for external lb) failed\n"); 2737 return -ENODEV; 2738 } 2739 bnx2x_wait_for_link(bp, 1, is_serdes); 2740 2741 bnx2x_netif_stop(bp, 1); 2742 2743 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 2744 if (rc) 2745 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 2746 2747 bnx2x_netif_start(bp); 2748 2749 return rc; 2750 } 2751 2752 struct code_entry { 2753 u32 sram_start_addr; 2754 u32 code_attribute; 2755 #define CODE_IMAGE_TYPE_MASK 0xf0800003 2756 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2757 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2758 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2759 u32 nvm_start_addr; 2760 }; 2761 2762 #define CODE_ENTRY_MAX 16 2763 #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2764 #define MAX_IMAGES_IN_EXTENDED_DIR 64 2765 #define NVRAM_DIR_OFFSET 0x14 2766 2767 #define EXTENDED_DIR_EXISTS(code) \ 2768 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2769 (code & CODE_IMAGE_LENGTH_MASK) != 0) 2770 2771 #define CRC32_RESIDUAL 0xdebb20e3 2772 #define CRC_BUFF_SIZE 256 2773 2774 static int bnx2x_nvram_crc(struct bnx2x *bp, 2775 int offset, 2776 int size, 2777 u8 *buff) 2778 { 2779 u32 crc = ~0; 2780 int rc = 0, done = 0; 2781 2782 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2783 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2784 2785 while (done < size) { 2786 int count = min_t(int, size - done, CRC_BUFF_SIZE); 2787 2788 rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2789 2790 if (rc) 2791 return rc; 2792 2793 crc = crc32_le(crc, buff, count); 2794 done += count; 2795 } 2796 2797 if (crc != CRC32_RESIDUAL) 2798 rc = -EINVAL; 2799 2800 return rc; 2801 } 2802 2803 static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2804 struct code_entry *entry, 2805 u8 *buff) 2806 { 2807 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2808 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2809 int rc; 2810 2811 /* Zero-length images and AFEX profiles do not have CRC */ 2812 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2813 return 0; 2814 2815 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2816 if (rc) 2817 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2818 "image %x has failed crc test (rc %d)\n", type, rc); 2819 2820 return rc; 2821 } 2822 2823 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2824 { 2825 int rc; 2826 struct code_entry entry; 2827 2828 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2829 if (rc) 2830 return rc; 2831 2832 return bnx2x_test_nvram_dir(bp, &entry, buff); 2833 } 2834 2835 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2836 { 2837 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2838 struct code_entry entry; 2839 int i; 2840 2841 rc = bnx2x_nvram_read32(bp, 2842 dir_offset + 2843 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2844 (u32 *)&entry, sizeof(entry)); 2845 if (rc) 2846 return rc; 2847 2848 if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2849 return 0; 2850 2851 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2852 &cnt, sizeof(u32)); 2853 if (rc) 2854 return rc; 2855 2856 dir_offset = entry.nvm_start_addr + 8; 2857 2858 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2859 rc = bnx2x_test_dir_entry(bp, dir_offset + 2860 sizeof(struct code_entry) * i, 2861 buff); 2862 if (rc) 2863 return rc; 2864 } 2865 2866 return 0; 2867 } 2868 2869 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2870 { 2871 u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2872 int i; 2873 2874 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2875 2876 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2877 rc = bnx2x_test_dir_entry(bp, dir_offset + 2878 sizeof(struct code_entry) * i, 2879 buff); 2880 if (rc) 2881 return rc; 2882 } 2883 2884 return bnx2x_test_nvram_ext_dirs(bp, buff); 2885 } 2886 2887 struct crc_pair { 2888 int offset; 2889 int size; 2890 }; 2891 2892 static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2893 const struct crc_pair *nvram_tbl, u8 *buf) 2894 { 2895 int i; 2896 2897 for (i = 0; nvram_tbl[i].size; i++) { 2898 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2899 nvram_tbl[i].size, buf); 2900 if (rc) { 2901 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2902 "nvram_tbl[%d] has failed crc test (rc %d)\n", 2903 i, rc); 2904 return rc; 2905 } 2906 } 2907 2908 return 0; 2909 } 2910 2911 static int bnx2x_test_nvram(struct bnx2x *bp) 2912 { 2913 static const struct crc_pair nvram_tbl[] = { 2914 { 0, 0x14 }, /* bootstrap */ 2915 { 0x14, 0xec }, /* dir */ 2916 { 0x100, 0x350 }, /* manuf_info */ 2917 { 0x450, 0xf0 }, /* feature_info */ 2918 { 0x640, 0x64 }, /* upgrade_key_info */ 2919 { 0x708, 0x70 }, /* manuf_key_info */ 2920 { 0, 0 } 2921 }; 2922 static const struct crc_pair nvram_tbl2[] = { 2923 { 0x7e8, 0x350 }, /* manuf_info2 */ 2924 { 0xb38, 0xf0 }, /* feature_info */ 2925 { 0, 0 } 2926 }; 2927 2928 u8 *buf; 2929 int rc; 2930 u32 magic; 2931 2932 if (BP_NOMCP(bp)) 2933 return 0; 2934 2935 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2936 if (!buf) { 2937 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2938 rc = -ENOMEM; 2939 goto test_nvram_exit; 2940 } 2941 2942 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2943 if (rc) { 2944 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2945 "magic value read (rc %d)\n", rc); 2946 goto test_nvram_exit; 2947 } 2948 2949 if (magic != 0x669955aa) { 2950 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2951 "wrong magic value (0x%08x)\n", magic); 2952 rc = -ENODEV; 2953 goto test_nvram_exit; 2954 } 2955 2956 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2957 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2958 if (rc) 2959 goto test_nvram_exit; 2960 2961 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2962 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2963 SHARED_HW_CFG_HIDE_PORT1; 2964 2965 if (!hide) { 2966 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2967 "Port 1 CRC test-set\n"); 2968 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2969 if (rc) 2970 goto test_nvram_exit; 2971 } 2972 } 2973 2974 rc = bnx2x_test_nvram_dirs(bp, buf); 2975 2976 test_nvram_exit: 2977 kfree(buf); 2978 return rc; 2979 } 2980 2981 /* Send an EMPTY ramrod on the first queue */ 2982 static int bnx2x_test_intr(struct bnx2x *bp) 2983 { 2984 struct bnx2x_queue_state_params params = {NULL}; 2985 2986 if (!netif_running(bp->dev)) { 2987 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2988 "cannot access eeprom when the interface is down\n"); 2989 return -ENODEV; 2990 } 2991 2992 params.q_obj = &bp->sp_objs->q_obj; 2993 params.cmd = BNX2X_Q_CMD_EMPTY; 2994 2995 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2996 2997 return bnx2x_queue_state_change(bp, ¶ms); 2998 } 2999 3000 static void bnx2x_self_test(struct net_device *dev, 3001 struct ethtool_test *etest, u64 *buf) 3002 { 3003 struct bnx2x *bp = netdev_priv(dev); 3004 u8 is_serdes, link_up; 3005 int rc, cnt = 0; 3006 3007 if (pci_num_vf(bp->pdev)) { 3008 DP(BNX2X_MSG_IOV, 3009 "VFs are enabled, can not perform self test\n"); 3010 return; 3011 } 3012 3013 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 3014 netdev_err(bp->dev, 3015 "Handling parity error recovery. Try again later\n"); 3016 etest->flags |= ETH_TEST_FL_FAILED; 3017 return; 3018 } 3019 3020 DP(BNX2X_MSG_ETHTOOL, 3021 "Self-test command parameters: offline = %d, external_lb = %d\n", 3022 (etest->flags & ETH_TEST_FL_OFFLINE), 3023 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 3024 3025 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 3026 3027 if (bnx2x_test_nvram(bp) != 0) { 3028 if (!IS_MF(bp)) 3029 buf[4] = 1; 3030 else 3031 buf[0] = 1; 3032 etest->flags |= ETH_TEST_FL_FAILED; 3033 } 3034 3035 if (!netif_running(dev)) { 3036 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 3037 return; 3038 } 3039 3040 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 3041 link_up = bp->link_vars.link_up; 3042 /* offline tests are not supported in MF mode */ 3043 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 3044 int port = BP_PORT(bp); 3045 u32 val; 3046 3047 /* save current value of input enable for TX port IF */ 3048 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 3049 /* disable input for TX port IF */ 3050 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 3051 3052 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3053 rc = bnx2x_nic_load(bp, LOAD_DIAG); 3054 if (rc) { 3055 etest->flags |= ETH_TEST_FL_FAILED; 3056 DP(BNX2X_MSG_ETHTOOL, 3057 "Can't perform self-test, nic_load (for offline) failed\n"); 3058 return; 3059 } 3060 3061 /* wait until link state is restored */ 3062 bnx2x_wait_for_link(bp, 1, is_serdes); 3063 3064 if (bnx2x_test_registers(bp) != 0) { 3065 buf[0] = 1; 3066 etest->flags |= ETH_TEST_FL_FAILED; 3067 } 3068 if (bnx2x_test_memory(bp) != 0) { 3069 buf[1] = 1; 3070 etest->flags |= ETH_TEST_FL_FAILED; 3071 } 3072 3073 buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3074 if (buf[2] != 0) 3075 etest->flags |= ETH_TEST_FL_FAILED; 3076 3077 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 3078 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 3079 if (buf[3] != 0) 3080 etest->flags |= ETH_TEST_FL_FAILED; 3081 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3082 } 3083 3084 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3085 3086 /* restore input for TX port IF */ 3087 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3088 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3089 if (rc) { 3090 etest->flags |= ETH_TEST_FL_FAILED; 3091 DP(BNX2X_MSG_ETHTOOL, 3092 "Can't perform self-test, nic_load (for online) failed\n"); 3093 return; 3094 } 3095 /* wait until link state is restored */ 3096 bnx2x_wait_for_link(bp, link_up, is_serdes); 3097 } 3098 3099 if (bnx2x_test_intr(bp) != 0) { 3100 if (!IS_MF(bp)) 3101 buf[5] = 1; 3102 else 3103 buf[1] = 1; 3104 etest->flags |= ETH_TEST_FL_FAILED; 3105 } 3106 3107 if (link_up) { 3108 cnt = 100; 3109 while (bnx2x_link_test(bp, is_serdes) && --cnt) 3110 msleep(20); 3111 } 3112 3113 if (!cnt) { 3114 if (!IS_MF(bp)) 3115 buf[6] = 1; 3116 else 3117 buf[2] = 1; 3118 etest->flags |= ETH_TEST_FL_FAILED; 3119 } 3120 } 3121 3122 #define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat) 3123 #define HIDE_PORT_STAT(bp) IS_VF(bp) 3124 3125 /* ethtool statistics are displayed for all regular ethernet queues and the 3126 * fcoe L2 queue if not disabled 3127 */ 3128 static int bnx2x_num_stat_queues(struct bnx2x *bp) 3129 { 3130 return BNX2X_NUM_ETH_QUEUES(bp); 3131 } 3132 3133 static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3134 { 3135 struct bnx2x *bp = netdev_priv(dev); 3136 int i, num_strings = 0; 3137 3138 switch (stringset) { 3139 case ETH_SS_STATS: 3140 if (is_multi(bp)) { 3141 num_strings = bnx2x_num_stat_queues(bp) * 3142 BNX2X_NUM_Q_STATS; 3143 } else 3144 num_strings = 0; 3145 if (HIDE_PORT_STAT(bp)) { 3146 for (i = 0; i < BNX2X_NUM_STATS; i++) 3147 if (!IS_PORT_STAT(i)) 3148 num_strings++; 3149 } else 3150 num_strings += BNX2X_NUM_STATS; 3151 3152 return num_strings; 3153 3154 case ETH_SS_TEST: 3155 return BNX2X_NUM_TESTS(bp); 3156 3157 case ETH_SS_PRIV_FLAGS: 3158 return BNX2X_PRI_FLAG_LEN; 3159 3160 default: 3161 return -EINVAL; 3162 } 3163 } 3164 3165 static u32 bnx2x_get_private_flags(struct net_device *dev) 3166 { 3167 struct bnx2x *bp = netdev_priv(dev); 3168 u32 flags = 0; 3169 3170 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 3171 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 3172 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 3173 3174 return flags; 3175 } 3176 3177 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3178 { 3179 struct bnx2x *bp = netdev_priv(dev); 3180 int i, j, k, start; 3181 char queue_name[MAX_QUEUE_NAME_LEN+1]; 3182 3183 switch (stringset) { 3184 case ETH_SS_STATS: 3185 k = 0; 3186 if (is_multi(bp)) { 3187 for_each_eth_queue(bp, i) { 3188 memset(queue_name, 0, sizeof(queue_name)); 3189 snprintf(queue_name, sizeof(queue_name), 3190 "%d", i); 3191 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3192 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3193 ETH_GSTRING_LEN, 3194 bnx2x_q_stats_arr[j].string, 3195 queue_name); 3196 k += BNX2X_NUM_Q_STATS; 3197 } 3198 } 3199 3200 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3201 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3202 continue; 3203 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3204 bnx2x_stats_arr[i].string); 3205 j++; 3206 } 3207 3208 break; 3209 3210 case ETH_SS_TEST: 3211 /* First 4 tests cannot be done in MF mode */ 3212 if (!IS_MF(bp)) 3213 start = 0; 3214 else 3215 start = 4; 3216 memcpy(buf, bnx2x_tests_str_arr + start, 3217 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 3218 break; 3219 3220 case ETH_SS_PRIV_FLAGS: 3221 memcpy(buf, bnx2x_private_arr, 3222 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 3223 break; 3224 } 3225 } 3226 3227 static void bnx2x_get_ethtool_stats(struct net_device *dev, 3228 struct ethtool_stats *stats, u64 *buf) 3229 { 3230 struct bnx2x *bp = netdev_priv(dev); 3231 u32 *hw_stats, *offset; 3232 int i, j, k = 0; 3233 3234 if (is_multi(bp)) { 3235 for_each_eth_queue(bp, i) { 3236 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3237 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3238 if (bnx2x_q_stats_arr[j].size == 0) { 3239 /* skip this counter */ 3240 buf[k + j] = 0; 3241 continue; 3242 } 3243 offset = (hw_stats + 3244 bnx2x_q_stats_arr[j].offset); 3245 if (bnx2x_q_stats_arr[j].size == 4) { 3246 /* 4-byte counter */ 3247 buf[k + j] = (u64) *offset; 3248 continue; 3249 } 3250 /* 8-byte counter */ 3251 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3252 } 3253 k += BNX2X_NUM_Q_STATS; 3254 } 3255 } 3256 3257 hw_stats = (u32 *)&bp->eth_stats; 3258 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3259 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3260 continue; 3261 if (bnx2x_stats_arr[i].size == 0) { 3262 /* skip this counter */ 3263 buf[k + j] = 0; 3264 j++; 3265 continue; 3266 } 3267 offset = (hw_stats + bnx2x_stats_arr[i].offset); 3268 if (bnx2x_stats_arr[i].size == 4) { 3269 /* 4-byte counter */ 3270 buf[k + j] = (u64) *offset; 3271 j++; 3272 continue; 3273 } 3274 /* 8-byte counter */ 3275 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3276 j++; 3277 } 3278 } 3279 3280 static int bnx2x_set_phys_id(struct net_device *dev, 3281 enum ethtool_phys_id_state state) 3282 { 3283 struct bnx2x *bp = netdev_priv(dev); 3284 3285 if (!bnx2x_is_nvm_accessible(bp)) { 3286 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 3287 "cannot access eeprom when the interface is down\n"); 3288 return -EAGAIN; 3289 } 3290 3291 switch (state) { 3292 case ETHTOOL_ID_ACTIVE: 3293 return 1; /* cycle on/off once per second */ 3294 3295 case ETHTOOL_ID_ON: 3296 bnx2x_acquire_phy_lock(bp); 3297 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3298 LED_MODE_ON, SPEED_1000); 3299 bnx2x_release_phy_lock(bp); 3300 break; 3301 3302 case ETHTOOL_ID_OFF: 3303 bnx2x_acquire_phy_lock(bp); 3304 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3305 LED_MODE_FRONT_PANEL_OFF, 0); 3306 bnx2x_release_phy_lock(bp); 3307 break; 3308 3309 case ETHTOOL_ID_INACTIVE: 3310 bnx2x_acquire_phy_lock(bp); 3311 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3312 LED_MODE_OPER, 3313 bp->link_vars.line_speed); 3314 bnx2x_release_phy_lock(bp); 3315 } 3316 3317 return 0; 3318 } 3319 3320 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3321 { 3322 switch (info->flow_type) { 3323 case TCP_V4_FLOW: 3324 case TCP_V6_FLOW: 3325 info->data = RXH_IP_SRC | RXH_IP_DST | 3326 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3327 break; 3328 case UDP_V4_FLOW: 3329 if (bp->rss_conf_obj.udp_rss_v4) 3330 info->data = RXH_IP_SRC | RXH_IP_DST | 3331 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3332 else 3333 info->data = RXH_IP_SRC | RXH_IP_DST; 3334 break; 3335 case UDP_V6_FLOW: 3336 if (bp->rss_conf_obj.udp_rss_v6) 3337 info->data = RXH_IP_SRC | RXH_IP_DST | 3338 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3339 else 3340 info->data = RXH_IP_SRC | RXH_IP_DST; 3341 break; 3342 case IPV4_FLOW: 3343 case IPV6_FLOW: 3344 info->data = RXH_IP_SRC | RXH_IP_DST; 3345 break; 3346 default: 3347 info->data = 0; 3348 break; 3349 } 3350 3351 return 0; 3352 } 3353 3354 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3355 u32 *rules __always_unused) 3356 { 3357 struct bnx2x *bp = netdev_priv(dev); 3358 3359 switch (info->cmd) { 3360 case ETHTOOL_GRXRINGS: 3361 info->data = BNX2X_NUM_ETH_QUEUES(bp); 3362 return 0; 3363 case ETHTOOL_GRXFH: 3364 return bnx2x_get_rss_flags(bp, info); 3365 default: 3366 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3367 return -EOPNOTSUPP; 3368 } 3369 } 3370 3371 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3372 { 3373 int udp_rss_requested; 3374 3375 DP(BNX2X_MSG_ETHTOOL, 3376 "Set rss flags command parameters: flow type = %d, data = %llu\n", 3377 info->flow_type, info->data); 3378 3379 switch (info->flow_type) { 3380 case TCP_V4_FLOW: 3381 case TCP_V6_FLOW: 3382 /* For TCP only 4-tupple hash is supported */ 3383 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 3384 RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 3385 DP(BNX2X_MSG_ETHTOOL, 3386 "Command parameters not supported\n"); 3387 return -EINVAL; 3388 } 3389 return 0; 3390 3391 case UDP_V4_FLOW: 3392 case UDP_V6_FLOW: 3393 /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 3394 if (info->data == (RXH_IP_SRC | RXH_IP_DST | 3395 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3396 udp_rss_requested = 1; 3397 else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 3398 udp_rss_requested = 0; 3399 else 3400 return -EINVAL; 3401 3402 if (CHIP_IS_E1x(bp) && udp_rss_requested) { 3403 DP(BNX2X_MSG_ETHTOOL, 3404 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n"); 3405 return -EINVAL; 3406 } 3407 3408 if ((info->flow_type == UDP_V4_FLOW) && 3409 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 3410 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 3411 DP(BNX2X_MSG_ETHTOOL, 3412 "rss re-configured, UDP 4-tupple %s\n", 3413 udp_rss_requested ? "enabled" : "disabled"); 3414 if (bp->state == BNX2X_STATE_OPEN) 3415 return bnx2x_rss(bp, &bp->rss_conf_obj, false, 3416 true); 3417 } else if ((info->flow_type == UDP_V6_FLOW) && 3418 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 3419 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 3420 DP(BNX2X_MSG_ETHTOOL, 3421 "rss re-configured, UDP 4-tupple %s\n", 3422 udp_rss_requested ? "enabled" : "disabled"); 3423 if (bp->state == BNX2X_STATE_OPEN) 3424 return bnx2x_rss(bp, &bp->rss_conf_obj, false, 3425 true); 3426 } 3427 return 0; 3428 3429 case IPV4_FLOW: 3430 case IPV6_FLOW: 3431 /* For IP only 2-tupple hash is supported */ 3432 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 3433 DP(BNX2X_MSG_ETHTOOL, 3434 "Command parameters not supported\n"); 3435 return -EINVAL; 3436 } 3437 return 0; 3438 3439 case SCTP_V4_FLOW: 3440 case AH_ESP_V4_FLOW: 3441 case AH_V4_FLOW: 3442 case ESP_V4_FLOW: 3443 case SCTP_V6_FLOW: 3444 case AH_ESP_V6_FLOW: 3445 case AH_V6_FLOW: 3446 case ESP_V6_FLOW: 3447 case IP_USER_FLOW: 3448 case ETHER_FLOW: 3449 /* RSS is not supported for these protocols */ 3450 if (info->data) { 3451 DP(BNX2X_MSG_ETHTOOL, 3452 "Command parameters not supported\n"); 3453 return -EINVAL; 3454 } 3455 return 0; 3456 3457 default: 3458 return -EINVAL; 3459 } 3460 } 3461 3462 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 3463 { 3464 struct bnx2x *bp = netdev_priv(dev); 3465 3466 switch (info->cmd) { 3467 case ETHTOOL_SRXFH: 3468 return bnx2x_set_rss_flags(bp, info); 3469 default: 3470 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3471 return -EOPNOTSUPP; 3472 } 3473 } 3474 3475 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3476 { 3477 return T_ETH_INDIRECTION_TABLE_SIZE; 3478 } 3479 3480 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3481 u8 *hfunc) 3482 { 3483 struct bnx2x *bp = netdev_priv(dev); 3484 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3485 size_t i; 3486 3487 if (hfunc) 3488 *hfunc = ETH_RSS_HASH_TOP; 3489 if (!indir) 3490 return 0; 3491 3492 /* Get the current configuration of the RSS indirection table */ 3493 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3494 3495 /* 3496 * We can't use a memcpy() as an internal storage of an 3497 * indirection table is a u8 array while indir->ring_index 3498 * points to an array of u32. 3499 * 3500 * Indirection table contains the FW Client IDs, so we need to 3501 * align the returned table to the Client ID of the leading RSS 3502 * queue. 3503 */ 3504 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 3505 indir[i] = ind_table[i] - bp->fp->cl_id; 3506 3507 return 0; 3508 } 3509 3510 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3511 const u8 *key, const u8 hfunc) 3512 { 3513 struct bnx2x *bp = netdev_priv(dev); 3514 size_t i; 3515 3516 /* We require at least one supported parameter to be changed and no 3517 * change in any of the unsupported parameters 3518 */ 3519 if (key || 3520 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3521 return -EOPNOTSUPP; 3522 3523 if (!indir) 3524 return 0; 3525 3526 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3527 /* 3528 * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3529 * as an internal storage of an indirection table is a u8 array 3530 * while indir->ring_index points to an array of u32. 3531 * 3532 * Indirection table contains the FW Client IDs, so we need to 3533 * align the received table to the Client ID of the leading RSS 3534 * queue 3535 */ 3536 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3537 } 3538 3539 if (bp->state == BNX2X_STATE_OPEN) 3540 return bnx2x_config_rss_eth(bp, false); 3541 3542 return 0; 3543 } 3544 3545 /** 3546 * bnx2x_get_channels - gets the number of RSS queues. 3547 * 3548 * @dev: net device 3549 * @channels: returns the number of max / current queues 3550 */ 3551 static void bnx2x_get_channels(struct net_device *dev, 3552 struct ethtool_channels *channels) 3553 { 3554 struct bnx2x *bp = netdev_priv(dev); 3555 3556 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 3557 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 3558 } 3559 3560 /** 3561 * bnx2x_change_num_queues - change the number of RSS queues. 3562 * 3563 * @bp: bnx2x private structure 3564 * 3565 * Re-configure interrupt mode to get the new number of MSI-X 3566 * vectors and re-add NAPI objects. 3567 */ 3568 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 3569 { 3570 bnx2x_disable_msi(bp); 3571 bp->num_ethernet_queues = num_rss; 3572 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 3573 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 3574 bnx2x_set_int_mode(bp); 3575 } 3576 3577 /** 3578 * bnx2x_set_channels - sets the number of RSS queues. 3579 * 3580 * @dev: net device 3581 * @channels: includes the number of queues requested 3582 */ 3583 static int bnx2x_set_channels(struct net_device *dev, 3584 struct ethtool_channels *channels) 3585 { 3586 struct bnx2x *bp = netdev_priv(dev); 3587 3588 DP(BNX2X_MSG_ETHTOOL, 3589 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 3590 channels->rx_count, channels->tx_count, channels->other_count, 3591 channels->combined_count); 3592 3593 if (pci_num_vf(bp->pdev)) { 3594 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3595 return -EPERM; 3596 } 3597 3598 /* We don't support separate rx / tx channels. 3599 * We don't allow setting 'other' channels. 3600 */ 3601 if (channels->rx_count || channels->tx_count || channels->other_count 3602 || (channels->combined_count == 0) || 3603 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 3604 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 3605 return -EINVAL; 3606 } 3607 3608 /* Check if there was a change in the active parameters */ 3609 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 3610 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 3611 return 0; 3612 } 3613 3614 /* Set the requested number of queues in bp context. 3615 * Note that the actual number of queues created during load may be 3616 * less than requested if memory is low. 3617 */ 3618 if (unlikely(!netif_running(dev))) { 3619 bnx2x_change_num_queues(bp, channels->combined_count); 3620 return 0; 3621 } 3622 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 3623 bnx2x_change_num_queues(bp, channels->combined_count); 3624 return bnx2x_nic_load(bp, LOAD_NORMAL); 3625 } 3626 3627 static int bnx2x_get_ts_info(struct net_device *dev, 3628 struct ethtool_ts_info *info) 3629 { 3630 struct bnx2x *bp = netdev_priv(dev); 3631 3632 if (bp->flags & PTP_SUPPORTED) { 3633 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3634 SOF_TIMESTAMPING_RX_SOFTWARE | 3635 SOF_TIMESTAMPING_SOFTWARE | 3636 SOF_TIMESTAMPING_TX_HARDWARE | 3637 SOF_TIMESTAMPING_RX_HARDWARE | 3638 SOF_TIMESTAMPING_RAW_HARDWARE; 3639 3640 if (bp->ptp_clock) 3641 info->phc_index = ptp_clock_index(bp->ptp_clock); 3642 else 3643 info->phc_index = -1; 3644 3645 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3646 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3647 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3648 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3649 3650 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3651 3652 return 0; 3653 } 3654 3655 return ethtool_op_get_ts_info(dev, info); 3656 } 3657 3658 static const struct ethtool_ops bnx2x_ethtool_ops = { 3659 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3660 .get_drvinfo = bnx2x_get_drvinfo, 3661 .get_regs_len = bnx2x_get_regs_len, 3662 .get_regs = bnx2x_get_regs, 3663 .get_dump_flag = bnx2x_get_dump_flag, 3664 .get_dump_data = bnx2x_get_dump_data, 3665 .set_dump = bnx2x_set_dump, 3666 .get_wol = bnx2x_get_wol, 3667 .set_wol = bnx2x_set_wol, 3668 .get_msglevel = bnx2x_get_msglevel, 3669 .set_msglevel = bnx2x_set_msglevel, 3670 .nway_reset = bnx2x_nway_reset, 3671 .get_link = bnx2x_get_link, 3672 .get_eeprom_len = bnx2x_get_eeprom_len, 3673 .get_eeprom = bnx2x_get_eeprom, 3674 .set_eeprom = bnx2x_set_eeprom, 3675 .get_coalesce = bnx2x_get_coalesce, 3676 .set_coalesce = bnx2x_set_coalesce, 3677 .get_ringparam = bnx2x_get_ringparam, 3678 .set_ringparam = bnx2x_set_ringparam, 3679 .get_pauseparam = bnx2x_get_pauseparam, 3680 .set_pauseparam = bnx2x_set_pauseparam, 3681 .self_test = bnx2x_self_test, 3682 .get_sset_count = bnx2x_get_sset_count, 3683 .get_priv_flags = bnx2x_get_private_flags, 3684 .get_strings = bnx2x_get_strings, 3685 .set_phys_id = bnx2x_set_phys_id, 3686 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3687 .get_rxnfc = bnx2x_get_rxnfc, 3688 .set_rxnfc = bnx2x_set_rxnfc, 3689 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3690 .get_rxfh = bnx2x_get_rxfh, 3691 .set_rxfh = bnx2x_set_rxfh, 3692 .get_channels = bnx2x_get_channels, 3693 .set_channels = bnx2x_set_channels, 3694 .get_module_info = bnx2x_get_module_info, 3695 .get_module_eeprom = bnx2x_get_module_eeprom, 3696 .get_eee = bnx2x_get_eee, 3697 .set_eee = bnx2x_set_eee, 3698 .get_ts_info = bnx2x_get_ts_info, 3699 .get_link_ksettings = bnx2x_get_link_ksettings, 3700 .set_link_ksettings = bnx2x_set_link_ksettings, 3701 }; 3702 3703 static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3704 .get_drvinfo = bnx2x_get_drvinfo, 3705 .get_msglevel = bnx2x_get_msglevel, 3706 .set_msglevel = bnx2x_set_msglevel, 3707 .get_link = bnx2x_get_link, 3708 .get_coalesce = bnx2x_get_coalesce, 3709 .get_ringparam = bnx2x_get_ringparam, 3710 .set_ringparam = bnx2x_set_ringparam, 3711 .get_sset_count = bnx2x_get_sset_count, 3712 .get_strings = bnx2x_get_strings, 3713 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3714 .get_rxnfc = bnx2x_get_rxnfc, 3715 .set_rxnfc = bnx2x_set_rxnfc, 3716 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3717 .get_rxfh = bnx2x_get_rxfh, 3718 .set_rxfh = bnx2x_set_rxfh, 3719 .get_channels = bnx2x_get_channels, 3720 .set_channels = bnx2x_set_channels, 3721 .get_link_ksettings = bnx2x_get_vf_link_ksettings, 3722 }; 3723 3724 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3725 { 3726 netdev->ethtool_ops = (IS_PF(bp)) ? 3727 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3728 } 3729