1 /* bnx2x_ethtool.c: QLogic Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  * Copyright (c) 2014 QLogic Corporation
5  * All rights reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12  * Written by: Eliezer Tamir
13  * Based on code from Michael Chan's bnx2 driver
14  * UDP CSUM errata workaround by Arik Gendelman
15  * Slowpath and fastpath rework by Vladislav Zolotarov
16  * Statistics and Link management by Yitchak Gertner
17  *
18  */
19 
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 
22 #include <linux/ethtool.h>
23 #include <linux/netdevice.h>
24 #include <linux/types.h>
25 #include <linux/sched.h>
26 #include <linux/crc32.h>
27 #include "bnx2x.h"
28 #include "bnx2x_cmn.h"
29 #include "bnx2x_dump.h"
30 #include "bnx2x_init.h"
31 
32 /* Note: in the format strings below %s is replaced by the queue-name which is
33  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
34  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
35  */
36 #define MAX_QUEUE_NAME_LEN	4
37 static const struct {
38 	long offset;
39 	int size;
40 	char string[ETH_GSTRING_LEN];
41 } bnx2x_q_stats_arr[] = {
42 /* 1 */	{ Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
43 	{ Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 						8, "[%s]: rx_ucast_packets" },
45 	{ Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 						8, "[%s]: rx_mcast_packets" },
47 	{ Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 						8, "[%s]: rx_bcast_packets" },
49 	{ Q_STATS_OFFSET32(no_buff_discard_hi),	8, "[%s]: rx_discards" },
50 	{ Q_STATS_OFFSET32(rx_err_discard_pkt),
51 					 4, "[%s]: rx_phy_ip_err_discards"},
52 	{ Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 					 4, "[%s]: rx_skb_alloc_discard" },
54 	{ Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
55 	{ Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
56 	{ Q_STATS_OFFSET32(total_bytes_transmitted_hi),	8, "[%s]: tx_bytes" },
57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
58 						8, "[%s]: tx_ucast_packets" },
59 	{ Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 						8, "[%s]: tx_mcast_packets" },
61 	{ Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
62 						8, "[%s]: tx_bcast_packets" },
63 	{ Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 						8, "[%s]: tpa_aggregations" },
65 	{ Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 					8, "[%s]: tpa_aggregated_frames"},
67 	{ Q_STATS_OFFSET32(total_tpa_bytes_hi),	8, "[%s]: tpa_bytes"},
68 	{ Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 					4, "[%s]: driver_filtered_tx_pkt" }
70 };
71 
72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
73 
74 static const struct {
75 	long offset;
76 	int size;
77 	bool is_port_stat;
78 	char string[ETH_GSTRING_LEN];
79 } bnx2x_stats_arr[] = {
80 /* 1 */	{ STATS_OFFSET32(total_bytes_received_hi),
81 				8, false, "rx_bytes" },
82 	{ STATS_OFFSET32(error_bytes_received_hi),
83 				8, false, "rx_error_bytes" },
84 	{ STATS_OFFSET32(total_unicast_packets_received_hi),
85 				8, false, "rx_ucast_packets" },
86 	{ STATS_OFFSET32(total_multicast_packets_received_hi),
87 				8, false, "rx_mcast_packets" },
88 	{ STATS_OFFSET32(total_broadcast_packets_received_hi),
89 				8, false, "rx_bcast_packets" },
90 	{ STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
91 				8, true, "rx_crc_errors" },
92 	{ STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
93 				8, true, "rx_align_errors" },
94 	{ STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
95 				8, true, "rx_undersize_packets" },
96 	{ STATS_OFFSET32(etherstatsoverrsizepkts_hi),
97 				8, true, "rx_oversize_packets" },
98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
99 				8, true, "rx_fragments" },
100 	{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
101 				8, true, "rx_jabbers" },
102 	{ STATS_OFFSET32(no_buff_discard_hi),
103 				8, false, "rx_discards" },
104 	{ STATS_OFFSET32(mac_filter_discard),
105 				4, true, "rx_filtered_packets" },
106 	{ STATS_OFFSET32(mf_tag_discard),
107 				4, true, "rx_mf_tag_discard" },
108 	{ STATS_OFFSET32(pfc_frames_received_hi),
109 				8, true, "pfc_frames_received" },
110 	{ STATS_OFFSET32(pfc_frames_sent_hi),
111 				8, true, "pfc_frames_sent" },
112 	{ STATS_OFFSET32(brb_drop_hi),
113 				8, true, "rx_brb_discard" },
114 	{ STATS_OFFSET32(brb_truncate_hi),
115 				8, true, "rx_brb_truncate" },
116 	{ STATS_OFFSET32(pause_frames_received_hi),
117 				8, true, "rx_pause_frames" },
118 	{ STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
119 				8, true, "rx_mac_ctrl_frames" },
120 	{ STATS_OFFSET32(nig_timer_max),
121 				4, true, "rx_constant_pause_events" },
122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
123 				4, false, "rx_phy_ip_err_discards"},
124 	{ STATS_OFFSET32(rx_skb_alloc_failed),
125 				4, false, "rx_skb_alloc_discard" },
126 	{ STATS_OFFSET32(hw_csum_err),
127 				4, false, "rx_csum_offload_errors" },
128 	{ STATS_OFFSET32(driver_xoff),
129 				4, false, "tx_exhaustion_events" },
130 	{ STATS_OFFSET32(total_bytes_transmitted_hi),
131 				8, false, "tx_bytes" },
132 	{ STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 				8, true, "tx_error_bytes" },
134 	{ STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 				8, false, "tx_ucast_packets" },
136 	{ STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 				8, false, "tx_mcast_packets" },
138 	{ STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 				8, false, "tx_bcast_packets" },
140 	{ STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 				8, true, "tx_mac_errors" },
142 	{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 				8, true, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 				8, true, "tx_single_collisions" },
146 	{ STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 				8, true, "tx_multi_collisions" },
148 	{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 				8, true, "tx_deferred" },
150 	{ STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 				8, true, "tx_excess_collisions" },
152 	{ STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 				8, true, "tx_late_collisions" },
154 	{ STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 				8, true, "tx_total_collisions" },
156 	{ STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 				8, true, "tx_64_byte_packets" },
158 	{ STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 				8, true, "tx_65_to_127_byte_packets" },
160 	{ STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 				8, true, "tx_128_to_255_byte_packets" },
162 	{ STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 				8, true, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 				8, true, "tx_512_to_1023_byte_packets" },
166 	{ STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 				8, true, "tx_1024_to_1522_byte_packets" },
168 	{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 				8, true, "tx_1523_to_9022_byte_packets" },
170 	{ STATS_OFFSET32(pause_frames_sent_hi),
171 				8, true, "tx_pause_frames" },
172 	{ STATS_OFFSET32(total_tpa_aggregations_hi),
173 				8, false, "tpa_aggregations" },
174 	{ STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 				8, false, "tpa_aggregated_frames"},
176 	{ STATS_OFFSET32(total_tpa_bytes_hi),
177 				8, false, "tpa_bytes"},
178 	{ STATS_OFFSET32(recoverable_error),
179 				4, false, "recoverable_errors" },
180 	{ STATS_OFFSET32(unrecoverable_error),
181 				4, false, "unrecoverable_errors" },
182 	{ STATS_OFFSET32(driver_filtered_tx_pkt),
183 				4, false, "driver_filtered_tx_pkt" },
184 	{ STATS_OFFSET32(eee_tx_lpi),
185 				4, true, "Tx LPI entry count"}
186 };
187 
188 #define BNX2X_NUM_STATS		ARRAY_SIZE(bnx2x_stats_arr)
189 
190 static int bnx2x_get_port_type(struct bnx2x *bp)
191 {
192 	int port_type;
193 	u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 	switch (bp->link_params.phy[phy_idx].media_type) {
195 	case ETH_PHY_SFPP_10G_FIBER:
196 	case ETH_PHY_SFP_1G_FIBER:
197 	case ETH_PHY_XFP_FIBER:
198 	case ETH_PHY_KR:
199 	case ETH_PHY_CX4:
200 		port_type = PORT_FIBRE;
201 		break;
202 	case ETH_PHY_DA_TWINAX:
203 		port_type = PORT_DA;
204 		break;
205 	case ETH_PHY_BASE_T:
206 		port_type = PORT_TP;
207 		break;
208 	case ETH_PHY_NOT_PRESENT:
209 		port_type = PORT_NONE;
210 		break;
211 	case ETH_PHY_UNSPECIFIED:
212 	default:
213 		port_type = PORT_OTHER;
214 		break;
215 	}
216 	return port_type;
217 }
218 
219 static int bnx2x_get_vf_link_ksettings(struct net_device *dev,
220 				       struct ethtool_link_ksettings *cmd)
221 {
222 	struct bnx2x *bp = netdev_priv(dev);
223 	u32 supported, advertising;
224 
225 	ethtool_convert_link_mode_to_legacy_u32(&supported,
226 						cmd->link_modes.supported);
227 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
228 						cmd->link_modes.advertising);
229 
230 	if (bp->state == BNX2X_STATE_OPEN) {
231 		if (test_bit(BNX2X_LINK_REPORT_FD,
232 			     &bp->vf_link_vars.link_report_flags))
233 			cmd->base.duplex = DUPLEX_FULL;
234 		else
235 			cmd->base.duplex = DUPLEX_HALF;
236 
237 		cmd->base.speed = bp->vf_link_vars.line_speed;
238 	} else {
239 		cmd->base.duplex = DUPLEX_UNKNOWN;
240 		cmd->base.speed = SPEED_UNKNOWN;
241 	}
242 
243 	cmd->base.port		= PORT_OTHER;
244 	cmd->base.phy_address	= 0;
245 	cmd->base.autoneg	= AUTONEG_DISABLE;
246 
247 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
248 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
249 	   "  duplex %d  port %d  phy_address %d\n"
250 	   "  autoneg %d\n",
251 	   cmd->base.cmd, supported, advertising,
252 	   cmd->base.speed,
253 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
254 	   cmd->base.autoneg);
255 
256 	return 0;
257 }
258 
259 static int bnx2x_get_link_ksettings(struct net_device *dev,
260 				    struct ethtool_link_ksettings *cmd)
261 {
262 	struct bnx2x *bp = netdev_priv(dev);
263 	int cfg_idx = bnx2x_get_link_cfg_idx(bp);
264 	u32 media_type;
265 	u32 supported, advertising, lp_advertising;
266 
267 	ethtool_convert_link_mode_to_legacy_u32(&lp_advertising,
268 						cmd->link_modes.lp_advertising);
269 
270 	/* Dual Media boards present all available port types */
271 	supported = bp->port.supported[cfg_idx] |
272 		(bp->port.supported[cfg_idx ^ 1] &
273 		 (SUPPORTED_TP | SUPPORTED_FIBRE));
274 	advertising = bp->port.advertising[cfg_idx];
275 	media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
276 	if (media_type == ETH_PHY_SFP_1G_FIBER) {
277 		supported &= ~(SUPPORTED_10000baseT_Full);
278 		advertising &= ~(ADVERTISED_10000baseT_Full);
279 	}
280 
281 	if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
282 	    !(bp->flags & MF_FUNC_DIS)) {
283 		cmd->base.duplex = bp->link_vars.duplex;
284 
285 		if (IS_MF(bp) && !BP_NOMCP(bp))
286 			cmd->base.speed = bnx2x_get_mf_speed(bp);
287 		else
288 			cmd->base.speed = bp->link_vars.line_speed;
289 	} else {
290 		cmd->base.duplex = DUPLEX_UNKNOWN;
291 		cmd->base.speed = SPEED_UNKNOWN;
292 	}
293 
294 	cmd->base.port = bnx2x_get_port_type(bp);
295 
296 	cmd->base.phy_address = bp->mdio.prtad;
297 
298 	if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
299 		cmd->base.autoneg = AUTONEG_ENABLE;
300 	else
301 		cmd->base.autoneg = AUTONEG_DISABLE;
302 
303 	/* Publish LP advertised speeds and FC */
304 	if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
305 		u32 status = bp->link_vars.link_status;
306 
307 		lp_advertising |= ADVERTISED_Autoneg;
308 		if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
309 			lp_advertising |= ADVERTISED_Pause;
310 		if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
311 			lp_advertising |= ADVERTISED_Asym_Pause;
312 
313 		if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
314 			lp_advertising |= ADVERTISED_10baseT_Half;
315 		if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
316 			lp_advertising |= ADVERTISED_10baseT_Full;
317 		if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
318 			lp_advertising |= ADVERTISED_100baseT_Half;
319 		if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
320 			lp_advertising |= ADVERTISED_100baseT_Full;
321 		if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
322 			lp_advertising |= ADVERTISED_1000baseT_Half;
323 		if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
324 			if (media_type == ETH_PHY_KR) {
325 				lp_advertising |=
326 					ADVERTISED_1000baseKX_Full;
327 			} else {
328 				lp_advertising |=
329 					ADVERTISED_1000baseT_Full;
330 			}
331 		}
332 		if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
333 			lp_advertising |= ADVERTISED_2500baseX_Full;
334 		if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
335 			if (media_type == ETH_PHY_KR) {
336 				lp_advertising |=
337 					ADVERTISED_10000baseKR_Full;
338 			} else {
339 				lp_advertising |=
340 					ADVERTISED_10000baseT_Full;
341 			}
342 		}
343 		if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
344 			lp_advertising |= ADVERTISED_20000baseKR2_Full;
345 	}
346 
347 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
348 						supported);
349 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
350 						advertising);
351 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
352 						lp_advertising);
353 
354 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
355 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
356 	   "  duplex %d  port %d  phy_address %d\n"
357 	   "  autoneg %d\n",
358 	   cmd->base.cmd, supported, advertising,
359 	   cmd->base.speed,
360 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
361 	   cmd->base.autoneg);
362 
363 	return 0;
364 }
365 
366 static int bnx2x_set_link_ksettings(struct net_device *dev,
367 				    const struct ethtool_link_ksettings *cmd)
368 {
369 	struct bnx2x *bp = netdev_priv(dev);
370 	u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
371 	u32 speed, phy_idx;
372 	u32 supported;
373 	u8 duplex = cmd->base.duplex;
374 
375 	ethtool_convert_link_mode_to_legacy_u32(&supported,
376 						cmd->link_modes.supported);
377 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
378 						cmd->link_modes.advertising);
379 
380 	if (IS_MF_SD(bp))
381 		return 0;
382 
383 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
384 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
385 	   "  duplex %d  port %d  phy_address %d\n"
386 	   "  autoneg %d\n",
387 	   cmd->base.cmd, supported, advertising,
388 	   cmd->base.speed,
389 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
390 	   cmd->base.autoneg);
391 
392 	speed = cmd->base.speed;
393 
394 	/* If received a request for an unknown duplex, assume full*/
395 	if (duplex == DUPLEX_UNKNOWN)
396 		duplex = DUPLEX_FULL;
397 
398 	if (IS_MF_SI(bp)) {
399 		u32 part;
400 		u32 line_speed = bp->link_vars.line_speed;
401 
402 		/* use 10G if no link detected */
403 		if (!line_speed)
404 			line_speed = 10000;
405 
406 		if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
407 			DP(BNX2X_MSG_ETHTOOL,
408 			   "To set speed BC %X or higher is required, please upgrade BC\n",
409 			   REQ_BC_VER_4_SET_MF_BW);
410 			return -EINVAL;
411 		}
412 
413 		part = (speed * 100) / line_speed;
414 
415 		if (line_speed < speed || !part) {
416 			DP(BNX2X_MSG_ETHTOOL,
417 			   "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
418 			return -EINVAL;
419 		}
420 
421 		if (bp->state != BNX2X_STATE_OPEN)
422 			/* store value for following "load" */
423 			bp->pending_max = part;
424 		else
425 			bnx2x_update_max_mf_config(bp, part);
426 
427 		return 0;
428 	}
429 
430 	cfg_idx = bnx2x_get_link_cfg_idx(bp);
431 	old_multi_phy_config = bp->link_params.multi_phy_config;
432 	if (cmd->base.port != bnx2x_get_port_type(bp)) {
433 		switch (cmd->base.port) {
434 		case PORT_TP:
435 			if (!(bp->port.supported[0] & SUPPORTED_TP ||
436 			      bp->port.supported[1] & SUPPORTED_TP)) {
437 				DP(BNX2X_MSG_ETHTOOL,
438 				   "Unsupported port type\n");
439 				return -EINVAL;
440 			}
441 			bp->link_params.multi_phy_config &=
442 				~PORT_HW_CFG_PHY_SELECTION_MASK;
443 			if (bp->link_params.multi_phy_config &
444 			    PORT_HW_CFG_PHY_SWAPPED_ENABLED)
445 				bp->link_params.multi_phy_config |=
446 				PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
447 			else
448 				bp->link_params.multi_phy_config |=
449 				PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
450 			break;
451 		case PORT_FIBRE:
452 		case PORT_DA:
453 		case PORT_NONE:
454 			if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
455 			      bp->port.supported[1] & SUPPORTED_FIBRE)) {
456 				DP(BNX2X_MSG_ETHTOOL,
457 				   "Unsupported port type\n");
458 				return -EINVAL;
459 			}
460 			bp->link_params.multi_phy_config &=
461 				~PORT_HW_CFG_PHY_SELECTION_MASK;
462 			if (bp->link_params.multi_phy_config &
463 			    PORT_HW_CFG_PHY_SWAPPED_ENABLED)
464 				bp->link_params.multi_phy_config |=
465 				PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
466 			else
467 				bp->link_params.multi_phy_config |=
468 				PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
469 			break;
470 		default:
471 			DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
472 			return -EINVAL;
473 		}
474 	}
475 	/* Save new config in case command complete successfully */
476 	new_multi_phy_config = bp->link_params.multi_phy_config;
477 	/* Get the new cfg_idx */
478 	cfg_idx = bnx2x_get_link_cfg_idx(bp);
479 	/* Restore old config in case command failed */
480 	bp->link_params.multi_phy_config = old_multi_phy_config;
481 	DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
482 
483 	if (cmd->base.autoneg == AUTONEG_ENABLE) {
484 		u32 an_supported_speed = bp->port.supported[cfg_idx];
485 		if (bp->link_params.phy[EXT_PHY1].type ==
486 		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
487 			an_supported_speed |= (SUPPORTED_100baseT_Half |
488 					       SUPPORTED_100baseT_Full);
489 		if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
490 			DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
491 			return -EINVAL;
492 		}
493 
494 		/* advertise the requested speed and duplex if supported */
495 		if (advertising & ~an_supported_speed) {
496 			DP(BNX2X_MSG_ETHTOOL,
497 			   "Advertisement parameters are not supported\n");
498 			return -EINVAL;
499 		}
500 
501 		bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
502 		bp->link_params.req_duplex[cfg_idx] = duplex;
503 		bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
504 					 advertising);
505 		if (advertising) {
506 
507 			bp->link_params.speed_cap_mask[cfg_idx] = 0;
508 			if (advertising & ADVERTISED_10baseT_Half) {
509 				bp->link_params.speed_cap_mask[cfg_idx] |=
510 				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
511 			}
512 			if (advertising & ADVERTISED_10baseT_Full)
513 				bp->link_params.speed_cap_mask[cfg_idx] |=
514 				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
515 
516 			if (advertising & ADVERTISED_100baseT_Full)
517 				bp->link_params.speed_cap_mask[cfg_idx] |=
518 				PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
519 
520 			if (advertising & ADVERTISED_100baseT_Half) {
521 				bp->link_params.speed_cap_mask[cfg_idx] |=
522 				     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
523 			}
524 			if (advertising & ADVERTISED_1000baseT_Half) {
525 				bp->link_params.speed_cap_mask[cfg_idx] |=
526 					PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
527 			}
528 			if (advertising & (ADVERTISED_1000baseT_Full |
529 						ADVERTISED_1000baseKX_Full))
530 				bp->link_params.speed_cap_mask[cfg_idx] |=
531 					PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
532 
533 			if (advertising & (ADVERTISED_10000baseT_Full |
534 						ADVERTISED_10000baseKX4_Full |
535 						ADVERTISED_10000baseKR_Full))
536 				bp->link_params.speed_cap_mask[cfg_idx] |=
537 					PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
538 
539 			if (advertising & ADVERTISED_20000baseKR2_Full)
540 				bp->link_params.speed_cap_mask[cfg_idx] |=
541 					PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
542 		}
543 	} else { /* forced speed */
544 		/* advertise the requested speed and duplex if supported */
545 		switch (speed) {
546 		case SPEED_10:
547 			if (duplex == DUPLEX_FULL) {
548 				if (!(bp->port.supported[cfg_idx] &
549 				      SUPPORTED_10baseT_Full)) {
550 					DP(BNX2X_MSG_ETHTOOL,
551 					   "10M full not supported\n");
552 					return -EINVAL;
553 				}
554 
555 				advertising = (ADVERTISED_10baseT_Full |
556 					       ADVERTISED_TP);
557 			} else {
558 				if (!(bp->port.supported[cfg_idx] &
559 				      SUPPORTED_10baseT_Half)) {
560 					DP(BNX2X_MSG_ETHTOOL,
561 					   "10M half not supported\n");
562 					return -EINVAL;
563 				}
564 
565 				advertising = (ADVERTISED_10baseT_Half |
566 					       ADVERTISED_TP);
567 			}
568 			break;
569 
570 		case SPEED_100:
571 			if (duplex == DUPLEX_FULL) {
572 				if (!(bp->port.supported[cfg_idx] &
573 						SUPPORTED_100baseT_Full)) {
574 					DP(BNX2X_MSG_ETHTOOL,
575 					   "100M full not supported\n");
576 					return -EINVAL;
577 				}
578 
579 				advertising = (ADVERTISED_100baseT_Full |
580 					       ADVERTISED_TP);
581 			} else {
582 				if (!(bp->port.supported[cfg_idx] &
583 						SUPPORTED_100baseT_Half)) {
584 					DP(BNX2X_MSG_ETHTOOL,
585 					   "100M half not supported\n");
586 					return -EINVAL;
587 				}
588 
589 				advertising = (ADVERTISED_100baseT_Half |
590 					       ADVERTISED_TP);
591 			}
592 			break;
593 
594 		case SPEED_1000:
595 			if (duplex != DUPLEX_FULL) {
596 				DP(BNX2X_MSG_ETHTOOL,
597 				   "1G half not supported\n");
598 				return -EINVAL;
599 			}
600 
601 			if (bp->port.supported[cfg_idx] &
602 			     SUPPORTED_1000baseT_Full) {
603 				advertising = (ADVERTISED_1000baseT_Full |
604 					       ADVERTISED_TP);
605 
606 			} else if (bp->port.supported[cfg_idx] &
607 				   SUPPORTED_1000baseKX_Full) {
608 				advertising = ADVERTISED_1000baseKX_Full;
609 			} else {
610 				DP(BNX2X_MSG_ETHTOOL,
611 				   "1G full not supported\n");
612 				return -EINVAL;
613 			}
614 
615 			break;
616 
617 		case SPEED_2500:
618 			if (duplex != DUPLEX_FULL) {
619 				DP(BNX2X_MSG_ETHTOOL,
620 				   "2.5G half not supported\n");
621 				return -EINVAL;
622 			}
623 
624 			if (!(bp->port.supported[cfg_idx]
625 			      & SUPPORTED_2500baseX_Full)) {
626 				DP(BNX2X_MSG_ETHTOOL,
627 				   "2.5G full not supported\n");
628 				return -EINVAL;
629 			}
630 
631 			advertising = (ADVERTISED_2500baseX_Full |
632 				       ADVERTISED_TP);
633 			break;
634 
635 		case SPEED_10000:
636 			if (duplex != DUPLEX_FULL) {
637 				DP(BNX2X_MSG_ETHTOOL,
638 				   "10G half not supported\n");
639 				return -EINVAL;
640 			}
641 			phy_idx = bnx2x_get_cur_phy_idx(bp);
642 			if ((bp->port.supported[cfg_idx] &
643 			     SUPPORTED_10000baseT_Full) &&
644 			    (bp->link_params.phy[phy_idx].media_type !=
645 			     ETH_PHY_SFP_1G_FIBER)) {
646 				advertising = (ADVERTISED_10000baseT_Full |
647 					       ADVERTISED_FIBRE);
648 			} else if (bp->port.supported[cfg_idx] &
649 			       SUPPORTED_10000baseKR_Full) {
650 				advertising = (ADVERTISED_10000baseKR_Full |
651 					       ADVERTISED_FIBRE);
652 			} else {
653 				DP(BNX2X_MSG_ETHTOOL,
654 				   "10G full not supported\n");
655 				return -EINVAL;
656 			}
657 
658 			break;
659 
660 		default:
661 			DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
662 			return -EINVAL;
663 		}
664 
665 		bp->link_params.req_line_speed[cfg_idx] = speed;
666 		bp->link_params.req_duplex[cfg_idx] = duplex;
667 		bp->port.advertising[cfg_idx] = advertising;
668 	}
669 
670 	DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
671 	   "  req_duplex %d  advertising 0x%x\n",
672 	   bp->link_params.req_line_speed[cfg_idx],
673 	   bp->link_params.req_duplex[cfg_idx],
674 	   bp->port.advertising[cfg_idx]);
675 
676 	/* Set new config */
677 	bp->link_params.multi_phy_config = new_multi_phy_config;
678 	if (netif_running(dev)) {
679 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
680 		bnx2x_force_link_reset(bp);
681 		bnx2x_link_set(bp);
682 	}
683 
684 	return 0;
685 }
686 
687 #define DUMP_ALL_PRESETS		0x1FFF
688 #define DUMP_MAX_PRESETS		13
689 
690 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
691 {
692 	if (CHIP_IS_E1(bp))
693 		return dump_num_registers[0][preset-1];
694 	else if (CHIP_IS_E1H(bp))
695 		return dump_num_registers[1][preset-1];
696 	else if (CHIP_IS_E2(bp))
697 		return dump_num_registers[2][preset-1];
698 	else if (CHIP_IS_E3A0(bp))
699 		return dump_num_registers[3][preset-1];
700 	else if (CHIP_IS_E3B0(bp))
701 		return dump_num_registers[4][preset-1];
702 	else
703 		return 0;
704 }
705 
706 static int __bnx2x_get_regs_len(struct bnx2x *bp)
707 {
708 	u32 preset_idx;
709 	int regdump_len = 0;
710 
711 	/* Calculate the total preset regs length */
712 	for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
713 		regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
714 
715 	return regdump_len;
716 }
717 
718 static int bnx2x_get_regs_len(struct net_device *dev)
719 {
720 	struct bnx2x *bp = netdev_priv(dev);
721 	int regdump_len = 0;
722 
723 	if (IS_VF(bp))
724 		return 0;
725 
726 	regdump_len = __bnx2x_get_regs_len(bp);
727 	regdump_len *= 4;
728 	regdump_len += sizeof(struct dump_header);
729 
730 	return regdump_len;
731 }
732 
733 #define IS_E1_REG(chips)	((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
734 #define IS_E1H_REG(chips)	((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
735 #define IS_E2_REG(chips)	((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
736 #define IS_E3A0_REG(chips)	((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
737 #define IS_E3B0_REG(chips)	((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
738 
739 #define IS_REG_IN_PRESET(presets, idx)  \
740 		((presets & (1 << (idx-1))) == (1 << (idx-1)))
741 
742 /******* Paged registers info selectors ********/
743 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
744 {
745 	if (CHIP_IS_E2(bp))
746 		return page_vals_e2;
747 	else if (CHIP_IS_E3(bp))
748 		return page_vals_e3;
749 	else
750 		return NULL;
751 }
752 
753 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
754 {
755 	if (CHIP_IS_E2(bp))
756 		return PAGE_MODE_VALUES_E2;
757 	else if (CHIP_IS_E3(bp))
758 		return PAGE_MODE_VALUES_E3;
759 	else
760 		return 0;
761 }
762 
763 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
764 {
765 	if (CHIP_IS_E2(bp))
766 		return page_write_regs_e2;
767 	else if (CHIP_IS_E3(bp))
768 		return page_write_regs_e3;
769 	else
770 		return NULL;
771 }
772 
773 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
774 {
775 	if (CHIP_IS_E2(bp))
776 		return PAGE_WRITE_REGS_E2;
777 	else if (CHIP_IS_E3(bp))
778 		return PAGE_WRITE_REGS_E3;
779 	else
780 		return 0;
781 }
782 
783 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
784 {
785 	if (CHIP_IS_E2(bp))
786 		return page_read_regs_e2;
787 	else if (CHIP_IS_E3(bp))
788 		return page_read_regs_e3;
789 	else
790 		return NULL;
791 }
792 
793 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
794 {
795 	if (CHIP_IS_E2(bp))
796 		return PAGE_READ_REGS_E2;
797 	else if (CHIP_IS_E3(bp))
798 		return PAGE_READ_REGS_E3;
799 	else
800 		return 0;
801 }
802 
803 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
804 				       const struct reg_addr *reg_info)
805 {
806 	if (CHIP_IS_E1(bp))
807 		return IS_E1_REG(reg_info->chips);
808 	else if (CHIP_IS_E1H(bp))
809 		return IS_E1H_REG(reg_info->chips);
810 	else if (CHIP_IS_E2(bp))
811 		return IS_E2_REG(reg_info->chips);
812 	else if (CHIP_IS_E3A0(bp))
813 		return IS_E3A0_REG(reg_info->chips);
814 	else if (CHIP_IS_E3B0(bp))
815 		return IS_E3B0_REG(reg_info->chips);
816 	else
817 		return false;
818 }
819 
820 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
821 	const struct wreg_addr *wreg_info)
822 {
823 	if (CHIP_IS_E1(bp))
824 		return IS_E1_REG(wreg_info->chips);
825 	else if (CHIP_IS_E1H(bp))
826 		return IS_E1H_REG(wreg_info->chips);
827 	else if (CHIP_IS_E2(bp))
828 		return IS_E2_REG(wreg_info->chips);
829 	else if (CHIP_IS_E3A0(bp))
830 		return IS_E3A0_REG(wreg_info->chips);
831 	else if (CHIP_IS_E3B0(bp))
832 		return IS_E3B0_REG(wreg_info->chips);
833 	else
834 		return false;
835 }
836 
837 /**
838  * bnx2x_read_pages_regs - read "paged" registers
839  *
840  * @bp		device handle
841  * @p		output buffer
842  *
843  * Reads "paged" memories: memories that may only be read by first writing to a
844  * specific address ("write address") and then reading from a specific address
845  * ("read address"). There may be more than one write address per "page" and
846  * more than one read address per write address.
847  */
848 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
849 {
850 	u32 i, j, k, n;
851 
852 	/* addresses of the paged registers */
853 	const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
854 	/* number of paged registers */
855 	int num_pages = __bnx2x_get_page_reg_num(bp);
856 	/* write addresses */
857 	const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
858 	/* number of write addresses */
859 	int write_num = __bnx2x_get_page_write_num(bp);
860 	/* read addresses info */
861 	const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
862 	/* number of read addresses */
863 	int read_num = __bnx2x_get_page_read_num(bp);
864 	u32 addr, size;
865 
866 	for (i = 0; i < num_pages; i++) {
867 		for (j = 0; j < write_num; j++) {
868 			REG_WR(bp, write_addr[j], page_addr[i]);
869 
870 			for (k = 0; k < read_num; k++) {
871 				if (IS_REG_IN_PRESET(read_addr[k].presets,
872 						     preset)) {
873 					size = read_addr[k].size;
874 					for (n = 0; n < size; n++) {
875 						addr = read_addr[k].addr + n*4;
876 						*p++ = REG_RD(bp, addr);
877 					}
878 				}
879 			}
880 		}
881 	}
882 }
883 
884 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
885 {
886 	u32 i, j, addr;
887 	const struct wreg_addr *wreg_addr_p = NULL;
888 
889 	if (CHIP_IS_E1(bp))
890 		wreg_addr_p = &wreg_addr_e1;
891 	else if (CHIP_IS_E1H(bp))
892 		wreg_addr_p = &wreg_addr_e1h;
893 	else if (CHIP_IS_E2(bp))
894 		wreg_addr_p = &wreg_addr_e2;
895 	else if (CHIP_IS_E3A0(bp))
896 		wreg_addr_p = &wreg_addr_e3;
897 	else if (CHIP_IS_E3B0(bp))
898 		wreg_addr_p = &wreg_addr_e3b0;
899 
900 	/* Read the idle_chk registers */
901 	for (i = 0; i < IDLE_REGS_COUNT; i++) {
902 		if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
903 		    IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
904 			for (j = 0; j < idle_reg_addrs[i].size; j++)
905 				*p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
906 		}
907 	}
908 
909 	/* Read the regular registers */
910 	for (i = 0; i < REGS_COUNT; i++) {
911 		if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
912 		    IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
913 			for (j = 0; j < reg_addrs[i].size; j++)
914 				*p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
915 		}
916 	}
917 
918 	/* Read the CAM registers */
919 	if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
920 	    IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
921 		for (i = 0; i < wreg_addr_p->size; i++) {
922 			*p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
923 
924 			/* In case of wreg_addr register, read additional
925 			   registers from read_regs array
926 			*/
927 			for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
928 				addr = *(wreg_addr_p->read_regs);
929 				*p++ = REG_RD(bp, addr + j*4);
930 			}
931 		}
932 	}
933 
934 	/* Paged registers are supported in E2 & E3 only */
935 	if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
936 		/* Read "paged" registers */
937 		bnx2x_read_pages_regs(bp, p, preset);
938 	}
939 
940 	return 0;
941 }
942 
943 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
944 {
945 	u32 preset_idx;
946 
947 	/* Read all registers, by reading all preset registers */
948 	for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
949 		/* Skip presets with IOR */
950 		if ((preset_idx == 2) ||
951 		    (preset_idx == 5) ||
952 		    (preset_idx == 8) ||
953 		    (preset_idx == 11))
954 			continue;
955 		__bnx2x_get_preset_regs(bp, p, preset_idx);
956 		p += __bnx2x_get_preset_regs_len(bp, preset_idx);
957 	}
958 }
959 
960 static void bnx2x_get_regs(struct net_device *dev,
961 			   struct ethtool_regs *regs, void *_p)
962 {
963 	u32 *p = _p;
964 	struct bnx2x *bp = netdev_priv(dev);
965 	struct dump_header dump_hdr = {0};
966 
967 	regs->version = 2;
968 	memset(p, 0, regs->len);
969 
970 	if (!netif_running(bp->dev))
971 		return;
972 
973 	/* Disable parity attentions as long as following dump may
974 	 * cause false alarms by reading never written registers. We
975 	 * will re-enable parity attentions right after the dump.
976 	 */
977 
978 	bnx2x_disable_blocks_parity(bp);
979 
980 	dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
981 	dump_hdr.preset = DUMP_ALL_PRESETS;
982 	dump_hdr.version = BNX2X_DUMP_VERSION;
983 
984 	/* dump_meta_data presents OR of CHIP and PATH. */
985 	if (CHIP_IS_E1(bp)) {
986 		dump_hdr.dump_meta_data = DUMP_CHIP_E1;
987 	} else if (CHIP_IS_E1H(bp)) {
988 		dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
989 	} else if (CHIP_IS_E2(bp)) {
990 		dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
991 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
992 	} else if (CHIP_IS_E3A0(bp)) {
993 		dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
994 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
995 	} else if (CHIP_IS_E3B0(bp)) {
996 		dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
997 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
998 	}
999 
1000 	memcpy(p, &dump_hdr, sizeof(struct dump_header));
1001 	p += dump_hdr.header_size + 1;
1002 
1003 	/* This isn't really an error, but since attention handling is going
1004 	 * to print the GRC timeouts using this macro, we use the same.
1005 	 */
1006 	BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
1007 
1008 	/* Actually read the registers */
1009 	__bnx2x_get_regs(bp, p);
1010 
1011 	/* Re-enable parity attentions */
1012 	bnx2x_clear_blocks_parity(bp);
1013 	bnx2x_enable_blocks_parity(bp);
1014 }
1015 
1016 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
1017 {
1018 	struct bnx2x *bp = netdev_priv(dev);
1019 	int regdump_len = 0;
1020 
1021 	regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1022 	regdump_len *= 4;
1023 	regdump_len += sizeof(struct dump_header);
1024 
1025 	return regdump_len;
1026 }
1027 
1028 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1029 {
1030 	struct bnx2x *bp = netdev_priv(dev);
1031 
1032 	/* Use the ethtool_dump "flag" field as the dump preset index */
1033 	if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1034 		return -EINVAL;
1035 
1036 	bp->dump_preset_idx = val->flag;
1037 	return 0;
1038 }
1039 
1040 static int bnx2x_get_dump_flag(struct net_device *dev,
1041 			       struct ethtool_dump *dump)
1042 {
1043 	struct bnx2x *bp = netdev_priv(dev);
1044 
1045 	dump->version = BNX2X_DUMP_VERSION;
1046 	dump->flag = bp->dump_preset_idx;
1047 	/* Calculate the requested preset idx length */
1048 	dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1049 	DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1050 	   bp->dump_preset_idx, dump->len);
1051 	return 0;
1052 }
1053 
1054 static int bnx2x_get_dump_data(struct net_device *dev,
1055 			       struct ethtool_dump *dump,
1056 			       void *buffer)
1057 {
1058 	u32 *p = buffer;
1059 	struct bnx2x *bp = netdev_priv(dev);
1060 	struct dump_header dump_hdr = {0};
1061 
1062 	/* Disable parity attentions as long as following dump may
1063 	 * cause false alarms by reading never written registers. We
1064 	 * will re-enable parity attentions right after the dump.
1065 	 */
1066 
1067 	bnx2x_disable_blocks_parity(bp);
1068 
1069 	dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1070 	dump_hdr.preset = bp->dump_preset_idx;
1071 	dump_hdr.version = BNX2X_DUMP_VERSION;
1072 
1073 	DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1074 
1075 	/* dump_meta_data presents OR of CHIP and PATH. */
1076 	if (CHIP_IS_E1(bp)) {
1077 		dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1078 	} else if (CHIP_IS_E1H(bp)) {
1079 		dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1080 	} else if (CHIP_IS_E2(bp)) {
1081 		dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1082 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1083 	} else if (CHIP_IS_E3A0(bp)) {
1084 		dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1085 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1086 	} else if (CHIP_IS_E3B0(bp)) {
1087 		dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1088 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1089 	}
1090 
1091 	memcpy(p, &dump_hdr, sizeof(struct dump_header));
1092 	p += dump_hdr.header_size + 1;
1093 
1094 	/* Actually read the registers */
1095 	__bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1096 
1097 	/* Re-enable parity attentions */
1098 	bnx2x_clear_blocks_parity(bp);
1099 	bnx2x_enable_blocks_parity(bp);
1100 
1101 	return 0;
1102 }
1103 
1104 static void bnx2x_get_drvinfo(struct net_device *dev,
1105 			      struct ethtool_drvinfo *info)
1106 {
1107 	struct bnx2x *bp = netdev_priv(dev);
1108 	char version[ETHTOOL_FWVERS_LEN];
1109 	int ext_dev_info_offset;
1110 	u32 mbi;
1111 
1112 	strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1113 	strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1114 
1115 	memset(version, 0, sizeof(version));
1116 	snprintf(version, ETHTOOL_FWVERS_LEN, " storm %d.%d.%d.%d",
1117 		 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
1118 		 BCM_5710_FW_REVISION_VERSION, BCM_5710_FW_ENGINEERING_VERSION);
1119 	strlcat(info->version, version, sizeof(info->version));
1120 
1121 	if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) {
1122 		ext_dev_info_offset = SHMEM2_RD(bp,
1123 						extended_dev_info_shared_addr);
1124 		mbi = REG_RD(bp, ext_dev_info_offset +
1125 			     offsetof(struct extended_dev_info_shared_cfg,
1126 				      mbi_version));
1127 		if (mbi) {
1128 			memset(version, 0, sizeof(version));
1129 			snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ",
1130 				 (mbi & 0xff000000) >> 24,
1131 				 (mbi & 0x00ff0000) >> 16,
1132 				 (mbi & 0x0000ff00) >> 8);
1133 			strlcpy(info->fw_version, version,
1134 				sizeof(info->fw_version));
1135 		}
1136 	}
1137 
1138 	memset(version, 0, sizeof(version));
1139 	bnx2x_fill_fw_str(bp, version, ETHTOOL_FWVERS_LEN);
1140 	strlcat(info->fw_version, version, sizeof(info->fw_version));
1141 
1142 	strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1143 }
1144 
1145 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1146 {
1147 	struct bnx2x *bp = netdev_priv(dev);
1148 
1149 	if (bp->flags & NO_WOL_FLAG) {
1150 		wol->supported = 0;
1151 		wol->wolopts = 0;
1152 	} else {
1153 		wol->supported = WAKE_MAGIC;
1154 		if (bp->wol)
1155 			wol->wolopts = WAKE_MAGIC;
1156 		else
1157 			wol->wolopts = 0;
1158 	}
1159 	memset(&wol->sopass, 0, sizeof(wol->sopass));
1160 }
1161 
1162 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1163 {
1164 	struct bnx2x *bp = netdev_priv(dev);
1165 
1166 	if (wol->wolopts & ~WAKE_MAGIC) {
1167 		DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1168 		return -EINVAL;
1169 	}
1170 
1171 	if (wol->wolopts & WAKE_MAGIC) {
1172 		if (bp->flags & NO_WOL_FLAG) {
1173 			DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1174 			return -EINVAL;
1175 		}
1176 		bp->wol = 1;
1177 	} else
1178 		bp->wol = 0;
1179 
1180 	if (SHMEM2_HAS(bp, curr_cfg))
1181 		SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1182 
1183 	return 0;
1184 }
1185 
1186 static u32 bnx2x_get_msglevel(struct net_device *dev)
1187 {
1188 	struct bnx2x *bp = netdev_priv(dev);
1189 
1190 	return bp->msg_enable;
1191 }
1192 
1193 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1194 {
1195 	struct bnx2x *bp = netdev_priv(dev);
1196 
1197 	if (capable(CAP_NET_ADMIN)) {
1198 		/* dump MCP trace */
1199 		if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1200 			bnx2x_fw_dump_lvl(bp, KERN_INFO);
1201 		bp->msg_enable = level;
1202 	}
1203 }
1204 
1205 static int bnx2x_nway_reset(struct net_device *dev)
1206 {
1207 	struct bnx2x *bp = netdev_priv(dev);
1208 
1209 	if (!bp->port.pmf)
1210 		return 0;
1211 
1212 	if (netif_running(dev)) {
1213 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1214 		bnx2x_force_link_reset(bp);
1215 		bnx2x_link_set(bp);
1216 	}
1217 
1218 	return 0;
1219 }
1220 
1221 static u32 bnx2x_get_link(struct net_device *dev)
1222 {
1223 	struct bnx2x *bp = netdev_priv(dev);
1224 
1225 	if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1226 		return 0;
1227 
1228 	if (IS_VF(bp))
1229 		return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1230 				 &bp->vf_link_vars.link_report_flags);
1231 
1232 	return bp->link_vars.link_up;
1233 }
1234 
1235 static int bnx2x_get_eeprom_len(struct net_device *dev)
1236 {
1237 	struct bnx2x *bp = netdev_priv(dev);
1238 
1239 	return bp->common.flash_size;
1240 }
1241 
1242 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1243  * had we done things the other way around, if two pfs from the same port would
1244  * attempt to access nvram at the same time, we could run into a scenario such
1245  * as:
1246  * pf A takes the port lock.
1247  * pf B succeeds in taking the same lock since they are from the same port.
1248  * pf A takes the per pf misc lock. Performs eeprom access.
1249  * pf A finishes. Unlocks the per pf misc lock.
1250  * Pf B takes the lock and proceeds to perform it's own access.
1251  * pf A unlocks the per port lock, while pf B is still working (!).
1252  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1253  * access corrupted by pf B)
1254  */
1255 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1256 {
1257 	int port = BP_PORT(bp);
1258 	int count, i;
1259 	u32 val;
1260 
1261 	/* acquire HW lock: protect against other PFs in PF Direct Assignment */
1262 	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1263 
1264 	/* adjust timeout for emulation/FPGA */
1265 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1266 	if (CHIP_REV_IS_SLOW(bp))
1267 		count *= 100;
1268 
1269 	/* request access to nvram interface */
1270 	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1271 	       (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1272 
1273 	for (i = 0; i < count*10; i++) {
1274 		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1275 		if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1276 			break;
1277 
1278 		udelay(5);
1279 	}
1280 
1281 	if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1282 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1283 		   "cannot get access to nvram interface\n");
1284 		bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1285 		return -EBUSY;
1286 	}
1287 
1288 	return 0;
1289 }
1290 
1291 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1292 {
1293 	int port = BP_PORT(bp);
1294 	int count, i;
1295 	u32 val;
1296 
1297 	/* adjust timeout for emulation/FPGA */
1298 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1299 	if (CHIP_REV_IS_SLOW(bp))
1300 		count *= 100;
1301 
1302 	/* relinquish nvram interface */
1303 	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1304 	       (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1305 
1306 	for (i = 0; i < count*10; i++) {
1307 		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1308 		if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1309 			break;
1310 
1311 		udelay(5);
1312 	}
1313 
1314 	if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1315 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1316 		   "cannot free access to nvram interface\n");
1317 		return -EBUSY;
1318 	}
1319 
1320 	/* release HW lock: protect against other PFs in PF Direct Assignment */
1321 	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1322 	return 0;
1323 }
1324 
1325 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1326 {
1327 	u32 val;
1328 
1329 	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1330 
1331 	/* enable both bits, even on read */
1332 	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1333 	       (val | MCPR_NVM_ACCESS_ENABLE_EN |
1334 		      MCPR_NVM_ACCESS_ENABLE_WR_EN));
1335 }
1336 
1337 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1338 {
1339 	u32 val;
1340 
1341 	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1342 
1343 	/* disable both bits, even after read */
1344 	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1345 	       (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1346 			MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1347 }
1348 
1349 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1350 				  u32 cmd_flags)
1351 {
1352 	int count, i, rc;
1353 	u32 val;
1354 
1355 	/* build the command word */
1356 	cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1357 
1358 	/* need to clear DONE bit separately */
1359 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1360 
1361 	/* address of the NVRAM to read from */
1362 	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1363 	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1364 
1365 	/* issue a read command */
1366 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1367 
1368 	/* adjust timeout for emulation/FPGA */
1369 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1370 	if (CHIP_REV_IS_SLOW(bp))
1371 		count *= 100;
1372 
1373 	/* wait for completion */
1374 	*ret_val = 0;
1375 	rc = -EBUSY;
1376 	for (i = 0; i < count; i++) {
1377 		udelay(5);
1378 		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1379 
1380 		if (val & MCPR_NVM_COMMAND_DONE) {
1381 			val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1382 			/* we read nvram data in cpu order
1383 			 * but ethtool sees it as an array of bytes
1384 			 * converting to big-endian will do the work
1385 			 */
1386 			*ret_val = cpu_to_be32(val);
1387 			rc = 0;
1388 			break;
1389 		}
1390 	}
1391 	if (rc == -EBUSY)
1392 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1393 		   "nvram read timeout expired\n");
1394 	return rc;
1395 }
1396 
1397 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1398 		     int buf_size)
1399 {
1400 	int rc;
1401 	u32 cmd_flags;
1402 	__be32 val;
1403 
1404 	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1405 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1406 		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1407 		   offset, buf_size);
1408 		return -EINVAL;
1409 	}
1410 
1411 	if (offset + buf_size > bp->common.flash_size) {
1412 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1413 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1414 		   offset, buf_size, bp->common.flash_size);
1415 		return -EINVAL;
1416 	}
1417 
1418 	/* request access to nvram interface */
1419 	rc = bnx2x_acquire_nvram_lock(bp);
1420 	if (rc)
1421 		return rc;
1422 
1423 	/* enable access to nvram interface */
1424 	bnx2x_enable_nvram_access(bp);
1425 
1426 	/* read the first word(s) */
1427 	cmd_flags = MCPR_NVM_COMMAND_FIRST;
1428 	while ((buf_size > sizeof(u32)) && (rc == 0)) {
1429 		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1430 		memcpy(ret_buf, &val, 4);
1431 
1432 		/* advance to the next dword */
1433 		offset += sizeof(u32);
1434 		ret_buf += sizeof(u32);
1435 		buf_size -= sizeof(u32);
1436 		cmd_flags = 0;
1437 	}
1438 
1439 	if (rc == 0) {
1440 		cmd_flags |= MCPR_NVM_COMMAND_LAST;
1441 		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1442 		memcpy(ret_buf, &val, 4);
1443 	}
1444 
1445 	/* disable access to nvram interface */
1446 	bnx2x_disable_nvram_access(bp);
1447 	bnx2x_release_nvram_lock(bp);
1448 
1449 	return rc;
1450 }
1451 
1452 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1453 			      int buf_size)
1454 {
1455 	int rc;
1456 
1457 	rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1458 
1459 	if (!rc) {
1460 		__be32 *be = (__be32 *)buf;
1461 
1462 		while ((buf_size -= 4) >= 0)
1463 			*buf++ = be32_to_cpu(*be++);
1464 	}
1465 
1466 	return rc;
1467 }
1468 
1469 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1470 {
1471 	int rc = 1;
1472 	u16 pm = 0;
1473 	struct net_device *dev = pci_get_drvdata(bp->pdev);
1474 
1475 	if (bp->pdev->pm_cap)
1476 		rc = pci_read_config_word(bp->pdev,
1477 					  bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1478 
1479 	if ((rc && !netif_running(dev)) ||
1480 	    (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1481 		return false;
1482 
1483 	return true;
1484 }
1485 
1486 static int bnx2x_get_eeprom(struct net_device *dev,
1487 			    struct ethtool_eeprom *eeprom, u8 *eebuf)
1488 {
1489 	struct bnx2x *bp = netdev_priv(dev);
1490 
1491 	if (!bnx2x_is_nvm_accessible(bp)) {
1492 		DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1493 		   "cannot access eeprom when the interface is down\n");
1494 		return -EAGAIN;
1495 	}
1496 
1497 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1498 	   "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1499 	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1500 	   eeprom->len, eeprom->len);
1501 
1502 	/* parameters already validated in ethtool_get_eeprom */
1503 
1504 	return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1505 }
1506 
1507 static int bnx2x_get_module_eeprom(struct net_device *dev,
1508 				   struct ethtool_eeprom *ee,
1509 				   u8 *data)
1510 {
1511 	struct bnx2x *bp = netdev_priv(dev);
1512 	int rc = -EINVAL, phy_idx;
1513 	u8 *user_data = data;
1514 	unsigned int start_addr = ee->offset, xfer_size = 0;
1515 
1516 	if (!bnx2x_is_nvm_accessible(bp)) {
1517 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1518 		   "cannot access eeprom when the interface is down\n");
1519 		return -EAGAIN;
1520 	}
1521 
1522 	phy_idx = bnx2x_get_cur_phy_idx(bp);
1523 
1524 	/* Read A0 section */
1525 	if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1526 		/* Limit transfer size to the A0 section boundary */
1527 		if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1528 			xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1529 		else
1530 			xfer_size = ee->len;
1531 		bnx2x_acquire_phy_lock(bp);
1532 		rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1533 						  &bp->link_params,
1534 						  I2C_DEV_ADDR_A0,
1535 						  start_addr,
1536 						  xfer_size,
1537 						  user_data);
1538 		bnx2x_release_phy_lock(bp);
1539 		if (rc) {
1540 			DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1541 
1542 			return -EINVAL;
1543 		}
1544 		user_data += xfer_size;
1545 		start_addr += xfer_size;
1546 	}
1547 
1548 	/* Read A2 section */
1549 	if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1550 	    (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1551 		xfer_size = ee->len - xfer_size;
1552 		/* Limit transfer size to the A2 section boundary */
1553 		if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1554 			xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1555 		start_addr -= ETH_MODULE_SFF_8079_LEN;
1556 		bnx2x_acquire_phy_lock(bp);
1557 		rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1558 						  &bp->link_params,
1559 						  I2C_DEV_ADDR_A2,
1560 						  start_addr,
1561 						  xfer_size,
1562 						  user_data);
1563 		bnx2x_release_phy_lock(bp);
1564 		if (rc) {
1565 			DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1566 			return -EINVAL;
1567 		}
1568 	}
1569 	return rc;
1570 }
1571 
1572 static int bnx2x_get_module_info(struct net_device *dev,
1573 				 struct ethtool_modinfo *modinfo)
1574 {
1575 	struct bnx2x *bp = netdev_priv(dev);
1576 	int phy_idx, rc;
1577 	u8 sff8472_comp, diag_type;
1578 
1579 	if (!bnx2x_is_nvm_accessible(bp)) {
1580 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1581 		   "cannot access eeprom when the interface is down\n");
1582 		return -EAGAIN;
1583 	}
1584 	phy_idx = bnx2x_get_cur_phy_idx(bp);
1585 	bnx2x_acquire_phy_lock(bp);
1586 	rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1587 					  &bp->link_params,
1588 					  I2C_DEV_ADDR_A0,
1589 					  SFP_EEPROM_SFF_8472_COMP_ADDR,
1590 					  SFP_EEPROM_SFF_8472_COMP_SIZE,
1591 					  &sff8472_comp);
1592 	bnx2x_release_phy_lock(bp);
1593 	if (rc) {
1594 		DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1595 		return -EINVAL;
1596 	}
1597 
1598 	bnx2x_acquire_phy_lock(bp);
1599 	rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1600 					  &bp->link_params,
1601 					  I2C_DEV_ADDR_A0,
1602 					  SFP_EEPROM_DIAG_TYPE_ADDR,
1603 					  SFP_EEPROM_DIAG_TYPE_SIZE,
1604 					  &diag_type);
1605 	bnx2x_release_phy_lock(bp);
1606 	if (rc) {
1607 		DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1608 		return -EINVAL;
1609 	}
1610 
1611 	if (!sff8472_comp ||
1612 	    (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1613 		modinfo->type = ETH_MODULE_SFF_8079;
1614 		modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1615 	} else {
1616 		modinfo->type = ETH_MODULE_SFF_8472;
1617 		modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1618 	}
1619 	return 0;
1620 }
1621 
1622 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1623 				   u32 cmd_flags)
1624 {
1625 	int count, i, rc;
1626 
1627 	/* build the command word */
1628 	cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1629 
1630 	/* need to clear DONE bit separately */
1631 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1632 
1633 	/* write the data */
1634 	REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1635 
1636 	/* address of the NVRAM to write to */
1637 	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1638 	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1639 
1640 	/* issue the write command */
1641 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1642 
1643 	/* adjust timeout for emulation/FPGA */
1644 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1645 	if (CHIP_REV_IS_SLOW(bp))
1646 		count *= 100;
1647 
1648 	/* wait for completion */
1649 	rc = -EBUSY;
1650 	for (i = 0; i < count; i++) {
1651 		udelay(5);
1652 		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1653 		if (val & MCPR_NVM_COMMAND_DONE) {
1654 			rc = 0;
1655 			break;
1656 		}
1657 	}
1658 
1659 	if (rc == -EBUSY)
1660 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1661 		   "nvram write timeout expired\n");
1662 	return rc;
1663 }
1664 
1665 #define BYTE_OFFSET(offset)		(8 * (offset & 0x03))
1666 
1667 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1668 			      int buf_size)
1669 {
1670 	int rc;
1671 	u32 cmd_flags, align_offset, val;
1672 	__be32 val_be;
1673 
1674 	if (offset + buf_size > bp->common.flash_size) {
1675 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1676 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1677 		   offset, buf_size, bp->common.flash_size);
1678 		return -EINVAL;
1679 	}
1680 
1681 	/* request access to nvram interface */
1682 	rc = bnx2x_acquire_nvram_lock(bp);
1683 	if (rc)
1684 		return rc;
1685 
1686 	/* enable access to nvram interface */
1687 	bnx2x_enable_nvram_access(bp);
1688 
1689 	cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1690 	align_offset = (offset & ~0x03);
1691 	rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1692 
1693 	if (rc == 0) {
1694 		/* nvram data is returned as an array of bytes
1695 		 * convert it back to cpu order
1696 		 */
1697 		val = be32_to_cpu(val_be);
1698 
1699 		val &= ~le32_to_cpu((__force __le32)
1700 				    (0xff << BYTE_OFFSET(offset)));
1701 		val |= le32_to_cpu((__force __le32)
1702 				   (*data_buf << BYTE_OFFSET(offset)));
1703 
1704 		rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1705 					     cmd_flags);
1706 	}
1707 
1708 	/* disable access to nvram interface */
1709 	bnx2x_disable_nvram_access(bp);
1710 	bnx2x_release_nvram_lock(bp);
1711 
1712 	return rc;
1713 }
1714 
1715 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1716 			     int buf_size)
1717 {
1718 	int rc;
1719 	u32 cmd_flags;
1720 	u32 val;
1721 	u32 written_so_far;
1722 
1723 	if (buf_size == 1)	/* ethtool */
1724 		return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1725 
1726 	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1727 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1728 		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1729 		   offset, buf_size);
1730 		return -EINVAL;
1731 	}
1732 
1733 	if (offset + buf_size > bp->common.flash_size) {
1734 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1735 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1736 		   offset, buf_size, bp->common.flash_size);
1737 		return -EINVAL;
1738 	}
1739 
1740 	/* request access to nvram interface */
1741 	rc = bnx2x_acquire_nvram_lock(bp);
1742 	if (rc)
1743 		return rc;
1744 
1745 	/* enable access to nvram interface */
1746 	bnx2x_enable_nvram_access(bp);
1747 
1748 	written_so_far = 0;
1749 	cmd_flags = MCPR_NVM_COMMAND_FIRST;
1750 	while ((written_so_far < buf_size) && (rc == 0)) {
1751 		if (written_so_far == (buf_size - sizeof(u32)))
1752 			cmd_flags |= MCPR_NVM_COMMAND_LAST;
1753 		else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1754 			cmd_flags |= MCPR_NVM_COMMAND_LAST;
1755 		else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1756 			cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1757 
1758 		memcpy(&val, data_buf, 4);
1759 
1760 		/* Notice unlike bnx2x_nvram_read_dword() this will not
1761 		 * change val using be32_to_cpu(), which causes data to flip
1762 		 * if the eeprom is read and then written back. This is due
1763 		 * to tools utilizing this functionality that would break
1764 		 * if this would be resolved.
1765 		 */
1766 		rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1767 
1768 		/* advance to the next dword */
1769 		offset += sizeof(u32);
1770 		data_buf += sizeof(u32);
1771 		written_so_far += sizeof(u32);
1772 
1773 		/* At end of each 4Kb page, release nvram lock to allow MFW
1774 		 * chance to take it for its own use.
1775 		 */
1776 		if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1777 		    (written_so_far < buf_size)) {
1778 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1779 			   "Releasing NVM lock after offset 0x%x\n",
1780 			   (u32)(offset - sizeof(u32)));
1781 			bnx2x_release_nvram_lock(bp);
1782 			usleep_range(1000, 2000);
1783 			rc = bnx2x_acquire_nvram_lock(bp);
1784 			if (rc)
1785 				return rc;
1786 		}
1787 
1788 		cmd_flags = 0;
1789 	}
1790 
1791 	/* disable access to nvram interface */
1792 	bnx2x_disable_nvram_access(bp);
1793 	bnx2x_release_nvram_lock(bp);
1794 
1795 	return rc;
1796 }
1797 
1798 static int bnx2x_set_eeprom(struct net_device *dev,
1799 			    struct ethtool_eeprom *eeprom, u8 *eebuf)
1800 {
1801 	struct bnx2x *bp = netdev_priv(dev);
1802 	int port = BP_PORT(bp);
1803 	int rc = 0;
1804 	u32 ext_phy_config;
1805 
1806 	if (!bnx2x_is_nvm_accessible(bp)) {
1807 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1808 		   "cannot access eeprom when the interface is down\n");
1809 		return -EAGAIN;
1810 	}
1811 
1812 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1813 	   "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1814 	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1815 	   eeprom->len, eeprom->len);
1816 
1817 	/* parameters already validated in ethtool_set_eeprom */
1818 
1819 	/* PHY eeprom can be accessed only by the PMF */
1820 	if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1821 	    !bp->port.pmf) {
1822 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1823 		   "wrong magic or interface is not pmf\n");
1824 		return -EINVAL;
1825 	}
1826 
1827 	ext_phy_config =
1828 		SHMEM_RD(bp,
1829 			 dev_info.port_hw_config[port].external_phy_config);
1830 
1831 	if (eeprom->magic == 0x50485950) {
1832 		/* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1833 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1834 
1835 		bnx2x_acquire_phy_lock(bp);
1836 		rc |= bnx2x_link_reset(&bp->link_params,
1837 				       &bp->link_vars, 0);
1838 		if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1839 					PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1840 			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1841 				       MISC_REGISTERS_GPIO_HIGH, port);
1842 		bnx2x_release_phy_lock(bp);
1843 		bnx2x_link_report(bp);
1844 
1845 	} else if (eeprom->magic == 0x50485952) {
1846 		/* 'PHYR' (0x50485952): re-init link after FW upgrade */
1847 		if (bp->state == BNX2X_STATE_OPEN) {
1848 			bnx2x_acquire_phy_lock(bp);
1849 			rc |= bnx2x_link_reset(&bp->link_params,
1850 					       &bp->link_vars, 1);
1851 
1852 			rc |= bnx2x_phy_init(&bp->link_params,
1853 					     &bp->link_vars);
1854 			bnx2x_release_phy_lock(bp);
1855 			bnx2x_calc_fc_adv(bp);
1856 		}
1857 	} else if (eeprom->magic == 0x53985943) {
1858 		/* 'PHYC' (0x53985943): PHY FW upgrade completed */
1859 		if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1860 				       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1861 
1862 			/* DSP Remove Download Mode */
1863 			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1864 				       MISC_REGISTERS_GPIO_LOW, port);
1865 
1866 			bnx2x_acquire_phy_lock(bp);
1867 
1868 			bnx2x_sfx7101_sp_sw_reset(bp,
1869 						&bp->link_params.phy[EXT_PHY1]);
1870 
1871 			/* wait 0.5 sec to allow it to run */
1872 			msleep(500);
1873 			bnx2x_ext_phy_hw_reset(bp, port);
1874 			msleep(500);
1875 			bnx2x_release_phy_lock(bp);
1876 		}
1877 	} else
1878 		rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1879 
1880 	return rc;
1881 }
1882 
1883 static int bnx2x_get_coalesce(struct net_device *dev,
1884 			      struct ethtool_coalesce *coal)
1885 {
1886 	struct bnx2x *bp = netdev_priv(dev);
1887 
1888 	memset(coal, 0, sizeof(struct ethtool_coalesce));
1889 
1890 	coal->rx_coalesce_usecs = bp->rx_ticks;
1891 	coal->tx_coalesce_usecs = bp->tx_ticks;
1892 
1893 	return 0;
1894 }
1895 
1896 static int bnx2x_set_coalesce(struct net_device *dev,
1897 			      struct ethtool_coalesce *coal)
1898 {
1899 	struct bnx2x *bp = netdev_priv(dev);
1900 
1901 	bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1902 	if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1903 		bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1904 
1905 	bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1906 	if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1907 		bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1908 
1909 	if (netif_running(dev))
1910 		bnx2x_update_coalesce(bp);
1911 
1912 	return 0;
1913 }
1914 
1915 static void bnx2x_get_ringparam(struct net_device *dev,
1916 				struct ethtool_ringparam *ering)
1917 {
1918 	struct bnx2x *bp = netdev_priv(dev);
1919 
1920 	ering->rx_max_pending = MAX_RX_AVAIL;
1921 
1922 	/* If size isn't already set, we give an estimation of the number
1923 	 * of buffers we'll have. We're neglecting some possible conditions
1924 	 * [we couldn't know for certain at this point if number of queues
1925 	 * might shrink] but the number would be correct for the likely
1926 	 * scenario.
1927 	 */
1928 	if (bp->rx_ring_size)
1929 		ering->rx_pending = bp->rx_ring_size;
1930 	else if (BNX2X_NUM_RX_QUEUES(bp))
1931 		ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1932 	else
1933 		ering->rx_pending = MAX_RX_AVAIL;
1934 
1935 	ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1936 	ering->tx_pending = bp->tx_ring_size;
1937 }
1938 
1939 static int bnx2x_set_ringparam(struct net_device *dev,
1940 			       struct ethtool_ringparam *ering)
1941 {
1942 	struct bnx2x *bp = netdev_priv(dev);
1943 
1944 	DP(BNX2X_MSG_ETHTOOL,
1945 	   "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1946 	   ering->rx_pending, ering->tx_pending);
1947 
1948 	if (pci_num_vf(bp->pdev)) {
1949 		DP(BNX2X_MSG_IOV,
1950 		   "VFs are enabled, can not change ring parameters\n");
1951 		return -EPERM;
1952 	}
1953 
1954 	if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1955 		DP(BNX2X_MSG_ETHTOOL,
1956 		   "Handling parity error recovery. Try again later\n");
1957 		return -EAGAIN;
1958 	}
1959 
1960 	if ((ering->rx_pending > MAX_RX_AVAIL) ||
1961 	    (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1962 						    MIN_RX_SIZE_TPA)) ||
1963 	    (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1964 	    (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1965 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1966 		return -EINVAL;
1967 	}
1968 
1969 	bp->rx_ring_size = ering->rx_pending;
1970 	bp->tx_ring_size = ering->tx_pending;
1971 
1972 	return bnx2x_reload_if_running(dev);
1973 }
1974 
1975 static void bnx2x_get_pauseparam(struct net_device *dev,
1976 				 struct ethtool_pauseparam *epause)
1977 {
1978 	struct bnx2x *bp = netdev_priv(dev);
1979 	int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1980 	int cfg_reg;
1981 
1982 	epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1983 			   BNX2X_FLOW_CTRL_AUTO);
1984 
1985 	if (!epause->autoneg)
1986 		cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1987 	else
1988 		cfg_reg = bp->link_params.req_fc_auto_adv;
1989 
1990 	epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1991 			    BNX2X_FLOW_CTRL_RX);
1992 	epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1993 			    BNX2X_FLOW_CTRL_TX);
1994 
1995 	DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1996 	   "  autoneg %d  rx_pause %d  tx_pause %d\n",
1997 	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1998 }
1999 
2000 static int bnx2x_set_pauseparam(struct net_device *dev,
2001 				struct ethtool_pauseparam *epause)
2002 {
2003 	struct bnx2x *bp = netdev_priv(dev);
2004 	u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2005 	if (IS_MF(bp))
2006 		return 0;
2007 
2008 	DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
2009 	   "  autoneg %d  rx_pause %d  tx_pause %d\n",
2010 	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
2011 
2012 	bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
2013 
2014 	if (epause->rx_pause)
2015 		bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
2016 
2017 	if (epause->tx_pause)
2018 		bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
2019 
2020 	if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
2021 		bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
2022 
2023 	if (epause->autoneg) {
2024 		if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
2025 			DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
2026 			return -EINVAL;
2027 		}
2028 
2029 		if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
2030 			bp->link_params.req_flow_ctrl[cfg_idx] =
2031 				BNX2X_FLOW_CTRL_AUTO;
2032 		}
2033 		bp->link_params.req_fc_auto_adv = 0;
2034 		if (epause->rx_pause)
2035 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
2036 
2037 		if (epause->tx_pause)
2038 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
2039 
2040 		if (!bp->link_params.req_fc_auto_adv)
2041 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
2042 	}
2043 
2044 	DP(BNX2X_MSG_ETHTOOL,
2045 	   "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
2046 
2047 	if (netif_running(dev)) {
2048 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2049 		bnx2x_force_link_reset(bp);
2050 		bnx2x_link_set(bp);
2051 	}
2052 
2053 	return 0;
2054 }
2055 
2056 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2057 	"register_test (offline)    ",
2058 	"memory_test (offline)      ",
2059 	"int_loopback_test (offline)",
2060 	"ext_loopback_test (offline)",
2061 	"nvram_test (online)        ",
2062 	"interrupt_test (online)    ",
2063 	"link_test (online)         "
2064 };
2065 
2066 enum {
2067 	BNX2X_PRI_FLAG_ISCSI,
2068 	BNX2X_PRI_FLAG_FCOE,
2069 	BNX2X_PRI_FLAG_STORAGE,
2070 	BNX2X_PRI_FLAG_LEN,
2071 };
2072 
2073 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2074 	"iSCSI offload support",
2075 	"FCoE offload support",
2076 	"Storage only interface"
2077 };
2078 
2079 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2080 {
2081 	u32 modes = 0;
2082 
2083 	if (eee_adv & SHMEM_EEE_100M_ADV)
2084 		modes |= ADVERTISED_100baseT_Full;
2085 	if (eee_adv & SHMEM_EEE_1G_ADV)
2086 		modes |= ADVERTISED_1000baseT_Full;
2087 	if (eee_adv & SHMEM_EEE_10G_ADV)
2088 		modes |= ADVERTISED_10000baseT_Full;
2089 
2090 	return modes;
2091 }
2092 
2093 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2094 {
2095 	u32 eee_adv = 0;
2096 	if (modes & ADVERTISED_100baseT_Full)
2097 		eee_adv |= SHMEM_EEE_100M_ADV;
2098 	if (modes & ADVERTISED_1000baseT_Full)
2099 		eee_adv |= SHMEM_EEE_1G_ADV;
2100 	if (modes & ADVERTISED_10000baseT_Full)
2101 		eee_adv |= SHMEM_EEE_10G_ADV;
2102 
2103 	return eee_adv << shift;
2104 }
2105 
2106 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2107 {
2108 	struct bnx2x *bp = netdev_priv(dev);
2109 	u32 eee_cfg;
2110 
2111 	if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2112 		DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2113 		return -EOPNOTSUPP;
2114 	}
2115 
2116 	eee_cfg = bp->link_vars.eee_status;
2117 
2118 	edata->supported =
2119 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2120 				 SHMEM_EEE_SUPPORTED_SHIFT);
2121 
2122 	edata->advertised =
2123 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2124 				 SHMEM_EEE_ADV_STATUS_SHIFT);
2125 	edata->lp_advertised =
2126 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2127 				 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2128 
2129 	/* SHMEM value is in 16u units --> Convert to 1u units. */
2130 	edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2131 
2132 	edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)	? 1 : 0;
2133 	edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)	? 1 : 0;
2134 	edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2135 
2136 	return 0;
2137 }
2138 
2139 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2140 {
2141 	struct bnx2x *bp = netdev_priv(dev);
2142 	u32 eee_cfg;
2143 	u32 advertised;
2144 
2145 	if (IS_MF(bp))
2146 		return 0;
2147 
2148 	if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2149 		DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2150 		return -EOPNOTSUPP;
2151 	}
2152 
2153 	eee_cfg = bp->link_vars.eee_status;
2154 
2155 	if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2156 		DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2157 		return -EOPNOTSUPP;
2158 	}
2159 
2160 	advertised = bnx2x_adv_to_eee(edata->advertised,
2161 				      SHMEM_EEE_ADV_STATUS_SHIFT);
2162 	if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2163 		DP(BNX2X_MSG_ETHTOOL,
2164 		   "Direct manipulation of EEE advertisement is not supported\n");
2165 		return -EINVAL;
2166 	}
2167 
2168 	if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2169 		DP(BNX2X_MSG_ETHTOOL,
2170 		   "Maximal Tx Lpi timer supported is %x(u)\n",
2171 		   EEE_MODE_TIMER_MASK);
2172 		return -EINVAL;
2173 	}
2174 	if (edata->tx_lpi_enabled &&
2175 	    (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2176 		DP(BNX2X_MSG_ETHTOOL,
2177 		   "Minimal Tx Lpi timer supported is %d(u)\n",
2178 		   EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2179 		return -EINVAL;
2180 	}
2181 
2182 	/* All is well; Apply changes*/
2183 	if (edata->eee_enabled)
2184 		bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2185 	else
2186 		bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2187 
2188 	if (edata->tx_lpi_enabled)
2189 		bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2190 	else
2191 		bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2192 
2193 	bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2194 	bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2195 				    EEE_MODE_TIMER_MASK) |
2196 				    EEE_MODE_OVERRIDE_NVRAM |
2197 				    EEE_MODE_OUTPUT_TIME;
2198 
2199 	/* Restart link to propagate changes */
2200 	if (netif_running(dev)) {
2201 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2202 		bnx2x_force_link_reset(bp);
2203 		bnx2x_link_set(bp);
2204 	}
2205 
2206 	return 0;
2207 }
2208 
2209 enum {
2210 	BNX2X_CHIP_E1_OFST = 0,
2211 	BNX2X_CHIP_E1H_OFST,
2212 	BNX2X_CHIP_E2_OFST,
2213 	BNX2X_CHIP_E3_OFST,
2214 	BNX2X_CHIP_E3B0_OFST,
2215 	BNX2X_CHIP_MAX_OFST
2216 };
2217 
2218 #define BNX2X_CHIP_MASK_E1	(1 << BNX2X_CHIP_E1_OFST)
2219 #define BNX2X_CHIP_MASK_E1H	(1 << BNX2X_CHIP_E1H_OFST)
2220 #define BNX2X_CHIP_MASK_E2	(1 << BNX2X_CHIP_E2_OFST)
2221 #define BNX2X_CHIP_MASK_E3	(1 << BNX2X_CHIP_E3_OFST)
2222 #define BNX2X_CHIP_MASK_E3B0	(1 << BNX2X_CHIP_E3B0_OFST)
2223 
2224 #define BNX2X_CHIP_MASK_ALL	((1 << BNX2X_CHIP_MAX_OFST) - 1)
2225 #define BNX2X_CHIP_MASK_E1X	(BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2226 
2227 static int bnx2x_test_registers(struct bnx2x *bp)
2228 {
2229 	int idx, i, rc = -ENODEV;
2230 	u32 wr_val = 0, hw;
2231 	int port = BP_PORT(bp);
2232 	static const struct {
2233 		u32 hw;
2234 		u32 offset0;
2235 		u32 offset1;
2236 		u32 mask;
2237 	} reg_tbl[] = {
2238 /* 0 */		{ BNX2X_CHIP_MASK_ALL,
2239 			BRB1_REG_PAUSE_LOW_THRESHOLD_0,	4, 0x000003ff },
2240 		{ BNX2X_CHIP_MASK_ALL,
2241 			DORQ_REG_DB_ADDR0,		4, 0xffffffff },
2242 		{ BNX2X_CHIP_MASK_E1X,
2243 			HC_REG_AGG_INT_0,		4, 0x000003ff },
2244 		{ BNX2X_CHIP_MASK_ALL,
2245 			PBF_REG_MAC_IF0_ENABLE,		4, 0x00000001 },
2246 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2247 			PBF_REG_P0_INIT_CRD,		4, 0x000007ff },
2248 		{ BNX2X_CHIP_MASK_E3B0,
2249 			PBF_REG_INIT_CRD_Q0,		4, 0x000007ff },
2250 		{ BNX2X_CHIP_MASK_ALL,
2251 			PRS_REG_CID_PORT_0,		4, 0x00ffffff },
2252 		{ BNX2X_CHIP_MASK_ALL,
2253 			PXP2_REG_PSWRQ_CDU0_L2P,	4, 0x000fffff },
2254 		{ BNX2X_CHIP_MASK_ALL,
2255 			PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2256 		{ BNX2X_CHIP_MASK_ALL,
2257 			PXP2_REG_PSWRQ_TM0_L2P,		4, 0x000fffff },
2258 /* 10 */	{ BNX2X_CHIP_MASK_ALL,
2259 			PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2260 		{ BNX2X_CHIP_MASK_ALL,
2261 			PXP2_REG_PSWRQ_TSDM0_L2P,	4, 0x000fffff },
2262 		{ BNX2X_CHIP_MASK_ALL,
2263 			QM_REG_CONNNUM_0,		4, 0x000fffff },
2264 		{ BNX2X_CHIP_MASK_ALL,
2265 			TM_REG_LIN0_MAX_ACTIVE_CID,	4, 0x0003ffff },
2266 		{ BNX2X_CHIP_MASK_ALL,
2267 			SRC_REG_KEYRSS0_0,		40, 0xffffffff },
2268 		{ BNX2X_CHIP_MASK_ALL,
2269 			SRC_REG_KEYRSS0_7,		40, 0xffffffff },
2270 		{ BNX2X_CHIP_MASK_ALL,
2271 			XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2272 		{ BNX2X_CHIP_MASK_ALL,
2273 			XCM_REG_WU_DA_CNT_CMD00,	4, 0x00000003 },
2274 		{ BNX2X_CHIP_MASK_ALL,
2275 			XCM_REG_GLB_DEL_ACK_MAX_CNT_0,	4, 0x000000ff },
2276 		{ BNX2X_CHIP_MASK_ALL,
2277 			NIG_REG_LLH0_T_BIT,		4, 0x00000001 },
2278 /* 20 */	{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2279 			NIG_REG_EMAC0_IN_EN,		4, 0x00000001 },
2280 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2281 			NIG_REG_BMAC0_IN_EN,		4, 0x00000001 },
2282 		{ BNX2X_CHIP_MASK_ALL,
2283 			NIG_REG_XCM0_OUT_EN,		4, 0x00000001 },
2284 		{ BNX2X_CHIP_MASK_ALL,
2285 			NIG_REG_BRB0_OUT_EN,		4, 0x00000001 },
2286 		{ BNX2X_CHIP_MASK_ALL,
2287 			NIG_REG_LLH0_XCM_MASK,		4, 0x00000007 },
2288 		{ BNX2X_CHIP_MASK_ALL,
2289 			NIG_REG_LLH0_ACPI_PAT_6_LEN,	68, 0x000000ff },
2290 		{ BNX2X_CHIP_MASK_ALL,
2291 			NIG_REG_LLH0_ACPI_PAT_0_CRC,	68, 0xffffffff },
2292 		{ BNX2X_CHIP_MASK_ALL,
2293 			NIG_REG_LLH0_DEST_MAC_0_0,	160, 0xffffffff },
2294 		{ BNX2X_CHIP_MASK_ALL,
2295 			NIG_REG_LLH0_DEST_IP_0_1,	160, 0xffffffff },
2296 		{ BNX2X_CHIP_MASK_ALL,
2297 			NIG_REG_LLH0_IPV4_IPV6_0,	160, 0x00000001 },
2298 /* 30 */	{ BNX2X_CHIP_MASK_ALL,
2299 			NIG_REG_LLH0_DEST_UDP_0,	160, 0x0000ffff },
2300 		{ BNX2X_CHIP_MASK_ALL,
2301 			NIG_REG_LLH0_DEST_TCP_0,	160, 0x0000ffff },
2302 		{ BNX2X_CHIP_MASK_ALL,
2303 			NIG_REG_LLH0_VLAN_ID_0,	160, 0x00000fff },
2304 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2305 			NIG_REG_XGXS_SERDES0_MODE_SEL,	4, 0x00000001 },
2306 		{ BNX2X_CHIP_MASK_ALL,
2307 			NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2308 		{ BNX2X_CHIP_MASK_ALL,
2309 			NIG_REG_STATUS_INTERRUPT_PORT0,	4, 0x07ffffff },
2310 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2311 			NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2312 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2313 			NIG_REG_SERDES0_CTRL_PHY_ADDR,	16, 0x0000001f },
2314 
2315 		{ BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2316 	};
2317 
2318 	if (!bnx2x_is_nvm_accessible(bp)) {
2319 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2320 		   "cannot access eeprom when the interface is down\n");
2321 		return rc;
2322 	}
2323 
2324 	if (CHIP_IS_E1(bp))
2325 		hw = BNX2X_CHIP_MASK_E1;
2326 	else if (CHIP_IS_E1H(bp))
2327 		hw = BNX2X_CHIP_MASK_E1H;
2328 	else if (CHIP_IS_E2(bp))
2329 		hw = BNX2X_CHIP_MASK_E2;
2330 	else if (CHIP_IS_E3B0(bp))
2331 		hw = BNX2X_CHIP_MASK_E3B0;
2332 	else /* e3 A0 */
2333 		hw = BNX2X_CHIP_MASK_E3;
2334 
2335 	/* Repeat the test twice:
2336 	 * First by writing 0x00000000, second by writing 0xffffffff
2337 	 */
2338 	for (idx = 0; idx < 2; idx++) {
2339 
2340 		switch (idx) {
2341 		case 0:
2342 			wr_val = 0;
2343 			break;
2344 		case 1:
2345 			wr_val = 0xffffffff;
2346 			break;
2347 		}
2348 
2349 		for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2350 			u32 offset, mask, save_val, val;
2351 			if (!(hw & reg_tbl[i].hw))
2352 				continue;
2353 
2354 			offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2355 			mask = reg_tbl[i].mask;
2356 
2357 			save_val = REG_RD(bp, offset);
2358 
2359 			REG_WR(bp, offset, wr_val & mask);
2360 
2361 			val = REG_RD(bp, offset);
2362 
2363 			/* Restore the original register's value */
2364 			REG_WR(bp, offset, save_val);
2365 
2366 			/* verify value is as expected */
2367 			if ((val & mask) != (wr_val & mask)) {
2368 				DP(BNX2X_MSG_ETHTOOL,
2369 				   "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2370 				   offset, val, wr_val, mask);
2371 				goto test_reg_exit;
2372 			}
2373 		}
2374 	}
2375 
2376 	rc = 0;
2377 
2378 test_reg_exit:
2379 	return rc;
2380 }
2381 
2382 static int bnx2x_test_memory(struct bnx2x *bp)
2383 {
2384 	int i, j, rc = -ENODEV;
2385 	u32 val, index;
2386 	static const struct {
2387 		u32 offset;
2388 		int size;
2389 	} mem_tbl[] = {
2390 		{ CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2391 		{ CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2392 		{ CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2393 		{ DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2394 		{ TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2395 		{ UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2396 		{ XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2397 
2398 		{ 0xffffffff, 0 }
2399 	};
2400 
2401 	static const struct {
2402 		char *name;
2403 		u32 offset;
2404 		u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2405 	} prty_tbl[] = {
2406 		{ "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2407 			{0x3ffc0, 0,   0, 0} },
2408 		{ "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2409 			{0x2,     0x2, 0, 0} },
2410 		{ "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2411 			{0,       0,   0, 0} },
2412 		{ "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2413 			{0x3ffc0, 0,   0, 0} },
2414 		{ "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2415 			{0x3ffc0, 0,   0, 0} },
2416 		{ "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2417 			{0x3ffc1, 0,   0, 0} },
2418 
2419 		{ NULL, 0xffffffff, {0, 0, 0, 0} }
2420 	};
2421 
2422 	if (!bnx2x_is_nvm_accessible(bp)) {
2423 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2424 		   "cannot access eeprom when the interface is down\n");
2425 		return rc;
2426 	}
2427 
2428 	if (CHIP_IS_E1(bp))
2429 		index = BNX2X_CHIP_E1_OFST;
2430 	else if (CHIP_IS_E1H(bp))
2431 		index = BNX2X_CHIP_E1H_OFST;
2432 	else if (CHIP_IS_E2(bp))
2433 		index = BNX2X_CHIP_E2_OFST;
2434 	else /* e3 */
2435 		index = BNX2X_CHIP_E3_OFST;
2436 
2437 	/* pre-Check the parity status */
2438 	for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2439 		val = REG_RD(bp, prty_tbl[i].offset);
2440 		if (val & ~(prty_tbl[i].hw_mask[index])) {
2441 			DP(BNX2X_MSG_ETHTOOL,
2442 			   "%s is 0x%x\n", prty_tbl[i].name, val);
2443 			goto test_mem_exit;
2444 		}
2445 	}
2446 
2447 	/* Go through all the memories */
2448 	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2449 		for (j = 0; j < mem_tbl[i].size; j++)
2450 			REG_RD(bp, mem_tbl[i].offset + j*4);
2451 
2452 	/* Check the parity status */
2453 	for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2454 		val = REG_RD(bp, prty_tbl[i].offset);
2455 		if (val & ~(prty_tbl[i].hw_mask[index])) {
2456 			DP(BNX2X_MSG_ETHTOOL,
2457 			   "%s is 0x%x\n", prty_tbl[i].name, val);
2458 			goto test_mem_exit;
2459 		}
2460 	}
2461 
2462 	rc = 0;
2463 
2464 test_mem_exit:
2465 	return rc;
2466 }
2467 
2468 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2469 {
2470 	int cnt = 1400;
2471 
2472 	if (link_up) {
2473 		while (bnx2x_link_test(bp, is_serdes) && cnt--)
2474 			msleep(20);
2475 
2476 		if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2477 			DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2478 
2479 		cnt = 1400;
2480 		while (!bp->link_vars.link_up && cnt--)
2481 			msleep(20);
2482 
2483 		if (cnt <= 0 && !bp->link_vars.link_up)
2484 			DP(BNX2X_MSG_ETHTOOL,
2485 			   "Timeout waiting for link init\n");
2486 	}
2487 }
2488 
2489 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2490 {
2491 	unsigned int pkt_size, num_pkts, i;
2492 	struct sk_buff *skb;
2493 	unsigned char *packet;
2494 	struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2495 	struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2496 	struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2497 	u16 tx_start_idx, tx_idx;
2498 	u16 rx_start_idx, rx_idx;
2499 	u16 pkt_prod, bd_prod;
2500 	struct sw_tx_bd *tx_buf;
2501 	struct eth_tx_start_bd *tx_start_bd;
2502 	dma_addr_t mapping;
2503 	union eth_rx_cqe *cqe;
2504 	u8 cqe_fp_flags, cqe_fp_type;
2505 	struct sw_rx_bd *rx_buf;
2506 	u16 len;
2507 	int rc = -ENODEV;
2508 	u8 *data;
2509 	struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2510 						       txdata->txq_index);
2511 
2512 	/* check the loopback mode */
2513 	switch (loopback_mode) {
2514 	case BNX2X_PHY_LOOPBACK:
2515 		if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2516 			DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2517 			return -EINVAL;
2518 		}
2519 		break;
2520 	case BNX2X_MAC_LOOPBACK:
2521 		if (CHIP_IS_E3(bp)) {
2522 			int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2523 			if (bp->port.supported[cfg_idx] &
2524 			    (SUPPORTED_10000baseT_Full |
2525 			     SUPPORTED_20000baseMLD2_Full |
2526 			     SUPPORTED_20000baseKR2_Full))
2527 				bp->link_params.loopback_mode = LOOPBACK_XMAC;
2528 			else
2529 				bp->link_params.loopback_mode = LOOPBACK_UMAC;
2530 		} else
2531 			bp->link_params.loopback_mode = LOOPBACK_BMAC;
2532 
2533 		bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2534 		break;
2535 	case BNX2X_EXT_LOOPBACK:
2536 		if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2537 			DP(BNX2X_MSG_ETHTOOL,
2538 			   "Can't configure external loopback\n");
2539 			return -EINVAL;
2540 		}
2541 		break;
2542 	default:
2543 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2544 		return -EINVAL;
2545 	}
2546 
2547 	/* prepare the loopback packet */
2548 	pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2549 		     bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2550 	skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2551 	if (!skb) {
2552 		DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2553 		rc = -ENOMEM;
2554 		goto test_loopback_exit;
2555 	}
2556 	packet = skb_put(skb, pkt_size);
2557 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2558 	eth_zero_addr(packet + ETH_ALEN);
2559 	memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2560 	for (i = ETH_HLEN; i < pkt_size; i++)
2561 		packet[i] = (unsigned char) (i & 0xff);
2562 	mapping = dma_map_single(&bp->pdev->dev, skb->data,
2563 				 skb_headlen(skb), DMA_TO_DEVICE);
2564 	if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2565 		rc = -ENOMEM;
2566 		dev_kfree_skb(skb);
2567 		DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2568 		goto test_loopback_exit;
2569 	}
2570 
2571 	/* send the loopback packet */
2572 	num_pkts = 0;
2573 	tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2574 	rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2575 
2576 	netdev_tx_sent_queue(txq, skb->len);
2577 
2578 	pkt_prod = txdata->tx_pkt_prod++;
2579 	tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2580 	tx_buf->first_bd = txdata->tx_bd_prod;
2581 	tx_buf->skb = skb;
2582 	tx_buf->flags = 0;
2583 
2584 	bd_prod = TX_BD(txdata->tx_bd_prod);
2585 	tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2586 	tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2587 	tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2588 	tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2589 	tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2590 	tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2591 	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2592 	SET_FLAG(tx_start_bd->general_data,
2593 		 ETH_TX_START_BD_HDR_NBDS,
2594 		 1);
2595 	SET_FLAG(tx_start_bd->general_data,
2596 		 ETH_TX_START_BD_PARSE_NBDS,
2597 		 0);
2598 
2599 	/* turn on parsing and get a BD */
2600 	bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2601 
2602 	if (CHIP_IS_E1x(bp)) {
2603 		u16 global_data = 0;
2604 		struct eth_tx_parse_bd_e1x  *pbd_e1x =
2605 			&txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2606 		memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2607 		SET_FLAG(global_data,
2608 			 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2609 		pbd_e1x->global_data = cpu_to_le16(global_data);
2610 	} else {
2611 		u32 parsing_data = 0;
2612 		struct eth_tx_parse_bd_e2  *pbd_e2 =
2613 			&txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2614 		memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2615 		SET_FLAG(parsing_data,
2616 			 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2617 		pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2618 	}
2619 	wmb();
2620 
2621 	txdata->tx_db.data.prod += 2;
2622 	/* make sure descriptor update is observed by the HW */
2623 	wmb();
2624 	DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
2625 
2626 	barrier();
2627 
2628 	num_pkts++;
2629 	txdata->tx_bd_prod += 2; /* start + pbd */
2630 
2631 	udelay(100);
2632 
2633 	tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2634 	if (tx_idx != tx_start_idx + num_pkts)
2635 		goto test_loopback_exit;
2636 
2637 	/* Unlike HC IGU won't generate an interrupt for status block
2638 	 * updates that have been performed while interrupts were
2639 	 * disabled.
2640 	 */
2641 	if (bp->common.int_block == INT_BLOCK_IGU) {
2642 		/* Disable local BHes to prevent a dead-lock situation between
2643 		 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2644 		 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2645 		 */
2646 		local_bh_disable();
2647 		bnx2x_tx_int(bp, txdata);
2648 		local_bh_enable();
2649 	}
2650 
2651 	rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2652 	if (rx_idx != rx_start_idx + num_pkts)
2653 		goto test_loopback_exit;
2654 
2655 	cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2656 	cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2657 	cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2658 	if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2659 		goto test_loopback_rx_exit;
2660 
2661 	len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2662 	if (len != pkt_size)
2663 		goto test_loopback_rx_exit;
2664 
2665 	rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2666 	dma_sync_single_for_cpu(&bp->pdev->dev,
2667 				   dma_unmap_addr(rx_buf, mapping),
2668 				   fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2669 	data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2670 	for (i = ETH_HLEN; i < pkt_size; i++)
2671 		if (*(data + i) != (unsigned char) (i & 0xff))
2672 			goto test_loopback_rx_exit;
2673 
2674 	rc = 0;
2675 
2676 test_loopback_rx_exit:
2677 
2678 	fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2679 	fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2680 	fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2681 	fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2682 
2683 	/* Update producers */
2684 	bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2685 			     fp_rx->rx_sge_prod);
2686 
2687 test_loopback_exit:
2688 	bp->link_params.loopback_mode = LOOPBACK_NONE;
2689 
2690 	return rc;
2691 }
2692 
2693 static int bnx2x_test_loopback(struct bnx2x *bp)
2694 {
2695 	int rc = 0, res;
2696 
2697 	if (BP_NOMCP(bp))
2698 		return rc;
2699 
2700 	if (!netif_running(bp->dev))
2701 		return BNX2X_LOOPBACK_FAILED;
2702 
2703 	bnx2x_netif_stop(bp, 1);
2704 	bnx2x_acquire_phy_lock(bp);
2705 
2706 	res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2707 	if (res) {
2708 		DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2709 		rc |= BNX2X_PHY_LOOPBACK_FAILED;
2710 	}
2711 
2712 	res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2713 	if (res) {
2714 		DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2715 		rc |= BNX2X_MAC_LOOPBACK_FAILED;
2716 	}
2717 
2718 	bnx2x_release_phy_lock(bp);
2719 	bnx2x_netif_start(bp);
2720 
2721 	return rc;
2722 }
2723 
2724 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2725 {
2726 	int rc;
2727 	u8 is_serdes =
2728 		(bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2729 
2730 	if (BP_NOMCP(bp))
2731 		return -ENODEV;
2732 
2733 	if (!netif_running(bp->dev))
2734 		return BNX2X_EXT_LOOPBACK_FAILED;
2735 
2736 	bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2737 	rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2738 	if (rc) {
2739 		DP(BNX2X_MSG_ETHTOOL,
2740 		   "Can't perform self-test, nic_load (for external lb) failed\n");
2741 		return -ENODEV;
2742 	}
2743 	bnx2x_wait_for_link(bp, 1, is_serdes);
2744 
2745 	bnx2x_netif_stop(bp, 1);
2746 
2747 	rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2748 	if (rc)
2749 		DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2750 
2751 	bnx2x_netif_start(bp);
2752 
2753 	return rc;
2754 }
2755 
2756 struct code_entry {
2757 	u32 sram_start_addr;
2758 	u32 code_attribute;
2759 #define CODE_IMAGE_TYPE_MASK			0xf0800003
2760 #define CODE_IMAGE_VNTAG_PROFILES_DATA		0xd0000003
2761 #define CODE_IMAGE_LENGTH_MASK			0x007ffffc
2762 #define CODE_IMAGE_TYPE_EXTENDED_DIR		0xe0000000
2763 	u32 nvm_start_addr;
2764 };
2765 
2766 #define CODE_ENTRY_MAX			16
2767 #define CODE_ENTRY_EXTENDED_DIR_IDX	15
2768 #define MAX_IMAGES_IN_EXTENDED_DIR	64
2769 #define NVRAM_DIR_OFFSET		0x14
2770 
2771 #define EXTENDED_DIR_EXISTS(code)					  \
2772 	((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2773 	 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2774 
2775 #define CRC32_RESIDUAL			0xdebb20e3
2776 #define CRC_BUFF_SIZE			256
2777 
2778 static int bnx2x_nvram_crc(struct bnx2x *bp,
2779 			   int offset,
2780 			   int size,
2781 			   u8 *buff)
2782 {
2783 	u32 crc = ~0;
2784 	int rc = 0, done = 0;
2785 
2786 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2787 	   "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2788 
2789 	while (done < size) {
2790 		int count = min_t(int, size - done, CRC_BUFF_SIZE);
2791 
2792 		rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2793 
2794 		if (rc)
2795 			return rc;
2796 
2797 		crc = crc32_le(crc, buff, count);
2798 		done += count;
2799 	}
2800 
2801 	if (crc != CRC32_RESIDUAL)
2802 		rc = -EINVAL;
2803 
2804 	return rc;
2805 }
2806 
2807 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2808 				struct code_entry *entry,
2809 				u8 *buff)
2810 {
2811 	size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2812 	u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2813 	int rc;
2814 
2815 	/* Zero-length images and AFEX profiles do not have CRC */
2816 	if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2817 		return 0;
2818 
2819 	rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2820 	if (rc)
2821 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2822 		   "image %x has failed crc test (rc %d)\n", type, rc);
2823 
2824 	return rc;
2825 }
2826 
2827 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2828 {
2829 	int rc;
2830 	struct code_entry entry;
2831 
2832 	rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2833 	if (rc)
2834 		return rc;
2835 
2836 	return bnx2x_test_nvram_dir(bp, &entry, buff);
2837 }
2838 
2839 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2840 {
2841 	u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2842 	struct code_entry entry;
2843 	int i;
2844 
2845 	rc = bnx2x_nvram_read32(bp,
2846 				dir_offset +
2847 				sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2848 				(u32 *)&entry, sizeof(entry));
2849 	if (rc)
2850 		return rc;
2851 
2852 	if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2853 		return 0;
2854 
2855 	rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2856 				&cnt, sizeof(u32));
2857 	if (rc)
2858 		return rc;
2859 
2860 	dir_offset = entry.nvm_start_addr + 8;
2861 
2862 	for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2863 		rc = bnx2x_test_dir_entry(bp, dir_offset +
2864 					      sizeof(struct code_entry) * i,
2865 					  buff);
2866 		if (rc)
2867 			return rc;
2868 	}
2869 
2870 	return 0;
2871 }
2872 
2873 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2874 {
2875 	u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2876 	int i;
2877 
2878 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2879 
2880 	for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2881 		rc = bnx2x_test_dir_entry(bp, dir_offset +
2882 					      sizeof(struct code_entry) * i,
2883 					  buff);
2884 		if (rc)
2885 			return rc;
2886 	}
2887 
2888 	return bnx2x_test_nvram_ext_dirs(bp, buff);
2889 }
2890 
2891 struct crc_pair {
2892 	int offset;
2893 	int size;
2894 };
2895 
2896 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2897 				const struct crc_pair *nvram_tbl, u8 *buf)
2898 {
2899 	int i;
2900 
2901 	for (i = 0; nvram_tbl[i].size; i++) {
2902 		int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2903 					 nvram_tbl[i].size, buf);
2904 		if (rc) {
2905 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2906 			   "nvram_tbl[%d] has failed crc test (rc %d)\n",
2907 			   i, rc);
2908 			return rc;
2909 		}
2910 	}
2911 
2912 	return 0;
2913 }
2914 
2915 static int bnx2x_test_nvram(struct bnx2x *bp)
2916 {
2917 	static const struct crc_pair nvram_tbl[] = {
2918 		{     0,  0x14 }, /* bootstrap */
2919 		{  0x14,  0xec }, /* dir */
2920 		{ 0x100, 0x350 }, /* manuf_info */
2921 		{ 0x450,  0xf0 }, /* feature_info */
2922 		{ 0x640,  0x64 }, /* upgrade_key_info */
2923 		{ 0x708,  0x70 }, /* manuf_key_info */
2924 		{     0,     0 }
2925 	};
2926 	static const struct crc_pair nvram_tbl2[] = {
2927 		{ 0x7e8, 0x350 }, /* manuf_info2 */
2928 		{ 0xb38,  0xf0 }, /* feature_info */
2929 		{     0,     0 }
2930 	};
2931 
2932 	u8 *buf;
2933 	int rc;
2934 	u32 magic;
2935 
2936 	if (BP_NOMCP(bp))
2937 		return 0;
2938 
2939 	buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2940 	if (!buf) {
2941 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2942 		rc = -ENOMEM;
2943 		goto test_nvram_exit;
2944 	}
2945 
2946 	rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2947 	if (rc) {
2948 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2949 		   "magic value read (rc %d)\n", rc);
2950 		goto test_nvram_exit;
2951 	}
2952 
2953 	if (magic != 0x669955aa) {
2954 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2955 		   "wrong magic value (0x%08x)\n", magic);
2956 		rc = -ENODEV;
2957 		goto test_nvram_exit;
2958 	}
2959 
2960 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2961 	rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2962 	if (rc)
2963 		goto test_nvram_exit;
2964 
2965 	if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2966 		u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2967 			   SHARED_HW_CFG_HIDE_PORT1;
2968 
2969 		if (!hide) {
2970 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2971 			   "Port 1 CRC test-set\n");
2972 			rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2973 			if (rc)
2974 				goto test_nvram_exit;
2975 		}
2976 	}
2977 
2978 	rc = bnx2x_test_nvram_dirs(bp, buf);
2979 
2980 test_nvram_exit:
2981 	kfree(buf);
2982 	return rc;
2983 }
2984 
2985 /* Send an EMPTY ramrod on the first queue */
2986 static int bnx2x_test_intr(struct bnx2x *bp)
2987 {
2988 	struct bnx2x_queue_state_params params = {NULL};
2989 
2990 	if (!netif_running(bp->dev)) {
2991 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2992 		   "cannot access eeprom when the interface is down\n");
2993 		return -ENODEV;
2994 	}
2995 
2996 	params.q_obj = &bp->sp_objs->q_obj;
2997 	params.cmd = BNX2X_Q_CMD_EMPTY;
2998 
2999 	__set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
3000 
3001 	return bnx2x_queue_state_change(bp, &params);
3002 }
3003 
3004 static void bnx2x_self_test(struct net_device *dev,
3005 			    struct ethtool_test *etest, u64 *buf)
3006 {
3007 	struct bnx2x *bp = netdev_priv(dev);
3008 	u8 is_serdes, link_up;
3009 	int rc, cnt = 0;
3010 
3011 	if (pci_num_vf(bp->pdev)) {
3012 		DP(BNX2X_MSG_IOV,
3013 		   "VFs are enabled, can not perform self test\n");
3014 		return;
3015 	}
3016 
3017 	if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
3018 		netdev_err(bp->dev,
3019 			   "Handling parity error recovery. Try again later\n");
3020 		etest->flags |= ETH_TEST_FL_FAILED;
3021 		return;
3022 	}
3023 
3024 	DP(BNX2X_MSG_ETHTOOL,
3025 	   "Self-test command parameters: offline = %d, external_lb = %d\n",
3026 	   (etest->flags & ETH_TEST_FL_OFFLINE),
3027 	   (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
3028 
3029 	memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
3030 
3031 	if (bnx2x_test_nvram(bp) != 0) {
3032 		if (!IS_MF(bp))
3033 			buf[4] = 1;
3034 		else
3035 			buf[0] = 1;
3036 		etest->flags |= ETH_TEST_FL_FAILED;
3037 	}
3038 
3039 	if (!netif_running(dev)) {
3040 		DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
3041 		return;
3042 	}
3043 
3044 	is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
3045 	link_up = bp->link_vars.link_up;
3046 	/* offline tests are not supported in MF mode */
3047 	if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3048 		int port = BP_PORT(bp);
3049 		u32 val;
3050 
3051 		/* save current value of input enable for TX port IF */
3052 		val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3053 		/* disable input for TX port IF */
3054 		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3055 
3056 		bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3057 		rc = bnx2x_nic_load(bp, LOAD_DIAG);
3058 		if (rc) {
3059 			etest->flags |= ETH_TEST_FL_FAILED;
3060 			DP(BNX2X_MSG_ETHTOOL,
3061 			   "Can't perform self-test, nic_load (for offline) failed\n");
3062 			return;
3063 		}
3064 
3065 		/* wait until link state is restored */
3066 		bnx2x_wait_for_link(bp, 1, is_serdes);
3067 
3068 		if (bnx2x_test_registers(bp) != 0) {
3069 			buf[0] = 1;
3070 			etest->flags |= ETH_TEST_FL_FAILED;
3071 		}
3072 		if (bnx2x_test_memory(bp) != 0) {
3073 			buf[1] = 1;
3074 			etest->flags |= ETH_TEST_FL_FAILED;
3075 		}
3076 
3077 		buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3078 		if (buf[2] != 0)
3079 			etest->flags |= ETH_TEST_FL_FAILED;
3080 
3081 		if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3082 			buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3083 			if (buf[3] != 0)
3084 				etest->flags |= ETH_TEST_FL_FAILED;
3085 			etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3086 		}
3087 
3088 		bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3089 
3090 		/* restore input for TX port IF */
3091 		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3092 		rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3093 		if (rc) {
3094 			etest->flags |= ETH_TEST_FL_FAILED;
3095 			DP(BNX2X_MSG_ETHTOOL,
3096 			   "Can't perform self-test, nic_load (for online) failed\n");
3097 			return;
3098 		}
3099 		/* wait until link state is restored */
3100 		bnx2x_wait_for_link(bp, link_up, is_serdes);
3101 	}
3102 
3103 	if (bnx2x_test_intr(bp) != 0) {
3104 		if (!IS_MF(bp))
3105 			buf[5] = 1;
3106 		else
3107 			buf[1] = 1;
3108 		etest->flags |= ETH_TEST_FL_FAILED;
3109 	}
3110 
3111 	if (link_up) {
3112 		cnt = 100;
3113 		while (bnx2x_link_test(bp, is_serdes) && --cnt)
3114 			msleep(20);
3115 	}
3116 
3117 	if (!cnt) {
3118 		if (!IS_MF(bp))
3119 			buf[6] = 1;
3120 		else
3121 			buf[2] = 1;
3122 		etest->flags |= ETH_TEST_FL_FAILED;
3123 	}
3124 }
3125 
3126 #define IS_PORT_STAT(i)		(bnx2x_stats_arr[i].is_port_stat)
3127 #define HIDE_PORT_STAT(bp)	IS_VF(bp)
3128 
3129 /* ethtool statistics are displayed for all regular ethernet queues and the
3130  * fcoe L2 queue if not disabled
3131  */
3132 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3133 {
3134 	return BNX2X_NUM_ETH_QUEUES(bp);
3135 }
3136 
3137 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3138 {
3139 	struct bnx2x *bp = netdev_priv(dev);
3140 	int i, num_strings = 0;
3141 
3142 	switch (stringset) {
3143 	case ETH_SS_STATS:
3144 		if (is_multi(bp)) {
3145 			num_strings = bnx2x_num_stat_queues(bp) *
3146 				      BNX2X_NUM_Q_STATS;
3147 		} else
3148 			num_strings = 0;
3149 		if (HIDE_PORT_STAT(bp)) {
3150 			for (i = 0; i < BNX2X_NUM_STATS; i++)
3151 				if (!IS_PORT_STAT(i))
3152 					num_strings++;
3153 		} else
3154 			num_strings += BNX2X_NUM_STATS;
3155 
3156 		return num_strings;
3157 
3158 	case ETH_SS_TEST:
3159 		return BNX2X_NUM_TESTS(bp);
3160 
3161 	case ETH_SS_PRIV_FLAGS:
3162 		return BNX2X_PRI_FLAG_LEN;
3163 
3164 	default:
3165 		return -EINVAL;
3166 	}
3167 }
3168 
3169 static u32 bnx2x_get_private_flags(struct net_device *dev)
3170 {
3171 	struct bnx2x *bp = netdev_priv(dev);
3172 	u32 flags = 0;
3173 
3174 	flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3175 	flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3176 	flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3177 
3178 	return flags;
3179 }
3180 
3181 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3182 {
3183 	struct bnx2x *bp = netdev_priv(dev);
3184 	int i, j, k, start;
3185 	char queue_name[MAX_QUEUE_NAME_LEN+1];
3186 
3187 	switch (stringset) {
3188 	case ETH_SS_STATS:
3189 		k = 0;
3190 		if (is_multi(bp)) {
3191 			for_each_eth_queue(bp, i) {
3192 				memset(queue_name, 0, sizeof(queue_name));
3193 				snprintf(queue_name, sizeof(queue_name),
3194 					 "%d", i);
3195 				for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3196 					snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3197 						ETH_GSTRING_LEN,
3198 						bnx2x_q_stats_arr[j].string,
3199 						queue_name);
3200 				k += BNX2X_NUM_Q_STATS;
3201 			}
3202 		}
3203 
3204 		for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3205 			if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3206 				continue;
3207 			strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3208 				   bnx2x_stats_arr[i].string);
3209 			j++;
3210 		}
3211 
3212 		break;
3213 
3214 	case ETH_SS_TEST:
3215 		/* First 4 tests cannot be done in MF mode */
3216 		if (!IS_MF(bp))
3217 			start = 0;
3218 		else
3219 			start = 4;
3220 		memcpy(buf, bnx2x_tests_str_arr + start,
3221 		       ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3222 		break;
3223 
3224 	case ETH_SS_PRIV_FLAGS:
3225 		memcpy(buf, bnx2x_private_arr,
3226 		       ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3227 		break;
3228 	}
3229 }
3230 
3231 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3232 				    struct ethtool_stats *stats, u64 *buf)
3233 {
3234 	struct bnx2x *bp = netdev_priv(dev);
3235 	u32 *hw_stats, *offset;
3236 	int i, j, k = 0;
3237 
3238 	if (is_multi(bp)) {
3239 		for_each_eth_queue(bp, i) {
3240 			hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3241 			for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3242 				if (bnx2x_q_stats_arr[j].size == 0) {
3243 					/* skip this counter */
3244 					buf[k + j] = 0;
3245 					continue;
3246 				}
3247 				offset = (hw_stats +
3248 					  bnx2x_q_stats_arr[j].offset);
3249 				if (bnx2x_q_stats_arr[j].size == 4) {
3250 					/* 4-byte counter */
3251 					buf[k + j] = (u64) *offset;
3252 					continue;
3253 				}
3254 				/* 8-byte counter */
3255 				buf[k + j] = HILO_U64(*offset, *(offset + 1));
3256 			}
3257 			k += BNX2X_NUM_Q_STATS;
3258 		}
3259 	}
3260 
3261 	hw_stats = (u32 *)&bp->eth_stats;
3262 	for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3263 		if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3264 			continue;
3265 		if (bnx2x_stats_arr[i].size == 0) {
3266 			/* skip this counter */
3267 			buf[k + j] = 0;
3268 			j++;
3269 			continue;
3270 		}
3271 		offset = (hw_stats + bnx2x_stats_arr[i].offset);
3272 		if (bnx2x_stats_arr[i].size == 4) {
3273 			/* 4-byte counter */
3274 			buf[k + j] = (u64) *offset;
3275 			j++;
3276 			continue;
3277 		}
3278 		/* 8-byte counter */
3279 		buf[k + j] = HILO_U64(*offset, *(offset + 1));
3280 		j++;
3281 	}
3282 }
3283 
3284 static int bnx2x_set_phys_id(struct net_device *dev,
3285 			     enum ethtool_phys_id_state state)
3286 {
3287 	struct bnx2x *bp = netdev_priv(dev);
3288 
3289 	if (!bnx2x_is_nvm_accessible(bp)) {
3290 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3291 		   "cannot access eeprom when the interface is down\n");
3292 		return -EAGAIN;
3293 	}
3294 
3295 	switch (state) {
3296 	case ETHTOOL_ID_ACTIVE:
3297 		return 1;	/* cycle on/off once per second */
3298 
3299 	case ETHTOOL_ID_ON:
3300 		bnx2x_acquire_phy_lock(bp);
3301 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3302 			      LED_MODE_ON, SPEED_1000);
3303 		bnx2x_release_phy_lock(bp);
3304 		break;
3305 
3306 	case ETHTOOL_ID_OFF:
3307 		bnx2x_acquire_phy_lock(bp);
3308 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3309 			      LED_MODE_FRONT_PANEL_OFF, 0);
3310 		bnx2x_release_phy_lock(bp);
3311 		break;
3312 
3313 	case ETHTOOL_ID_INACTIVE:
3314 		bnx2x_acquire_phy_lock(bp);
3315 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3316 			      LED_MODE_OPER,
3317 			      bp->link_vars.line_speed);
3318 		bnx2x_release_phy_lock(bp);
3319 	}
3320 
3321 	return 0;
3322 }
3323 
3324 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3325 {
3326 	switch (info->flow_type) {
3327 	case TCP_V4_FLOW:
3328 	case TCP_V6_FLOW:
3329 		info->data = RXH_IP_SRC | RXH_IP_DST |
3330 			     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3331 		break;
3332 	case UDP_V4_FLOW:
3333 		if (bp->rss_conf_obj.udp_rss_v4)
3334 			info->data = RXH_IP_SRC | RXH_IP_DST |
3335 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3336 		else
3337 			info->data = RXH_IP_SRC | RXH_IP_DST;
3338 		break;
3339 	case UDP_V6_FLOW:
3340 		if (bp->rss_conf_obj.udp_rss_v6)
3341 			info->data = RXH_IP_SRC | RXH_IP_DST |
3342 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3343 		else
3344 			info->data = RXH_IP_SRC | RXH_IP_DST;
3345 		break;
3346 	case IPV4_FLOW:
3347 	case IPV6_FLOW:
3348 		info->data = RXH_IP_SRC | RXH_IP_DST;
3349 		break;
3350 	default:
3351 		info->data = 0;
3352 		break;
3353 	}
3354 
3355 	return 0;
3356 }
3357 
3358 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3359 			   u32 *rules __always_unused)
3360 {
3361 	struct bnx2x *bp = netdev_priv(dev);
3362 
3363 	switch (info->cmd) {
3364 	case ETHTOOL_GRXRINGS:
3365 		info->data = BNX2X_NUM_ETH_QUEUES(bp);
3366 		return 0;
3367 	case ETHTOOL_GRXFH:
3368 		return bnx2x_get_rss_flags(bp, info);
3369 	default:
3370 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3371 		return -EOPNOTSUPP;
3372 	}
3373 }
3374 
3375 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3376 {
3377 	int udp_rss_requested;
3378 
3379 	DP(BNX2X_MSG_ETHTOOL,
3380 	   "Set rss flags command parameters: flow type = %d, data = %llu\n",
3381 	   info->flow_type, info->data);
3382 
3383 	switch (info->flow_type) {
3384 	case TCP_V4_FLOW:
3385 	case TCP_V6_FLOW:
3386 		/* For TCP only 4-tupple hash is supported */
3387 		if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3388 				  RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3389 			DP(BNX2X_MSG_ETHTOOL,
3390 			   "Command parameters not supported\n");
3391 			return -EINVAL;
3392 		}
3393 		return 0;
3394 
3395 	case UDP_V4_FLOW:
3396 	case UDP_V6_FLOW:
3397 		/* For UDP either 2-tupple hash or 4-tupple hash is supported */
3398 		if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3399 				   RXH_L4_B_0_1 | RXH_L4_B_2_3))
3400 			udp_rss_requested = 1;
3401 		else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3402 			udp_rss_requested = 0;
3403 		else
3404 			return -EINVAL;
3405 
3406 		if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3407 			DP(BNX2X_MSG_ETHTOOL,
3408 			   "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3409 			return -EINVAL;
3410 		}
3411 
3412 		if ((info->flow_type == UDP_V4_FLOW) &&
3413 		    (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3414 			bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3415 			DP(BNX2X_MSG_ETHTOOL,
3416 			   "rss re-configured, UDP 4-tupple %s\n",
3417 			   udp_rss_requested ? "enabled" : "disabled");
3418 			if (bp->state == BNX2X_STATE_OPEN)
3419 				return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3420 						 true);
3421 		} else if ((info->flow_type == UDP_V6_FLOW) &&
3422 			   (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3423 			bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3424 			DP(BNX2X_MSG_ETHTOOL,
3425 			   "rss re-configured, UDP 4-tupple %s\n",
3426 			   udp_rss_requested ? "enabled" : "disabled");
3427 			if (bp->state == BNX2X_STATE_OPEN)
3428 				return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3429 						 true);
3430 		}
3431 		return 0;
3432 
3433 	case IPV4_FLOW:
3434 	case IPV6_FLOW:
3435 		/* For IP only 2-tupple hash is supported */
3436 		if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3437 			DP(BNX2X_MSG_ETHTOOL,
3438 			   "Command parameters not supported\n");
3439 			return -EINVAL;
3440 		}
3441 		return 0;
3442 
3443 	case SCTP_V4_FLOW:
3444 	case AH_ESP_V4_FLOW:
3445 	case AH_V4_FLOW:
3446 	case ESP_V4_FLOW:
3447 	case SCTP_V6_FLOW:
3448 	case AH_ESP_V6_FLOW:
3449 	case AH_V6_FLOW:
3450 	case ESP_V6_FLOW:
3451 	case IP_USER_FLOW:
3452 	case ETHER_FLOW:
3453 		/* RSS is not supported for these protocols */
3454 		if (info->data) {
3455 			DP(BNX2X_MSG_ETHTOOL,
3456 			   "Command parameters not supported\n");
3457 			return -EINVAL;
3458 		}
3459 		return 0;
3460 
3461 	default:
3462 		return -EINVAL;
3463 	}
3464 }
3465 
3466 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3467 {
3468 	struct bnx2x *bp = netdev_priv(dev);
3469 
3470 	switch (info->cmd) {
3471 	case ETHTOOL_SRXFH:
3472 		return bnx2x_set_rss_flags(bp, info);
3473 	default:
3474 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3475 		return -EOPNOTSUPP;
3476 	}
3477 }
3478 
3479 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3480 {
3481 	return T_ETH_INDIRECTION_TABLE_SIZE;
3482 }
3483 
3484 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3485 			  u8 *hfunc)
3486 {
3487 	struct bnx2x *bp = netdev_priv(dev);
3488 	u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3489 	size_t i;
3490 
3491 	if (hfunc)
3492 		*hfunc = ETH_RSS_HASH_TOP;
3493 	if (!indir)
3494 		return 0;
3495 
3496 	/* Get the current configuration of the RSS indirection table */
3497 	bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3498 
3499 	/*
3500 	 * We can't use a memcpy() as an internal storage of an
3501 	 * indirection table is a u8 array while indir->ring_index
3502 	 * points to an array of u32.
3503 	 *
3504 	 * Indirection table contains the FW Client IDs, so we need to
3505 	 * align the returned table to the Client ID of the leading RSS
3506 	 * queue.
3507 	 */
3508 	for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3509 		indir[i] = ind_table[i] - bp->fp->cl_id;
3510 
3511 	return 0;
3512 }
3513 
3514 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3515 			  const u8 *key, const u8 hfunc)
3516 {
3517 	struct bnx2x *bp = netdev_priv(dev);
3518 	size_t i;
3519 
3520 	/* We require at least one supported parameter to be changed and no
3521 	 * change in any of the unsupported parameters
3522 	 */
3523 	if (key ||
3524 	    (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3525 		return -EOPNOTSUPP;
3526 
3527 	if (!indir)
3528 		return 0;
3529 
3530 	for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3531 		/*
3532 		 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3533 		 * as an internal storage of an indirection table is a u8 array
3534 		 * while indir->ring_index points to an array of u32.
3535 		 *
3536 		 * Indirection table contains the FW Client IDs, so we need to
3537 		 * align the received table to the Client ID of the leading RSS
3538 		 * queue
3539 		 */
3540 		bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3541 	}
3542 
3543 	if (bp->state == BNX2X_STATE_OPEN)
3544 		return bnx2x_config_rss_eth(bp, false);
3545 
3546 	return 0;
3547 }
3548 
3549 /**
3550  * bnx2x_get_channels - gets the number of RSS queues.
3551  *
3552  * @dev:		net device
3553  * @channels:		returns the number of max / current queues
3554  */
3555 static void bnx2x_get_channels(struct net_device *dev,
3556 			       struct ethtool_channels *channels)
3557 {
3558 	struct bnx2x *bp = netdev_priv(dev);
3559 
3560 	channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3561 	channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3562 }
3563 
3564 /**
3565  * bnx2x_change_num_queues - change the number of RSS queues.
3566  *
3567  * @bp:			bnx2x private structure
3568  *
3569  * Re-configure interrupt mode to get the new number of MSI-X
3570  * vectors and re-add NAPI objects.
3571  */
3572 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3573 {
3574 	bnx2x_disable_msi(bp);
3575 	bp->num_ethernet_queues = num_rss;
3576 	bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3577 	BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3578 	bnx2x_set_int_mode(bp);
3579 }
3580 
3581 /**
3582  * bnx2x_set_channels - sets the number of RSS queues.
3583  *
3584  * @dev:		net device
3585  * @channels:		includes the number of queues requested
3586  */
3587 static int bnx2x_set_channels(struct net_device *dev,
3588 			      struct ethtool_channels *channels)
3589 {
3590 	struct bnx2x *bp = netdev_priv(dev);
3591 
3592 	DP(BNX2X_MSG_ETHTOOL,
3593 	   "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3594 	   channels->rx_count, channels->tx_count, channels->other_count,
3595 	   channels->combined_count);
3596 
3597 	if (pci_num_vf(bp->pdev)) {
3598 		DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3599 		return -EPERM;
3600 	}
3601 
3602 	/* We don't support separate rx / tx channels.
3603 	 * We don't allow setting 'other' channels.
3604 	 */
3605 	if (channels->rx_count || channels->tx_count || channels->other_count
3606 	    || (channels->combined_count == 0) ||
3607 	    (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3608 		DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3609 		return -EINVAL;
3610 	}
3611 
3612 	/* Check if there was a change in the active parameters */
3613 	if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3614 		DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3615 		return 0;
3616 	}
3617 
3618 	/* Set the requested number of queues in bp context.
3619 	 * Note that the actual number of queues created during load may be
3620 	 * less than requested if memory is low.
3621 	 */
3622 	if (unlikely(!netif_running(dev))) {
3623 		bnx2x_change_num_queues(bp, channels->combined_count);
3624 		return 0;
3625 	}
3626 	bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3627 	bnx2x_change_num_queues(bp, channels->combined_count);
3628 	return bnx2x_nic_load(bp, LOAD_NORMAL);
3629 }
3630 
3631 static int bnx2x_get_ts_info(struct net_device *dev,
3632 			     struct ethtool_ts_info *info)
3633 {
3634 	struct bnx2x *bp = netdev_priv(dev);
3635 
3636 	if (bp->flags & PTP_SUPPORTED) {
3637 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3638 					SOF_TIMESTAMPING_RX_SOFTWARE |
3639 					SOF_TIMESTAMPING_SOFTWARE |
3640 					SOF_TIMESTAMPING_TX_HARDWARE |
3641 					SOF_TIMESTAMPING_RX_HARDWARE |
3642 					SOF_TIMESTAMPING_RAW_HARDWARE;
3643 
3644 		if (bp->ptp_clock)
3645 			info->phc_index = ptp_clock_index(bp->ptp_clock);
3646 		else
3647 			info->phc_index = -1;
3648 
3649 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3650 				   (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3651 				   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3652 				   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3653 
3654 		info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3655 
3656 		return 0;
3657 	}
3658 
3659 	return ethtool_op_get_ts_info(dev, info);
3660 }
3661 
3662 static const struct ethtool_ops bnx2x_ethtool_ops = {
3663 	.get_drvinfo		= bnx2x_get_drvinfo,
3664 	.get_regs_len		= bnx2x_get_regs_len,
3665 	.get_regs		= bnx2x_get_regs,
3666 	.get_dump_flag		= bnx2x_get_dump_flag,
3667 	.get_dump_data		= bnx2x_get_dump_data,
3668 	.set_dump		= bnx2x_set_dump,
3669 	.get_wol		= bnx2x_get_wol,
3670 	.set_wol		= bnx2x_set_wol,
3671 	.get_msglevel		= bnx2x_get_msglevel,
3672 	.set_msglevel		= bnx2x_set_msglevel,
3673 	.nway_reset		= bnx2x_nway_reset,
3674 	.get_link		= bnx2x_get_link,
3675 	.get_eeprom_len		= bnx2x_get_eeprom_len,
3676 	.get_eeprom		= bnx2x_get_eeprom,
3677 	.set_eeprom		= bnx2x_set_eeprom,
3678 	.get_coalesce		= bnx2x_get_coalesce,
3679 	.set_coalesce		= bnx2x_set_coalesce,
3680 	.get_ringparam		= bnx2x_get_ringparam,
3681 	.set_ringparam		= bnx2x_set_ringparam,
3682 	.get_pauseparam		= bnx2x_get_pauseparam,
3683 	.set_pauseparam		= bnx2x_set_pauseparam,
3684 	.self_test		= bnx2x_self_test,
3685 	.get_sset_count		= bnx2x_get_sset_count,
3686 	.get_priv_flags		= bnx2x_get_private_flags,
3687 	.get_strings		= bnx2x_get_strings,
3688 	.set_phys_id		= bnx2x_set_phys_id,
3689 	.get_ethtool_stats	= bnx2x_get_ethtool_stats,
3690 	.get_rxnfc		= bnx2x_get_rxnfc,
3691 	.set_rxnfc		= bnx2x_set_rxnfc,
3692 	.get_rxfh_indir_size	= bnx2x_get_rxfh_indir_size,
3693 	.get_rxfh		= bnx2x_get_rxfh,
3694 	.set_rxfh		= bnx2x_set_rxfh,
3695 	.get_channels		= bnx2x_get_channels,
3696 	.set_channels		= bnx2x_set_channels,
3697 	.get_module_info	= bnx2x_get_module_info,
3698 	.get_module_eeprom	= bnx2x_get_module_eeprom,
3699 	.get_eee		= bnx2x_get_eee,
3700 	.set_eee		= bnx2x_set_eee,
3701 	.get_ts_info		= bnx2x_get_ts_info,
3702 	.get_link_ksettings	= bnx2x_get_link_ksettings,
3703 	.set_link_ksettings	= bnx2x_set_link_ksettings,
3704 };
3705 
3706 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3707 	.get_drvinfo		= bnx2x_get_drvinfo,
3708 	.get_msglevel		= bnx2x_get_msglevel,
3709 	.set_msglevel		= bnx2x_set_msglevel,
3710 	.get_link		= bnx2x_get_link,
3711 	.get_coalesce		= bnx2x_get_coalesce,
3712 	.get_ringparam		= bnx2x_get_ringparam,
3713 	.set_ringparam		= bnx2x_set_ringparam,
3714 	.get_sset_count		= bnx2x_get_sset_count,
3715 	.get_strings		= bnx2x_get_strings,
3716 	.get_ethtool_stats	= bnx2x_get_ethtool_stats,
3717 	.get_rxnfc		= bnx2x_get_rxnfc,
3718 	.set_rxnfc		= bnx2x_set_rxnfc,
3719 	.get_rxfh_indir_size	= bnx2x_get_rxfh_indir_size,
3720 	.get_rxfh		= bnx2x_get_rxfh,
3721 	.set_rxfh		= bnx2x_set_rxfh,
3722 	.get_channels		= bnx2x_get_channels,
3723 	.set_channels		= bnx2x_set_channels,
3724 	.get_link_ksettings	= bnx2x_get_vf_link_ksettings,
3725 };
3726 
3727 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3728 {
3729 	netdev->ethtool_ops = (IS_PF(bp)) ?
3730 		&bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3731 }
3732