1 /* bnx2x_ethtool.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/ethtool.h> 23 #include <linux/netdevice.h> 24 #include <linux/types.h> 25 #include <linux/sched.h> 26 #include <linux/crc32.h> 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 #include "bnx2x_dump.h" 30 #include "bnx2x_init.h" 31 32 /* Note: in the format strings below %s is replaced by the queue-name which is 33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35 */ 36 #define MAX_QUEUE_NAME_LEN 4 37 static const struct { 38 long offset; 39 int size; 40 char string[ETH_GSTRING_LEN]; 41 } bnx2x_q_stats_arr[] = { 42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44 8, "[%s]: rx_ucast_packets" }, 45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46 8, "[%s]: rx_mcast_packets" }, 47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48 8, "[%s]: rx_bcast_packets" }, 49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50 { Q_STATS_OFFSET32(rx_err_discard_pkt), 51 4, "[%s]: rx_phy_ip_err_discards"}, 52 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53 4, "[%s]: rx_skb_alloc_discard" }, 54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 55 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" }, 56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58 8, "[%s]: tx_ucast_packets" }, 59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60 8, "[%s]: tx_mcast_packets" }, 61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62 8, "[%s]: tx_bcast_packets" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64 8, "[%s]: tpa_aggregations" }, 65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66 8, "[%s]: tpa_aggregated_frames"}, 67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69 4, "[%s]: driver_filtered_tx_pkt" } 70 }; 71 72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73 74 static const struct { 75 long offset; 76 int size; 77 bool is_port_stat; 78 char string[ETH_GSTRING_LEN]; 79 } bnx2x_stats_arr[] = { 80 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 81 8, false, "rx_bytes" }, 82 { STATS_OFFSET32(error_bytes_received_hi), 83 8, false, "rx_error_bytes" }, 84 { STATS_OFFSET32(total_unicast_packets_received_hi), 85 8, false, "rx_ucast_packets" }, 86 { STATS_OFFSET32(total_multicast_packets_received_hi), 87 8, false, "rx_mcast_packets" }, 88 { STATS_OFFSET32(total_broadcast_packets_received_hi), 89 8, false, "rx_bcast_packets" }, 90 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 91 8, true, "rx_crc_errors" }, 92 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 93 8, true, "rx_align_errors" }, 94 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 95 8, true, "rx_undersize_packets" }, 96 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 97 8, true, "rx_oversize_packets" }, 98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 99 8, true, "rx_fragments" }, 100 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 101 8, true, "rx_jabbers" }, 102 { STATS_OFFSET32(no_buff_discard_hi), 103 8, false, "rx_discards" }, 104 { STATS_OFFSET32(mac_filter_discard), 105 4, true, "rx_filtered_packets" }, 106 { STATS_OFFSET32(mf_tag_discard), 107 4, true, "rx_mf_tag_discard" }, 108 { STATS_OFFSET32(pfc_frames_received_hi), 109 8, true, "pfc_frames_received" }, 110 { STATS_OFFSET32(pfc_frames_sent_hi), 111 8, true, "pfc_frames_sent" }, 112 { STATS_OFFSET32(brb_drop_hi), 113 8, true, "rx_brb_discard" }, 114 { STATS_OFFSET32(brb_truncate_hi), 115 8, true, "rx_brb_truncate" }, 116 { STATS_OFFSET32(pause_frames_received_hi), 117 8, true, "rx_pause_frames" }, 118 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 119 8, true, "rx_mac_ctrl_frames" }, 120 { STATS_OFFSET32(nig_timer_max), 121 4, true, "rx_constant_pause_events" }, 122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 123 4, false, "rx_phy_ip_err_discards"}, 124 { STATS_OFFSET32(rx_skb_alloc_failed), 125 4, false, "rx_skb_alloc_discard" }, 126 { STATS_OFFSET32(hw_csum_err), 127 4, false, "rx_csum_offload_errors" }, 128 { STATS_OFFSET32(driver_xoff), 129 4, false, "tx_exhaustion_events" }, 130 { STATS_OFFSET32(total_bytes_transmitted_hi), 131 8, false, "tx_bytes" }, 132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133 8, true, "tx_error_bytes" }, 134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135 8, false, "tx_ucast_packets" }, 136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137 8, false, "tx_mcast_packets" }, 138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139 8, false, "tx_bcast_packets" }, 140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141 8, true, "tx_mac_errors" }, 142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143 8, true, "tx_carrier_errors" }, 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145 8, true, "tx_single_collisions" }, 146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147 8, true, "tx_multi_collisions" }, 148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149 8, true, "tx_deferred" }, 150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151 8, true, "tx_excess_collisions" }, 152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153 8, true, "tx_late_collisions" }, 154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155 8, true, "tx_total_collisions" }, 156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157 8, true, "tx_64_byte_packets" }, 158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159 8, true, "tx_65_to_127_byte_packets" }, 160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161 8, true, "tx_128_to_255_byte_packets" }, 162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163 8, true, "tx_256_to_511_byte_packets" }, 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165 8, true, "tx_512_to_1023_byte_packets" }, 166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167 8, true, "tx_1024_to_1522_byte_packets" }, 168 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169 8, true, "tx_1523_to_9022_byte_packets" }, 170 { STATS_OFFSET32(pause_frames_sent_hi), 171 8, true, "tx_pause_frames" }, 172 { STATS_OFFSET32(total_tpa_aggregations_hi), 173 8, false, "tpa_aggregations" }, 174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175 8, false, "tpa_aggregated_frames"}, 176 { STATS_OFFSET32(total_tpa_bytes_hi), 177 8, false, "tpa_bytes"}, 178 { STATS_OFFSET32(recoverable_error), 179 4, false, "recoverable_errors" }, 180 { STATS_OFFSET32(unrecoverable_error), 181 4, false, "unrecoverable_errors" }, 182 { STATS_OFFSET32(driver_filtered_tx_pkt), 183 4, false, "driver_filtered_tx_pkt" }, 184 { STATS_OFFSET32(eee_tx_lpi), 185 4, true, "Tx LPI entry count"} 186 }; 187 188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 189 190 static int bnx2x_get_port_type(struct bnx2x *bp) 191 { 192 int port_type; 193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194 switch (bp->link_params.phy[phy_idx].media_type) { 195 case ETH_PHY_SFPP_10G_FIBER: 196 case ETH_PHY_SFP_1G_FIBER: 197 case ETH_PHY_XFP_FIBER: 198 case ETH_PHY_KR: 199 case ETH_PHY_CX4: 200 port_type = PORT_FIBRE; 201 break; 202 case ETH_PHY_DA_TWINAX: 203 port_type = PORT_DA; 204 break; 205 case ETH_PHY_BASE_T: 206 port_type = PORT_TP; 207 break; 208 case ETH_PHY_NOT_PRESENT: 209 port_type = PORT_NONE; 210 break; 211 case ETH_PHY_UNSPECIFIED: 212 default: 213 port_type = PORT_OTHER; 214 break; 215 } 216 return port_type; 217 } 218 219 static int bnx2x_get_vf_settings(struct net_device *dev, 220 struct ethtool_cmd *cmd) 221 { 222 struct bnx2x *bp = netdev_priv(dev); 223 224 if (bp->state == BNX2X_STATE_OPEN) { 225 if (test_bit(BNX2X_LINK_REPORT_FD, 226 &bp->vf_link_vars.link_report_flags)) 227 cmd->duplex = DUPLEX_FULL; 228 else 229 cmd->duplex = DUPLEX_HALF; 230 231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed); 232 } else { 233 cmd->duplex = DUPLEX_UNKNOWN; 234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 235 } 236 237 cmd->port = PORT_OTHER; 238 cmd->phy_address = 0; 239 cmd->transceiver = XCVR_INTERNAL; 240 cmd->autoneg = AUTONEG_DISABLE; 241 cmd->maxtxpkt = 0; 242 cmd->maxrxpkt = 0; 243 244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 245 " supported 0x%x advertising 0x%x speed %u\n" 246 " duplex %d port %d phy_address %d transceiver %d\n" 247 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 248 cmd->cmd, cmd->supported, cmd->advertising, 249 ethtool_cmd_speed(cmd), 250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 252 253 return 0; 254 } 255 256 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 257 { 258 struct bnx2x *bp = netdev_priv(dev); 259 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 260 u32 media_type; 261 262 /* Dual Media boards present all available port types */ 263 cmd->supported = bp->port.supported[cfg_idx] | 264 (bp->port.supported[cfg_idx ^ 1] & 265 (SUPPORTED_TP | SUPPORTED_FIBRE)); 266 cmd->advertising = bp->port.advertising[cfg_idx]; 267 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 268 if (media_type == ETH_PHY_SFP_1G_FIBER) { 269 cmd->supported &= ~(SUPPORTED_10000baseT_Full); 270 cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 271 } 272 273 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 274 !(bp->flags & MF_FUNC_DIS)) { 275 cmd->duplex = bp->link_vars.duplex; 276 277 if (IS_MF(bp) && !BP_NOMCP(bp)) 278 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 279 else 280 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 281 } else { 282 cmd->duplex = DUPLEX_UNKNOWN; 283 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 284 } 285 286 cmd->port = bnx2x_get_port_type(bp); 287 288 cmd->phy_address = bp->mdio.prtad; 289 cmd->transceiver = XCVR_INTERNAL; 290 291 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 292 cmd->autoneg = AUTONEG_ENABLE; 293 else 294 cmd->autoneg = AUTONEG_DISABLE; 295 296 /* Publish LP advertised speeds and FC */ 297 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 298 u32 status = bp->link_vars.link_status; 299 300 cmd->lp_advertising |= ADVERTISED_Autoneg; 301 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 302 cmd->lp_advertising |= ADVERTISED_Pause; 303 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 304 cmd->lp_advertising |= ADVERTISED_Asym_Pause; 305 306 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 307 cmd->lp_advertising |= ADVERTISED_10baseT_Half; 308 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 309 cmd->lp_advertising |= ADVERTISED_10baseT_Full; 310 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 311 cmd->lp_advertising |= ADVERTISED_100baseT_Half; 312 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 313 cmd->lp_advertising |= ADVERTISED_100baseT_Full; 314 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 315 cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 316 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 317 if (media_type == ETH_PHY_KR) { 318 cmd->lp_advertising |= 319 ADVERTISED_1000baseKX_Full; 320 } else { 321 cmd->lp_advertising |= 322 ADVERTISED_1000baseT_Full; 323 } 324 } 325 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 326 cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 327 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 328 if (media_type == ETH_PHY_KR) { 329 cmd->lp_advertising |= 330 ADVERTISED_10000baseKR_Full; 331 } else { 332 cmd->lp_advertising |= 333 ADVERTISED_10000baseT_Full; 334 } 335 } 336 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 337 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 338 } 339 340 cmd->maxtxpkt = 0; 341 cmd->maxrxpkt = 0; 342 343 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 344 " supported 0x%x advertising 0x%x speed %u\n" 345 " duplex %d port %d phy_address %d transceiver %d\n" 346 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 347 cmd->cmd, cmd->supported, cmd->advertising, 348 ethtool_cmd_speed(cmd), 349 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 350 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 351 352 return 0; 353 } 354 355 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 356 { 357 struct bnx2x *bp = netdev_priv(dev); 358 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 359 u32 speed, phy_idx; 360 361 if (IS_MF_SD(bp)) 362 return 0; 363 364 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 365 " supported 0x%x advertising 0x%x speed %u\n" 366 " duplex %d port %d phy_address %d transceiver %d\n" 367 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 368 cmd->cmd, cmd->supported, cmd->advertising, 369 ethtool_cmd_speed(cmd), 370 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 371 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 372 373 speed = ethtool_cmd_speed(cmd); 374 375 /* If received a request for an unknown duplex, assume full*/ 376 if (cmd->duplex == DUPLEX_UNKNOWN) 377 cmd->duplex = DUPLEX_FULL; 378 379 if (IS_MF_SI(bp)) { 380 u32 part; 381 u32 line_speed = bp->link_vars.line_speed; 382 383 /* use 10G if no link detected */ 384 if (!line_speed) 385 line_speed = 10000; 386 387 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 388 DP(BNX2X_MSG_ETHTOOL, 389 "To set speed BC %X or higher is required, please upgrade BC\n", 390 REQ_BC_VER_4_SET_MF_BW); 391 return -EINVAL; 392 } 393 394 part = (speed * 100) / line_speed; 395 396 if (line_speed < speed || !part) { 397 DP(BNX2X_MSG_ETHTOOL, 398 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 399 return -EINVAL; 400 } 401 402 if (bp->state != BNX2X_STATE_OPEN) 403 /* store value for following "load" */ 404 bp->pending_max = part; 405 else 406 bnx2x_update_max_mf_config(bp, part); 407 408 return 0; 409 } 410 411 cfg_idx = bnx2x_get_link_cfg_idx(bp); 412 old_multi_phy_config = bp->link_params.multi_phy_config; 413 if (cmd->port != bnx2x_get_port_type(bp)) { 414 switch (cmd->port) { 415 case PORT_TP: 416 if (!(bp->port.supported[0] & SUPPORTED_TP || 417 bp->port.supported[1] & SUPPORTED_TP)) { 418 DP(BNX2X_MSG_ETHTOOL, 419 "Unsupported port type\n"); 420 return -EINVAL; 421 } 422 bp->link_params.multi_phy_config &= 423 ~PORT_HW_CFG_PHY_SELECTION_MASK; 424 if (bp->link_params.multi_phy_config & 425 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 426 bp->link_params.multi_phy_config |= 427 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 428 else 429 bp->link_params.multi_phy_config |= 430 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 431 break; 432 case PORT_FIBRE: 433 case PORT_DA: 434 case PORT_NONE: 435 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 436 bp->port.supported[1] & SUPPORTED_FIBRE)) { 437 DP(BNX2X_MSG_ETHTOOL, 438 "Unsupported port type\n"); 439 return -EINVAL; 440 } 441 bp->link_params.multi_phy_config &= 442 ~PORT_HW_CFG_PHY_SELECTION_MASK; 443 if (bp->link_params.multi_phy_config & 444 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 445 bp->link_params.multi_phy_config |= 446 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 447 else 448 bp->link_params.multi_phy_config |= 449 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 450 break; 451 default: 452 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 453 return -EINVAL; 454 } 455 } 456 /* Save new config in case command complete successfully */ 457 new_multi_phy_config = bp->link_params.multi_phy_config; 458 /* Get the new cfg_idx */ 459 cfg_idx = bnx2x_get_link_cfg_idx(bp); 460 /* Restore old config in case command failed */ 461 bp->link_params.multi_phy_config = old_multi_phy_config; 462 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 463 464 if (cmd->autoneg == AUTONEG_ENABLE) { 465 u32 an_supported_speed = bp->port.supported[cfg_idx]; 466 if (bp->link_params.phy[EXT_PHY1].type == 467 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 468 an_supported_speed |= (SUPPORTED_100baseT_Half | 469 SUPPORTED_100baseT_Full); 470 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 471 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 472 return -EINVAL; 473 } 474 475 /* advertise the requested speed and duplex if supported */ 476 if (cmd->advertising & ~an_supported_speed) { 477 DP(BNX2X_MSG_ETHTOOL, 478 "Advertisement parameters are not supported\n"); 479 return -EINVAL; 480 } 481 482 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 483 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 484 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 485 cmd->advertising); 486 if (cmd->advertising) { 487 488 bp->link_params.speed_cap_mask[cfg_idx] = 0; 489 if (cmd->advertising & ADVERTISED_10baseT_Half) { 490 bp->link_params.speed_cap_mask[cfg_idx] |= 491 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 492 } 493 if (cmd->advertising & ADVERTISED_10baseT_Full) 494 bp->link_params.speed_cap_mask[cfg_idx] |= 495 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 496 497 if (cmd->advertising & ADVERTISED_100baseT_Full) 498 bp->link_params.speed_cap_mask[cfg_idx] |= 499 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 500 501 if (cmd->advertising & ADVERTISED_100baseT_Half) { 502 bp->link_params.speed_cap_mask[cfg_idx] |= 503 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 504 } 505 if (cmd->advertising & ADVERTISED_1000baseT_Half) { 506 bp->link_params.speed_cap_mask[cfg_idx] |= 507 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 508 } 509 if (cmd->advertising & (ADVERTISED_1000baseT_Full | 510 ADVERTISED_1000baseKX_Full)) 511 bp->link_params.speed_cap_mask[cfg_idx] |= 512 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 513 514 if (cmd->advertising & (ADVERTISED_10000baseT_Full | 515 ADVERTISED_10000baseKX4_Full | 516 ADVERTISED_10000baseKR_Full)) 517 bp->link_params.speed_cap_mask[cfg_idx] |= 518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 519 520 if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 521 bp->link_params.speed_cap_mask[cfg_idx] |= 522 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 523 } 524 } else { /* forced speed */ 525 /* advertise the requested speed and duplex if supported */ 526 switch (speed) { 527 case SPEED_10: 528 if (cmd->duplex == DUPLEX_FULL) { 529 if (!(bp->port.supported[cfg_idx] & 530 SUPPORTED_10baseT_Full)) { 531 DP(BNX2X_MSG_ETHTOOL, 532 "10M full not supported\n"); 533 return -EINVAL; 534 } 535 536 advertising = (ADVERTISED_10baseT_Full | 537 ADVERTISED_TP); 538 } else { 539 if (!(bp->port.supported[cfg_idx] & 540 SUPPORTED_10baseT_Half)) { 541 DP(BNX2X_MSG_ETHTOOL, 542 "10M half not supported\n"); 543 return -EINVAL; 544 } 545 546 advertising = (ADVERTISED_10baseT_Half | 547 ADVERTISED_TP); 548 } 549 break; 550 551 case SPEED_100: 552 if (cmd->duplex == DUPLEX_FULL) { 553 if (!(bp->port.supported[cfg_idx] & 554 SUPPORTED_100baseT_Full)) { 555 DP(BNX2X_MSG_ETHTOOL, 556 "100M full not supported\n"); 557 return -EINVAL; 558 } 559 560 advertising = (ADVERTISED_100baseT_Full | 561 ADVERTISED_TP); 562 } else { 563 if (!(bp->port.supported[cfg_idx] & 564 SUPPORTED_100baseT_Half)) { 565 DP(BNX2X_MSG_ETHTOOL, 566 "100M half not supported\n"); 567 return -EINVAL; 568 } 569 570 advertising = (ADVERTISED_100baseT_Half | 571 ADVERTISED_TP); 572 } 573 break; 574 575 case SPEED_1000: 576 if (cmd->duplex != DUPLEX_FULL) { 577 DP(BNX2X_MSG_ETHTOOL, 578 "1G half not supported\n"); 579 return -EINVAL; 580 } 581 582 if (bp->port.supported[cfg_idx] & 583 SUPPORTED_1000baseT_Full) { 584 advertising = (ADVERTISED_1000baseT_Full | 585 ADVERTISED_TP); 586 587 } else if (bp->port.supported[cfg_idx] & 588 SUPPORTED_1000baseKX_Full) { 589 advertising = ADVERTISED_1000baseKX_Full; 590 } else { 591 DP(BNX2X_MSG_ETHTOOL, 592 "1G full not supported\n"); 593 return -EINVAL; 594 } 595 596 break; 597 598 case SPEED_2500: 599 if (cmd->duplex != DUPLEX_FULL) { 600 DP(BNX2X_MSG_ETHTOOL, 601 "2.5G half not supported\n"); 602 return -EINVAL; 603 } 604 605 if (!(bp->port.supported[cfg_idx] 606 & SUPPORTED_2500baseX_Full)) { 607 DP(BNX2X_MSG_ETHTOOL, 608 "2.5G full not supported\n"); 609 return -EINVAL; 610 } 611 612 advertising = (ADVERTISED_2500baseX_Full | 613 ADVERTISED_TP); 614 break; 615 616 case SPEED_10000: 617 if (cmd->duplex != DUPLEX_FULL) { 618 DP(BNX2X_MSG_ETHTOOL, 619 "10G half not supported\n"); 620 return -EINVAL; 621 } 622 phy_idx = bnx2x_get_cur_phy_idx(bp); 623 if ((bp->port.supported[cfg_idx] & 624 SUPPORTED_10000baseT_Full) && 625 (bp->link_params.phy[phy_idx].media_type != 626 ETH_PHY_SFP_1G_FIBER)) { 627 advertising = (ADVERTISED_10000baseT_Full | 628 ADVERTISED_FIBRE); 629 } else if (bp->port.supported[cfg_idx] & 630 SUPPORTED_10000baseKR_Full) { 631 advertising = (ADVERTISED_10000baseKR_Full | 632 ADVERTISED_FIBRE); 633 } else { 634 DP(BNX2X_MSG_ETHTOOL, 635 "10G full not supported\n"); 636 return -EINVAL; 637 } 638 639 break; 640 641 default: 642 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 643 return -EINVAL; 644 } 645 646 bp->link_params.req_line_speed[cfg_idx] = speed; 647 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 648 bp->port.advertising[cfg_idx] = advertising; 649 } 650 651 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 652 " req_duplex %d advertising 0x%x\n", 653 bp->link_params.req_line_speed[cfg_idx], 654 bp->link_params.req_duplex[cfg_idx], 655 bp->port.advertising[cfg_idx]); 656 657 /* Set new config */ 658 bp->link_params.multi_phy_config = new_multi_phy_config; 659 if (netif_running(dev)) { 660 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 661 bnx2x_force_link_reset(bp); 662 bnx2x_link_set(bp); 663 } 664 665 return 0; 666 } 667 668 #define DUMP_ALL_PRESETS 0x1FFF 669 #define DUMP_MAX_PRESETS 13 670 671 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 672 { 673 if (CHIP_IS_E1(bp)) 674 return dump_num_registers[0][preset-1]; 675 else if (CHIP_IS_E1H(bp)) 676 return dump_num_registers[1][preset-1]; 677 else if (CHIP_IS_E2(bp)) 678 return dump_num_registers[2][preset-1]; 679 else if (CHIP_IS_E3A0(bp)) 680 return dump_num_registers[3][preset-1]; 681 else if (CHIP_IS_E3B0(bp)) 682 return dump_num_registers[4][preset-1]; 683 else 684 return 0; 685 } 686 687 static int __bnx2x_get_regs_len(struct bnx2x *bp) 688 { 689 u32 preset_idx; 690 int regdump_len = 0; 691 692 /* Calculate the total preset regs length */ 693 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 694 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 695 696 return regdump_len; 697 } 698 699 static int bnx2x_get_regs_len(struct net_device *dev) 700 { 701 struct bnx2x *bp = netdev_priv(dev); 702 int regdump_len = 0; 703 704 if (IS_VF(bp)) 705 return 0; 706 707 regdump_len = __bnx2x_get_regs_len(bp); 708 regdump_len *= 4; 709 regdump_len += sizeof(struct dump_header); 710 711 return regdump_len; 712 } 713 714 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 715 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 716 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 717 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 718 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 719 720 #define IS_REG_IN_PRESET(presets, idx) \ 721 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 722 723 /******* Paged registers info selectors ********/ 724 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 725 { 726 if (CHIP_IS_E2(bp)) 727 return page_vals_e2; 728 else if (CHIP_IS_E3(bp)) 729 return page_vals_e3; 730 else 731 return NULL; 732 } 733 734 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 735 { 736 if (CHIP_IS_E2(bp)) 737 return PAGE_MODE_VALUES_E2; 738 else if (CHIP_IS_E3(bp)) 739 return PAGE_MODE_VALUES_E3; 740 else 741 return 0; 742 } 743 744 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 745 { 746 if (CHIP_IS_E2(bp)) 747 return page_write_regs_e2; 748 else if (CHIP_IS_E3(bp)) 749 return page_write_regs_e3; 750 else 751 return NULL; 752 } 753 754 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 755 { 756 if (CHIP_IS_E2(bp)) 757 return PAGE_WRITE_REGS_E2; 758 else if (CHIP_IS_E3(bp)) 759 return PAGE_WRITE_REGS_E3; 760 else 761 return 0; 762 } 763 764 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 765 { 766 if (CHIP_IS_E2(bp)) 767 return page_read_regs_e2; 768 else if (CHIP_IS_E3(bp)) 769 return page_read_regs_e3; 770 else 771 return NULL; 772 } 773 774 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 775 { 776 if (CHIP_IS_E2(bp)) 777 return PAGE_READ_REGS_E2; 778 else if (CHIP_IS_E3(bp)) 779 return PAGE_READ_REGS_E3; 780 else 781 return 0; 782 } 783 784 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 785 const struct reg_addr *reg_info) 786 { 787 if (CHIP_IS_E1(bp)) 788 return IS_E1_REG(reg_info->chips); 789 else if (CHIP_IS_E1H(bp)) 790 return IS_E1H_REG(reg_info->chips); 791 else if (CHIP_IS_E2(bp)) 792 return IS_E2_REG(reg_info->chips); 793 else if (CHIP_IS_E3A0(bp)) 794 return IS_E3A0_REG(reg_info->chips); 795 else if (CHIP_IS_E3B0(bp)) 796 return IS_E3B0_REG(reg_info->chips); 797 else 798 return false; 799 } 800 801 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 802 const struct wreg_addr *wreg_info) 803 { 804 if (CHIP_IS_E1(bp)) 805 return IS_E1_REG(wreg_info->chips); 806 else if (CHIP_IS_E1H(bp)) 807 return IS_E1H_REG(wreg_info->chips); 808 else if (CHIP_IS_E2(bp)) 809 return IS_E2_REG(wreg_info->chips); 810 else if (CHIP_IS_E3A0(bp)) 811 return IS_E3A0_REG(wreg_info->chips); 812 else if (CHIP_IS_E3B0(bp)) 813 return IS_E3B0_REG(wreg_info->chips); 814 else 815 return false; 816 } 817 818 /** 819 * bnx2x_read_pages_regs - read "paged" registers 820 * 821 * @bp device handle 822 * @p output buffer 823 * 824 * Reads "paged" memories: memories that may only be read by first writing to a 825 * specific address ("write address") and then reading from a specific address 826 * ("read address"). There may be more than one write address per "page" and 827 * more than one read address per write address. 828 */ 829 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 830 { 831 u32 i, j, k, n; 832 833 /* addresses of the paged registers */ 834 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 835 /* number of paged registers */ 836 int num_pages = __bnx2x_get_page_reg_num(bp); 837 /* write addresses */ 838 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 839 /* number of write addresses */ 840 int write_num = __bnx2x_get_page_write_num(bp); 841 /* read addresses info */ 842 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 843 /* number of read addresses */ 844 int read_num = __bnx2x_get_page_read_num(bp); 845 u32 addr, size; 846 847 for (i = 0; i < num_pages; i++) { 848 for (j = 0; j < write_num; j++) { 849 REG_WR(bp, write_addr[j], page_addr[i]); 850 851 for (k = 0; k < read_num; k++) { 852 if (IS_REG_IN_PRESET(read_addr[k].presets, 853 preset)) { 854 size = read_addr[k].size; 855 for (n = 0; n < size; n++) { 856 addr = read_addr[k].addr + n*4; 857 *p++ = REG_RD(bp, addr); 858 } 859 } 860 } 861 } 862 } 863 } 864 865 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 866 { 867 u32 i, j, addr; 868 const struct wreg_addr *wreg_addr_p = NULL; 869 870 if (CHIP_IS_E1(bp)) 871 wreg_addr_p = &wreg_addr_e1; 872 else if (CHIP_IS_E1H(bp)) 873 wreg_addr_p = &wreg_addr_e1h; 874 else if (CHIP_IS_E2(bp)) 875 wreg_addr_p = &wreg_addr_e2; 876 else if (CHIP_IS_E3A0(bp)) 877 wreg_addr_p = &wreg_addr_e3; 878 else if (CHIP_IS_E3B0(bp)) 879 wreg_addr_p = &wreg_addr_e3b0; 880 881 /* Read the idle_chk registers */ 882 for (i = 0; i < IDLE_REGS_COUNT; i++) { 883 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 884 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 885 for (j = 0; j < idle_reg_addrs[i].size; j++) 886 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 887 } 888 } 889 890 /* Read the regular registers */ 891 for (i = 0; i < REGS_COUNT; i++) { 892 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 893 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 894 for (j = 0; j < reg_addrs[i].size; j++) 895 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 896 } 897 } 898 899 /* Read the CAM registers */ 900 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 901 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 902 for (i = 0; i < wreg_addr_p->size; i++) { 903 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 904 905 /* In case of wreg_addr register, read additional 906 registers from read_regs array 907 */ 908 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 909 addr = *(wreg_addr_p->read_regs); 910 *p++ = REG_RD(bp, addr + j*4); 911 } 912 } 913 } 914 915 /* Paged registers are supported in E2 & E3 only */ 916 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 917 /* Read "paged" registers */ 918 bnx2x_read_pages_regs(bp, p, preset); 919 } 920 921 return 0; 922 } 923 924 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 925 { 926 u32 preset_idx; 927 928 /* Read all registers, by reading all preset registers */ 929 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 930 /* Skip presets with IOR */ 931 if ((preset_idx == 2) || 932 (preset_idx == 5) || 933 (preset_idx == 8) || 934 (preset_idx == 11)) 935 continue; 936 __bnx2x_get_preset_regs(bp, p, preset_idx); 937 p += __bnx2x_get_preset_regs_len(bp, preset_idx); 938 } 939 } 940 941 static void bnx2x_get_regs(struct net_device *dev, 942 struct ethtool_regs *regs, void *_p) 943 { 944 u32 *p = _p; 945 struct bnx2x *bp = netdev_priv(dev); 946 struct dump_header dump_hdr = {0}; 947 948 regs->version = 2; 949 memset(p, 0, regs->len); 950 951 if (!netif_running(bp->dev)) 952 return; 953 954 /* Disable parity attentions as long as following dump may 955 * cause false alarms by reading never written registers. We 956 * will re-enable parity attentions right after the dump. 957 */ 958 959 bnx2x_disable_blocks_parity(bp); 960 961 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 962 dump_hdr.preset = DUMP_ALL_PRESETS; 963 dump_hdr.version = BNX2X_DUMP_VERSION; 964 965 /* dump_meta_data presents OR of CHIP and PATH. */ 966 if (CHIP_IS_E1(bp)) { 967 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 968 } else if (CHIP_IS_E1H(bp)) { 969 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 970 } else if (CHIP_IS_E2(bp)) { 971 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 972 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 973 } else if (CHIP_IS_E3A0(bp)) { 974 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 975 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 976 } else if (CHIP_IS_E3B0(bp)) { 977 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 978 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 979 } 980 981 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 982 p += dump_hdr.header_size + 1; 983 984 /* Actually read the registers */ 985 __bnx2x_get_regs(bp, p); 986 987 /* Re-enable parity attentions */ 988 bnx2x_clear_blocks_parity(bp); 989 bnx2x_enable_blocks_parity(bp); 990 } 991 992 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 993 { 994 struct bnx2x *bp = netdev_priv(dev); 995 int regdump_len = 0; 996 997 regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 998 regdump_len *= 4; 999 regdump_len += sizeof(struct dump_header); 1000 1001 return regdump_len; 1002 } 1003 1004 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 1005 { 1006 struct bnx2x *bp = netdev_priv(dev); 1007 1008 /* Use the ethtool_dump "flag" field as the dump preset index */ 1009 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 1010 return -EINVAL; 1011 1012 bp->dump_preset_idx = val->flag; 1013 return 0; 1014 } 1015 1016 static int bnx2x_get_dump_flag(struct net_device *dev, 1017 struct ethtool_dump *dump) 1018 { 1019 struct bnx2x *bp = netdev_priv(dev); 1020 1021 dump->version = BNX2X_DUMP_VERSION; 1022 dump->flag = bp->dump_preset_idx; 1023 /* Calculate the requested preset idx length */ 1024 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 1025 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 1026 bp->dump_preset_idx, dump->len); 1027 return 0; 1028 } 1029 1030 static int bnx2x_get_dump_data(struct net_device *dev, 1031 struct ethtool_dump *dump, 1032 void *buffer) 1033 { 1034 u32 *p = buffer; 1035 struct bnx2x *bp = netdev_priv(dev); 1036 struct dump_header dump_hdr = {0}; 1037 1038 /* Disable parity attentions as long as following dump may 1039 * cause false alarms by reading never written registers. We 1040 * will re-enable parity attentions right after the dump. 1041 */ 1042 1043 bnx2x_disable_blocks_parity(bp); 1044 1045 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 1046 dump_hdr.preset = bp->dump_preset_idx; 1047 dump_hdr.version = BNX2X_DUMP_VERSION; 1048 1049 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 1050 1051 /* dump_meta_data presents OR of CHIP and PATH. */ 1052 if (CHIP_IS_E1(bp)) { 1053 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 1054 } else if (CHIP_IS_E1H(bp)) { 1055 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 1056 } else if (CHIP_IS_E2(bp)) { 1057 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 1058 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1059 } else if (CHIP_IS_E3A0(bp)) { 1060 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 1061 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1062 } else if (CHIP_IS_E3B0(bp)) { 1063 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 1064 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1065 } 1066 1067 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1068 p += dump_hdr.header_size + 1; 1069 1070 /* Actually read the registers */ 1071 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1072 1073 /* Re-enable parity attentions */ 1074 bnx2x_clear_blocks_parity(bp); 1075 bnx2x_enable_blocks_parity(bp); 1076 1077 return 0; 1078 } 1079 1080 static void bnx2x_get_drvinfo(struct net_device *dev, 1081 struct ethtool_drvinfo *info) 1082 { 1083 struct bnx2x *bp = netdev_priv(dev); 1084 1085 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1086 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1087 1088 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 1089 1090 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1091 } 1092 1093 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1094 { 1095 struct bnx2x *bp = netdev_priv(dev); 1096 1097 if (bp->flags & NO_WOL_FLAG) { 1098 wol->supported = 0; 1099 wol->wolopts = 0; 1100 } else { 1101 wol->supported = WAKE_MAGIC; 1102 if (bp->wol) 1103 wol->wolopts = WAKE_MAGIC; 1104 else 1105 wol->wolopts = 0; 1106 } 1107 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1108 } 1109 1110 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1111 { 1112 struct bnx2x *bp = netdev_priv(dev); 1113 1114 if (wol->wolopts & ~WAKE_MAGIC) { 1115 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1116 return -EINVAL; 1117 } 1118 1119 if (wol->wolopts & WAKE_MAGIC) { 1120 if (bp->flags & NO_WOL_FLAG) { 1121 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1122 return -EINVAL; 1123 } 1124 bp->wol = 1; 1125 } else 1126 bp->wol = 0; 1127 1128 if (SHMEM2_HAS(bp, curr_cfg)) 1129 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1130 1131 return 0; 1132 } 1133 1134 static u32 bnx2x_get_msglevel(struct net_device *dev) 1135 { 1136 struct bnx2x *bp = netdev_priv(dev); 1137 1138 return bp->msg_enable; 1139 } 1140 1141 static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1142 { 1143 struct bnx2x *bp = netdev_priv(dev); 1144 1145 if (capable(CAP_NET_ADMIN)) { 1146 /* dump MCP trace */ 1147 if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1148 bnx2x_fw_dump_lvl(bp, KERN_INFO); 1149 bp->msg_enable = level; 1150 } 1151 } 1152 1153 static int bnx2x_nway_reset(struct net_device *dev) 1154 { 1155 struct bnx2x *bp = netdev_priv(dev); 1156 1157 if (!bp->port.pmf) 1158 return 0; 1159 1160 if (netif_running(dev)) { 1161 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1162 bnx2x_force_link_reset(bp); 1163 bnx2x_link_set(bp); 1164 } 1165 1166 return 0; 1167 } 1168 1169 static u32 bnx2x_get_link(struct net_device *dev) 1170 { 1171 struct bnx2x *bp = netdev_priv(dev); 1172 1173 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1174 return 0; 1175 1176 if (IS_VF(bp)) 1177 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1178 &bp->vf_link_vars.link_report_flags); 1179 1180 return bp->link_vars.link_up; 1181 } 1182 1183 static int bnx2x_get_eeprom_len(struct net_device *dev) 1184 { 1185 struct bnx2x *bp = netdev_priv(dev); 1186 1187 return bp->common.flash_size; 1188 } 1189 1190 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1191 * had we done things the other way around, if two pfs from the same port would 1192 * attempt to access nvram at the same time, we could run into a scenario such 1193 * as: 1194 * pf A takes the port lock. 1195 * pf B succeeds in taking the same lock since they are from the same port. 1196 * pf A takes the per pf misc lock. Performs eeprom access. 1197 * pf A finishes. Unlocks the per pf misc lock. 1198 * Pf B takes the lock and proceeds to perform it's own access. 1199 * pf A unlocks the per port lock, while pf B is still working (!). 1200 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1201 * access corrupted by pf B) 1202 */ 1203 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1204 { 1205 int port = BP_PORT(bp); 1206 int count, i; 1207 u32 val; 1208 1209 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1210 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1211 1212 /* adjust timeout for emulation/FPGA */ 1213 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1214 if (CHIP_REV_IS_SLOW(bp)) 1215 count *= 100; 1216 1217 /* request access to nvram interface */ 1218 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1219 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1220 1221 for (i = 0; i < count*10; i++) { 1222 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1223 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1224 break; 1225 1226 udelay(5); 1227 } 1228 1229 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1230 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1231 "cannot get access to nvram interface\n"); 1232 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1233 return -EBUSY; 1234 } 1235 1236 return 0; 1237 } 1238 1239 static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1240 { 1241 int port = BP_PORT(bp); 1242 int count, i; 1243 u32 val; 1244 1245 /* adjust timeout for emulation/FPGA */ 1246 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1247 if (CHIP_REV_IS_SLOW(bp)) 1248 count *= 100; 1249 1250 /* relinquish nvram interface */ 1251 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1252 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1253 1254 for (i = 0; i < count*10; i++) { 1255 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1256 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1257 break; 1258 1259 udelay(5); 1260 } 1261 1262 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1263 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1264 "cannot free access to nvram interface\n"); 1265 return -EBUSY; 1266 } 1267 1268 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1269 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1270 return 0; 1271 } 1272 1273 static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1274 { 1275 u32 val; 1276 1277 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1278 1279 /* enable both bits, even on read */ 1280 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1281 (val | MCPR_NVM_ACCESS_ENABLE_EN | 1282 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1283 } 1284 1285 static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1286 { 1287 u32 val; 1288 1289 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1290 1291 /* disable both bits, even after read */ 1292 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1293 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1294 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1295 } 1296 1297 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1298 u32 cmd_flags) 1299 { 1300 int count, i, rc; 1301 u32 val; 1302 1303 /* build the command word */ 1304 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1305 1306 /* need to clear DONE bit separately */ 1307 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1308 1309 /* address of the NVRAM to read from */ 1310 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1311 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1312 1313 /* issue a read command */ 1314 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1315 1316 /* adjust timeout for emulation/FPGA */ 1317 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1318 if (CHIP_REV_IS_SLOW(bp)) 1319 count *= 100; 1320 1321 /* wait for completion */ 1322 *ret_val = 0; 1323 rc = -EBUSY; 1324 for (i = 0; i < count; i++) { 1325 udelay(5); 1326 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1327 1328 if (val & MCPR_NVM_COMMAND_DONE) { 1329 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1330 /* we read nvram data in cpu order 1331 * but ethtool sees it as an array of bytes 1332 * converting to big-endian will do the work 1333 */ 1334 *ret_val = cpu_to_be32(val); 1335 rc = 0; 1336 break; 1337 } 1338 } 1339 if (rc == -EBUSY) 1340 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1341 "nvram read timeout expired\n"); 1342 return rc; 1343 } 1344 1345 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1346 int buf_size) 1347 { 1348 int rc; 1349 u32 cmd_flags; 1350 __be32 val; 1351 1352 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1353 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1354 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1355 offset, buf_size); 1356 return -EINVAL; 1357 } 1358 1359 if (offset + buf_size > bp->common.flash_size) { 1360 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1361 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1362 offset, buf_size, bp->common.flash_size); 1363 return -EINVAL; 1364 } 1365 1366 /* request access to nvram interface */ 1367 rc = bnx2x_acquire_nvram_lock(bp); 1368 if (rc) 1369 return rc; 1370 1371 /* enable access to nvram interface */ 1372 bnx2x_enable_nvram_access(bp); 1373 1374 /* read the first word(s) */ 1375 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1376 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1377 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1378 memcpy(ret_buf, &val, 4); 1379 1380 /* advance to the next dword */ 1381 offset += sizeof(u32); 1382 ret_buf += sizeof(u32); 1383 buf_size -= sizeof(u32); 1384 cmd_flags = 0; 1385 } 1386 1387 if (rc == 0) { 1388 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1389 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1390 memcpy(ret_buf, &val, 4); 1391 } 1392 1393 /* disable access to nvram interface */ 1394 bnx2x_disable_nvram_access(bp); 1395 bnx2x_release_nvram_lock(bp); 1396 1397 return rc; 1398 } 1399 1400 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 1401 int buf_size) 1402 { 1403 int rc; 1404 1405 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 1406 1407 if (!rc) { 1408 __be32 *be = (__be32 *)buf; 1409 1410 while ((buf_size -= 4) >= 0) 1411 *buf++ = be32_to_cpu(*be++); 1412 } 1413 1414 return rc; 1415 } 1416 1417 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 1418 { 1419 int rc = 1; 1420 u16 pm = 0; 1421 struct net_device *dev = pci_get_drvdata(bp->pdev); 1422 1423 if (bp->pdev->pm_cap) 1424 rc = pci_read_config_word(bp->pdev, 1425 bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 1426 1427 if ((rc && !netif_running(dev)) || 1428 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 1429 return false; 1430 1431 return true; 1432 } 1433 1434 static int bnx2x_get_eeprom(struct net_device *dev, 1435 struct ethtool_eeprom *eeprom, u8 *eebuf) 1436 { 1437 struct bnx2x *bp = netdev_priv(dev); 1438 1439 if (!bnx2x_is_nvm_accessible(bp)) { 1440 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1441 "cannot access eeprom when the interface is down\n"); 1442 return -EAGAIN; 1443 } 1444 1445 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1446 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1447 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1448 eeprom->len, eeprom->len); 1449 1450 /* parameters already validated in ethtool_get_eeprom */ 1451 1452 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1453 } 1454 1455 static int bnx2x_get_module_eeprom(struct net_device *dev, 1456 struct ethtool_eeprom *ee, 1457 u8 *data) 1458 { 1459 struct bnx2x *bp = netdev_priv(dev); 1460 int rc = -EINVAL, phy_idx; 1461 u8 *user_data = data; 1462 unsigned int start_addr = ee->offset, xfer_size = 0; 1463 1464 if (!bnx2x_is_nvm_accessible(bp)) { 1465 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1466 "cannot access eeprom when the interface is down\n"); 1467 return -EAGAIN; 1468 } 1469 1470 phy_idx = bnx2x_get_cur_phy_idx(bp); 1471 1472 /* Read A0 section */ 1473 if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1474 /* Limit transfer size to the A0 section boundary */ 1475 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1476 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1477 else 1478 xfer_size = ee->len; 1479 bnx2x_acquire_phy_lock(bp); 1480 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1481 &bp->link_params, 1482 I2C_DEV_ADDR_A0, 1483 start_addr, 1484 xfer_size, 1485 user_data); 1486 bnx2x_release_phy_lock(bp); 1487 if (rc) { 1488 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1489 1490 return -EINVAL; 1491 } 1492 user_data += xfer_size; 1493 start_addr += xfer_size; 1494 } 1495 1496 /* Read A2 section */ 1497 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1498 (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1499 xfer_size = ee->len - xfer_size; 1500 /* Limit transfer size to the A2 section boundary */ 1501 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1502 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1503 start_addr -= ETH_MODULE_SFF_8079_LEN; 1504 bnx2x_acquire_phy_lock(bp); 1505 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1506 &bp->link_params, 1507 I2C_DEV_ADDR_A2, 1508 start_addr, 1509 xfer_size, 1510 user_data); 1511 bnx2x_release_phy_lock(bp); 1512 if (rc) { 1513 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1514 return -EINVAL; 1515 } 1516 } 1517 return rc; 1518 } 1519 1520 static int bnx2x_get_module_info(struct net_device *dev, 1521 struct ethtool_modinfo *modinfo) 1522 { 1523 struct bnx2x *bp = netdev_priv(dev); 1524 int phy_idx, rc; 1525 u8 sff8472_comp, diag_type; 1526 1527 if (!bnx2x_is_nvm_accessible(bp)) { 1528 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1529 "cannot access eeprom when the interface is down\n"); 1530 return -EAGAIN; 1531 } 1532 phy_idx = bnx2x_get_cur_phy_idx(bp); 1533 bnx2x_acquire_phy_lock(bp); 1534 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1535 &bp->link_params, 1536 I2C_DEV_ADDR_A0, 1537 SFP_EEPROM_SFF_8472_COMP_ADDR, 1538 SFP_EEPROM_SFF_8472_COMP_SIZE, 1539 &sff8472_comp); 1540 bnx2x_release_phy_lock(bp); 1541 if (rc) { 1542 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1543 return -EINVAL; 1544 } 1545 1546 bnx2x_acquire_phy_lock(bp); 1547 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1548 &bp->link_params, 1549 I2C_DEV_ADDR_A0, 1550 SFP_EEPROM_DIAG_TYPE_ADDR, 1551 SFP_EEPROM_DIAG_TYPE_SIZE, 1552 &diag_type); 1553 bnx2x_release_phy_lock(bp); 1554 if (rc) { 1555 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1556 return -EINVAL; 1557 } 1558 1559 if (!sff8472_comp || 1560 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 1561 modinfo->type = ETH_MODULE_SFF_8079; 1562 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1563 } else { 1564 modinfo->type = ETH_MODULE_SFF_8472; 1565 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1566 } 1567 return 0; 1568 } 1569 1570 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1571 u32 cmd_flags) 1572 { 1573 int count, i, rc; 1574 1575 /* build the command word */ 1576 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1577 1578 /* need to clear DONE bit separately */ 1579 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1580 1581 /* write the data */ 1582 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1583 1584 /* address of the NVRAM to write to */ 1585 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1586 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1587 1588 /* issue the write command */ 1589 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1590 1591 /* adjust timeout for emulation/FPGA */ 1592 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1593 if (CHIP_REV_IS_SLOW(bp)) 1594 count *= 100; 1595 1596 /* wait for completion */ 1597 rc = -EBUSY; 1598 for (i = 0; i < count; i++) { 1599 udelay(5); 1600 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1601 if (val & MCPR_NVM_COMMAND_DONE) { 1602 rc = 0; 1603 break; 1604 } 1605 } 1606 1607 if (rc == -EBUSY) 1608 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1609 "nvram write timeout expired\n"); 1610 return rc; 1611 } 1612 1613 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1614 1615 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1616 int buf_size) 1617 { 1618 int rc; 1619 u32 cmd_flags, align_offset, val; 1620 __be32 val_be; 1621 1622 if (offset + buf_size > bp->common.flash_size) { 1623 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1624 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1625 offset, buf_size, bp->common.flash_size); 1626 return -EINVAL; 1627 } 1628 1629 /* request access to nvram interface */ 1630 rc = bnx2x_acquire_nvram_lock(bp); 1631 if (rc) 1632 return rc; 1633 1634 /* enable access to nvram interface */ 1635 bnx2x_enable_nvram_access(bp); 1636 1637 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1638 align_offset = (offset & ~0x03); 1639 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1640 1641 if (rc == 0) { 1642 /* nvram data is returned as an array of bytes 1643 * convert it back to cpu order 1644 */ 1645 val = be32_to_cpu(val_be); 1646 1647 val &= ~le32_to_cpu((__force __le32) 1648 (0xff << BYTE_OFFSET(offset))); 1649 val |= le32_to_cpu((__force __le32) 1650 (*data_buf << BYTE_OFFSET(offset))); 1651 1652 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1653 cmd_flags); 1654 } 1655 1656 /* disable access to nvram interface */ 1657 bnx2x_disable_nvram_access(bp); 1658 bnx2x_release_nvram_lock(bp); 1659 1660 return rc; 1661 } 1662 1663 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1664 int buf_size) 1665 { 1666 int rc; 1667 u32 cmd_flags; 1668 u32 val; 1669 u32 written_so_far; 1670 1671 if (buf_size == 1) /* ethtool */ 1672 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1673 1674 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1675 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1676 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1677 offset, buf_size); 1678 return -EINVAL; 1679 } 1680 1681 if (offset + buf_size > bp->common.flash_size) { 1682 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1683 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1684 offset, buf_size, bp->common.flash_size); 1685 return -EINVAL; 1686 } 1687 1688 /* request access to nvram interface */ 1689 rc = bnx2x_acquire_nvram_lock(bp); 1690 if (rc) 1691 return rc; 1692 1693 /* enable access to nvram interface */ 1694 bnx2x_enable_nvram_access(bp); 1695 1696 written_so_far = 0; 1697 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1698 while ((written_so_far < buf_size) && (rc == 0)) { 1699 if (written_so_far == (buf_size - sizeof(u32))) 1700 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1701 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1702 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1703 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1704 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1705 1706 memcpy(&val, data_buf, 4); 1707 1708 /* Notice unlike bnx2x_nvram_read_dword() this will not 1709 * change val using be32_to_cpu(), which causes data to flip 1710 * if the eeprom is read and then written back. This is due 1711 * to tools utilizing this functionality that would break 1712 * if this would be resolved. 1713 */ 1714 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1715 1716 /* advance to the next dword */ 1717 offset += sizeof(u32); 1718 data_buf += sizeof(u32); 1719 written_so_far += sizeof(u32); 1720 1721 /* At end of each 4Kb page, release nvram lock to allow MFW 1722 * chance to take it for its own use. 1723 */ 1724 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) && 1725 (written_so_far < buf_size)) { 1726 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1727 "Releasing NVM lock after offset 0x%x\n", 1728 (u32)(offset - sizeof(u32))); 1729 bnx2x_release_nvram_lock(bp); 1730 usleep_range(1000, 2000); 1731 rc = bnx2x_acquire_nvram_lock(bp); 1732 if (rc) 1733 return rc; 1734 } 1735 1736 cmd_flags = 0; 1737 } 1738 1739 /* disable access to nvram interface */ 1740 bnx2x_disable_nvram_access(bp); 1741 bnx2x_release_nvram_lock(bp); 1742 1743 return rc; 1744 } 1745 1746 static int bnx2x_set_eeprom(struct net_device *dev, 1747 struct ethtool_eeprom *eeprom, u8 *eebuf) 1748 { 1749 struct bnx2x *bp = netdev_priv(dev); 1750 int port = BP_PORT(bp); 1751 int rc = 0; 1752 u32 ext_phy_config; 1753 1754 if (!bnx2x_is_nvm_accessible(bp)) { 1755 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1756 "cannot access eeprom when the interface is down\n"); 1757 return -EAGAIN; 1758 } 1759 1760 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1761 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1762 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1763 eeprom->len, eeprom->len); 1764 1765 /* parameters already validated in ethtool_set_eeprom */ 1766 1767 /* PHY eeprom can be accessed only by the PMF */ 1768 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1769 !bp->port.pmf) { 1770 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1771 "wrong magic or interface is not pmf\n"); 1772 return -EINVAL; 1773 } 1774 1775 ext_phy_config = 1776 SHMEM_RD(bp, 1777 dev_info.port_hw_config[port].external_phy_config); 1778 1779 if (eeprom->magic == 0x50485950) { 1780 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1781 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1782 1783 bnx2x_acquire_phy_lock(bp); 1784 rc |= bnx2x_link_reset(&bp->link_params, 1785 &bp->link_vars, 0); 1786 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1787 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1788 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1789 MISC_REGISTERS_GPIO_HIGH, port); 1790 bnx2x_release_phy_lock(bp); 1791 bnx2x_link_report(bp); 1792 1793 } else if (eeprom->magic == 0x50485952) { 1794 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1795 if (bp->state == BNX2X_STATE_OPEN) { 1796 bnx2x_acquire_phy_lock(bp); 1797 rc |= bnx2x_link_reset(&bp->link_params, 1798 &bp->link_vars, 1); 1799 1800 rc |= bnx2x_phy_init(&bp->link_params, 1801 &bp->link_vars); 1802 bnx2x_release_phy_lock(bp); 1803 bnx2x_calc_fc_adv(bp); 1804 } 1805 } else if (eeprom->magic == 0x53985943) { 1806 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1807 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1808 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1809 1810 /* DSP Remove Download Mode */ 1811 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1812 MISC_REGISTERS_GPIO_LOW, port); 1813 1814 bnx2x_acquire_phy_lock(bp); 1815 1816 bnx2x_sfx7101_sp_sw_reset(bp, 1817 &bp->link_params.phy[EXT_PHY1]); 1818 1819 /* wait 0.5 sec to allow it to run */ 1820 msleep(500); 1821 bnx2x_ext_phy_hw_reset(bp, port); 1822 msleep(500); 1823 bnx2x_release_phy_lock(bp); 1824 } 1825 } else 1826 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1827 1828 return rc; 1829 } 1830 1831 static int bnx2x_get_coalesce(struct net_device *dev, 1832 struct ethtool_coalesce *coal) 1833 { 1834 struct bnx2x *bp = netdev_priv(dev); 1835 1836 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1837 1838 coal->rx_coalesce_usecs = bp->rx_ticks; 1839 coal->tx_coalesce_usecs = bp->tx_ticks; 1840 1841 return 0; 1842 } 1843 1844 static int bnx2x_set_coalesce(struct net_device *dev, 1845 struct ethtool_coalesce *coal) 1846 { 1847 struct bnx2x *bp = netdev_priv(dev); 1848 1849 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1850 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1851 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1852 1853 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1854 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1855 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1856 1857 if (netif_running(dev)) 1858 bnx2x_update_coalesce(bp); 1859 1860 return 0; 1861 } 1862 1863 static void bnx2x_get_ringparam(struct net_device *dev, 1864 struct ethtool_ringparam *ering) 1865 { 1866 struct bnx2x *bp = netdev_priv(dev); 1867 1868 ering->rx_max_pending = MAX_RX_AVAIL; 1869 1870 if (bp->rx_ring_size) 1871 ering->rx_pending = bp->rx_ring_size; 1872 else 1873 ering->rx_pending = MAX_RX_AVAIL; 1874 1875 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1876 ering->tx_pending = bp->tx_ring_size; 1877 } 1878 1879 static int bnx2x_set_ringparam(struct net_device *dev, 1880 struct ethtool_ringparam *ering) 1881 { 1882 struct bnx2x *bp = netdev_priv(dev); 1883 1884 DP(BNX2X_MSG_ETHTOOL, 1885 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 1886 ering->rx_pending, ering->tx_pending); 1887 1888 if (pci_num_vf(bp->pdev)) { 1889 DP(BNX2X_MSG_IOV, 1890 "VFs are enabled, can not change ring parameters\n"); 1891 return -EPERM; 1892 } 1893 1894 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1895 DP(BNX2X_MSG_ETHTOOL, 1896 "Handling parity error recovery. Try again later\n"); 1897 return -EAGAIN; 1898 } 1899 1900 if ((ering->rx_pending > MAX_RX_AVAIL) || 1901 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1902 MIN_RX_SIZE_TPA)) || 1903 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 1904 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 1905 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1906 return -EINVAL; 1907 } 1908 1909 bp->rx_ring_size = ering->rx_pending; 1910 bp->tx_ring_size = ering->tx_pending; 1911 1912 return bnx2x_reload_if_running(dev); 1913 } 1914 1915 static void bnx2x_get_pauseparam(struct net_device *dev, 1916 struct ethtool_pauseparam *epause) 1917 { 1918 struct bnx2x *bp = netdev_priv(dev); 1919 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1920 int cfg_reg; 1921 1922 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1923 BNX2X_FLOW_CTRL_AUTO); 1924 1925 if (!epause->autoneg) 1926 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1927 else 1928 cfg_reg = bp->link_params.req_fc_auto_adv; 1929 1930 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1931 BNX2X_FLOW_CTRL_RX); 1932 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1933 BNX2X_FLOW_CTRL_TX); 1934 1935 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1936 " autoneg %d rx_pause %d tx_pause %d\n", 1937 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1938 } 1939 1940 static int bnx2x_set_pauseparam(struct net_device *dev, 1941 struct ethtool_pauseparam *epause) 1942 { 1943 struct bnx2x *bp = netdev_priv(dev); 1944 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1945 if (IS_MF(bp)) 1946 return 0; 1947 1948 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1949 " autoneg %d rx_pause %d tx_pause %d\n", 1950 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1951 1952 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1953 1954 if (epause->rx_pause) 1955 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1956 1957 if (epause->tx_pause) 1958 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1959 1960 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1961 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1962 1963 if (epause->autoneg) { 1964 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1965 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1966 return -EINVAL; 1967 } 1968 1969 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1970 bp->link_params.req_flow_ctrl[cfg_idx] = 1971 BNX2X_FLOW_CTRL_AUTO; 1972 } 1973 bp->link_params.req_fc_auto_adv = 0; 1974 if (epause->rx_pause) 1975 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 1976 1977 if (epause->tx_pause) 1978 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1979 1980 if (!bp->link_params.req_fc_auto_adv) 1981 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1982 } 1983 1984 DP(BNX2X_MSG_ETHTOOL, 1985 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1986 1987 if (netif_running(dev)) { 1988 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1989 bnx2x_force_link_reset(bp); 1990 bnx2x_link_set(bp); 1991 } 1992 1993 return 0; 1994 } 1995 1996 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1997 "register_test (offline) ", 1998 "memory_test (offline) ", 1999 "int_loopback_test (offline)", 2000 "ext_loopback_test (offline)", 2001 "nvram_test (online) ", 2002 "interrupt_test (online) ", 2003 "link_test (online) " 2004 }; 2005 2006 enum { 2007 BNX2X_PRI_FLAG_ISCSI, 2008 BNX2X_PRI_FLAG_FCOE, 2009 BNX2X_PRI_FLAG_STORAGE, 2010 BNX2X_PRI_FLAG_LEN, 2011 }; 2012 2013 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 2014 "iSCSI offload support", 2015 "FCoE offload support", 2016 "Storage only interface" 2017 }; 2018 2019 static u32 bnx2x_eee_to_adv(u32 eee_adv) 2020 { 2021 u32 modes = 0; 2022 2023 if (eee_adv & SHMEM_EEE_100M_ADV) 2024 modes |= ADVERTISED_100baseT_Full; 2025 if (eee_adv & SHMEM_EEE_1G_ADV) 2026 modes |= ADVERTISED_1000baseT_Full; 2027 if (eee_adv & SHMEM_EEE_10G_ADV) 2028 modes |= ADVERTISED_10000baseT_Full; 2029 2030 return modes; 2031 } 2032 2033 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2034 { 2035 u32 eee_adv = 0; 2036 if (modes & ADVERTISED_100baseT_Full) 2037 eee_adv |= SHMEM_EEE_100M_ADV; 2038 if (modes & ADVERTISED_1000baseT_Full) 2039 eee_adv |= SHMEM_EEE_1G_ADV; 2040 if (modes & ADVERTISED_10000baseT_Full) 2041 eee_adv |= SHMEM_EEE_10G_ADV; 2042 2043 return eee_adv << shift; 2044 } 2045 2046 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2047 { 2048 struct bnx2x *bp = netdev_priv(dev); 2049 u32 eee_cfg; 2050 2051 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2052 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2053 return -EOPNOTSUPP; 2054 } 2055 2056 eee_cfg = bp->link_vars.eee_status; 2057 2058 edata->supported = 2059 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2060 SHMEM_EEE_SUPPORTED_SHIFT); 2061 2062 edata->advertised = 2063 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2064 SHMEM_EEE_ADV_STATUS_SHIFT); 2065 edata->lp_advertised = 2066 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2067 SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2068 2069 /* SHMEM value is in 16u units --> Convert to 1u units. */ 2070 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2071 2072 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2073 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2074 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2075 2076 return 0; 2077 } 2078 2079 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2080 { 2081 struct bnx2x *bp = netdev_priv(dev); 2082 u32 eee_cfg; 2083 u32 advertised; 2084 2085 if (IS_MF(bp)) 2086 return 0; 2087 2088 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2089 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2090 return -EOPNOTSUPP; 2091 } 2092 2093 eee_cfg = bp->link_vars.eee_status; 2094 2095 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2096 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2097 return -EOPNOTSUPP; 2098 } 2099 2100 advertised = bnx2x_adv_to_eee(edata->advertised, 2101 SHMEM_EEE_ADV_STATUS_SHIFT); 2102 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2103 DP(BNX2X_MSG_ETHTOOL, 2104 "Direct manipulation of EEE advertisement is not supported\n"); 2105 return -EINVAL; 2106 } 2107 2108 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2109 DP(BNX2X_MSG_ETHTOOL, 2110 "Maximal Tx Lpi timer supported is %x(u)\n", 2111 EEE_MODE_TIMER_MASK); 2112 return -EINVAL; 2113 } 2114 if (edata->tx_lpi_enabled && 2115 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2116 DP(BNX2X_MSG_ETHTOOL, 2117 "Minimal Tx Lpi timer supported is %d(u)\n", 2118 EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2119 return -EINVAL; 2120 } 2121 2122 /* All is well; Apply changes*/ 2123 if (edata->eee_enabled) 2124 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2125 else 2126 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2127 2128 if (edata->tx_lpi_enabled) 2129 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2130 else 2131 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2132 2133 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2134 bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2135 EEE_MODE_TIMER_MASK) | 2136 EEE_MODE_OVERRIDE_NVRAM | 2137 EEE_MODE_OUTPUT_TIME; 2138 2139 /* Restart link to propagate changes */ 2140 if (netif_running(dev)) { 2141 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2142 bnx2x_force_link_reset(bp); 2143 bnx2x_link_set(bp); 2144 } 2145 2146 return 0; 2147 } 2148 2149 enum { 2150 BNX2X_CHIP_E1_OFST = 0, 2151 BNX2X_CHIP_E1H_OFST, 2152 BNX2X_CHIP_E2_OFST, 2153 BNX2X_CHIP_E3_OFST, 2154 BNX2X_CHIP_E3B0_OFST, 2155 BNX2X_CHIP_MAX_OFST 2156 }; 2157 2158 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2159 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2160 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2161 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2162 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2163 2164 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2165 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2166 2167 static int bnx2x_test_registers(struct bnx2x *bp) 2168 { 2169 int idx, i, rc = -ENODEV; 2170 u32 wr_val = 0, hw; 2171 int port = BP_PORT(bp); 2172 static const struct { 2173 u32 hw; 2174 u32 offset0; 2175 u32 offset1; 2176 u32 mask; 2177 } reg_tbl[] = { 2178 /* 0 */ { BNX2X_CHIP_MASK_ALL, 2179 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2180 { BNX2X_CHIP_MASK_ALL, 2181 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2182 { BNX2X_CHIP_MASK_E1X, 2183 HC_REG_AGG_INT_0, 4, 0x000003ff }, 2184 { BNX2X_CHIP_MASK_ALL, 2185 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2186 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2187 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2188 { BNX2X_CHIP_MASK_E3B0, 2189 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2190 { BNX2X_CHIP_MASK_ALL, 2191 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2192 { BNX2X_CHIP_MASK_ALL, 2193 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2194 { BNX2X_CHIP_MASK_ALL, 2195 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2196 { BNX2X_CHIP_MASK_ALL, 2197 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2198 /* 10 */ { BNX2X_CHIP_MASK_ALL, 2199 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2200 { BNX2X_CHIP_MASK_ALL, 2201 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2202 { BNX2X_CHIP_MASK_ALL, 2203 QM_REG_CONNNUM_0, 4, 0x000fffff }, 2204 { BNX2X_CHIP_MASK_ALL, 2205 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2206 { BNX2X_CHIP_MASK_ALL, 2207 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2208 { BNX2X_CHIP_MASK_ALL, 2209 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2210 { BNX2X_CHIP_MASK_ALL, 2211 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2212 { BNX2X_CHIP_MASK_ALL, 2213 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2214 { BNX2X_CHIP_MASK_ALL, 2215 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2216 { BNX2X_CHIP_MASK_ALL, 2217 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2218 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2219 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2220 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2221 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2222 { BNX2X_CHIP_MASK_ALL, 2223 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2224 { BNX2X_CHIP_MASK_ALL, 2225 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2226 { BNX2X_CHIP_MASK_ALL, 2227 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2228 { BNX2X_CHIP_MASK_ALL, 2229 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2230 { BNX2X_CHIP_MASK_ALL, 2231 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2232 { BNX2X_CHIP_MASK_ALL, 2233 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2234 { BNX2X_CHIP_MASK_ALL, 2235 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2236 { BNX2X_CHIP_MASK_ALL, 2237 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2238 /* 30 */ { BNX2X_CHIP_MASK_ALL, 2239 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2240 { BNX2X_CHIP_MASK_ALL, 2241 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2242 { BNX2X_CHIP_MASK_ALL, 2243 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2244 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2245 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2246 { BNX2X_CHIP_MASK_ALL, 2247 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2248 { BNX2X_CHIP_MASK_ALL, 2249 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2250 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2251 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2252 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2253 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2254 2255 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2256 }; 2257 2258 if (!bnx2x_is_nvm_accessible(bp)) { 2259 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2260 "cannot access eeprom when the interface is down\n"); 2261 return rc; 2262 } 2263 2264 if (CHIP_IS_E1(bp)) 2265 hw = BNX2X_CHIP_MASK_E1; 2266 else if (CHIP_IS_E1H(bp)) 2267 hw = BNX2X_CHIP_MASK_E1H; 2268 else if (CHIP_IS_E2(bp)) 2269 hw = BNX2X_CHIP_MASK_E2; 2270 else if (CHIP_IS_E3B0(bp)) 2271 hw = BNX2X_CHIP_MASK_E3B0; 2272 else /* e3 A0 */ 2273 hw = BNX2X_CHIP_MASK_E3; 2274 2275 /* Repeat the test twice: 2276 * First by writing 0x00000000, second by writing 0xffffffff 2277 */ 2278 for (idx = 0; idx < 2; idx++) { 2279 2280 switch (idx) { 2281 case 0: 2282 wr_val = 0; 2283 break; 2284 case 1: 2285 wr_val = 0xffffffff; 2286 break; 2287 } 2288 2289 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2290 u32 offset, mask, save_val, val; 2291 if (!(hw & reg_tbl[i].hw)) 2292 continue; 2293 2294 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2295 mask = reg_tbl[i].mask; 2296 2297 save_val = REG_RD(bp, offset); 2298 2299 REG_WR(bp, offset, wr_val & mask); 2300 2301 val = REG_RD(bp, offset); 2302 2303 /* Restore the original register's value */ 2304 REG_WR(bp, offset, save_val); 2305 2306 /* verify value is as expected */ 2307 if ((val & mask) != (wr_val & mask)) { 2308 DP(BNX2X_MSG_ETHTOOL, 2309 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2310 offset, val, wr_val, mask); 2311 goto test_reg_exit; 2312 } 2313 } 2314 } 2315 2316 rc = 0; 2317 2318 test_reg_exit: 2319 return rc; 2320 } 2321 2322 static int bnx2x_test_memory(struct bnx2x *bp) 2323 { 2324 int i, j, rc = -ENODEV; 2325 u32 val, index; 2326 static const struct { 2327 u32 offset; 2328 int size; 2329 } mem_tbl[] = { 2330 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2331 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2332 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2333 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2334 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2335 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2336 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2337 2338 { 0xffffffff, 0 } 2339 }; 2340 2341 static const struct { 2342 char *name; 2343 u32 offset; 2344 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2345 } prty_tbl[] = { 2346 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2347 {0x3ffc0, 0, 0, 0} }, 2348 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2349 {0x2, 0x2, 0, 0} }, 2350 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2351 {0, 0, 0, 0} }, 2352 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2353 {0x3ffc0, 0, 0, 0} }, 2354 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2355 {0x3ffc0, 0, 0, 0} }, 2356 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2357 {0x3ffc1, 0, 0, 0} }, 2358 2359 { NULL, 0xffffffff, {0, 0, 0, 0} } 2360 }; 2361 2362 if (!bnx2x_is_nvm_accessible(bp)) { 2363 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2364 "cannot access eeprom when the interface is down\n"); 2365 return rc; 2366 } 2367 2368 if (CHIP_IS_E1(bp)) 2369 index = BNX2X_CHIP_E1_OFST; 2370 else if (CHIP_IS_E1H(bp)) 2371 index = BNX2X_CHIP_E1H_OFST; 2372 else if (CHIP_IS_E2(bp)) 2373 index = BNX2X_CHIP_E2_OFST; 2374 else /* e3 */ 2375 index = BNX2X_CHIP_E3_OFST; 2376 2377 /* pre-Check the parity status */ 2378 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2379 val = REG_RD(bp, prty_tbl[i].offset); 2380 if (val & ~(prty_tbl[i].hw_mask[index])) { 2381 DP(BNX2X_MSG_ETHTOOL, 2382 "%s is 0x%x\n", prty_tbl[i].name, val); 2383 goto test_mem_exit; 2384 } 2385 } 2386 2387 /* Go through all the memories */ 2388 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2389 for (j = 0; j < mem_tbl[i].size; j++) 2390 REG_RD(bp, mem_tbl[i].offset + j*4); 2391 2392 /* Check the parity status */ 2393 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2394 val = REG_RD(bp, prty_tbl[i].offset); 2395 if (val & ~(prty_tbl[i].hw_mask[index])) { 2396 DP(BNX2X_MSG_ETHTOOL, 2397 "%s is 0x%x\n", prty_tbl[i].name, val); 2398 goto test_mem_exit; 2399 } 2400 } 2401 2402 rc = 0; 2403 2404 test_mem_exit: 2405 return rc; 2406 } 2407 2408 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2409 { 2410 int cnt = 1400; 2411 2412 if (link_up) { 2413 while (bnx2x_link_test(bp, is_serdes) && cnt--) 2414 msleep(20); 2415 2416 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 2417 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 2418 2419 cnt = 1400; 2420 while (!bp->link_vars.link_up && cnt--) 2421 msleep(20); 2422 2423 if (cnt <= 0 && !bp->link_vars.link_up) 2424 DP(BNX2X_MSG_ETHTOOL, 2425 "Timeout waiting for link init\n"); 2426 } 2427 } 2428 2429 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2430 { 2431 unsigned int pkt_size, num_pkts, i; 2432 struct sk_buff *skb; 2433 unsigned char *packet; 2434 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2435 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 2436 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2437 u16 tx_start_idx, tx_idx; 2438 u16 rx_start_idx, rx_idx; 2439 u16 pkt_prod, bd_prod; 2440 struct sw_tx_bd *tx_buf; 2441 struct eth_tx_start_bd *tx_start_bd; 2442 dma_addr_t mapping; 2443 union eth_rx_cqe *cqe; 2444 u8 cqe_fp_flags, cqe_fp_type; 2445 struct sw_rx_bd *rx_buf; 2446 u16 len; 2447 int rc = -ENODEV; 2448 u8 *data; 2449 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 2450 txdata->txq_index); 2451 2452 /* check the loopback mode */ 2453 switch (loopback_mode) { 2454 case BNX2X_PHY_LOOPBACK: 2455 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 2456 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2457 return -EINVAL; 2458 } 2459 break; 2460 case BNX2X_MAC_LOOPBACK: 2461 if (CHIP_IS_E3(bp)) { 2462 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2463 if (bp->port.supported[cfg_idx] & 2464 (SUPPORTED_10000baseT_Full | 2465 SUPPORTED_20000baseMLD2_Full | 2466 SUPPORTED_20000baseKR2_Full)) 2467 bp->link_params.loopback_mode = LOOPBACK_XMAC; 2468 else 2469 bp->link_params.loopback_mode = LOOPBACK_UMAC; 2470 } else 2471 bp->link_params.loopback_mode = LOOPBACK_BMAC; 2472 2473 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2474 break; 2475 case BNX2X_EXT_LOOPBACK: 2476 if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 2477 DP(BNX2X_MSG_ETHTOOL, 2478 "Can't configure external loopback\n"); 2479 return -EINVAL; 2480 } 2481 break; 2482 default: 2483 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2484 return -EINVAL; 2485 } 2486 2487 /* prepare the loopback packet */ 2488 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2489 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2490 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2491 if (!skb) { 2492 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2493 rc = -ENOMEM; 2494 goto test_loopback_exit; 2495 } 2496 packet = skb_put(skb, pkt_size); 2497 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2498 eth_zero_addr(packet + ETH_ALEN); 2499 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2500 for (i = ETH_HLEN; i < pkt_size; i++) 2501 packet[i] = (unsigned char) (i & 0xff); 2502 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2503 skb_headlen(skb), DMA_TO_DEVICE); 2504 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2505 rc = -ENOMEM; 2506 dev_kfree_skb(skb); 2507 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2508 goto test_loopback_exit; 2509 } 2510 2511 /* send the loopback packet */ 2512 num_pkts = 0; 2513 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2514 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2515 2516 netdev_tx_sent_queue(txq, skb->len); 2517 2518 pkt_prod = txdata->tx_pkt_prod++; 2519 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2520 tx_buf->first_bd = txdata->tx_bd_prod; 2521 tx_buf->skb = skb; 2522 tx_buf->flags = 0; 2523 2524 bd_prod = TX_BD(txdata->tx_bd_prod); 2525 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2526 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2527 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2528 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2529 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2530 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2531 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2532 SET_FLAG(tx_start_bd->general_data, 2533 ETH_TX_START_BD_HDR_NBDS, 2534 1); 2535 SET_FLAG(tx_start_bd->general_data, 2536 ETH_TX_START_BD_PARSE_NBDS, 2537 0); 2538 2539 /* turn on parsing and get a BD */ 2540 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2541 2542 if (CHIP_IS_E1x(bp)) { 2543 u16 global_data = 0; 2544 struct eth_tx_parse_bd_e1x *pbd_e1x = 2545 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2546 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2547 SET_FLAG(global_data, 2548 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2549 pbd_e1x->global_data = cpu_to_le16(global_data); 2550 } else { 2551 u32 parsing_data = 0; 2552 struct eth_tx_parse_bd_e2 *pbd_e2 = 2553 &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2554 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2555 SET_FLAG(parsing_data, 2556 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2557 pbd_e2->parsing_data = cpu_to_le32(parsing_data); 2558 } 2559 wmb(); 2560 2561 txdata->tx_db.data.prod += 2; 2562 barrier(); 2563 DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2564 2565 mmiowb(); 2566 barrier(); 2567 2568 num_pkts++; 2569 txdata->tx_bd_prod += 2; /* start + pbd */ 2570 2571 udelay(100); 2572 2573 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2574 if (tx_idx != tx_start_idx + num_pkts) 2575 goto test_loopback_exit; 2576 2577 /* Unlike HC IGU won't generate an interrupt for status block 2578 * updates that have been performed while interrupts were 2579 * disabled. 2580 */ 2581 if (bp->common.int_block == INT_BLOCK_IGU) { 2582 /* Disable local BHes to prevent a dead-lock situation between 2583 * sch_direct_xmit() and bnx2x_run_loopback() (calling 2584 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2585 */ 2586 local_bh_disable(); 2587 bnx2x_tx_int(bp, txdata); 2588 local_bh_enable(); 2589 } 2590 2591 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2592 if (rx_idx != rx_start_idx + num_pkts) 2593 goto test_loopback_exit; 2594 2595 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2596 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2597 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2598 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2599 goto test_loopback_rx_exit; 2600 2601 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2602 if (len != pkt_size) 2603 goto test_loopback_rx_exit; 2604 2605 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2606 dma_sync_single_for_cpu(&bp->pdev->dev, 2607 dma_unmap_addr(rx_buf, mapping), 2608 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2609 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2610 for (i = ETH_HLEN; i < pkt_size; i++) 2611 if (*(data + i) != (unsigned char) (i & 0xff)) 2612 goto test_loopback_rx_exit; 2613 2614 rc = 0; 2615 2616 test_loopback_rx_exit: 2617 2618 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2619 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2620 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2621 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2622 2623 /* Update producers */ 2624 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2625 fp_rx->rx_sge_prod); 2626 2627 test_loopback_exit: 2628 bp->link_params.loopback_mode = LOOPBACK_NONE; 2629 2630 return rc; 2631 } 2632 2633 static int bnx2x_test_loopback(struct bnx2x *bp) 2634 { 2635 int rc = 0, res; 2636 2637 if (BP_NOMCP(bp)) 2638 return rc; 2639 2640 if (!netif_running(bp->dev)) 2641 return BNX2X_LOOPBACK_FAILED; 2642 2643 bnx2x_netif_stop(bp, 1); 2644 bnx2x_acquire_phy_lock(bp); 2645 2646 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2647 if (res) { 2648 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2649 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2650 } 2651 2652 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2653 if (res) { 2654 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2655 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2656 } 2657 2658 bnx2x_release_phy_lock(bp); 2659 bnx2x_netif_start(bp); 2660 2661 return rc; 2662 } 2663 2664 static int bnx2x_test_ext_loopback(struct bnx2x *bp) 2665 { 2666 int rc; 2667 u8 is_serdes = 2668 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2669 2670 if (BP_NOMCP(bp)) 2671 return -ENODEV; 2672 2673 if (!netif_running(bp->dev)) 2674 return BNX2X_EXT_LOOPBACK_FAILED; 2675 2676 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2677 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 2678 if (rc) { 2679 DP(BNX2X_MSG_ETHTOOL, 2680 "Can't perform self-test, nic_load (for external lb) failed\n"); 2681 return -ENODEV; 2682 } 2683 bnx2x_wait_for_link(bp, 1, is_serdes); 2684 2685 bnx2x_netif_stop(bp, 1); 2686 2687 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 2688 if (rc) 2689 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 2690 2691 bnx2x_netif_start(bp); 2692 2693 return rc; 2694 } 2695 2696 struct code_entry { 2697 u32 sram_start_addr; 2698 u32 code_attribute; 2699 #define CODE_IMAGE_TYPE_MASK 0xf0800003 2700 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2701 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2702 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2703 u32 nvm_start_addr; 2704 }; 2705 2706 #define CODE_ENTRY_MAX 16 2707 #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2708 #define MAX_IMAGES_IN_EXTENDED_DIR 64 2709 #define NVRAM_DIR_OFFSET 0x14 2710 2711 #define EXTENDED_DIR_EXISTS(code) \ 2712 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2713 (code & CODE_IMAGE_LENGTH_MASK) != 0) 2714 2715 #define CRC32_RESIDUAL 0xdebb20e3 2716 #define CRC_BUFF_SIZE 256 2717 2718 static int bnx2x_nvram_crc(struct bnx2x *bp, 2719 int offset, 2720 int size, 2721 u8 *buff) 2722 { 2723 u32 crc = ~0; 2724 int rc = 0, done = 0; 2725 2726 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2727 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2728 2729 while (done < size) { 2730 int count = min_t(int, size - done, CRC_BUFF_SIZE); 2731 2732 rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2733 2734 if (rc) 2735 return rc; 2736 2737 crc = crc32_le(crc, buff, count); 2738 done += count; 2739 } 2740 2741 if (crc != CRC32_RESIDUAL) 2742 rc = -EINVAL; 2743 2744 return rc; 2745 } 2746 2747 static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2748 struct code_entry *entry, 2749 u8 *buff) 2750 { 2751 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2752 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2753 int rc; 2754 2755 /* Zero-length images and AFEX profiles do not have CRC */ 2756 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2757 return 0; 2758 2759 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2760 if (rc) 2761 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2762 "image %x has failed crc test (rc %d)\n", type, rc); 2763 2764 return rc; 2765 } 2766 2767 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2768 { 2769 int rc; 2770 struct code_entry entry; 2771 2772 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2773 if (rc) 2774 return rc; 2775 2776 return bnx2x_test_nvram_dir(bp, &entry, buff); 2777 } 2778 2779 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2780 { 2781 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2782 struct code_entry entry; 2783 int i; 2784 2785 rc = bnx2x_nvram_read32(bp, 2786 dir_offset + 2787 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2788 (u32 *)&entry, sizeof(entry)); 2789 if (rc) 2790 return rc; 2791 2792 if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2793 return 0; 2794 2795 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2796 &cnt, sizeof(u32)); 2797 if (rc) 2798 return rc; 2799 2800 dir_offset = entry.nvm_start_addr + 8; 2801 2802 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2803 rc = bnx2x_test_dir_entry(bp, dir_offset + 2804 sizeof(struct code_entry) * i, 2805 buff); 2806 if (rc) 2807 return rc; 2808 } 2809 2810 return 0; 2811 } 2812 2813 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2814 { 2815 u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2816 int i; 2817 2818 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2819 2820 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2821 rc = bnx2x_test_dir_entry(bp, dir_offset + 2822 sizeof(struct code_entry) * i, 2823 buff); 2824 if (rc) 2825 return rc; 2826 } 2827 2828 return bnx2x_test_nvram_ext_dirs(bp, buff); 2829 } 2830 2831 struct crc_pair { 2832 int offset; 2833 int size; 2834 }; 2835 2836 static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2837 const struct crc_pair *nvram_tbl, u8 *buf) 2838 { 2839 int i; 2840 2841 for (i = 0; nvram_tbl[i].size; i++) { 2842 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2843 nvram_tbl[i].size, buf); 2844 if (rc) { 2845 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2846 "nvram_tbl[%d] has failed crc test (rc %d)\n", 2847 i, rc); 2848 return rc; 2849 } 2850 } 2851 2852 return 0; 2853 } 2854 2855 static int bnx2x_test_nvram(struct bnx2x *bp) 2856 { 2857 const struct crc_pair nvram_tbl[] = { 2858 { 0, 0x14 }, /* bootstrap */ 2859 { 0x14, 0xec }, /* dir */ 2860 { 0x100, 0x350 }, /* manuf_info */ 2861 { 0x450, 0xf0 }, /* feature_info */ 2862 { 0x640, 0x64 }, /* upgrade_key_info */ 2863 { 0x708, 0x70 }, /* manuf_key_info */ 2864 { 0, 0 } 2865 }; 2866 const struct crc_pair nvram_tbl2[] = { 2867 { 0x7e8, 0x350 }, /* manuf_info2 */ 2868 { 0xb38, 0xf0 }, /* feature_info */ 2869 { 0, 0 } 2870 }; 2871 2872 u8 *buf; 2873 int rc; 2874 u32 magic; 2875 2876 if (BP_NOMCP(bp)) 2877 return 0; 2878 2879 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2880 if (!buf) { 2881 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2882 rc = -ENOMEM; 2883 goto test_nvram_exit; 2884 } 2885 2886 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2887 if (rc) { 2888 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2889 "magic value read (rc %d)\n", rc); 2890 goto test_nvram_exit; 2891 } 2892 2893 if (magic != 0x669955aa) { 2894 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2895 "wrong magic value (0x%08x)\n", magic); 2896 rc = -ENODEV; 2897 goto test_nvram_exit; 2898 } 2899 2900 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2901 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2902 if (rc) 2903 goto test_nvram_exit; 2904 2905 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2906 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2907 SHARED_HW_CFG_HIDE_PORT1; 2908 2909 if (!hide) { 2910 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2911 "Port 1 CRC test-set\n"); 2912 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2913 if (rc) 2914 goto test_nvram_exit; 2915 } 2916 } 2917 2918 rc = bnx2x_test_nvram_dirs(bp, buf); 2919 2920 test_nvram_exit: 2921 kfree(buf); 2922 return rc; 2923 } 2924 2925 /* Send an EMPTY ramrod on the first queue */ 2926 static int bnx2x_test_intr(struct bnx2x *bp) 2927 { 2928 struct bnx2x_queue_state_params params = {NULL}; 2929 2930 if (!netif_running(bp->dev)) { 2931 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2932 "cannot access eeprom when the interface is down\n"); 2933 return -ENODEV; 2934 } 2935 2936 params.q_obj = &bp->sp_objs->q_obj; 2937 params.cmd = BNX2X_Q_CMD_EMPTY; 2938 2939 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2940 2941 return bnx2x_queue_state_change(bp, ¶ms); 2942 } 2943 2944 static void bnx2x_self_test(struct net_device *dev, 2945 struct ethtool_test *etest, u64 *buf) 2946 { 2947 struct bnx2x *bp = netdev_priv(dev); 2948 u8 is_serdes, link_up; 2949 int rc, cnt = 0; 2950 2951 if (pci_num_vf(bp->pdev)) { 2952 DP(BNX2X_MSG_IOV, 2953 "VFs are enabled, can not perform self test\n"); 2954 return; 2955 } 2956 2957 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2958 netdev_err(bp->dev, 2959 "Handling parity error recovery. Try again later\n"); 2960 etest->flags |= ETH_TEST_FL_FAILED; 2961 return; 2962 } 2963 2964 DP(BNX2X_MSG_ETHTOOL, 2965 "Self-test command parameters: offline = %d, external_lb = %d\n", 2966 (etest->flags & ETH_TEST_FL_OFFLINE), 2967 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2968 2969 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2970 2971 if (bnx2x_test_nvram(bp) != 0) { 2972 if (!IS_MF(bp)) 2973 buf[4] = 1; 2974 else 2975 buf[0] = 1; 2976 etest->flags |= ETH_TEST_FL_FAILED; 2977 } 2978 2979 if (!netif_running(dev)) { 2980 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2981 return; 2982 } 2983 2984 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2985 link_up = bp->link_vars.link_up; 2986 /* offline tests are not supported in MF mode */ 2987 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2988 int port = BP_PORT(bp); 2989 u32 val; 2990 2991 /* save current value of input enable for TX port IF */ 2992 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2993 /* disable input for TX port IF */ 2994 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2995 2996 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2997 rc = bnx2x_nic_load(bp, LOAD_DIAG); 2998 if (rc) { 2999 etest->flags |= ETH_TEST_FL_FAILED; 3000 DP(BNX2X_MSG_ETHTOOL, 3001 "Can't perform self-test, nic_load (for offline) failed\n"); 3002 return; 3003 } 3004 3005 /* wait until link state is restored */ 3006 bnx2x_wait_for_link(bp, 1, is_serdes); 3007 3008 if (bnx2x_test_registers(bp) != 0) { 3009 buf[0] = 1; 3010 etest->flags |= ETH_TEST_FL_FAILED; 3011 } 3012 if (bnx2x_test_memory(bp) != 0) { 3013 buf[1] = 1; 3014 etest->flags |= ETH_TEST_FL_FAILED; 3015 } 3016 3017 buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3018 if (buf[2] != 0) 3019 etest->flags |= ETH_TEST_FL_FAILED; 3020 3021 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 3022 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 3023 if (buf[3] != 0) 3024 etest->flags |= ETH_TEST_FL_FAILED; 3025 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3026 } 3027 3028 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3029 3030 /* restore input for TX port IF */ 3031 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3032 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3033 if (rc) { 3034 etest->flags |= ETH_TEST_FL_FAILED; 3035 DP(BNX2X_MSG_ETHTOOL, 3036 "Can't perform self-test, nic_load (for online) failed\n"); 3037 return; 3038 } 3039 /* wait until link state is restored */ 3040 bnx2x_wait_for_link(bp, link_up, is_serdes); 3041 } 3042 3043 if (bnx2x_test_intr(bp) != 0) { 3044 if (!IS_MF(bp)) 3045 buf[5] = 1; 3046 else 3047 buf[1] = 1; 3048 etest->flags |= ETH_TEST_FL_FAILED; 3049 } 3050 3051 if (link_up) { 3052 cnt = 100; 3053 while (bnx2x_link_test(bp, is_serdes) && --cnt) 3054 msleep(20); 3055 } 3056 3057 if (!cnt) { 3058 if (!IS_MF(bp)) 3059 buf[6] = 1; 3060 else 3061 buf[2] = 1; 3062 etest->flags |= ETH_TEST_FL_FAILED; 3063 } 3064 } 3065 3066 #define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat) 3067 #define HIDE_PORT_STAT(bp) IS_VF(bp) 3068 3069 /* ethtool statistics are displayed for all regular ethernet queues and the 3070 * fcoe L2 queue if not disabled 3071 */ 3072 static int bnx2x_num_stat_queues(struct bnx2x *bp) 3073 { 3074 return BNX2X_NUM_ETH_QUEUES(bp); 3075 } 3076 3077 static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3078 { 3079 struct bnx2x *bp = netdev_priv(dev); 3080 int i, num_strings = 0; 3081 3082 switch (stringset) { 3083 case ETH_SS_STATS: 3084 if (is_multi(bp)) { 3085 num_strings = bnx2x_num_stat_queues(bp) * 3086 BNX2X_NUM_Q_STATS; 3087 } else 3088 num_strings = 0; 3089 if (HIDE_PORT_STAT(bp)) { 3090 for (i = 0; i < BNX2X_NUM_STATS; i++) 3091 if (!IS_PORT_STAT(i)) 3092 num_strings++; 3093 } else 3094 num_strings += BNX2X_NUM_STATS; 3095 3096 return num_strings; 3097 3098 case ETH_SS_TEST: 3099 return BNX2X_NUM_TESTS(bp); 3100 3101 case ETH_SS_PRIV_FLAGS: 3102 return BNX2X_PRI_FLAG_LEN; 3103 3104 default: 3105 return -EINVAL; 3106 } 3107 } 3108 3109 static u32 bnx2x_get_private_flags(struct net_device *dev) 3110 { 3111 struct bnx2x *bp = netdev_priv(dev); 3112 u32 flags = 0; 3113 3114 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 3115 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 3116 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 3117 3118 return flags; 3119 } 3120 3121 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3122 { 3123 struct bnx2x *bp = netdev_priv(dev); 3124 int i, j, k, start; 3125 char queue_name[MAX_QUEUE_NAME_LEN+1]; 3126 3127 switch (stringset) { 3128 case ETH_SS_STATS: 3129 k = 0; 3130 if (is_multi(bp)) { 3131 for_each_eth_queue(bp, i) { 3132 memset(queue_name, 0, sizeof(queue_name)); 3133 sprintf(queue_name, "%d", i); 3134 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3135 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3136 ETH_GSTRING_LEN, 3137 bnx2x_q_stats_arr[j].string, 3138 queue_name); 3139 k += BNX2X_NUM_Q_STATS; 3140 } 3141 } 3142 3143 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3144 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3145 continue; 3146 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3147 bnx2x_stats_arr[i].string); 3148 j++; 3149 } 3150 3151 break; 3152 3153 case ETH_SS_TEST: 3154 /* First 4 tests cannot be done in MF mode */ 3155 if (!IS_MF(bp)) 3156 start = 0; 3157 else 3158 start = 4; 3159 memcpy(buf, bnx2x_tests_str_arr + start, 3160 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 3161 break; 3162 3163 case ETH_SS_PRIV_FLAGS: 3164 memcpy(buf, bnx2x_private_arr, 3165 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 3166 break; 3167 } 3168 } 3169 3170 static void bnx2x_get_ethtool_stats(struct net_device *dev, 3171 struct ethtool_stats *stats, u64 *buf) 3172 { 3173 struct bnx2x *bp = netdev_priv(dev); 3174 u32 *hw_stats, *offset; 3175 int i, j, k = 0; 3176 3177 if (is_multi(bp)) { 3178 for_each_eth_queue(bp, i) { 3179 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3180 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3181 if (bnx2x_q_stats_arr[j].size == 0) { 3182 /* skip this counter */ 3183 buf[k + j] = 0; 3184 continue; 3185 } 3186 offset = (hw_stats + 3187 bnx2x_q_stats_arr[j].offset); 3188 if (bnx2x_q_stats_arr[j].size == 4) { 3189 /* 4-byte counter */ 3190 buf[k + j] = (u64) *offset; 3191 continue; 3192 } 3193 /* 8-byte counter */ 3194 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3195 } 3196 k += BNX2X_NUM_Q_STATS; 3197 } 3198 } 3199 3200 hw_stats = (u32 *)&bp->eth_stats; 3201 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3202 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3203 continue; 3204 if (bnx2x_stats_arr[i].size == 0) { 3205 /* skip this counter */ 3206 buf[k + j] = 0; 3207 j++; 3208 continue; 3209 } 3210 offset = (hw_stats + bnx2x_stats_arr[i].offset); 3211 if (bnx2x_stats_arr[i].size == 4) { 3212 /* 4-byte counter */ 3213 buf[k + j] = (u64) *offset; 3214 j++; 3215 continue; 3216 } 3217 /* 8-byte counter */ 3218 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3219 j++; 3220 } 3221 } 3222 3223 static int bnx2x_set_phys_id(struct net_device *dev, 3224 enum ethtool_phys_id_state state) 3225 { 3226 struct bnx2x *bp = netdev_priv(dev); 3227 3228 if (!bnx2x_is_nvm_accessible(bp)) { 3229 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 3230 "cannot access eeprom when the interface is down\n"); 3231 return -EAGAIN; 3232 } 3233 3234 switch (state) { 3235 case ETHTOOL_ID_ACTIVE: 3236 return 1; /* cycle on/off once per second */ 3237 3238 case ETHTOOL_ID_ON: 3239 bnx2x_acquire_phy_lock(bp); 3240 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3241 LED_MODE_ON, SPEED_1000); 3242 bnx2x_release_phy_lock(bp); 3243 break; 3244 3245 case ETHTOOL_ID_OFF: 3246 bnx2x_acquire_phy_lock(bp); 3247 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3248 LED_MODE_FRONT_PANEL_OFF, 0); 3249 bnx2x_release_phy_lock(bp); 3250 break; 3251 3252 case ETHTOOL_ID_INACTIVE: 3253 bnx2x_acquire_phy_lock(bp); 3254 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3255 LED_MODE_OPER, 3256 bp->link_vars.line_speed); 3257 bnx2x_release_phy_lock(bp); 3258 } 3259 3260 return 0; 3261 } 3262 3263 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3264 { 3265 switch (info->flow_type) { 3266 case TCP_V4_FLOW: 3267 case TCP_V6_FLOW: 3268 info->data = RXH_IP_SRC | RXH_IP_DST | 3269 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3270 break; 3271 case UDP_V4_FLOW: 3272 if (bp->rss_conf_obj.udp_rss_v4) 3273 info->data = RXH_IP_SRC | RXH_IP_DST | 3274 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3275 else 3276 info->data = RXH_IP_SRC | RXH_IP_DST; 3277 break; 3278 case UDP_V6_FLOW: 3279 if (bp->rss_conf_obj.udp_rss_v6) 3280 info->data = RXH_IP_SRC | RXH_IP_DST | 3281 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3282 else 3283 info->data = RXH_IP_SRC | RXH_IP_DST; 3284 break; 3285 case IPV4_FLOW: 3286 case IPV6_FLOW: 3287 info->data = RXH_IP_SRC | RXH_IP_DST; 3288 break; 3289 default: 3290 info->data = 0; 3291 break; 3292 } 3293 3294 return 0; 3295 } 3296 3297 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3298 u32 *rules __always_unused) 3299 { 3300 struct bnx2x *bp = netdev_priv(dev); 3301 3302 switch (info->cmd) { 3303 case ETHTOOL_GRXRINGS: 3304 info->data = BNX2X_NUM_ETH_QUEUES(bp); 3305 return 0; 3306 case ETHTOOL_GRXFH: 3307 return bnx2x_get_rss_flags(bp, info); 3308 default: 3309 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3310 return -EOPNOTSUPP; 3311 } 3312 } 3313 3314 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3315 { 3316 int udp_rss_requested; 3317 3318 DP(BNX2X_MSG_ETHTOOL, 3319 "Set rss flags command parameters: flow type = %d, data = %llu\n", 3320 info->flow_type, info->data); 3321 3322 switch (info->flow_type) { 3323 case TCP_V4_FLOW: 3324 case TCP_V6_FLOW: 3325 /* For TCP only 4-tupple hash is supported */ 3326 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 3327 RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 3328 DP(BNX2X_MSG_ETHTOOL, 3329 "Command parameters not supported\n"); 3330 return -EINVAL; 3331 } 3332 return 0; 3333 3334 case UDP_V4_FLOW: 3335 case UDP_V6_FLOW: 3336 /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 3337 if (info->data == (RXH_IP_SRC | RXH_IP_DST | 3338 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3339 udp_rss_requested = 1; 3340 else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 3341 udp_rss_requested = 0; 3342 else 3343 return -EINVAL; 3344 3345 if (CHIP_IS_E1x(bp) && udp_rss_requested) { 3346 DP(BNX2X_MSG_ETHTOOL, 3347 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n"); 3348 return -EINVAL; 3349 } 3350 3351 if ((info->flow_type == UDP_V4_FLOW) && 3352 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 3353 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 3354 DP(BNX2X_MSG_ETHTOOL, 3355 "rss re-configured, UDP 4-tupple %s\n", 3356 udp_rss_requested ? "enabled" : "disabled"); 3357 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3358 } else if ((info->flow_type == UDP_V6_FLOW) && 3359 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 3360 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 3361 DP(BNX2X_MSG_ETHTOOL, 3362 "rss re-configured, UDP 4-tupple %s\n", 3363 udp_rss_requested ? "enabled" : "disabled"); 3364 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3365 } 3366 return 0; 3367 3368 case IPV4_FLOW: 3369 case IPV6_FLOW: 3370 /* For IP only 2-tupple hash is supported */ 3371 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 3372 DP(BNX2X_MSG_ETHTOOL, 3373 "Command parameters not supported\n"); 3374 return -EINVAL; 3375 } 3376 return 0; 3377 3378 case SCTP_V4_FLOW: 3379 case AH_ESP_V4_FLOW: 3380 case AH_V4_FLOW: 3381 case ESP_V4_FLOW: 3382 case SCTP_V6_FLOW: 3383 case AH_ESP_V6_FLOW: 3384 case AH_V6_FLOW: 3385 case ESP_V6_FLOW: 3386 case IP_USER_FLOW: 3387 case ETHER_FLOW: 3388 /* RSS is not supported for these protocols */ 3389 if (info->data) { 3390 DP(BNX2X_MSG_ETHTOOL, 3391 "Command parameters not supported\n"); 3392 return -EINVAL; 3393 } 3394 return 0; 3395 3396 default: 3397 return -EINVAL; 3398 } 3399 } 3400 3401 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 3402 { 3403 struct bnx2x *bp = netdev_priv(dev); 3404 3405 switch (info->cmd) { 3406 case ETHTOOL_SRXFH: 3407 return bnx2x_set_rss_flags(bp, info); 3408 default: 3409 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3410 return -EOPNOTSUPP; 3411 } 3412 } 3413 3414 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3415 { 3416 return T_ETH_INDIRECTION_TABLE_SIZE; 3417 } 3418 3419 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3420 u8 *hfunc) 3421 { 3422 struct bnx2x *bp = netdev_priv(dev); 3423 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3424 size_t i; 3425 3426 if (hfunc) 3427 *hfunc = ETH_RSS_HASH_TOP; 3428 if (!indir) 3429 return 0; 3430 3431 /* Get the current configuration of the RSS indirection table */ 3432 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3433 3434 /* 3435 * We can't use a memcpy() as an internal storage of an 3436 * indirection table is a u8 array while indir->ring_index 3437 * points to an array of u32. 3438 * 3439 * Indirection table contains the FW Client IDs, so we need to 3440 * align the returned table to the Client ID of the leading RSS 3441 * queue. 3442 */ 3443 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 3444 indir[i] = ind_table[i] - bp->fp->cl_id; 3445 3446 return 0; 3447 } 3448 3449 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3450 const u8 *key, const u8 hfunc) 3451 { 3452 struct bnx2x *bp = netdev_priv(dev); 3453 size_t i; 3454 3455 /* We require at least one supported parameter to be changed and no 3456 * change in any of the unsupported parameters 3457 */ 3458 if (key || 3459 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3460 return -EOPNOTSUPP; 3461 3462 if (!indir) 3463 return 0; 3464 3465 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3466 /* 3467 * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3468 * as an internal storage of an indirection table is a u8 array 3469 * while indir->ring_index points to an array of u32. 3470 * 3471 * Indirection table contains the FW Client IDs, so we need to 3472 * align the received table to the Client ID of the leading RSS 3473 * queue 3474 */ 3475 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3476 } 3477 3478 return bnx2x_config_rss_eth(bp, false); 3479 } 3480 3481 /** 3482 * bnx2x_get_channels - gets the number of RSS queues. 3483 * 3484 * @dev: net device 3485 * @channels: returns the number of max / current queues 3486 */ 3487 static void bnx2x_get_channels(struct net_device *dev, 3488 struct ethtool_channels *channels) 3489 { 3490 struct bnx2x *bp = netdev_priv(dev); 3491 3492 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 3493 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 3494 } 3495 3496 /** 3497 * bnx2x_change_num_queues - change the number of RSS queues. 3498 * 3499 * @bp: bnx2x private structure 3500 * 3501 * Re-configure interrupt mode to get the new number of MSI-X 3502 * vectors and re-add NAPI objects. 3503 */ 3504 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 3505 { 3506 bnx2x_disable_msi(bp); 3507 bp->num_ethernet_queues = num_rss; 3508 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 3509 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 3510 bnx2x_set_int_mode(bp); 3511 } 3512 3513 /** 3514 * bnx2x_set_channels - sets the number of RSS queues. 3515 * 3516 * @dev: net device 3517 * @channels: includes the number of queues requested 3518 */ 3519 static int bnx2x_set_channels(struct net_device *dev, 3520 struct ethtool_channels *channels) 3521 { 3522 struct bnx2x *bp = netdev_priv(dev); 3523 3524 DP(BNX2X_MSG_ETHTOOL, 3525 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 3526 channels->rx_count, channels->tx_count, channels->other_count, 3527 channels->combined_count); 3528 3529 if (pci_num_vf(bp->pdev)) { 3530 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3531 return -EPERM; 3532 } 3533 3534 /* We don't support separate rx / tx channels. 3535 * We don't allow setting 'other' channels. 3536 */ 3537 if (channels->rx_count || channels->tx_count || channels->other_count 3538 || (channels->combined_count == 0) || 3539 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 3540 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 3541 return -EINVAL; 3542 } 3543 3544 /* Check if there was a change in the active parameters */ 3545 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 3546 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 3547 return 0; 3548 } 3549 3550 /* Set the requested number of queues in bp context. 3551 * Note that the actual number of queues created during load may be 3552 * less than requested if memory is low. 3553 */ 3554 if (unlikely(!netif_running(dev))) { 3555 bnx2x_change_num_queues(bp, channels->combined_count); 3556 return 0; 3557 } 3558 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 3559 bnx2x_change_num_queues(bp, channels->combined_count); 3560 return bnx2x_nic_load(bp, LOAD_NORMAL); 3561 } 3562 3563 static int bnx2x_get_ts_info(struct net_device *dev, 3564 struct ethtool_ts_info *info) 3565 { 3566 struct bnx2x *bp = netdev_priv(dev); 3567 3568 if (bp->flags & PTP_SUPPORTED) { 3569 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3570 SOF_TIMESTAMPING_RX_SOFTWARE | 3571 SOF_TIMESTAMPING_SOFTWARE | 3572 SOF_TIMESTAMPING_TX_HARDWARE | 3573 SOF_TIMESTAMPING_RX_HARDWARE | 3574 SOF_TIMESTAMPING_RAW_HARDWARE; 3575 3576 if (bp->ptp_clock) 3577 info->phc_index = ptp_clock_index(bp->ptp_clock); 3578 else 3579 info->phc_index = -1; 3580 3581 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3582 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3583 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3584 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3585 3586 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3587 3588 return 0; 3589 } 3590 3591 return ethtool_op_get_ts_info(dev, info); 3592 } 3593 3594 static const struct ethtool_ops bnx2x_ethtool_ops = { 3595 .get_settings = bnx2x_get_settings, 3596 .set_settings = bnx2x_set_settings, 3597 .get_drvinfo = bnx2x_get_drvinfo, 3598 .get_regs_len = bnx2x_get_regs_len, 3599 .get_regs = bnx2x_get_regs, 3600 .get_dump_flag = bnx2x_get_dump_flag, 3601 .get_dump_data = bnx2x_get_dump_data, 3602 .set_dump = bnx2x_set_dump, 3603 .get_wol = bnx2x_get_wol, 3604 .set_wol = bnx2x_set_wol, 3605 .get_msglevel = bnx2x_get_msglevel, 3606 .set_msglevel = bnx2x_set_msglevel, 3607 .nway_reset = bnx2x_nway_reset, 3608 .get_link = bnx2x_get_link, 3609 .get_eeprom_len = bnx2x_get_eeprom_len, 3610 .get_eeprom = bnx2x_get_eeprom, 3611 .set_eeprom = bnx2x_set_eeprom, 3612 .get_coalesce = bnx2x_get_coalesce, 3613 .set_coalesce = bnx2x_set_coalesce, 3614 .get_ringparam = bnx2x_get_ringparam, 3615 .set_ringparam = bnx2x_set_ringparam, 3616 .get_pauseparam = bnx2x_get_pauseparam, 3617 .set_pauseparam = bnx2x_set_pauseparam, 3618 .self_test = bnx2x_self_test, 3619 .get_sset_count = bnx2x_get_sset_count, 3620 .get_priv_flags = bnx2x_get_private_flags, 3621 .get_strings = bnx2x_get_strings, 3622 .set_phys_id = bnx2x_set_phys_id, 3623 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3624 .get_rxnfc = bnx2x_get_rxnfc, 3625 .set_rxnfc = bnx2x_set_rxnfc, 3626 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3627 .get_rxfh = bnx2x_get_rxfh, 3628 .set_rxfh = bnx2x_set_rxfh, 3629 .get_channels = bnx2x_get_channels, 3630 .set_channels = bnx2x_set_channels, 3631 .get_module_info = bnx2x_get_module_info, 3632 .get_module_eeprom = bnx2x_get_module_eeprom, 3633 .get_eee = bnx2x_get_eee, 3634 .set_eee = bnx2x_set_eee, 3635 .get_ts_info = bnx2x_get_ts_info, 3636 }; 3637 3638 static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3639 .get_settings = bnx2x_get_vf_settings, 3640 .get_drvinfo = bnx2x_get_drvinfo, 3641 .get_msglevel = bnx2x_get_msglevel, 3642 .set_msglevel = bnx2x_set_msglevel, 3643 .get_link = bnx2x_get_link, 3644 .get_coalesce = bnx2x_get_coalesce, 3645 .get_ringparam = bnx2x_get_ringparam, 3646 .set_ringparam = bnx2x_set_ringparam, 3647 .get_sset_count = bnx2x_get_sset_count, 3648 .get_strings = bnx2x_get_strings, 3649 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3650 .get_rxnfc = bnx2x_get_rxnfc, 3651 .set_rxnfc = bnx2x_set_rxnfc, 3652 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3653 .get_rxfh = bnx2x_get_rxfh, 3654 .set_rxfh = bnx2x_set_rxfh, 3655 .get_channels = bnx2x_get_channels, 3656 .set_channels = bnx2x_set_channels, 3657 }; 3658 3659 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3660 { 3661 netdev->ethtool_ops = (IS_PF(bp)) ? 3662 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3663 } 3664