1 /* bnx2x_ethtool.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/ethtool.h> 23 #include <linux/netdevice.h> 24 #include <linux/types.h> 25 #include <linux/sched.h> 26 #include <linux/crc32.h> 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 #include "bnx2x_dump.h" 30 #include "bnx2x_init.h" 31 32 /* Note: in the format strings below %s is replaced by the queue-name which is 33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35 */ 36 #define MAX_QUEUE_NAME_LEN 4 37 static const struct { 38 long offset; 39 int size; 40 char string[ETH_GSTRING_LEN]; 41 } bnx2x_q_stats_arr[] = { 42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44 8, "[%s]: rx_ucast_packets" }, 45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46 8, "[%s]: rx_mcast_packets" }, 47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48 8, "[%s]: rx_bcast_packets" }, 49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50 { Q_STATS_OFFSET32(rx_err_discard_pkt), 51 4, "[%s]: rx_phy_ip_err_discards"}, 52 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53 4, "[%s]: rx_skb_alloc_discard" }, 54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 55 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" }, 56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58 8, "[%s]: tx_ucast_packets" }, 59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60 8, "[%s]: tx_mcast_packets" }, 61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62 8, "[%s]: tx_bcast_packets" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64 8, "[%s]: tpa_aggregations" }, 65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66 8, "[%s]: tpa_aggregated_frames"}, 67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69 4, "[%s]: driver_filtered_tx_pkt" } 70 }; 71 72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73 74 static const struct { 75 long offset; 76 int size; 77 u32 flags; 78 #define STATS_FLAGS_PORT 1 79 #define STATS_FLAGS_FUNC 2 80 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 81 char string[ETH_GSTRING_LEN]; 82 } bnx2x_stats_arr[] = { 83 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 84 8, STATS_FLAGS_BOTH, "rx_bytes" }, 85 { STATS_OFFSET32(error_bytes_received_hi), 86 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 87 { STATS_OFFSET32(total_unicast_packets_received_hi), 88 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 89 { STATS_OFFSET32(total_multicast_packets_received_hi), 90 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 91 { STATS_OFFSET32(total_broadcast_packets_received_hi), 92 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 93 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 94 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 95 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 96 8, STATS_FLAGS_PORT, "rx_align_errors" }, 97 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 98 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 99 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 100 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 101 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 102 8, STATS_FLAGS_PORT, "rx_fragments" }, 103 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 104 8, STATS_FLAGS_PORT, "rx_jabbers" }, 105 { STATS_OFFSET32(no_buff_discard_hi), 106 8, STATS_FLAGS_BOTH, "rx_discards" }, 107 { STATS_OFFSET32(mac_filter_discard), 108 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 109 { STATS_OFFSET32(mf_tag_discard), 110 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 111 { STATS_OFFSET32(pfc_frames_received_hi), 112 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 113 { STATS_OFFSET32(pfc_frames_sent_hi), 114 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 115 { STATS_OFFSET32(brb_drop_hi), 116 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 117 { STATS_OFFSET32(brb_truncate_hi), 118 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 119 { STATS_OFFSET32(pause_frames_received_hi), 120 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 121 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 122 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 123 { STATS_OFFSET32(nig_timer_max), 124 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 125 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 126 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 127 { STATS_OFFSET32(rx_skb_alloc_failed), 128 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 129 { STATS_OFFSET32(hw_csum_err), 130 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 131 { STATS_OFFSET32(driver_xoff), 132 4, STATS_FLAGS_BOTH, "tx_exhaustion_events" }, 133 { STATS_OFFSET32(total_bytes_transmitted_hi), 134 8, STATS_FLAGS_BOTH, "tx_bytes" }, 135 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 136 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 137 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 138 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 139 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 140 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 141 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 142 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 143 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 144 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 145 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 146 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 147 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 148 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 149 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 150 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 151 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 152 8, STATS_FLAGS_PORT, "tx_deferred" }, 153 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 154 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 155 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 156 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 157 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 158 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 159 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 160 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 161 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 162 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 163 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 164 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 165 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 166 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 167 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 168 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 169 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 170 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 171 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 172 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 173 { STATS_OFFSET32(pause_frames_sent_hi), 174 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 175 { STATS_OFFSET32(total_tpa_aggregations_hi), 176 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 177 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 178 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 179 { STATS_OFFSET32(total_tpa_bytes_hi), 180 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 181 { STATS_OFFSET32(recoverable_error), 182 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 183 { STATS_OFFSET32(unrecoverable_error), 184 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 185 { STATS_OFFSET32(driver_filtered_tx_pkt), 186 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 187 { STATS_OFFSET32(eee_tx_lpi), 188 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 189 }; 190 191 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 192 193 static int bnx2x_get_port_type(struct bnx2x *bp) 194 { 195 int port_type; 196 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 197 switch (bp->link_params.phy[phy_idx].media_type) { 198 case ETH_PHY_SFPP_10G_FIBER: 199 case ETH_PHY_SFP_1G_FIBER: 200 case ETH_PHY_XFP_FIBER: 201 case ETH_PHY_KR: 202 case ETH_PHY_CX4: 203 port_type = PORT_FIBRE; 204 break; 205 case ETH_PHY_DA_TWINAX: 206 port_type = PORT_DA; 207 break; 208 case ETH_PHY_BASE_T: 209 port_type = PORT_TP; 210 break; 211 case ETH_PHY_NOT_PRESENT: 212 port_type = PORT_NONE; 213 break; 214 case ETH_PHY_UNSPECIFIED: 215 default: 216 port_type = PORT_OTHER; 217 break; 218 } 219 return port_type; 220 } 221 222 static int bnx2x_get_vf_settings(struct net_device *dev, 223 struct ethtool_cmd *cmd) 224 { 225 struct bnx2x *bp = netdev_priv(dev); 226 227 if (bp->state == BNX2X_STATE_OPEN) { 228 if (test_bit(BNX2X_LINK_REPORT_FD, 229 &bp->vf_link_vars.link_report_flags)) 230 cmd->duplex = DUPLEX_FULL; 231 else 232 cmd->duplex = DUPLEX_HALF; 233 234 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed); 235 } else { 236 cmd->duplex = DUPLEX_UNKNOWN; 237 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 238 } 239 240 cmd->port = PORT_OTHER; 241 cmd->phy_address = 0; 242 cmd->transceiver = XCVR_INTERNAL; 243 cmd->autoneg = AUTONEG_DISABLE; 244 cmd->maxtxpkt = 0; 245 cmd->maxrxpkt = 0; 246 247 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 248 " supported 0x%x advertising 0x%x speed %u\n" 249 " duplex %d port %d phy_address %d transceiver %d\n" 250 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 251 cmd->cmd, cmd->supported, cmd->advertising, 252 ethtool_cmd_speed(cmd), 253 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 254 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 255 256 return 0; 257 } 258 259 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 260 { 261 struct bnx2x *bp = netdev_priv(dev); 262 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 263 u32 media_type; 264 265 /* Dual Media boards present all available port types */ 266 cmd->supported = bp->port.supported[cfg_idx] | 267 (bp->port.supported[cfg_idx ^ 1] & 268 (SUPPORTED_TP | SUPPORTED_FIBRE)); 269 cmd->advertising = bp->port.advertising[cfg_idx]; 270 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 271 if (media_type == ETH_PHY_SFP_1G_FIBER) { 272 cmd->supported &= ~(SUPPORTED_10000baseT_Full); 273 cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 274 } 275 276 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 277 !(bp->flags & MF_FUNC_DIS)) { 278 cmd->duplex = bp->link_vars.duplex; 279 280 if (IS_MF(bp) && !BP_NOMCP(bp)) 281 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 282 else 283 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 284 } else { 285 cmd->duplex = DUPLEX_UNKNOWN; 286 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 287 } 288 289 cmd->port = bnx2x_get_port_type(bp); 290 291 cmd->phy_address = bp->mdio.prtad; 292 cmd->transceiver = XCVR_INTERNAL; 293 294 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 295 cmd->autoneg = AUTONEG_ENABLE; 296 else 297 cmd->autoneg = AUTONEG_DISABLE; 298 299 /* Publish LP advertised speeds and FC */ 300 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 301 u32 status = bp->link_vars.link_status; 302 303 cmd->lp_advertising |= ADVERTISED_Autoneg; 304 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 305 cmd->lp_advertising |= ADVERTISED_Pause; 306 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 307 cmd->lp_advertising |= ADVERTISED_Asym_Pause; 308 309 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 310 cmd->lp_advertising |= ADVERTISED_10baseT_Half; 311 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 312 cmd->lp_advertising |= ADVERTISED_10baseT_Full; 313 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 314 cmd->lp_advertising |= ADVERTISED_100baseT_Half; 315 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 316 cmd->lp_advertising |= ADVERTISED_100baseT_Full; 317 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 318 cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 319 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 320 if (media_type == ETH_PHY_KR) { 321 cmd->lp_advertising |= 322 ADVERTISED_1000baseKX_Full; 323 } else { 324 cmd->lp_advertising |= 325 ADVERTISED_1000baseT_Full; 326 } 327 } 328 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 329 cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 330 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 331 if (media_type == ETH_PHY_KR) { 332 cmd->lp_advertising |= 333 ADVERTISED_10000baseKR_Full; 334 } else { 335 cmd->lp_advertising |= 336 ADVERTISED_10000baseT_Full; 337 } 338 } 339 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 340 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 341 } 342 343 cmd->maxtxpkt = 0; 344 cmd->maxrxpkt = 0; 345 346 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 347 " supported 0x%x advertising 0x%x speed %u\n" 348 " duplex %d port %d phy_address %d transceiver %d\n" 349 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 350 cmd->cmd, cmd->supported, cmd->advertising, 351 ethtool_cmd_speed(cmd), 352 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 353 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 354 355 return 0; 356 } 357 358 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 359 { 360 struct bnx2x *bp = netdev_priv(dev); 361 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 362 u32 speed, phy_idx; 363 364 if (IS_MF_SD(bp)) 365 return 0; 366 367 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 368 " supported 0x%x advertising 0x%x speed %u\n" 369 " duplex %d port %d phy_address %d transceiver %d\n" 370 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 371 cmd->cmd, cmd->supported, cmd->advertising, 372 ethtool_cmd_speed(cmd), 373 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 374 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 375 376 speed = ethtool_cmd_speed(cmd); 377 378 /* If received a request for an unknown duplex, assume full*/ 379 if (cmd->duplex == DUPLEX_UNKNOWN) 380 cmd->duplex = DUPLEX_FULL; 381 382 if (IS_MF_SI(bp)) { 383 u32 part; 384 u32 line_speed = bp->link_vars.line_speed; 385 386 /* use 10G if no link detected */ 387 if (!line_speed) 388 line_speed = 10000; 389 390 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 391 DP(BNX2X_MSG_ETHTOOL, 392 "To set speed BC %X or higher is required, please upgrade BC\n", 393 REQ_BC_VER_4_SET_MF_BW); 394 return -EINVAL; 395 } 396 397 part = (speed * 100) / line_speed; 398 399 if (line_speed < speed || !part) { 400 DP(BNX2X_MSG_ETHTOOL, 401 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 402 return -EINVAL; 403 } 404 405 if (bp->state != BNX2X_STATE_OPEN) 406 /* store value for following "load" */ 407 bp->pending_max = part; 408 else 409 bnx2x_update_max_mf_config(bp, part); 410 411 return 0; 412 } 413 414 cfg_idx = bnx2x_get_link_cfg_idx(bp); 415 old_multi_phy_config = bp->link_params.multi_phy_config; 416 if (cmd->port != bnx2x_get_port_type(bp)) { 417 switch (cmd->port) { 418 case PORT_TP: 419 if (!(bp->port.supported[0] & SUPPORTED_TP || 420 bp->port.supported[1] & SUPPORTED_TP)) { 421 DP(BNX2X_MSG_ETHTOOL, 422 "Unsupported port type\n"); 423 return -EINVAL; 424 } 425 bp->link_params.multi_phy_config &= 426 ~PORT_HW_CFG_PHY_SELECTION_MASK; 427 if (bp->link_params.multi_phy_config & 428 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 429 bp->link_params.multi_phy_config |= 430 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 431 else 432 bp->link_params.multi_phy_config |= 433 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 434 break; 435 case PORT_FIBRE: 436 case PORT_DA: 437 case PORT_NONE: 438 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 439 bp->port.supported[1] & SUPPORTED_FIBRE)) { 440 DP(BNX2X_MSG_ETHTOOL, 441 "Unsupported port type\n"); 442 return -EINVAL; 443 } 444 bp->link_params.multi_phy_config &= 445 ~PORT_HW_CFG_PHY_SELECTION_MASK; 446 if (bp->link_params.multi_phy_config & 447 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 448 bp->link_params.multi_phy_config |= 449 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 450 else 451 bp->link_params.multi_phy_config |= 452 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 453 break; 454 default: 455 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 456 return -EINVAL; 457 } 458 } 459 /* Save new config in case command complete successfully */ 460 new_multi_phy_config = bp->link_params.multi_phy_config; 461 /* Get the new cfg_idx */ 462 cfg_idx = bnx2x_get_link_cfg_idx(bp); 463 /* Restore old config in case command failed */ 464 bp->link_params.multi_phy_config = old_multi_phy_config; 465 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 466 467 if (cmd->autoneg == AUTONEG_ENABLE) { 468 u32 an_supported_speed = bp->port.supported[cfg_idx]; 469 if (bp->link_params.phy[EXT_PHY1].type == 470 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 471 an_supported_speed |= (SUPPORTED_100baseT_Half | 472 SUPPORTED_100baseT_Full); 473 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 474 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 475 return -EINVAL; 476 } 477 478 /* advertise the requested speed and duplex if supported */ 479 if (cmd->advertising & ~an_supported_speed) { 480 DP(BNX2X_MSG_ETHTOOL, 481 "Advertisement parameters are not supported\n"); 482 return -EINVAL; 483 } 484 485 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 486 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 487 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 488 cmd->advertising); 489 if (cmd->advertising) { 490 491 bp->link_params.speed_cap_mask[cfg_idx] = 0; 492 if (cmd->advertising & ADVERTISED_10baseT_Half) { 493 bp->link_params.speed_cap_mask[cfg_idx] |= 494 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 495 } 496 if (cmd->advertising & ADVERTISED_10baseT_Full) 497 bp->link_params.speed_cap_mask[cfg_idx] |= 498 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 499 500 if (cmd->advertising & ADVERTISED_100baseT_Full) 501 bp->link_params.speed_cap_mask[cfg_idx] |= 502 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 503 504 if (cmd->advertising & ADVERTISED_100baseT_Half) { 505 bp->link_params.speed_cap_mask[cfg_idx] |= 506 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 507 } 508 if (cmd->advertising & ADVERTISED_1000baseT_Half) { 509 bp->link_params.speed_cap_mask[cfg_idx] |= 510 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 511 } 512 if (cmd->advertising & (ADVERTISED_1000baseT_Full | 513 ADVERTISED_1000baseKX_Full)) 514 bp->link_params.speed_cap_mask[cfg_idx] |= 515 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 516 517 if (cmd->advertising & (ADVERTISED_10000baseT_Full | 518 ADVERTISED_10000baseKX4_Full | 519 ADVERTISED_10000baseKR_Full)) 520 bp->link_params.speed_cap_mask[cfg_idx] |= 521 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 522 523 if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 524 bp->link_params.speed_cap_mask[cfg_idx] |= 525 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 526 } 527 } else { /* forced speed */ 528 /* advertise the requested speed and duplex if supported */ 529 switch (speed) { 530 case SPEED_10: 531 if (cmd->duplex == DUPLEX_FULL) { 532 if (!(bp->port.supported[cfg_idx] & 533 SUPPORTED_10baseT_Full)) { 534 DP(BNX2X_MSG_ETHTOOL, 535 "10M full not supported\n"); 536 return -EINVAL; 537 } 538 539 advertising = (ADVERTISED_10baseT_Full | 540 ADVERTISED_TP); 541 } else { 542 if (!(bp->port.supported[cfg_idx] & 543 SUPPORTED_10baseT_Half)) { 544 DP(BNX2X_MSG_ETHTOOL, 545 "10M half not supported\n"); 546 return -EINVAL; 547 } 548 549 advertising = (ADVERTISED_10baseT_Half | 550 ADVERTISED_TP); 551 } 552 break; 553 554 case SPEED_100: 555 if (cmd->duplex == DUPLEX_FULL) { 556 if (!(bp->port.supported[cfg_idx] & 557 SUPPORTED_100baseT_Full)) { 558 DP(BNX2X_MSG_ETHTOOL, 559 "100M full not supported\n"); 560 return -EINVAL; 561 } 562 563 advertising = (ADVERTISED_100baseT_Full | 564 ADVERTISED_TP); 565 } else { 566 if (!(bp->port.supported[cfg_idx] & 567 SUPPORTED_100baseT_Half)) { 568 DP(BNX2X_MSG_ETHTOOL, 569 "100M half not supported\n"); 570 return -EINVAL; 571 } 572 573 advertising = (ADVERTISED_100baseT_Half | 574 ADVERTISED_TP); 575 } 576 break; 577 578 case SPEED_1000: 579 if (cmd->duplex != DUPLEX_FULL) { 580 DP(BNX2X_MSG_ETHTOOL, 581 "1G half not supported\n"); 582 return -EINVAL; 583 } 584 585 if (bp->port.supported[cfg_idx] & 586 SUPPORTED_1000baseT_Full) { 587 advertising = (ADVERTISED_1000baseT_Full | 588 ADVERTISED_TP); 589 590 } else if (bp->port.supported[cfg_idx] & 591 SUPPORTED_1000baseKX_Full) { 592 advertising = ADVERTISED_1000baseKX_Full; 593 } else { 594 DP(BNX2X_MSG_ETHTOOL, 595 "1G full not supported\n"); 596 return -EINVAL; 597 } 598 599 break; 600 601 case SPEED_2500: 602 if (cmd->duplex != DUPLEX_FULL) { 603 DP(BNX2X_MSG_ETHTOOL, 604 "2.5G half not supported\n"); 605 return -EINVAL; 606 } 607 608 if (!(bp->port.supported[cfg_idx] 609 & SUPPORTED_2500baseX_Full)) { 610 DP(BNX2X_MSG_ETHTOOL, 611 "2.5G full not supported\n"); 612 return -EINVAL; 613 } 614 615 advertising = (ADVERTISED_2500baseX_Full | 616 ADVERTISED_TP); 617 break; 618 619 case SPEED_10000: 620 if (cmd->duplex != DUPLEX_FULL) { 621 DP(BNX2X_MSG_ETHTOOL, 622 "10G half not supported\n"); 623 return -EINVAL; 624 } 625 phy_idx = bnx2x_get_cur_phy_idx(bp); 626 if ((bp->port.supported[cfg_idx] & 627 SUPPORTED_10000baseT_Full) && 628 (bp->link_params.phy[phy_idx].media_type != 629 ETH_PHY_SFP_1G_FIBER)) { 630 advertising = (ADVERTISED_10000baseT_Full | 631 ADVERTISED_FIBRE); 632 } else if (bp->port.supported[cfg_idx] & 633 SUPPORTED_10000baseKR_Full) { 634 advertising = (ADVERTISED_10000baseKR_Full | 635 ADVERTISED_FIBRE); 636 } else { 637 DP(BNX2X_MSG_ETHTOOL, 638 "10G full not supported\n"); 639 return -EINVAL; 640 } 641 642 break; 643 644 default: 645 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 646 return -EINVAL; 647 } 648 649 bp->link_params.req_line_speed[cfg_idx] = speed; 650 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 651 bp->port.advertising[cfg_idx] = advertising; 652 } 653 654 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 655 " req_duplex %d advertising 0x%x\n", 656 bp->link_params.req_line_speed[cfg_idx], 657 bp->link_params.req_duplex[cfg_idx], 658 bp->port.advertising[cfg_idx]); 659 660 /* Set new config */ 661 bp->link_params.multi_phy_config = new_multi_phy_config; 662 if (netif_running(dev)) { 663 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 664 bnx2x_force_link_reset(bp); 665 bnx2x_link_set(bp); 666 } 667 668 return 0; 669 } 670 671 #define DUMP_ALL_PRESETS 0x1FFF 672 #define DUMP_MAX_PRESETS 13 673 674 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 675 { 676 if (CHIP_IS_E1(bp)) 677 return dump_num_registers[0][preset-1]; 678 else if (CHIP_IS_E1H(bp)) 679 return dump_num_registers[1][preset-1]; 680 else if (CHIP_IS_E2(bp)) 681 return dump_num_registers[2][preset-1]; 682 else if (CHIP_IS_E3A0(bp)) 683 return dump_num_registers[3][preset-1]; 684 else if (CHIP_IS_E3B0(bp)) 685 return dump_num_registers[4][preset-1]; 686 else 687 return 0; 688 } 689 690 static int __bnx2x_get_regs_len(struct bnx2x *bp) 691 { 692 u32 preset_idx; 693 int regdump_len = 0; 694 695 /* Calculate the total preset regs length */ 696 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 697 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 698 699 return regdump_len; 700 } 701 702 static int bnx2x_get_regs_len(struct net_device *dev) 703 { 704 struct bnx2x *bp = netdev_priv(dev); 705 int regdump_len = 0; 706 707 if (IS_VF(bp)) 708 return 0; 709 710 regdump_len = __bnx2x_get_regs_len(bp); 711 regdump_len *= 4; 712 regdump_len += sizeof(struct dump_header); 713 714 return regdump_len; 715 } 716 717 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 718 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 719 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 720 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 721 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 722 723 #define IS_REG_IN_PRESET(presets, idx) \ 724 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 725 726 /******* Paged registers info selectors ********/ 727 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 728 { 729 if (CHIP_IS_E2(bp)) 730 return page_vals_e2; 731 else if (CHIP_IS_E3(bp)) 732 return page_vals_e3; 733 else 734 return NULL; 735 } 736 737 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 738 { 739 if (CHIP_IS_E2(bp)) 740 return PAGE_MODE_VALUES_E2; 741 else if (CHIP_IS_E3(bp)) 742 return PAGE_MODE_VALUES_E3; 743 else 744 return 0; 745 } 746 747 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 748 { 749 if (CHIP_IS_E2(bp)) 750 return page_write_regs_e2; 751 else if (CHIP_IS_E3(bp)) 752 return page_write_regs_e3; 753 else 754 return NULL; 755 } 756 757 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 758 { 759 if (CHIP_IS_E2(bp)) 760 return PAGE_WRITE_REGS_E2; 761 else if (CHIP_IS_E3(bp)) 762 return PAGE_WRITE_REGS_E3; 763 else 764 return 0; 765 } 766 767 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 768 { 769 if (CHIP_IS_E2(bp)) 770 return page_read_regs_e2; 771 else if (CHIP_IS_E3(bp)) 772 return page_read_regs_e3; 773 else 774 return NULL; 775 } 776 777 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 778 { 779 if (CHIP_IS_E2(bp)) 780 return PAGE_READ_REGS_E2; 781 else if (CHIP_IS_E3(bp)) 782 return PAGE_READ_REGS_E3; 783 else 784 return 0; 785 } 786 787 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 788 const struct reg_addr *reg_info) 789 { 790 if (CHIP_IS_E1(bp)) 791 return IS_E1_REG(reg_info->chips); 792 else if (CHIP_IS_E1H(bp)) 793 return IS_E1H_REG(reg_info->chips); 794 else if (CHIP_IS_E2(bp)) 795 return IS_E2_REG(reg_info->chips); 796 else if (CHIP_IS_E3A0(bp)) 797 return IS_E3A0_REG(reg_info->chips); 798 else if (CHIP_IS_E3B0(bp)) 799 return IS_E3B0_REG(reg_info->chips); 800 else 801 return false; 802 } 803 804 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 805 const struct wreg_addr *wreg_info) 806 { 807 if (CHIP_IS_E1(bp)) 808 return IS_E1_REG(wreg_info->chips); 809 else if (CHIP_IS_E1H(bp)) 810 return IS_E1H_REG(wreg_info->chips); 811 else if (CHIP_IS_E2(bp)) 812 return IS_E2_REG(wreg_info->chips); 813 else if (CHIP_IS_E3A0(bp)) 814 return IS_E3A0_REG(wreg_info->chips); 815 else if (CHIP_IS_E3B0(bp)) 816 return IS_E3B0_REG(wreg_info->chips); 817 else 818 return false; 819 } 820 821 /** 822 * bnx2x_read_pages_regs - read "paged" registers 823 * 824 * @bp device handle 825 * @p output buffer 826 * 827 * Reads "paged" memories: memories that may only be read by first writing to a 828 * specific address ("write address") and then reading from a specific address 829 * ("read address"). There may be more than one write address per "page" and 830 * more than one read address per write address. 831 */ 832 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 833 { 834 u32 i, j, k, n; 835 836 /* addresses of the paged registers */ 837 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 838 /* number of paged registers */ 839 int num_pages = __bnx2x_get_page_reg_num(bp); 840 /* write addresses */ 841 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 842 /* number of write addresses */ 843 int write_num = __bnx2x_get_page_write_num(bp); 844 /* read addresses info */ 845 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 846 /* number of read addresses */ 847 int read_num = __bnx2x_get_page_read_num(bp); 848 u32 addr, size; 849 850 for (i = 0; i < num_pages; i++) { 851 for (j = 0; j < write_num; j++) { 852 REG_WR(bp, write_addr[j], page_addr[i]); 853 854 for (k = 0; k < read_num; k++) { 855 if (IS_REG_IN_PRESET(read_addr[k].presets, 856 preset)) { 857 size = read_addr[k].size; 858 for (n = 0; n < size; n++) { 859 addr = read_addr[k].addr + n*4; 860 *p++ = REG_RD(bp, addr); 861 } 862 } 863 } 864 } 865 } 866 } 867 868 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 869 { 870 u32 i, j, addr; 871 const struct wreg_addr *wreg_addr_p = NULL; 872 873 if (CHIP_IS_E1(bp)) 874 wreg_addr_p = &wreg_addr_e1; 875 else if (CHIP_IS_E1H(bp)) 876 wreg_addr_p = &wreg_addr_e1h; 877 else if (CHIP_IS_E2(bp)) 878 wreg_addr_p = &wreg_addr_e2; 879 else if (CHIP_IS_E3A0(bp)) 880 wreg_addr_p = &wreg_addr_e3; 881 else if (CHIP_IS_E3B0(bp)) 882 wreg_addr_p = &wreg_addr_e3b0; 883 884 /* Read the idle_chk registers */ 885 for (i = 0; i < IDLE_REGS_COUNT; i++) { 886 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 887 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 888 for (j = 0; j < idle_reg_addrs[i].size; j++) 889 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 890 } 891 } 892 893 /* Read the regular registers */ 894 for (i = 0; i < REGS_COUNT; i++) { 895 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 896 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 897 for (j = 0; j < reg_addrs[i].size; j++) 898 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 899 } 900 } 901 902 /* Read the CAM registers */ 903 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 904 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 905 for (i = 0; i < wreg_addr_p->size; i++) { 906 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 907 908 /* In case of wreg_addr register, read additional 909 registers from read_regs array 910 */ 911 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 912 addr = *(wreg_addr_p->read_regs); 913 *p++ = REG_RD(bp, addr + j*4); 914 } 915 } 916 } 917 918 /* Paged registers are supported in E2 & E3 only */ 919 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 920 /* Read "paged" registers */ 921 bnx2x_read_pages_regs(bp, p, preset); 922 } 923 924 return 0; 925 } 926 927 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 928 { 929 u32 preset_idx; 930 931 /* Read all registers, by reading all preset registers */ 932 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 933 /* Skip presets with IOR */ 934 if ((preset_idx == 2) || 935 (preset_idx == 5) || 936 (preset_idx == 8) || 937 (preset_idx == 11)) 938 continue; 939 __bnx2x_get_preset_regs(bp, p, preset_idx); 940 p += __bnx2x_get_preset_regs_len(bp, preset_idx); 941 } 942 } 943 944 static void bnx2x_get_regs(struct net_device *dev, 945 struct ethtool_regs *regs, void *_p) 946 { 947 u32 *p = _p; 948 struct bnx2x *bp = netdev_priv(dev); 949 struct dump_header dump_hdr = {0}; 950 951 regs->version = 2; 952 memset(p, 0, regs->len); 953 954 if (!netif_running(bp->dev)) 955 return; 956 957 /* Disable parity attentions as long as following dump may 958 * cause false alarms by reading never written registers. We 959 * will re-enable parity attentions right after the dump. 960 */ 961 962 bnx2x_disable_blocks_parity(bp); 963 964 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 965 dump_hdr.preset = DUMP_ALL_PRESETS; 966 dump_hdr.version = BNX2X_DUMP_VERSION; 967 968 /* dump_meta_data presents OR of CHIP and PATH. */ 969 if (CHIP_IS_E1(bp)) { 970 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 971 } else if (CHIP_IS_E1H(bp)) { 972 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 973 } else if (CHIP_IS_E2(bp)) { 974 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 975 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 976 } else if (CHIP_IS_E3A0(bp)) { 977 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 978 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 979 } else if (CHIP_IS_E3B0(bp)) { 980 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 981 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 982 } 983 984 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 985 p += dump_hdr.header_size + 1; 986 987 /* Actually read the registers */ 988 __bnx2x_get_regs(bp, p); 989 990 /* Re-enable parity attentions */ 991 bnx2x_clear_blocks_parity(bp); 992 bnx2x_enable_blocks_parity(bp); 993 } 994 995 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 996 { 997 struct bnx2x *bp = netdev_priv(dev); 998 int regdump_len = 0; 999 1000 regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 1001 regdump_len *= 4; 1002 regdump_len += sizeof(struct dump_header); 1003 1004 return regdump_len; 1005 } 1006 1007 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 1008 { 1009 struct bnx2x *bp = netdev_priv(dev); 1010 1011 /* Use the ethtool_dump "flag" field as the dump preset index */ 1012 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 1013 return -EINVAL; 1014 1015 bp->dump_preset_idx = val->flag; 1016 return 0; 1017 } 1018 1019 static int bnx2x_get_dump_flag(struct net_device *dev, 1020 struct ethtool_dump *dump) 1021 { 1022 struct bnx2x *bp = netdev_priv(dev); 1023 1024 dump->version = BNX2X_DUMP_VERSION; 1025 dump->flag = bp->dump_preset_idx; 1026 /* Calculate the requested preset idx length */ 1027 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 1028 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 1029 bp->dump_preset_idx, dump->len); 1030 return 0; 1031 } 1032 1033 static int bnx2x_get_dump_data(struct net_device *dev, 1034 struct ethtool_dump *dump, 1035 void *buffer) 1036 { 1037 u32 *p = buffer; 1038 struct bnx2x *bp = netdev_priv(dev); 1039 struct dump_header dump_hdr = {0}; 1040 1041 /* Disable parity attentions as long as following dump may 1042 * cause false alarms by reading never written registers. We 1043 * will re-enable parity attentions right after the dump. 1044 */ 1045 1046 bnx2x_disable_blocks_parity(bp); 1047 1048 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 1049 dump_hdr.preset = bp->dump_preset_idx; 1050 dump_hdr.version = BNX2X_DUMP_VERSION; 1051 1052 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 1053 1054 /* dump_meta_data presents OR of CHIP and PATH. */ 1055 if (CHIP_IS_E1(bp)) { 1056 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 1057 } else if (CHIP_IS_E1H(bp)) { 1058 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 1059 } else if (CHIP_IS_E2(bp)) { 1060 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 1061 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1062 } else if (CHIP_IS_E3A0(bp)) { 1063 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 1064 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1065 } else if (CHIP_IS_E3B0(bp)) { 1066 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 1067 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1068 } 1069 1070 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1071 p += dump_hdr.header_size + 1; 1072 1073 /* Actually read the registers */ 1074 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1075 1076 /* Re-enable parity attentions */ 1077 bnx2x_clear_blocks_parity(bp); 1078 bnx2x_enable_blocks_parity(bp); 1079 1080 return 0; 1081 } 1082 1083 static void bnx2x_get_drvinfo(struct net_device *dev, 1084 struct ethtool_drvinfo *info) 1085 { 1086 struct bnx2x *bp = netdev_priv(dev); 1087 1088 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1089 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1090 1091 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 1092 1093 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1094 } 1095 1096 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1097 { 1098 struct bnx2x *bp = netdev_priv(dev); 1099 1100 if (bp->flags & NO_WOL_FLAG) { 1101 wol->supported = 0; 1102 wol->wolopts = 0; 1103 } else { 1104 wol->supported = WAKE_MAGIC; 1105 if (bp->wol) 1106 wol->wolopts = WAKE_MAGIC; 1107 else 1108 wol->wolopts = 0; 1109 } 1110 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1111 } 1112 1113 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1114 { 1115 struct bnx2x *bp = netdev_priv(dev); 1116 1117 if (wol->wolopts & ~WAKE_MAGIC) { 1118 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1119 return -EINVAL; 1120 } 1121 1122 if (wol->wolopts & WAKE_MAGIC) { 1123 if (bp->flags & NO_WOL_FLAG) { 1124 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1125 return -EINVAL; 1126 } 1127 bp->wol = 1; 1128 } else 1129 bp->wol = 0; 1130 1131 if (SHMEM2_HAS(bp, curr_cfg)) 1132 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1133 1134 return 0; 1135 } 1136 1137 static u32 bnx2x_get_msglevel(struct net_device *dev) 1138 { 1139 struct bnx2x *bp = netdev_priv(dev); 1140 1141 return bp->msg_enable; 1142 } 1143 1144 static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1145 { 1146 struct bnx2x *bp = netdev_priv(dev); 1147 1148 if (capable(CAP_NET_ADMIN)) { 1149 /* dump MCP trace */ 1150 if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1151 bnx2x_fw_dump_lvl(bp, KERN_INFO); 1152 bp->msg_enable = level; 1153 } 1154 } 1155 1156 static int bnx2x_nway_reset(struct net_device *dev) 1157 { 1158 struct bnx2x *bp = netdev_priv(dev); 1159 1160 if (!bp->port.pmf) 1161 return 0; 1162 1163 if (netif_running(dev)) { 1164 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1165 bnx2x_force_link_reset(bp); 1166 bnx2x_link_set(bp); 1167 } 1168 1169 return 0; 1170 } 1171 1172 static u32 bnx2x_get_link(struct net_device *dev) 1173 { 1174 struct bnx2x *bp = netdev_priv(dev); 1175 1176 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1177 return 0; 1178 1179 if (IS_VF(bp)) 1180 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1181 &bp->vf_link_vars.link_report_flags); 1182 1183 return bp->link_vars.link_up; 1184 } 1185 1186 static int bnx2x_get_eeprom_len(struct net_device *dev) 1187 { 1188 struct bnx2x *bp = netdev_priv(dev); 1189 1190 return bp->common.flash_size; 1191 } 1192 1193 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1194 * had we done things the other way around, if two pfs from the same port would 1195 * attempt to access nvram at the same time, we could run into a scenario such 1196 * as: 1197 * pf A takes the port lock. 1198 * pf B succeeds in taking the same lock since they are from the same port. 1199 * pf A takes the per pf misc lock. Performs eeprom access. 1200 * pf A finishes. Unlocks the per pf misc lock. 1201 * Pf B takes the lock and proceeds to perform it's own access. 1202 * pf A unlocks the per port lock, while pf B is still working (!). 1203 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1204 * access corrupted by pf B) 1205 */ 1206 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1207 { 1208 int port = BP_PORT(bp); 1209 int count, i; 1210 u32 val; 1211 1212 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1213 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1214 1215 /* adjust timeout for emulation/FPGA */ 1216 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1217 if (CHIP_REV_IS_SLOW(bp)) 1218 count *= 100; 1219 1220 /* request access to nvram interface */ 1221 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1222 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1223 1224 for (i = 0; i < count*10; i++) { 1225 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1226 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1227 break; 1228 1229 udelay(5); 1230 } 1231 1232 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1233 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1234 "cannot get access to nvram interface\n"); 1235 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1236 return -EBUSY; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1243 { 1244 int port = BP_PORT(bp); 1245 int count, i; 1246 u32 val; 1247 1248 /* adjust timeout for emulation/FPGA */ 1249 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1250 if (CHIP_REV_IS_SLOW(bp)) 1251 count *= 100; 1252 1253 /* relinquish nvram interface */ 1254 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1255 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1256 1257 for (i = 0; i < count*10; i++) { 1258 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1259 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1260 break; 1261 1262 udelay(5); 1263 } 1264 1265 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1266 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1267 "cannot free access to nvram interface\n"); 1268 return -EBUSY; 1269 } 1270 1271 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1272 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1273 return 0; 1274 } 1275 1276 static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1277 { 1278 u32 val; 1279 1280 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1281 1282 /* enable both bits, even on read */ 1283 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1284 (val | MCPR_NVM_ACCESS_ENABLE_EN | 1285 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1286 } 1287 1288 static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1289 { 1290 u32 val; 1291 1292 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1293 1294 /* disable both bits, even after read */ 1295 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1296 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1297 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1298 } 1299 1300 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1301 u32 cmd_flags) 1302 { 1303 int count, i, rc; 1304 u32 val; 1305 1306 /* build the command word */ 1307 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1308 1309 /* need to clear DONE bit separately */ 1310 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1311 1312 /* address of the NVRAM to read from */ 1313 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1314 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1315 1316 /* issue a read command */ 1317 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1318 1319 /* adjust timeout for emulation/FPGA */ 1320 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1321 if (CHIP_REV_IS_SLOW(bp)) 1322 count *= 100; 1323 1324 /* wait for completion */ 1325 *ret_val = 0; 1326 rc = -EBUSY; 1327 for (i = 0; i < count; i++) { 1328 udelay(5); 1329 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1330 1331 if (val & MCPR_NVM_COMMAND_DONE) { 1332 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1333 /* we read nvram data in cpu order 1334 * but ethtool sees it as an array of bytes 1335 * converting to big-endian will do the work 1336 */ 1337 *ret_val = cpu_to_be32(val); 1338 rc = 0; 1339 break; 1340 } 1341 } 1342 if (rc == -EBUSY) 1343 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1344 "nvram read timeout expired\n"); 1345 return rc; 1346 } 1347 1348 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1349 int buf_size) 1350 { 1351 int rc; 1352 u32 cmd_flags; 1353 __be32 val; 1354 1355 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1356 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1357 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1358 offset, buf_size); 1359 return -EINVAL; 1360 } 1361 1362 if (offset + buf_size > bp->common.flash_size) { 1363 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1364 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1365 offset, buf_size, bp->common.flash_size); 1366 return -EINVAL; 1367 } 1368 1369 /* request access to nvram interface */ 1370 rc = bnx2x_acquire_nvram_lock(bp); 1371 if (rc) 1372 return rc; 1373 1374 /* enable access to nvram interface */ 1375 bnx2x_enable_nvram_access(bp); 1376 1377 /* read the first word(s) */ 1378 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1379 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1380 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1381 memcpy(ret_buf, &val, 4); 1382 1383 /* advance to the next dword */ 1384 offset += sizeof(u32); 1385 ret_buf += sizeof(u32); 1386 buf_size -= sizeof(u32); 1387 cmd_flags = 0; 1388 } 1389 1390 if (rc == 0) { 1391 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1392 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1393 memcpy(ret_buf, &val, 4); 1394 } 1395 1396 /* disable access to nvram interface */ 1397 bnx2x_disable_nvram_access(bp); 1398 bnx2x_release_nvram_lock(bp); 1399 1400 return rc; 1401 } 1402 1403 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 1404 int buf_size) 1405 { 1406 int rc; 1407 1408 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 1409 1410 if (!rc) { 1411 __be32 *be = (__be32 *)buf; 1412 1413 while ((buf_size -= 4) >= 0) 1414 *buf++ = be32_to_cpu(*be++); 1415 } 1416 1417 return rc; 1418 } 1419 1420 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 1421 { 1422 int rc = 1; 1423 u16 pm = 0; 1424 struct net_device *dev = pci_get_drvdata(bp->pdev); 1425 1426 if (bp->pdev->pm_cap) 1427 rc = pci_read_config_word(bp->pdev, 1428 bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 1429 1430 if ((rc && !netif_running(dev)) || 1431 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 1432 return false; 1433 1434 return true; 1435 } 1436 1437 static int bnx2x_get_eeprom(struct net_device *dev, 1438 struct ethtool_eeprom *eeprom, u8 *eebuf) 1439 { 1440 struct bnx2x *bp = netdev_priv(dev); 1441 1442 if (!bnx2x_is_nvm_accessible(bp)) { 1443 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1444 "cannot access eeprom when the interface is down\n"); 1445 return -EAGAIN; 1446 } 1447 1448 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1449 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1450 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1451 eeprom->len, eeprom->len); 1452 1453 /* parameters already validated in ethtool_get_eeprom */ 1454 1455 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1456 } 1457 1458 static int bnx2x_get_module_eeprom(struct net_device *dev, 1459 struct ethtool_eeprom *ee, 1460 u8 *data) 1461 { 1462 struct bnx2x *bp = netdev_priv(dev); 1463 int rc = -EINVAL, phy_idx; 1464 u8 *user_data = data; 1465 unsigned int start_addr = ee->offset, xfer_size = 0; 1466 1467 if (!bnx2x_is_nvm_accessible(bp)) { 1468 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1469 "cannot access eeprom when the interface is down\n"); 1470 return -EAGAIN; 1471 } 1472 1473 phy_idx = bnx2x_get_cur_phy_idx(bp); 1474 1475 /* Read A0 section */ 1476 if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1477 /* Limit transfer size to the A0 section boundary */ 1478 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1479 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1480 else 1481 xfer_size = ee->len; 1482 bnx2x_acquire_phy_lock(bp); 1483 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1484 &bp->link_params, 1485 I2C_DEV_ADDR_A0, 1486 start_addr, 1487 xfer_size, 1488 user_data); 1489 bnx2x_release_phy_lock(bp); 1490 if (rc) { 1491 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1492 1493 return -EINVAL; 1494 } 1495 user_data += xfer_size; 1496 start_addr += xfer_size; 1497 } 1498 1499 /* Read A2 section */ 1500 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1501 (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1502 xfer_size = ee->len - xfer_size; 1503 /* Limit transfer size to the A2 section boundary */ 1504 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1505 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1506 start_addr -= ETH_MODULE_SFF_8079_LEN; 1507 bnx2x_acquire_phy_lock(bp); 1508 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1509 &bp->link_params, 1510 I2C_DEV_ADDR_A2, 1511 start_addr, 1512 xfer_size, 1513 user_data); 1514 bnx2x_release_phy_lock(bp); 1515 if (rc) { 1516 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1517 return -EINVAL; 1518 } 1519 } 1520 return rc; 1521 } 1522 1523 static int bnx2x_get_module_info(struct net_device *dev, 1524 struct ethtool_modinfo *modinfo) 1525 { 1526 struct bnx2x *bp = netdev_priv(dev); 1527 int phy_idx, rc; 1528 u8 sff8472_comp, diag_type; 1529 1530 if (!bnx2x_is_nvm_accessible(bp)) { 1531 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1532 "cannot access eeprom when the interface is down\n"); 1533 return -EAGAIN; 1534 } 1535 phy_idx = bnx2x_get_cur_phy_idx(bp); 1536 bnx2x_acquire_phy_lock(bp); 1537 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1538 &bp->link_params, 1539 I2C_DEV_ADDR_A0, 1540 SFP_EEPROM_SFF_8472_COMP_ADDR, 1541 SFP_EEPROM_SFF_8472_COMP_SIZE, 1542 &sff8472_comp); 1543 bnx2x_release_phy_lock(bp); 1544 if (rc) { 1545 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1546 return -EINVAL; 1547 } 1548 1549 bnx2x_acquire_phy_lock(bp); 1550 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1551 &bp->link_params, 1552 I2C_DEV_ADDR_A0, 1553 SFP_EEPROM_DIAG_TYPE_ADDR, 1554 SFP_EEPROM_DIAG_TYPE_SIZE, 1555 &diag_type); 1556 bnx2x_release_phy_lock(bp); 1557 if (rc) { 1558 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1559 return -EINVAL; 1560 } 1561 1562 if (!sff8472_comp || 1563 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 1564 modinfo->type = ETH_MODULE_SFF_8079; 1565 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1566 } else { 1567 modinfo->type = ETH_MODULE_SFF_8472; 1568 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1569 } 1570 return 0; 1571 } 1572 1573 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1574 u32 cmd_flags) 1575 { 1576 int count, i, rc; 1577 1578 /* build the command word */ 1579 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1580 1581 /* need to clear DONE bit separately */ 1582 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1583 1584 /* write the data */ 1585 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1586 1587 /* address of the NVRAM to write to */ 1588 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1589 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1590 1591 /* issue the write command */ 1592 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1593 1594 /* adjust timeout for emulation/FPGA */ 1595 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1596 if (CHIP_REV_IS_SLOW(bp)) 1597 count *= 100; 1598 1599 /* wait for completion */ 1600 rc = -EBUSY; 1601 for (i = 0; i < count; i++) { 1602 udelay(5); 1603 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1604 if (val & MCPR_NVM_COMMAND_DONE) { 1605 rc = 0; 1606 break; 1607 } 1608 } 1609 1610 if (rc == -EBUSY) 1611 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1612 "nvram write timeout expired\n"); 1613 return rc; 1614 } 1615 1616 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1617 1618 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1619 int buf_size) 1620 { 1621 int rc; 1622 u32 cmd_flags, align_offset, val; 1623 __be32 val_be; 1624 1625 if (offset + buf_size > bp->common.flash_size) { 1626 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1627 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1628 offset, buf_size, bp->common.flash_size); 1629 return -EINVAL; 1630 } 1631 1632 /* request access to nvram interface */ 1633 rc = bnx2x_acquire_nvram_lock(bp); 1634 if (rc) 1635 return rc; 1636 1637 /* enable access to nvram interface */ 1638 bnx2x_enable_nvram_access(bp); 1639 1640 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1641 align_offset = (offset & ~0x03); 1642 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1643 1644 if (rc == 0) { 1645 /* nvram data is returned as an array of bytes 1646 * convert it back to cpu order 1647 */ 1648 val = be32_to_cpu(val_be); 1649 1650 val &= ~le32_to_cpu((__force __le32) 1651 (0xff << BYTE_OFFSET(offset))); 1652 val |= le32_to_cpu((__force __le32) 1653 (*data_buf << BYTE_OFFSET(offset))); 1654 1655 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1656 cmd_flags); 1657 } 1658 1659 /* disable access to nvram interface */ 1660 bnx2x_disable_nvram_access(bp); 1661 bnx2x_release_nvram_lock(bp); 1662 1663 return rc; 1664 } 1665 1666 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1667 int buf_size) 1668 { 1669 int rc; 1670 u32 cmd_flags; 1671 u32 val; 1672 u32 written_so_far; 1673 1674 if (buf_size == 1) /* ethtool */ 1675 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1676 1677 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1678 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1679 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1680 offset, buf_size); 1681 return -EINVAL; 1682 } 1683 1684 if (offset + buf_size > bp->common.flash_size) { 1685 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1686 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1687 offset, buf_size, bp->common.flash_size); 1688 return -EINVAL; 1689 } 1690 1691 /* request access to nvram interface */ 1692 rc = bnx2x_acquire_nvram_lock(bp); 1693 if (rc) 1694 return rc; 1695 1696 /* enable access to nvram interface */ 1697 bnx2x_enable_nvram_access(bp); 1698 1699 written_so_far = 0; 1700 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1701 while ((written_so_far < buf_size) && (rc == 0)) { 1702 if (written_so_far == (buf_size - sizeof(u32))) 1703 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1704 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1705 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1706 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1707 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1708 1709 memcpy(&val, data_buf, 4); 1710 1711 /* Notice unlike bnx2x_nvram_read_dword() this will not 1712 * change val using be32_to_cpu(), which causes data to flip 1713 * if the eeprom is read and then written back. This is due 1714 * to tools utilizing this functionality that would break 1715 * if this would be resolved. 1716 */ 1717 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1718 1719 /* advance to the next dword */ 1720 offset += sizeof(u32); 1721 data_buf += sizeof(u32); 1722 written_so_far += sizeof(u32); 1723 1724 /* At end of each 4Kb page, release nvram lock to allow MFW 1725 * chance to take it for its own use. 1726 */ 1727 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) && 1728 (written_so_far < buf_size)) { 1729 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1730 "Releasing NVM lock after offset 0x%x\n", 1731 (u32)(offset - sizeof(u32))); 1732 bnx2x_release_nvram_lock(bp); 1733 usleep_range(1000, 2000); 1734 rc = bnx2x_acquire_nvram_lock(bp); 1735 if (rc) 1736 return rc; 1737 } 1738 1739 cmd_flags = 0; 1740 } 1741 1742 /* disable access to nvram interface */ 1743 bnx2x_disable_nvram_access(bp); 1744 bnx2x_release_nvram_lock(bp); 1745 1746 return rc; 1747 } 1748 1749 static int bnx2x_set_eeprom(struct net_device *dev, 1750 struct ethtool_eeprom *eeprom, u8 *eebuf) 1751 { 1752 struct bnx2x *bp = netdev_priv(dev); 1753 int port = BP_PORT(bp); 1754 int rc = 0; 1755 u32 ext_phy_config; 1756 1757 if (!bnx2x_is_nvm_accessible(bp)) { 1758 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1759 "cannot access eeprom when the interface is down\n"); 1760 return -EAGAIN; 1761 } 1762 1763 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1764 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1765 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1766 eeprom->len, eeprom->len); 1767 1768 /* parameters already validated in ethtool_set_eeprom */ 1769 1770 /* PHY eeprom can be accessed only by the PMF */ 1771 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1772 !bp->port.pmf) { 1773 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1774 "wrong magic or interface is not pmf\n"); 1775 return -EINVAL; 1776 } 1777 1778 ext_phy_config = 1779 SHMEM_RD(bp, 1780 dev_info.port_hw_config[port].external_phy_config); 1781 1782 if (eeprom->magic == 0x50485950) { 1783 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1784 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1785 1786 bnx2x_acquire_phy_lock(bp); 1787 rc |= bnx2x_link_reset(&bp->link_params, 1788 &bp->link_vars, 0); 1789 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1790 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1791 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1792 MISC_REGISTERS_GPIO_HIGH, port); 1793 bnx2x_release_phy_lock(bp); 1794 bnx2x_link_report(bp); 1795 1796 } else if (eeprom->magic == 0x50485952) { 1797 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1798 if (bp->state == BNX2X_STATE_OPEN) { 1799 bnx2x_acquire_phy_lock(bp); 1800 rc |= bnx2x_link_reset(&bp->link_params, 1801 &bp->link_vars, 1); 1802 1803 rc |= bnx2x_phy_init(&bp->link_params, 1804 &bp->link_vars); 1805 bnx2x_release_phy_lock(bp); 1806 bnx2x_calc_fc_adv(bp); 1807 } 1808 } else if (eeprom->magic == 0x53985943) { 1809 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1810 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1811 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1812 1813 /* DSP Remove Download Mode */ 1814 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1815 MISC_REGISTERS_GPIO_LOW, port); 1816 1817 bnx2x_acquire_phy_lock(bp); 1818 1819 bnx2x_sfx7101_sp_sw_reset(bp, 1820 &bp->link_params.phy[EXT_PHY1]); 1821 1822 /* wait 0.5 sec to allow it to run */ 1823 msleep(500); 1824 bnx2x_ext_phy_hw_reset(bp, port); 1825 msleep(500); 1826 bnx2x_release_phy_lock(bp); 1827 } 1828 } else 1829 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1830 1831 return rc; 1832 } 1833 1834 static int bnx2x_get_coalesce(struct net_device *dev, 1835 struct ethtool_coalesce *coal) 1836 { 1837 struct bnx2x *bp = netdev_priv(dev); 1838 1839 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1840 1841 coal->rx_coalesce_usecs = bp->rx_ticks; 1842 coal->tx_coalesce_usecs = bp->tx_ticks; 1843 1844 return 0; 1845 } 1846 1847 static int bnx2x_set_coalesce(struct net_device *dev, 1848 struct ethtool_coalesce *coal) 1849 { 1850 struct bnx2x *bp = netdev_priv(dev); 1851 1852 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1853 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1854 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1855 1856 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1857 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1858 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1859 1860 if (netif_running(dev)) 1861 bnx2x_update_coalesce(bp); 1862 1863 return 0; 1864 } 1865 1866 static void bnx2x_get_ringparam(struct net_device *dev, 1867 struct ethtool_ringparam *ering) 1868 { 1869 struct bnx2x *bp = netdev_priv(dev); 1870 1871 ering->rx_max_pending = MAX_RX_AVAIL; 1872 1873 if (bp->rx_ring_size) 1874 ering->rx_pending = bp->rx_ring_size; 1875 else 1876 ering->rx_pending = MAX_RX_AVAIL; 1877 1878 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1879 ering->tx_pending = bp->tx_ring_size; 1880 } 1881 1882 static int bnx2x_set_ringparam(struct net_device *dev, 1883 struct ethtool_ringparam *ering) 1884 { 1885 struct bnx2x *bp = netdev_priv(dev); 1886 1887 DP(BNX2X_MSG_ETHTOOL, 1888 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 1889 ering->rx_pending, ering->tx_pending); 1890 1891 if (pci_num_vf(bp->pdev)) { 1892 DP(BNX2X_MSG_IOV, 1893 "VFs are enabled, can not change ring parameters\n"); 1894 return -EPERM; 1895 } 1896 1897 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1898 DP(BNX2X_MSG_ETHTOOL, 1899 "Handling parity error recovery. Try again later\n"); 1900 return -EAGAIN; 1901 } 1902 1903 if ((ering->rx_pending > MAX_RX_AVAIL) || 1904 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1905 MIN_RX_SIZE_TPA)) || 1906 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 1907 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 1908 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1909 return -EINVAL; 1910 } 1911 1912 bp->rx_ring_size = ering->rx_pending; 1913 bp->tx_ring_size = ering->tx_pending; 1914 1915 return bnx2x_reload_if_running(dev); 1916 } 1917 1918 static void bnx2x_get_pauseparam(struct net_device *dev, 1919 struct ethtool_pauseparam *epause) 1920 { 1921 struct bnx2x *bp = netdev_priv(dev); 1922 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1923 int cfg_reg; 1924 1925 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1926 BNX2X_FLOW_CTRL_AUTO); 1927 1928 if (!epause->autoneg) 1929 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1930 else 1931 cfg_reg = bp->link_params.req_fc_auto_adv; 1932 1933 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1934 BNX2X_FLOW_CTRL_RX); 1935 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1936 BNX2X_FLOW_CTRL_TX); 1937 1938 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1939 " autoneg %d rx_pause %d tx_pause %d\n", 1940 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1941 } 1942 1943 static int bnx2x_set_pauseparam(struct net_device *dev, 1944 struct ethtool_pauseparam *epause) 1945 { 1946 struct bnx2x *bp = netdev_priv(dev); 1947 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1948 if (IS_MF(bp)) 1949 return 0; 1950 1951 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1952 " autoneg %d rx_pause %d tx_pause %d\n", 1953 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1954 1955 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1956 1957 if (epause->rx_pause) 1958 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1959 1960 if (epause->tx_pause) 1961 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1962 1963 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1964 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1965 1966 if (epause->autoneg) { 1967 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1968 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1969 return -EINVAL; 1970 } 1971 1972 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1973 bp->link_params.req_flow_ctrl[cfg_idx] = 1974 BNX2X_FLOW_CTRL_AUTO; 1975 } 1976 bp->link_params.req_fc_auto_adv = 0; 1977 if (epause->rx_pause) 1978 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 1979 1980 if (epause->tx_pause) 1981 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1982 1983 if (!bp->link_params.req_fc_auto_adv) 1984 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1985 } 1986 1987 DP(BNX2X_MSG_ETHTOOL, 1988 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1989 1990 if (netif_running(dev)) { 1991 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1992 bnx2x_force_link_reset(bp); 1993 bnx2x_link_set(bp); 1994 } 1995 1996 return 0; 1997 } 1998 1999 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 2000 "register_test (offline) ", 2001 "memory_test (offline) ", 2002 "int_loopback_test (offline)", 2003 "ext_loopback_test (offline)", 2004 "nvram_test (online) ", 2005 "interrupt_test (online) ", 2006 "link_test (online) " 2007 }; 2008 2009 enum { 2010 BNX2X_PRI_FLAG_ISCSI, 2011 BNX2X_PRI_FLAG_FCOE, 2012 BNX2X_PRI_FLAG_STORAGE, 2013 BNX2X_PRI_FLAG_LEN, 2014 }; 2015 2016 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 2017 "iSCSI offload support", 2018 "FCoE offload support", 2019 "Storage only interface" 2020 }; 2021 2022 static u32 bnx2x_eee_to_adv(u32 eee_adv) 2023 { 2024 u32 modes = 0; 2025 2026 if (eee_adv & SHMEM_EEE_100M_ADV) 2027 modes |= ADVERTISED_100baseT_Full; 2028 if (eee_adv & SHMEM_EEE_1G_ADV) 2029 modes |= ADVERTISED_1000baseT_Full; 2030 if (eee_adv & SHMEM_EEE_10G_ADV) 2031 modes |= ADVERTISED_10000baseT_Full; 2032 2033 return modes; 2034 } 2035 2036 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2037 { 2038 u32 eee_adv = 0; 2039 if (modes & ADVERTISED_100baseT_Full) 2040 eee_adv |= SHMEM_EEE_100M_ADV; 2041 if (modes & ADVERTISED_1000baseT_Full) 2042 eee_adv |= SHMEM_EEE_1G_ADV; 2043 if (modes & ADVERTISED_10000baseT_Full) 2044 eee_adv |= SHMEM_EEE_10G_ADV; 2045 2046 return eee_adv << shift; 2047 } 2048 2049 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2050 { 2051 struct bnx2x *bp = netdev_priv(dev); 2052 u32 eee_cfg; 2053 2054 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2055 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2056 return -EOPNOTSUPP; 2057 } 2058 2059 eee_cfg = bp->link_vars.eee_status; 2060 2061 edata->supported = 2062 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2063 SHMEM_EEE_SUPPORTED_SHIFT); 2064 2065 edata->advertised = 2066 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2067 SHMEM_EEE_ADV_STATUS_SHIFT); 2068 edata->lp_advertised = 2069 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2070 SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2071 2072 /* SHMEM value is in 16u units --> Convert to 1u units. */ 2073 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2074 2075 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2076 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2077 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2078 2079 return 0; 2080 } 2081 2082 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2083 { 2084 struct bnx2x *bp = netdev_priv(dev); 2085 u32 eee_cfg; 2086 u32 advertised; 2087 2088 if (IS_MF(bp)) 2089 return 0; 2090 2091 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2092 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2093 return -EOPNOTSUPP; 2094 } 2095 2096 eee_cfg = bp->link_vars.eee_status; 2097 2098 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2099 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2100 return -EOPNOTSUPP; 2101 } 2102 2103 advertised = bnx2x_adv_to_eee(edata->advertised, 2104 SHMEM_EEE_ADV_STATUS_SHIFT); 2105 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2106 DP(BNX2X_MSG_ETHTOOL, 2107 "Direct manipulation of EEE advertisement is not supported\n"); 2108 return -EINVAL; 2109 } 2110 2111 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2112 DP(BNX2X_MSG_ETHTOOL, 2113 "Maximal Tx Lpi timer supported is %x(u)\n", 2114 EEE_MODE_TIMER_MASK); 2115 return -EINVAL; 2116 } 2117 if (edata->tx_lpi_enabled && 2118 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2119 DP(BNX2X_MSG_ETHTOOL, 2120 "Minimal Tx Lpi timer supported is %d(u)\n", 2121 EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2122 return -EINVAL; 2123 } 2124 2125 /* All is well; Apply changes*/ 2126 if (edata->eee_enabled) 2127 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2128 else 2129 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2130 2131 if (edata->tx_lpi_enabled) 2132 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2133 else 2134 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2135 2136 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2137 bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2138 EEE_MODE_TIMER_MASK) | 2139 EEE_MODE_OVERRIDE_NVRAM | 2140 EEE_MODE_OUTPUT_TIME; 2141 2142 /* Restart link to propagate changes */ 2143 if (netif_running(dev)) { 2144 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2145 bnx2x_force_link_reset(bp); 2146 bnx2x_link_set(bp); 2147 } 2148 2149 return 0; 2150 } 2151 2152 enum { 2153 BNX2X_CHIP_E1_OFST = 0, 2154 BNX2X_CHIP_E1H_OFST, 2155 BNX2X_CHIP_E2_OFST, 2156 BNX2X_CHIP_E3_OFST, 2157 BNX2X_CHIP_E3B0_OFST, 2158 BNX2X_CHIP_MAX_OFST 2159 }; 2160 2161 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2162 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2163 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2164 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2165 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2166 2167 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2168 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2169 2170 static int bnx2x_test_registers(struct bnx2x *bp) 2171 { 2172 int idx, i, rc = -ENODEV; 2173 u32 wr_val = 0, hw; 2174 int port = BP_PORT(bp); 2175 static const struct { 2176 u32 hw; 2177 u32 offset0; 2178 u32 offset1; 2179 u32 mask; 2180 } reg_tbl[] = { 2181 /* 0 */ { BNX2X_CHIP_MASK_ALL, 2182 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2183 { BNX2X_CHIP_MASK_ALL, 2184 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2185 { BNX2X_CHIP_MASK_E1X, 2186 HC_REG_AGG_INT_0, 4, 0x000003ff }, 2187 { BNX2X_CHIP_MASK_ALL, 2188 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2189 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2190 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2191 { BNX2X_CHIP_MASK_E3B0, 2192 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2193 { BNX2X_CHIP_MASK_ALL, 2194 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2195 { BNX2X_CHIP_MASK_ALL, 2196 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2197 { BNX2X_CHIP_MASK_ALL, 2198 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2199 { BNX2X_CHIP_MASK_ALL, 2200 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2201 /* 10 */ { BNX2X_CHIP_MASK_ALL, 2202 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2203 { BNX2X_CHIP_MASK_ALL, 2204 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2205 { BNX2X_CHIP_MASK_ALL, 2206 QM_REG_CONNNUM_0, 4, 0x000fffff }, 2207 { BNX2X_CHIP_MASK_ALL, 2208 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2209 { BNX2X_CHIP_MASK_ALL, 2210 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2211 { BNX2X_CHIP_MASK_ALL, 2212 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2213 { BNX2X_CHIP_MASK_ALL, 2214 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2215 { BNX2X_CHIP_MASK_ALL, 2216 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2217 { BNX2X_CHIP_MASK_ALL, 2218 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2219 { BNX2X_CHIP_MASK_ALL, 2220 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2221 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2222 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2223 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2224 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2225 { BNX2X_CHIP_MASK_ALL, 2226 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2227 { BNX2X_CHIP_MASK_ALL, 2228 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2229 { BNX2X_CHIP_MASK_ALL, 2230 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2231 { BNX2X_CHIP_MASK_ALL, 2232 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2233 { BNX2X_CHIP_MASK_ALL, 2234 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2235 { BNX2X_CHIP_MASK_ALL, 2236 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2237 { BNX2X_CHIP_MASK_ALL, 2238 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2239 { BNX2X_CHIP_MASK_ALL, 2240 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2241 /* 30 */ { BNX2X_CHIP_MASK_ALL, 2242 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2243 { BNX2X_CHIP_MASK_ALL, 2244 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2245 { BNX2X_CHIP_MASK_ALL, 2246 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2247 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2248 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2249 { BNX2X_CHIP_MASK_ALL, 2250 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2251 { BNX2X_CHIP_MASK_ALL, 2252 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2253 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2254 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2255 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2256 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2257 2258 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2259 }; 2260 2261 if (!bnx2x_is_nvm_accessible(bp)) { 2262 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2263 "cannot access eeprom when the interface is down\n"); 2264 return rc; 2265 } 2266 2267 if (CHIP_IS_E1(bp)) 2268 hw = BNX2X_CHIP_MASK_E1; 2269 else if (CHIP_IS_E1H(bp)) 2270 hw = BNX2X_CHIP_MASK_E1H; 2271 else if (CHIP_IS_E2(bp)) 2272 hw = BNX2X_CHIP_MASK_E2; 2273 else if (CHIP_IS_E3B0(bp)) 2274 hw = BNX2X_CHIP_MASK_E3B0; 2275 else /* e3 A0 */ 2276 hw = BNX2X_CHIP_MASK_E3; 2277 2278 /* Repeat the test twice: 2279 * First by writing 0x00000000, second by writing 0xffffffff 2280 */ 2281 for (idx = 0; idx < 2; idx++) { 2282 2283 switch (idx) { 2284 case 0: 2285 wr_val = 0; 2286 break; 2287 case 1: 2288 wr_val = 0xffffffff; 2289 break; 2290 } 2291 2292 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2293 u32 offset, mask, save_val, val; 2294 if (!(hw & reg_tbl[i].hw)) 2295 continue; 2296 2297 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2298 mask = reg_tbl[i].mask; 2299 2300 save_val = REG_RD(bp, offset); 2301 2302 REG_WR(bp, offset, wr_val & mask); 2303 2304 val = REG_RD(bp, offset); 2305 2306 /* Restore the original register's value */ 2307 REG_WR(bp, offset, save_val); 2308 2309 /* verify value is as expected */ 2310 if ((val & mask) != (wr_val & mask)) { 2311 DP(BNX2X_MSG_ETHTOOL, 2312 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2313 offset, val, wr_val, mask); 2314 goto test_reg_exit; 2315 } 2316 } 2317 } 2318 2319 rc = 0; 2320 2321 test_reg_exit: 2322 return rc; 2323 } 2324 2325 static int bnx2x_test_memory(struct bnx2x *bp) 2326 { 2327 int i, j, rc = -ENODEV; 2328 u32 val, index; 2329 static const struct { 2330 u32 offset; 2331 int size; 2332 } mem_tbl[] = { 2333 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2334 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2335 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2336 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2337 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2338 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2339 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2340 2341 { 0xffffffff, 0 } 2342 }; 2343 2344 static const struct { 2345 char *name; 2346 u32 offset; 2347 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2348 } prty_tbl[] = { 2349 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2350 {0x3ffc0, 0, 0, 0} }, 2351 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2352 {0x2, 0x2, 0, 0} }, 2353 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2354 {0, 0, 0, 0} }, 2355 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2356 {0x3ffc0, 0, 0, 0} }, 2357 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2358 {0x3ffc0, 0, 0, 0} }, 2359 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2360 {0x3ffc1, 0, 0, 0} }, 2361 2362 { NULL, 0xffffffff, {0, 0, 0, 0} } 2363 }; 2364 2365 if (!bnx2x_is_nvm_accessible(bp)) { 2366 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2367 "cannot access eeprom when the interface is down\n"); 2368 return rc; 2369 } 2370 2371 if (CHIP_IS_E1(bp)) 2372 index = BNX2X_CHIP_E1_OFST; 2373 else if (CHIP_IS_E1H(bp)) 2374 index = BNX2X_CHIP_E1H_OFST; 2375 else if (CHIP_IS_E2(bp)) 2376 index = BNX2X_CHIP_E2_OFST; 2377 else /* e3 */ 2378 index = BNX2X_CHIP_E3_OFST; 2379 2380 /* pre-Check the parity status */ 2381 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2382 val = REG_RD(bp, prty_tbl[i].offset); 2383 if (val & ~(prty_tbl[i].hw_mask[index])) { 2384 DP(BNX2X_MSG_ETHTOOL, 2385 "%s is 0x%x\n", prty_tbl[i].name, val); 2386 goto test_mem_exit; 2387 } 2388 } 2389 2390 /* Go through all the memories */ 2391 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2392 for (j = 0; j < mem_tbl[i].size; j++) 2393 REG_RD(bp, mem_tbl[i].offset + j*4); 2394 2395 /* Check the parity status */ 2396 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2397 val = REG_RD(bp, prty_tbl[i].offset); 2398 if (val & ~(prty_tbl[i].hw_mask[index])) { 2399 DP(BNX2X_MSG_ETHTOOL, 2400 "%s is 0x%x\n", prty_tbl[i].name, val); 2401 goto test_mem_exit; 2402 } 2403 } 2404 2405 rc = 0; 2406 2407 test_mem_exit: 2408 return rc; 2409 } 2410 2411 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2412 { 2413 int cnt = 1400; 2414 2415 if (link_up) { 2416 while (bnx2x_link_test(bp, is_serdes) && cnt--) 2417 msleep(20); 2418 2419 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 2420 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 2421 2422 cnt = 1400; 2423 while (!bp->link_vars.link_up && cnt--) 2424 msleep(20); 2425 2426 if (cnt <= 0 && !bp->link_vars.link_up) 2427 DP(BNX2X_MSG_ETHTOOL, 2428 "Timeout waiting for link init\n"); 2429 } 2430 } 2431 2432 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2433 { 2434 unsigned int pkt_size, num_pkts, i; 2435 struct sk_buff *skb; 2436 unsigned char *packet; 2437 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2438 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 2439 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2440 u16 tx_start_idx, tx_idx; 2441 u16 rx_start_idx, rx_idx; 2442 u16 pkt_prod, bd_prod; 2443 struct sw_tx_bd *tx_buf; 2444 struct eth_tx_start_bd *tx_start_bd; 2445 dma_addr_t mapping; 2446 union eth_rx_cqe *cqe; 2447 u8 cqe_fp_flags, cqe_fp_type; 2448 struct sw_rx_bd *rx_buf; 2449 u16 len; 2450 int rc = -ENODEV; 2451 u8 *data; 2452 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 2453 txdata->txq_index); 2454 2455 /* check the loopback mode */ 2456 switch (loopback_mode) { 2457 case BNX2X_PHY_LOOPBACK: 2458 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 2459 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2460 return -EINVAL; 2461 } 2462 break; 2463 case BNX2X_MAC_LOOPBACK: 2464 if (CHIP_IS_E3(bp)) { 2465 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2466 if (bp->port.supported[cfg_idx] & 2467 (SUPPORTED_10000baseT_Full | 2468 SUPPORTED_20000baseMLD2_Full | 2469 SUPPORTED_20000baseKR2_Full)) 2470 bp->link_params.loopback_mode = LOOPBACK_XMAC; 2471 else 2472 bp->link_params.loopback_mode = LOOPBACK_UMAC; 2473 } else 2474 bp->link_params.loopback_mode = LOOPBACK_BMAC; 2475 2476 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2477 break; 2478 case BNX2X_EXT_LOOPBACK: 2479 if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 2480 DP(BNX2X_MSG_ETHTOOL, 2481 "Can't configure external loopback\n"); 2482 return -EINVAL; 2483 } 2484 break; 2485 default: 2486 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2487 return -EINVAL; 2488 } 2489 2490 /* prepare the loopback packet */ 2491 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2492 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2493 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2494 if (!skb) { 2495 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2496 rc = -ENOMEM; 2497 goto test_loopback_exit; 2498 } 2499 packet = skb_put(skb, pkt_size); 2500 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2501 eth_zero_addr(packet + ETH_ALEN); 2502 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2503 for (i = ETH_HLEN; i < pkt_size; i++) 2504 packet[i] = (unsigned char) (i & 0xff); 2505 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2506 skb_headlen(skb), DMA_TO_DEVICE); 2507 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2508 rc = -ENOMEM; 2509 dev_kfree_skb(skb); 2510 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2511 goto test_loopback_exit; 2512 } 2513 2514 /* send the loopback packet */ 2515 num_pkts = 0; 2516 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2517 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2518 2519 netdev_tx_sent_queue(txq, skb->len); 2520 2521 pkt_prod = txdata->tx_pkt_prod++; 2522 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2523 tx_buf->first_bd = txdata->tx_bd_prod; 2524 tx_buf->skb = skb; 2525 tx_buf->flags = 0; 2526 2527 bd_prod = TX_BD(txdata->tx_bd_prod); 2528 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2529 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2530 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2531 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2532 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2533 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2534 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2535 SET_FLAG(tx_start_bd->general_data, 2536 ETH_TX_START_BD_HDR_NBDS, 2537 1); 2538 SET_FLAG(tx_start_bd->general_data, 2539 ETH_TX_START_BD_PARSE_NBDS, 2540 0); 2541 2542 /* turn on parsing and get a BD */ 2543 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2544 2545 if (CHIP_IS_E1x(bp)) { 2546 u16 global_data = 0; 2547 struct eth_tx_parse_bd_e1x *pbd_e1x = 2548 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2549 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2550 SET_FLAG(global_data, 2551 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2552 pbd_e1x->global_data = cpu_to_le16(global_data); 2553 } else { 2554 u32 parsing_data = 0; 2555 struct eth_tx_parse_bd_e2 *pbd_e2 = 2556 &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2557 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2558 SET_FLAG(parsing_data, 2559 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2560 pbd_e2->parsing_data = cpu_to_le32(parsing_data); 2561 } 2562 wmb(); 2563 2564 txdata->tx_db.data.prod += 2; 2565 barrier(); 2566 DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2567 2568 mmiowb(); 2569 barrier(); 2570 2571 num_pkts++; 2572 txdata->tx_bd_prod += 2; /* start + pbd */ 2573 2574 udelay(100); 2575 2576 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2577 if (tx_idx != tx_start_idx + num_pkts) 2578 goto test_loopback_exit; 2579 2580 /* Unlike HC IGU won't generate an interrupt for status block 2581 * updates that have been performed while interrupts were 2582 * disabled. 2583 */ 2584 if (bp->common.int_block == INT_BLOCK_IGU) { 2585 /* Disable local BHes to prevent a dead-lock situation between 2586 * sch_direct_xmit() and bnx2x_run_loopback() (calling 2587 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2588 */ 2589 local_bh_disable(); 2590 bnx2x_tx_int(bp, txdata); 2591 local_bh_enable(); 2592 } 2593 2594 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2595 if (rx_idx != rx_start_idx + num_pkts) 2596 goto test_loopback_exit; 2597 2598 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2599 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2600 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2601 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2602 goto test_loopback_rx_exit; 2603 2604 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2605 if (len != pkt_size) 2606 goto test_loopback_rx_exit; 2607 2608 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2609 dma_sync_single_for_cpu(&bp->pdev->dev, 2610 dma_unmap_addr(rx_buf, mapping), 2611 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2612 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2613 for (i = ETH_HLEN; i < pkt_size; i++) 2614 if (*(data + i) != (unsigned char) (i & 0xff)) 2615 goto test_loopback_rx_exit; 2616 2617 rc = 0; 2618 2619 test_loopback_rx_exit: 2620 2621 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2622 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2623 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2624 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2625 2626 /* Update producers */ 2627 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2628 fp_rx->rx_sge_prod); 2629 2630 test_loopback_exit: 2631 bp->link_params.loopback_mode = LOOPBACK_NONE; 2632 2633 return rc; 2634 } 2635 2636 static int bnx2x_test_loopback(struct bnx2x *bp) 2637 { 2638 int rc = 0, res; 2639 2640 if (BP_NOMCP(bp)) 2641 return rc; 2642 2643 if (!netif_running(bp->dev)) 2644 return BNX2X_LOOPBACK_FAILED; 2645 2646 bnx2x_netif_stop(bp, 1); 2647 bnx2x_acquire_phy_lock(bp); 2648 2649 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2650 if (res) { 2651 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2652 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2653 } 2654 2655 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2656 if (res) { 2657 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2658 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2659 } 2660 2661 bnx2x_release_phy_lock(bp); 2662 bnx2x_netif_start(bp); 2663 2664 return rc; 2665 } 2666 2667 static int bnx2x_test_ext_loopback(struct bnx2x *bp) 2668 { 2669 int rc; 2670 u8 is_serdes = 2671 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2672 2673 if (BP_NOMCP(bp)) 2674 return -ENODEV; 2675 2676 if (!netif_running(bp->dev)) 2677 return BNX2X_EXT_LOOPBACK_FAILED; 2678 2679 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2680 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 2681 if (rc) { 2682 DP(BNX2X_MSG_ETHTOOL, 2683 "Can't perform self-test, nic_load (for external lb) failed\n"); 2684 return -ENODEV; 2685 } 2686 bnx2x_wait_for_link(bp, 1, is_serdes); 2687 2688 bnx2x_netif_stop(bp, 1); 2689 2690 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 2691 if (rc) 2692 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 2693 2694 bnx2x_netif_start(bp); 2695 2696 return rc; 2697 } 2698 2699 struct code_entry { 2700 u32 sram_start_addr; 2701 u32 code_attribute; 2702 #define CODE_IMAGE_TYPE_MASK 0xf0800003 2703 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2704 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2705 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2706 u32 nvm_start_addr; 2707 }; 2708 2709 #define CODE_ENTRY_MAX 16 2710 #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2711 #define MAX_IMAGES_IN_EXTENDED_DIR 64 2712 #define NVRAM_DIR_OFFSET 0x14 2713 2714 #define EXTENDED_DIR_EXISTS(code) \ 2715 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2716 (code & CODE_IMAGE_LENGTH_MASK) != 0) 2717 2718 #define CRC32_RESIDUAL 0xdebb20e3 2719 #define CRC_BUFF_SIZE 256 2720 2721 static int bnx2x_nvram_crc(struct bnx2x *bp, 2722 int offset, 2723 int size, 2724 u8 *buff) 2725 { 2726 u32 crc = ~0; 2727 int rc = 0, done = 0; 2728 2729 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2730 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2731 2732 while (done < size) { 2733 int count = min_t(int, size - done, CRC_BUFF_SIZE); 2734 2735 rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2736 2737 if (rc) 2738 return rc; 2739 2740 crc = crc32_le(crc, buff, count); 2741 done += count; 2742 } 2743 2744 if (crc != CRC32_RESIDUAL) 2745 rc = -EINVAL; 2746 2747 return rc; 2748 } 2749 2750 static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2751 struct code_entry *entry, 2752 u8 *buff) 2753 { 2754 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2755 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2756 int rc; 2757 2758 /* Zero-length images and AFEX profiles do not have CRC */ 2759 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2760 return 0; 2761 2762 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2763 if (rc) 2764 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2765 "image %x has failed crc test (rc %d)\n", type, rc); 2766 2767 return rc; 2768 } 2769 2770 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2771 { 2772 int rc; 2773 struct code_entry entry; 2774 2775 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2776 if (rc) 2777 return rc; 2778 2779 return bnx2x_test_nvram_dir(bp, &entry, buff); 2780 } 2781 2782 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2783 { 2784 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2785 struct code_entry entry; 2786 int i; 2787 2788 rc = bnx2x_nvram_read32(bp, 2789 dir_offset + 2790 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2791 (u32 *)&entry, sizeof(entry)); 2792 if (rc) 2793 return rc; 2794 2795 if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2796 return 0; 2797 2798 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2799 &cnt, sizeof(u32)); 2800 if (rc) 2801 return rc; 2802 2803 dir_offset = entry.nvm_start_addr + 8; 2804 2805 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2806 rc = bnx2x_test_dir_entry(bp, dir_offset + 2807 sizeof(struct code_entry) * i, 2808 buff); 2809 if (rc) 2810 return rc; 2811 } 2812 2813 return 0; 2814 } 2815 2816 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2817 { 2818 u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2819 int i; 2820 2821 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2822 2823 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2824 rc = bnx2x_test_dir_entry(bp, dir_offset + 2825 sizeof(struct code_entry) * i, 2826 buff); 2827 if (rc) 2828 return rc; 2829 } 2830 2831 return bnx2x_test_nvram_ext_dirs(bp, buff); 2832 } 2833 2834 struct crc_pair { 2835 int offset; 2836 int size; 2837 }; 2838 2839 static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2840 const struct crc_pair *nvram_tbl, u8 *buf) 2841 { 2842 int i; 2843 2844 for (i = 0; nvram_tbl[i].size; i++) { 2845 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2846 nvram_tbl[i].size, buf); 2847 if (rc) { 2848 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2849 "nvram_tbl[%d] has failed crc test (rc %d)\n", 2850 i, rc); 2851 return rc; 2852 } 2853 } 2854 2855 return 0; 2856 } 2857 2858 static int bnx2x_test_nvram(struct bnx2x *bp) 2859 { 2860 const struct crc_pair nvram_tbl[] = { 2861 { 0, 0x14 }, /* bootstrap */ 2862 { 0x14, 0xec }, /* dir */ 2863 { 0x100, 0x350 }, /* manuf_info */ 2864 { 0x450, 0xf0 }, /* feature_info */ 2865 { 0x640, 0x64 }, /* upgrade_key_info */ 2866 { 0x708, 0x70 }, /* manuf_key_info */ 2867 { 0, 0 } 2868 }; 2869 const struct crc_pair nvram_tbl2[] = { 2870 { 0x7e8, 0x350 }, /* manuf_info2 */ 2871 { 0xb38, 0xf0 }, /* feature_info */ 2872 { 0, 0 } 2873 }; 2874 2875 u8 *buf; 2876 int rc; 2877 u32 magic; 2878 2879 if (BP_NOMCP(bp)) 2880 return 0; 2881 2882 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2883 if (!buf) { 2884 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2885 rc = -ENOMEM; 2886 goto test_nvram_exit; 2887 } 2888 2889 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2890 if (rc) { 2891 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2892 "magic value read (rc %d)\n", rc); 2893 goto test_nvram_exit; 2894 } 2895 2896 if (magic != 0x669955aa) { 2897 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2898 "wrong magic value (0x%08x)\n", magic); 2899 rc = -ENODEV; 2900 goto test_nvram_exit; 2901 } 2902 2903 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2904 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2905 if (rc) 2906 goto test_nvram_exit; 2907 2908 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2909 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2910 SHARED_HW_CFG_HIDE_PORT1; 2911 2912 if (!hide) { 2913 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2914 "Port 1 CRC test-set\n"); 2915 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2916 if (rc) 2917 goto test_nvram_exit; 2918 } 2919 } 2920 2921 rc = bnx2x_test_nvram_dirs(bp, buf); 2922 2923 test_nvram_exit: 2924 kfree(buf); 2925 return rc; 2926 } 2927 2928 /* Send an EMPTY ramrod on the first queue */ 2929 static int bnx2x_test_intr(struct bnx2x *bp) 2930 { 2931 struct bnx2x_queue_state_params params = {NULL}; 2932 2933 if (!netif_running(bp->dev)) { 2934 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2935 "cannot access eeprom when the interface is down\n"); 2936 return -ENODEV; 2937 } 2938 2939 params.q_obj = &bp->sp_objs->q_obj; 2940 params.cmd = BNX2X_Q_CMD_EMPTY; 2941 2942 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2943 2944 return bnx2x_queue_state_change(bp, ¶ms); 2945 } 2946 2947 static void bnx2x_self_test(struct net_device *dev, 2948 struct ethtool_test *etest, u64 *buf) 2949 { 2950 struct bnx2x *bp = netdev_priv(dev); 2951 u8 is_serdes, link_up; 2952 int rc, cnt = 0; 2953 2954 if (pci_num_vf(bp->pdev)) { 2955 DP(BNX2X_MSG_IOV, 2956 "VFs are enabled, can not perform self test\n"); 2957 return; 2958 } 2959 2960 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2961 netdev_err(bp->dev, 2962 "Handling parity error recovery. Try again later\n"); 2963 etest->flags |= ETH_TEST_FL_FAILED; 2964 return; 2965 } 2966 2967 DP(BNX2X_MSG_ETHTOOL, 2968 "Self-test command parameters: offline = %d, external_lb = %d\n", 2969 (etest->flags & ETH_TEST_FL_OFFLINE), 2970 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2971 2972 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2973 2974 if (bnx2x_test_nvram(bp) != 0) { 2975 if (!IS_MF(bp)) 2976 buf[4] = 1; 2977 else 2978 buf[0] = 1; 2979 etest->flags |= ETH_TEST_FL_FAILED; 2980 } 2981 2982 if (!netif_running(dev)) { 2983 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2984 return; 2985 } 2986 2987 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2988 link_up = bp->link_vars.link_up; 2989 /* offline tests are not supported in MF mode */ 2990 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2991 int port = BP_PORT(bp); 2992 u32 val; 2993 2994 /* save current value of input enable for TX port IF */ 2995 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2996 /* disable input for TX port IF */ 2997 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2998 2999 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3000 rc = bnx2x_nic_load(bp, LOAD_DIAG); 3001 if (rc) { 3002 etest->flags |= ETH_TEST_FL_FAILED; 3003 DP(BNX2X_MSG_ETHTOOL, 3004 "Can't perform self-test, nic_load (for offline) failed\n"); 3005 return; 3006 } 3007 3008 /* wait until link state is restored */ 3009 bnx2x_wait_for_link(bp, 1, is_serdes); 3010 3011 if (bnx2x_test_registers(bp) != 0) { 3012 buf[0] = 1; 3013 etest->flags |= ETH_TEST_FL_FAILED; 3014 } 3015 if (bnx2x_test_memory(bp) != 0) { 3016 buf[1] = 1; 3017 etest->flags |= ETH_TEST_FL_FAILED; 3018 } 3019 3020 buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3021 if (buf[2] != 0) 3022 etest->flags |= ETH_TEST_FL_FAILED; 3023 3024 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 3025 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 3026 if (buf[3] != 0) 3027 etest->flags |= ETH_TEST_FL_FAILED; 3028 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3029 } 3030 3031 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3032 3033 /* restore input for TX port IF */ 3034 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3035 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3036 if (rc) { 3037 etest->flags |= ETH_TEST_FL_FAILED; 3038 DP(BNX2X_MSG_ETHTOOL, 3039 "Can't perform self-test, nic_load (for online) failed\n"); 3040 return; 3041 } 3042 /* wait until link state is restored */ 3043 bnx2x_wait_for_link(bp, link_up, is_serdes); 3044 } 3045 3046 if (bnx2x_test_intr(bp) != 0) { 3047 if (!IS_MF(bp)) 3048 buf[5] = 1; 3049 else 3050 buf[1] = 1; 3051 etest->flags |= ETH_TEST_FL_FAILED; 3052 } 3053 3054 if (link_up) { 3055 cnt = 100; 3056 while (bnx2x_link_test(bp, is_serdes) && --cnt) 3057 msleep(20); 3058 } 3059 3060 if (!cnt) { 3061 if (!IS_MF(bp)) 3062 buf[6] = 1; 3063 else 3064 buf[2] = 1; 3065 etest->flags |= ETH_TEST_FL_FAILED; 3066 } 3067 } 3068 3069 #define IS_PORT_STAT(i) \ 3070 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 3071 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 3072 #define HIDE_PORT_STAT(bp) IS_VF(bp) 3073 3074 /* ethtool statistics are displayed for all regular ethernet queues and the 3075 * fcoe L2 queue if not disabled 3076 */ 3077 static int bnx2x_num_stat_queues(struct bnx2x *bp) 3078 { 3079 return BNX2X_NUM_ETH_QUEUES(bp); 3080 } 3081 3082 static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3083 { 3084 struct bnx2x *bp = netdev_priv(dev); 3085 int i, num_strings = 0; 3086 3087 switch (stringset) { 3088 case ETH_SS_STATS: 3089 if (is_multi(bp)) { 3090 num_strings = bnx2x_num_stat_queues(bp) * 3091 BNX2X_NUM_Q_STATS; 3092 } else 3093 num_strings = 0; 3094 if (HIDE_PORT_STAT(bp)) { 3095 for (i = 0; i < BNX2X_NUM_STATS; i++) 3096 if (IS_FUNC_STAT(i)) 3097 num_strings++; 3098 } else 3099 num_strings += BNX2X_NUM_STATS; 3100 3101 return num_strings; 3102 3103 case ETH_SS_TEST: 3104 return BNX2X_NUM_TESTS(bp); 3105 3106 case ETH_SS_PRIV_FLAGS: 3107 return BNX2X_PRI_FLAG_LEN; 3108 3109 default: 3110 return -EINVAL; 3111 } 3112 } 3113 3114 static u32 bnx2x_get_private_flags(struct net_device *dev) 3115 { 3116 struct bnx2x *bp = netdev_priv(dev); 3117 u32 flags = 0; 3118 3119 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 3120 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 3121 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 3122 3123 return flags; 3124 } 3125 3126 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3127 { 3128 struct bnx2x *bp = netdev_priv(dev); 3129 int i, j, k, start; 3130 char queue_name[MAX_QUEUE_NAME_LEN+1]; 3131 3132 switch (stringset) { 3133 case ETH_SS_STATS: 3134 k = 0; 3135 if (is_multi(bp)) { 3136 for_each_eth_queue(bp, i) { 3137 memset(queue_name, 0, sizeof(queue_name)); 3138 sprintf(queue_name, "%d", i); 3139 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3140 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3141 ETH_GSTRING_LEN, 3142 bnx2x_q_stats_arr[j].string, 3143 queue_name); 3144 k += BNX2X_NUM_Q_STATS; 3145 } 3146 } 3147 3148 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3149 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3150 continue; 3151 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3152 bnx2x_stats_arr[i].string); 3153 j++; 3154 } 3155 3156 break; 3157 3158 case ETH_SS_TEST: 3159 /* First 4 tests cannot be done in MF mode */ 3160 if (!IS_MF(bp)) 3161 start = 0; 3162 else 3163 start = 4; 3164 memcpy(buf, bnx2x_tests_str_arr + start, 3165 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 3166 break; 3167 3168 case ETH_SS_PRIV_FLAGS: 3169 memcpy(buf, bnx2x_private_arr, 3170 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 3171 break; 3172 } 3173 } 3174 3175 static void bnx2x_get_ethtool_stats(struct net_device *dev, 3176 struct ethtool_stats *stats, u64 *buf) 3177 { 3178 struct bnx2x *bp = netdev_priv(dev); 3179 u32 *hw_stats, *offset; 3180 int i, j, k = 0; 3181 3182 if (is_multi(bp)) { 3183 for_each_eth_queue(bp, i) { 3184 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3185 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3186 if (bnx2x_q_stats_arr[j].size == 0) { 3187 /* skip this counter */ 3188 buf[k + j] = 0; 3189 continue; 3190 } 3191 offset = (hw_stats + 3192 bnx2x_q_stats_arr[j].offset); 3193 if (bnx2x_q_stats_arr[j].size == 4) { 3194 /* 4-byte counter */ 3195 buf[k + j] = (u64) *offset; 3196 continue; 3197 } 3198 /* 8-byte counter */ 3199 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3200 } 3201 k += BNX2X_NUM_Q_STATS; 3202 } 3203 } 3204 3205 hw_stats = (u32 *)&bp->eth_stats; 3206 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3207 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3208 continue; 3209 if (bnx2x_stats_arr[i].size == 0) { 3210 /* skip this counter */ 3211 buf[k + j] = 0; 3212 j++; 3213 continue; 3214 } 3215 offset = (hw_stats + bnx2x_stats_arr[i].offset); 3216 if (bnx2x_stats_arr[i].size == 4) { 3217 /* 4-byte counter */ 3218 buf[k + j] = (u64) *offset; 3219 j++; 3220 continue; 3221 } 3222 /* 8-byte counter */ 3223 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3224 j++; 3225 } 3226 } 3227 3228 static int bnx2x_set_phys_id(struct net_device *dev, 3229 enum ethtool_phys_id_state state) 3230 { 3231 struct bnx2x *bp = netdev_priv(dev); 3232 3233 if (!bnx2x_is_nvm_accessible(bp)) { 3234 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 3235 "cannot access eeprom when the interface is down\n"); 3236 return -EAGAIN; 3237 } 3238 3239 switch (state) { 3240 case ETHTOOL_ID_ACTIVE: 3241 return 1; /* cycle on/off once per second */ 3242 3243 case ETHTOOL_ID_ON: 3244 bnx2x_acquire_phy_lock(bp); 3245 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3246 LED_MODE_ON, SPEED_1000); 3247 bnx2x_release_phy_lock(bp); 3248 break; 3249 3250 case ETHTOOL_ID_OFF: 3251 bnx2x_acquire_phy_lock(bp); 3252 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3253 LED_MODE_FRONT_PANEL_OFF, 0); 3254 bnx2x_release_phy_lock(bp); 3255 break; 3256 3257 case ETHTOOL_ID_INACTIVE: 3258 bnx2x_acquire_phy_lock(bp); 3259 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3260 LED_MODE_OPER, 3261 bp->link_vars.line_speed); 3262 bnx2x_release_phy_lock(bp); 3263 } 3264 3265 return 0; 3266 } 3267 3268 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3269 { 3270 switch (info->flow_type) { 3271 case TCP_V4_FLOW: 3272 case TCP_V6_FLOW: 3273 info->data = RXH_IP_SRC | RXH_IP_DST | 3274 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3275 break; 3276 case UDP_V4_FLOW: 3277 if (bp->rss_conf_obj.udp_rss_v4) 3278 info->data = RXH_IP_SRC | RXH_IP_DST | 3279 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3280 else 3281 info->data = RXH_IP_SRC | RXH_IP_DST; 3282 break; 3283 case UDP_V6_FLOW: 3284 if (bp->rss_conf_obj.udp_rss_v6) 3285 info->data = RXH_IP_SRC | RXH_IP_DST | 3286 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3287 else 3288 info->data = RXH_IP_SRC | RXH_IP_DST; 3289 break; 3290 case IPV4_FLOW: 3291 case IPV6_FLOW: 3292 info->data = RXH_IP_SRC | RXH_IP_DST; 3293 break; 3294 default: 3295 info->data = 0; 3296 break; 3297 } 3298 3299 return 0; 3300 } 3301 3302 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3303 u32 *rules __always_unused) 3304 { 3305 struct bnx2x *bp = netdev_priv(dev); 3306 3307 switch (info->cmd) { 3308 case ETHTOOL_GRXRINGS: 3309 info->data = BNX2X_NUM_ETH_QUEUES(bp); 3310 return 0; 3311 case ETHTOOL_GRXFH: 3312 return bnx2x_get_rss_flags(bp, info); 3313 default: 3314 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3315 return -EOPNOTSUPP; 3316 } 3317 } 3318 3319 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3320 { 3321 int udp_rss_requested; 3322 3323 DP(BNX2X_MSG_ETHTOOL, 3324 "Set rss flags command parameters: flow type = %d, data = %llu\n", 3325 info->flow_type, info->data); 3326 3327 switch (info->flow_type) { 3328 case TCP_V4_FLOW: 3329 case TCP_V6_FLOW: 3330 /* For TCP only 4-tupple hash is supported */ 3331 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 3332 RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 3333 DP(BNX2X_MSG_ETHTOOL, 3334 "Command parameters not supported\n"); 3335 return -EINVAL; 3336 } 3337 return 0; 3338 3339 case UDP_V4_FLOW: 3340 case UDP_V6_FLOW: 3341 /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 3342 if (info->data == (RXH_IP_SRC | RXH_IP_DST | 3343 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3344 udp_rss_requested = 1; 3345 else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 3346 udp_rss_requested = 0; 3347 else 3348 return -EINVAL; 3349 3350 if (CHIP_IS_E1x(bp) && udp_rss_requested) { 3351 DP(BNX2X_MSG_ETHTOOL, 3352 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n"); 3353 return -EINVAL; 3354 } 3355 3356 if ((info->flow_type == UDP_V4_FLOW) && 3357 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 3358 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 3359 DP(BNX2X_MSG_ETHTOOL, 3360 "rss re-configured, UDP 4-tupple %s\n", 3361 udp_rss_requested ? "enabled" : "disabled"); 3362 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3363 } else if ((info->flow_type == UDP_V6_FLOW) && 3364 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 3365 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 3366 DP(BNX2X_MSG_ETHTOOL, 3367 "rss re-configured, UDP 4-tupple %s\n", 3368 udp_rss_requested ? "enabled" : "disabled"); 3369 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3370 } 3371 return 0; 3372 3373 case IPV4_FLOW: 3374 case IPV6_FLOW: 3375 /* For IP only 2-tupple hash is supported */ 3376 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 3377 DP(BNX2X_MSG_ETHTOOL, 3378 "Command parameters not supported\n"); 3379 return -EINVAL; 3380 } 3381 return 0; 3382 3383 case SCTP_V4_FLOW: 3384 case AH_ESP_V4_FLOW: 3385 case AH_V4_FLOW: 3386 case ESP_V4_FLOW: 3387 case SCTP_V6_FLOW: 3388 case AH_ESP_V6_FLOW: 3389 case AH_V6_FLOW: 3390 case ESP_V6_FLOW: 3391 case IP_USER_FLOW: 3392 case ETHER_FLOW: 3393 /* RSS is not supported for these protocols */ 3394 if (info->data) { 3395 DP(BNX2X_MSG_ETHTOOL, 3396 "Command parameters not supported\n"); 3397 return -EINVAL; 3398 } 3399 return 0; 3400 3401 default: 3402 return -EINVAL; 3403 } 3404 } 3405 3406 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 3407 { 3408 struct bnx2x *bp = netdev_priv(dev); 3409 3410 switch (info->cmd) { 3411 case ETHTOOL_SRXFH: 3412 return bnx2x_set_rss_flags(bp, info); 3413 default: 3414 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3415 return -EOPNOTSUPP; 3416 } 3417 } 3418 3419 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3420 { 3421 return T_ETH_INDIRECTION_TABLE_SIZE; 3422 } 3423 3424 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3425 u8 *hfunc) 3426 { 3427 struct bnx2x *bp = netdev_priv(dev); 3428 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3429 size_t i; 3430 3431 if (hfunc) 3432 *hfunc = ETH_RSS_HASH_TOP; 3433 if (!indir) 3434 return 0; 3435 3436 /* Get the current configuration of the RSS indirection table */ 3437 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3438 3439 /* 3440 * We can't use a memcpy() as an internal storage of an 3441 * indirection table is a u8 array while indir->ring_index 3442 * points to an array of u32. 3443 * 3444 * Indirection table contains the FW Client IDs, so we need to 3445 * align the returned table to the Client ID of the leading RSS 3446 * queue. 3447 */ 3448 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 3449 indir[i] = ind_table[i] - bp->fp->cl_id; 3450 3451 return 0; 3452 } 3453 3454 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3455 const u8 *key, const u8 hfunc) 3456 { 3457 struct bnx2x *bp = netdev_priv(dev); 3458 size_t i; 3459 3460 /* We require at least one supported parameter to be changed and no 3461 * change in any of the unsupported parameters 3462 */ 3463 if (key || 3464 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3465 return -EOPNOTSUPP; 3466 3467 if (!indir) 3468 return 0; 3469 3470 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3471 /* 3472 * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3473 * as an internal storage of an indirection table is a u8 array 3474 * while indir->ring_index points to an array of u32. 3475 * 3476 * Indirection table contains the FW Client IDs, so we need to 3477 * align the received table to the Client ID of the leading RSS 3478 * queue 3479 */ 3480 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3481 } 3482 3483 return bnx2x_config_rss_eth(bp, false); 3484 } 3485 3486 /** 3487 * bnx2x_get_channels - gets the number of RSS queues. 3488 * 3489 * @dev: net device 3490 * @channels: returns the number of max / current queues 3491 */ 3492 static void bnx2x_get_channels(struct net_device *dev, 3493 struct ethtool_channels *channels) 3494 { 3495 struct bnx2x *bp = netdev_priv(dev); 3496 3497 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 3498 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 3499 } 3500 3501 /** 3502 * bnx2x_change_num_queues - change the number of RSS queues. 3503 * 3504 * @bp: bnx2x private structure 3505 * 3506 * Re-configure interrupt mode to get the new number of MSI-X 3507 * vectors and re-add NAPI objects. 3508 */ 3509 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 3510 { 3511 bnx2x_disable_msi(bp); 3512 bp->num_ethernet_queues = num_rss; 3513 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 3514 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 3515 bnx2x_set_int_mode(bp); 3516 } 3517 3518 /** 3519 * bnx2x_set_channels - sets the number of RSS queues. 3520 * 3521 * @dev: net device 3522 * @channels: includes the number of queues requested 3523 */ 3524 static int bnx2x_set_channels(struct net_device *dev, 3525 struct ethtool_channels *channels) 3526 { 3527 struct bnx2x *bp = netdev_priv(dev); 3528 3529 DP(BNX2X_MSG_ETHTOOL, 3530 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 3531 channels->rx_count, channels->tx_count, channels->other_count, 3532 channels->combined_count); 3533 3534 if (pci_num_vf(bp->pdev)) { 3535 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3536 return -EPERM; 3537 } 3538 3539 /* We don't support separate rx / tx channels. 3540 * We don't allow setting 'other' channels. 3541 */ 3542 if (channels->rx_count || channels->tx_count || channels->other_count 3543 || (channels->combined_count == 0) || 3544 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 3545 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 3546 return -EINVAL; 3547 } 3548 3549 /* Check if there was a change in the active parameters */ 3550 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 3551 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 3552 return 0; 3553 } 3554 3555 /* Set the requested number of queues in bp context. 3556 * Note that the actual number of queues created during load may be 3557 * less than requested if memory is low. 3558 */ 3559 if (unlikely(!netif_running(dev))) { 3560 bnx2x_change_num_queues(bp, channels->combined_count); 3561 return 0; 3562 } 3563 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 3564 bnx2x_change_num_queues(bp, channels->combined_count); 3565 return bnx2x_nic_load(bp, LOAD_NORMAL); 3566 } 3567 3568 static int bnx2x_get_ts_info(struct net_device *dev, 3569 struct ethtool_ts_info *info) 3570 { 3571 struct bnx2x *bp = netdev_priv(dev); 3572 3573 if (bp->flags & PTP_SUPPORTED) { 3574 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3575 SOF_TIMESTAMPING_RX_SOFTWARE | 3576 SOF_TIMESTAMPING_SOFTWARE | 3577 SOF_TIMESTAMPING_TX_HARDWARE | 3578 SOF_TIMESTAMPING_RX_HARDWARE | 3579 SOF_TIMESTAMPING_RAW_HARDWARE; 3580 3581 if (bp->ptp_clock) 3582 info->phc_index = ptp_clock_index(bp->ptp_clock); 3583 else 3584 info->phc_index = -1; 3585 3586 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3587 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3588 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3589 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3590 3591 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3592 3593 return 0; 3594 } 3595 3596 return ethtool_op_get_ts_info(dev, info); 3597 } 3598 3599 static const struct ethtool_ops bnx2x_ethtool_ops = { 3600 .get_settings = bnx2x_get_settings, 3601 .set_settings = bnx2x_set_settings, 3602 .get_drvinfo = bnx2x_get_drvinfo, 3603 .get_regs_len = bnx2x_get_regs_len, 3604 .get_regs = bnx2x_get_regs, 3605 .get_dump_flag = bnx2x_get_dump_flag, 3606 .get_dump_data = bnx2x_get_dump_data, 3607 .set_dump = bnx2x_set_dump, 3608 .get_wol = bnx2x_get_wol, 3609 .set_wol = bnx2x_set_wol, 3610 .get_msglevel = bnx2x_get_msglevel, 3611 .set_msglevel = bnx2x_set_msglevel, 3612 .nway_reset = bnx2x_nway_reset, 3613 .get_link = bnx2x_get_link, 3614 .get_eeprom_len = bnx2x_get_eeprom_len, 3615 .get_eeprom = bnx2x_get_eeprom, 3616 .set_eeprom = bnx2x_set_eeprom, 3617 .get_coalesce = bnx2x_get_coalesce, 3618 .set_coalesce = bnx2x_set_coalesce, 3619 .get_ringparam = bnx2x_get_ringparam, 3620 .set_ringparam = bnx2x_set_ringparam, 3621 .get_pauseparam = bnx2x_get_pauseparam, 3622 .set_pauseparam = bnx2x_set_pauseparam, 3623 .self_test = bnx2x_self_test, 3624 .get_sset_count = bnx2x_get_sset_count, 3625 .get_priv_flags = bnx2x_get_private_flags, 3626 .get_strings = bnx2x_get_strings, 3627 .set_phys_id = bnx2x_set_phys_id, 3628 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3629 .get_rxnfc = bnx2x_get_rxnfc, 3630 .set_rxnfc = bnx2x_set_rxnfc, 3631 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3632 .get_rxfh = bnx2x_get_rxfh, 3633 .set_rxfh = bnx2x_set_rxfh, 3634 .get_channels = bnx2x_get_channels, 3635 .set_channels = bnx2x_set_channels, 3636 .get_module_info = bnx2x_get_module_info, 3637 .get_module_eeprom = bnx2x_get_module_eeprom, 3638 .get_eee = bnx2x_get_eee, 3639 .set_eee = bnx2x_set_eee, 3640 .get_ts_info = bnx2x_get_ts_info, 3641 }; 3642 3643 static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3644 .get_settings = bnx2x_get_vf_settings, 3645 .get_drvinfo = bnx2x_get_drvinfo, 3646 .get_msglevel = bnx2x_get_msglevel, 3647 .set_msglevel = bnx2x_set_msglevel, 3648 .get_link = bnx2x_get_link, 3649 .get_coalesce = bnx2x_get_coalesce, 3650 .get_ringparam = bnx2x_get_ringparam, 3651 .set_ringparam = bnx2x_set_ringparam, 3652 .get_sset_count = bnx2x_get_sset_count, 3653 .get_strings = bnx2x_get_strings, 3654 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3655 .get_rxnfc = bnx2x_get_rxnfc, 3656 .set_rxnfc = bnx2x_set_rxnfc, 3657 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3658 .get_rxfh = bnx2x_get_rxfh, 3659 .set_rxfh = bnx2x_set_rxfh, 3660 .get_channels = bnx2x_get_channels, 3661 .set_channels = bnx2x_set_channels, 3662 }; 3663 3664 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3665 { 3666 netdev->ethtool_ops = (IS_PF(bp)) ? 3667 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3668 } 3669