1 /* bnx2x_ethtool.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/ethtool.h> 23 #include <linux/netdevice.h> 24 #include <linux/types.h> 25 #include <linux/sched.h> 26 #include <linux/crc32.h> 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 #include "bnx2x_dump.h" 30 #include "bnx2x_init.h" 31 32 /* Note: in the format strings below %s is replaced by the queue-name which is 33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35 */ 36 #define MAX_QUEUE_NAME_LEN 4 37 static const struct { 38 long offset; 39 int size; 40 char string[ETH_GSTRING_LEN]; 41 } bnx2x_q_stats_arr[] = { 42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44 8, "[%s]: rx_ucast_packets" }, 45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46 8, "[%s]: rx_mcast_packets" }, 47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48 8, "[%s]: rx_bcast_packets" }, 49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50 { Q_STATS_OFFSET32(rx_err_discard_pkt), 51 4, "[%s]: rx_phy_ip_err_discards"}, 52 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53 4, "[%s]: rx_skb_alloc_discard" }, 54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 55 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" }, 56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58 8, "[%s]: tx_ucast_packets" }, 59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60 8, "[%s]: tx_mcast_packets" }, 61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62 8, "[%s]: tx_bcast_packets" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64 8, "[%s]: tpa_aggregations" }, 65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66 8, "[%s]: tpa_aggregated_frames"}, 67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69 4, "[%s]: driver_filtered_tx_pkt" } 70 }; 71 72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73 74 static const struct { 75 long offset; 76 int size; 77 bool is_port_stat; 78 char string[ETH_GSTRING_LEN]; 79 } bnx2x_stats_arr[] = { 80 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 81 8, false, "rx_bytes" }, 82 { STATS_OFFSET32(error_bytes_received_hi), 83 8, false, "rx_error_bytes" }, 84 { STATS_OFFSET32(total_unicast_packets_received_hi), 85 8, false, "rx_ucast_packets" }, 86 { STATS_OFFSET32(total_multicast_packets_received_hi), 87 8, false, "rx_mcast_packets" }, 88 { STATS_OFFSET32(total_broadcast_packets_received_hi), 89 8, false, "rx_bcast_packets" }, 90 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 91 8, true, "rx_crc_errors" }, 92 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 93 8, true, "rx_align_errors" }, 94 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 95 8, true, "rx_undersize_packets" }, 96 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 97 8, true, "rx_oversize_packets" }, 98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 99 8, true, "rx_fragments" }, 100 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 101 8, true, "rx_jabbers" }, 102 { STATS_OFFSET32(no_buff_discard_hi), 103 8, false, "rx_discards" }, 104 { STATS_OFFSET32(mac_filter_discard), 105 4, true, "rx_filtered_packets" }, 106 { STATS_OFFSET32(mf_tag_discard), 107 4, true, "rx_mf_tag_discard" }, 108 { STATS_OFFSET32(pfc_frames_received_hi), 109 8, true, "pfc_frames_received" }, 110 { STATS_OFFSET32(pfc_frames_sent_hi), 111 8, true, "pfc_frames_sent" }, 112 { STATS_OFFSET32(brb_drop_hi), 113 8, true, "rx_brb_discard" }, 114 { STATS_OFFSET32(brb_truncate_hi), 115 8, true, "rx_brb_truncate" }, 116 { STATS_OFFSET32(pause_frames_received_hi), 117 8, true, "rx_pause_frames" }, 118 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 119 8, true, "rx_mac_ctrl_frames" }, 120 { STATS_OFFSET32(nig_timer_max), 121 4, true, "rx_constant_pause_events" }, 122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 123 4, false, "rx_phy_ip_err_discards"}, 124 { STATS_OFFSET32(rx_skb_alloc_failed), 125 4, false, "rx_skb_alloc_discard" }, 126 { STATS_OFFSET32(hw_csum_err), 127 4, false, "rx_csum_offload_errors" }, 128 { STATS_OFFSET32(driver_xoff), 129 4, false, "tx_exhaustion_events" }, 130 { STATS_OFFSET32(total_bytes_transmitted_hi), 131 8, false, "tx_bytes" }, 132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133 8, true, "tx_error_bytes" }, 134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135 8, false, "tx_ucast_packets" }, 136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137 8, false, "tx_mcast_packets" }, 138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139 8, false, "tx_bcast_packets" }, 140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141 8, true, "tx_mac_errors" }, 142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143 8, true, "tx_carrier_errors" }, 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145 8, true, "tx_single_collisions" }, 146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147 8, true, "tx_multi_collisions" }, 148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149 8, true, "tx_deferred" }, 150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151 8, true, "tx_excess_collisions" }, 152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153 8, true, "tx_late_collisions" }, 154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155 8, true, "tx_total_collisions" }, 156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157 8, true, "tx_64_byte_packets" }, 158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159 8, true, "tx_65_to_127_byte_packets" }, 160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161 8, true, "tx_128_to_255_byte_packets" }, 162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163 8, true, "tx_256_to_511_byte_packets" }, 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165 8, true, "tx_512_to_1023_byte_packets" }, 166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167 8, true, "tx_1024_to_1522_byte_packets" }, 168 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169 8, true, "tx_1523_to_9022_byte_packets" }, 170 { STATS_OFFSET32(pause_frames_sent_hi), 171 8, true, "tx_pause_frames" }, 172 { STATS_OFFSET32(total_tpa_aggregations_hi), 173 8, false, "tpa_aggregations" }, 174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175 8, false, "tpa_aggregated_frames"}, 176 { STATS_OFFSET32(total_tpa_bytes_hi), 177 8, false, "tpa_bytes"}, 178 { STATS_OFFSET32(recoverable_error), 179 4, false, "recoverable_errors" }, 180 { STATS_OFFSET32(unrecoverable_error), 181 4, false, "unrecoverable_errors" }, 182 { STATS_OFFSET32(driver_filtered_tx_pkt), 183 4, false, "driver_filtered_tx_pkt" }, 184 { STATS_OFFSET32(eee_tx_lpi), 185 4, true, "Tx LPI entry count"}, 186 { STATS_OFFSET32(ptp_skip_tx_ts), 187 4, false, "ptp_skipped_tx_tstamp" }, 188 }; 189 190 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 191 192 static int bnx2x_get_port_type(struct bnx2x *bp) 193 { 194 int port_type; 195 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 196 switch (bp->link_params.phy[phy_idx].media_type) { 197 case ETH_PHY_SFPP_10G_FIBER: 198 case ETH_PHY_SFP_1G_FIBER: 199 case ETH_PHY_XFP_FIBER: 200 case ETH_PHY_KR: 201 case ETH_PHY_CX4: 202 port_type = PORT_FIBRE; 203 break; 204 case ETH_PHY_DA_TWINAX: 205 port_type = PORT_DA; 206 break; 207 case ETH_PHY_BASE_T: 208 port_type = PORT_TP; 209 break; 210 case ETH_PHY_NOT_PRESENT: 211 port_type = PORT_NONE; 212 break; 213 case ETH_PHY_UNSPECIFIED: 214 default: 215 port_type = PORT_OTHER; 216 break; 217 } 218 return port_type; 219 } 220 221 static int bnx2x_get_vf_link_ksettings(struct net_device *dev, 222 struct ethtool_link_ksettings *cmd) 223 { 224 struct bnx2x *bp = netdev_priv(dev); 225 u32 supported, advertising; 226 227 ethtool_convert_link_mode_to_legacy_u32(&supported, 228 cmd->link_modes.supported); 229 ethtool_convert_link_mode_to_legacy_u32(&advertising, 230 cmd->link_modes.advertising); 231 232 if (bp->state == BNX2X_STATE_OPEN) { 233 if (test_bit(BNX2X_LINK_REPORT_FD, 234 &bp->vf_link_vars.link_report_flags)) 235 cmd->base.duplex = DUPLEX_FULL; 236 else 237 cmd->base.duplex = DUPLEX_HALF; 238 239 cmd->base.speed = bp->vf_link_vars.line_speed; 240 } else { 241 cmd->base.duplex = DUPLEX_UNKNOWN; 242 cmd->base.speed = SPEED_UNKNOWN; 243 } 244 245 cmd->base.port = PORT_OTHER; 246 cmd->base.phy_address = 0; 247 cmd->base.autoneg = AUTONEG_DISABLE; 248 249 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 250 " supported 0x%x advertising 0x%x speed %u\n" 251 " duplex %d port %d phy_address %d\n" 252 " autoneg %d\n", 253 cmd->base.cmd, supported, advertising, 254 cmd->base.speed, 255 cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 256 cmd->base.autoneg); 257 258 return 0; 259 } 260 261 static int bnx2x_get_link_ksettings(struct net_device *dev, 262 struct ethtool_link_ksettings *cmd) 263 { 264 struct bnx2x *bp = netdev_priv(dev); 265 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 266 u32 media_type; 267 u32 supported, advertising, lp_advertising; 268 269 ethtool_convert_link_mode_to_legacy_u32(&lp_advertising, 270 cmd->link_modes.lp_advertising); 271 272 /* Dual Media boards present all available port types */ 273 supported = bp->port.supported[cfg_idx] | 274 (bp->port.supported[cfg_idx ^ 1] & 275 (SUPPORTED_TP | SUPPORTED_FIBRE)); 276 advertising = bp->port.advertising[cfg_idx]; 277 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 278 if (media_type == ETH_PHY_SFP_1G_FIBER) { 279 supported &= ~(SUPPORTED_10000baseT_Full); 280 advertising &= ~(ADVERTISED_10000baseT_Full); 281 } 282 283 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 284 !(bp->flags & MF_FUNC_DIS)) { 285 cmd->base.duplex = bp->link_vars.duplex; 286 287 if (IS_MF(bp) && !BP_NOMCP(bp)) 288 cmd->base.speed = bnx2x_get_mf_speed(bp); 289 else 290 cmd->base.speed = bp->link_vars.line_speed; 291 } else { 292 cmd->base.duplex = DUPLEX_UNKNOWN; 293 cmd->base.speed = SPEED_UNKNOWN; 294 } 295 296 cmd->base.port = bnx2x_get_port_type(bp); 297 298 cmd->base.phy_address = bp->mdio.prtad; 299 300 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 301 cmd->base.autoneg = AUTONEG_ENABLE; 302 else 303 cmd->base.autoneg = AUTONEG_DISABLE; 304 305 /* Publish LP advertised speeds and FC */ 306 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 307 u32 status = bp->link_vars.link_status; 308 309 lp_advertising |= ADVERTISED_Autoneg; 310 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 311 lp_advertising |= ADVERTISED_Pause; 312 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 313 lp_advertising |= ADVERTISED_Asym_Pause; 314 315 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 316 lp_advertising |= ADVERTISED_10baseT_Half; 317 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 318 lp_advertising |= ADVERTISED_10baseT_Full; 319 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 320 lp_advertising |= ADVERTISED_100baseT_Half; 321 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 322 lp_advertising |= ADVERTISED_100baseT_Full; 323 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 324 lp_advertising |= ADVERTISED_1000baseT_Half; 325 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 326 if (media_type == ETH_PHY_KR) { 327 lp_advertising |= 328 ADVERTISED_1000baseKX_Full; 329 } else { 330 lp_advertising |= 331 ADVERTISED_1000baseT_Full; 332 } 333 } 334 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 335 lp_advertising |= ADVERTISED_2500baseX_Full; 336 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 337 if (media_type == ETH_PHY_KR) { 338 lp_advertising |= 339 ADVERTISED_10000baseKR_Full; 340 } else { 341 lp_advertising |= 342 ADVERTISED_10000baseT_Full; 343 } 344 } 345 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 346 lp_advertising |= ADVERTISED_20000baseKR2_Full; 347 } 348 349 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 350 supported); 351 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 352 advertising); 353 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 354 lp_advertising); 355 356 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 357 " supported 0x%x advertising 0x%x speed %u\n" 358 " duplex %d port %d phy_address %d\n" 359 " autoneg %d\n", 360 cmd->base.cmd, supported, advertising, 361 cmd->base.speed, 362 cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 363 cmd->base.autoneg); 364 365 return 0; 366 } 367 368 static int bnx2x_set_link_ksettings(struct net_device *dev, 369 const struct ethtool_link_ksettings *cmd) 370 { 371 struct bnx2x *bp = netdev_priv(dev); 372 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 373 u32 speed, phy_idx; 374 u32 supported; 375 u8 duplex = cmd->base.duplex; 376 377 ethtool_convert_link_mode_to_legacy_u32(&supported, 378 cmd->link_modes.supported); 379 ethtool_convert_link_mode_to_legacy_u32(&advertising, 380 cmd->link_modes.advertising); 381 382 if (IS_MF_SD(bp)) 383 return 0; 384 385 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 386 " supported 0x%x advertising 0x%x speed %u\n" 387 " duplex %d port %d phy_address %d\n" 388 " autoneg %d\n", 389 cmd->base.cmd, supported, advertising, 390 cmd->base.speed, 391 cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 392 cmd->base.autoneg); 393 394 speed = cmd->base.speed; 395 396 /* If received a request for an unknown duplex, assume full*/ 397 if (duplex == DUPLEX_UNKNOWN) 398 duplex = DUPLEX_FULL; 399 400 if (IS_MF_SI(bp)) { 401 u32 part; 402 u32 line_speed = bp->link_vars.line_speed; 403 404 /* use 10G if no link detected */ 405 if (!line_speed) 406 line_speed = 10000; 407 408 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 409 DP(BNX2X_MSG_ETHTOOL, 410 "To set speed BC %X or higher is required, please upgrade BC\n", 411 REQ_BC_VER_4_SET_MF_BW); 412 return -EINVAL; 413 } 414 415 part = (speed * 100) / line_speed; 416 417 if (line_speed < speed || !part) { 418 DP(BNX2X_MSG_ETHTOOL, 419 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 420 return -EINVAL; 421 } 422 423 if (bp->state != BNX2X_STATE_OPEN) 424 /* store value for following "load" */ 425 bp->pending_max = part; 426 else 427 bnx2x_update_max_mf_config(bp, part); 428 429 return 0; 430 } 431 432 cfg_idx = bnx2x_get_link_cfg_idx(bp); 433 old_multi_phy_config = bp->link_params.multi_phy_config; 434 if (cmd->base.port != bnx2x_get_port_type(bp)) { 435 switch (cmd->base.port) { 436 case PORT_TP: 437 if (!(bp->port.supported[0] & SUPPORTED_TP || 438 bp->port.supported[1] & SUPPORTED_TP)) { 439 DP(BNX2X_MSG_ETHTOOL, 440 "Unsupported port type\n"); 441 return -EINVAL; 442 } 443 bp->link_params.multi_phy_config &= 444 ~PORT_HW_CFG_PHY_SELECTION_MASK; 445 if (bp->link_params.multi_phy_config & 446 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 447 bp->link_params.multi_phy_config |= 448 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 449 else 450 bp->link_params.multi_phy_config |= 451 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 452 break; 453 case PORT_FIBRE: 454 case PORT_DA: 455 case PORT_NONE: 456 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 457 bp->port.supported[1] & SUPPORTED_FIBRE)) { 458 DP(BNX2X_MSG_ETHTOOL, 459 "Unsupported port type\n"); 460 return -EINVAL; 461 } 462 bp->link_params.multi_phy_config &= 463 ~PORT_HW_CFG_PHY_SELECTION_MASK; 464 if (bp->link_params.multi_phy_config & 465 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 466 bp->link_params.multi_phy_config |= 467 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 468 else 469 bp->link_params.multi_phy_config |= 470 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 471 break; 472 default: 473 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 474 return -EINVAL; 475 } 476 } 477 /* Save new config in case command complete successfully */ 478 new_multi_phy_config = bp->link_params.multi_phy_config; 479 /* Get the new cfg_idx */ 480 cfg_idx = bnx2x_get_link_cfg_idx(bp); 481 /* Restore old config in case command failed */ 482 bp->link_params.multi_phy_config = old_multi_phy_config; 483 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 484 485 if (cmd->base.autoneg == AUTONEG_ENABLE) { 486 u32 an_supported_speed = bp->port.supported[cfg_idx]; 487 if (bp->link_params.phy[EXT_PHY1].type == 488 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 489 an_supported_speed |= (SUPPORTED_100baseT_Half | 490 SUPPORTED_100baseT_Full); 491 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 492 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 493 return -EINVAL; 494 } 495 496 /* advertise the requested speed and duplex if supported */ 497 if (advertising & ~an_supported_speed) { 498 DP(BNX2X_MSG_ETHTOOL, 499 "Advertisement parameters are not supported\n"); 500 return -EINVAL; 501 } 502 503 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 504 bp->link_params.req_duplex[cfg_idx] = duplex; 505 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 506 advertising); 507 if (advertising) { 508 509 bp->link_params.speed_cap_mask[cfg_idx] = 0; 510 if (advertising & ADVERTISED_10baseT_Half) { 511 bp->link_params.speed_cap_mask[cfg_idx] |= 512 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 513 } 514 if (advertising & ADVERTISED_10baseT_Full) 515 bp->link_params.speed_cap_mask[cfg_idx] |= 516 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 517 518 if (advertising & ADVERTISED_100baseT_Full) 519 bp->link_params.speed_cap_mask[cfg_idx] |= 520 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 521 522 if (advertising & ADVERTISED_100baseT_Half) { 523 bp->link_params.speed_cap_mask[cfg_idx] |= 524 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 525 } 526 if (advertising & ADVERTISED_1000baseT_Half) { 527 bp->link_params.speed_cap_mask[cfg_idx] |= 528 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 529 } 530 if (advertising & (ADVERTISED_1000baseT_Full | 531 ADVERTISED_1000baseKX_Full)) 532 bp->link_params.speed_cap_mask[cfg_idx] |= 533 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 534 535 if (advertising & (ADVERTISED_10000baseT_Full | 536 ADVERTISED_10000baseKX4_Full | 537 ADVERTISED_10000baseKR_Full)) 538 bp->link_params.speed_cap_mask[cfg_idx] |= 539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 540 541 if (advertising & ADVERTISED_20000baseKR2_Full) 542 bp->link_params.speed_cap_mask[cfg_idx] |= 543 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 544 } 545 } else { /* forced speed */ 546 /* advertise the requested speed and duplex if supported */ 547 switch (speed) { 548 case SPEED_10: 549 if (duplex == DUPLEX_FULL) { 550 if (!(bp->port.supported[cfg_idx] & 551 SUPPORTED_10baseT_Full)) { 552 DP(BNX2X_MSG_ETHTOOL, 553 "10M full not supported\n"); 554 return -EINVAL; 555 } 556 557 advertising = (ADVERTISED_10baseT_Full | 558 ADVERTISED_TP); 559 } else { 560 if (!(bp->port.supported[cfg_idx] & 561 SUPPORTED_10baseT_Half)) { 562 DP(BNX2X_MSG_ETHTOOL, 563 "10M half not supported\n"); 564 return -EINVAL; 565 } 566 567 advertising = (ADVERTISED_10baseT_Half | 568 ADVERTISED_TP); 569 } 570 break; 571 572 case SPEED_100: 573 if (duplex == DUPLEX_FULL) { 574 if (!(bp->port.supported[cfg_idx] & 575 SUPPORTED_100baseT_Full)) { 576 DP(BNX2X_MSG_ETHTOOL, 577 "100M full not supported\n"); 578 return -EINVAL; 579 } 580 581 advertising = (ADVERTISED_100baseT_Full | 582 ADVERTISED_TP); 583 } else { 584 if (!(bp->port.supported[cfg_idx] & 585 SUPPORTED_100baseT_Half)) { 586 DP(BNX2X_MSG_ETHTOOL, 587 "100M half not supported\n"); 588 return -EINVAL; 589 } 590 591 advertising = (ADVERTISED_100baseT_Half | 592 ADVERTISED_TP); 593 } 594 break; 595 596 case SPEED_1000: 597 if (duplex != DUPLEX_FULL) { 598 DP(BNX2X_MSG_ETHTOOL, 599 "1G half not supported\n"); 600 return -EINVAL; 601 } 602 603 if (bp->port.supported[cfg_idx] & 604 SUPPORTED_1000baseT_Full) { 605 advertising = (ADVERTISED_1000baseT_Full | 606 ADVERTISED_TP); 607 608 } else if (bp->port.supported[cfg_idx] & 609 SUPPORTED_1000baseKX_Full) { 610 advertising = ADVERTISED_1000baseKX_Full; 611 } else { 612 DP(BNX2X_MSG_ETHTOOL, 613 "1G full not supported\n"); 614 return -EINVAL; 615 } 616 617 break; 618 619 case SPEED_2500: 620 if (duplex != DUPLEX_FULL) { 621 DP(BNX2X_MSG_ETHTOOL, 622 "2.5G half not supported\n"); 623 return -EINVAL; 624 } 625 626 if (!(bp->port.supported[cfg_idx] 627 & SUPPORTED_2500baseX_Full)) { 628 DP(BNX2X_MSG_ETHTOOL, 629 "2.5G full not supported\n"); 630 return -EINVAL; 631 } 632 633 advertising = (ADVERTISED_2500baseX_Full | 634 ADVERTISED_TP); 635 break; 636 637 case SPEED_10000: 638 if (duplex != DUPLEX_FULL) { 639 DP(BNX2X_MSG_ETHTOOL, 640 "10G half not supported\n"); 641 return -EINVAL; 642 } 643 phy_idx = bnx2x_get_cur_phy_idx(bp); 644 if ((bp->port.supported[cfg_idx] & 645 SUPPORTED_10000baseT_Full) && 646 (bp->link_params.phy[phy_idx].media_type != 647 ETH_PHY_SFP_1G_FIBER)) { 648 advertising = (ADVERTISED_10000baseT_Full | 649 ADVERTISED_FIBRE); 650 } else if (bp->port.supported[cfg_idx] & 651 SUPPORTED_10000baseKR_Full) { 652 advertising = (ADVERTISED_10000baseKR_Full | 653 ADVERTISED_FIBRE); 654 } else { 655 DP(BNX2X_MSG_ETHTOOL, 656 "10G full not supported\n"); 657 return -EINVAL; 658 } 659 660 break; 661 662 default: 663 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 664 return -EINVAL; 665 } 666 667 bp->link_params.req_line_speed[cfg_idx] = speed; 668 bp->link_params.req_duplex[cfg_idx] = duplex; 669 bp->port.advertising[cfg_idx] = advertising; 670 } 671 672 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 673 " req_duplex %d advertising 0x%x\n", 674 bp->link_params.req_line_speed[cfg_idx], 675 bp->link_params.req_duplex[cfg_idx], 676 bp->port.advertising[cfg_idx]); 677 678 /* Set new config */ 679 bp->link_params.multi_phy_config = new_multi_phy_config; 680 if (netif_running(dev)) { 681 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 682 bnx2x_force_link_reset(bp); 683 bnx2x_link_set(bp); 684 } 685 686 return 0; 687 } 688 689 #define DUMP_ALL_PRESETS 0x1FFF 690 #define DUMP_MAX_PRESETS 13 691 692 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 693 { 694 if (CHIP_IS_E1(bp)) 695 return dump_num_registers[0][preset-1]; 696 else if (CHIP_IS_E1H(bp)) 697 return dump_num_registers[1][preset-1]; 698 else if (CHIP_IS_E2(bp)) 699 return dump_num_registers[2][preset-1]; 700 else if (CHIP_IS_E3A0(bp)) 701 return dump_num_registers[3][preset-1]; 702 else if (CHIP_IS_E3B0(bp)) 703 return dump_num_registers[4][preset-1]; 704 else 705 return 0; 706 } 707 708 static int __bnx2x_get_regs_len(struct bnx2x *bp) 709 { 710 u32 preset_idx; 711 int regdump_len = 0; 712 713 /* Calculate the total preset regs length */ 714 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 715 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 716 717 return regdump_len; 718 } 719 720 static int bnx2x_get_regs_len(struct net_device *dev) 721 { 722 struct bnx2x *bp = netdev_priv(dev); 723 int regdump_len = 0; 724 725 if (IS_VF(bp)) 726 return 0; 727 728 regdump_len = __bnx2x_get_regs_len(bp); 729 regdump_len *= 4; 730 regdump_len += sizeof(struct dump_header); 731 732 return regdump_len; 733 } 734 735 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 736 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 737 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 738 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 739 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 740 741 #define IS_REG_IN_PRESET(presets, idx) \ 742 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 743 744 /******* Paged registers info selectors ********/ 745 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 746 { 747 if (CHIP_IS_E2(bp)) 748 return page_vals_e2; 749 else if (CHIP_IS_E3(bp)) 750 return page_vals_e3; 751 else 752 return NULL; 753 } 754 755 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 756 { 757 if (CHIP_IS_E2(bp)) 758 return PAGE_MODE_VALUES_E2; 759 else if (CHIP_IS_E3(bp)) 760 return PAGE_MODE_VALUES_E3; 761 else 762 return 0; 763 } 764 765 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 766 { 767 if (CHIP_IS_E2(bp)) 768 return page_write_regs_e2; 769 else if (CHIP_IS_E3(bp)) 770 return page_write_regs_e3; 771 else 772 return NULL; 773 } 774 775 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 776 { 777 if (CHIP_IS_E2(bp)) 778 return PAGE_WRITE_REGS_E2; 779 else if (CHIP_IS_E3(bp)) 780 return PAGE_WRITE_REGS_E3; 781 else 782 return 0; 783 } 784 785 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 786 { 787 if (CHIP_IS_E2(bp)) 788 return page_read_regs_e2; 789 else if (CHIP_IS_E3(bp)) 790 return page_read_regs_e3; 791 else 792 return NULL; 793 } 794 795 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 796 { 797 if (CHIP_IS_E2(bp)) 798 return PAGE_READ_REGS_E2; 799 else if (CHIP_IS_E3(bp)) 800 return PAGE_READ_REGS_E3; 801 else 802 return 0; 803 } 804 805 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 806 const struct reg_addr *reg_info) 807 { 808 if (CHIP_IS_E1(bp)) 809 return IS_E1_REG(reg_info->chips); 810 else if (CHIP_IS_E1H(bp)) 811 return IS_E1H_REG(reg_info->chips); 812 else if (CHIP_IS_E2(bp)) 813 return IS_E2_REG(reg_info->chips); 814 else if (CHIP_IS_E3A0(bp)) 815 return IS_E3A0_REG(reg_info->chips); 816 else if (CHIP_IS_E3B0(bp)) 817 return IS_E3B0_REG(reg_info->chips); 818 else 819 return false; 820 } 821 822 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 823 const struct wreg_addr *wreg_info) 824 { 825 if (CHIP_IS_E1(bp)) 826 return IS_E1_REG(wreg_info->chips); 827 else if (CHIP_IS_E1H(bp)) 828 return IS_E1H_REG(wreg_info->chips); 829 else if (CHIP_IS_E2(bp)) 830 return IS_E2_REG(wreg_info->chips); 831 else if (CHIP_IS_E3A0(bp)) 832 return IS_E3A0_REG(wreg_info->chips); 833 else if (CHIP_IS_E3B0(bp)) 834 return IS_E3B0_REG(wreg_info->chips); 835 else 836 return false; 837 } 838 839 /** 840 * bnx2x_read_pages_regs - read "paged" registers 841 * 842 * @bp device handle 843 * @p output buffer 844 * 845 * Reads "paged" memories: memories that may only be read by first writing to a 846 * specific address ("write address") and then reading from a specific address 847 * ("read address"). There may be more than one write address per "page" and 848 * more than one read address per write address. 849 */ 850 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 851 { 852 u32 i, j, k, n; 853 854 /* addresses of the paged registers */ 855 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 856 /* number of paged registers */ 857 int num_pages = __bnx2x_get_page_reg_num(bp); 858 /* write addresses */ 859 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 860 /* number of write addresses */ 861 int write_num = __bnx2x_get_page_write_num(bp); 862 /* read addresses info */ 863 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 864 /* number of read addresses */ 865 int read_num = __bnx2x_get_page_read_num(bp); 866 u32 addr, size; 867 868 for (i = 0; i < num_pages; i++) { 869 for (j = 0; j < write_num; j++) { 870 REG_WR(bp, write_addr[j], page_addr[i]); 871 872 for (k = 0; k < read_num; k++) { 873 if (IS_REG_IN_PRESET(read_addr[k].presets, 874 preset)) { 875 size = read_addr[k].size; 876 for (n = 0; n < size; n++) { 877 addr = read_addr[k].addr + n*4; 878 *p++ = REG_RD(bp, addr); 879 } 880 } 881 } 882 } 883 } 884 } 885 886 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 887 { 888 u32 i, j, addr; 889 const struct wreg_addr *wreg_addr_p = NULL; 890 891 if (CHIP_IS_E1(bp)) 892 wreg_addr_p = &wreg_addr_e1; 893 else if (CHIP_IS_E1H(bp)) 894 wreg_addr_p = &wreg_addr_e1h; 895 else if (CHIP_IS_E2(bp)) 896 wreg_addr_p = &wreg_addr_e2; 897 else if (CHIP_IS_E3A0(bp)) 898 wreg_addr_p = &wreg_addr_e3; 899 else if (CHIP_IS_E3B0(bp)) 900 wreg_addr_p = &wreg_addr_e3b0; 901 902 /* Read the idle_chk registers */ 903 for (i = 0; i < IDLE_REGS_COUNT; i++) { 904 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 905 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 906 for (j = 0; j < idle_reg_addrs[i].size; j++) 907 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 908 } 909 } 910 911 /* Read the regular registers */ 912 for (i = 0; i < REGS_COUNT; i++) { 913 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 914 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 915 for (j = 0; j < reg_addrs[i].size; j++) 916 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 917 } 918 } 919 920 /* Read the CAM registers */ 921 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 922 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 923 for (i = 0; i < wreg_addr_p->size; i++) { 924 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 925 926 /* In case of wreg_addr register, read additional 927 registers from read_regs array 928 */ 929 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 930 addr = *(wreg_addr_p->read_regs); 931 *p++ = REG_RD(bp, addr + j*4); 932 } 933 } 934 } 935 936 /* Paged registers are supported in E2 & E3 only */ 937 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 938 /* Read "paged" registers */ 939 bnx2x_read_pages_regs(bp, p, preset); 940 } 941 942 return 0; 943 } 944 945 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 946 { 947 u32 preset_idx; 948 949 /* Read all registers, by reading all preset registers */ 950 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 951 /* Skip presets with IOR */ 952 if ((preset_idx == 2) || 953 (preset_idx == 5) || 954 (preset_idx == 8) || 955 (preset_idx == 11)) 956 continue; 957 __bnx2x_get_preset_regs(bp, p, preset_idx); 958 p += __bnx2x_get_preset_regs_len(bp, preset_idx); 959 } 960 } 961 962 static void bnx2x_get_regs(struct net_device *dev, 963 struct ethtool_regs *regs, void *_p) 964 { 965 u32 *p = _p; 966 struct bnx2x *bp = netdev_priv(dev); 967 struct dump_header dump_hdr = {0}; 968 969 regs->version = 2; 970 memset(p, 0, regs->len); 971 972 if (!netif_running(bp->dev)) 973 return; 974 975 /* Disable parity attentions as long as following dump may 976 * cause false alarms by reading never written registers. We 977 * will re-enable parity attentions right after the dump. 978 */ 979 980 bnx2x_disable_blocks_parity(bp); 981 982 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 983 dump_hdr.preset = DUMP_ALL_PRESETS; 984 dump_hdr.version = BNX2X_DUMP_VERSION; 985 986 /* dump_meta_data presents OR of CHIP and PATH. */ 987 if (CHIP_IS_E1(bp)) { 988 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 989 } else if (CHIP_IS_E1H(bp)) { 990 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 991 } else if (CHIP_IS_E2(bp)) { 992 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 993 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 994 } else if (CHIP_IS_E3A0(bp)) { 995 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 996 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 997 } else if (CHIP_IS_E3B0(bp)) { 998 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 999 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1000 } 1001 1002 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1003 p += dump_hdr.header_size + 1; 1004 1005 /* This isn't really an error, but since attention handling is going 1006 * to print the GRC timeouts using this macro, we use the same. 1007 */ 1008 BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n"); 1009 1010 /* Actually read the registers */ 1011 __bnx2x_get_regs(bp, p); 1012 1013 /* Re-enable parity attentions */ 1014 bnx2x_clear_blocks_parity(bp); 1015 bnx2x_enable_blocks_parity(bp); 1016 } 1017 1018 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 1019 { 1020 struct bnx2x *bp = netdev_priv(dev); 1021 int regdump_len = 0; 1022 1023 regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 1024 regdump_len *= 4; 1025 regdump_len += sizeof(struct dump_header); 1026 1027 return regdump_len; 1028 } 1029 1030 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 1031 { 1032 struct bnx2x *bp = netdev_priv(dev); 1033 1034 /* Use the ethtool_dump "flag" field as the dump preset index */ 1035 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 1036 return -EINVAL; 1037 1038 bp->dump_preset_idx = val->flag; 1039 return 0; 1040 } 1041 1042 static int bnx2x_get_dump_flag(struct net_device *dev, 1043 struct ethtool_dump *dump) 1044 { 1045 struct bnx2x *bp = netdev_priv(dev); 1046 1047 dump->version = BNX2X_DUMP_VERSION; 1048 dump->flag = bp->dump_preset_idx; 1049 /* Calculate the requested preset idx length */ 1050 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 1051 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 1052 bp->dump_preset_idx, dump->len); 1053 return 0; 1054 } 1055 1056 static int bnx2x_get_dump_data(struct net_device *dev, 1057 struct ethtool_dump *dump, 1058 void *buffer) 1059 { 1060 u32 *p = buffer; 1061 struct bnx2x *bp = netdev_priv(dev); 1062 struct dump_header dump_hdr = {0}; 1063 1064 /* Disable parity attentions as long as following dump may 1065 * cause false alarms by reading never written registers. We 1066 * will re-enable parity attentions right after the dump. 1067 */ 1068 1069 bnx2x_disable_blocks_parity(bp); 1070 1071 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 1072 dump_hdr.preset = bp->dump_preset_idx; 1073 dump_hdr.version = BNX2X_DUMP_VERSION; 1074 1075 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 1076 1077 /* dump_meta_data presents OR of CHIP and PATH. */ 1078 if (CHIP_IS_E1(bp)) { 1079 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 1080 } else if (CHIP_IS_E1H(bp)) { 1081 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 1082 } else if (CHIP_IS_E2(bp)) { 1083 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 1084 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1085 } else if (CHIP_IS_E3A0(bp)) { 1086 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 1087 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1088 } else if (CHIP_IS_E3B0(bp)) { 1089 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 1090 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1091 } 1092 1093 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1094 p += dump_hdr.header_size + 1; 1095 1096 /* Actually read the registers */ 1097 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1098 1099 /* Re-enable parity attentions */ 1100 bnx2x_clear_blocks_parity(bp); 1101 bnx2x_enable_blocks_parity(bp); 1102 1103 return 0; 1104 } 1105 1106 static void bnx2x_get_drvinfo(struct net_device *dev, 1107 struct ethtool_drvinfo *info) 1108 { 1109 struct bnx2x *bp = netdev_priv(dev); 1110 char version[ETHTOOL_FWVERS_LEN]; 1111 int ext_dev_info_offset; 1112 u32 mbi; 1113 1114 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1115 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1116 1117 memset(version, 0, sizeof(version)); 1118 snprintf(version, ETHTOOL_FWVERS_LEN, " storm %d.%d.%d.%d", 1119 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION, 1120 BCM_5710_FW_REVISION_VERSION, BCM_5710_FW_ENGINEERING_VERSION); 1121 strlcat(info->version, version, sizeof(info->version)); 1122 1123 if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) { 1124 ext_dev_info_offset = SHMEM2_RD(bp, 1125 extended_dev_info_shared_addr); 1126 mbi = REG_RD(bp, ext_dev_info_offset + 1127 offsetof(struct extended_dev_info_shared_cfg, 1128 mbi_version)); 1129 if (mbi) { 1130 memset(version, 0, sizeof(version)); 1131 snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ", 1132 (mbi & 0xff000000) >> 24, 1133 (mbi & 0x00ff0000) >> 16, 1134 (mbi & 0x0000ff00) >> 8); 1135 strlcpy(info->fw_version, version, 1136 sizeof(info->fw_version)); 1137 } 1138 } 1139 1140 memset(version, 0, sizeof(version)); 1141 bnx2x_fill_fw_str(bp, version, ETHTOOL_FWVERS_LEN); 1142 strlcat(info->fw_version, version, sizeof(info->fw_version)); 1143 1144 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1145 } 1146 1147 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1148 { 1149 struct bnx2x *bp = netdev_priv(dev); 1150 1151 if (bp->flags & NO_WOL_FLAG) { 1152 wol->supported = 0; 1153 wol->wolopts = 0; 1154 } else { 1155 wol->supported = WAKE_MAGIC; 1156 if (bp->wol) 1157 wol->wolopts = WAKE_MAGIC; 1158 else 1159 wol->wolopts = 0; 1160 } 1161 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1162 } 1163 1164 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1165 { 1166 struct bnx2x *bp = netdev_priv(dev); 1167 1168 if (wol->wolopts & ~WAKE_MAGIC) { 1169 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1170 return -EINVAL; 1171 } 1172 1173 if (wol->wolopts & WAKE_MAGIC) { 1174 if (bp->flags & NO_WOL_FLAG) { 1175 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1176 return -EINVAL; 1177 } 1178 bp->wol = 1; 1179 } else 1180 bp->wol = 0; 1181 1182 if (SHMEM2_HAS(bp, curr_cfg)) 1183 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1184 1185 return 0; 1186 } 1187 1188 static u32 bnx2x_get_msglevel(struct net_device *dev) 1189 { 1190 struct bnx2x *bp = netdev_priv(dev); 1191 1192 return bp->msg_enable; 1193 } 1194 1195 static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1196 { 1197 struct bnx2x *bp = netdev_priv(dev); 1198 1199 if (capable(CAP_NET_ADMIN)) { 1200 /* dump MCP trace */ 1201 if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1202 bnx2x_fw_dump_lvl(bp, KERN_INFO); 1203 bp->msg_enable = level; 1204 } 1205 } 1206 1207 static int bnx2x_nway_reset(struct net_device *dev) 1208 { 1209 struct bnx2x *bp = netdev_priv(dev); 1210 1211 if (!bp->port.pmf) 1212 return 0; 1213 1214 if (netif_running(dev)) { 1215 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1216 bnx2x_force_link_reset(bp); 1217 bnx2x_link_set(bp); 1218 } 1219 1220 return 0; 1221 } 1222 1223 static u32 bnx2x_get_link(struct net_device *dev) 1224 { 1225 struct bnx2x *bp = netdev_priv(dev); 1226 1227 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1228 return 0; 1229 1230 if (IS_VF(bp)) 1231 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1232 &bp->vf_link_vars.link_report_flags); 1233 1234 return bp->link_vars.link_up; 1235 } 1236 1237 static int bnx2x_get_eeprom_len(struct net_device *dev) 1238 { 1239 struct bnx2x *bp = netdev_priv(dev); 1240 1241 return bp->common.flash_size; 1242 } 1243 1244 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1245 * had we done things the other way around, if two pfs from the same port would 1246 * attempt to access nvram at the same time, we could run into a scenario such 1247 * as: 1248 * pf A takes the port lock. 1249 * pf B succeeds in taking the same lock since they are from the same port. 1250 * pf A takes the per pf misc lock. Performs eeprom access. 1251 * pf A finishes. Unlocks the per pf misc lock. 1252 * Pf B takes the lock and proceeds to perform it's own access. 1253 * pf A unlocks the per port lock, while pf B is still working (!). 1254 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1255 * access corrupted by pf B) 1256 */ 1257 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1258 { 1259 int port = BP_PORT(bp); 1260 int count, i; 1261 u32 val; 1262 1263 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1264 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1265 1266 /* adjust timeout for emulation/FPGA */ 1267 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1268 if (CHIP_REV_IS_SLOW(bp)) 1269 count *= 100; 1270 1271 /* request access to nvram interface */ 1272 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1273 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1274 1275 for (i = 0; i < count*10; i++) { 1276 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1277 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1278 break; 1279 1280 udelay(5); 1281 } 1282 1283 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1284 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1285 "cannot get access to nvram interface\n"); 1286 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1287 return -EBUSY; 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1294 { 1295 int port = BP_PORT(bp); 1296 int count, i; 1297 u32 val; 1298 1299 /* adjust timeout for emulation/FPGA */ 1300 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1301 if (CHIP_REV_IS_SLOW(bp)) 1302 count *= 100; 1303 1304 /* relinquish nvram interface */ 1305 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1306 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1307 1308 for (i = 0; i < count*10; i++) { 1309 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1310 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1311 break; 1312 1313 udelay(5); 1314 } 1315 1316 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1317 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1318 "cannot free access to nvram interface\n"); 1319 return -EBUSY; 1320 } 1321 1322 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1323 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1324 return 0; 1325 } 1326 1327 static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1328 { 1329 u32 val; 1330 1331 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1332 1333 /* enable both bits, even on read */ 1334 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1335 (val | MCPR_NVM_ACCESS_ENABLE_EN | 1336 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1337 } 1338 1339 static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1340 { 1341 u32 val; 1342 1343 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1344 1345 /* disable both bits, even after read */ 1346 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1347 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1348 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1349 } 1350 1351 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1352 u32 cmd_flags) 1353 { 1354 int count, i, rc; 1355 u32 val; 1356 1357 /* build the command word */ 1358 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1359 1360 /* need to clear DONE bit separately */ 1361 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1362 1363 /* address of the NVRAM to read from */ 1364 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1365 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1366 1367 /* issue a read command */ 1368 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1369 1370 /* adjust timeout for emulation/FPGA */ 1371 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1372 if (CHIP_REV_IS_SLOW(bp)) 1373 count *= 100; 1374 1375 /* wait for completion */ 1376 *ret_val = 0; 1377 rc = -EBUSY; 1378 for (i = 0; i < count; i++) { 1379 udelay(5); 1380 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1381 1382 if (val & MCPR_NVM_COMMAND_DONE) { 1383 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1384 /* we read nvram data in cpu order 1385 * but ethtool sees it as an array of bytes 1386 * converting to big-endian will do the work 1387 */ 1388 *ret_val = cpu_to_be32(val); 1389 rc = 0; 1390 break; 1391 } 1392 } 1393 if (rc == -EBUSY) 1394 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1395 "nvram read timeout expired\n"); 1396 return rc; 1397 } 1398 1399 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1400 int buf_size) 1401 { 1402 int rc; 1403 u32 cmd_flags; 1404 __be32 val; 1405 1406 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1407 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1408 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1409 offset, buf_size); 1410 return -EINVAL; 1411 } 1412 1413 if (offset + buf_size > bp->common.flash_size) { 1414 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1415 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1416 offset, buf_size, bp->common.flash_size); 1417 return -EINVAL; 1418 } 1419 1420 /* request access to nvram interface */ 1421 rc = bnx2x_acquire_nvram_lock(bp); 1422 if (rc) 1423 return rc; 1424 1425 /* enable access to nvram interface */ 1426 bnx2x_enable_nvram_access(bp); 1427 1428 /* read the first word(s) */ 1429 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1430 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1431 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1432 memcpy(ret_buf, &val, 4); 1433 1434 /* advance to the next dword */ 1435 offset += sizeof(u32); 1436 ret_buf += sizeof(u32); 1437 buf_size -= sizeof(u32); 1438 cmd_flags = 0; 1439 } 1440 1441 if (rc == 0) { 1442 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1443 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1444 memcpy(ret_buf, &val, 4); 1445 } 1446 1447 /* disable access to nvram interface */ 1448 bnx2x_disable_nvram_access(bp); 1449 bnx2x_release_nvram_lock(bp); 1450 1451 return rc; 1452 } 1453 1454 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 1455 int buf_size) 1456 { 1457 int rc; 1458 1459 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 1460 1461 if (!rc) { 1462 __be32 *be = (__be32 *)buf; 1463 1464 while ((buf_size -= 4) >= 0) 1465 *buf++ = be32_to_cpu(*be++); 1466 } 1467 1468 return rc; 1469 } 1470 1471 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 1472 { 1473 int rc = 1; 1474 u16 pm = 0; 1475 struct net_device *dev = pci_get_drvdata(bp->pdev); 1476 1477 if (bp->pdev->pm_cap) 1478 rc = pci_read_config_word(bp->pdev, 1479 bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 1480 1481 if ((rc && !netif_running(dev)) || 1482 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 1483 return false; 1484 1485 return true; 1486 } 1487 1488 static int bnx2x_get_eeprom(struct net_device *dev, 1489 struct ethtool_eeprom *eeprom, u8 *eebuf) 1490 { 1491 struct bnx2x *bp = netdev_priv(dev); 1492 1493 if (!bnx2x_is_nvm_accessible(bp)) { 1494 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1495 "cannot access eeprom when the interface is down\n"); 1496 return -EAGAIN; 1497 } 1498 1499 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1500 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1501 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1502 eeprom->len, eeprom->len); 1503 1504 /* parameters already validated in ethtool_get_eeprom */ 1505 1506 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1507 } 1508 1509 static int bnx2x_get_module_eeprom(struct net_device *dev, 1510 struct ethtool_eeprom *ee, 1511 u8 *data) 1512 { 1513 struct bnx2x *bp = netdev_priv(dev); 1514 int rc = -EINVAL, phy_idx; 1515 u8 *user_data = data; 1516 unsigned int start_addr = ee->offset, xfer_size = 0; 1517 1518 if (!bnx2x_is_nvm_accessible(bp)) { 1519 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1520 "cannot access eeprom when the interface is down\n"); 1521 return -EAGAIN; 1522 } 1523 1524 phy_idx = bnx2x_get_cur_phy_idx(bp); 1525 1526 /* Read A0 section */ 1527 if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1528 /* Limit transfer size to the A0 section boundary */ 1529 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1530 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1531 else 1532 xfer_size = ee->len; 1533 bnx2x_acquire_phy_lock(bp); 1534 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1535 &bp->link_params, 1536 I2C_DEV_ADDR_A0, 1537 start_addr, 1538 xfer_size, 1539 user_data); 1540 bnx2x_release_phy_lock(bp); 1541 if (rc) { 1542 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1543 1544 return -EINVAL; 1545 } 1546 user_data += xfer_size; 1547 start_addr += xfer_size; 1548 } 1549 1550 /* Read A2 section */ 1551 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1552 (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1553 xfer_size = ee->len - xfer_size; 1554 /* Limit transfer size to the A2 section boundary */ 1555 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1556 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1557 start_addr -= ETH_MODULE_SFF_8079_LEN; 1558 bnx2x_acquire_phy_lock(bp); 1559 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1560 &bp->link_params, 1561 I2C_DEV_ADDR_A2, 1562 start_addr, 1563 xfer_size, 1564 user_data); 1565 bnx2x_release_phy_lock(bp); 1566 if (rc) { 1567 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1568 return -EINVAL; 1569 } 1570 } 1571 return rc; 1572 } 1573 1574 static int bnx2x_get_module_info(struct net_device *dev, 1575 struct ethtool_modinfo *modinfo) 1576 { 1577 struct bnx2x *bp = netdev_priv(dev); 1578 int phy_idx, rc; 1579 u8 sff8472_comp, diag_type; 1580 1581 if (!bnx2x_is_nvm_accessible(bp)) { 1582 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1583 "cannot access eeprom when the interface is down\n"); 1584 return -EAGAIN; 1585 } 1586 phy_idx = bnx2x_get_cur_phy_idx(bp); 1587 bnx2x_acquire_phy_lock(bp); 1588 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1589 &bp->link_params, 1590 I2C_DEV_ADDR_A0, 1591 SFP_EEPROM_SFF_8472_COMP_ADDR, 1592 SFP_EEPROM_SFF_8472_COMP_SIZE, 1593 &sff8472_comp); 1594 bnx2x_release_phy_lock(bp); 1595 if (rc) { 1596 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1597 return -EINVAL; 1598 } 1599 1600 bnx2x_acquire_phy_lock(bp); 1601 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1602 &bp->link_params, 1603 I2C_DEV_ADDR_A0, 1604 SFP_EEPROM_DIAG_TYPE_ADDR, 1605 SFP_EEPROM_DIAG_TYPE_SIZE, 1606 &diag_type); 1607 bnx2x_release_phy_lock(bp); 1608 if (rc) { 1609 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1610 return -EINVAL; 1611 } 1612 1613 if (!sff8472_comp || 1614 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) || 1615 !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) { 1616 modinfo->type = ETH_MODULE_SFF_8079; 1617 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1618 } else { 1619 modinfo->type = ETH_MODULE_SFF_8472; 1620 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1621 } 1622 return 0; 1623 } 1624 1625 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1626 u32 cmd_flags) 1627 { 1628 int count, i, rc; 1629 1630 /* build the command word */ 1631 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1632 1633 /* need to clear DONE bit separately */ 1634 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1635 1636 /* write the data */ 1637 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1638 1639 /* address of the NVRAM to write to */ 1640 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1641 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1642 1643 /* issue the write command */ 1644 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1645 1646 /* adjust timeout for emulation/FPGA */ 1647 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1648 if (CHIP_REV_IS_SLOW(bp)) 1649 count *= 100; 1650 1651 /* wait for completion */ 1652 rc = -EBUSY; 1653 for (i = 0; i < count; i++) { 1654 udelay(5); 1655 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1656 if (val & MCPR_NVM_COMMAND_DONE) { 1657 rc = 0; 1658 break; 1659 } 1660 } 1661 1662 if (rc == -EBUSY) 1663 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1664 "nvram write timeout expired\n"); 1665 return rc; 1666 } 1667 1668 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1669 1670 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1671 int buf_size) 1672 { 1673 int rc; 1674 u32 cmd_flags, align_offset, val; 1675 __be32 val_be; 1676 1677 if (offset + buf_size > bp->common.flash_size) { 1678 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1679 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1680 offset, buf_size, bp->common.flash_size); 1681 return -EINVAL; 1682 } 1683 1684 /* request access to nvram interface */ 1685 rc = bnx2x_acquire_nvram_lock(bp); 1686 if (rc) 1687 return rc; 1688 1689 /* enable access to nvram interface */ 1690 bnx2x_enable_nvram_access(bp); 1691 1692 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1693 align_offset = (offset & ~0x03); 1694 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1695 1696 if (rc == 0) { 1697 /* nvram data is returned as an array of bytes 1698 * convert it back to cpu order 1699 */ 1700 val = be32_to_cpu(val_be); 1701 1702 val &= ~le32_to_cpu((__force __le32) 1703 (0xff << BYTE_OFFSET(offset))); 1704 val |= le32_to_cpu((__force __le32) 1705 (*data_buf << BYTE_OFFSET(offset))); 1706 1707 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1708 cmd_flags); 1709 } 1710 1711 /* disable access to nvram interface */ 1712 bnx2x_disable_nvram_access(bp); 1713 bnx2x_release_nvram_lock(bp); 1714 1715 return rc; 1716 } 1717 1718 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1719 int buf_size) 1720 { 1721 int rc; 1722 u32 cmd_flags; 1723 u32 val; 1724 u32 written_so_far; 1725 1726 if (buf_size == 1) /* ethtool */ 1727 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1728 1729 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1730 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1731 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1732 offset, buf_size); 1733 return -EINVAL; 1734 } 1735 1736 if (offset + buf_size > bp->common.flash_size) { 1737 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1738 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1739 offset, buf_size, bp->common.flash_size); 1740 return -EINVAL; 1741 } 1742 1743 /* request access to nvram interface */ 1744 rc = bnx2x_acquire_nvram_lock(bp); 1745 if (rc) 1746 return rc; 1747 1748 /* enable access to nvram interface */ 1749 bnx2x_enable_nvram_access(bp); 1750 1751 written_so_far = 0; 1752 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1753 while ((written_so_far < buf_size) && (rc == 0)) { 1754 if (written_so_far == (buf_size - sizeof(u32))) 1755 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1756 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1757 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1758 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1759 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1760 1761 memcpy(&val, data_buf, 4); 1762 1763 /* Notice unlike bnx2x_nvram_read_dword() this will not 1764 * change val using be32_to_cpu(), which causes data to flip 1765 * if the eeprom is read and then written back. This is due 1766 * to tools utilizing this functionality that would break 1767 * if this would be resolved. 1768 */ 1769 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1770 1771 /* advance to the next dword */ 1772 offset += sizeof(u32); 1773 data_buf += sizeof(u32); 1774 written_so_far += sizeof(u32); 1775 1776 /* At end of each 4Kb page, release nvram lock to allow MFW 1777 * chance to take it for its own use. 1778 */ 1779 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) && 1780 (written_so_far < buf_size)) { 1781 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1782 "Releasing NVM lock after offset 0x%x\n", 1783 (u32)(offset - sizeof(u32))); 1784 bnx2x_release_nvram_lock(bp); 1785 usleep_range(1000, 2000); 1786 rc = bnx2x_acquire_nvram_lock(bp); 1787 if (rc) 1788 return rc; 1789 } 1790 1791 cmd_flags = 0; 1792 } 1793 1794 /* disable access to nvram interface */ 1795 bnx2x_disable_nvram_access(bp); 1796 bnx2x_release_nvram_lock(bp); 1797 1798 return rc; 1799 } 1800 1801 static int bnx2x_set_eeprom(struct net_device *dev, 1802 struct ethtool_eeprom *eeprom, u8 *eebuf) 1803 { 1804 struct bnx2x *bp = netdev_priv(dev); 1805 int port = BP_PORT(bp); 1806 int rc = 0; 1807 u32 ext_phy_config; 1808 1809 if (!bnx2x_is_nvm_accessible(bp)) { 1810 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1811 "cannot access eeprom when the interface is down\n"); 1812 return -EAGAIN; 1813 } 1814 1815 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1816 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1817 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1818 eeprom->len, eeprom->len); 1819 1820 /* parameters already validated in ethtool_set_eeprom */ 1821 1822 /* PHY eeprom can be accessed only by the PMF */ 1823 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1824 !bp->port.pmf) { 1825 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1826 "wrong magic or interface is not pmf\n"); 1827 return -EINVAL; 1828 } 1829 1830 ext_phy_config = 1831 SHMEM_RD(bp, 1832 dev_info.port_hw_config[port].external_phy_config); 1833 1834 if (eeprom->magic == 0x50485950) { 1835 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1836 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1837 1838 bnx2x_acquire_phy_lock(bp); 1839 rc |= bnx2x_link_reset(&bp->link_params, 1840 &bp->link_vars, 0); 1841 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1842 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1843 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1844 MISC_REGISTERS_GPIO_HIGH, port); 1845 bnx2x_release_phy_lock(bp); 1846 bnx2x_link_report(bp); 1847 1848 } else if (eeprom->magic == 0x50485952) { 1849 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1850 if (bp->state == BNX2X_STATE_OPEN) { 1851 bnx2x_acquire_phy_lock(bp); 1852 rc |= bnx2x_link_reset(&bp->link_params, 1853 &bp->link_vars, 1); 1854 1855 rc |= bnx2x_phy_init(&bp->link_params, 1856 &bp->link_vars); 1857 bnx2x_release_phy_lock(bp); 1858 bnx2x_calc_fc_adv(bp); 1859 } 1860 } else if (eeprom->magic == 0x53985943) { 1861 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1862 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1863 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1864 1865 /* DSP Remove Download Mode */ 1866 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1867 MISC_REGISTERS_GPIO_LOW, port); 1868 1869 bnx2x_acquire_phy_lock(bp); 1870 1871 bnx2x_sfx7101_sp_sw_reset(bp, 1872 &bp->link_params.phy[EXT_PHY1]); 1873 1874 /* wait 0.5 sec to allow it to run */ 1875 msleep(500); 1876 bnx2x_ext_phy_hw_reset(bp, port); 1877 msleep(500); 1878 bnx2x_release_phy_lock(bp); 1879 } 1880 } else 1881 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1882 1883 return rc; 1884 } 1885 1886 static int bnx2x_get_coalesce(struct net_device *dev, 1887 struct ethtool_coalesce *coal) 1888 { 1889 struct bnx2x *bp = netdev_priv(dev); 1890 1891 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1892 1893 coal->rx_coalesce_usecs = bp->rx_ticks; 1894 coal->tx_coalesce_usecs = bp->tx_ticks; 1895 1896 return 0; 1897 } 1898 1899 static int bnx2x_set_coalesce(struct net_device *dev, 1900 struct ethtool_coalesce *coal) 1901 { 1902 struct bnx2x *bp = netdev_priv(dev); 1903 1904 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1905 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1906 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1907 1908 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1909 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1910 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1911 1912 if (netif_running(dev)) 1913 bnx2x_update_coalesce(bp); 1914 1915 return 0; 1916 } 1917 1918 static void bnx2x_get_ringparam(struct net_device *dev, 1919 struct ethtool_ringparam *ering) 1920 { 1921 struct bnx2x *bp = netdev_priv(dev); 1922 1923 ering->rx_max_pending = MAX_RX_AVAIL; 1924 1925 /* If size isn't already set, we give an estimation of the number 1926 * of buffers we'll have. We're neglecting some possible conditions 1927 * [we couldn't know for certain at this point if number of queues 1928 * might shrink] but the number would be correct for the likely 1929 * scenario. 1930 */ 1931 if (bp->rx_ring_size) 1932 ering->rx_pending = bp->rx_ring_size; 1933 else if (BNX2X_NUM_RX_QUEUES(bp)) 1934 ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp); 1935 else 1936 ering->rx_pending = MAX_RX_AVAIL; 1937 1938 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1939 ering->tx_pending = bp->tx_ring_size; 1940 } 1941 1942 static int bnx2x_set_ringparam(struct net_device *dev, 1943 struct ethtool_ringparam *ering) 1944 { 1945 struct bnx2x *bp = netdev_priv(dev); 1946 1947 DP(BNX2X_MSG_ETHTOOL, 1948 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 1949 ering->rx_pending, ering->tx_pending); 1950 1951 if (pci_num_vf(bp->pdev)) { 1952 DP(BNX2X_MSG_IOV, 1953 "VFs are enabled, can not change ring parameters\n"); 1954 return -EPERM; 1955 } 1956 1957 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1958 DP(BNX2X_MSG_ETHTOOL, 1959 "Handling parity error recovery. Try again later\n"); 1960 return -EAGAIN; 1961 } 1962 1963 if ((ering->rx_pending > MAX_RX_AVAIL) || 1964 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1965 MIN_RX_SIZE_TPA)) || 1966 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 1967 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 1968 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1969 return -EINVAL; 1970 } 1971 1972 bp->rx_ring_size = ering->rx_pending; 1973 bp->tx_ring_size = ering->tx_pending; 1974 1975 return bnx2x_reload_if_running(dev); 1976 } 1977 1978 static void bnx2x_get_pauseparam(struct net_device *dev, 1979 struct ethtool_pauseparam *epause) 1980 { 1981 struct bnx2x *bp = netdev_priv(dev); 1982 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1983 int cfg_reg; 1984 1985 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1986 BNX2X_FLOW_CTRL_AUTO); 1987 1988 if (!epause->autoneg) 1989 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1990 else 1991 cfg_reg = bp->link_params.req_fc_auto_adv; 1992 1993 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1994 BNX2X_FLOW_CTRL_RX); 1995 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1996 BNX2X_FLOW_CTRL_TX); 1997 1998 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1999 " autoneg %d rx_pause %d tx_pause %d\n", 2000 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 2001 } 2002 2003 static int bnx2x_set_pauseparam(struct net_device *dev, 2004 struct ethtool_pauseparam *epause) 2005 { 2006 struct bnx2x *bp = netdev_priv(dev); 2007 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2008 if (IS_MF(bp)) 2009 return 0; 2010 2011 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 2012 " autoneg %d rx_pause %d tx_pause %d\n", 2013 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 2014 2015 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 2016 2017 if (epause->rx_pause) 2018 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 2019 2020 if (epause->tx_pause) 2021 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 2022 2023 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 2024 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 2025 2026 if (epause->autoneg) { 2027 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 2028 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 2029 return -EINVAL; 2030 } 2031 2032 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 2033 bp->link_params.req_flow_ctrl[cfg_idx] = 2034 BNX2X_FLOW_CTRL_AUTO; 2035 } 2036 bp->link_params.req_fc_auto_adv = 0; 2037 if (epause->rx_pause) 2038 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 2039 2040 if (epause->tx_pause) 2041 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 2042 2043 if (!bp->link_params.req_fc_auto_adv) 2044 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 2045 } 2046 2047 DP(BNX2X_MSG_ETHTOOL, 2048 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 2049 2050 if (netif_running(dev)) { 2051 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2052 bnx2x_force_link_reset(bp); 2053 bnx2x_link_set(bp); 2054 } 2055 2056 return 0; 2057 } 2058 2059 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 2060 "register_test (offline) ", 2061 "memory_test (offline) ", 2062 "int_loopback_test (offline)", 2063 "ext_loopback_test (offline)", 2064 "nvram_test (online) ", 2065 "interrupt_test (online) ", 2066 "link_test (online) " 2067 }; 2068 2069 enum { 2070 BNX2X_PRI_FLAG_ISCSI, 2071 BNX2X_PRI_FLAG_FCOE, 2072 BNX2X_PRI_FLAG_STORAGE, 2073 BNX2X_PRI_FLAG_LEN, 2074 }; 2075 2076 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 2077 "iSCSI offload support", 2078 "FCoE offload support", 2079 "Storage only interface" 2080 }; 2081 2082 static u32 bnx2x_eee_to_adv(u32 eee_adv) 2083 { 2084 u32 modes = 0; 2085 2086 if (eee_adv & SHMEM_EEE_100M_ADV) 2087 modes |= ADVERTISED_100baseT_Full; 2088 if (eee_adv & SHMEM_EEE_1G_ADV) 2089 modes |= ADVERTISED_1000baseT_Full; 2090 if (eee_adv & SHMEM_EEE_10G_ADV) 2091 modes |= ADVERTISED_10000baseT_Full; 2092 2093 return modes; 2094 } 2095 2096 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2097 { 2098 u32 eee_adv = 0; 2099 if (modes & ADVERTISED_100baseT_Full) 2100 eee_adv |= SHMEM_EEE_100M_ADV; 2101 if (modes & ADVERTISED_1000baseT_Full) 2102 eee_adv |= SHMEM_EEE_1G_ADV; 2103 if (modes & ADVERTISED_10000baseT_Full) 2104 eee_adv |= SHMEM_EEE_10G_ADV; 2105 2106 return eee_adv << shift; 2107 } 2108 2109 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2110 { 2111 struct bnx2x *bp = netdev_priv(dev); 2112 u32 eee_cfg; 2113 2114 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2115 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2116 return -EOPNOTSUPP; 2117 } 2118 2119 eee_cfg = bp->link_vars.eee_status; 2120 2121 edata->supported = 2122 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2123 SHMEM_EEE_SUPPORTED_SHIFT); 2124 2125 edata->advertised = 2126 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2127 SHMEM_EEE_ADV_STATUS_SHIFT); 2128 edata->lp_advertised = 2129 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2130 SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2131 2132 /* SHMEM value is in 16u units --> Convert to 1u units. */ 2133 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2134 2135 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2136 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2137 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2138 2139 return 0; 2140 } 2141 2142 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2143 { 2144 struct bnx2x *bp = netdev_priv(dev); 2145 u32 eee_cfg; 2146 u32 advertised; 2147 2148 if (IS_MF(bp)) 2149 return 0; 2150 2151 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2152 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2153 return -EOPNOTSUPP; 2154 } 2155 2156 eee_cfg = bp->link_vars.eee_status; 2157 2158 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2159 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2160 return -EOPNOTSUPP; 2161 } 2162 2163 advertised = bnx2x_adv_to_eee(edata->advertised, 2164 SHMEM_EEE_ADV_STATUS_SHIFT); 2165 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2166 DP(BNX2X_MSG_ETHTOOL, 2167 "Direct manipulation of EEE advertisement is not supported\n"); 2168 return -EINVAL; 2169 } 2170 2171 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2172 DP(BNX2X_MSG_ETHTOOL, 2173 "Maximal Tx Lpi timer supported is %x(u)\n", 2174 EEE_MODE_TIMER_MASK); 2175 return -EINVAL; 2176 } 2177 if (edata->tx_lpi_enabled && 2178 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2179 DP(BNX2X_MSG_ETHTOOL, 2180 "Minimal Tx Lpi timer supported is %d(u)\n", 2181 EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2182 return -EINVAL; 2183 } 2184 2185 /* All is well; Apply changes*/ 2186 if (edata->eee_enabled) 2187 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2188 else 2189 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2190 2191 if (edata->tx_lpi_enabled) 2192 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2193 else 2194 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2195 2196 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2197 bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2198 EEE_MODE_TIMER_MASK) | 2199 EEE_MODE_OVERRIDE_NVRAM | 2200 EEE_MODE_OUTPUT_TIME; 2201 2202 /* Restart link to propagate changes */ 2203 if (netif_running(dev)) { 2204 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2205 bnx2x_force_link_reset(bp); 2206 bnx2x_link_set(bp); 2207 } 2208 2209 return 0; 2210 } 2211 2212 enum { 2213 BNX2X_CHIP_E1_OFST = 0, 2214 BNX2X_CHIP_E1H_OFST, 2215 BNX2X_CHIP_E2_OFST, 2216 BNX2X_CHIP_E3_OFST, 2217 BNX2X_CHIP_E3B0_OFST, 2218 BNX2X_CHIP_MAX_OFST 2219 }; 2220 2221 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2222 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2223 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2224 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2225 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2226 2227 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2228 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2229 2230 static int bnx2x_test_registers(struct bnx2x *bp) 2231 { 2232 int idx, i, rc = -ENODEV; 2233 u32 wr_val = 0, hw; 2234 int port = BP_PORT(bp); 2235 static const struct { 2236 u32 hw; 2237 u32 offset0; 2238 u32 offset1; 2239 u32 mask; 2240 } reg_tbl[] = { 2241 /* 0 */ { BNX2X_CHIP_MASK_ALL, 2242 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2243 { BNX2X_CHIP_MASK_ALL, 2244 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2245 { BNX2X_CHIP_MASK_E1X, 2246 HC_REG_AGG_INT_0, 4, 0x000003ff }, 2247 { BNX2X_CHIP_MASK_ALL, 2248 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2249 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2250 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2251 { BNX2X_CHIP_MASK_E3B0, 2252 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2253 { BNX2X_CHIP_MASK_ALL, 2254 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2255 { BNX2X_CHIP_MASK_ALL, 2256 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2257 { BNX2X_CHIP_MASK_ALL, 2258 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2259 { BNX2X_CHIP_MASK_ALL, 2260 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2261 /* 10 */ { BNX2X_CHIP_MASK_ALL, 2262 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2263 { BNX2X_CHIP_MASK_ALL, 2264 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2265 { BNX2X_CHIP_MASK_ALL, 2266 QM_REG_CONNNUM_0, 4, 0x000fffff }, 2267 { BNX2X_CHIP_MASK_ALL, 2268 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2269 { BNX2X_CHIP_MASK_ALL, 2270 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2271 { BNX2X_CHIP_MASK_ALL, 2272 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2273 { BNX2X_CHIP_MASK_ALL, 2274 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2275 { BNX2X_CHIP_MASK_ALL, 2276 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2277 { BNX2X_CHIP_MASK_ALL, 2278 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2279 { BNX2X_CHIP_MASK_ALL, 2280 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2281 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2282 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2283 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2284 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2285 { BNX2X_CHIP_MASK_ALL, 2286 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2287 { BNX2X_CHIP_MASK_ALL, 2288 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2289 { BNX2X_CHIP_MASK_ALL, 2290 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2291 { BNX2X_CHIP_MASK_ALL, 2292 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2293 { BNX2X_CHIP_MASK_ALL, 2294 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2295 { BNX2X_CHIP_MASK_ALL, 2296 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2297 { BNX2X_CHIP_MASK_ALL, 2298 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2299 { BNX2X_CHIP_MASK_ALL, 2300 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2301 /* 30 */ { BNX2X_CHIP_MASK_ALL, 2302 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2303 { BNX2X_CHIP_MASK_ALL, 2304 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2305 { BNX2X_CHIP_MASK_ALL, 2306 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2307 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2308 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2309 { BNX2X_CHIP_MASK_ALL, 2310 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2311 { BNX2X_CHIP_MASK_ALL, 2312 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2313 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2314 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2315 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2316 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2317 2318 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2319 }; 2320 2321 if (!bnx2x_is_nvm_accessible(bp)) { 2322 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2323 "cannot access eeprom when the interface is down\n"); 2324 return rc; 2325 } 2326 2327 if (CHIP_IS_E1(bp)) 2328 hw = BNX2X_CHIP_MASK_E1; 2329 else if (CHIP_IS_E1H(bp)) 2330 hw = BNX2X_CHIP_MASK_E1H; 2331 else if (CHIP_IS_E2(bp)) 2332 hw = BNX2X_CHIP_MASK_E2; 2333 else if (CHIP_IS_E3B0(bp)) 2334 hw = BNX2X_CHIP_MASK_E3B0; 2335 else /* e3 A0 */ 2336 hw = BNX2X_CHIP_MASK_E3; 2337 2338 /* Repeat the test twice: 2339 * First by writing 0x00000000, second by writing 0xffffffff 2340 */ 2341 for (idx = 0; idx < 2; idx++) { 2342 2343 switch (idx) { 2344 case 0: 2345 wr_val = 0; 2346 break; 2347 case 1: 2348 wr_val = 0xffffffff; 2349 break; 2350 } 2351 2352 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2353 u32 offset, mask, save_val, val; 2354 if (!(hw & reg_tbl[i].hw)) 2355 continue; 2356 2357 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2358 mask = reg_tbl[i].mask; 2359 2360 save_val = REG_RD(bp, offset); 2361 2362 REG_WR(bp, offset, wr_val & mask); 2363 2364 val = REG_RD(bp, offset); 2365 2366 /* Restore the original register's value */ 2367 REG_WR(bp, offset, save_val); 2368 2369 /* verify value is as expected */ 2370 if ((val & mask) != (wr_val & mask)) { 2371 DP(BNX2X_MSG_ETHTOOL, 2372 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2373 offset, val, wr_val, mask); 2374 goto test_reg_exit; 2375 } 2376 } 2377 } 2378 2379 rc = 0; 2380 2381 test_reg_exit: 2382 return rc; 2383 } 2384 2385 static int bnx2x_test_memory(struct bnx2x *bp) 2386 { 2387 int i, j, rc = -ENODEV; 2388 u32 val, index; 2389 static const struct { 2390 u32 offset; 2391 int size; 2392 } mem_tbl[] = { 2393 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2394 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2395 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2396 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2397 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2398 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2399 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2400 2401 { 0xffffffff, 0 } 2402 }; 2403 2404 static const struct { 2405 char *name; 2406 u32 offset; 2407 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2408 } prty_tbl[] = { 2409 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2410 {0x3ffc0, 0, 0, 0} }, 2411 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2412 {0x2, 0x2, 0, 0} }, 2413 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2414 {0, 0, 0, 0} }, 2415 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2416 {0x3ffc0, 0, 0, 0} }, 2417 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2418 {0x3ffc0, 0, 0, 0} }, 2419 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2420 {0x3ffc1, 0, 0, 0} }, 2421 2422 { NULL, 0xffffffff, {0, 0, 0, 0} } 2423 }; 2424 2425 if (!bnx2x_is_nvm_accessible(bp)) { 2426 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2427 "cannot access eeprom when the interface is down\n"); 2428 return rc; 2429 } 2430 2431 if (CHIP_IS_E1(bp)) 2432 index = BNX2X_CHIP_E1_OFST; 2433 else if (CHIP_IS_E1H(bp)) 2434 index = BNX2X_CHIP_E1H_OFST; 2435 else if (CHIP_IS_E2(bp)) 2436 index = BNX2X_CHIP_E2_OFST; 2437 else /* e3 */ 2438 index = BNX2X_CHIP_E3_OFST; 2439 2440 /* pre-Check the parity status */ 2441 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2442 val = REG_RD(bp, prty_tbl[i].offset); 2443 if (val & ~(prty_tbl[i].hw_mask[index])) { 2444 DP(BNX2X_MSG_ETHTOOL, 2445 "%s is 0x%x\n", prty_tbl[i].name, val); 2446 goto test_mem_exit; 2447 } 2448 } 2449 2450 /* Go through all the memories */ 2451 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2452 for (j = 0; j < mem_tbl[i].size; j++) 2453 REG_RD(bp, mem_tbl[i].offset + j*4); 2454 2455 /* Check the parity status */ 2456 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2457 val = REG_RD(bp, prty_tbl[i].offset); 2458 if (val & ~(prty_tbl[i].hw_mask[index])) { 2459 DP(BNX2X_MSG_ETHTOOL, 2460 "%s is 0x%x\n", prty_tbl[i].name, val); 2461 goto test_mem_exit; 2462 } 2463 } 2464 2465 rc = 0; 2466 2467 test_mem_exit: 2468 return rc; 2469 } 2470 2471 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2472 { 2473 int cnt = 1400; 2474 2475 if (link_up) { 2476 while (bnx2x_link_test(bp, is_serdes) && cnt--) 2477 msleep(20); 2478 2479 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 2480 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 2481 2482 cnt = 1400; 2483 while (!bp->link_vars.link_up && cnt--) 2484 msleep(20); 2485 2486 if (cnt <= 0 && !bp->link_vars.link_up) 2487 DP(BNX2X_MSG_ETHTOOL, 2488 "Timeout waiting for link init\n"); 2489 } 2490 } 2491 2492 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2493 { 2494 unsigned int pkt_size, num_pkts, i; 2495 struct sk_buff *skb; 2496 unsigned char *packet; 2497 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2498 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 2499 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2500 u16 tx_start_idx, tx_idx; 2501 u16 rx_start_idx, rx_idx; 2502 u16 pkt_prod, bd_prod; 2503 struct sw_tx_bd *tx_buf; 2504 struct eth_tx_start_bd *tx_start_bd; 2505 dma_addr_t mapping; 2506 union eth_rx_cqe *cqe; 2507 u8 cqe_fp_flags, cqe_fp_type; 2508 struct sw_rx_bd *rx_buf; 2509 u16 len; 2510 int rc = -ENODEV; 2511 u8 *data; 2512 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 2513 txdata->txq_index); 2514 2515 /* check the loopback mode */ 2516 switch (loopback_mode) { 2517 case BNX2X_PHY_LOOPBACK: 2518 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 2519 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2520 return -EINVAL; 2521 } 2522 break; 2523 case BNX2X_MAC_LOOPBACK: 2524 if (CHIP_IS_E3(bp)) { 2525 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2526 if (bp->port.supported[cfg_idx] & 2527 (SUPPORTED_10000baseT_Full | 2528 SUPPORTED_20000baseMLD2_Full | 2529 SUPPORTED_20000baseKR2_Full)) 2530 bp->link_params.loopback_mode = LOOPBACK_XMAC; 2531 else 2532 bp->link_params.loopback_mode = LOOPBACK_UMAC; 2533 } else 2534 bp->link_params.loopback_mode = LOOPBACK_BMAC; 2535 2536 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2537 break; 2538 case BNX2X_EXT_LOOPBACK: 2539 if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 2540 DP(BNX2X_MSG_ETHTOOL, 2541 "Can't configure external loopback\n"); 2542 return -EINVAL; 2543 } 2544 break; 2545 default: 2546 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2547 return -EINVAL; 2548 } 2549 2550 /* prepare the loopback packet */ 2551 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2552 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2553 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2554 if (!skb) { 2555 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2556 rc = -ENOMEM; 2557 goto test_loopback_exit; 2558 } 2559 packet = skb_put(skb, pkt_size); 2560 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2561 eth_zero_addr(packet + ETH_ALEN); 2562 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2563 for (i = ETH_HLEN; i < pkt_size; i++) 2564 packet[i] = (unsigned char) (i & 0xff); 2565 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2566 skb_headlen(skb), DMA_TO_DEVICE); 2567 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2568 rc = -ENOMEM; 2569 dev_kfree_skb(skb); 2570 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2571 goto test_loopback_exit; 2572 } 2573 2574 /* send the loopback packet */ 2575 num_pkts = 0; 2576 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2577 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2578 2579 netdev_tx_sent_queue(txq, skb->len); 2580 2581 pkt_prod = txdata->tx_pkt_prod++; 2582 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2583 tx_buf->first_bd = txdata->tx_bd_prod; 2584 tx_buf->skb = skb; 2585 tx_buf->flags = 0; 2586 2587 bd_prod = TX_BD(txdata->tx_bd_prod); 2588 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2589 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2590 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2591 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2592 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2593 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2594 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2595 SET_FLAG(tx_start_bd->general_data, 2596 ETH_TX_START_BD_HDR_NBDS, 2597 1); 2598 SET_FLAG(tx_start_bd->general_data, 2599 ETH_TX_START_BD_PARSE_NBDS, 2600 0); 2601 2602 /* turn on parsing and get a BD */ 2603 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2604 2605 if (CHIP_IS_E1x(bp)) { 2606 u16 global_data = 0; 2607 struct eth_tx_parse_bd_e1x *pbd_e1x = 2608 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2609 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2610 SET_FLAG(global_data, 2611 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2612 pbd_e1x->global_data = cpu_to_le16(global_data); 2613 } else { 2614 u32 parsing_data = 0; 2615 struct eth_tx_parse_bd_e2 *pbd_e2 = 2616 &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2617 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2618 SET_FLAG(parsing_data, 2619 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2620 pbd_e2->parsing_data = cpu_to_le32(parsing_data); 2621 } 2622 wmb(); 2623 2624 txdata->tx_db.data.prod += 2; 2625 /* make sure descriptor update is observed by the HW */ 2626 wmb(); 2627 DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw); 2628 2629 barrier(); 2630 2631 num_pkts++; 2632 txdata->tx_bd_prod += 2; /* start + pbd */ 2633 2634 udelay(100); 2635 2636 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2637 if (tx_idx != tx_start_idx + num_pkts) 2638 goto test_loopback_exit; 2639 2640 /* Unlike HC IGU won't generate an interrupt for status block 2641 * updates that have been performed while interrupts were 2642 * disabled. 2643 */ 2644 if (bp->common.int_block == INT_BLOCK_IGU) { 2645 /* Disable local BHes to prevent a dead-lock situation between 2646 * sch_direct_xmit() and bnx2x_run_loopback() (calling 2647 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2648 */ 2649 local_bh_disable(); 2650 bnx2x_tx_int(bp, txdata); 2651 local_bh_enable(); 2652 } 2653 2654 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2655 if (rx_idx != rx_start_idx + num_pkts) 2656 goto test_loopback_exit; 2657 2658 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2659 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2660 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2661 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2662 goto test_loopback_rx_exit; 2663 2664 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2665 if (len != pkt_size) 2666 goto test_loopback_rx_exit; 2667 2668 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2669 dma_sync_single_for_cpu(&bp->pdev->dev, 2670 dma_unmap_addr(rx_buf, mapping), 2671 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2672 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2673 for (i = ETH_HLEN; i < pkt_size; i++) 2674 if (*(data + i) != (unsigned char) (i & 0xff)) 2675 goto test_loopback_rx_exit; 2676 2677 rc = 0; 2678 2679 test_loopback_rx_exit: 2680 2681 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2682 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2683 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2684 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2685 2686 /* Update producers */ 2687 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2688 fp_rx->rx_sge_prod); 2689 2690 test_loopback_exit: 2691 bp->link_params.loopback_mode = LOOPBACK_NONE; 2692 2693 return rc; 2694 } 2695 2696 static int bnx2x_test_loopback(struct bnx2x *bp) 2697 { 2698 int rc = 0, res; 2699 2700 if (BP_NOMCP(bp)) 2701 return rc; 2702 2703 if (!netif_running(bp->dev)) 2704 return BNX2X_LOOPBACK_FAILED; 2705 2706 bnx2x_netif_stop(bp, 1); 2707 bnx2x_acquire_phy_lock(bp); 2708 2709 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2710 if (res) { 2711 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2712 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2713 } 2714 2715 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2716 if (res) { 2717 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2718 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2719 } 2720 2721 bnx2x_release_phy_lock(bp); 2722 bnx2x_netif_start(bp); 2723 2724 return rc; 2725 } 2726 2727 static int bnx2x_test_ext_loopback(struct bnx2x *bp) 2728 { 2729 int rc; 2730 u8 is_serdes = 2731 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2732 2733 if (BP_NOMCP(bp)) 2734 return -ENODEV; 2735 2736 if (!netif_running(bp->dev)) 2737 return BNX2X_EXT_LOOPBACK_FAILED; 2738 2739 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2740 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 2741 if (rc) { 2742 DP(BNX2X_MSG_ETHTOOL, 2743 "Can't perform self-test, nic_load (for external lb) failed\n"); 2744 return -ENODEV; 2745 } 2746 bnx2x_wait_for_link(bp, 1, is_serdes); 2747 2748 bnx2x_netif_stop(bp, 1); 2749 2750 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 2751 if (rc) 2752 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 2753 2754 bnx2x_netif_start(bp); 2755 2756 return rc; 2757 } 2758 2759 struct code_entry { 2760 u32 sram_start_addr; 2761 u32 code_attribute; 2762 #define CODE_IMAGE_TYPE_MASK 0xf0800003 2763 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2764 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2765 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2766 u32 nvm_start_addr; 2767 }; 2768 2769 #define CODE_ENTRY_MAX 16 2770 #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2771 #define MAX_IMAGES_IN_EXTENDED_DIR 64 2772 #define NVRAM_DIR_OFFSET 0x14 2773 2774 #define EXTENDED_DIR_EXISTS(code) \ 2775 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2776 (code & CODE_IMAGE_LENGTH_MASK) != 0) 2777 2778 #define CRC32_RESIDUAL 0xdebb20e3 2779 #define CRC_BUFF_SIZE 256 2780 2781 static int bnx2x_nvram_crc(struct bnx2x *bp, 2782 int offset, 2783 int size, 2784 u8 *buff) 2785 { 2786 u32 crc = ~0; 2787 int rc = 0, done = 0; 2788 2789 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2790 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2791 2792 while (done < size) { 2793 int count = min_t(int, size - done, CRC_BUFF_SIZE); 2794 2795 rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2796 2797 if (rc) 2798 return rc; 2799 2800 crc = crc32_le(crc, buff, count); 2801 done += count; 2802 } 2803 2804 if (crc != CRC32_RESIDUAL) 2805 rc = -EINVAL; 2806 2807 return rc; 2808 } 2809 2810 static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2811 struct code_entry *entry, 2812 u8 *buff) 2813 { 2814 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2815 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2816 int rc; 2817 2818 /* Zero-length images and AFEX profiles do not have CRC */ 2819 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2820 return 0; 2821 2822 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2823 if (rc) 2824 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2825 "image %x has failed crc test (rc %d)\n", type, rc); 2826 2827 return rc; 2828 } 2829 2830 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2831 { 2832 int rc; 2833 struct code_entry entry; 2834 2835 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2836 if (rc) 2837 return rc; 2838 2839 return bnx2x_test_nvram_dir(bp, &entry, buff); 2840 } 2841 2842 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2843 { 2844 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2845 struct code_entry entry; 2846 int i; 2847 2848 rc = bnx2x_nvram_read32(bp, 2849 dir_offset + 2850 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2851 (u32 *)&entry, sizeof(entry)); 2852 if (rc) 2853 return rc; 2854 2855 if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2856 return 0; 2857 2858 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2859 &cnt, sizeof(u32)); 2860 if (rc) 2861 return rc; 2862 2863 dir_offset = entry.nvm_start_addr + 8; 2864 2865 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2866 rc = bnx2x_test_dir_entry(bp, dir_offset + 2867 sizeof(struct code_entry) * i, 2868 buff); 2869 if (rc) 2870 return rc; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2877 { 2878 u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2879 int i; 2880 2881 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2882 2883 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2884 rc = bnx2x_test_dir_entry(bp, dir_offset + 2885 sizeof(struct code_entry) * i, 2886 buff); 2887 if (rc) 2888 return rc; 2889 } 2890 2891 return bnx2x_test_nvram_ext_dirs(bp, buff); 2892 } 2893 2894 struct crc_pair { 2895 int offset; 2896 int size; 2897 }; 2898 2899 static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2900 const struct crc_pair *nvram_tbl, u8 *buf) 2901 { 2902 int i; 2903 2904 for (i = 0; nvram_tbl[i].size; i++) { 2905 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2906 nvram_tbl[i].size, buf); 2907 if (rc) { 2908 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2909 "nvram_tbl[%d] has failed crc test (rc %d)\n", 2910 i, rc); 2911 return rc; 2912 } 2913 } 2914 2915 return 0; 2916 } 2917 2918 static int bnx2x_test_nvram(struct bnx2x *bp) 2919 { 2920 static const struct crc_pair nvram_tbl[] = { 2921 { 0, 0x14 }, /* bootstrap */ 2922 { 0x14, 0xec }, /* dir */ 2923 { 0x100, 0x350 }, /* manuf_info */ 2924 { 0x450, 0xf0 }, /* feature_info */ 2925 { 0x640, 0x64 }, /* upgrade_key_info */ 2926 { 0x708, 0x70 }, /* manuf_key_info */ 2927 { 0, 0 } 2928 }; 2929 static const struct crc_pair nvram_tbl2[] = { 2930 { 0x7e8, 0x350 }, /* manuf_info2 */ 2931 { 0xb38, 0xf0 }, /* feature_info */ 2932 { 0, 0 } 2933 }; 2934 2935 u8 *buf; 2936 int rc; 2937 u32 magic; 2938 2939 if (BP_NOMCP(bp)) 2940 return 0; 2941 2942 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2943 if (!buf) { 2944 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2945 rc = -ENOMEM; 2946 goto test_nvram_exit; 2947 } 2948 2949 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2950 if (rc) { 2951 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2952 "magic value read (rc %d)\n", rc); 2953 goto test_nvram_exit; 2954 } 2955 2956 if (magic != 0x669955aa) { 2957 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2958 "wrong magic value (0x%08x)\n", magic); 2959 rc = -ENODEV; 2960 goto test_nvram_exit; 2961 } 2962 2963 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2964 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2965 if (rc) 2966 goto test_nvram_exit; 2967 2968 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2969 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2970 SHARED_HW_CFG_HIDE_PORT1; 2971 2972 if (!hide) { 2973 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2974 "Port 1 CRC test-set\n"); 2975 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2976 if (rc) 2977 goto test_nvram_exit; 2978 } 2979 } 2980 2981 rc = bnx2x_test_nvram_dirs(bp, buf); 2982 2983 test_nvram_exit: 2984 kfree(buf); 2985 return rc; 2986 } 2987 2988 /* Send an EMPTY ramrod on the first queue */ 2989 static int bnx2x_test_intr(struct bnx2x *bp) 2990 { 2991 struct bnx2x_queue_state_params params = {NULL}; 2992 2993 if (!netif_running(bp->dev)) { 2994 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2995 "cannot access eeprom when the interface is down\n"); 2996 return -ENODEV; 2997 } 2998 2999 params.q_obj = &bp->sp_objs->q_obj; 3000 params.cmd = BNX2X_Q_CMD_EMPTY; 3001 3002 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 3003 3004 return bnx2x_queue_state_change(bp, ¶ms); 3005 } 3006 3007 static void bnx2x_self_test(struct net_device *dev, 3008 struct ethtool_test *etest, u64 *buf) 3009 { 3010 struct bnx2x *bp = netdev_priv(dev); 3011 u8 is_serdes, link_up; 3012 int rc, cnt = 0; 3013 3014 if (pci_num_vf(bp->pdev)) { 3015 DP(BNX2X_MSG_IOV, 3016 "VFs are enabled, can not perform self test\n"); 3017 return; 3018 } 3019 3020 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 3021 netdev_err(bp->dev, 3022 "Handling parity error recovery. Try again later\n"); 3023 etest->flags |= ETH_TEST_FL_FAILED; 3024 return; 3025 } 3026 3027 DP(BNX2X_MSG_ETHTOOL, 3028 "Self-test command parameters: offline = %d, external_lb = %d\n", 3029 (etest->flags & ETH_TEST_FL_OFFLINE), 3030 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 3031 3032 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 3033 3034 if (bnx2x_test_nvram(bp) != 0) { 3035 if (!IS_MF(bp)) 3036 buf[4] = 1; 3037 else 3038 buf[0] = 1; 3039 etest->flags |= ETH_TEST_FL_FAILED; 3040 } 3041 3042 if (!netif_running(dev)) { 3043 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 3044 return; 3045 } 3046 3047 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 3048 link_up = bp->link_vars.link_up; 3049 /* offline tests are not supported in MF mode */ 3050 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 3051 int port = BP_PORT(bp); 3052 u32 val; 3053 3054 /* save current value of input enable for TX port IF */ 3055 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 3056 /* disable input for TX port IF */ 3057 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 3058 3059 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3060 rc = bnx2x_nic_load(bp, LOAD_DIAG); 3061 if (rc) { 3062 etest->flags |= ETH_TEST_FL_FAILED; 3063 DP(BNX2X_MSG_ETHTOOL, 3064 "Can't perform self-test, nic_load (for offline) failed\n"); 3065 return; 3066 } 3067 3068 /* wait until link state is restored */ 3069 bnx2x_wait_for_link(bp, 1, is_serdes); 3070 3071 if (bnx2x_test_registers(bp) != 0) { 3072 buf[0] = 1; 3073 etest->flags |= ETH_TEST_FL_FAILED; 3074 } 3075 if (bnx2x_test_memory(bp) != 0) { 3076 buf[1] = 1; 3077 etest->flags |= ETH_TEST_FL_FAILED; 3078 } 3079 3080 buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3081 if (buf[2] != 0) 3082 etest->flags |= ETH_TEST_FL_FAILED; 3083 3084 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 3085 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 3086 if (buf[3] != 0) 3087 etest->flags |= ETH_TEST_FL_FAILED; 3088 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3089 } 3090 3091 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3092 3093 /* restore input for TX port IF */ 3094 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3095 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3096 if (rc) { 3097 etest->flags |= ETH_TEST_FL_FAILED; 3098 DP(BNX2X_MSG_ETHTOOL, 3099 "Can't perform self-test, nic_load (for online) failed\n"); 3100 return; 3101 } 3102 /* wait until link state is restored */ 3103 bnx2x_wait_for_link(bp, link_up, is_serdes); 3104 } 3105 3106 if (bnx2x_test_intr(bp) != 0) { 3107 if (!IS_MF(bp)) 3108 buf[5] = 1; 3109 else 3110 buf[1] = 1; 3111 etest->flags |= ETH_TEST_FL_FAILED; 3112 } 3113 3114 if (link_up) { 3115 cnt = 100; 3116 while (bnx2x_link_test(bp, is_serdes) && --cnt) 3117 msleep(20); 3118 } 3119 3120 if (!cnt) { 3121 if (!IS_MF(bp)) 3122 buf[6] = 1; 3123 else 3124 buf[2] = 1; 3125 etest->flags |= ETH_TEST_FL_FAILED; 3126 } 3127 } 3128 3129 #define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat) 3130 #define HIDE_PORT_STAT(bp) IS_VF(bp) 3131 3132 /* ethtool statistics are displayed for all regular ethernet queues and the 3133 * fcoe L2 queue if not disabled 3134 */ 3135 static int bnx2x_num_stat_queues(struct bnx2x *bp) 3136 { 3137 return BNX2X_NUM_ETH_QUEUES(bp); 3138 } 3139 3140 static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3141 { 3142 struct bnx2x *bp = netdev_priv(dev); 3143 int i, num_strings = 0; 3144 3145 switch (stringset) { 3146 case ETH_SS_STATS: 3147 if (is_multi(bp)) { 3148 num_strings = bnx2x_num_stat_queues(bp) * 3149 BNX2X_NUM_Q_STATS; 3150 } else 3151 num_strings = 0; 3152 if (HIDE_PORT_STAT(bp)) { 3153 for (i = 0; i < BNX2X_NUM_STATS; i++) 3154 if (!IS_PORT_STAT(i)) 3155 num_strings++; 3156 } else 3157 num_strings += BNX2X_NUM_STATS; 3158 3159 return num_strings; 3160 3161 case ETH_SS_TEST: 3162 return BNX2X_NUM_TESTS(bp); 3163 3164 case ETH_SS_PRIV_FLAGS: 3165 return BNX2X_PRI_FLAG_LEN; 3166 3167 default: 3168 return -EINVAL; 3169 } 3170 } 3171 3172 static u32 bnx2x_get_private_flags(struct net_device *dev) 3173 { 3174 struct bnx2x *bp = netdev_priv(dev); 3175 u32 flags = 0; 3176 3177 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 3178 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 3179 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 3180 3181 return flags; 3182 } 3183 3184 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3185 { 3186 struct bnx2x *bp = netdev_priv(dev); 3187 int i, j, k, start; 3188 char queue_name[MAX_QUEUE_NAME_LEN+1]; 3189 3190 switch (stringset) { 3191 case ETH_SS_STATS: 3192 k = 0; 3193 if (is_multi(bp)) { 3194 for_each_eth_queue(bp, i) { 3195 memset(queue_name, 0, sizeof(queue_name)); 3196 snprintf(queue_name, sizeof(queue_name), 3197 "%d", i); 3198 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3199 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3200 ETH_GSTRING_LEN, 3201 bnx2x_q_stats_arr[j].string, 3202 queue_name); 3203 k += BNX2X_NUM_Q_STATS; 3204 } 3205 } 3206 3207 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3208 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3209 continue; 3210 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3211 bnx2x_stats_arr[i].string); 3212 j++; 3213 } 3214 3215 break; 3216 3217 case ETH_SS_TEST: 3218 /* First 4 tests cannot be done in MF mode */ 3219 if (!IS_MF(bp)) 3220 start = 0; 3221 else 3222 start = 4; 3223 memcpy(buf, bnx2x_tests_str_arr + start, 3224 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 3225 break; 3226 3227 case ETH_SS_PRIV_FLAGS: 3228 memcpy(buf, bnx2x_private_arr, 3229 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 3230 break; 3231 } 3232 } 3233 3234 static void bnx2x_get_ethtool_stats(struct net_device *dev, 3235 struct ethtool_stats *stats, u64 *buf) 3236 { 3237 struct bnx2x *bp = netdev_priv(dev); 3238 u32 *hw_stats, *offset; 3239 int i, j, k = 0; 3240 3241 if (is_multi(bp)) { 3242 for_each_eth_queue(bp, i) { 3243 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3244 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3245 if (bnx2x_q_stats_arr[j].size == 0) { 3246 /* skip this counter */ 3247 buf[k + j] = 0; 3248 continue; 3249 } 3250 offset = (hw_stats + 3251 bnx2x_q_stats_arr[j].offset); 3252 if (bnx2x_q_stats_arr[j].size == 4) { 3253 /* 4-byte counter */ 3254 buf[k + j] = (u64) *offset; 3255 continue; 3256 } 3257 /* 8-byte counter */ 3258 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3259 } 3260 k += BNX2X_NUM_Q_STATS; 3261 } 3262 } 3263 3264 hw_stats = (u32 *)&bp->eth_stats; 3265 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3266 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3267 continue; 3268 if (bnx2x_stats_arr[i].size == 0) { 3269 /* skip this counter */ 3270 buf[k + j] = 0; 3271 j++; 3272 continue; 3273 } 3274 offset = (hw_stats + bnx2x_stats_arr[i].offset); 3275 if (bnx2x_stats_arr[i].size == 4) { 3276 /* 4-byte counter */ 3277 buf[k + j] = (u64) *offset; 3278 j++; 3279 continue; 3280 } 3281 /* 8-byte counter */ 3282 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3283 j++; 3284 } 3285 } 3286 3287 static int bnx2x_set_phys_id(struct net_device *dev, 3288 enum ethtool_phys_id_state state) 3289 { 3290 struct bnx2x *bp = netdev_priv(dev); 3291 3292 if (!bnx2x_is_nvm_accessible(bp)) { 3293 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 3294 "cannot access eeprom when the interface is down\n"); 3295 return -EAGAIN; 3296 } 3297 3298 switch (state) { 3299 case ETHTOOL_ID_ACTIVE: 3300 return 1; /* cycle on/off once per second */ 3301 3302 case ETHTOOL_ID_ON: 3303 bnx2x_acquire_phy_lock(bp); 3304 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3305 LED_MODE_ON, SPEED_1000); 3306 bnx2x_release_phy_lock(bp); 3307 break; 3308 3309 case ETHTOOL_ID_OFF: 3310 bnx2x_acquire_phy_lock(bp); 3311 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3312 LED_MODE_FRONT_PANEL_OFF, 0); 3313 bnx2x_release_phy_lock(bp); 3314 break; 3315 3316 case ETHTOOL_ID_INACTIVE: 3317 bnx2x_acquire_phy_lock(bp); 3318 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3319 LED_MODE_OPER, 3320 bp->link_vars.line_speed); 3321 bnx2x_release_phy_lock(bp); 3322 } 3323 3324 return 0; 3325 } 3326 3327 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3328 { 3329 switch (info->flow_type) { 3330 case TCP_V4_FLOW: 3331 case TCP_V6_FLOW: 3332 info->data = RXH_IP_SRC | RXH_IP_DST | 3333 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3334 break; 3335 case UDP_V4_FLOW: 3336 if (bp->rss_conf_obj.udp_rss_v4) 3337 info->data = RXH_IP_SRC | RXH_IP_DST | 3338 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3339 else 3340 info->data = RXH_IP_SRC | RXH_IP_DST; 3341 break; 3342 case UDP_V6_FLOW: 3343 if (bp->rss_conf_obj.udp_rss_v6) 3344 info->data = RXH_IP_SRC | RXH_IP_DST | 3345 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3346 else 3347 info->data = RXH_IP_SRC | RXH_IP_DST; 3348 break; 3349 case IPV4_FLOW: 3350 case IPV6_FLOW: 3351 info->data = RXH_IP_SRC | RXH_IP_DST; 3352 break; 3353 default: 3354 info->data = 0; 3355 break; 3356 } 3357 3358 return 0; 3359 } 3360 3361 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3362 u32 *rules __always_unused) 3363 { 3364 struct bnx2x *bp = netdev_priv(dev); 3365 3366 switch (info->cmd) { 3367 case ETHTOOL_GRXRINGS: 3368 info->data = BNX2X_NUM_ETH_QUEUES(bp); 3369 return 0; 3370 case ETHTOOL_GRXFH: 3371 return bnx2x_get_rss_flags(bp, info); 3372 default: 3373 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3374 return -EOPNOTSUPP; 3375 } 3376 } 3377 3378 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3379 { 3380 int udp_rss_requested; 3381 3382 DP(BNX2X_MSG_ETHTOOL, 3383 "Set rss flags command parameters: flow type = %d, data = %llu\n", 3384 info->flow_type, info->data); 3385 3386 switch (info->flow_type) { 3387 case TCP_V4_FLOW: 3388 case TCP_V6_FLOW: 3389 /* For TCP only 4-tupple hash is supported */ 3390 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 3391 RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 3392 DP(BNX2X_MSG_ETHTOOL, 3393 "Command parameters not supported\n"); 3394 return -EINVAL; 3395 } 3396 return 0; 3397 3398 case UDP_V4_FLOW: 3399 case UDP_V6_FLOW: 3400 /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 3401 if (info->data == (RXH_IP_SRC | RXH_IP_DST | 3402 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3403 udp_rss_requested = 1; 3404 else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 3405 udp_rss_requested = 0; 3406 else 3407 return -EINVAL; 3408 3409 if (CHIP_IS_E1x(bp) && udp_rss_requested) { 3410 DP(BNX2X_MSG_ETHTOOL, 3411 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n"); 3412 return -EINVAL; 3413 } 3414 3415 if ((info->flow_type == UDP_V4_FLOW) && 3416 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 3417 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 3418 DP(BNX2X_MSG_ETHTOOL, 3419 "rss re-configured, UDP 4-tupple %s\n", 3420 udp_rss_requested ? "enabled" : "disabled"); 3421 if (bp->state == BNX2X_STATE_OPEN) 3422 return bnx2x_rss(bp, &bp->rss_conf_obj, false, 3423 true); 3424 } else if ((info->flow_type == UDP_V6_FLOW) && 3425 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 3426 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 3427 DP(BNX2X_MSG_ETHTOOL, 3428 "rss re-configured, UDP 4-tupple %s\n", 3429 udp_rss_requested ? "enabled" : "disabled"); 3430 if (bp->state == BNX2X_STATE_OPEN) 3431 return bnx2x_rss(bp, &bp->rss_conf_obj, false, 3432 true); 3433 } 3434 return 0; 3435 3436 case IPV4_FLOW: 3437 case IPV6_FLOW: 3438 /* For IP only 2-tupple hash is supported */ 3439 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 3440 DP(BNX2X_MSG_ETHTOOL, 3441 "Command parameters not supported\n"); 3442 return -EINVAL; 3443 } 3444 return 0; 3445 3446 case SCTP_V4_FLOW: 3447 case AH_ESP_V4_FLOW: 3448 case AH_V4_FLOW: 3449 case ESP_V4_FLOW: 3450 case SCTP_V6_FLOW: 3451 case AH_ESP_V6_FLOW: 3452 case AH_V6_FLOW: 3453 case ESP_V6_FLOW: 3454 case IP_USER_FLOW: 3455 case ETHER_FLOW: 3456 /* RSS is not supported for these protocols */ 3457 if (info->data) { 3458 DP(BNX2X_MSG_ETHTOOL, 3459 "Command parameters not supported\n"); 3460 return -EINVAL; 3461 } 3462 return 0; 3463 3464 default: 3465 return -EINVAL; 3466 } 3467 } 3468 3469 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 3470 { 3471 struct bnx2x *bp = netdev_priv(dev); 3472 3473 switch (info->cmd) { 3474 case ETHTOOL_SRXFH: 3475 return bnx2x_set_rss_flags(bp, info); 3476 default: 3477 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3478 return -EOPNOTSUPP; 3479 } 3480 } 3481 3482 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3483 { 3484 return T_ETH_INDIRECTION_TABLE_SIZE; 3485 } 3486 3487 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3488 u8 *hfunc) 3489 { 3490 struct bnx2x *bp = netdev_priv(dev); 3491 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3492 size_t i; 3493 3494 if (hfunc) 3495 *hfunc = ETH_RSS_HASH_TOP; 3496 if (!indir) 3497 return 0; 3498 3499 /* Get the current configuration of the RSS indirection table */ 3500 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3501 3502 /* 3503 * We can't use a memcpy() as an internal storage of an 3504 * indirection table is a u8 array while indir->ring_index 3505 * points to an array of u32. 3506 * 3507 * Indirection table contains the FW Client IDs, so we need to 3508 * align the returned table to the Client ID of the leading RSS 3509 * queue. 3510 */ 3511 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 3512 indir[i] = ind_table[i] - bp->fp->cl_id; 3513 3514 return 0; 3515 } 3516 3517 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3518 const u8 *key, const u8 hfunc) 3519 { 3520 struct bnx2x *bp = netdev_priv(dev); 3521 size_t i; 3522 3523 /* We require at least one supported parameter to be changed and no 3524 * change in any of the unsupported parameters 3525 */ 3526 if (key || 3527 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3528 return -EOPNOTSUPP; 3529 3530 if (!indir) 3531 return 0; 3532 3533 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3534 /* 3535 * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3536 * as an internal storage of an indirection table is a u8 array 3537 * while indir->ring_index points to an array of u32. 3538 * 3539 * Indirection table contains the FW Client IDs, so we need to 3540 * align the received table to the Client ID of the leading RSS 3541 * queue 3542 */ 3543 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3544 } 3545 3546 if (bp->state == BNX2X_STATE_OPEN) 3547 return bnx2x_config_rss_eth(bp, false); 3548 3549 return 0; 3550 } 3551 3552 /** 3553 * bnx2x_get_channels - gets the number of RSS queues. 3554 * 3555 * @dev: net device 3556 * @channels: returns the number of max / current queues 3557 */ 3558 static void bnx2x_get_channels(struct net_device *dev, 3559 struct ethtool_channels *channels) 3560 { 3561 struct bnx2x *bp = netdev_priv(dev); 3562 3563 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 3564 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 3565 } 3566 3567 /** 3568 * bnx2x_change_num_queues - change the number of RSS queues. 3569 * 3570 * @bp: bnx2x private structure 3571 * 3572 * Re-configure interrupt mode to get the new number of MSI-X 3573 * vectors and re-add NAPI objects. 3574 */ 3575 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 3576 { 3577 bnx2x_disable_msi(bp); 3578 bp->num_ethernet_queues = num_rss; 3579 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 3580 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 3581 bnx2x_set_int_mode(bp); 3582 } 3583 3584 /** 3585 * bnx2x_set_channels - sets the number of RSS queues. 3586 * 3587 * @dev: net device 3588 * @channels: includes the number of queues requested 3589 */ 3590 static int bnx2x_set_channels(struct net_device *dev, 3591 struct ethtool_channels *channels) 3592 { 3593 struct bnx2x *bp = netdev_priv(dev); 3594 3595 DP(BNX2X_MSG_ETHTOOL, 3596 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 3597 channels->rx_count, channels->tx_count, channels->other_count, 3598 channels->combined_count); 3599 3600 if (pci_num_vf(bp->pdev)) { 3601 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3602 return -EPERM; 3603 } 3604 3605 /* We don't support separate rx / tx channels. 3606 * We don't allow setting 'other' channels. 3607 */ 3608 if (channels->rx_count || channels->tx_count || channels->other_count 3609 || (channels->combined_count == 0) || 3610 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 3611 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 3612 return -EINVAL; 3613 } 3614 3615 /* Check if there was a change in the active parameters */ 3616 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 3617 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 3618 return 0; 3619 } 3620 3621 /* Set the requested number of queues in bp context. 3622 * Note that the actual number of queues created during load may be 3623 * less than requested if memory is low. 3624 */ 3625 if (unlikely(!netif_running(dev))) { 3626 bnx2x_change_num_queues(bp, channels->combined_count); 3627 return 0; 3628 } 3629 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 3630 bnx2x_change_num_queues(bp, channels->combined_count); 3631 return bnx2x_nic_load(bp, LOAD_NORMAL); 3632 } 3633 3634 static int bnx2x_get_ts_info(struct net_device *dev, 3635 struct ethtool_ts_info *info) 3636 { 3637 struct bnx2x *bp = netdev_priv(dev); 3638 3639 if (bp->flags & PTP_SUPPORTED) { 3640 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3641 SOF_TIMESTAMPING_RX_SOFTWARE | 3642 SOF_TIMESTAMPING_SOFTWARE | 3643 SOF_TIMESTAMPING_TX_HARDWARE | 3644 SOF_TIMESTAMPING_RX_HARDWARE | 3645 SOF_TIMESTAMPING_RAW_HARDWARE; 3646 3647 if (bp->ptp_clock) 3648 info->phc_index = ptp_clock_index(bp->ptp_clock); 3649 else 3650 info->phc_index = -1; 3651 3652 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3653 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3654 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3655 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3656 3657 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3658 3659 return 0; 3660 } 3661 3662 return ethtool_op_get_ts_info(dev, info); 3663 } 3664 3665 static const struct ethtool_ops bnx2x_ethtool_ops = { 3666 .get_drvinfo = bnx2x_get_drvinfo, 3667 .get_regs_len = bnx2x_get_regs_len, 3668 .get_regs = bnx2x_get_regs, 3669 .get_dump_flag = bnx2x_get_dump_flag, 3670 .get_dump_data = bnx2x_get_dump_data, 3671 .set_dump = bnx2x_set_dump, 3672 .get_wol = bnx2x_get_wol, 3673 .set_wol = bnx2x_set_wol, 3674 .get_msglevel = bnx2x_get_msglevel, 3675 .set_msglevel = bnx2x_set_msglevel, 3676 .nway_reset = bnx2x_nway_reset, 3677 .get_link = bnx2x_get_link, 3678 .get_eeprom_len = bnx2x_get_eeprom_len, 3679 .get_eeprom = bnx2x_get_eeprom, 3680 .set_eeprom = bnx2x_set_eeprom, 3681 .get_coalesce = bnx2x_get_coalesce, 3682 .set_coalesce = bnx2x_set_coalesce, 3683 .get_ringparam = bnx2x_get_ringparam, 3684 .set_ringparam = bnx2x_set_ringparam, 3685 .get_pauseparam = bnx2x_get_pauseparam, 3686 .set_pauseparam = bnx2x_set_pauseparam, 3687 .self_test = bnx2x_self_test, 3688 .get_sset_count = bnx2x_get_sset_count, 3689 .get_priv_flags = bnx2x_get_private_flags, 3690 .get_strings = bnx2x_get_strings, 3691 .set_phys_id = bnx2x_set_phys_id, 3692 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3693 .get_rxnfc = bnx2x_get_rxnfc, 3694 .set_rxnfc = bnx2x_set_rxnfc, 3695 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3696 .get_rxfh = bnx2x_get_rxfh, 3697 .set_rxfh = bnx2x_set_rxfh, 3698 .get_channels = bnx2x_get_channels, 3699 .set_channels = bnx2x_set_channels, 3700 .get_module_info = bnx2x_get_module_info, 3701 .get_module_eeprom = bnx2x_get_module_eeprom, 3702 .get_eee = bnx2x_get_eee, 3703 .set_eee = bnx2x_set_eee, 3704 .get_ts_info = bnx2x_get_ts_info, 3705 .get_link_ksettings = bnx2x_get_link_ksettings, 3706 .set_link_ksettings = bnx2x_set_link_ksettings, 3707 }; 3708 3709 static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3710 .get_drvinfo = bnx2x_get_drvinfo, 3711 .get_msglevel = bnx2x_get_msglevel, 3712 .set_msglevel = bnx2x_set_msglevel, 3713 .get_link = bnx2x_get_link, 3714 .get_coalesce = bnx2x_get_coalesce, 3715 .get_ringparam = bnx2x_get_ringparam, 3716 .set_ringparam = bnx2x_set_ringparam, 3717 .get_sset_count = bnx2x_get_sset_count, 3718 .get_strings = bnx2x_get_strings, 3719 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3720 .get_rxnfc = bnx2x_get_rxnfc, 3721 .set_rxnfc = bnx2x_set_rxnfc, 3722 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3723 .get_rxfh = bnx2x_get_rxfh, 3724 .set_rxfh = bnx2x_set_rxfh, 3725 .get_channels = bnx2x_get_channels, 3726 .set_channels = bnx2x_set_channels, 3727 .get_link_ksettings = bnx2x_get_vf_link_ksettings, 3728 }; 3729 3730 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3731 { 3732 netdev->ethtool_ops = (IS_PF(bp)) ? 3733 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3734 } 3735