1 /* bnx2x_ethtool.c: QLogic Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  * Copyright (c) 2014 QLogic Corporation
5  * All rights reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12  * Written by: Eliezer Tamir
13  * Based on code from Michael Chan's bnx2 driver
14  * UDP CSUM errata workaround by Arik Gendelman
15  * Slowpath and fastpath rework by Vladislav Zolotarov
16  * Statistics and Link management by Yitchak Gertner
17  *
18  */
19 
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 
22 #include <linux/ethtool.h>
23 #include <linux/netdevice.h>
24 #include <linux/types.h>
25 #include <linux/sched.h>
26 #include <linux/crc32.h>
27 #include "bnx2x.h"
28 #include "bnx2x_cmn.h"
29 #include "bnx2x_dump.h"
30 #include "bnx2x_init.h"
31 
32 /* Note: in the format strings below %s is replaced by the queue-name which is
33  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
34  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
35  */
36 #define MAX_QUEUE_NAME_LEN	4
37 static const struct {
38 	long offset;
39 	int size;
40 	char string[ETH_GSTRING_LEN];
41 } bnx2x_q_stats_arr[] = {
42 /* 1 */	{ Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
43 	{ Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 						8, "[%s]: rx_ucast_packets" },
45 	{ Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 						8, "[%s]: rx_mcast_packets" },
47 	{ Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 						8, "[%s]: rx_bcast_packets" },
49 	{ Q_STATS_OFFSET32(no_buff_discard_hi),	8, "[%s]: rx_discards" },
50 	{ Q_STATS_OFFSET32(rx_err_discard_pkt),
51 					 4, "[%s]: rx_phy_ip_err_discards"},
52 	{ Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 					 4, "[%s]: rx_skb_alloc_discard" },
54 	{ Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
55 	{ Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
56 	{ Q_STATS_OFFSET32(total_bytes_transmitted_hi),	8, "[%s]: tx_bytes" },
57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
58 						8, "[%s]: tx_ucast_packets" },
59 	{ Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 						8, "[%s]: tx_mcast_packets" },
61 	{ Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
62 						8, "[%s]: tx_bcast_packets" },
63 	{ Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 						8, "[%s]: tpa_aggregations" },
65 	{ Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 					8, "[%s]: tpa_aggregated_frames"},
67 	{ Q_STATS_OFFSET32(total_tpa_bytes_hi),	8, "[%s]: tpa_bytes"},
68 	{ Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 					4, "[%s]: driver_filtered_tx_pkt" }
70 };
71 
72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
73 
74 static const struct {
75 	long offset;
76 	int size;
77 	bool is_port_stat;
78 	char string[ETH_GSTRING_LEN];
79 } bnx2x_stats_arr[] = {
80 /* 1 */	{ STATS_OFFSET32(total_bytes_received_hi),
81 				8, false, "rx_bytes" },
82 	{ STATS_OFFSET32(error_bytes_received_hi),
83 				8, false, "rx_error_bytes" },
84 	{ STATS_OFFSET32(total_unicast_packets_received_hi),
85 				8, false, "rx_ucast_packets" },
86 	{ STATS_OFFSET32(total_multicast_packets_received_hi),
87 				8, false, "rx_mcast_packets" },
88 	{ STATS_OFFSET32(total_broadcast_packets_received_hi),
89 				8, false, "rx_bcast_packets" },
90 	{ STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
91 				8, true, "rx_crc_errors" },
92 	{ STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
93 				8, true, "rx_align_errors" },
94 	{ STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
95 				8, true, "rx_undersize_packets" },
96 	{ STATS_OFFSET32(etherstatsoverrsizepkts_hi),
97 				8, true, "rx_oversize_packets" },
98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
99 				8, true, "rx_fragments" },
100 	{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
101 				8, true, "rx_jabbers" },
102 	{ STATS_OFFSET32(no_buff_discard_hi),
103 				8, false, "rx_discards" },
104 	{ STATS_OFFSET32(mac_filter_discard),
105 				4, true, "rx_filtered_packets" },
106 	{ STATS_OFFSET32(mf_tag_discard),
107 				4, true, "rx_mf_tag_discard" },
108 	{ STATS_OFFSET32(pfc_frames_received_hi),
109 				8, true, "pfc_frames_received" },
110 	{ STATS_OFFSET32(pfc_frames_sent_hi),
111 				8, true, "pfc_frames_sent" },
112 	{ STATS_OFFSET32(brb_drop_hi),
113 				8, true, "rx_brb_discard" },
114 	{ STATS_OFFSET32(brb_truncate_hi),
115 				8, true, "rx_brb_truncate" },
116 	{ STATS_OFFSET32(pause_frames_received_hi),
117 				8, true, "rx_pause_frames" },
118 	{ STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
119 				8, true, "rx_mac_ctrl_frames" },
120 	{ STATS_OFFSET32(nig_timer_max),
121 				4, true, "rx_constant_pause_events" },
122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
123 				4, false, "rx_phy_ip_err_discards"},
124 	{ STATS_OFFSET32(rx_skb_alloc_failed),
125 				4, false, "rx_skb_alloc_discard" },
126 	{ STATS_OFFSET32(hw_csum_err),
127 				4, false, "rx_csum_offload_errors" },
128 	{ STATS_OFFSET32(driver_xoff),
129 				4, false, "tx_exhaustion_events" },
130 	{ STATS_OFFSET32(total_bytes_transmitted_hi),
131 				8, false, "tx_bytes" },
132 	{ STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 				8, true, "tx_error_bytes" },
134 	{ STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 				8, false, "tx_ucast_packets" },
136 	{ STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 				8, false, "tx_mcast_packets" },
138 	{ STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 				8, false, "tx_bcast_packets" },
140 	{ STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 				8, true, "tx_mac_errors" },
142 	{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 				8, true, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 				8, true, "tx_single_collisions" },
146 	{ STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 				8, true, "tx_multi_collisions" },
148 	{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 				8, true, "tx_deferred" },
150 	{ STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 				8, true, "tx_excess_collisions" },
152 	{ STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 				8, true, "tx_late_collisions" },
154 	{ STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 				8, true, "tx_total_collisions" },
156 	{ STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 				8, true, "tx_64_byte_packets" },
158 	{ STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 				8, true, "tx_65_to_127_byte_packets" },
160 	{ STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 				8, true, "tx_128_to_255_byte_packets" },
162 	{ STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 				8, true, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 				8, true, "tx_512_to_1023_byte_packets" },
166 	{ STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 				8, true, "tx_1024_to_1522_byte_packets" },
168 	{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 				8, true, "tx_1523_to_9022_byte_packets" },
170 	{ STATS_OFFSET32(pause_frames_sent_hi),
171 				8, true, "tx_pause_frames" },
172 	{ STATS_OFFSET32(total_tpa_aggregations_hi),
173 				8, false, "tpa_aggregations" },
174 	{ STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 				8, false, "tpa_aggregated_frames"},
176 	{ STATS_OFFSET32(total_tpa_bytes_hi),
177 				8, false, "tpa_bytes"},
178 	{ STATS_OFFSET32(recoverable_error),
179 				4, false, "recoverable_errors" },
180 	{ STATS_OFFSET32(unrecoverable_error),
181 				4, false, "unrecoverable_errors" },
182 	{ STATS_OFFSET32(driver_filtered_tx_pkt),
183 				4, false, "driver_filtered_tx_pkt" },
184 	{ STATS_OFFSET32(eee_tx_lpi),
185 				4, true, "Tx LPI entry count"},
186 	{ STATS_OFFSET32(ptp_skip_tx_ts),
187 				4, false, "ptp_skipped_tx_tstamp" },
188 };
189 
190 #define BNX2X_NUM_STATS		ARRAY_SIZE(bnx2x_stats_arr)
191 
192 static int bnx2x_get_port_type(struct bnx2x *bp)
193 {
194 	int port_type;
195 	u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
196 	switch (bp->link_params.phy[phy_idx].media_type) {
197 	case ETH_PHY_SFPP_10G_FIBER:
198 	case ETH_PHY_SFP_1G_FIBER:
199 	case ETH_PHY_XFP_FIBER:
200 	case ETH_PHY_KR:
201 	case ETH_PHY_CX4:
202 		port_type = PORT_FIBRE;
203 		break;
204 	case ETH_PHY_DA_TWINAX:
205 		port_type = PORT_DA;
206 		break;
207 	case ETH_PHY_BASE_T:
208 		port_type = PORT_TP;
209 		break;
210 	case ETH_PHY_NOT_PRESENT:
211 		port_type = PORT_NONE;
212 		break;
213 	case ETH_PHY_UNSPECIFIED:
214 	default:
215 		port_type = PORT_OTHER;
216 		break;
217 	}
218 	return port_type;
219 }
220 
221 static int bnx2x_get_vf_link_ksettings(struct net_device *dev,
222 				       struct ethtool_link_ksettings *cmd)
223 {
224 	struct bnx2x *bp = netdev_priv(dev);
225 	u32 supported, advertising;
226 
227 	ethtool_convert_link_mode_to_legacy_u32(&supported,
228 						cmd->link_modes.supported);
229 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
230 						cmd->link_modes.advertising);
231 
232 	if (bp->state == BNX2X_STATE_OPEN) {
233 		if (test_bit(BNX2X_LINK_REPORT_FD,
234 			     &bp->vf_link_vars.link_report_flags))
235 			cmd->base.duplex = DUPLEX_FULL;
236 		else
237 			cmd->base.duplex = DUPLEX_HALF;
238 
239 		cmd->base.speed = bp->vf_link_vars.line_speed;
240 	} else {
241 		cmd->base.duplex = DUPLEX_UNKNOWN;
242 		cmd->base.speed = SPEED_UNKNOWN;
243 	}
244 
245 	cmd->base.port		= PORT_OTHER;
246 	cmd->base.phy_address	= 0;
247 	cmd->base.autoneg	= AUTONEG_DISABLE;
248 
249 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
250 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
251 	   "  duplex %d  port %d  phy_address %d\n"
252 	   "  autoneg %d\n",
253 	   cmd->base.cmd, supported, advertising,
254 	   cmd->base.speed,
255 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
256 	   cmd->base.autoneg);
257 
258 	return 0;
259 }
260 
261 static int bnx2x_get_link_ksettings(struct net_device *dev,
262 				    struct ethtool_link_ksettings *cmd)
263 {
264 	struct bnx2x *bp = netdev_priv(dev);
265 	int cfg_idx = bnx2x_get_link_cfg_idx(bp);
266 	u32 media_type;
267 	u32 supported, advertising, lp_advertising;
268 
269 	ethtool_convert_link_mode_to_legacy_u32(&lp_advertising,
270 						cmd->link_modes.lp_advertising);
271 
272 	/* Dual Media boards present all available port types */
273 	supported = bp->port.supported[cfg_idx] |
274 		(bp->port.supported[cfg_idx ^ 1] &
275 		 (SUPPORTED_TP | SUPPORTED_FIBRE));
276 	advertising = bp->port.advertising[cfg_idx];
277 	media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
278 	if (media_type == ETH_PHY_SFP_1G_FIBER) {
279 		supported &= ~(SUPPORTED_10000baseT_Full);
280 		advertising &= ~(ADVERTISED_10000baseT_Full);
281 	}
282 
283 	if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
284 	    !(bp->flags & MF_FUNC_DIS)) {
285 		cmd->base.duplex = bp->link_vars.duplex;
286 
287 		if (IS_MF(bp) && !BP_NOMCP(bp))
288 			cmd->base.speed = bnx2x_get_mf_speed(bp);
289 		else
290 			cmd->base.speed = bp->link_vars.line_speed;
291 	} else {
292 		cmd->base.duplex = DUPLEX_UNKNOWN;
293 		cmd->base.speed = SPEED_UNKNOWN;
294 	}
295 
296 	cmd->base.port = bnx2x_get_port_type(bp);
297 
298 	cmd->base.phy_address = bp->mdio.prtad;
299 
300 	if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
301 		cmd->base.autoneg = AUTONEG_ENABLE;
302 	else
303 		cmd->base.autoneg = AUTONEG_DISABLE;
304 
305 	/* Publish LP advertised speeds and FC */
306 	if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
307 		u32 status = bp->link_vars.link_status;
308 
309 		lp_advertising |= ADVERTISED_Autoneg;
310 		if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
311 			lp_advertising |= ADVERTISED_Pause;
312 		if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
313 			lp_advertising |= ADVERTISED_Asym_Pause;
314 
315 		if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
316 			lp_advertising |= ADVERTISED_10baseT_Half;
317 		if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
318 			lp_advertising |= ADVERTISED_10baseT_Full;
319 		if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
320 			lp_advertising |= ADVERTISED_100baseT_Half;
321 		if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
322 			lp_advertising |= ADVERTISED_100baseT_Full;
323 		if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
324 			lp_advertising |= ADVERTISED_1000baseT_Half;
325 		if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
326 			if (media_type == ETH_PHY_KR) {
327 				lp_advertising |=
328 					ADVERTISED_1000baseKX_Full;
329 			} else {
330 				lp_advertising |=
331 					ADVERTISED_1000baseT_Full;
332 			}
333 		}
334 		if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
335 			lp_advertising |= ADVERTISED_2500baseX_Full;
336 		if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
337 			if (media_type == ETH_PHY_KR) {
338 				lp_advertising |=
339 					ADVERTISED_10000baseKR_Full;
340 			} else {
341 				lp_advertising |=
342 					ADVERTISED_10000baseT_Full;
343 			}
344 		}
345 		if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
346 			lp_advertising |= ADVERTISED_20000baseKR2_Full;
347 	}
348 
349 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
350 						supported);
351 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
352 						advertising);
353 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
354 						lp_advertising);
355 
356 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
357 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
358 	   "  duplex %d  port %d  phy_address %d\n"
359 	   "  autoneg %d\n",
360 	   cmd->base.cmd, supported, advertising,
361 	   cmd->base.speed,
362 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
363 	   cmd->base.autoneg);
364 
365 	return 0;
366 }
367 
368 static int bnx2x_set_link_ksettings(struct net_device *dev,
369 				    const struct ethtool_link_ksettings *cmd)
370 {
371 	struct bnx2x *bp = netdev_priv(dev);
372 	u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
373 	u32 speed, phy_idx;
374 	u32 supported;
375 	u8 duplex = cmd->base.duplex;
376 
377 	ethtool_convert_link_mode_to_legacy_u32(&supported,
378 						cmd->link_modes.supported);
379 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
380 						cmd->link_modes.advertising);
381 
382 	if (IS_MF_SD(bp))
383 		return 0;
384 
385 	DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
386 	   "  supported 0x%x  advertising 0x%x  speed %u\n"
387 	   "  duplex %d  port %d  phy_address %d\n"
388 	   "  autoneg %d\n",
389 	   cmd->base.cmd, supported, advertising,
390 	   cmd->base.speed,
391 	   cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
392 	   cmd->base.autoneg);
393 
394 	speed = cmd->base.speed;
395 
396 	/* If received a request for an unknown duplex, assume full*/
397 	if (duplex == DUPLEX_UNKNOWN)
398 		duplex = DUPLEX_FULL;
399 
400 	if (IS_MF_SI(bp)) {
401 		u32 part;
402 		u32 line_speed = bp->link_vars.line_speed;
403 
404 		/* use 10G if no link detected */
405 		if (!line_speed)
406 			line_speed = 10000;
407 
408 		if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
409 			DP(BNX2X_MSG_ETHTOOL,
410 			   "To set speed BC %X or higher is required, please upgrade BC\n",
411 			   REQ_BC_VER_4_SET_MF_BW);
412 			return -EINVAL;
413 		}
414 
415 		part = (speed * 100) / line_speed;
416 
417 		if (line_speed < speed || !part) {
418 			DP(BNX2X_MSG_ETHTOOL,
419 			   "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
420 			return -EINVAL;
421 		}
422 
423 		if (bp->state != BNX2X_STATE_OPEN)
424 			/* store value for following "load" */
425 			bp->pending_max = part;
426 		else
427 			bnx2x_update_max_mf_config(bp, part);
428 
429 		return 0;
430 	}
431 
432 	cfg_idx = bnx2x_get_link_cfg_idx(bp);
433 	old_multi_phy_config = bp->link_params.multi_phy_config;
434 	if (cmd->base.port != bnx2x_get_port_type(bp)) {
435 		switch (cmd->base.port) {
436 		case PORT_TP:
437 			if (!(bp->port.supported[0] & SUPPORTED_TP ||
438 			      bp->port.supported[1] & SUPPORTED_TP)) {
439 				DP(BNX2X_MSG_ETHTOOL,
440 				   "Unsupported port type\n");
441 				return -EINVAL;
442 			}
443 			bp->link_params.multi_phy_config &=
444 				~PORT_HW_CFG_PHY_SELECTION_MASK;
445 			if (bp->link_params.multi_phy_config &
446 			    PORT_HW_CFG_PHY_SWAPPED_ENABLED)
447 				bp->link_params.multi_phy_config |=
448 				PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
449 			else
450 				bp->link_params.multi_phy_config |=
451 				PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
452 			break;
453 		case PORT_FIBRE:
454 		case PORT_DA:
455 		case PORT_NONE:
456 			if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
457 			      bp->port.supported[1] & SUPPORTED_FIBRE)) {
458 				DP(BNX2X_MSG_ETHTOOL,
459 				   "Unsupported port type\n");
460 				return -EINVAL;
461 			}
462 			bp->link_params.multi_phy_config &=
463 				~PORT_HW_CFG_PHY_SELECTION_MASK;
464 			if (bp->link_params.multi_phy_config &
465 			    PORT_HW_CFG_PHY_SWAPPED_ENABLED)
466 				bp->link_params.multi_phy_config |=
467 				PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
468 			else
469 				bp->link_params.multi_phy_config |=
470 				PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
471 			break;
472 		default:
473 			DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
474 			return -EINVAL;
475 		}
476 	}
477 	/* Save new config in case command complete successfully */
478 	new_multi_phy_config = bp->link_params.multi_phy_config;
479 	/* Get the new cfg_idx */
480 	cfg_idx = bnx2x_get_link_cfg_idx(bp);
481 	/* Restore old config in case command failed */
482 	bp->link_params.multi_phy_config = old_multi_phy_config;
483 	DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
484 
485 	if (cmd->base.autoneg == AUTONEG_ENABLE) {
486 		u32 an_supported_speed = bp->port.supported[cfg_idx];
487 		if (bp->link_params.phy[EXT_PHY1].type ==
488 		    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
489 			an_supported_speed |= (SUPPORTED_100baseT_Half |
490 					       SUPPORTED_100baseT_Full);
491 		if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
492 			DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
493 			return -EINVAL;
494 		}
495 
496 		/* advertise the requested speed and duplex if supported */
497 		if (advertising & ~an_supported_speed) {
498 			DP(BNX2X_MSG_ETHTOOL,
499 			   "Advertisement parameters are not supported\n");
500 			return -EINVAL;
501 		}
502 
503 		bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
504 		bp->link_params.req_duplex[cfg_idx] = duplex;
505 		bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
506 					 advertising);
507 		if (advertising) {
508 
509 			bp->link_params.speed_cap_mask[cfg_idx] = 0;
510 			if (advertising & ADVERTISED_10baseT_Half) {
511 				bp->link_params.speed_cap_mask[cfg_idx] |=
512 				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
513 			}
514 			if (advertising & ADVERTISED_10baseT_Full)
515 				bp->link_params.speed_cap_mask[cfg_idx] |=
516 				PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
517 
518 			if (advertising & ADVERTISED_100baseT_Full)
519 				bp->link_params.speed_cap_mask[cfg_idx] |=
520 				PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
521 
522 			if (advertising & ADVERTISED_100baseT_Half) {
523 				bp->link_params.speed_cap_mask[cfg_idx] |=
524 				     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
525 			}
526 			if (advertising & ADVERTISED_1000baseT_Half) {
527 				bp->link_params.speed_cap_mask[cfg_idx] |=
528 					PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
529 			}
530 			if (advertising & (ADVERTISED_1000baseT_Full |
531 						ADVERTISED_1000baseKX_Full))
532 				bp->link_params.speed_cap_mask[cfg_idx] |=
533 					PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
534 
535 			if (advertising & (ADVERTISED_10000baseT_Full |
536 						ADVERTISED_10000baseKX4_Full |
537 						ADVERTISED_10000baseKR_Full))
538 				bp->link_params.speed_cap_mask[cfg_idx] |=
539 					PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
540 
541 			if (advertising & ADVERTISED_20000baseKR2_Full)
542 				bp->link_params.speed_cap_mask[cfg_idx] |=
543 					PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
544 		}
545 	} else { /* forced speed */
546 		/* advertise the requested speed and duplex if supported */
547 		switch (speed) {
548 		case SPEED_10:
549 			if (duplex == DUPLEX_FULL) {
550 				if (!(bp->port.supported[cfg_idx] &
551 				      SUPPORTED_10baseT_Full)) {
552 					DP(BNX2X_MSG_ETHTOOL,
553 					   "10M full not supported\n");
554 					return -EINVAL;
555 				}
556 
557 				advertising = (ADVERTISED_10baseT_Full |
558 					       ADVERTISED_TP);
559 			} else {
560 				if (!(bp->port.supported[cfg_idx] &
561 				      SUPPORTED_10baseT_Half)) {
562 					DP(BNX2X_MSG_ETHTOOL,
563 					   "10M half not supported\n");
564 					return -EINVAL;
565 				}
566 
567 				advertising = (ADVERTISED_10baseT_Half |
568 					       ADVERTISED_TP);
569 			}
570 			break;
571 
572 		case SPEED_100:
573 			if (duplex == DUPLEX_FULL) {
574 				if (!(bp->port.supported[cfg_idx] &
575 						SUPPORTED_100baseT_Full)) {
576 					DP(BNX2X_MSG_ETHTOOL,
577 					   "100M full not supported\n");
578 					return -EINVAL;
579 				}
580 
581 				advertising = (ADVERTISED_100baseT_Full |
582 					       ADVERTISED_TP);
583 			} else {
584 				if (!(bp->port.supported[cfg_idx] &
585 						SUPPORTED_100baseT_Half)) {
586 					DP(BNX2X_MSG_ETHTOOL,
587 					   "100M half not supported\n");
588 					return -EINVAL;
589 				}
590 
591 				advertising = (ADVERTISED_100baseT_Half |
592 					       ADVERTISED_TP);
593 			}
594 			break;
595 
596 		case SPEED_1000:
597 			if (duplex != DUPLEX_FULL) {
598 				DP(BNX2X_MSG_ETHTOOL,
599 				   "1G half not supported\n");
600 				return -EINVAL;
601 			}
602 
603 			if (bp->port.supported[cfg_idx] &
604 			     SUPPORTED_1000baseT_Full) {
605 				advertising = (ADVERTISED_1000baseT_Full |
606 					       ADVERTISED_TP);
607 
608 			} else if (bp->port.supported[cfg_idx] &
609 				   SUPPORTED_1000baseKX_Full) {
610 				advertising = ADVERTISED_1000baseKX_Full;
611 			} else {
612 				DP(BNX2X_MSG_ETHTOOL,
613 				   "1G full not supported\n");
614 				return -EINVAL;
615 			}
616 
617 			break;
618 
619 		case SPEED_2500:
620 			if (duplex != DUPLEX_FULL) {
621 				DP(BNX2X_MSG_ETHTOOL,
622 				   "2.5G half not supported\n");
623 				return -EINVAL;
624 			}
625 
626 			if (!(bp->port.supported[cfg_idx]
627 			      & SUPPORTED_2500baseX_Full)) {
628 				DP(BNX2X_MSG_ETHTOOL,
629 				   "2.5G full not supported\n");
630 				return -EINVAL;
631 			}
632 
633 			advertising = (ADVERTISED_2500baseX_Full |
634 				       ADVERTISED_TP);
635 			break;
636 
637 		case SPEED_10000:
638 			if (duplex != DUPLEX_FULL) {
639 				DP(BNX2X_MSG_ETHTOOL,
640 				   "10G half not supported\n");
641 				return -EINVAL;
642 			}
643 			phy_idx = bnx2x_get_cur_phy_idx(bp);
644 			if ((bp->port.supported[cfg_idx] &
645 			     SUPPORTED_10000baseT_Full) &&
646 			    (bp->link_params.phy[phy_idx].media_type !=
647 			     ETH_PHY_SFP_1G_FIBER)) {
648 				advertising = (ADVERTISED_10000baseT_Full |
649 					       ADVERTISED_FIBRE);
650 			} else if (bp->port.supported[cfg_idx] &
651 			       SUPPORTED_10000baseKR_Full) {
652 				advertising = (ADVERTISED_10000baseKR_Full |
653 					       ADVERTISED_FIBRE);
654 			} else {
655 				DP(BNX2X_MSG_ETHTOOL,
656 				   "10G full not supported\n");
657 				return -EINVAL;
658 			}
659 
660 			break;
661 
662 		default:
663 			DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
664 			return -EINVAL;
665 		}
666 
667 		bp->link_params.req_line_speed[cfg_idx] = speed;
668 		bp->link_params.req_duplex[cfg_idx] = duplex;
669 		bp->port.advertising[cfg_idx] = advertising;
670 	}
671 
672 	DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
673 	   "  req_duplex %d  advertising 0x%x\n",
674 	   bp->link_params.req_line_speed[cfg_idx],
675 	   bp->link_params.req_duplex[cfg_idx],
676 	   bp->port.advertising[cfg_idx]);
677 
678 	/* Set new config */
679 	bp->link_params.multi_phy_config = new_multi_phy_config;
680 	if (netif_running(dev)) {
681 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
682 		bnx2x_force_link_reset(bp);
683 		bnx2x_link_set(bp);
684 	}
685 
686 	return 0;
687 }
688 
689 #define DUMP_ALL_PRESETS		0x1FFF
690 #define DUMP_MAX_PRESETS		13
691 
692 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
693 {
694 	if (CHIP_IS_E1(bp))
695 		return dump_num_registers[0][preset-1];
696 	else if (CHIP_IS_E1H(bp))
697 		return dump_num_registers[1][preset-1];
698 	else if (CHIP_IS_E2(bp))
699 		return dump_num_registers[2][preset-1];
700 	else if (CHIP_IS_E3A0(bp))
701 		return dump_num_registers[3][preset-1];
702 	else if (CHIP_IS_E3B0(bp))
703 		return dump_num_registers[4][preset-1];
704 	else
705 		return 0;
706 }
707 
708 static int __bnx2x_get_regs_len(struct bnx2x *bp)
709 {
710 	u32 preset_idx;
711 	int regdump_len = 0;
712 
713 	/* Calculate the total preset regs length */
714 	for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
715 		regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
716 
717 	return regdump_len;
718 }
719 
720 static int bnx2x_get_regs_len(struct net_device *dev)
721 {
722 	struct bnx2x *bp = netdev_priv(dev);
723 	int regdump_len = 0;
724 
725 	if (IS_VF(bp))
726 		return 0;
727 
728 	regdump_len = __bnx2x_get_regs_len(bp);
729 	regdump_len *= 4;
730 	regdump_len += sizeof(struct dump_header);
731 
732 	return regdump_len;
733 }
734 
735 #define IS_E1_REG(chips)	((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
736 #define IS_E1H_REG(chips)	((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
737 #define IS_E2_REG(chips)	((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
738 #define IS_E3A0_REG(chips)	((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
739 #define IS_E3B0_REG(chips)	((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
740 
741 #define IS_REG_IN_PRESET(presets, idx)  \
742 		((presets & (1 << (idx-1))) == (1 << (idx-1)))
743 
744 /******* Paged registers info selectors ********/
745 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
746 {
747 	if (CHIP_IS_E2(bp))
748 		return page_vals_e2;
749 	else if (CHIP_IS_E3(bp))
750 		return page_vals_e3;
751 	else
752 		return NULL;
753 }
754 
755 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
756 {
757 	if (CHIP_IS_E2(bp))
758 		return PAGE_MODE_VALUES_E2;
759 	else if (CHIP_IS_E3(bp))
760 		return PAGE_MODE_VALUES_E3;
761 	else
762 		return 0;
763 }
764 
765 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
766 {
767 	if (CHIP_IS_E2(bp))
768 		return page_write_regs_e2;
769 	else if (CHIP_IS_E3(bp))
770 		return page_write_regs_e3;
771 	else
772 		return NULL;
773 }
774 
775 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
776 {
777 	if (CHIP_IS_E2(bp))
778 		return PAGE_WRITE_REGS_E2;
779 	else if (CHIP_IS_E3(bp))
780 		return PAGE_WRITE_REGS_E3;
781 	else
782 		return 0;
783 }
784 
785 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
786 {
787 	if (CHIP_IS_E2(bp))
788 		return page_read_regs_e2;
789 	else if (CHIP_IS_E3(bp))
790 		return page_read_regs_e3;
791 	else
792 		return NULL;
793 }
794 
795 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
796 {
797 	if (CHIP_IS_E2(bp))
798 		return PAGE_READ_REGS_E2;
799 	else if (CHIP_IS_E3(bp))
800 		return PAGE_READ_REGS_E3;
801 	else
802 		return 0;
803 }
804 
805 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
806 				       const struct reg_addr *reg_info)
807 {
808 	if (CHIP_IS_E1(bp))
809 		return IS_E1_REG(reg_info->chips);
810 	else if (CHIP_IS_E1H(bp))
811 		return IS_E1H_REG(reg_info->chips);
812 	else if (CHIP_IS_E2(bp))
813 		return IS_E2_REG(reg_info->chips);
814 	else if (CHIP_IS_E3A0(bp))
815 		return IS_E3A0_REG(reg_info->chips);
816 	else if (CHIP_IS_E3B0(bp))
817 		return IS_E3B0_REG(reg_info->chips);
818 	else
819 		return false;
820 }
821 
822 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
823 	const struct wreg_addr *wreg_info)
824 {
825 	if (CHIP_IS_E1(bp))
826 		return IS_E1_REG(wreg_info->chips);
827 	else if (CHIP_IS_E1H(bp))
828 		return IS_E1H_REG(wreg_info->chips);
829 	else if (CHIP_IS_E2(bp))
830 		return IS_E2_REG(wreg_info->chips);
831 	else if (CHIP_IS_E3A0(bp))
832 		return IS_E3A0_REG(wreg_info->chips);
833 	else if (CHIP_IS_E3B0(bp))
834 		return IS_E3B0_REG(wreg_info->chips);
835 	else
836 		return false;
837 }
838 
839 /**
840  * bnx2x_read_pages_regs - read "paged" registers
841  *
842  * @bp:		device handle
843  * @p:		output buffer
844  * @preset:	the preset value
845  *
846  * Reads "paged" memories: memories that may only be read by first writing to a
847  * specific address ("write address") and then reading from a specific address
848  * ("read address"). There may be more than one write address per "page" and
849  * more than one read address per write address.
850  */
851 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
852 {
853 	u32 i, j, k, n;
854 
855 	/* addresses of the paged registers */
856 	const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
857 	/* number of paged registers */
858 	int num_pages = __bnx2x_get_page_reg_num(bp);
859 	/* write addresses */
860 	const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
861 	/* number of write addresses */
862 	int write_num = __bnx2x_get_page_write_num(bp);
863 	/* read addresses info */
864 	const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
865 	/* number of read addresses */
866 	int read_num = __bnx2x_get_page_read_num(bp);
867 	u32 addr, size;
868 
869 	for (i = 0; i < num_pages; i++) {
870 		for (j = 0; j < write_num; j++) {
871 			REG_WR(bp, write_addr[j], page_addr[i]);
872 
873 			for (k = 0; k < read_num; k++) {
874 				if (IS_REG_IN_PRESET(read_addr[k].presets,
875 						     preset)) {
876 					size = read_addr[k].size;
877 					for (n = 0; n < size; n++) {
878 						addr = read_addr[k].addr + n*4;
879 						*p++ = REG_RD(bp, addr);
880 					}
881 				}
882 			}
883 		}
884 	}
885 }
886 
887 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
888 {
889 	u32 i, j, addr;
890 	const struct wreg_addr *wreg_addr_p = NULL;
891 
892 	if (CHIP_IS_E1(bp))
893 		wreg_addr_p = &wreg_addr_e1;
894 	else if (CHIP_IS_E1H(bp))
895 		wreg_addr_p = &wreg_addr_e1h;
896 	else if (CHIP_IS_E2(bp))
897 		wreg_addr_p = &wreg_addr_e2;
898 	else if (CHIP_IS_E3A0(bp))
899 		wreg_addr_p = &wreg_addr_e3;
900 	else if (CHIP_IS_E3B0(bp))
901 		wreg_addr_p = &wreg_addr_e3b0;
902 
903 	/* Read the idle_chk registers */
904 	for (i = 0; i < IDLE_REGS_COUNT; i++) {
905 		if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
906 		    IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
907 			for (j = 0; j < idle_reg_addrs[i].size; j++)
908 				*p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
909 		}
910 	}
911 
912 	/* Read the regular registers */
913 	for (i = 0; i < REGS_COUNT; i++) {
914 		if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
915 		    IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
916 			for (j = 0; j < reg_addrs[i].size; j++)
917 				*p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
918 		}
919 	}
920 
921 	/* Read the CAM registers */
922 	if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
923 	    IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
924 		for (i = 0; i < wreg_addr_p->size; i++) {
925 			*p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
926 
927 			/* In case of wreg_addr register, read additional
928 			   registers from read_regs array
929 			*/
930 			for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
931 				addr = *(wreg_addr_p->read_regs);
932 				*p++ = REG_RD(bp, addr + j*4);
933 			}
934 		}
935 	}
936 
937 	/* Paged registers are supported in E2 & E3 only */
938 	if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
939 		/* Read "paged" registers */
940 		bnx2x_read_pages_regs(bp, p, preset);
941 	}
942 
943 	return 0;
944 }
945 
946 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
947 {
948 	u32 preset_idx;
949 
950 	/* Read all registers, by reading all preset registers */
951 	for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
952 		/* Skip presets with IOR */
953 		if ((preset_idx == 2) ||
954 		    (preset_idx == 5) ||
955 		    (preset_idx == 8) ||
956 		    (preset_idx == 11))
957 			continue;
958 		__bnx2x_get_preset_regs(bp, p, preset_idx);
959 		p += __bnx2x_get_preset_regs_len(bp, preset_idx);
960 	}
961 }
962 
963 static void bnx2x_get_regs(struct net_device *dev,
964 			   struct ethtool_regs *regs, void *_p)
965 {
966 	u32 *p = _p;
967 	struct bnx2x *bp = netdev_priv(dev);
968 	struct dump_header dump_hdr = {0};
969 
970 	regs->version = 2;
971 	memset(p, 0, regs->len);
972 
973 	if (!netif_running(bp->dev))
974 		return;
975 
976 	/* Disable parity attentions as long as following dump may
977 	 * cause false alarms by reading never written registers. We
978 	 * will re-enable parity attentions right after the dump.
979 	 */
980 
981 	bnx2x_disable_blocks_parity(bp);
982 
983 	dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
984 	dump_hdr.preset = DUMP_ALL_PRESETS;
985 	dump_hdr.version = BNX2X_DUMP_VERSION;
986 
987 	/* dump_meta_data presents OR of CHIP and PATH. */
988 	if (CHIP_IS_E1(bp)) {
989 		dump_hdr.dump_meta_data = DUMP_CHIP_E1;
990 	} else if (CHIP_IS_E1H(bp)) {
991 		dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
992 	} else if (CHIP_IS_E2(bp)) {
993 		dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
994 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
995 	} else if (CHIP_IS_E3A0(bp)) {
996 		dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
997 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
998 	} else if (CHIP_IS_E3B0(bp)) {
999 		dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1000 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1001 	}
1002 
1003 	memcpy(p, &dump_hdr, sizeof(struct dump_header));
1004 	p += dump_hdr.header_size + 1;
1005 
1006 	/* This isn't really an error, but since attention handling is going
1007 	 * to print the GRC timeouts using this macro, we use the same.
1008 	 */
1009 	BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
1010 
1011 	/* Actually read the registers */
1012 	__bnx2x_get_regs(bp, p);
1013 
1014 	/* Re-enable parity attentions */
1015 	bnx2x_clear_blocks_parity(bp);
1016 	bnx2x_enable_blocks_parity(bp);
1017 }
1018 
1019 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
1020 {
1021 	struct bnx2x *bp = netdev_priv(dev);
1022 	int regdump_len = 0;
1023 
1024 	regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1025 	regdump_len *= 4;
1026 	regdump_len += sizeof(struct dump_header);
1027 
1028 	return regdump_len;
1029 }
1030 
1031 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1032 {
1033 	struct bnx2x *bp = netdev_priv(dev);
1034 
1035 	/* Use the ethtool_dump "flag" field as the dump preset index */
1036 	if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1037 		return -EINVAL;
1038 
1039 	bp->dump_preset_idx = val->flag;
1040 	return 0;
1041 }
1042 
1043 static int bnx2x_get_dump_flag(struct net_device *dev,
1044 			       struct ethtool_dump *dump)
1045 {
1046 	struct bnx2x *bp = netdev_priv(dev);
1047 
1048 	dump->version = BNX2X_DUMP_VERSION;
1049 	dump->flag = bp->dump_preset_idx;
1050 	/* Calculate the requested preset idx length */
1051 	dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1052 	DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1053 	   bp->dump_preset_idx, dump->len);
1054 	return 0;
1055 }
1056 
1057 static int bnx2x_get_dump_data(struct net_device *dev,
1058 			       struct ethtool_dump *dump,
1059 			       void *buffer)
1060 {
1061 	u32 *p = buffer;
1062 	struct bnx2x *bp = netdev_priv(dev);
1063 	struct dump_header dump_hdr = {0};
1064 
1065 	/* Disable parity attentions as long as following dump may
1066 	 * cause false alarms by reading never written registers. We
1067 	 * will re-enable parity attentions right after the dump.
1068 	 */
1069 
1070 	bnx2x_disable_blocks_parity(bp);
1071 
1072 	dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1073 	dump_hdr.preset = bp->dump_preset_idx;
1074 	dump_hdr.version = BNX2X_DUMP_VERSION;
1075 
1076 	DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1077 
1078 	/* dump_meta_data presents OR of CHIP and PATH. */
1079 	if (CHIP_IS_E1(bp)) {
1080 		dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1081 	} else if (CHIP_IS_E1H(bp)) {
1082 		dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1083 	} else if (CHIP_IS_E2(bp)) {
1084 		dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1085 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1086 	} else if (CHIP_IS_E3A0(bp)) {
1087 		dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1088 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1089 	} else if (CHIP_IS_E3B0(bp)) {
1090 		dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1091 		(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1092 	}
1093 
1094 	memcpy(p, &dump_hdr, sizeof(struct dump_header));
1095 	p += dump_hdr.header_size + 1;
1096 
1097 	/* Actually read the registers */
1098 	__bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1099 
1100 	/* Re-enable parity attentions */
1101 	bnx2x_clear_blocks_parity(bp);
1102 	bnx2x_enable_blocks_parity(bp);
1103 
1104 	return 0;
1105 }
1106 
1107 static void bnx2x_get_drvinfo(struct net_device *dev,
1108 			      struct ethtool_drvinfo *info)
1109 {
1110 	struct bnx2x *bp = netdev_priv(dev);
1111 	char version[ETHTOOL_FWVERS_LEN];
1112 	int ext_dev_info_offset;
1113 	u32 mbi;
1114 
1115 	strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1116 
1117 	if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) {
1118 		ext_dev_info_offset = SHMEM2_RD(bp,
1119 						extended_dev_info_shared_addr);
1120 		mbi = REG_RD(bp, ext_dev_info_offset +
1121 			     offsetof(struct extended_dev_info_shared_cfg,
1122 				      mbi_version));
1123 		if (mbi) {
1124 			memset(version, 0, sizeof(version));
1125 			snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ",
1126 				 (mbi & 0xff000000) >> 24,
1127 				 (mbi & 0x00ff0000) >> 16,
1128 				 (mbi & 0x0000ff00) >> 8);
1129 			strscpy(info->fw_version, version,
1130 				sizeof(info->fw_version));
1131 		}
1132 	}
1133 
1134 	memset(version, 0, sizeof(version));
1135 	bnx2x_fill_fw_str(bp, version, sizeof(version));
1136 	strlcat(info->fw_version, version, sizeof(info->fw_version));
1137 
1138 	strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1139 }
1140 
1141 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1142 {
1143 	struct bnx2x *bp = netdev_priv(dev);
1144 
1145 	if (bp->flags & NO_WOL_FLAG) {
1146 		wol->supported = 0;
1147 		wol->wolopts = 0;
1148 	} else {
1149 		wol->supported = WAKE_MAGIC;
1150 		if (bp->wol)
1151 			wol->wolopts = WAKE_MAGIC;
1152 		else
1153 			wol->wolopts = 0;
1154 	}
1155 	memset(&wol->sopass, 0, sizeof(wol->sopass));
1156 }
1157 
1158 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1159 {
1160 	struct bnx2x *bp = netdev_priv(dev);
1161 
1162 	if (wol->wolopts & ~WAKE_MAGIC) {
1163 		DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1164 		return -EINVAL;
1165 	}
1166 
1167 	if (wol->wolopts & WAKE_MAGIC) {
1168 		if (bp->flags & NO_WOL_FLAG) {
1169 			DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1170 			return -EINVAL;
1171 		}
1172 		bp->wol = 1;
1173 	} else
1174 		bp->wol = 0;
1175 
1176 	if (SHMEM2_HAS(bp, curr_cfg))
1177 		SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1178 
1179 	return 0;
1180 }
1181 
1182 static u32 bnx2x_get_msglevel(struct net_device *dev)
1183 {
1184 	struct bnx2x *bp = netdev_priv(dev);
1185 
1186 	return bp->msg_enable;
1187 }
1188 
1189 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1190 {
1191 	struct bnx2x *bp = netdev_priv(dev);
1192 
1193 	if (capable(CAP_NET_ADMIN)) {
1194 		/* dump MCP trace */
1195 		if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1196 			bnx2x_fw_dump_lvl(bp, KERN_INFO);
1197 		bp->msg_enable = level;
1198 	}
1199 }
1200 
1201 static int bnx2x_nway_reset(struct net_device *dev)
1202 {
1203 	struct bnx2x *bp = netdev_priv(dev);
1204 
1205 	if (!bp->port.pmf)
1206 		return 0;
1207 
1208 	if (netif_running(dev)) {
1209 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1210 		bnx2x_force_link_reset(bp);
1211 		bnx2x_link_set(bp);
1212 	}
1213 
1214 	return 0;
1215 }
1216 
1217 static u32 bnx2x_get_link(struct net_device *dev)
1218 {
1219 	struct bnx2x *bp = netdev_priv(dev);
1220 
1221 	if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1222 		return 0;
1223 
1224 	if (IS_VF(bp))
1225 		return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1226 				 &bp->vf_link_vars.link_report_flags);
1227 
1228 	return bp->link_vars.link_up;
1229 }
1230 
1231 static int bnx2x_get_eeprom_len(struct net_device *dev)
1232 {
1233 	struct bnx2x *bp = netdev_priv(dev);
1234 
1235 	return bp->common.flash_size;
1236 }
1237 
1238 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1239  * had we done things the other way around, if two pfs from the same port would
1240  * attempt to access nvram at the same time, we could run into a scenario such
1241  * as:
1242  * pf A takes the port lock.
1243  * pf B succeeds in taking the same lock since they are from the same port.
1244  * pf A takes the per pf misc lock. Performs eeprom access.
1245  * pf A finishes. Unlocks the per pf misc lock.
1246  * Pf B takes the lock and proceeds to perform it's own access.
1247  * pf A unlocks the per port lock, while pf B is still working (!).
1248  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1249  * access corrupted by pf B)
1250  */
1251 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1252 {
1253 	int port = BP_PORT(bp);
1254 	int count, i;
1255 	u32 val;
1256 
1257 	/* acquire HW lock: protect against other PFs in PF Direct Assignment */
1258 	bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1259 
1260 	/* adjust timeout for emulation/FPGA */
1261 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1262 	if (CHIP_REV_IS_SLOW(bp))
1263 		count *= 100;
1264 
1265 	/* request access to nvram interface */
1266 	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1267 	       (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1268 
1269 	for (i = 0; i < count*10; i++) {
1270 		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1271 		if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1272 			break;
1273 
1274 		udelay(5);
1275 	}
1276 
1277 	if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1278 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1279 		   "cannot get access to nvram interface\n");
1280 		bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1281 		return -EBUSY;
1282 	}
1283 
1284 	return 0;
1285 }
1286 
1287 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1288 {
1289 	int port = BP_PORT(bp);
1290 	int count, i;
1291 	u32 val;
1292 
1293 	/* adjust timeout for emulation/FPGA */
1294 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1295 	if (CHIP_REV_IS_SLOW(bp))
1296 		count *= 100;
1297 
1298 	/* relinquish nvram interface */
1299 	REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1300 	       (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1301 
1302 	for (i = 0; i < count*10; i++) {
1303 		val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1304 		if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1305 			break;
1306 
1307 		udelay(5);
1308 	}
1309 
1310 	if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1311 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1312 		   "cannot free access to nvram interface\n");
1313 		return -EBUSY;
1314 	}
1315 
1316 	/* release HW lock: protect against other PFs in PF Direct Assignment */
1317 	bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1318 	return 0;
1319 }
1320 
1321 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1322 {
1323 	u32 val;
1324 
1325 	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1326 
1327 	/* enable both bits, even on read */
1328 	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1329 	       (val | MCPR_NVM_ACCESS_ENABLE_EN |
1330 		      MCPR_NVM_ACCESS_ENABLE_WR_EN));
1331 }
1332 
1333 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1334 {
1335 	u32 val;
1336 
1337 	val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1338 
1339 	/* disable both bits, even after read */
1340 	REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1341 	       (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1342 			MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1343 }
1344 
1345 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1346 				  u32 cmd_flags)
1347 {
1348 	int count, i, rc;
1349 	u32 val;
1350 
1351 	/* build the command word */
1352 	cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1353 
1354 	/* need to clear DONE bit separately */
1355 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1356 
1357 	/* address of the NVRAM to read from */
1358 	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1359 	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1360 
1361 	/* issue a read command */
1362 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1363 
1364 	/* adjust timeout for emulation/FPGA */
1365 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1366 	if (CHIP_REV_IS_SLOW(bp))
1367 		count *= 100;
1368 
1369 	/* wait for completion */
1370 	*ret_val = 0;
1371 	rc = -EBUSY;
1372 	for (i = 0; i < count; i++) {
1373 		udelay(5);
1374 		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1375 
1376 		if (val & MCPR_NVM_COMMAND_DONE) {
1377 			val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1378 			/* we read nvram data in cpu order
1379 			 * but ethtool sees it as an array of bytes
1380 			 * converting to big-endian will do the work
1381 			 */
1382 			*ret_val = cpu_to_be32(val);
1383 			rc = 0;
1384 			break;
1385 		}
1386 	}
1387 	if (rc == -EBUSY)
1388 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1389 		   "nvram read timeout expired\n");
1390 	return rc;
1391 }
1392 
1393 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1394 		     int buf_size)
1395 {
1396 	int rc;
1397 	u32 cmd_flags;
1398 	__be32 val;
1399 
1400 	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1401 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1402 		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1403 		   offset, buf_size);
1404 		return -EINVAL;
1405 	}
1406 
1407 	if (offset + buf_size > bp->common.flash_size) {
1408 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1409 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1410 		   offset, buf_size, bp->common.flash_size);
1411 		return -EINVAL;
1412 	}
1413 
1414 	/* request access to nvram interface */
1415 	rc = bnx2x_acquire_nvram_lock(bp);
1416 	if (rc)
1417 		return rc;
1418 
1419 	/* enable access to nvram interface */
1420 	bnx2x_enable_nvram_access(bp);
1421 
1422 	/* read the first word(s) */
1423 	cmd_flags = MCPR_NVM_COMMAND_FIRST;
1424 	while ((buf_size > sizeof(u32)) && (rc == 0)) {
1425 		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1426 		memcpy(ret_buf, &val, 4);
1427 
1428 		/* advance to the next dword */
1429 		offset += sizeof(u32);
1430 		ret_buf += sizeof(u32);
1431 		buf_size -= sizeof(u32);
1432 		cmd_flags = 0;
1433 	}
1434 
1435 	if (rc == 0) {
1436 		cmd_flags |= MCPR_NVM_COMMAND_LAST;
1437 		rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1438 		memcpy(ret_buf, &val, 4);
1439 	}
1440 
1441 	/* disable access to nvram interface */
1442 	bnx2x_disable_nvram_access(bp);
1443 	bnx2x_release_nvram_lock(bp);
1444 
1445 	return rc;
1446 }
1447 
1448 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1449 			      int buf_size)
1450 {
1451 	int rc;
1452 
1453 	rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1454 
1455 	if (!rc) {
1456 		__be32 *be = (__be32 *)buf;
1457 
1458 		while ((buf_size -= 4) >= 0)
1459 			*buf++ = be32_to_cpu(*be++);
1460 	}
1461 
1462 	return rc;
1463 }
1464 
1465 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1466 {
1467 	int rc = 1;
1468 	u16 pm = 0;
1469 	struct net_device *dev = pci_get_drvdata(bp->pdev);
1470 
1471 	if (bp->pdev->pm_cap)
1472 		rc = pci_read_config_word(bp->pdev,
1473 					  bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1474 
1475 	if ((rc && !netif_running(dev)) ||
1476 	    (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1477 		return false;
1478 
1479 	return true;
1480 }
1481 
1482 static int bnx2x_get_eeprom(struct net_device *dev,
1483 			    struct ethtool_eeprom *eeprom, u8 *eebuf)
1484 {
1485 	struct bnx2x *bp = netdev_priv(dev);
1486 
1487 	if (!bnx2x_is_nvm_accessible(bp)) {
1488 		DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1489 		   "cannot access eeprom when the interface is down\n");
1490 		return -EAGAIN;
1491 	}
1492 
1493 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1494 	   "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1495 	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1496 	   eeprom->len, eeprom->len);
1497 
1498 	/* parameters already validated in ethtool_get_eeprom */
1499 
1500 	return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1501 }
1502 
1503 static int bnx2x_get_module_eeprom(struct net_device *dev,
1504 				   struct ethtool_eeprom *ee,
1505 				   u8 *data)
1506 {
1507 	struct bnx2x *bp = netdev_priv(dev);
1508 	int rc = -EINVAL, phy_idx;
1509 	u8 *user_data = data;
1510 	unsigned int start_addr = ee->offset, xfer_size = 0;
1511 
1512 	if (!bnx2x_is_nvm_accessible(bp)) {
1513 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1514 		   "cannot access eeprom when the interface is down\n");
1515 		return -EAGAIN;
1516 	}
1517 
1518 	phy_idx = bnx2x_get_cur_phy_idx(bp);
1519 
1520 	/* Read A0 section */
1521 	if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1522 		/* Limit transfer size to the A0 section boundary */
1523 		if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1524 			xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1525 		else
1526 			xfer_size = ee->len;
1527 		bnx2x_acquire_phy_lock(bp);
1528 		rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1529 						  &bp->link_params,
1530 						  I2C_DEV_ADDR_A0,
1531 						  start_addr,
1532 						  xfer_size,
1533 						  user_data);
1534 		bnx2x_release_phy_lock(bp);
1535 		if (rc) {
1536 			DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1537 
1538 			return -EINVAL;
1539 		}
1540 		user_data += xfer_size;
1541 		start_addr += xfer_size;
1542 	}
1543 
1544 	/* Read A2 section */
1545 	if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1546 	    (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1547 		xfer_size = ee->len - xfer_size;
1548 		/* Limit transfer size to the A2 section boundary */
1549 		if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1550 			xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1551 		start_addr -= ETH_MODULE_SFF_8079_LEN;
1552 		bnx2x_acquire_phy_lock(bp);
1553 		rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1554 						  &bp->link_params,
1555 						  I2C_DEV_ADDR_A2,
1556 						  start_addr,
1557 						  xfer_size,
1558 						  user_data);
1559 		bnx2x_release_phy_lock(bp);
1560 		if (rc) {
1561 			DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1562 			return -EINVAL;
1563 		}
1564 	}
1565 	return rc;
1566 }
1567 
1568 static int bnx2x_get_module_info(struct net_device *dev,
1569 				 struct ethtool_modinfo *modinfo)
1570 {
1571 	struct bnx2x *bp = netdev_priv(dev);
1572 	int phy_idx, rc;
1573 	u8 sff8472_comp, diag_type;
1574 
1575 	if (!bnx2x_is_nvm_accessible(bp)) {
1576 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1577 		   "cannot access eeprom when the interface is down\n");
1578 		return -EAGAIN;
1579 	}
1580 	phy_idx = bnx2x_get_cur_phy_idx(bp);
1581 	bnx2x_acquire_phy_lock(bp);
1582 	rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1583 					  &bp->link_params,
1584 					  I2C_DEV_ADDR_A0,
1585 					  SFP_EEPROM_SFF_8472_COMP_ADDR,
1586 					  SFP_EEPROM_SFF_8472_COMP_SIZE,
1587 					  &sff8472_comp);
1588 	bnx2x_release_phy_lock(bp);
1589 	if (rc) {
1590 		DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1591 		return -EINVAL;
1592 	}
1593 
1594 	bnx2x_acquire_phy_lock(bp);
1595 	rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1596 					  &bp->link_params,
1597 					  I2C_DEV_ADDR_A0,
1598 					  SFP_EEPROM_DIAG_TYPE_ADDR,
1599 					  SFP_EEPROM_DIAG_TYPE_SIZE,
1600 					  &diag_type);
1601 	bnx2x_release_phy_lock(bp);
1602 	if (rc) {
1603 		DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1604 		return -EINVAL;
1605 	}
1606 
1607 	if (!sff8472_comp ||
1608 	    (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) ||
1609 	    !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) {
1610 		modinfo->type = ETH_MODULE_SFF_8079;
1611 		modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1612 	} else {
1613 		modinfo->type = ETH_MODULE_SFF_8472;
1614 		modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1615 	}
1616 	return 0;
1617 }
1618 
1619 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1620 				   u32 cmd_flags)
1621 {
1622 	int count, i, rc;
1623 
1624 	/* build the command word */
1625 	cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1626 
1627 	/* need to clear DONE bit separately */
1628 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1629 
1630 	/* write the data */
1631 	REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1632 
1633 	/* address of the NVRAM to write to */
1634 	REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1635 	       (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1636 
1637 	/* issue the write command */
1638 	REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1639 
1640 	/* adjust timeout for emulation/FPGA */
1641 	count = BNX2X_NVRAM_TIMEOUT_COUNT;
1642 	if (CHIP_REV_IS_SLOW(bp))
1643 		count *= 100;
1644 
1645 	/* wait for completion */
1646 	rc = -EBUSY;
1647 	for (i = 0; i < count; i++) {
1648 		udelay(5);
1649 		val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1650 		if (val & MCPR_NVM_COMMAND_DONE) {
1651 			rc = 0;
1652 			break;
1653 		}
1654 	}
1655 
1656 	if (rc == -EBUSY)
1657 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1658 		   "nvram write timeout expired\n");
1659 	return rc;
1660 }
1661 
1662 #define BYTE_OFFSET(offset)		(8 * (offset & 0x03))
1663 
1664 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1665 			      int buf_size)
1666 {
1667 	int rc;
1668 	u32 cmd_flags, align_offset, val;
1669 	__be32 val_be;
1670 
1671 	if (offset + buf_size > bp->common.flash_size) {
1672 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1673 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1674 		   offset, buf_size, bp->common.flash_size);
1675 		return -EINVAL;
1676 	}
1677 
1678 	/* request access to nvram interface */
1679 	rc = bnx2x_acquire_nvram_lock(bp);
1680 	if (rc)
1681 		return rc;
1682 
1683 	/* enable access to nvram interface */
1684 	bnx2x_enable_nvram_access(bp);
1685 
1686 	cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1687 	align_offset = (offset & ~0x03);
1688 	rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1689 
1690 	if (rc == 0) {
1691 		/* nvram data is returned as an array of bytes
1692 		 * convert it back to cpu order
1693 		 */
1694 		val = be32_to_cpu(val_be);
1695 
1696 		val &= ~le32_to_cpu((__force __le32)
1697 				    (0xff << BYTE_OFFSET(offset)));
1698 		val |= le32_to_cpu((__force __le32)
1699 				   (*data_buf << BYTE_OFFSET(offset)));
1700 
1701 		rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1702 					     cmd_flags);
1703 	}
1704 
1705 	/* disable access to nvram interface */
1706 	bnx2x_disable_nvram_access(bp);
1707 	bnx2x_release_nvram_lock(bp);
1708 
1709 	return rc;
1710 }
1711 
1712 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1713 			     int buf_size)
1714 {
1715 	int rc;
1716 	u32 cmd_flags;
1717 	u32 val;
1718 	u32 written_so_far;
1719 
1720 	if (buf_size == 1)	/* ethtool */
1721 		return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1722 
1723 	if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1724 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1725 		   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1726 		   offset, buf_size);
1727 		return -EINVAL;
1728 	}
1729 
1730 	if (offset + buf_size > bp->common.flash_size) {
1731 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1732 		   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1733 		   offset, buf_size, bp->common.flash_size);
1734 		return -EINVAL;
1735 	}
1736 
1737 	/* request access to nvram interface */
1738 	rc = bnx2x_acquire_nvram_lock(bp);
1739 	if (rc)
1740 		return rc;
1741 
1742 	/* enable access to nvram interface */
1743 	bnx2x_enable_nvram_access(bp);
1744 
1745 	written_so_far = 0;
1746 	cmd_flags = MCPR_NVM_COMMAND_FIRST;
1747 	while ((written_so_far < buf_size) && (rc == 0)) {
1748 		if (written_so_far == (buf_size - sizeof(u32)))
1749 			cmd_flags |= MCPR_NVM_COMMAND_LAST;
1750 		else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1751 			cmd_flags |= MCPR_NVM_COMMAND_LAST;
1752 		else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1753 			cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1754 
1755 		memcpy(&val, data_buf, 4);
1756 
1757 		/* Notice unlike bnx2x_nvram_read_dword() this will not
1758 		 * change val using be32_to_cpu(), which causes data to flip
1759 		 * if the eeprom is read and then written back. This is due
1760 		 * to tools utilizing this functionality that would break
1761 		 * if this would be resolved.
1762 		 */
1763 		rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1764 
1765 		/* advance to the next dword */
1766 		offset += sizeof(u32);
1767 		data_buf += sizeof(u32);
1768 		written_so_far += sizeof(u32);
1769 
1770 		/* At end of each 4Kb page, release nvram lock to allow MFW
1771 		 * chance to take it for its own use.
1772 		 */
1773 		if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1774 		    (written_so_far < buf_size)) {
1775 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1776 			   "Releasing NVM lock after offset 0x%x\n",
1777 			   (u32)(offset - sizeof(u32)));
1778 			bnx2x_release_nvram_lock(bp);
1779 			usleep_range(1000, 2000);
1780 			rc = bnx2x_acquire_nvram_lock(bp);
1781 			if (rc)
1782 				return rc;
1783 		}
1784 
1785 		cmd_flags = 0;
1786 	}
1787 
1788 	/* disable access to nvram interface */
1789 	bnx2x_disable_nvram_access(bp);
1790 	bnx2x_release_nvram_lock(bp);
1791 
1792 	return rc;
1793 }
1794 
1795 static int bnx2x_set_eeprom(struct net_device *dev,
1796 			    struct ethtool_eeprom *eeprom, u8 *eebuf)
1797 {
1798 	struct bnx2x *bp = netdev_priv(dev);
1799 	int port = BP_PORT(bp);
1800 	int rc = 0;
1801 	u32 ext_phy_config;
1802 
1803 	if (!bnx2x_is_nvm_accessible(bp)) {
1804 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1805 		   "cannot access eeprom when the interface is down\n");
1806 		return -EAGAIN;
1807 	}
1808 
1809 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1810 	   "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1811 	   eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1812 	   eeprom->len, eeprom->len);
1813 
1814 	/* parameters already validated in ethtool_set_eeprom */
1815 
1816 	/* PHY eeprom can be accessed only by the PMF */
1817 	if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1818 	    !bp->port.pmf) {
1819 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1820 		   "wrong magic or interface is not pmf\n");
1821 		return -EINVAL;
1822 	}
1823 
1824 	ext_phy_config =
1825 		SHMEM_RD(bp,
1826 			 dev_info.port_hw_config[port].external_phy_config);
1827 
1828 	if (eeprom->magic == 0x50485950) {
1829 		/* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1830 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1831 
1832 		bnx2x_acquire_phy_lock(bp);
1833 		rc |= bnx2x_link_reset(&bp->link_params,
1834 				       &bp->link_vars, 0);
1835 		if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1836 					PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1837 			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1838 				       MISC_REGISTERS_GPIO_HIGH, port);
1839 		bnx2x_release_phy_lock(bp);
1840 		bnx2x_link_report(bp);
1841 
1842 	} else if (eeprom->magic == 0x50485952) {
1843 		/* 'PHYR' (0x50485952): re-init link after FW upgrade */
1844 		if (bp->state == BNX2X_STATE_OPEN) {
1845 			bnx2x_acquire_phy_lock(bp);
1846 			rc |= bnx2x_link_reset(&bp->link_params,
1847 					       &bp->link_vars, 1);
1848 
1849 			rc |= bnx2x_phy_init(&bp->link_params,
1850 					     &bp->link_vars);
1851 			bnx2x_release_phy_lock(bp);
1852 			bnx2x_calc_fc_adv(bp);
1853 		}
1854 	} else if (eeprom->magic == 0x53985943) {
1855 		/* 'PHYC' (0x53985943): PHY FW upgrade completed */
1856 		if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1857 				       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1858 
1859 			/* DSP Remove Download Mode */
1860 			bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1861 				       MISC_REGISTERS_GPIO_LOW, port);
1862 
1863 			bnx2x_acquire_phy_lock(bp);
1864 
1865 			bnx2x_sfx7101_sp_sw_reset(bp,
1866 						&bp->link_params.phy[EXT_PHY1]);
1867 
1868 			/* wait 0.5 sec to allow it to run */
1869 			msleep(500);
1870 			bnx2x_ext_phy_hw_reset(bp, port);
1871 			msleep(500);
1872 			bnx2x_release_phy_lock(bp);
1873 		}
1874 	} else
1875 		rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1876 
1877 	return rc;
1878 }
1879 
1880 static int bnx2x_get_coalesce(struct net_device *dev,
1881 			      struct ethtool_coalesce *coal,
1882 			      struct kernel_ethtool_coalesce *kernel_coal,
1883 			      struct netlink_ext_ack *extack)
1884 {
1885 	struct bnx2x *bp = netdev_priv(dev);
1886 
1887 	memset(coal, 0, sizeof(struct ethtool_coalesce));
1888 
1889 	coal->rx_coalesce_usecs = bp->rx_ticks;
1890 	coal->tx_coalesce_usecs = bp->tx_ticks;
1891 
1892 	return 0;
1893 }
1894 
1895 static int bnx2x_set_coalesce(struct net_device *dev,
1896 			      struct ethtool_coalesce *coal,
1897 			      struct kernel_ethtool_coalesce *kernel_coal,
1898 			      struct netlink_ext_ack *extack)
1899 {
1900 	struct bnx2x *bp = netdev_priv(dev);
1901 
1902 	bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1903 	if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1904 		bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1905 
1906 	bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1907 	if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1908 		bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1909 
1910 	if (netif_running(dev))
1911 		bnx2x_update_coalesce(bp);
1912 
1913 	return 0;
1914 }
1915 
1916 static void bnx2x_get_ringparam(struct net_device *dev,
1917 				struct ethtool_ringparam *ering,
1918 				struct kernel_ethtool_ringparam *kernel_ering,
1919 				struct netlink_ext_ack *extack)
1920 {
1921 	struct bnx2x *bp = netdev_priv(dev);
1922 
1923 	ering->rx_max_pending = MAX_RX_AVAIL;
1924 
1925 	/* If size isn't already set, we give an estimation of the number
1926 	 * of buffers we'll have. We're neglecting some possible conditions
1927 	 * [we couldn't know for certain at this point if number of queues
1928 	 * might shrink] but the number would be correct for the likely
1929 	 * scenario.
1930 	 */
1931 	if (bp->rx_ring_size)
1932 		ering->rx_pending = bp->rx_ring_size;
1933 	else if (BNX2X_NUM_RX_QUEUES(bp))
1934 		ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1935 	else
1936 		ering->rx_pending = MAX_RX_AVAIL;
1937 
1938 	ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1939 	ering->tx_pending = bp->tx_ring_size;
1940 }
1941 
1942 static int bnx2x_set_ringparam(struct net_device *dev,
1943 			       struct ethtool_ringparam *ering,
1944 			       struct kernel_ethtool_ringparam *kernel_ering,
1945 			       struct netlink_ext_ack *extack)
1946 {
1947 	struct bnx2x *bp = netdev_priv(dev);
1948 
1949 	DP(BNX2X_MSG_ETHTOOL,
1950 	   "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1951 	   ering->rx_pending, ering->tx_pending);
1952 
1953 	if (pci_num_vf(bp->pdev)) {
1954 		DP(BNX2X_MSG_IOV,
1955 		   "VFs are enabled, can not change ring parameters\n");
1956 		return -EPERM;
1957 	}
1958 
1959 	if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1960 		DP(BNX2X_MSG_ETHTOOL,
1961 		   "Handling parity error recovery. Try again later\n");
1962 		return -EAGAIN;
1963 	}
1964 
1965 	if ((ering->rx_pending > MAX_RX_AVAIL) ||
1966 	    (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1967 						    MIN_RX_SIZE_TPA)) ||
1968 	    (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1969 	    (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1970 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1971 		return -EINVAL;
1972 	}
1973 
1974 	bp->rx_ring_size = ering->rx_pending;
1975 	bp->tx_ring_size = ering->tx_pending;
1976 
1977 	return bnx2x_reload_if_running(dev);
1978 }
1979 
1980 static void bnx2x_get_pauseparam(struct net_device *dev,
1981 				 struct ethtool_pauseparam *epause)
1982 {
1983 	struct bnx2x *bp = netdev_priv(dev);
1984 	int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1985 	int cfg_reg;
1986 
1987 	epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1988 			   BNX2X_FLOW_CTRL_AUTO);
1989 
1990 	if (!epause->autoneg)
1991 		cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1992 	else
1993 		cfg_reg = bp->link_params.req_fc_auto_adv;
1994 
1995 	epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1996 			    BNX2X_FLOW_CTRL_RX);
1997 	epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1998 			    BNX2X_FLOW_CTRL_TX);
1999 
2000 	DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
2001 	   "  autoneg %d  rx_pause %d  tx_pause %d\n",
2002 	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
2003 }
2004 
2005 static int bnx2x_set_pauseparam(struct net_device *dev,
2006 				struct ethtool_pauseparam *epause)
2007 {
2008 	struct bnx2x *bp = netdev_priv(dev);
2009 	u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2010 	if (IS_MF(bp))
2011 		return 0;
2012 
2013 	DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
2014 	   "  autoneg %d  rx_pause %d  tx_pause %d\n",
2015 	   epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
2016 
2017 	bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
2018 
2019 	if (epause->rx_pause)
2020 		bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
2021 
2022 	if (epause->tx_pause)
2023 		bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
2024 
2025 	if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
2026 		bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
2027 
2028 	if (epause->autoneg) {
2029 		if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
2030 			DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
2031 			return -EINVAL;
2032 		}
2033 
2034 		if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
2035 			bp->link_params.req_flow_ctrl[cfg_idx] =
2036 				BNX2X_FLOW_CTRL_AUTO;
2037 		}
2038 		bp->link_params.req_fc_auto_adv = 0;
2039 		if (epause->rx_pause)
2040 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
2041 
2042 		if (epause->tx_pause)
2043 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
2044 
2045 		if (!bp->link_params.req_fc_auto_adv)
2046 			bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
2047 	}
2048 
2049 	DP(BNX2X_MSG_ETHTOOL,
2050 	   "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
2051 
2052 	if (netif_running(dev)) {
2053 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2054 		bnx2x_force_link_reset(bp);
2055 		bnx2x_link_set(bp);
2056 	}
2057 
2058 	return 0;
2059 }
2060 
2061 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2062 	"register_test (offline)    ",
2063 	"memory_test (offline)      ",
2064 	"int_loopback_test (offline)",
2065 	"ext_loopback_test (offline)",
2066 	"nvram_test (online)        ",
2067 	"interrupt_test (online)    ",
2068 	"link_test (online)         "
2069 };
2070 
2071 enum {
2072 	BNX2X_PRI_FLAG_ISCSI,
2073 	BNX2X_PRI_FLAG_FCOE,
2074 	BNX2X_PRI_FLAG_STORAGE,
2075 	BNX2X_PRI_FLAG_LEN,
2076 };
2077 
2078 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2079 	"iSCSI offload support",
2080 	"FCoE offload support",
2081 	"Storage only interface"
2082 };
2083 
2084 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2085 {
2086 	u32 modes = 0;
2087 
2088 	if (eee_adv & SHMEM_EEE_100M_ADV)
2089 		modes |= ADVERTISED_100baseT_Full;
2090 	if (eee_adv & SHMEM_EEE_1G_ADV)
2091 		modes |= ADVERTISED_1000baseT_Full;
2092 	if (eee_adv & SHMEM_EEE_10G_ADV)
2093 		modes |= ADVERTISED_10000baseT_Full;
2094 
2095 	return modes;
2096 }
2097 
2098 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2099 {
2100 	u32 eee_adv = 0;
2101 	if (modes & ADVERTISED_100baseT_Full)
2102 		eee_adv |= SHMEM_EEE_100M_ADV;
2103 	if (modes & ADVERTISED_1000baseT_Full)
2104 		eee_adv |= SHMEM_EEE_1G_ADV;
2105 	if (modes & ADVERTISED_10000baseT_Full)
2106 		eee_adv |= SHMEM_EEE_10G_ADV;
2107 
2108 	return eee_adv << shift;
2109 }
2110 
2111 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2112 {
2113 	struct bnx2x *bp = netdev_priv(dev);
2114 	u32 eee_cfg;
2115 
2116 	if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2117 		DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2118 		return -EOPNOTSUPP;
2119 	}
2120 
2121 	eee_cfg = bp->link_vars.eee_status;
2122 
2123 	edata->supported =
2124 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2125 				 SHMEM_EEE_SUPPORTED_SHIFT);
2126 
2127 	edata->advertised =
2128 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2129 				 SHMEM_EEE_ADV_STATUS_SHIFT);
2130 	edata->lp_advertised =
2131 		bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2132 				 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2133 
2134 	/* SHMEM value is in 16u units --> Convert to 1u units. */
2135 	edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2136 
2137 	edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)	? 1 : 0;
2138 	edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)	? 1 : 0;
2139 	edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2140 
2141 	return 0;
2142 }
2143 
2144 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2145 {
2146 	struct bnx2x *bp = netdev_priv(dev);
2147 	u32 eee_cfg;
2148 	u32 advertised;
2149 
2150 	if (IS_MF(bp))
2151 		return 0;
2152 
2153 	if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2154 		DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2155 		return -EOPNOTSUPP;
2156 	}
2157 
2158 	eee_cfg = bp->link_vars.eee_status;
2159 
2160 	if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2161 		DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2162 		return -EOPNOTSUPP;
2163 	}
2164 
2165 	advertised = bnx2x_adv_to_eee(edata->advertised,
2166 				      SHMEM_EEE_ADV_STATUS_SHIFT);
2167 	if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2168 		DP(BNX2X_MSG_ETHTOOL,
2169 		   "Direct manipulation of EEE advertisement is not supported\n");
2170 		return -EINVAL;
2171 	}
2172 
2173 	if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2174 		DP(BNX2X_MSG_ETHTOOL,
2175 		   "Maximal Tx Lpi timer supported is %x(u)\n",
2176 		   EEE_MODE_TIMER_MASK);
2177 		return -EINVAL;
2178 	}
2179 	if (edata->tx_lpi_enabled &&
2180 	    (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2181 		DP(BNX2X_MSG_ETHTOOL,
2182 		   "Minimal Tx Lpi timer supported is %d(u)\n",
2183 		   EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2184 		return -EINVAL;
2185 	}
2186 
2187 	/* All is well; Apply changes*/
2188 	if (edata->eee_enabled)
2189 		bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2190 	else
2191 		bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2192 
2193 	if (edata->tx_lpi_enabled)
2194 		bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2195 	else
2196 		bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2197 
2198 	bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2199 	bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2200 				    EEE_MODE_TIMER_MASK) |
2201 				    EEE_MODE_OVERRIDE_NVRAM |
2202 				    EEE_MODE_OUTPUT_TIME;
2203 
2204 	/* Restart link to propagate changes */
2205 	if (netif_running(dev)) {
2206 		bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2207 		bnx2x_force_link_reset(bp);
2208 		bnx2x_link_set(bp);
2209 	}
2210 
2211 	return 0;
2212 }
2213 
2214 enum {
2215 	BNX2X_CHIP_E1_OFST = 0,
2216 	BNX2X_CHIP_E1H_OFST,
2217 	BNX2X_CHIP_E2_OFST,
2218 	BNX2X_CHIP_E3_OFST,
2219 	BNX2X_CHIP_E3B0_OFST,
2220 	BNX2X_CHIP_MAX_OFST
2221 };
2222 
2223 #define BNX2X_CHIP_MASK_E1	(1 << BNX2X_CHIP_E1_OFST)
2224 #define BNX2X_CHIP_MASK_E1H	(1 << BNX2X_CHIP_E1H_OFST)
2225 #define BNX2X_CHIP_MASK_E2	(1 << BNX2X_CHIP_E2_OFST)
2226 #define BNX2X_CHIP_MASK_E3	(1 << BNX2X_CHIP_E3_OFST)
2227 #define BNX2X_CHIP_MASK_E3B0	(1 << BNX2X_CHIP_E3B0_OFST)
2228 
2229 #define BNX2X_CHIP_MASK_ALL	((1 << BNX2X_CHIP_MAX_OFST) - 1)
2230 #define BNX2X_CHIP_MASK_E1X	(BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2231 
2232 static int bnx2x_test_registers(struct bnx2x *bp)
2233 {
2234 	int idx, i, rc = -ENODEV;
2235 	u32 wr_val = 0, hw;
2236 	int port = BP_PORT(bp);
2237 	static const struct {
2238 		u32 hw;
2239 		u32 offset0;
2240 		u32 offset1;
2241 		u32 mask;
2242 	} reg_tbl[] = {
2243 /* 0 */		{ BNX2X_CHIP_MASK_ALL,
2244 			BRB1_REG_PAUSE_LOW_THRESHOLD_0,	4, 0x000003ff },
2245 		{ BNX2X_CHIP_MASK_ALL,
2246 			DORQ_REG_DB_ADDR0,		4, 0xffffffff },
2247 		{ BNX2X_CHIP_MASK_E1X,
2248 			HC_REG_AGG_INT_0,		4, 0x000003ff },
2249 		{ BNX2X_CHIP_MASK_ALL,
2250 			PBF_REG_MAC_IF0_ENABLE,		4, 0x00000001 },
2251 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2252 			PBF_REG_P0_INIT_CRD,		4, 0x000007ff },
2253 		{ BNX2X_CHIP_MASK_E3B0,
2254 			PBF_REG_INIT_CRD_Q0,		4, 0x000007ff },
2255 		{ BNX2X_CHIP_MASK_ALL,
2256 			PRS_REG_CID_PORT_0,		4, 0x00ffffff },
2257 		{ BNX2X_CHIP_MASK_ALL,
2258 			PXP2_REG_PSWRQ_CDU0_L2P,	4, 0x000fffff },
2259 		{ BNX2X_CHIP_MASK_ALL,
2260 			PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2261 		{ BNX2X_CHIP_MASK_ALL,
2262 			PXP2_REG_PSWRQ_TM0_L2P,		4, 0x000fffff },
2263 /* 10 */	{ BNX2X_CHIP_MASK_ALL,
2264 			PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2265 		{ BNX2X_CHIP_MASK_ALL,
2266 			PXP2_REG_PSWRQ_TSDM0_L2P,	4, 0x000fffff },
2267 		{ BNX2X_CHIP_MASK_ALL,
2268 			QM_REG_CONNNUM_0,		4, 0x000fffff },
2269 		{ BNX2X_CHIP_MASK_ALL,
2270 			TM_REG_LIN0_MAX_ACTIVE_CID,	4, 0x0003ffff },
2271 		{ BNX2X_CHIP_MASK_ALL,
2272 			SRC_REG_KEYRSS0_0,		40, 0xffffffff },
2273 		{ BNX2X_CHIP_MASK_ALL,
2274 			SRC_REG_KEYRSS0_7,		40, 0xffffffff },
2275 		{ BNX2X_CHIP_MASK_ALL,
2276 			XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2277 		{ BNX2X_CHIP_MASK_ALL,
2278 			XCM_REG_WU_DA_CNT_CMD00,	4, 0x00000003 },
2279 		{ BNX2X_CHIP_MASK_ALL,
2280 			XCM_REG_GLB_DEL_ACK_MAX_CNT_0,	4, 0x000000ff },
2281 		{ BNX2X_CHIP_MASK_ALL,
2282 			NIG_REG_LLH0_T_BIT,		4, 0x00000001 },
2283 /* 20 */	{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2284 			NIG_REG_EMAC0_IN_EN,		4, 0x00000001 },
2285 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2286 			NIG_REG_BMAC0_IN_EN,		4, 0x00000001 },
2287 		{ BNX2X_CHIP_MASK_ALL,
2288 			NIG_REG_XCM0_OUT_EN,		4, 0x00000001 },
2289 		{ BNX2X_CHIP_MASK_ALL,
2290 			NIG_REG_BRB0_OUT_EN,		4, 0x00000001 },
2291 		{ BNX2X_CHIP_MASK_ALL,
2292 			NIG_REG_LLH0_XCM_MASK,		4, 0x00000007 },
2293 		{ BNX2X_CHIP_MASK_ALL,
2294 			NIG_REG_LLH0_ACPI_PAT_6_LEN,	68, 0x000000ff },
2295 		{ BNX2X_CHIP_MASK_ALL,
2296 			NIG_REG_LLH0_ACPI_PAT_0_CRC,	68, 0xffffffff },
2297 		{ BNX2X_CHIP_MASK_ALL,
2298 			NIG_REG_LLH0_DEST_MAC_0_0,	160, 0xffffffff },
2299 		{ BNX2X_CHIP_MASK_ALL,
2300 			NIG_REG_LLH0_DEST_IP_0_1,	160, 0xffffffff },
2301 		{ BNX2X_CHIP_MASK_ALL,
2302 			NIG_REG_LLH0_IPV4_IPV6_0,	160, 0x00000001 },
2303 /* 30 */	{ BNX2X_CHIP_MASK_ALL,
2304 			NIG_REG_LLH0_DEST_UDP_0,	160, 0x0000ffff },
2305 		{ BNX2X_CHIP_MASK_ALL,
2306 			NIG_REG_LLH0_DEST_TCP_0,	160, 0x0000ffff },
2307 		{ BNX2X_CHIP_MASK_ALL,
2308 			NIG_REG_LLH0_VLAN_ID_0,	160, 0x00000fff },
2309 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2310 			NIG_REG_XGXS_SERDES0_MODE_SEL,	4, 0x00000001 },
2311 		{ BNX2X_CHIP_MASK_ALL,
2312 			NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2313 		{ BNX2X_CHIP_MASK_ALL,
2314 			NIG_REG_STATUS_INTERRUPT_PORT0,	4, 0x07ffffff },
2315 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2316 			NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2317 		{ BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2318 			NIG_REG_SERDES0_CTRL_PHY_ADDR,	16, 0x0000001f },
2319 
2320 		{ BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2321 	};
2322 
2323 	if (!bnx2x_is_nvm_accessible(bp)) {
2324 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2325 		   "cannot access eeprom when the interface is down\n");
2326 		return rc;
2327 	}
2328 
2329 	if (CHIP_IS_E1(bp))
2330 		hw = BNX2X_CHIP_MASK_E1;
2331 	else if (CHIP_IS_E1H(bp))
2332 		hw = BNX2X_CHIP_MASK_E1H;
2333 	else if (CHIP_IS_E2(bp))
2334 		hw = BNX2X_CHIP_MASK_E2;
2335 	else if (CHIP_IS_E3B0(bp))
2336 		hw = BNX2X_CHIP_MASK_E3B0;
2337 	else /* e3 A0 */
2338 		hw = BNX2X_CHIP_MASK_E3;
2339 
2340 	/* Repeat the test twice:
2341 	 * First by writing 0x00000000, second by writing 0xffffffff
2342 	 */
2343 	for (idx = 0; idx < 2; idx++) {
2344 
2345 		switch (idx) {
2346 		case 0:
2347 			wr_val = 0;
2348 			break;
2349 		case 1:
2350 			wr_val = 0xffffffff;
2351 			break;
2352 		}
2353 
2354 		for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2355 			u32 offset, mask, save_val, val;
2356 			if (!(hw & reg_tbl[i].hw))
2357 				continue;
2358 
2359 			offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2360 			mask = reg_tbl[i].mask;
2361 
2362 			save_val = REG_RD(bp, offset);
2363 
2364 			REG_WR(bp, offset, wr_val & mask);
2365 
2366 			val = REG_RD(bp, offset);
2367 
2368 			/* Restore the original register's value */
2369 			REG_WR(bp, offset, save_val);
2370 
2371 			/* verify value is as expected */
2372 			if ((val & mask) != (wr_val & mask)) {
2373 				DP(BNX2X_MSG_ETHTOOL,
2374 				   "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2375 				   offset, val, wr_val, mask);
2376 				goto test_reg_exit;
2377 			}
2378 		}
2379 	}
2380 
2381 	rc = 0;
2382 
2383 test_reg_exit:
2384 	return rc;
2385 }
2386 
2387 static int bnx2x_test_memory(struct bnx2x *bp)
2388 {
2389 	int i, j, rc = -ENODEV;
2390 	u32 val, index;
2391 	static const struct {
2392 		u32 offset;
2393 		int size;
2394 	} mem_tbl[] = {
2395 		{ CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2396 		{ CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2397 		{ CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2398 		{ DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2399 		{ TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2400 		{ UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2401 		{ XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2402 
2403 		{ 0xffffffff, 0 }
2404 	};
2405 
2406 	static const struct {
2407 		char *name;
2408 		u32 offset;
2409 		u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2410 	} prty_tbl[] = {
2411 		{ "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2412 			{0x3ffc0, 0,   0, 0} },
2413 		{ "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2414 			{0x2,     0x2, 0, 0} },
2415 		{ "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2416 			{0,       0,   0, 0} },
2417 		{ "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2418 			{0x3ffc0, 0,   0, 0} },
2419 		{ "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2420 			{0x3ffc0, 0,   0, 0} },
2421 		{ "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2422 			{0x3ffc1, 0,   0, 0} },
2423 
2424 		{ NULL, 0xffffffff, {0, 0, 0, 0} }
2425 	};
2426 
2427 	if (!bnx2x_is_nvm_accessible(bp)) {
2428 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2429 		   "cannot access eeprom when the interface is down\n");
2430 		return rc;
2431 	}
2432 
2433 	if (CHIP_IS_E1(bp))
2434 		index = BNX2X_CHIP_E1_OFST;
2435 	else if (CHIP_IS_E1H(bp))
2436 		index = BNX2X_CHIP_E1H_OFST;
2437 	else if (CHIP_IS_E2(bp))
2438 		index = BNX2X_CHIP_E2_OFST;
2439 	else /* e3 */
2440 		index = BNX2X_CHIP_E3_OFST;
2441 
2442 	/* pre-Check the parity status */
2443 	for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2444 		val = REG_RD(bp, prty_tbl[i].offset);
2445 		if (val & ~(prty_tbl[i].hw_mask[index])) {
2446 			DP(BNX2X_MSG_ETHTOOL,
2447 			   "%s is 0x%x\n", prty_tbl[i].name, val);
2448 			goto test_mem_exit;
2449 		}
2450 	}
2451 
2452 	/* Go through all the memories */
2453 	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2454 		for (j = 0; j < mem_tbl[i].size; j++)
2455 			REG_RD(bp, mem_tbl[i].offset + j*4);
2456 
2457 	/* Check the parity status */
2458 	for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2459 		val = REG_RD(bp, prty_tbl[i].offset);
2460 		if (val & ~(prty_tbl[i].hw_mask[index])) {
2461 			DP(BNX2X_MSG_ETHTOOL,
2462 			   "%s is 0x%x\n", prty_tbl[i].name, val);
2463 			goto test_mem_exit;
2464 		}
2465 	}
2466 
2467 	rc = 0;
2468 
2469 test_mem_exit:
2470 	return rc;
2471 }
2472 
2473 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2474 {
2475 	int cnt = 1400;
2476 
2477 	if (link_up) {
2478 		while (bnx2x_link_test(bp, is_serdes) && cnt--)
2479 			msleep(20);
2480 
2481 		if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2482 			DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2483 
2484 		cnt = 1400;
2485 		while (!bp->link_vars.link_up && cnt--)
2486 			msleep(20);
2487 
2488 		if (cnt <= 0 && !bp->link_vars.link_up)
2489 			DP(BNX2X_MSG_ETHTOOL,
2490 			   "Timeout waiting for link init\n");
2491 	}
2492 }
2493 
2494 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2495 {
2496 	unsigned int pkt_size, num_pkts, i;
2497 	struct sk_buff *skb;
2498 	unsigned char *packet;
2499 	struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2500 	struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2501 	struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2502 	u16 tx_start_idx, tx_idx;
2503 	u16 rx_start_idx, rx_idx;
2504 	u16 pkt_prod, bd_prod;
2505 	struct sw_tx_bd *tx_buf;
2506 	struct eth_tx_start_bd *tx_start_bd;
2507 	dma_addr_t mapping;
2508 	union eth_rx_cqe *cqe;
2509 	u8 cqe_fp_flags, cqe_fp_type;
2510 	struct sw_rx_bd *rx_buf;
2511 	u16 len;
2512 	int rc = -ENODEV;
2513 	u8 *data;
2514 	struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2515 						       txdata->txq_index);
2516 
2517 	/* check the loopback mode */
2518 	switch (loopback_mode) {
2519 	case BNX2X_PHY_LOOPBACK:
2520 		if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2521 			DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2522 			return -EINVAL;
2523 		}
2524 		break;
2525 	case BNX2X_MAC_LOOPBACK:
2526 		if (CHIP_IS_E3(bp)) {
2527 			int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2528 			if (bp->port.supported[cfg_idx] &
2529 			    (SUPPORTED_10000baseT_Full |
2530 			     SUPPORTED_20000baseMLD2_Full |
2531 			     SUPPORTED_20000baseKR2_Full))
2532 				bp->link_params.loopback_mode = LOOPBACK_XMAC;
2533 			else
2534 				bp->link_params.loopback_mode = LOOPBACK_UMAC;
2535 		} else
2536 			bp->link_params.loopback_mode = LOOPBACK_BMAC;
2537 
2538 		bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2539 		break;
2540 	case BNX2X_EXT_LOOPBACK:
2541 		if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2542 			DP(BNX2X_MSG_ETHTOOL,
2543 			   "Can't configure external loopback\n");
2544 			return -EINVAL;
2545 		}
2546 		break;
2547 	default:
2548 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2549 		return -EINVAL;
2550 	}
2551 
2552 	/* prepare the loopback packet */
2553 	pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2554 		     bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2555 	skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2556 	if (!skb) {
2557 		DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2558 		rc = -ENOMEM;
2559 		goto test_loopback_exit;
2560 	}
2561 	packet = skb_put(skb, pkt_size);
2562 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2563 	eth_zero_addr(packet + ETH_ALEN);
2564 	memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2565 	for (i = ETH_HLEN; i < pkt_size; i++)
2566 		packet[i] = (unsigned char) (i & 0xff);
2567 	mapping = dma_map_single(&bp->pdev->dev, skb->data,
2568 				 skb_headlen(skb), DMA_TO_DEVICE);
2569 	if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2570 		rc = -ENOMEM;
2571 		dev_kfree_skb(skb);
2572 		DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2573 		goto test_loopback_exit;
2574 	}
2575 
2576 	/* send the loopback packet */
2577 	num_pkts = 0;
2578 	tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2579 	rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2580 
2581 	netdev_tx_sent_queue(txq, skb->len);
2582 
2583 	pkt_prod = txdata->tx_pkt_prod++;
2584 	tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2585 	tx_buf->first_bd = txdata->tx_bd_prod;
2586 	tx_buf->skb = skb;
2587 	tx_buf->flags = 0;
2588 
2589 	bd_prod = TX_BD(txdata->tx_bd_prod);
2590 	tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2591 	tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2592 	tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2593 	tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2594 	tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2595 	tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2596 	tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2597 	SET_FLAG(tx_start_bd->general_data,
2598 		 ETH_TX_START_BD_HDR_NBDS,
2599 		 1);
2600 	SET_FLAG(tx_start_bd->general_data,
2601 		 ETH_TX_START_BD_PARSE_NBDS,
2602 		 0);
2603 
2604 	/* turn on parsing and get a BD */
2605 	bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2606 
2607 	if (CHIP_IS_E1x(bp)) {
2608 		u16 global_data = 0;
2609 		struct eth_tx_parse_bd_e1x  *pbd_e1x =
2610 			&txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2611 		memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2612 		SET_FLAG(global_data,
2613 			 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2614 		pbd_e1x->global_data = cpu_to_le16(global_data);
2615 	} else {
2616 		u32 parsing_data = 0;
2617 		struct eth_tx_parse_bd_e2  *pbd_e2 =
2618 			&txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2619 		memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2620 		SET_FLAG(parsing_data,
2621 			 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2622 		pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2623 	}
2624 	wmb();
2625 
2626 	txdata->tx_db.data.prod += 2;
2627 	/* make sure descriptor update is observed by the HW */
2628 	wmb();
2629 	DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
2630 
2631 	barrier();
2632 
2633 	num_pkts++;
2634 	txdata->tx_bd_prod += 2; /* start + pbd */
2635 
2636 	udelay(100);
2637 
2638 	tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2639 	if (tx_idx != tx_start_idx + num_pkts)
2640 		goto test_loopback_exit;
2641 
2642 	/* Unlike HC IGU won't generate an interrupt for status block
2643 	 * updates that have been performed while interrupts were
2644 	 * disabled.
2645 	 */
2646 	if (bp->common.int_block == INT_BLOCK_IGU) {
2647 		/* Disable local BHes to prevent a dead-lock situation between
2648 		 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2649 		 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2650 		 */
2651 		local_bh_disable();
2652 		bnx2x_tx_int(bp, txdata);
2653 		local_bh_enable();
2654 	}
2655 
2656 	rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2657 	if (rx_idx != rx_start_idx + num_pkts)
2658 		goto test_loopback_exit;
2659 
2660 	cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2661 	cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2662 	cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2663 	if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2664 		goto test_loopback_rx_exit;
2665 
2666 	len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2667 	if (len != pkt_size)
2668 		goto test_loopback_rx_exit;
2669 
2670 	rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2671 	dma_sync_single_for_cpu(&bp->pdev->dev,
2672 				   dma_unmap_addr(rx_buf, mapping),
2673 				   fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2674 	data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2675 	for (i = ETH_HLEN; i < pkt_size; i++)
2676 		if (*(data + i) != (unsigned char) (i & 0xff))
2677 			goto test_loopback_rx_exit;
2678 
2679 	rc = 0;
2680 
2681 test_loopback_rx_exit:
2682 
2683 	fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2684 	fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2685 	fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2686 	fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2687 
2688 	/* Update producers */
2689 	bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2690 			     fp_rx->rx_sge_prod);
2691 
2692 test_loopback_exit:
2693 	bp->link_params.loopback_mode = LOOPBACK_NONE;
2694 
2695 	return rc;
2696 }
2697 
2698 static int bnx2x_test_loopback(struct bnx2x *bp)
2699 {
2700 	int rc = 0, res;
2701 
2702 	if (BP_NOMCP(bp))
2703 		return rc;
2704 
2705 	if (!netif_running(bp->dev))
2706 		return BNX2X_LOOPBACK_FAILED;
2707 
2708 	bnx2x_netif_stop(bp, 1);
2709 	bnx2x_acquire_phy_lock(bp);
2710 
2711 	res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2712 	if (res) {
2713 		DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2714 		rc |= BNX2X_PHY_LOOPBACK_FAILED;
2715 	}
2716 
2717 	res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2718 	if (res) {
2719 		DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2720 		rc |= BNX2X_MAC_LOOPBACK_FAILED;
2721 	}
2722 
2723 	bnx2x_release_phy_lock(bp);
2724 	bnx2x_netif_start(bp);
2725 
2726 	return rc;
2727 }
2728 
2729 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2730 {
2731 	int rc;
2732 	u8 is_serdes =
2733 		(bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2734 
2735 	if (BP_NOMCP(bp))
2736 		return -ENODEV;
2737 
2738 	if (!netif_running(bp->dev))
2739 		return BNX2X_EXT_LOOPBACK_FAILED;
2740 
2741 	bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2742 	rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2743 	if (rc) {
2744 		DP(BNX2X_MSG_ETHTOOL,
2745 		   "Can't perform self-test, nic_load (for external lb) failed\n");
2746 		return -ENODEV;
2747 	}
2748 	bnx2x_wait_for_link(bp, 1, is_serdes);
2749 
2750 	bnx2x_netif_stop(bp, 1);
2751 
2752 	rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2753 	if (rc)
2754 		DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2755 
2756 	bnx2x_netif_start(bp);
2757 
2758 	return rc;
2759 }
2760 
2761 struct code_entry {
2762 	u32 sram_start_addr;
2763 	u32 code_attribute;
2764 #define CODE_IMAGE_TYPE_MASK			0xf0800003
2765 #define CODE_IMAGE_VNTAG_PROFILES_DATA		0xd0000003
2766 #define CODE_IMAGE_LENGTH_MASK			0x007ffffc
2767 #define CODE_IMAGE_TYPE_EXTENDED_DIR		0xe0000000
2768 	u32 nvm_start_addr;
2769 };
2770 
2771 #define CODE_ENTRY_MAX			16
2772 #define CODE_ENTRY_EXTENDED_DIR_IDX	15
2773 #define MAX_IMAGES_IN_EXTENDED_DIR	64
2774 #define NVRAM_DIR_OFFSET		0x14
2775 
2776 #define EXTENDED_DIR_EXISTS(code)					  \
2777 	((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2778 	 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2779 
2780 #define CRC32_RESIDUAL			0xdebb20e3
2781 #define CRC_BUFF_SIZE			256
2782 
2783 static int bnx2x_nvram_crc(struct bnx2x *bp,
2784 			   int offset,
2785 			   int size,
2786 			   u8 *buff)
2787 {
2788 	u32 crc = ~0;
2789 	int rc = 0, done = 0;
2790 
2791 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2792 	   "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2793 
2794 	while (done < size) {
2795 		int count = min_t(int, size - done, CRC_BUFF_SIZE);
2796 
2797 		rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2798 
2799 		if (rc)
2800 			return rc;
2801 
2802 		crc = crc32_le(crc, buff, count);
2803 		done += count;
2804 	}
2805 
2806 	if (crc != CRC32_RESIDUAL)
2807 		rc = -EINVAL;
2808 
2809 	return rc;
2810 }
2811 
2812 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2813 				struct code_entry *entry,
2814 				u8 *buff)
2815 {
2816 	size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2817 	u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2818 	int rc;
2819 
2820 	/* Zero-length images and AFEX profiles do not have CRC */
2821 	if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2822 		return 0;
2823 
2824 	rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2825 	if (rc)
2826 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2827 		   "image %x has failed crc test (rc %d)\n", type, rc);
2828 
2829 	return rc;
2830 }
2831 
2832 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2833 {
2834 	int rc;
2835 	struct code_entry entry;
2836 
2837 	rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2838 	if (rc)
2839 		return rc;
2840 
2841 	return bnx2x_test_nvram_dir(bp, &entry, buff);
2842 }
2843 
2844 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2845 {
2846 	u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2847 	struct code_entry entry;
2848 	int i;
2849 
2850 	rc = bnx2x_nvram_read32(bp,
2851 				dir_offset +
2852 				sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2853 				(u32 *)&entry, sizeof(entry));
2854 	if (rc)
2855 		return rc;
2856 
2857 	if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2858 		return 0;
2859 
2860 	rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2861 				&cnt, sizeof(u32));
2862 	if (rc)
2863 		return rc;
2864 
2865 	dir_offset = entry.nvm_start_addr + 8;
2866 
2867 	for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2868 		rc = bnx2x_test_dir_entry(bp, dir_offset +
2869 					      sizeof(struct code_entry) * i,
2870 					  buff);
2871 		if (rc)
2872 			return rc;
2873 	}
2874 
2875 	return 0;
2876 }
2877 
2878 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2879 {
2880 	u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2881 	int i;
2882 
2883 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2884 
2885 	for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2886 		rc = bnx2x_test_dir_entry(bp, dir_offset +
2887 					      sizeof(struct code_entry) * i,
2888 					  buff);
2889 		if (rc)
2890 			return rc;
2891 	}
2892 
2893 	return bnx2x_test_nvram_ext_dirs(bp, buff);
2894 }
2895 
2896 struct crc_pair {
2897 	int offset;
2898 	int size;
2899 };
2900 
2901 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2902 				const struct crc_pair *nvram_tbl, u8 *buf)
2903 {
2904 	int i;
2905 
2906 	for (i = 0; nvram_tbl[i].size; i++) {
2907 		int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2908 					 nvram_tbl[i].size, buf);
2909 		if (rc) {
2910 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2911 			   "nvram_tbl[%d] has failed crc test (rc %d)\n",
2912 			   i, rc);
2913 			return rc;
2914 		}
2915 	}
2916 
2917 	return 0;
2918 }
2919 
2920 static int bnx2x_test_nvram(struct bnx2x *bp)
2921 {
2922 	static const struct crc_pair nvram_tbl[] = {
2923 		{     0,  0x14 }, /* bootstrap */
2924 		{  0x14,  0xec }, /* dir */
2925 		{ 0x100, 0x350 }, /* manuf_info */
2926 		{ 0x450,  0xf0 }, /* feature_info */
2927 		{ 0x640,  0x64 }, /* upgrade_key_info */
2928 		{ 0x708,  0x70 }, /* manuf_key_info */
2929 		{     0,     0 }
2930 	};
2931 	static const struct crc_pair nvram_tbl2[] = {
2932 		{ 0x7e8, 0x350 }, /* manuf_info2 */
2933 		{ 0xb38,  0xf0 }, /* feature_info */
2934 		{     0,     0 }
2935 	};
2936 
2937 	u8 *buf;
2938 	int rc;
2939 	u32 magic;
2940 
2941 	if (BP_NOMCP(bp))
2942 		return 0;
2943 
2944 	buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2945 	if (!buf) {
2946 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2947 		rc = -ENOMEM;
2948 		goto test_nvram_exit;
2949 	}
2950 
2951 	rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2952 	if (rc) {
2953 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2954 		   "magic value read (rc %d)\n", rc);
2955 		goto test_nvram_exit;
2956 	}
2957 
2958 	if (magic != 0x669955aa) {
2959 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2960 		   "wrong magic value (0x%08x)\n", magic);
2961 		rc = -ENODEV;
2962 		goto test_nvram_exit;
2963 	}
2964 
2965 	DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2966 	rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2967 	if (rc)
2968 		goto test_nvram_exit;
2969 
2970 	if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2971 		u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2972 			   SHARED_HW_CFG_HIDE_PORT1;
2973 
2974 		if (!hide) {
2975 			DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2976 			   "Port 1 CRC test-set\n");
2977 			rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2978 			if (rc)
2979 				goto test_nvram_exit;
2980 		}
2981 	}
2982 
2983 	rc = bnx2x_test_nvram_dirs(bp, buf);
2984 
2985 test_nvram_exit:
2986 	kfree(buf);
2987 	return rc;
2988 }
2989 
2990 /* Send an EMPTY ramrod on the first queue */
2991 static int bnx2x_test_intr(struct bnx2x *bp)
2992 {
2993 	struct bnx2x_queue_state_params params = {NULL};
2994 
2995 	if (!netif_running(bp->dev)) {
2996 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2997 		   "cannot access eeprom when the interface is down\n");
2998 		return -ENODEV;
2999 	}
3000 
3001 	params.q_obj = &bp->sp_objs->q_obj;
3002 	params.cmd = BNX2X_Q_CMD_EMPTY;
3003 
3004 	__set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
3005 
3006 	return bnx2x_queue_state_change(bp, &params);
3007 }
3008 
3009 static void bnx2x_self_test(struct net_device *dev,
3010 			    struct ethtool_test *etest, u64 *buf)
3011 {
3012 	struct bnx2x *bp = netdev_priv(dev);
3013 	u8 is_serdes, link_up;
3014 	int rc, cnt = 0;
3015 
3016 	if (pci_num_vf(bp->pdev)) {
3017 		DP(BNX2X_MSG_IOV,
3018 		   "VFs are enabled, can not perform self test\n");
3019 		return;
3020 	}
3021 
3022 	if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
3023 		netdev_err(bp->dev,
3024 			   "Handling parity error recovery. Try again later\n");
3025 		etest->flags |= ETH_TEST_FL_FAILED;
3026 		return;
3027 	}
3028 
3029 	DP(BNX2X_MSG_ETHTOOL,
3030 	   "Self-test command parameters: offline = %d, external_lb = %d\n",
3031 	   (etest->flags & ETH_TEST_FL_OFFLINE),
3032 	   (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
3033 
3034 	memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
3035 
3036 	if (bnx2x_test_nvram(bp) != 0) {
3037 		if (!IS_MF(bp))
3038 			buf[4] = 1;
3039 		else
3040 			buf[0] = 1;
3041 		etest->flags |= ETH_TEST_FL_FAILED;
3042 	}
3043 
3044 	if (!netif_running(dev)) {
3045 		DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
3046 		return;
3047 	}
3048 
3049 	is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
3050 	link_up = bp->link_vars.link_up;
3051 	/* offline tests are not supported in MF mode */
3052 	if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3053 		int port = BP_PORT(bp);
3054 		u32 val;
3055 
3056 		/* save current value of input enable for TX port IF */
3057 		val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3058 		/* disable input for TX port IF */
3059 		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3060 
3061 		bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3062 		rc = bnx2x_nic_load(bp, LOAD_DIAG);
3063 		if (rc) {
3064 			etest->flags |= ETH_TEST_FL_FAILED;
3065 			DP(BNX2X_MSG_ETHTOOL,
3066 			   "Can't perform self-test, nic_load (for offline) failed\n");
3067 			return;
3068 		}
3069 
3070 		/* wait until link state is restored */
3071 		bnx2x_wait_for_link(bp, 1, is_serdes);
3072 
3073 		if (bnx2x_test_registers(bp) != 0) {
3074 			buf[0] = 1;
3075 			etest->flags |= ETH_TEST_FL_FAILED;
3076 		}
3077 		if (bnx2x_test_memory(bp) != 0) {
3078 			buf[1] = 1;
3079 			etest->flags |= ETH_TEST_FL_FAILED;
3080 		}
3081 
3082 		buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3083 		if (buf[2] != 0)
3084 			etest->flags |= ETH_TEST_FL_FAILED;
3085 
3086 		if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3087 			buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3088 			if (buf[3] != 0)
3089 				etest->flags |= ETH_TEST_FL_FAILED;
3090 			etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3091 		}
3092 
3093 		bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3094 
3095 		/* restore input for TX port IF */
3096 		REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3097 		rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3098 		if (rc) {
3099 			etest->flags |= ETH_TEST_FL_FAILED;
3100 			DP(BNX2X_MSG_ETHTOOL,
3101 			   "Can't perform self-test, nic_load (for online) failed\n");
3102 			return;
3103 		}
3104 		/* wait until link state is restored */
3105 		bnx2x_wait_for_link(bp, link_up, is_serdes);
3106 	}
3107 
3108 	if (bnx2x_test_intr(bp) != 0) {
3109 		if (!IS_MF(bp))
3110 			buf[5] = 1;
3111 		else
3112 			buf[1] = 1;
3113 		etest->flags |= ETH_TEST_FL_FAILED;
3114 	}
3115 
3116 	if (link_up) {
3117 		cnt = 100;
3118 		while (bnx2x_link_test(bp, is_serdes) && --cnt)
3119 			msleep(20);
3120 	}
3121 
3122 	if (!cnt) {
3123 		if (!IS_MF(bp))
3124 			buf[6] = 1;
3125 		else
3126 			buf[2] = 1;
3127 		etest->flags |= ETH_TEST_FL_FAILED;
3128 	}
3129 }
3130 
3131 #define IS_PORT_STAT(i)		(bnx2x_stats_arr[i].is_port_stat)
3132 #define HIDE_PORT_STAT(bp)	IS_VF(bp)
3133 
3134 /* ethtool statistics are displayed for all regular ethernet queues and the
3135  * fcoe L2 queue if not disabled
3136  */
3137 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3138 {
3139 	return BNX2X_NUM_ETH_QUEUES(bp);
3140 }
3141 
3142 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3143 {
3144 	struct bnx2x *bp = netdev_priv(dev);
3145 	int i, num_strings = 0;
3146 
3147 	switch (stringset) {
3148 	case ETH_SS_STATS:
3149 		if (is_multi(bp)) {
3150 			num_strings = bnx2x_num_stat_queues(bp) *
3151 				      BNX2X_NUM_Q_STATS;
3152 		} else
3153 			num_strings = 0;
3154 		if (HIDE_PORT_STAT(bp)) {
3155 			for (i = 0; i < BNX2X_NUM_STATS; i++)
3156 				if (!IS_PORT_STAT(i))
3157 					num_strings++;
3158 		} else
3159 			num_strings += BNX2X_NUM_STATS;
3160 
3161 		return num_strings;
3162 
3163 	case ETH_SS_TEST:
3164 		return BNX2X_NUM_TESTS(bp);
3165 
3166 	case ETH_SS_PRIV_FLAGS:
3167 		return BNX2X_PRI_FLAG_LEN;
3168 
3169 	default:
3170 		return -EINVAL;
3171 	}
3172 }
3173 
3174 static u32 bnx2x_get_private_flags(struct net_device *dev)
3175 {
3176 	struct bnx2x *bp = netdev_priv(dev);
3177 	u32 flags = 0;
3178 
3179 	flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3180 	flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3181 	flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3182 
3183 	return flags;
3184 }
3185 
3186 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3187 {
3188 	struct bnx2x *bp = netdev_priv(dev);
3189 	int i, j, k, start;
3190 	char queue_name[MAX_QUEUE_NAME_LEN+1];
3191 
3192 	switch (stringset) {
3193 	case ETH_SS_STATS:
3194 		k = 0;
3195 		if (is_multi(bp)) {
3196 			for_each_eth_queue(bp, i) {
3197 				memset(queue_name, 0, sizeof(queue_name));
3198 				snprintf(queue_name, sizeof(queue_name),
3199 					 "%d", i);
3200 				for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3201 					snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3202 						ETH_GSTRING_LEN,
3203 						bnx2x_q_stats_arr[j].string,
3204 						queue_name);
3205 				k += BNX2X_NUM_Q_STATS;
3206 			}
3207 		}
3208 
3209 		for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3210 			if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3211 				continue;
3212 			strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3213 				   bnx2x_stats_arr[i].string);
3214 			j++;
3215 		}
3216 
3217 		break;
3218 
3219 	case ETH_SS_TEST:
3220 		/* First 4 tests cannot be done in MF mode */
3221 		if (!IS_MF(bp))
3222 			start = 0;
3223 		else
3224 			start = 4;
3225 		memcpy(buf, bnx2x_tests_str_arr + start,
3226 		       ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3227 		break;
3228 
3229 	case ETH_SS_PRIV_FLAGS:
3230 		memcpy(buf, bnx2x_private_arr,
3231 		       ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3232 		break;
3233 	}
3234 }
3235 
3236 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3237 				    struct ethtool_stats *stats, u64 *buf)
3238 {
3239 	struct bnx2x *bp = netdev_priv(dev);
3240 	u32 *hw_stats, *offset;
3241 	int i, j, k = 0;
3242 
3243 	if (is_multi(bp)) {
3244 		for_each_eth_queue(bp, i) {
3245 			hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3246 			for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3247 				if (bnx2x_q_stats_arr[j].size == 0) {
3248 					/* skip this counter */
3249 					buf[k + j] = 0;
3250 					continue;
3251 				}
3252 				offset = (hw_stats +
3253 					  bnx2x_q_stats_arr[j].offset);
3254 				if (bnx2x_q_stats_arr[j].size == 4) {
3255 					/* 4-byte counter */
3256 					buf[k + j] = (u64) *offset;
3257 					continue;
3258 				}
3259 				/* 8-byte counter */
3260 				buf[k + j] = HILO_U64(*offset, *(offset + 1));
3261 			}
3262 			k += BNX2X_NUM_Q_STATS;
3263 		}
3264 	}
3265 
3266 	hw_stats = (u32 *)&bp->eth_stats;
3267 	for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3268 		if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3269 			continue;
3270 		if (bnx2x_stats_arr[i].size == 0) {
3271 			/* skip this counter */
3272 			buf[k + j] = 0;
3273 			j++;
3274 			continue;
3275 		}
3276 		offset = (hw_stats + bnx2x_stats_arr[i].offset);
3277 		if (bnx2x_stats_arr[i].size == 4) {
3278 			/* 4-byte counter */
3279 			buf[k + j] = (u64) *offset;
3280 			j++;
3281 			continue;
3282 		}
3283 		/* 8-byte counter */
3284 		buf[k + j] = HILO_U64(*offset, *(offset + 1));
3285 		j++;
3286 	}
3287 }
3288 
3289 static int bnx2x_set_phys_id(struct net_device *dev,
3290 			     enum ethtool_phys_id_state state)
3291 {
3292 	struct bnx2x *bp = netdev_priv(dev);
3293 
3294 	if (!bnx2x_is_nvm_accessible(bp)) {
3295 		DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3296 		   "cannot access eeprom when the interface is down\n");
3297 		return -EAGAIN;
3298 	}
3299 
3300 	switch (state) {
3301 	case ETHTOOL_ID_ACTIVE:
3302 		return 1;	/* cycle on/off once per second */
3303 
3304 	case ETHTOOL_ID_ON:
3305 		bnx2x_acquire_phy_lock(bp);
3306 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3307 			      LED_MODE_ON, SPEED_1000);
3308 		bnx2x_release_phy_lock(bp);
3309 		break;
3310 
3311 	case ETHTOOL_ID_OFF:
3312 		bnx2x_acquire_phy_lock(bp);
3313 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3314 			      LED_MODE_FRONT_PANEL_OFF, 0);
3315 		bnx2x_release_phy_lock(bp);
3316 		break;
3317 
3318 	case ETHTOOL_ID_INACTIVE:
3319 		bnx2x_acquire_phy_lock(bp);
3320 		bnx2x_set_led(&bp->link_params, &bp->link_vars,
3321 			      LED_MODE_OPER,
3322 			      bp->link_vars.line_speed);
3323 		bnx2x_release_phy_lock(bp);
3324 	}
3325 
3326 	return 0;
3327 }
3328 
3329 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3330 {
3331 	switch (info->flow_type) {
3332 	case TCP_V4_FLOW:
3333 	case TCP_V6_FLOW:
3334 		info->data = RXH_IP_SRC | RXH_IP_DST |
3335 			     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3336 		break;
3337 	case UDP_V4_FLOW:
3338 		if (bp->rss_conf_obj.udp_rss_v4)
3339 			info->data = RXH_IP_SRC | RXH_IP_DST |
3340 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3341 		else
3342 			info->data = RXH_IP_SRC | RXH_IP_DST;
3343 		break;
3344 	case UDP_V6_FLOW:
3345 		if (bp->rss_conf_obj.udp_rss_v6)
3346 			info->data = RXH_IP_SRC | RXH_IP_DST |
3347 				     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3348 		else
3349 			info->data = RXH_IP_SRC | RXH_IP_DST;
3350 		break;
3351 	case IPV4_FLOW:
3352 	case IPV6_FLOW:
3353 		info->data = RXH_IP_SRC | RXH_IP_DST;
3354 		break;
3355 	default:
3356 		info->data = 0;
3357 		break;
3358 	}
3359 
3360 	return 0;
3361 }
3362 
3363 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3364 			   u32 *rules __always_unused)
3365 {
3366 	struct bnx2x *bp = netdev_priv(dev);
3367 
3368 	switch (info->cmd) {
3369 	case ETHTOOL_GRXRINGS:
3370 		info->data = BNX2X_NUM_ETH_QUEUES(bp);
3371 		return 0;
3372 	case ETHTOOL_GRXFH:
3373 		return bnx2x_get_rss_flags(bp, info);
3374 	default:
3375 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3376 		return -EOPNOTSUPP;
3377 	}
3378 }
3379 
3380 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3381 {
3382 	int udp_rss_requested;
3383 
3384 	DP(BNX2X_MSG_ETHTOOL,
3385 	   "Set rss flags command parameters: flow type = %d, data = %llu\n",
3386 	   info->flow_type, info->data);
3387 
3388 	switch (info->flow_type) {
3389 	case TCP_V4_FLOW:
3390 	case TCP_V6_FLOW:
3391 		/* For TCP only 4-tupple hash is supported */
3392 		if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3393 				  RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3394 			DP(BNX2X_MSG_ETHTOOL,
3395 			   "Command parameters not supported\n");
3396 			return -EINVAL;
3397 		}
3398 		return 0;
3399 
3400 	case UDP_V4_FLOW:
3401 	case UDP_V6_FLOW:
3402 		/* For UDP either 2-tupple hash or 4-tupple hash is supported */
3403 		if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3404 				   RXH_L4_B_0_1 | RXH_L4_B_2_3))
3405 			udp_rss_requested = 1;
3406 		else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3407 			udp_rss_requested = 0;
3408 		else
3409 			return -EINVAL;
3410 
3411 		if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3412 			DP(BNX2X_MSG_ETHTOOL,
3413 			   "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3414 			return -EINVAL;
3415 		}
3416 
3417 		if ((info->flow_type == UDP_V4_FLOW) &&
3418 		    (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3419 			bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3420 			DP(BNX2X_MSG_ETHTOOL,
3421 			   "rss re-configured, UDP 4-tupple %s\n",
3422 			   udp_rss_requested ? "enabled" : "disabled");
3423 			if (bp->state == BNX2X_STATE_OPEN)
3424 				return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3425 						 true);
3426 		} else if ((info->flow_type == UDP_V6_FLOW) &&
3427 			   (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3428 			bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3429 			DP(BNX2X_MSG_ETHTOOL,
3430 			   "rss re-configured, UDP 4-tupple %s\n",
3431 			   udp_rss_requested ? "enabled" : "disabled");
3432 			if (bp->state == BNX2X_STATE_OPEN)
3433 				return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3434 						 true);
3435 		}
3436 		return 0;
3437 
3438 	case IPV4_FLOW:
3439 	case IPV6_FLOW:
3440 		/* For IP only 2-tupple hash is supported */
3441 		if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3442 			DP(BNX2X_MSG_ETHTOOL,
3443 			   "Command parameters not supported\n");
3444 			return -EINVAL;
3445 		}
3446 		return 0;
3447 
3448 	case SCTP_V4_FLOW:
3449 	case AH_ESP_V4_FLOW:
3450 	case AH_V4_FLOW:
3451 	case ESP_V4_FLOW:
3452 	case SCTP_V6_FLOW:
3453 	case AH_ESP_V6_FLOW:
3454 	case AH_V6_FLOW:
3455 	case ESP_V6_FLOW:
3456 	case IP_USER_FLOW:
3457 	case ETHER_FLOW:
3458 		/* RSS is not supported for these protocols */
3459 		if (info->data) {
3460 			DP(BNX2X_MSG_ETHTOOL,
3461 			   "Command parameters not supported\n");
3462 			return -EINVAL;
3463 		}
3464 		return 0;
3465 
3466 	default:
3467 		return -EINVAL;
3468 	}
3469 }
3470 
3471 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3472 {
3473 	struct bnx2x *bp = netdev_priv(dev);
3474 
3475 	switch (info->cmd) {
3476 	case ETHTOOL_SRXFH:
3477 		return bnx2x_set_rss_flags(bp, info);
3478 	default:
3479 		DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3480 		return -EOPNOTSUPP;
3481 	}
3482 }
3483 
3484 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3485 {
3486 	return T_ETH_INDIRECTION_TABLE_SIZE;
3487 }
3488 
3489 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3490 			  u8 *hfunc)
3491 {
3492 	struct bnx2x *bp = netdev_priv(dev);
3493 	u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3494 	size_t i;
3495 
3496 	if (hfunc)
3497 		*hfunc = ETH_RSS_HASH_TOP;
3498 	if (!indir)
3499 		return 0;
3500 
3501 	/* Get the current configuration of the RSS indirection table */
3502 	bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3503 
3504 	/*
3505 	 * We can't use a memcpy() as an internal storage of an
3506 	 * indirection table is a u8 array while indir->ring_index
3507 	 * points to an array of u32.
3508 	 *
3509 	 * Indirection table contains the FW Client IDs, so we need to
3510 	 * align the returned table to the Client ID of the leading RSS
3511 	 * queue.
3512 	 */
3513 	for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3514 		indir[i] = ind_table[i] - bp->fp->cl_id;
3515 
3516 	return 0;
3517 }
3518 
3519 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3520 			  const u8 *key, const u8 hfunc)
3521 {
3522 	struct bnx2x *bp = netdev_priv(dev);
3523 	size_t i;
3524 
3525 	/* We require at least one supported parameter to be changed and no
3526 	 * change in any of the unsupported parameters
3527 	 */
3528 	if (key ||
3529 	    (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3530 		return -EOPNOTSUPP;
3531 
3532 	if (!indir)
3533 		return 0;
3534 
3535 	for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3536 		/*
3537 		 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3538 		 * as an internal storage of an indirection table is a u8 array
3539 		 * while indir->ring_index points to an array of u32.
3540 		 *
3541 		 * Indirection table contains the FW Client IDs, so we need to
3542 		 * align the received table to the Client ID of the leading RSS
3543 		 * queue
3544 		 */
3545 		bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3546 	}
3547 
3548 	if (bp->state == BNX2X_STATE_OPEN)
3549 		return bnx2x_config_rss_eth(bp, false);
3550 
3551 	return 0;
3552 }
3553 
3554 /**
3555  * bnx2x_get_channels - gets the number of RSS queues.
3556  *
3557  * @dev:		net device
3558  * @channels:		returns the number of max / current queues
3559  */
3560 static void bnx2x_get_channels(struct net_device *dev,
3561 			       struct ethtool_channels *channels)
3562 {
3563 	struct bnx2x *bp = netdev_priv(dev);
3564 
3565 	channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3566 	channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3567 }
3568 
3569 /**
3570  * bnx2x_change_num_queues - change the number of RSS queues.
3571  *
3572  * @bp:			bnx2x private structure
3573  * @num_rss:		rss count
3574  *
3575  * Re-configure interrupt mode to get the new number of MSI-X
3576  * vectors and re-add NAPI objects.
3577  */
3578 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3579 {
3580 	bnx2x_disable_msi(bp);
3581 	bp->num_ethernet_queues = num_rss;
3582 	bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3583 	BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3584 	bnx2x_set_int_mode(bp);
3585 }
3586 
3587 /**
3588  * bnx2x_set_channels - sets the number of RSS queues.
3589  *
3590  * @dev:		net device
3591  * @channels:		includes the number of queues requested
3592  */
3593 static int bnx2x_set_channels(struct net_device *dev,
3594 			      struct ethtool_channels *channels)
3595 {
3596 	struct bnx2x *bp = netdev_priv(dev);
3597 
3598 	DP(BNX2X_MSG_ETHTOOL,
3599 	   "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3600 	   channels->rx_count, channels->tx_count, channels->other_count,
3601 	   channels->combined_count);
3602 
3603 	if (pci_num_vf(bp->pdev)) {
3604 		DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3605 		return -EPERM;
3606 	}
3607 
3608 	/* We don't support separate rx / tx channels.
3609 	 * We don't allow setting 'other' channels.
3610 	 */
3611 	if (channels->rx_count || channels->tx_count || channels->other_count
3612 	    || (channels->combined_count == 0) ||
3613 	    (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3614 		DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3615 		return -EINVAL;
3616 	}
3617 
3618 	/* Check if there was a change in the active parameters */
3619 	if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3620 		DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3621 		return 0;
3622 	}
3623 
3624 	/* Set the requested number of queues in bp context.
3625 	 * Note that the actual number of queues created during load may be
3626 	 * less than requested if memory is low.
3627 	 */
3628 	if (unlikely(!netif_running(dev))) {
3629 		bnx2x_change_num_queues(bp, channels->combined_count);
3630 		return 0;
3631 	}
3632 	bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3633 	bnx2x_change_num_queues(bp, channels->combined_count);
3634 	return bnx2x_nic_load(bp, LOAD_NORMAL);
3635 }
3636 
3637 static int bnx2x_get_ts_info(struct net_device *dev,
3638 			     struct ethtool_ts_info *info)
3639 {
3640 	struct bnx2x *bp = netdev_priv(dev);
3641 
3642 	if (bp->flags & PTP_SUPPORTED) {
3643 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3644 					SOF_TIMESTAMPING_RX_SOFTWARE |
3645 					SOF_TIMESTAMPING_SOFTWARE |
3646 					SOF_TIMESTAMPING_TX_HARDWARE |
3647 					SOF_TIMESTAMPING_RX_HARDWARE |
3648 					SOF_TIMESTAMPING_RAW_HARDWARE;
3649 
3650 		if (bp->ptp_clock)
3651 			info->phc_index = ptp_clock_index(bp->ptp_clock);
3652 		else
3653 			info->phc_index = -1;
3654 
3655 		info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3656 				   (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3657 				   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3658 				   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3659 
3660 		info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3661 
3662 		return 0;
3663 	}
3664 
3665 	return ethtool_op_get_ts_info(dev, info);
3666 }
3667 
3668 static const struct ethtool_ops bnx2x_ethtool_ops = {
3669 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3670 	.get_drvinfo		= bnx2x_get_drvinfo,
3671 	.get_regs_len		= bnx2x_get_regs_len,
3672 	.get_regs		= bnx2x_get_regs,
3673 	.get_dump_flag		= bnx2x_get_dump_flag,
3674 	.get_dump_data		= bnx2x_get_dump_data,
3675 	.set_dump		= bnx2x_set_dump,
3676 	.get_wol		= bnx2x_get_wol,
3677 	.set_wol		= bnx2x_set_wol,
3678 	.get_msglevel		= bnx2x_get_msglevel,
3679 	.set_msglevel		= bnx2x_set_msglevel,
3680 	.nway_reset		= bnx2x_nway_reset,
3681 	.get_link		= bnx2x_get_link,
3682 	.get_eeprom_len		= bnx2x_get_eeprom_len,
3683 	.get_eeprom		= bnx2x_get_eeprom,
3684 	.set_eeprom		= bnx2x_set_eeprom,
3685 	.get_coalesce		= bnx2x_get_coalesce,
3686 	.set_coalesce		= bnx2x_set_coalesce,
3687 	.get_ringparam		= bnx2x_get_ringparam,
3688 	.set_ringparam		= bnx2x_set_ringparam,
3689 	.get_pauseparam		= bnx2x_get_pauseparam,
3690 	.set_pauseparam		= bnx2x_set_pauseparam,
3691 	.self_test		= bnx2x_self_test,
3692 	.get_sset_count		= bnx2x_get_sset_count,
3693 	.get_priv_flags		= bnx2x_get_private_flags,
3694 	.get_strings		= bnx2x_get_strings,
3695 	.set_phys_id		= bnx2x_set_phys_id,
3696 	.get_ethtool_stats	= bnx2x_get_ethtool_stats,
3697 	.get_rxnfc		= bnx2x_get_rxnfc,
3698 	.set_rxnfc		= bnx2x_set_rxnfc,
3699 	.get_rxfh_indir_size	= bnx2x_get_rxfh_indir_size,
3700 	.get_rxfh		= bnx2x_get_rxfh,
3701 	.set_rxfh		= bnx2x_set_rxfh,
3702 	.get_channels		= bnx2x_get_channels,
3703 	.set_channels		= bnx2x_set_channels,
3704 	.get_module_info	= bnx2x_get_module_info,
3705 	.get_module_eeprom	= bnx2x_get_module_eeprom,
3706 	.get_eee		= bnx2x_get_eee,
3707 	.set_eee		= bnx2x_set_eee,
3708 	.get_ts_info		= bnx2x_get_ts_info,
3709 	.get_link_ksettings	= bnx2x_get_link_ksettings,
3710 	.set_link_ksettings	= bnx2x_set_link_ksettings,
3711 };
3712 
3713 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3714 	.get_drvinfo		= bnx2x_get_drvinfo,
3715 	.get_msglevel		= bnx2x_get_msglevel,
3716 	.set_msglevel		= bnx2x_set_msglevel,
3717 	.get_link		= bnx2x_get_link,
3718 	.get_coalesce		= bnx2x_get_coalesce,
3719 	.get_ringparam		= bnx2x_get_ringparam,
3720 	.set_ringparam		= bnx2x_set_ringparam,
3721 	.get_sset_count		= bnx2x_get_sset_count,
3722 	.get_strings		= bnx2x_get_strings,
3723 	.get_ethtool_stats	= bnx2x_get_ethtool_stats,
3724 	.get_rxnfc		= bnx2x_get_rxnfc,
3725 	.set_rxnfc		= bnx2x_set_rxnfc,
3726 	.get_rxfh_indir_size	= bnx2x_get_rxfh_indir_size,
3727 	.get_rxfh		= bnx2x_get_rxfh,
3728 	.set_rxfh		= bnx2x_set_rxfh,
3729 	.get_channels		= bnx2x_get_channels,
3730 	.set_channels		= bnx2x_set_channels,
3731 	.get_link_ksettings	= bnx2x_get_vf_link_ksettings,
3732 };
3733 
3734 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3735 {
3736 	netdev->ethtool_ops = (IS_PF(bp)) ?
3737 		&bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3738 }
3739