1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 385b26ea1SAriel Elior * Copyright (c) 2007-2012 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher #include "bnx2x.h" 26adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 27adfc5217SJeff Kirsher #include "bnx2x_dump.h" 28adfc5217SJeff Kirsher #include "bnx2x_init.h" 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 31adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33adfc5217SJeff Kirsher */ 34adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 35adfc5217SJeff Kirsher static const struct { 36adfc5217SJeff Kirsher long offset; 37adfc5217SJeff Kirsher int size; 38adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 39adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 40adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 49adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53adfc5217SJeff Kirsher 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 65c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 68adfc5217SJeff Kirsher }; 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher static const struct { 73adfc5217SJeff Kirsher long offset; 74adfc5217SJeff Kirsher int size; 75adfc5217SJeff Kirsher u32 flags; 76adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 77adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 78adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 80adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 81adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 101adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 104adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 106adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 108adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1090e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1100e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1110e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1120e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 114adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 122adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 128adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129adfc5217SJeff Kirsher 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 131adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1777a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1797a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1817a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 183c96bdc0cSDmitry Kravkov 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 185e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 189adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 190adfc5217SJeff Kirsher { 191adfc5217SJeff Kirsher int port_type; 192adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 193adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 194dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 195dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 196adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_KR: 198adfc5217SJeff Kirsher case ETH_PHY_CX4: 199adfc5217SJeff Kirsher port_type = PORT_FIBRE; 200adfc5217SJeff Kirsher break; 201adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 202adfc5217SJeff Kirsher port_type = PORT_DA; 203adfc5217SJeff Kirsher break; 204adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 205adfc5217SJeff Kirsher port_type = PORT_TP; 206adfc5217SJeff Kirsher break; 207adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 208adfc5217SJeff Kirsher port_type = PORT_NONE; 209adfc5217SJeff Kirsher break; 210adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 211adfc5217SJeff Kirsher default: 212adfc5217SJeff Kirsher port_type = PORT_OTHER; 213adfc5217SJeff Kirsher break; 214adfc5217SJeff Kirsher } 215adfc5217SJeff Kirsher return port_type; 216adfc5217SJeff Kirsher } 217adfc5217SJeff Kirsher 218adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 219adfc5217SJeff Kirsher { 220adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 221adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 222adfc5217SJeff Kirsher 223adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 224adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 225adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 226adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 227adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 228dbef807eSYuval Mintz if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 229dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER) { 230dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 231dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 232dbef807eSYuval Mintz } 233adfc5217SJeff Kirsher 23438298461SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) { 23538298461SYuval Mintz if (!(bp->flags & MF_FUNC_DIS)) { 236adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 237adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 238adfc5217SJeff Kirsher } else { 239adfc5217SJeff Kirsher ethtool_cmd_speed_set( 240adfc5217SJeff Kirsher cmd, bp->link_params.req_line_speed[cfg_idx]); 241adfc5217SJeff Kirsher cmd->duplex = bp->link_params.req_duplex[cfg_idx]; 242adfc5217SJeff Kirsher } 243adfc5217SJeff Kirsher 24438298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 245adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 24638298461SYuval Mintz } else { 24738298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 24838298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 24938298461SYuval Mintz } 250adfc5217SJeff Kirsher 251adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 254adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 255adfc5217SJeff Kirsher 256adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 257adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 258adfc5217SJeff Kirsher else 259adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 260adfc5217SJeff Kirsher 2619e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2629e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2639e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2649e7e8399SMintz Yuval 2659e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 2669e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 2679e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 2689e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 2699e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 2709e7e8399SMintz Yuval 2719e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 2729e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 2739e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 2749e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 2759e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 2769e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 2779e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 2789e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 2799e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 2809e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 2819e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 2829e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 2839e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 2849e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 2859e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 2869e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 2879e7e8399SMintz Yuval } 2889e7e8399SMintz Yuval 289adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 290adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 291adfc5217SJeff Kirsher 29251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 293f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 294f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 295f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 296adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 297adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 298adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 299adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 300adfc5217SJeff Kirsher 301adfc5217SJeff Kirsher return 0; 302adfc5217SJeff Kirsher } 303adfc5217SJeff Kirsher 304adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 305adfc5217SJeff Kirsher { 306adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 307adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 308dbef807eSYuval Mintz u32 speed, phy_idx; 309adfc5217SJeff Kirsher 310adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 311adfc5217SJeff Kirsher return 0; 312adfc5217SJeff Kirsher 31351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 314adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 315adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 316adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 317adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 318adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 319adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 320adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 321adfc5217SJeff Kirsher 322adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 323adfc5217SJeff Kirsher 32438298461SYuval Mintz /* If recieved a request for an unknown duplex, assume full*/ 32538298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 32638298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 32738298461SYuval Mintz 328adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 329adfc5217SJeff Kirsher u32 part; 330adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 331adfc5217SJeff Kirsher 332adfc5217SJeff Kirsher /* use 10G if no link detected */ 333adfc5217SJeff Kirsher if (!line_speed) 334adfc5217SJeff Kirsher line_speed = 10000; 335adfc5217SJeff Kirsher 336adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 33751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33851c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 339adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 340adfc5217SJeff Kirsher return -EINVAL; 341adfc5217SJeff Kirsher } 342adfc5217SJeff Kirsher 343adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 344adfc5217SJeff Kirsher 345adfc5217SJeff Kirsher if (line_speed < speed || !part) { 34651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34751c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 348adfc5217SJeff Kirsher return -EINVAL; 349adfc5217SJeff Kirsher } 350adfc5217SJeff Kirsher 351adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 352adfc5217SJeff Kirsher /* store value for following "load" */ 353adfc5217SJeff Kirsher bp->pending_max = part; 354adfc5217SJeff Kirsher else 355adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 356adfc5217SJeff Kirsher 357adfc5217SJeff Kirsher return 0; 358adfc5217SJeff Kirsher } 359adfc5217SJeff Kirsher 360adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 361adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 362adfc5217SJeff Kirsher switch (cmd->port) { 363adfc5217SJeff Kirsher case PORT_TP: 364adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 365adfc5217SJeff Kirsher break; /* no port change */ 366adfc5217SJeff Kirsher 367adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 368adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 36951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 370adfc5217SJeff Kirsher return -EINVAL; 371adfc5217SJeff Kirsher } 372adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 373adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 374adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 375adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 376adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 377adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 378adfc5217SJeff Kirsher else 379adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 380adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 381adfc5217SJeff Kirsher break; 382adfc5217SJeff Kirsher case PORT_FIBRE: 383bfdb5823SYaniv Rosner case PORT_DA: 384adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 385adfc5217SJeff Kirsher break; /* no port change */ 386adfc5217SJeff Kirsher 387adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 388adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 38951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 390adfc5217SJeff Kirsher return -EINVAL; 391adfc5217SJeff Kirsher } 392adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 393adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 394adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 395adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 396adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 397adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 398adfc5217SJeff Kirsher else 399adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 400adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 401adfc5217SJeff Kirsher break; 402adfc5217SJeff Kirsher default: 40351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 404adfc5217SJeff Kirsher return -EINVAL; 405adfc5217SJeff Kirsher } 4062f751a80SYaniv Rosner /* Save new config in case command complete successully */ 407adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 408adfc5217SJeff Kirsher /* Get the new cfg_idx */ 409adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 410adfc5217SJeff Kirsher /* Restore old config in case command failed */ 411adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 41251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 413adfc5217SJeff Kirsher 414adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 41575318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 41675318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 41775318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 41875318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 41975318327SYaniv Rosner SUPPORTED_100baseT_Full); 420adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 42151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 422adfc5217SJeff Kirsher return -EINVAL; 423adfc5217SJeff Kirsher } 424adfc5217SJeff Kirsher 425adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 42675318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 42751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 42851c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4298decf868SDavid S. Miller return -EINVAL; 4308decf868SDavid S. Miller } 431adfc5217SJeff Kirsher 432adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4338decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4348decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 435adfc5217SJeff Kirsher cmd->advertising); 4368decf868SDavid S. Miller if (cmd->advertising) { 437adfc5217SJeff Kirsher 4388decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4398decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4408decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4418decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4428decf868SDavid S. Miller } 4438decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4448decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4458decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4468decf868SDavid S. Miller 4478decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4488decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4498decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4508decf868SDavid S. Miller 4518decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4528decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4538decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4548decf868SDavid S. Miller } 4558decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4568decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4578decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4588decf868SDavid S. Miller } 4598decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4608decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4618decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4628decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4638decf868SDavid S. Miller 4648decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4658decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 4668decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 4678decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4688decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 4698decf868SDavid S. Miller } 470adfc5217SJeff Kirsher } else { /* forced speed */ 471adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 472adfc5217SJeff Kirsher switch (speed) { 473adfc5217SJeff Kirsher case SPEED_10: 474adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 475adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 476adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 47751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 478adfc5217SJeff Kirsher "10M full not supported\n"); 479adfc5217SJeff Kirsher return -EINVAL; 480adfc5217SJeff Kirsher } 481adfc5217SJeff Kirsher 482adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 483adfc5217SJeff Kirsher ADVERTISED_TP); 484adfc5217SJeff Kirsher } else { 485adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 486adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 48751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 488adfc5217SJeff Kirsher "10M half not supported\n"); 489adfc5217SJeff Kirsher return -EINVAL; 490adfc5217SJeff Kirsher } 491adfc5217SJeff Kirsher 492adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 493adfc5217SJeff Kirsher ADVERTISED_TP); 494adfc5217SJeff Kirsher } 495adfc5217SJeff Kirsher break; 496adfc5217SJeff Kirsher 497adfc5217SJeff Kirsher case SPEED_100: 498adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 499adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 500adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 50151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 502adfc5217SJeff Kirsher "100M full not supported\n"); 503adfc5217SJeff Kirsher return -EINVAL; 504adfc5217SJeff Kirsher } 505adfc5217SJeff Kirsher 506adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 507adfc5217SJeff Kirsher ADVERTISED_TP); 508adfc5217SJeff Kirsher } else { 509adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 510adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 51151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 512adfc5217SJeff Kirsher "100M half not supported\n"); 513adfc5217SJeff Kirsher return -EINVAL; 514adfc5217SJeff Kirsher } 515adfc5217SJeff Kirsher 516adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 517adfc5217SJeff Kirsher ADVERTISED_TP); 518adfc5217SJeff Kirsher } 519adfc5217SJeff Kirsher break; 520adfc5217SJeff Kirsher 521adfc5217SJeff Kirsher case SPEED_1000: 522adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 52351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52451c1a580SMerav Sicron "1G half not supported\n"); 525adfc5217SJeff Kirsher return -EINVAL; 526adfc5217SJeff Kirsher } 527adfc5217SJeff Kirsher 528adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 529adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 53051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 53151c1a580SMerav Sicron "1G full not supported\n"); 532adfc5217SJeff Kirsher return -EINVAL; 533adfc5217SJeff Kirsher } 534adfc5217SJeff Kirsher 535adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 536adfc5217SJeff Kirsher ADVERTISED_TP); 537adfc5217SJeff Kirsher break; 538adfc5217SJeff Kirsher 539adfc5217SJeff Kirsher case SPEED_2500: 540adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 54151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 542adfc5217SJeff Kirsher "2.5G half not supported\n"); 543adfc5217SJeff Kirsher return -EINVAL; 544adfc5217SJeff Kirsher } 545adfc5217SJeff Kirsher 546adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 547adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 54851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 549adfc5217SJeff Kirsher "2.5G full not supported\n"); 550adfc5217SJeff Kirsher return -EINVAL; 551adfc5217SJeff Kirsher } 552adfc5217SJeff Kirsher 553adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 554adfc5217SJeff Kirsher ADVERTISED_TP); 555adfc5217SJeff Kirsher break; 556adfc5217SJeff Kirsher 557adfc5217SJeff Kirsher case SPEED_10000: 558adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 55951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56051c1a580SMerav Sicron "10G half not supported\n"); 561adfc5217SJeff Kirsher return -EINVAL; 562adfc5217SJeff Kirsher } 563dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 564adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 565dbef807eSYuval Mintz & SUPPORTED_10000baseT_Full) || 566dbef807eSYuval Mintz (bp->link_params.phy[phy_idx].media_type == 567dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 56851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56951c1a580SMerav Sicron "10G full not supported\n"); 570adfc5217SJeff Kirsher return -EINVAL; 571adfc5217SJeff Kirsher } 572adfc5217SJeff Kirsher 573adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 574adfc5217SJeff Kirsher ADVERTISED_FIBRE); 575adfc5217SJeff Kirsher break; 576adfc5217SJeff Kirsher 577adfc5217SJeff Kirsher default: 57851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 579adfc5217SJeff Kirsher return -EINVAL; 580adfc5217SJeff Kirsher } 581adfc5217SJeff Kirsher 582adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 583adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 584adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 585adfc5217SJeff Kirsher } 586adfc5217SJeff Kirsher 58751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 588f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 589adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 590adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 591adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 592adfc5217SJeff Kirsher 593adfc5217SJeff Kirsher /* Set new config */ 594adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 595adfc5217SJeff Kirsher if (netif_running(dev)) { 596adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 597adfc5217SJeff Kirsher bnx2x_link_set(bp); 598adfc5217SJeff Kirsher } 599adfc5217SJeff Kirsher 600adfc5217SJeff Kirsher return 0; 601adfc5217SJeff Kirsher } 602adfc5217SJeff Kirsher 603adfc5217SJeff Kirsher #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) 604adfc5217SJeff Kirsher #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) 605adfc5217SJeff Kirsher #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) 606adfc5217SJeff Kirsher #define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE) 607adfc5217SJeff Kirsher #define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE) 608adfc5217SJeff Kirsher 6091191cb83SEric Dumazet static bool bnx2x_is_reg_online(struct bnx2x *bp, 610adfc5217SJeff Kirsher const struct reg_addr *reg_info) 611adfc5217SJeff Kirsher { 612adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 613adfc5217SJeff Kirsher return IS_E1_ONLINE(reg_info->info); 614adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 615adfc5217SJeff Kirsher return IS_E1H_ONLINE(reg_info->info); 616adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 617adfc5217SJeff Kirsher return IS_E2_ONLINE(reg_info->info); 618adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 619adfc5217SJeff Kirsher return IS_E3_ONLINE(reg_info->info); 620adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 621adfc5217SJeff Kirsher return IS_E3B0_ONLINE(reg_info->info); 622adfc5217SJeff Kirsher else 623adfc5217SJeff Kirsher return false; 624adfc5217SJeff Kirsher } 625adfc5217SJeff Kirsher 626adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 6271191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 628adfc5217SJeff Kirsher { 629adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 630adfc5217SJeff Kirsher return page_vals_e2; 631adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 632adfc5217SJeff Kirsher return page_vals_e3; 633adfc5217SJeff Kirsher else 634adfc5217SJeff Kirsher return NULL; 635adfc5217SJeff Kirsher } 636adfc5217SJeff Kirsher 6371191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 638adfc5217SJeff Kirsher { 639adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 640adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 641adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 642adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 643adfc5217SJeff Kirsher else 644adfc5217SJeff Kirsher return 0; 645adfc5217SJeff Kirsher } 646adfc5217SJeff Kirsher 6471191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 648adfc5217SJeff Kirsher { 649adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 650adfc5217SJeff Kirsher return page_write_regs_e2; 651adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 652adfc5217SJeff Kirsher return page_write_regs_e3; 653adfc5217SJeff Kirsher else 654adfc5217SJeff Kirsher return NULL; 655adfc5217SJeff Kirsher } 656adfc5217SJeff Kirsher 6571191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 658adfc5217SJeff Kirsher { 659adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 660adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 661adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 662adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 663adfc5217SJeff Kirsher else 664adfc5217SJeff Kirsher return 0; 665adfc5217SJeff Kirsher } 666adfc5217SJeff Kirsher 6671191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 668adfc5217SJeff Kirsher { 669adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 670adfc5217SJeff Kirsher return page_read_regs_e2; 671adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 672adfc5217SJeff Kirsher return page_read_regs_e3; 673adfc5217SJeff Kirsher else 674adfc5217SJeff Kirsher return NULL; 675adfc5217SJeff Kirsher } 676adfc5217SJeff Kirsher 6771191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 678adfc5217SJeff Kirsher { 679adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 680adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 681adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 682adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 683adfc5217SJeff Kirsher else 684adfc5217SJeff Kirsher return 0; 685adfc5217SJeff Kirsher } 686adfc5217SJeff Kirsher 6871191cb83SEric Dumazet static int __bnx2x_get_regs_len(struct bnx2x *bp) 688adfc5217SJeff Kirsher { 689adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 690adfc5217SJeff Kirsher int page_write_num = __bnx2x_get_page_write_num(bp); 691adfc5217SJeff Kirsher const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp); 692adfc5217SJeff Kirsher int page_read_num = __bnx2x_get_page_read_num(bp); 693adfc5217SJeff Kirsher int regdump_len = 0; 694adfc5217SJeff Kirsher int i, j, k; 695adfc5217SJeff Kirsher 696adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 697adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 698adfc5217SJeff Kirsher regdump_len += reg_addrs[i].size; 699adfc5217SJeff Kirsher 700adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) 701adfc5217SJeff Kirsher for (j = 0; j < page_write_num; j++) 702adfc5217SJeff Kirsher for (k = 0; k < page_read_num; k++) 703adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &page_read_addr[k])) 704adfc5217SJeff Kirsher regdump_len += page_read_addr[k].size; 705adfc5217SJeff Kirsher 706adfc5217SJeff Kirsher return regdump_len; 707adfc5217SJeff Kirsher } 708adfc5217SJeff Kirsher 709adfc5217SJeff Kirsher static int bnx2x_get_regs_len(struct net_device *dev) 710adfc5217SJeff Kirsher { 711adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 712adfc5217SJeff Kirsher int regdump_len = 0; 713adfc5217SJeff Kirsher 714adfc5217SJeff Kirsher regdump_len = __bnx2x_get_regs_len(bp); 715adfc5217SJeff Kirsher regdump_len *= 4; 716adfc5217SJeff Kirsher regdump_len += sizeof(struct dump_hdr); 717adfc5217SJeff Kirsher 718adfc5217SJeff Kirsher return regdump_len; 719adfc5217SJeff Kirsher } 720adfc5217SJeff Kirsher 721adfc5217SJeff Kirsher /** 722adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 723adfc5217SJeff Kirsher * 724adfc5217SJeff Kirsher * @bp device handle 725adfc5217SJeff Kirsher * @p output buffer 726adfc5217SJeff Kirsher * 727adfc5217SJeff Kirsher * Reads "paged" memories: memories that may only be read by first writing to a 728adfc5217SJeff Kirsher * specific address ("write address") and then reading from a specific address 729adfc5217SJeff Kirsher * ("read address"). There may be more than one write address per "page" and 730adfc5217SJeff Kirsher * more than one read address per write address. 731adfc5217SJeff Kirsher */ 7321191cb83SEric Dumazet static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p) 733adfc5217SJeff Kirsher { 734adfc5217SJeff Kirsher u32 i, j, k, n; 735adfc5217SJeff Kirsher /* addresses of the paged registers */ 736adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 737adfc5217SJeff Kirsher /* number of paged registers */ 738adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 739adfc5217SJeff Kirsher /* write addresses */ 740adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 741adfc5217SJeff Kirsher /* number of write addresses */ 742adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 743adfc5217SJeff Kirsher /* read addresses info */ 744adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 745adfc5217SJeff Kirsher /* number of read addresses */ 746adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 747adfc5217SJeff Kirsher 748adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 749adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 750adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 751adfc5217SJeff Kirsher for (k = 0; k < read_num; k++) 752adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &read_addr[k])) 753adfc5217SJeff Kirsher for (n = 0; n < 754adfc5217SJeff Kirsher read_addr[k].size; n++) 755adfc5217SJeff Kirsher *p++ = REG_RD(bp, 756adfc5217SJeff Kirsher read_addr[k].addr + n*4); 757adfc5217SJeff Kirsher } 758adfc5217SJeff Kirsher } 759adfc5217SJeff Kirsher } 760adfc5217SJeff Kirsher 7611191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 762adfc5217SJeff Kirsher { 763adfc5217SJeff Kirsher u32 i, j; 764adfc5217SJeff Kirsher 765adfc5217SJeff Kirsher /* Read the regular registers */ 766adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 767adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 768adfc5217SJeff Kirsher for (j = 0; j < reg_addrs[i].size; j++) 769adfc5217SJeff Kirsher *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 770adfc5217SJeff Kirsher 771adfc5217SJeff Kirsher /* Read "paged" registes */ 772adfc5217SJeff Kirsher bnx2x_read_pages_regs(bp, p); 773adfc5217SJeff Kirsher } 774adfc5217SJeff Kirsher 775adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 776adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 777adfc5217SJeff Kirsher { 778adfc5217SJeff Kirsher u32 *p = _p; 779adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 780adfc5217SJeff Kirsher struct dump_hdr dump_hdr = {0}; 781adfc5217SJeff Kirsher 7822ace9510SDmitry Kravkov regs->version = 1; 783adfc5217SJeff Kirsher memset(p, 0, regs->len); 784adfc5217SJeff Kirsher 785adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 786adfc5217SJeff Kirsher return; 787adfc5217SJeff Kirsher 788adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 789adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 790adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 791adfc5217SJeff Kirsher */ 792adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 793adfc5217SJeff Kirsher 794adfc5217SJeff Kirsher dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; 795adfc5217SJeff Kirsher dump_hdr.dump_sign = dump_sign_all; 796adfc5217SJeff Kirsher dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); 797adfc5217SJeff Kirsher dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); 798adfc5217SJeff Kirsher dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); 799adfc5217SJeff Kirsher dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); 800adfc5217SJeff Kirsher 801adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 802adfc5217SJeff Kirsher dump_hdr.info = RI_E1_ONLINE; 803adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 804adfc5217SJeff Kirsher dump_hdr.info = RI_E1H_ONLINE; 805adfc5217SJeff Kirsher else if (!CHIP_IS_E1x(bp)) 806adfc5217SJeff Kirsher dump_hdr.info = RI_E2_ONLINE | 807adfc5217SJeff Kirsher (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); 808adfc5217SJeff Kirsher 809adfc5217SJeff Kirsher memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); 810adfc5217SJeff Kirsher p += dump_hdr.hdr_size + 1; 811adfc5217SJeff Kirsher 812adfc5217SJeff Kirsher /* Actually read the registers */ 813adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 814adfc5217SJeff Kirsher 815adfc5217SJeff Kirsher /* Re-enable parity attentions */ 816adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 817adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 818adfc5217SJeff Kirsher } 819adfc5217SJeff Kirsher 820adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 821adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 822adfc5217SJeff Kirsher { 823adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 824adfc5217SJeff Kirsher u8 phy_fw_ver[PHY_FW_VER_LEN]; 825adfc5217SJeff Kirsher 82668aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 82768aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 828adfc5217SJeff Kirsher 829adfc5217SJeff Kirsher phy_fw_ver[0] = '\0'; 830adfc5217SJeff Kirsher bnx2x_get_ext_phy_fw_version(&bp->link_params, 831adfc5217SJeff Kirsher phy_fw_ver, PHY_FW_VER_LEN); 83268aad78cSRick Jones strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version)); 833adfc5217SJeff Kirsher snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), 834adfc5217SJeff Kirsher "bc %d.%d.%d%s%s", 835adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff0000) >> 16, 836adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff00) >> 8, 837adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff), 838adfc5217SJeff Kirsher ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); 83968aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 840adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 841cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 842adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 843adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 844adfc5217SJeff Kirsher } 845adfc5217SJeff Kirsher 846adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 847adfc5217SJeff Kirsher { 848adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 849adfc5217SJeff Kirsher 850adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 851adfc5217SJeff Kirsher wol->supported = 0; 852adfc5217SJeff Kirsher wol->wolopts = 0; 853adfc5217SJeff Kirsher } else { 854adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 855adfc5217SJeff Kirsher if (bp->wol) 856adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 857adfc5217SJeff Kirsher else 858adfc5217SJeff Kirsher wol->wolopts = 0; 859adfc5217SJeff Kirsher } 860adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 861adfc5217SJeff Kirsher } 862adfc5217SJeff Kirsher 863adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 864adfc5217SJeff Kirsher { 865adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 866adfc5217SJeff Kirsher 86751c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 86851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); 869adfc5217SJeff Kirsher return -EINVAL; 87051c1a580SMerav Sicron } 871adfc5217SJeff Kirsher 872adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 87351c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 87451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); 875adfc5217SJeff Kirsher return -EINVAL; 87651c1a580SMerav Sicron } 877adfc5217SJeff Kirsher bp->wol = 1; 878adfc5217SJeff Kirsher } else 879adfc5217SJeff Kirsher bp->wol = 0; 880adfc5217SJeff Kirsher 881adfc5217SJeff Kirsher return 0; 882adfc5217SJeff Kirsher } 883adfc5217SJeff Kirsher 884adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 885adfc5217SJeff Kirsher { 886adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 887adfc5217SJeff Kirsher 888adfc5217SJeff Kirsher return bp->msg_enable; 889adfc5217SJeff Kirsher } 890adfc5217SJeff Kirsher 891adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 892adfc5217SJeff Kirsher { 893adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 894adfc5217SJeff Kirsher 895adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 896adfc5217SJeff Kirsher /* dump MCP trace */ 897adfc5217SJeff Kirsher if (level & BNX2X_MSG_MCP) 898adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 899adfc5217SJeff Kirsher bp->msg_enable = level; 900adfc5217SJeff Kirsher } 901adfc5217SJeff Kirsher } 902adfc5217SJeff Kirsher 903adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 904adfc5217SJeff Kirsher { 905adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 906adfc5217SJeff Kirsher 907adfc5217SJeff Kirsher if (!bp->port.pmf) 908adfc5217SJeff Kirsher return 0; 909adfc5217SJeff Kirsher 910adfc5217SJeff Kirsher if (netif_running(dev)) { 911adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 9125d07d868SYuval Mintz bnx2x_force_link_reset(bp); 913adfc5217SJeff Kirsher bnx2x_link_set(bp); 914adfc5217SJeff Kirsher } 915adfc5217SJeff Kirsher 916adfc5217SJeff Kirsher return 0; 917adfc5217SJeff Kirsher } 918adfc5217SJeff Kirsher 919adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 920adfc5217SJeff Kirsher { 921adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 922adfc5217SJeff Kirsher 923adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 924adfc5217SJeff Kirsher return 0; 925adfc5217SJeff Kirsher 926adfc5217SJeff Kirsher return bp->link_vars.link_up; 927adfc5217SJeff Kirsher } 928adfc5217SJeff Kirsher 929adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 930adfc5217SJeff Kirsher { 931adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 932adfc5217SJeff Kirsher 933adfc5217SJeff Kirsher return bp->common.flash_size; 934adfc5217SJeff Kirsher } 935adfc5217SJeff Kirsher 936f16da43bSAriel Elior /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had 937f16da43bSAriel Elior * we done things the other way around, if two pfs from the same port would 938f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 939f16da43bSAriel Elior * as: 940f16da43bSAriel Elior * pf A takes the port lock. 941f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 942f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 943f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 944f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 945f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 946f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 947f16da43bSAriel Elior * acess corrupted by pf B).* 948f16da43bSAriel Elior */ 949adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 950adfc5217SJeff Kirsher { 951adfc5217SJeff Kirsher int port = BP_PORT(bp); 952adfc5217SJeff Kirsher int count, i; 953f16da43bSAriel Elior u32 val; 954f16da43bSAriel Elior 955f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 956f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 957adfc5217SJeff Kirsher 958adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 959adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 960adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 961adfc5217SJeff Kirsher count *= 100; 962adfc5217SJeff Kirsher 963adfc5217SJeff Kirsher /* request access to nvram interface */ 964adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 965adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 966adfc5217SJeff Kirsher 967adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 968adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 969adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 970adfc5217SJeff Kirsher break; 971adfc5217SJeff Kirsher 972adfc5217SJeff Kirsher udelay(5); 973adfc5217SJeff Kirsher } 974adfc5217SJeff Kirsher 975adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 97651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 97751c1a580SMerav Sicron "cannot get access to nvram interface\n"); 978adfc5217SJeff Kirsher return -EBUSY; 979adfc5217SJeff Kirsher } 980adfc5217SJeff Kirsher 981adfc5217SJeff Kirsher return 0; 982adfc5217SJeff Kirsher } 983adfc5217SJeff Kirsher 984adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 985adfc5217SJeff Kirsher { 986adfc5217SJeff Kirsher int port = BP_PORT(bp); 987adfc5217SJeff Kirsher int count, i; 988f16da43bSAriel Elior u32 val; 989adfc5217SJeff Kirsher 990adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 991adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 992adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 993adfc5217SJeff Kirsher count *= 100; 994adfc5217SJeff Kirsher 995adfc5217SJeff Kirsher /* relinquish nvram interface */ 996adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 997adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 998adfc5217SJeff Kirsher 999adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1000adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1001adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1002adfc5217SJeff Kirsher break; 1003adfc5217SJeff Kirsher 1004adfc5217SJeff Kirsher udelay(5); 1005adfc5217SJeff Kirsher } 1006adfc5217SJeff Kirsher 1007adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 100851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 100951c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1010adfc5217SJeff Kirsher return -EBUSY; 1011adfc5217SJeff Kirsher } 1012adfc5217SJeff Kirsher 1013f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1014f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1015adfc5217SJeff Kirsher return 0; 1016adfc5217SJeff Kirsher } 1017adfc5217SJeff Kirsher 1018adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1019adfc5217SJeff Kirsher { 1020adfc5217SJeff Kirsher u32 val; 1021adfc5217SJeff Kirsher 1022adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1023adfc5217SJeff Kirsher 1024adfc5217SJeff Kirsher /* enable both bits, even on read */ 1025adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1026adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1027adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1028adfc5217SJeff Kirsher } 1029adfc5217SJeff Kirsher 1030adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1031adfc5217SJeff Kirsher { 1032adfc5217SJeff Kirsher u32 val; 1033adfc5217SJeff Kirsher 1034adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1035adfc5217SJeff Kirsher 1036adfc5217SJeff Kirsher /* disable both bits, even after read */ 1037adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1038adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1039adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1040adfc5217SJeff Kirsher } 1041adfc5217SJeff Kirsher 1042adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1043adfc5217SJeff Kirsher u32 cmd_flags) 1044adfc5217SJeff Kirsher { 1045adfc5217SJeff Kirsher int count, i, rc; 1046adfc5217SJeff Kirsher u32 val; 1047adfc5217SJeff Kirsher 1048adfc5217SJeff Kirsher /* build the command word */ 1049adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1050adfc5217SJeff Kirsher 1051adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1052adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1053adfc5217SJeff Kirsher 1054adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1055adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1056adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1057adfc5217SJeff Kirsher 1058adfc5217SJeff Kirsher /* issue a read command */ 1059adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1060adfc5217SJeff Kirsher 1061adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1062adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1063adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1064adfc5217SJeff Kirsher count *= 100; 1065adfc5217SJeff Kirsher 1066adfc5217SJeff Kirsher /* wait for completion */ 1067adfc5217SJeff Kirsher *ret_val = 0; 1068adfc5217SJeff Kirsher rc = -EBUSY; 1069adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1070adfc5217SJeff Kirsher udelay(5); 1071adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1072adfc5217SJeff Kirsher 1073adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1074adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1075adfc5217SJeff Kirsher /* we read nvram data in cpu order 1076adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 1077adfc5217SJeff Kirsher * converting to big-endian will do the work */ 1078adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1079adfc5217SJeff Kirsher rc = 0; 1080adfc5217SJeff Kirsher break; 1081adfc5217SJeff Kirsher } 1082adfc5217SJeff Kirsher } 108351c1a580SMerav Sicron if (rc == -EBUSY) 108451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 108551c1a580SMerav Sicron "nvram read timeout expired\n"); 1086adfc5217SJeff Kirsher return rc; 1087adfc5217SJeff Kirsher } 1088adfc5217SJeff Kirsher 1089adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1090adfc5217SJeff Kirsher int buf_size) 1091adfc5217SJeff Kirsher { 1092adfc5217SJeff Kirsher int rc; 1093adfc5217SJeff Kirsher u32 cmd_flags; 1094adfc5217SJeff Kirsher __be32 val; 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 109751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1098adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1099adfc5217SJeff Kirsher offset, buf_size); 1100adfc5217SJeff Kirsher return -EINVAL; 1101adfc5217SJeff Kirsher } 1102adfc5217SJeff Kirsher 1103adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 110451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 110551c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1106adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1107adfc5217SJeff Kirsher return -EINVAL; 1108adfc5217SJeff Kirsher } 1109adfc5217SJeff Kirsher 1110adfc5217SJeff Kirsher /* request access to nvram interface */ 1111adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1112adfc5217SJeff Kirsher if (rc) 1113adfc5217SJeff Kirsher return rc; 1114adfc5217SJeff Kirsher 1115adfc5217SJeff Kirsher /* enable access to nvram interface */ 1116adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1117adfc5217SJeff Kirsher 1118adfc5217SJeff Kirsher /* read the first word(s) */ 1119adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1120adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1121adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1122adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1123adfc5217SJeff Kirsher 1124adfc5217SJeff Kirsher /* advance to the next dword */ 1125adfc5217SJeff Kirsher offset += sizeof(u32); 1126adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1127adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1128adfc5217SJeff Kirsher cmd_flags = 0; 1129adfc5217SJeff Kirsher } 1130adfc5217SJeff Kirsher 1131adfc5217SJeff Kirsher if (rc == 0) { 1132adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1133adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1134adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1135adfc5217SJeff Kirsher } 1136adfc5217SJeff Kirsher 1137adfc5217SJeff Kirsher /* disable access to nvram interface */ 1138adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1139adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1140adfc5217SJeff Kirsher 1141adfc5217SJeff Kirsher return rc; 1142adfc5217SJeff Kirsher } 1143adfc5217SJeff Kirsher 1144adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1145adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1146adfc5217SJeff Kirsher { 1147adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1148adfc5217SJeff Kirsher int rc; 1149adfc5217SJeff Kirsher 115051c1a580SMerav Sicron if (!netif_running(dev)) { 115151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 115251c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1153adfc5217SJeff Kirsher return -EAGAIN; 115451c1a580SMerav Sicron } 1155adfc5217SJeff Kirsher 115651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1157f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1158adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1159adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1160adfc5217SJeff Kirsher 1161adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1162adfc5217SJeff Kirsher 1163adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1164adfc5217SJeff Kirsher 1165adfc5217SJeff Kirsher return rc; 1166adfc5217SJeff Kirsher } 1167adfc5217SJeff Kirsher 116824ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 116924ea818eSYuval Mintz struct ethtool_eeprom *ee, 117024ea818eSYuval Mintz u8 *data) 117124ea818eSYuval Mintz { 117224ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 117324ea818eSYuval Mintz int rc = 0, phy_idx; 117424ea818eSYuval Mintz u8 *user_data = data; 117524ea818eSYuval Mintz int remaining_len = ee->len, xfer_size; 117624ea818eSYuval Mintz unsigned int page_off = ee->offset; 117724ea818eSYuval Mintz 117824ea818eSYuval Mintz if (!netif_running(dev)) { 117924ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 118024ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 118124ea818eSYuval Mintz return -EAGAIN; 118224ea818eSYuval Mintz } 118324ea818eSYuval Mintz 118424ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 118524ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 118624ea818eSYuval Mintz while (!rc && remaining_len > 0) { 118724ea818eSYuval Mintz xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ? 118824ea818eSYuval Mintz SFP_EEPROM_PAGE_SIZE : remaining_len; 118924ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 119024ea818eSYuval Mintz &bp->link_params, 119124ea818eSYuval Mintz page_off, 119224ea818eSYuval Mintz xfer_size, 119324ea818eSYuval Mintz user_data); 119424ea818eSYuval Mintz remaining_len -= xfer_size; 119524ea818eSYuval Mintz user_data += xfer_size; 119624ea818eSYuval Mintz page_off += xfer_size; 119724ea818eSYuval Mintz } 119824ea818eSYuval Mintz 119924ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 120024ea818eSYuval Mintz return rc; 120124ea818eSYuval Mintz } 120224ea818eSYuval Mintz 120324ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 120424ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 120524ea818eSYuval Mintz { 120624ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 120724ea818eSYuval Mintz int phy_idx; 120824ea818eSYuval Mintz if (!netif_running(dev)) { 120924ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 121024ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 121124ea818eSYuval Mintz return -EAGAIN; 121224ea818eSYuval Mintz } 121324ea818eSYuval Mintz 121424ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 121524ea818eSYuval Mintz switch (bp->link_params.phy[phy_idx].media_type) { 121624ea818eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 121724ea818eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 121824ea818eSYuval Mintz case ETH_PHY_DA_TWINAX: 121924ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 122024ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 122124ea818eSYuval Mintz return 0; 122224ea818eSYuval Mintz default: 122324ea818eSYuval Mintz return -EOPNOTSUPP; 122424ea818eSYuval Mintz } 122524ea818eSYuval Mintz } 122624ea818eSYuval Mintz 1227adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1228adfc5217SJeff Kirsher u32 cmd_flags) 1229adfc5217SJeff Kirsher { 1230adfc5217SJeff Kirsher int count, i, rc; 1231adfc5217SJeff Kirsher 1232adfc5217SJeff Kirsher /* build the command word */ 1233adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1234adfc5217SJeff Kirsher 1235adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1236adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1237adfc5217SJeff Kirsher 1238adfc5217SJeff Kirsher /* write the data */ 1239adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1240adfc5217SJeff Kirsher 1241adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1242adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1243adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1244adfc5217SJeff Kirsher 1245adfc5217SJeff Kirsher /* issue the write command */ 1246adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1247adfc5217SJeff Kirsher 1248adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1249adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1250adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1251adfc5217SJeff Kirsher count *= 100; 1252adfc5217SJeff Kirsher 1253adfc5217SJeff Kirsher /* wait for completion */ 1254adfc5217SJeff Kirsher rc = -EBUSY; 1255adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1256adfc5217SJeff Kirsher udelay(5); 1257adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1258adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1259adfc5217SJeff Kirsher rc = 0; 1260adfc5217SJeff Kirsher break; 1261adfc5217SJeff Kirsher } 1262adfc5217SJeff Kirsher } 1263adfc5217SJeff Kirsher 126451c1a580SMerav Sicron if (rc == -EBUSY) 126551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 126651c1a580SMerav Sicron "nvram write timeout expired\n"); 1267adfc5217SJeff Kirsher return rc; 1268adfc5217SJeff Kirsher } 1269adfc5217SJeff Kirsher 1270adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1271adfc5217SJeff Kirsher 1272adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1273adfc5217SJeff Kirsher int buf_size) 1274adfc5217SJeff Kirsher { 1275adfc5217SJeff Kirsher int rc; 1276adfc5217SJeff Kirsher u32 cmd_flags; 1277adfc5217SJeff Kirsher u32 align_offset; 1278adfc5217SJeff Kirsher __be32 val; 1279adfc5217SJeff Kirsher 1280adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 128151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 128251c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1283adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1284adfc5217SJeff Kirsher return -EINVAL; 1285adfc5217SJeff Kirsher } 1286adfc5217SJeff Kirsher 1287adfc5217SJeff Kirsher /* request access to nvram interface */ 1288adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1289adfc5217SJeff Kirsher if (rc) 1290adfc5217SJeff Kirsher return rc; 1291adfc5217SJeff Kirsher 1292adfc5217SJeff Kirsher /* enable access to nvram interface */ 1293adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1294adfc5217SJeff Kirsher 1295adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1296adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 1297adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); 1298adfc5217SJeff Kirsher 1299adfc5217SJeff Kirsher if (rc == 0) { 1300adfc5217SJeff Kirsher val &= ~(0xff << BYTE_OFFSET(offset)); 1301adfc5217SJeff Kirsher val |= (*data_buf << BYTE_OFFSET(offset)); 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 1304adfc5217SJeff Kirsher * convert it back to cpu order */ 1305adfc5217SJeff Kirsher val = be32_to_cpu(val); 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1308adfc5217SJeff Kirsher cmd_flags); 1309adfc5217SJeff Kirsher } 1310adfc5217SJeff Kirsher 1311adfc5217SJeff Kirsher /* disable access to nvram interface */ 1312adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1313adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1314adfc5217SJeff Kirsher 1315adfc5217SJeff Kirsher return rc; 1316adfc5217SJeff Kirsher } 1317adfc5217SJeff Kirsher 1318adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1319adfc5217SJeff Kirsher int buf_size) 1320adfc5217SJeff Kirsher { 1321adfc5217SJeff Kirsher int rc; 1322adfc5217SJeff Kirsher u32 cmd_flags; 1323adfc5217SJeff Kirsher u32 val; 1324adfc5217SJeff Kirsher u32 written_so_far; 1325adfc5217SJeff Kirsher 1326adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1327adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1328adfc5217SJeff Kirsher 1329adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 133051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1331adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1332adfc5217SJeff Kirsher offset, buf_size); 1333adfc5217SJeff Kirsher return -EINVAL; 1334adfc5217SJeff Kirsher } 1335adfc5217SJeff Kirsher 1336adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 133751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 133851c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1339adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1340adfc5217SJeff Kirsher return -EINVAL; 1341adfc5217SJeff Kirsher } 1342adfc5217SJeff Kirsher 1343adfc5217SJeff Kirsher /* request access to nvram interface */ 1344adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1345adfc5217SJeff Kirsher if (rc) 1346adfc5217SJeff Kirsher return rc; 1347adfc5217SJeff Kirsher 1348adfc5217SJeff Kirsher /* enable access to nvram interface */ 1349adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1350adfc5217SJeff Kirsher 1351adfc5217SJeff Kirsher written_so_far = 0; 1352adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1353adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1354adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1355adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1356adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1357adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1358adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1359adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1360adfc5217SJeff Kirsher 1361adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1362adfc5217SJeff Kirsher 1363adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1364adfc5217SJeff Kirsher 1365adfc5217SJeff Kirsher /* advance to the next dword */ 1366adfc5217SJeff Kirsher offset += sizeof(u32); 1367adfc5217SJeff Kirsher data_buf += sizeof(u32); 1368adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1369adfc5217SJeff Kirsher cmd_flags = 0; 1370adfc5217SJeff Kirsher } 1371adfc5217SJeff Kirsher 1372adfc5217SJeff Kirsher /* disable access to nvram interface */ 1373adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1374adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1375adfc5217SJeff Kirsher 1376adfc5217SJeff Kirsher return rc; 1377adfc5217SJeff Kirsher } 1378adfc5217SJeff Kirsher 1379adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1380adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1381adfc5217SJeff Kirsher { 1382adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1383adfc5217SJeff Kirsher int port = BP_PORT(bp); 1384adfc5217SJeff Kirsher int rc = 0; 1385adfc5217SJeff Kirsher u32 ext_phy_config; 138651c1a580SMerav Sicron if (!netif_running(dev)) { 138751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 138851c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1389adfc5217SJeff Kirsher return -EAGAIN; 139051c1a580SMerav Sicron } 1391adfc5217SJeff Kirsher 139251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1393f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1394adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1395adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1396adfc5217SJeff Kirsher 1397adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1398adfc5217SJeff Kirsher 1399adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1400adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 140151c1a580SMerav Sicron !bp->port.pmf) { 140251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 140351c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1404adfc5217SJeff Kirsher return -EINVAL; 140551c1a580SMerav Sicron } 1406adfc5217SJeff Kirsher 1407adfc5217SJeff Kirsher ext_phy_config = 1408adfc5217SJeff Kirsher SHMEM_RD(bp, 1409adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1410adfc5217SJeff Kirsher 1411adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1412adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1413adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1414adfc5217SJeff Kirsher 1415adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1416adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1417adfc5217SJeff Kirsher &bp->link_vars, 0); 1418adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1419adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1420adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1421adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1422adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1423adfc5217SJeff Kirsher bnx2x_link_report(bp); 1424adfc5217SJeff Kirsher 1425adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1426adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1427adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1428adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1429adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1430adfc5217SJeff Kirsher &bp->link_vars, 1); 1431adfc5217SJeff Kirsher 1432adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1433adfc5217SJeff Kirsher &bp->link_vars); 1434adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1435adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1436adfc5217SJeff Kirsher } 1437adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1438adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1439adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1440adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1441adfc5217SJeff Kirsher 1442adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1443adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1444adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1445adfc5217SJeff Kirsher 1446adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1447adfc5217SJeff Kirsher 1448adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1449adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1450adfc5217SJeff Kirsher 1451adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1452adfc5217SJeff Kirsher msleep(500); 1453adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1454adfc5217SJeff Kirsher msleep(500); 1455adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1456adfc5217SJeff Kirsher } 1457adfc5217SJeff Kirsher } else 1458adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1459adfc5217SJeff Kirsher 1460adfc5217SJeff Kirsher return rc; 1461adfc5217SJeff Kirsher } 1462adfc5217SJeff Kirsher 1463adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1464adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1465adfc5217SJeff Kirsher { 1466adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1467adfc5217SJeff Kirsher 1468adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1469adfc5217SJeff Kirsher 1470adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1471adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1472adfc5217SJeff Kirsher 1473adfc5217SJeff Kirsher return 0; 1474adfc5217SJeff Kirsher } 1475adfc5217SJeff Kirsher 1476adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1477adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1478adfc5217SJeff Kirsher { 1479adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1480adfc5217SJeff Kirsher 1481adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1482adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1483adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1484adfc5217SJeff Kirsher 1485adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1486adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1487adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1488adfc5217SJeff Kirsher 1489adfc5217SJeff Kirsher if (netif_running(dev)) 1490adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1491adfc5217SJeff Kirsher 1492adfc5217SJeff Kirsher return 0; 1493adfc5217SJeff Kirsher } 1494adfc5217SJeff Kirsher 1495adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1496adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1497adfc5217SJeff Kirsher { 1498adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1499adfc5217SJeff Kirsher 1500adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1501adfc5217SJeff Kirsher 1502adfc5217SJeff Kirsher if (bp->rx_ring_size) 1503adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1504adfc5217SJeff Kirsher else 1505adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1506adfc5217SJeff Kirsher 1507a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1508adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1509adfc5217SJeff Kirsher } 1510adfc5217SJeff Kirsher 1511adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1512adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1513adfc5217SJeff Kirsher { 1514adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1515adfc5217SJeff Kirsher 1516adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 151751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 151851c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1519adfc5217SJeff Kirsher return -EAGAIN; 1520adfc5217SJeff Kirsher } 1521adfc5217SJeff Kirsher 1522adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1523adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1524adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1525a3348722SBarak Witkowski (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 152651c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 152751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1528adfc5217SJeff Kirsher return -EINVAL; 152951c1a580SMerav Sicron } 1530adfc5217SJeff Kirsher 1531adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1532adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1533adfc5217SJeff Kirsher 1534adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1535adfc5217SJeff Kirsher } 1536adfc5217SJeff Kirsher 1537adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1538adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1539adfc5217SJeff Kirsher { 1540adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1541adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 15429e7e8399SMintz Yuval int cfg_reg; 15439e7e8399SMintz Yuval 1544adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1545adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1546adfc5217SJeff Kirsher 15479e7e8399SMintz Yuval if (!epause->autoneg) 1548241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 15499e7e8399SMintz Yuval else 15509e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 15519e7e8399SMintz Yuval 15529e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1553adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 15549e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1555adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1556adfc5217SJeff Kirsher 155751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1558f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1559adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1560adfc5217SJeff Kirsher } 1561adfc5217SJeff Kirsher 1562adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1563adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1564adfc5217SJeff Kirsher { 1565adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1566adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1567adfc5217SJeff Kirsher if (IS_MF(bp)) 1568adfc5217SJeff Kirsher return 0; 1569adfc5217SJeff Kirsher 157051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1571f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1572adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1573adfc5217SJeff Kirsher 1574adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1575adfc5217SJeff Kirsher 1576adfc5217SJeff Kirsher if (epause->rx_pause) 1577adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1578adfc5217SJeff Kirsher 1579adfc5217SJeff Kirsher if (epause->tx_pause) 1580adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1581adfc5217SJeff Kirsher 1582adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1583adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1584adfc5217SJeff Kirsher 1585adfc5217SJeff Kirsher if (epause->autoneg) { 1586adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 158751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1588adfc5217SJeff Kirsher return -EINVAL; 1589adfc5217SJeff Kirsher } 1590adfc5217SJeff Kirsher 1591adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1592adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1593adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1594adfc5217SJeff Kirsher } 15955cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE; 15965cd75f0cSYaniv Rosner if (epause->rx_pause) 15975cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 15985cd75f0cSYaniv Rosner 15995cd75f0cSYaniv Rosner if (epause->tx_pause) 16005cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1601adfc5217SJeff Kirsher } 1602adfc5217SJeff Kirsher 160351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1604adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1605adfc5217SJeff Kirsher 1606adfc5217SJeff Kirsher if (netif_running(dev)) { 1607adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1608adfc5217SJeff Kirsher bnx2x_link_set(bp); 1609adfc5217SJeff Kirsher } 1610adfc5217SJeff Kirsher 1611adfc5217SJeff Kirsher return 0; 1612adfc5217SJeff Kirsher } 1613adfc5217SJeff Kirsher 16145889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1615cf2c1df6SMerav Sicron "register_test (offline) ", 1616cf2c1df6SMerav Sicron "memory_test (offline) ", 1617cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1618cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1619cf2c1df6SMerav Sicron "nvram_test (online) ", 1620cf2c1df6SMerav Sicron "interrupt_test (online) ", 1621cf2c1df6SMerav Sicron "link_test (online) " 1622adfc5217SJeff Kirsher }; 1623adfc5217SJeff Kirsher 1624e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 1625e9939c80SYuval Mintz { 1626e9939c80SYuval Mintz u32 modes = 0; 1627e9939c80SYuval Mintz 1628e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 1629e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 1630e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 1631e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 1632e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 1633e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 1634e9939c80SYuval Mintz 1635e9939c80SYuval Mintz return modes; 1636e9939c80SYuval Mintz } 1637e9939c80SYuval Mintz 1638e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1639e9939c80SYuval Mintz { 1640e9939c80SYuval Mintz u32 eee_adv = 0; 1641e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 1642e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 1643e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 1644e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 1645e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 1646e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 1647e9939c80SYuval Mintz 1648e9939c80SYuval Mintz return eee_adv << shift; 1649e9939c80SYuval Mintz } 1650e9939c80SYuval Mintz 1651e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1652e9939c80SYuval Mintz { 1653e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1654e9939c80SYuval Mintz u32 eee_cfg; 1655e9939c80SYuval Mintz 1656e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1657e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1658e9939c80SYuval Mintz return -EOPNOTSUPP; 1659e9939c80SYuval Mintz } 1660e9939c80SYuval Mintz 166108e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1662e9939c80SYuval Mintz 1663e9939c80SYuval Mintz edata->supported = 1664e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 1665e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 1666e9939c80SYuval Mintz 1667e9939c80SYuval Mintz edata->advertised = 1668e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 1669e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1670e9939c80SYuval Mintz edata->lp_advertised = 1671e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 1672e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 1673e9939c80SYuval Mintz 1674e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 1675e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 1676e9939c80SYuval Mintz 1677e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 1678e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 1679e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 1680e9939c80SYuval Mintz 1681e9939c80SYuval Mintz return 0; 1682e9939c80SYuval Mintz } 1683e9939c80SYuval Mintz 1684e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 1685e9939c80SYuval Mintz { 1686e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1687e9939c80SYuval Mintz u32 eee_cfg; 1688e9939c80SYuval Mintz u32 advertised; 1689e9939c80SYuval Mintz 1690e9939c80SYuval Mintz if (IS_MF(bp)) 1691e9939c80SYuval Mintz return 0; 1692e9939c80SYuval Mintz 1693e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1694e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1695e9939c80SYuval Mintz return -EOPNOTSUPP; 1696e9939c80SYuval Mintz } 1697e9939c80SYuval Mintz 169808e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1699e9939c80SYuval Mintz 1700e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 1701e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 1702e9939c80SYuval Mintz return -EOPNOTSUPP; 1703e9939c80SYuval Mintz } 1704e9939c80SYuval Mintz 1705e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 1706e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1707e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 1708e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1709efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 1710e9939c80SYuval Mintz return -EINVAL; 1711e9939c80SYuval Mintz } 1712e9939c80SYuval Mintz 1713e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 1714e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1715e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 1716e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 1717e9939c80SYuval Mintz return -EINVAL; 1718e9939c80SYuval Mintz } 1719e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 1720e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 1721e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1722e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 1723e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 1724e9939c80SYuval Mintz return -EINVAL; 1725e9939c80SYuval Mintz } 1726e9939c80SYuval Mintz 1727e9939c80SYuval Mintz /* All is well; Apply changes*/ 1728e9939c80SYuval Mintz if (edata->eee_enabled) 1729e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 1730e9939c80SYuval Mintz else 1731e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 1732e9939c80SYuval Mintz 1733e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 1734e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 1735e9939c80SYuval Mintz else 1736e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 1737e9939c80SYuval Mintz 1738e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 1739e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 1740e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 1741e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 1742e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 1743e9939c80SYuval Mintz 1744e9939c80SYuval Mintz /* Restart link to propogate changes */ 1745e9939c80SYuval Mintz if (netif_running(dev)) { 1746e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 17475d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1748e9939c80SYuval Mintz bnx2x_link_set(bp); 1749e9939c80SYuval Mintz } 1750e9939c80SYuval Mintz 1751e9939c80SYuval Mintz return 0; 1752e9939c80SYuval Mintz } 1753e9939c80SYuval Mintz 1754e9939c80SYuval Mintz 1755adfc5217SJeff Kirsher enum { 1756adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 1757adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 1758adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 1759adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 1760adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 1761adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 1762adfc5217SJeff Kirsher }; 1763adfc5217SJeff Kirsher 1764adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 1765adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 1766adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 1767adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 1768adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 1769adfc5217SJeff Kirsher 1770adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 1771adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 1772adfc5217SJeff Kirsher 1773adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 1774adfc5217SJeff Kirsher { 1775adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 1776adfc5217SJeff Kirsher u32 wr_val = 0, hw; 1777adfc5217SJeff Kirsher int port = BP_PORT(bp); 1778adfc5217SJeff Kirsher static const struct { 1779adfc5217SJeff Kirsher u32 hw; 1780adfc5217SJeff Kirsher u32 offset0; 1781adfc5217SJeff Kirsher u32 offset1; 1782adfc5217SJeff Kirsher u32 mask; 1783adfc5217SJeff Kirsher } reg_tbl[] = { 1784adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 1785adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 1786adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1787adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 1788adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 1789adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 1790adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1791adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 1792adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 1793adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 1794adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 1795adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 1796adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1797adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 1798adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1799adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 1800adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1801adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1802adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1803adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 1804adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 1805adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1806adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1807adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 1808adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1809adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 1810adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1811adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 1812adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1813adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 1814adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1815adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 1816adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1817adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 1818adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1819adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 1820adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1821adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 1822adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1823adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 1824adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1825adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 1826adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1827adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 1828adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1829adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 1830adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1831adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 1832adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1833adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 1834adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1835adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 1836adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1837adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 1838adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1839adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 1840adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1841adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 1842adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1843adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 1844adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 1845adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 1846adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1847adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 1848adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1849adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 1850adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1851adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 1852adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1853adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 1854adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1855adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 1856adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1857adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 1858adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1859adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 1860adfc5217SJeff Kirsher 1861adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 1862adfc5217SJeff Kirsher }; 1863adfc5217SJeff Kirsher 186451c1a580SMerav Sicron if (!netif_running(bp->dev)) { 186551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 186651c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1867adfc5217SJeff Kirsher return rc; 186851c1a580SMerav Sicron } 1869adfc5217SJeff Kirsher 1870adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1871adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 1872adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1873adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 1874adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1875adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 1876adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 1877adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 1878adfc5217SJeff Kirsher else /* e3 A0 */ 1879adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 1880adfc5217SJeff Kirsher 1881adfc5217SJeff Kirsher /* Repeat the test twice: 1882adfc5217SJeff Kirsher First by writing 0x00000000, second by writing 0xffffffff */ 1883adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 1884adfc5217SJeff Kirsher 1885adfc5217SJeff Kirsher switch (idx) { 1886adfc5217SJeff Kirsher case 0: 1887adfc5217SJeff Kirsher wr_val = 0; 1888adfc5217SJeff Kirsher break; 1889adfc5217SJeff Kirsher case 1: 1890adfc5217SJeff Kirsher wr_val = 0xffffffff; 1891adfc5217SJeff Kirsher break; 1892adfc5217SJeff Kirsher } 1893adfc5217SJeff Kirsher 1894adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 1895adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 1896adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 1897adfc5217SJeff Kirsher continue; 1898adfc5217SJeff Kirsher 1899adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 1900adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 1901adfc5217SJeff Kirsher 1902adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 1903adfc5217SJeff Kirsher 1904adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 1905adfc5217SJeff Kirsher 1906adfc5217SJeff Kirsher val = REG_RD(bp, offset); 1907adfc5217SJeff Kirsher 1908adfc5217SJeff Kirsher /* Restore the original register's value */ 1909adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 1910adfc5217SJeff Kirsher 1911adfc5217SJeff Kirsher /* verify value is as expected */ 1912adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 191351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1914adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 1915adfc5217SJeff Kirsher offset, val, wr_val, mask); 1916adfc5217SJeff Kirsher goto test_reg_exit; 1917adfc5217SJeff Kirsher } 1918adfc5217SJeff Kirsher } 1919adfc5217SJeff Kirsher } 1920adfc5217SJeff Kirsher 1921adfc5217SJeff Kirsher rc = 0; 1922adfc5217SJeff Kirsher 1923adfc5217SJeff Kirsher test_reg_exit: 1924adfc5217SJeff Kirsher return rc; 1925adfc5217SJeff Kirsher } 1926adfc5217SJeff Kirsher 1927adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 1928adfc5217SJeff Kirsher { 1929adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 1930adfc5217SJeff Kirsher u32 val, index; 1931adfc5217SJeff Kirsher static const struct { 1932adfc5217SJeff Kirsher u32 offset; 1933adfc5217SJeff Kirsher int size; 1934adfc5217SJeff Kirsher } mem_tbl[] = { 1935adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 1936adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 1937adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 1938adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 1939adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 1940adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 1941adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 1942adfc5217SJeff Kirsher 1943adfc5217SJeff Kirsher { 0xffffffff, 0 } 1944adfc5217SJeff Kirsher }; 1945adfc5217SJeff Kirsher 1946adfc5217SJeff Kirsher static const struct { 1947adfc5217SJeff Kirsher char *name; 1948adfc5217SJeff Kirsher u32 offset; 1949adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 1950adfc5217SJeff Kirsher } prty_tbl[] = { 1951adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 1952adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1953adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 1954adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 1955adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 1956adfc5217SJeff Kirsher {0, 0, 0, 0} }, 1957adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 1958adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1959adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 1960adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1961adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 1962adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 1963adfc5217SJeff Kirsher 1964adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 1965adfc5217SJeff Kirsher }; 1966adfc5217SJeff Kirsher 196751c1a580SMerav Sicron if (!netif_running(bp->dev)) { 196851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 196951c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1970adfc5217SJeff Kirsher return rc; 197151c1a580SMerav Sicron } 1972adfc5217SJeff Kirsher 1973adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1974adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 1975adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1976adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 1977adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1978adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 1979adfc5217SJeff Kirsher else /* e3 */ 1980adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 1981adfc5217SJeff Kirsher 1982adfc5217SJeff Kirsher /* pre-Check the parity status */ 1983adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1984adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 1985adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 198651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1987adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 1988adfc5217SJeff Kirsher goto test_mem_exit; 1989adfc5217SJeff Kirsher } 1990adfc5217SJeff Kirsher } 1991adfc5217SJeff Kirsher 1992adfc5217SJeff Kirsher /* Go through all the memories */ 1993adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 1994adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 1995adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 1996adfc5217SJeff Kirsher 1997adfc5217SJeff Kirsher /* Check the parity status */ 1998adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1999adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2000adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 200151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2002adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2003adfc5217SJeff Kirsher goto test_mem_exit; 2004adfc5217SJeff Kirsher } 2005adfc5217SJeff Kirsher } 2006adfc5217SJeff Kirsher 2007adfc5217SJeff Kirsher rc = 0; 2008adfc5217SJeff Kirsher 2009adfc5217SJeff Kirsher test_mem_exit: 2010adfc5217SJeff Kirsher return rc; 2011adfc5217SJeff Kirsher } 2012adfc5217SJeff Kirsher 2013adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2014adfc5217SJeff Kirsher { 2015adfc5217SJeff Kirsher int cnt = 1400; 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher if (link_up) { 2018adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2019adfc5217SJeff Kirsher msleep(20); 2020adfc5217SJeff Kirsher 2021adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 202251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 20238970b2e4SMerav Sicron 20248970b2e4SMerav Sicron cnt = 1400; 20258970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 20268970b2e4SMerav Sicron msleep(20); 20278970b2e4SMerav Sicron 20288970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 20298970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 20308970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2031adfc5217SJeff Kirsher } 2032adfc5217SJeff Kirsher } 2033adfc5217SJeff Kirsher 2034adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2035adfc5217SJeff Kirsher { 2036adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2037adfc5217SJeff Kirsher struct sk_buff *skb; 2038adfc5217SJeff Kirsher unsigned char *packet; 2039adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2040adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 204165565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2042adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2043adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2044b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2045adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2046adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2047adfc5217SJeff Kirsher dma_addr_t mapping; 2048adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2049adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2050adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2051adfc5217SJeff Kirsher u16 len; 2052adfc5217SJeff Kirsher int rc = -ENODEV; 2053e52fcb24SEric Dumazet u8 *data; 20548970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 20558970b2e4SMerav Sicron txdata->txq_index); 2056adfc5217SJeff Kirsher 2057adfc5217SJeff Kirsher /* check the loopback mode */ 2058adfc5217SJeff Kirsher switch (loopback_mode) { 2059adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 20608970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 20618970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2062adfc5217SJeff Kirsher return -EINVAL; 20638970b2e4SMerav Sicron } 2064adfc5217SJeff Kirsher break; 2065adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 206632911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 206732911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 206832911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 206932911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 207032911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 207132911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 207232911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 207332911333SYaniv Rosner else 207432911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 207532911333SYaniv Rosner } else 207632911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 207732911333SYaniv Rosner 2078adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2079adfc5217SJeff Kirsher break; 20808970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 20818970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 20828970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 20838970b2e4SMerav Sicron "Can't configure external loopback\n"); 20848970b2e4SMerav Sicron return -EINVAL; 20858970b2e4SMerav Sicron } 20868970b2e4SMerav Sicron break; 2087adfc5217SJeff Kirsher default: 208851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2089adfc5217SJeff Kirsher return -EINVAL; 2090adfc5217SJeff Kirsher } 2091adfc5217SJeff Kirsher 2092adfc5217SJeff Kirsher /* prepare the loopback packet */ 2093adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2094adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2095adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2096adfc5217SJeff Kirsher if (!skb) { 209751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2098adfc5217SJeff Kirsher rc = -ENOMEM; 2099adfc5217SJeff Kirsher goto test_loopback_exit; 2100adfc5217SJeff Kirsher } 2101adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2102adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2103adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 2104adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2105adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2106adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2107adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2108adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2109adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2110adfc5217SJeff Kirsher rc = -ENOMEM; 2111adfc5217SJeff Kirsher dev_kfree_skb(skb); 211251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2113adfc5217SJeff Kirsher goto test_loopback_exit; 2114adfc5217SJeff Kirsher } 2115adfc5217SJeff Kirsher 2116adfc5217SJeff Kirsher /* send the loopback packet */ 2117adfc5217SJeff Kirsher num_pkts = 0; 2118adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2119adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2120adfc5217SJeff Kirsher 212173dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 212273dbb5e1SDmitry Kravkov 2123adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2124adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2125adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2126adfc5217SJeff Kirsher tx_buf->skb = skb; 2127adfc5217SJeff Kirsher tx_buf->flags = 0; 2128adfc5217SJeff Kirsher 2129adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2130adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2131adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2132adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2133adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2134adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2135adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2136adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2137adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2138adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2139adfc5217SJeff Kirsher 1); 214096bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 214196bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 214296bed4b9SYuval Mintz 0); 2143adfc5217SJeff Kirsher 2144adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2145adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2146adfc5217SJeff Kirsher 214796bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 214896bed4b9SYuval Mintz u16 global_data = 0; 214996bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 215096bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2151adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 215296bed4b9SYuval Mintz SET_FLAG(global_data, 215396bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 215496bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 215596bed4b9SYuval Mintz } else { 215696bed4b9SYuval Mintz u32 parsing_data = 0; 215796bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 215896bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 215996bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 216096bed4b9SYuval Mintz SET_FLAG(parsing_data, 216196bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 216296bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 216396bed4b9SYuval Mintz } 2164adfc5217SJeff Kirsher wmb(); 2165adfc5217SJeff Kirsher 2166adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2167adfc5217SJeff Kirsher barrier(); 2168adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2169adfc5217SJeff Kirsher 2170adfc5217SJeff Kirsher mmiowb(); 2171adfc5217SJeff Kirsher barrier(); 2172adfc5217SJeff Kirsher 2173adfc5217SJeff Kirsher num_pkts++; 2174adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2175adfc5217SJeff Kirsher 2176adfc5217SJeff Kirsher udelay(100); 2177adfc5217SJeff Kirsher 2178adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2179adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2180adfc5217SJeff Kirsher goto test_loopback_exit; 2181adfc5217SJeff Kirsher 2182adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2183adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2184adfc5217SJeff Kirsher * disabled. 2185adfc5217SJeff Kirsher */ 2186adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2187adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2188adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2189adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2190adfc5217SJeff Kirsher */ 2191adfc5217SJeff Kirsher local_bh_disable(); 2192adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2193adfc5217SJeff Kirsher local_bh_enable(); 2194adfc5217SJeff Kirsher } 2195adfc5217SJeff Kirsher 2196adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2197adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2198adfc5217SJeff Kirsher goto test_loopback_exit; 2199adfc5217SJeff Kirsher 2200b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2201adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2202adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2203adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2204adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2205adfc5217SJeff Kirsher 2206621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2207adfc5217SJeff Kirsher if (len != pkt_size) 2208adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2209adfc5217SJeff Kirsher 2210adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2211adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2212adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2213adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2214e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2215adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2216e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2217adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2218adfc5217SJeff Kirsher 2219adfc5217SJeff Kirsher rc = 0; 2220adfc5217SJeff Kirsher 2221adfc5217SJeff Kirsher test_loopback_rx_exit: 2222adfc5217SJeff Kirsher 2223adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2224adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2225adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2226adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2227adfc5217SJeff Kirsher 2228adfc5217SJeff Kirsher /* Update producers */ 2229adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2230adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2231adfc5217SJeff Kirsher 2232adfc5217SJeff Kirsher test_loopback_exit: 2233adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2234adfc5217SJeff Kirsher 2235adfc5217SJeff Kirsher return rc; 2236adfc5217SJeff Kirsher } 2237adfc5217SJeff Kirsher 2238adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2239adfc5217SJeff Kirsher { 2240adfc5217SJeff Kirsher int rc = 0, res; 2241adfc5217SJeff Kirsher 2242adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2243adfc5217SJeff Kirsher return rc; 2244adfc5217SJeff Kirsher 2245adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2246adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2247adfc5217SJeff Kirsher 2248adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2249adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2250adfc5217SJeff Kirsher 2251adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2252adfc5217SJeff Kirsher if (res) { 225351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2254adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2255adfc5217SJeff Kirsher } 2256adfc5217SJeff Kirsher 2257adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2258adfc5217SJeff Kirsher if (res) { 225951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2260adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2261adfc5217SJeff Kirsher } 2262adfc5217SJeff Kirsher 2263adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2264adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2265adfc5217SJeff Kirsher 2266adfc5217SJeff Kirsher return rc; 2267adfc5217SJeff Kirsher } 2268adfc5217SJeff Kirsher 22698970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 22708970b2e4SMerav Sicron { 22718970b2e4SMerav Sicron int rc; 22728970b2e4SMerav Sicron u8 is_serdes = 22738970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 22748970b2e4SMerav Sicron 22758970b2e4SMerav Sicron if (BP_NOMCP(bp)) 22768970b2e4SMerav Sicron return -ENODEV; 22778970b2e4SMerav Sicron 22788970b2e4SMerav Sicron if (!netif_running(bp->dev)) 22798970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 22808970b2e4SMerav Sicron 22815d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 22828970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 22838970b2e4SMerav Sicron if (rc) { 22848970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 22858970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 22868970b2e4SMerav Sicron return -ENODEV; 22878970b2e4SMerav Sicron } 22888970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 22898970b2e4SMerav Sicron 22908970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 22918970b2e4SMerav Sicron 22928970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 22938970b2e4SMerav Sicron if (rc) 22948970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 22958970b2e4SMerav Sicron 22968970b2e4SMerav Sicron bnx2x_netif_start(bp); 22978970b2e4SMerav Sicron 22988970b2e4SMerav Sicron return rc; 22998970b2e4SMerav Sicron } 23008970b2e4SMerav Sicron 2301adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2302adfc5217SJeff Kirsher 2303adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2304adfc5217SJeff Kirsher { 2305adfc5217SJeff Kirsher static const struct { 2306adfc5217SJeff Kirsher int offset; 2307adfc5217SJeff Kirsher int size; 2308adfc5217SJeff Kirsher } nvram_tbl[] = { 2309adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2310adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2311adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2312adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2313adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2314adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2315adfc5217SJeff Kirsher { 0, 0 } 2316adfc5217SJeff Kirsher }; 2317afa13b4bSMintz Yuval __be32 *buf; 2318afa13b4bSMintz Yuval u8 *data; 2319adfc5217SJeff Kirsher int i, rc; 2320adfc5217SJeff Kirsher u32 magic, crc; 2321adfc5217SJeff Kirsher 2322adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2323adfc5217SJeff Kirsher return 0; 2324adfc5217SJeff Kirsher 2325afa13b4bSMintz Yuval buf = kmalloc(0x350, GFP_KERNEL); 2326afa13b4bSMintz Yuval if (!buf) { 232751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2328afa13b4bSMintz Yuval rc = -ENOMEM; 2329afa13b4bSMintz Yuval goto test_nvram_exit; 2330afa13b4bSMintz Yuval } 2331afa13b4bSMintz Yuval data = (u8 *)buf; 2332afa13b4bSMintz Yuval 2333adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, 0, data, 4); 2334adfc5217SJeff Kirsher if (rc) { 233551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 233651c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2337adfc5217SJeff Kirsher goto test_nvram_exit; 2338adfc5217SJeff Kirsher } 2339adfc5217SJeff Kirsher 2340adfc5217SJeff Kirsher magic = be32_to_cpu(buf[0]); 2341adfc5217SJeff Kirsher if (magic != 0x669955aa) { 234251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 234351c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2344adfc5217SJeff Kirsher rc = -ENODEV; 2345adfc5217SJeff Kirsher goto test_nvram_exit; 2346adfc5217SJeff Kirsher } 2347adfc5217SJeff Kirsher 2348adfc5217SJeff Kirsher for (i = 0; nvram_tbl[i].size; i++) { 2349adfc5217SJeff Kirsher 2350adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 2351adfc5217SJeff Kirsher nvram_tbl[i].size); 2352adfc5217SJeff Kirsher if (rc) { 235351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2354adfc5217SJeff Kirsher "nvram_tbl[%d] read data (rc %d)\n", i, rc); 2355adfc5217SJeff Kirsher goto test_nvram_exit; 2356adfc5217SJeff Kirsher } 2357adfc5217SJeff Kirsher 2358adfc5217SJeff Kirsher crc = ether_crc_le(nvram_tbl[i].size, data); 2359adfc5217SJeff Kirsher if (crc != CRC32_RESIDUAL) { 236051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 236151c1a580SMerav Sicron "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc); 2362adfc5217SJeff Kirsher rc = -ENODEV; 2363adfc5217SJeff Kirsher goto test_nvram_exit; 2364adfc5217SJeff Kirsher } 2365adfc5217SJeff Kirsher } 2366adfc5217SJeff Kirsher 2367adfc5217SJeff Kirsher test_nvram_exit: 2368afa13b4bSMintz Yuval kfree(buf); 2369adfc5217SJeff Kirsher return rc; 2370adfc5217SJeff Kirsher } 2371adfc5217SJeff Kirsher 2372adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2373adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2374adfc5217SJeff Kirsher { 23753b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2376adfc5217SJeff Kirsher 237751c1a580SMerav Sicron if (!netif_running(bp->dev)) { 237851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 237951c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2380adfc5217SJeff Kirsher return -ENODEV; 238151c1a580SMerav Sicron } 2382adfc5217SJeff Kirsher 238315192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2384adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2385adfc5217SJeff Kirsher 2386adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2387adfc5217SJeff Kirsher 2388adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2389adfc5217SJeff Kirsher } 2390adfc5217SJeff Kirsher 2391adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2392adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2393adfc5217SJeff Kirsher { 2394adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2395adfc5217SJeff Kirsher u8 is_serdes; 2396cf2c1df6SMerav Sicron int rc; 2397cf2c1df6SMerav Sicron 2398adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 239951c1a580SMerav Sicron netdev_err(bp->dev, 240051c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2401adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2402adfc5217SJeff Kirsher return; 2403adfc5217SJeff Kirsher } 24048970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24058970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 24068970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 24078970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2408adfc5217SJeff Kirsher 2409cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2410adfc5217SJeff Kirsher 2411cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2412cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2413cf2c1df6SMerav Sicron "Can't perform self-test when interface is down\n"); 2414adfc5217SJeff Kirsher return; 2415cf2c1df6SMerav Sicron } 2416adfc5217SJeff Kirsher 2417adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2418adfc5217SJeff Kirsher 2419cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2420cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2421adfc5217SJeff Kirsher int port = BP_PORT(bp); 2422adfc5217SJeff Kirsher u32 val; 2423adfc5217SJeff Kirsher u8 link_up; 2424adfc5217SJeff Kirsher 2425adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2426adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2427adfc5217SJeff Kirsher /* disable input for TX port IF */ 2428adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2429adfc5217SJeff Kirsher 2430adfc5217SJeff Kirsher link_up = bp->link_vars.link_up; 2431adfc5217SJeff Kirsher 24325d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2433cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2434cf2c1df6SMerav Sicron if (rc) { 2435cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2436cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2437cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2438cf2c1df6SMerav Sicron return; 2439cf2c1df6SMerav Sicron } 2440cf2c1df6SMerav Sicron 2441adfc5217SJeff Kirsher /* wait until link state is restored */ 2442adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2443adfc5217SJeff Kirsher 2444adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2445adfc5217SJeff Kirsher buf[0] = 1; 2446adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2447adfc5217SJeff Kirsher } 2448adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2449adfc5217SJeff Kirsher buf[1] = 1; 2450adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2451adfc5217SJeff Kirsher } 2452adfc5217SJeff Kirsher 24538970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2454adfc5217SJeff Kirsher if (buf[2] != 0) 2455adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2456adfc5217SJeff Kirsher 24578970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 24588970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 24598970b2e4SMerav Sicron if (buf[3] != 0) 24608970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 24618970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 24628970b2e4SMerav Sicron } 24638970b2e4SMerav Sicron 24645d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2465adfc5217SJeff Kirsher 2466adfc5217SJeff Kirsher /* restore input for TX port IF */ 2467adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2468cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2469cf2c1df6SMerav Sicron if (rc) { 2470cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2471cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2472cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 2473cf2c1df6SMerav Sicron return; 2474cf2c1df6SMerav Sicron } 2475adfc5217SJeff Kirsher /* wait until link state is restored */ 2476adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2477adfc5217SJeff Kirsher } 2478adfc5217SJeff Kirsher if (bnx2x_test_nvram(bp) != 0) { 2479cf2c1df6SMerav Sicron if (!IS_MF(bp)) 24808970b2e4SMerav Sicron buf[4] = 1; 2481cf2c1df6SMerav Sicron else 2482cf2c1df6SMerav Sicron buf[0] = 1; 2483adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2484adfc5217SJeff Kirsher } 2485adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2486cf2c1df6SMerav Sicron if (!IS_MF(bp)) 24878970b2e4SMerav Sicron buf[5] = 1; 2488cf2c1df6SMerav Sicron else 2489cf2c1df6SMerav Sicron buf[1] = 1; 2490adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2491adfc5217SJeff Kirsher } 2492adfc5217SJeff Kirsher 2493adfc5217SJeff Kirsher if (bnx2x_link_test(bp, is_serdes) != 0) { 2494cf2c1df6SMerav Sicron if (!IS_MF(bp)) 24958970b2e4SMerav Sicron buf[6] = 1; 2496cf2c1df6SMerav Sicron else 2497cf2c1df6SMerav Sicron buf[2] = 1; 2498adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2499adfc5217SJeff Kirsher } 2500adfc5217SJeff Kirsher 2501adfc5217SJeff Kirsher #ifdef BNX2X_EXTRA_DEBUG 2502adfc5217SJeff Kirsher bnx2x_panic_dump(bp); 2503adfc5217SJeff Kirsher #endif 2504adfc5217SJeff Kirsher } 2505adfc5217SJeff Kirsher 2506adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 2507adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2508adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2509adfc5217SJeff Kirsher #define IS_MF_MODE_STAT(bp) \ 2510adfc5217SJeff Kirsher (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2511adfc5217SJeff Kirsher 2512adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 2513adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 2514adfc5217SJeff Kirsher */ 25151191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 2516adfc5217SJeff Kirsher { 2517adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 2518adfc5217SJeff Kirsher } 2519adfc5217SJeff Kirsher 2520adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2521adfc5217SJeff Kirsher { 2522adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2523adfc5217SJeff Kirsher int i, num_stats; 2524adfc5217SJeff Kirsher 2525adfc5217SJeff Kirsher switch (stringset) { 2526adfc5217SJeff Kirsher case ETH_SS_STATS: 2527adfc5217SJeff Kirsher if (is_multi(bp)) { 2528adfc5217SJeff Kirsher num_stats = bnx2x_num_stat_queues(bp) * 2529adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 2530d5e83632SYuval Mintz } else 2531adfc5217SJeff Kirsher num_stats = 0; 2532d5e83632SYuval Mintz if (IS_MF_MODE_STAT(bp)) { 2533adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 2534adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 2535adfc5217SJeff Kirsher num_stats++; 2536adfc5217SJeff Kirsher } else 2537d5e83632SYuval Mintz num_stats += BNX2X_NUM_STATS; 2538d5e83632SYuval Mintz 2539adfc5217SJeff Kirsher return num_stats; 2540adfc5217SJeff Kirsher 2541adfc5217SJeff Kirsher case ETH_SS_TEST: 2542cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 2543adfc5217SJeff Kirsher 2544adfc5217SJeff Kirsher default: 2545adfc5217SJeff Kirsher return -EINVAL; 2546adfc5217SJeff Kirsher } 2547adfc5217SJeff Kirsher } 2548adfc5217SJeff Kirsher 2549adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 2550adfc5217SJeff Kirsher { 2551adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 25525889335cSMerav Sicron int i, j, k, start; 2553adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 2554adfc5217SJeff Kirsher 2555adfc5217SJeff Kirsher switch (stringset) { 2556adfc5217SJeff Kirsher case ETH_SS_STATS: 2557adfc5217SJeff Kirsher k = 0; 2558d5e83632SYuval Mintz if (is_multi(bp)) { 2559adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 2560adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 2561adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 2562adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 2563adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 2564adfc5217SJeff Kirsher ETH_GSTRING_LEN, 2565adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 2566adfc5217SJeff Kirsher queue_name); 2567adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2568adfc5217SJeff Kirsher } 2569d5e83632SYuval Mintz } 2570d5e83632SYuval Mintz 2571d5e83632SYuval Mintz 2572adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2573adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2574adfc5217SJeff Kirsher continue; 2575d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 2576adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 2577adfc5217SJeff Kirsher j++; 2578adfc5217SJeff Kirsher } 2579d5e83632SYuval Mintz 2580adfc5217SJeff Kirsher break; 2581adfc5217SJeff Kirsher 2582adfc5217SJeff Kirsher case ETH_SS_TEST: 2583cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 2584cf2c1df6SMerav Sicron if (!IS_MF(bp)) 2585cf2c1df6SMerav Sicron start = 0; 2586cf2c1df6SMerav Sicron else 2587cf2c1df6SMerav Sicron start = 4; 25885889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 25895889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 2590adfc5217SJeff Kirsher } 2591adfc5217SJeff Kirsher } 2592adfc5217SJeff Kirsher 2593adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 2594adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 2595adfc5217SJeff Kirsher { 2596adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2597adfc5217SJeff Kirsher u32 *hw_stats, *offset; 2598d5e83632SYuval Mintz int i, j, k = 0; 2599adfc5217SJeff Kirsher 2600adfc5217SJeff Kirsher if (is_multi(bp)) { 2601adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 260215192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 2603adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 2604adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 2605adfc5217SJeff Kirsher /* skip this counter */ 2606adfc5217SJeff Kirsher buf[k + j] = 0; 2607adfc5217SJeff Kirsher continue; 2608adfc5217SJeff Kirsher } 2609adfc5217SJeff Kirsher offset = (hw_stats + 2610adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 2611adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 2612adfc5217SJeff Kirsher /* 4-byte counter */ 2613adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 2614adfc5217SJeff Kirsher continue; 2615adfc5217SJeff Kirsher } 2616adfc5217SJeff Kirsher /* 8-byte counter */ 2617adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2618adfc5217SJeff Kirsher } 2619adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2620adfc5217SJeff Kirsher } 2621adfc5217SJeff Kirsher } 2622d5e83632SYuval Mintz 2623adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 2624adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2625adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2626adfc5217SJeff Kirsher continue; 2627adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 2628adfc5217SJeff Kirsher /* skip this counter */ 2629d5e83632SYuval Mintz buf[k + j] = 0; 2630adfc5217SJeff Kirsher j++; 2631adfc5217SJeff Kirsher continue; 2632adfc5217SJeff Kirsher } 2633adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 2634adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 2635adfc5217SJeff Kirsher /* 4-byte counter */ 2636d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 2637adfc5217SJeff Kirsher j++; 2638adfc5217SJeff Kirsher continue; 2639adfc5217SJeff Kirsher } 2640adfc5217SJeff Kirsher /* 8-byte counter */ 2641d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2642adfc5217SJeff Kirsher j++; 2643adfc5217SJeff Kirsher } 2644adfc5217SJeff Kirsher } 2645adfc5217SJeff Kirsher 2646adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 2647adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 2648adfc5217SJeff Kirsher { 2649adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2650adfc5217SJeff Kirsher 265151c1a580SMerav Sicron if (!netif_running(dev)) { 265251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 265351c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2654adfc5217SJeff Kirsher return -EAGAIN; 265551c1a580SMerav Sicron } 2656adfc5217SJeff Kirsher 265751c1a580SMerav Sicron if (!bp->port.pmf) { 265851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n"); 2659adfc5217SJeff Kirsher return -EOPNOTSUPP; 266051c1a580SMerav Sicron } 2661adfc5217SJeff Kirsher 2662adfc5217SJeff Kirsher switch (state) { 2663adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 2664adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 2665adfc5217SJeff Kirsher 2666adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 26678203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2668adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2669adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 26708203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2671adfc5217SJeff Kirsher break; 2672adfc5217SJeff Kirsher 2673adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 26748203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2675adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2676adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 26778203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2678adfc5217SJeff Kirsher break; 2679adfc5217SJeff Kirsher 2680adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 26818203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2682adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2683adfc5217SJeff Kirsher LED_MODE_OPER, 2684adfc5217SJeff Kirsher bp->link_vars.line_speed); 26858203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2686adfc5217SJeff Kirsher } 2687adfc5217SJeff Kirsher 2688adfc5217SJeff Kirsher return 0; 2689adfc5217SJeff Kirsher } 2690adfc5217SJeff Kirsher 26915d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 26925d317c6aSMerav Sicron { 26935d317c6aSMerav Sicron 26945d317c6aSMerav Sicron switch (info->flow_type) { 26955d317c6aSMerav Sicron case TCP_V4_FLOW: 26965d317c6aSMerav Sicron case TCP_V6_FLOW: 26975d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 26985d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 26995d317c6aSMerav Sicron break; 27005d317c6aSMerav Sicron case UDP_V4_FLOW: 27015d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 27025d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 27035d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 27045d317c6aSMerav Sicron else 27055d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 27065d317c6aSMerav Sicron break; 27075d317c6aSMerav Sicron case UDP_V6_FLOW: 27085d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 27095d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 27105d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 27115d317c6aSMerav Sicron else 27125d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 27135d317c6aSMerav Sicron break; 27145d317c6aSMerav Sicron case IPV4_FLOW: 27155d317c6aSMerav Sicron case IPV6_FLOW: 27165d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 27175d317c6aSMerav Sicron break; 27185d317c6aSMerav Sicron default: 27195d317c6aSMerav Sicron info->data = 0; 27205d317c6aSMerav Sicron break; 27215d317c6aSMerav Sicron } 27225d317c6aSMerav Sicron 27235d317c6aSMerav Sicron return 0; 27245d317c6aSMerav Sicron } 27255d317c6aSMerav Sicron 2726adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2727815c7db5SBen Hutchings u32 *rules __always_unused) 2728adfc5217SJeff Kirsher { 2729adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2730adfc5217SJeff Kirsher 2731adfc5217SJeff Kirsher switch (info->cmd) { 2732adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 2733adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 2734adfc5217SJeff Kirsher return 0; 27355d317c6aSMerav Sicron case ETHTOOL_GRXFH: 27365d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 27375d317c6aSMerav Sicron default: 27385d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 27395d317c6aSMerav Sicron return -EOPNOTSUPP; 27405d317c6aSMerav Sicron } 27415d317c6aSMerav Sicron } 2742adfc5217SJeff Kirsher 27435d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 27445d317c6aSMerav Sicron { 27455d317c6aSMerav Sicron int udp_rss_requested; 27465d317c6aSMerav Sicron 27475d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27485d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 27495d317c6aSMerav Sicron info->flow_type, info->data); 27505d317c6aSMerav Sicron 27515d317c6aSMerav Sicron switch (info->flow_type) { 27525d317c6aSMerav Sicron case TCP_V4_FLOW: 27535d317c6aSMerav Sicron case TCP_V6_FLOW: 27545d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 27555d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 27565d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 27575d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27585d317c6aSMerav Sicron "Command parameters not supported\n"); 27595d317c6aSMerav Sicron return -EINVAL; 27605d317c6aSMerav Sicron } else { 27615d317c6aSMerav Sicron return 0; 27625d317c6aSMerav Sicron } 27635d317c6aSMerav Sicron 27645d317c6aSMerav Sicron case UDP_V4_FLOW: 27655d317c6aSMerav Sicron case UDP_V6_FLOW: 27665d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 27675d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 27685d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 27695d317c6aSMerav Sicron udp_rss_requested = 1; 27705d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 27715d317c6aSMerav Sicron udp_rss_requested = 0; 27725d317c6aSMerav Sicron else 27735d317c6aSMerav Sicron return -EINVAL; 27745d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 27755d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 27765d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 27775d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27785d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 27795d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 27805d317c6aSMerav Sicron return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 27815d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 27825d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 27835d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 27845d317c6aSMerav Sicron return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 27855d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27865d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 27875d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 27885d317c6aSMerav Sicron } else { 27895d317c6aSMerav Sicron return 0; 27905d317c6aSMerav Sicron } 27915d317c6aSMerav Sicron case IPV4_FLOW: 27925d317c6aSMerav Sicron case IPV6_FLOW: 27935d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 27945d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 27955d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27965d317c6aSMerav Sicron "Command parameters not supported\n"); 27975d317c6aSMerav Sicron return -EINVAL; 27985d317c6aSMerav Sicron } else { 27995d317c6aSMerav Sicron return 0; 28005d317c6aSMerav Sicron } 28015d317c6aSMerav Sicron case SCTP_V4_FLOW: 28025d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 28035d317c6aSMerav Sicron case AH_V4_FLOW: 28045d317c6aSMerav Sicron case ESP_V4_FLOW: 28055d317c6aSMerav Sicron case SCTP_V6_FLOW: 28065d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 28075d317c6aSMerav Sicron case AH_V6_FLOW: 28085d317c6aSMerav Sicron case ESP_V6_FLOW: 28095d317c6aSMerav Sicron case IP_USER_FLOW: 28105d317c6aSMerav Sicron case ETHER_FLOW: 28115d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 28125d317c6aSMerav Sicron if (info->data) { 28135d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 28145d317c6aSMerav Sicron "Command parameters not supported\n"); 28155d317c6aSMerav Sicron return -EINVAL; 28165d317c6aSMerav Sicron } else { 28175d317c6aSMerav Sicron return 0; 28185d317c6aSMerav Sicron } 28195d317c6aSMerav Sicron default: 28205d317c6aSMerav Sicron return -EINVAL; 28215d317c6aSMerav Sicron } 28225d317c6aSMerav Sicron } 28235d317c6aSMerav Sicron 28245d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 28255d317c6aSMerav Sicron { 28265d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 28275d317c6aSMerav Sicron 28285d317c6aSMerav Sicron switch (info->cmd) { 28295d317c6aSMerav Sicron case ETHTOOL_SRXFH: 28305d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 2831adfc5217SJeff Kirsher default: 283251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2833adfc5217SJeff Kirsher return -EOPNOTSUPP; 2834adfc5217SJeff Kirsher } 2835adfc5217SJeff Kirsher } 2836adfc5217SJeff Kirsher 28377850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 2838adfc5217SJeff Kirsher { 283996305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 28407850f63fSBen Hutchings } 28417850f63fSBen Hutchings 28427850f63fSBen Hutchings static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 28437850f63fSBen Hutchings { 28447850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 2845adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2846adfc5217SJeff Kirsher size_t i; 2847adfc5217SJeff Kirsher 2848adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 2849adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 2850adfc5217SJeff Kirsher 2851adfc5217SJeff Kirsher /* 2852adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 2853adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 2854adfc5217SJeff Kirsher * points to an array of u32. 2855adfc5217SJeff Kirsher * 2856adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2857adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 2858adfc5217SJeff Kirsher * queue. 2859adfc5217SJeff Kirsher */ 28607850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 28617850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 2862adfc5217SJeff Kirsher 2863adfc5217SJeff Kirsher return 0; 2864adfc5217SJeff Kirsher } 2865adfc5217SJeff Kirsher 28667850f63fSBen Hutchings static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 2867adfc5217SJeff Kirsher { 2868adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2869adfc5217SJeff Kirsher size_t i; 2870adfc5217SJeff Kirsher 2871adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2872adfc5217SJeff Kirsher /* 2873adfc5217SJeff Kirsher * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 2874adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 2875adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 2876adfc5217SJeff Kirsher * 2877adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2878adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 2879adfc5217SJeff Kirsher * queue 2880adfc5217SJeff Kirsher */ 28815d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 2882adfc5217SJeff Kirsher } 2883adfc5217SJeff Kirsher 28845d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 2885adfc5217SJeff Kirsher } 2886adfc5217SJeff Kirsher 28870e8d2ec5SMerav Sicron /** 28880e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 28890e8d2ec5SMerav Sicron * 28900e8d2ec5SMerav Sicron * @dev: net device 28910e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 28920e8d2ec5SMerav Sicron */ 28930e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 28940e8d2ec5SMerav Sicron struct ethtool_channels *channels) 28950e8d2ec5SMerav Sicron { 28960e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 28970e8d2ec5SMerav Sicron 28980e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 28990e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 29000e8d2ec5SMerav Sicron } 29010e8d2ec5SMerav Sicron 29020e8d2ec5SMerav Sicron /** 29030e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 29040e8d2ec5SMerav Sicron * 29050e8d2ec5SMerav Sicron * @bp: bnx2x private structure 29060e8d2ec5SMerav Sicron * 29070e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 29080e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 29090e8d2ec5SMerav Sicron */ 29100e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 29110e8d2ec5SMerav Sicron { 29120e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 291355c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 291455c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 291555c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 29160e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 29170e8d2ec5SMerav Sicron } 29180e8d2ec5SMerav Sicron 29190e8d2ec5SMerav Sicron /** 29200e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 29210e8d2ec5SMerav Sicron * 29220e8d2ec5SMerav Sicron * @dev: net device 29230e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 29240e8d2ec5SMerav Sicron */ 29250e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 29260e8d2ec5SMerav Sicron struct ethtool_channels *channels) 29270e8d2ec5SMerav Sicron { 29280e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 29290e8d2ec5SMerav Sicron 29300e8d2ec5SMerav Sicron 29310e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29320e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 29330e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 29340e8d2ec5SMerav Sicron channels->combined_count); 29350e8d2ec5SMerav Sicron 29360e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 29370e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 29380e8d2ec5SMerav Sicron */ 29390e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 29400e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 29410e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 29420e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 29430e8d2ec5SMerav Sicron return -EINVAL; 29440e8d2ec5SMerav Sicron } 29450e8d2ec5SMerav Sicron 29460e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 29470e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 29480e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 29490e8d2ec5SMerav Sicron return 0; 29500e8d2ec5SMerav Sicron } 29510e8d2ec5SMerav Sicron 29520e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 29530e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 29540e8d2ec5SMerav Sicron * less than requested if memory is low. 29550e8d2ec5SMerav Sicron */ 29560e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 29570e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 29580e8d2ec5SMerav Sicron return 0; 29590e8d2ec5SMerav Sicron } 29605d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 29610e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 29620e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 29630e8d2ec5SMerav Sicron } 29640e8d2ec5SMerav Sicron 2965adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 2966adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 2967adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 2968adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 2969adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 2970adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 2971adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 2972adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 2973adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 2974adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 2975adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 2976adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 2977adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 2978adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 2979adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 2980adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 2981adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 2982adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 2983adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 2984adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 2985adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 2986adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 2987adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 2988adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 2989adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 2990adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 2991adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 29925d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 29937850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 2994adfc5217SJeff Kirsher .get_rxfh_indir = bnx2x_get_rxfh_indir, 2995adfc5217SJeff Kirsher .set_rxfh_indir = bnx2x_set_rxfh_indir, 29960e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 29970e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 299824ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 299924ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3000e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3001e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3002be53ce1eSRichard Cochran .get_ts_info = ethtool_op_get_ts_info, 3003adfc5217SJeff Kirsher }; 3004adfc5217SJeff Kirsher 3005adfc5217SJeff Kirsher void bnx2x_set_ethtool_ops(struct net_device *netdev) 3006adfc5217SJeff Kirsher { 3007adfc5217SJeff Kirsher SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 3008adfc5217SJeff Kirsher } 3009