14ad79e13SYuval Mintz /* bnx2x_ethtool.c: QLogic Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 44ad79e13SYuval Mintz * Copyright (c) 2014 QLogic Corporation 54ad79e13SYuval Mintz * All rights reserved 6adfc5217SJeff Kirsher * 7adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 8adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 9adfc5217SJeff Kirsher * the Free Software Foundation. 10adfc5217SJeff Kirsher * 1108f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12adfc5217SJeff Kirsher * Written by: Eliezer Tamir 13adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 14adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 15adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 16adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19f1deab50SJoe Perches 20f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21f1deab50SJoe Perches 22adfc5217SJeff Kirsher #include <linux/ethtool.h> 23adfc5217SJeff Kirsher #include <linux/netdevice.h> 24adfc5217SJeff Kirsher #include <linux/types.h> 25adfc5217SJeff Kirsher #include <linux/sched.h> 26adfc5217SJeff Kirsher #include <linux/crc32.h> 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_dump.h" 30adfc5217SJeff Kirsher #include "bnx2x_init.h" 31adfc5217SJeff Kirsher 32adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 33adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35adfc5217SJeff Kirsher */ 36adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 37adfc5217SJeff Kirsher static const struct { 38adfc5217SJeff Kirsher long offset; 39adfc5217SJeff Kirsher int size; 40adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 41adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 42adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 49adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 51adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 556a531198SYuval Mintz { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" }, 56adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 65adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 67c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 70adfc5217SJeff Kirsher }; 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73adfc5217SJeff Kirsher 74adfc5217SJeff Kirsher static const struct { 75adfc5217SJeff Kirsher long offset; 76adfc5217SJeff Kirsher int size; 7744c33c66SMichal Schmidt bool is_port_stat; 78adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 79adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 80adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 8144c33c66SMichal Schmidt 8, false, "rx_bytes" }, 82adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 8344c33c66SMichal Schmidt 8, false, "rx_error_bytes" }, 84adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 8544c33c66SMichal Schmidt 8, false, "rx_ucast_packets" }, 86adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 8744c33c66SMichal Schmidt 8, false, "rx_mcast_packets" }, 88adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 8944c33c66SMichal Schmidt 8, false, "rx_bcast_packets" }, 90adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 9144c33c66SMichal Schmidt 8, true, "rx_crc_errors" }, 92adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 9344c33c66SMichal Schmidt 8, true, "rx_align_errors" }, 94adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 9544c33c66SMichal Schmidt 8, true, "rx_undersize_packets" }, 96adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 9744c33c66SMichal Schmidt 8, true, "rx_oversize_packets" }, 98adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 9944c33c66SMichal Schmidt 8, true, "rx_fragments" }, 100adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 10144c33c66SMichal Schmidt 8, true, "rx_jabbers" }, 102adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 10344c33c66SMichal Schmidt 8, false, "rx_discards" }, 104adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 10544c33c66SMichal Schmidt 4, true, "rx_filtered_packets" }, 106adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 10744c33c66SMichal Schmidt 4, true, "rx_mf_tag_discard" }, 1080e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 10944c33c66SMichal Schmidt 8, true, "pfc_frames_received" }, 1100e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 11144c33c66SMichal Schmidt 8, true, "pfc_frames_sent" }, 112adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 11344c33c66SMichal Schmidt 8, true, "rx_brb_discard" }, 114adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 11544c33c66SMichal Schmidt 8, true, "rx_brb_truncate" }, 116adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 11744c33c66SMichal Schmidt 8, true, "rx_pause_frames" }, 118adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 11944c33c66SMichal Schmidt 8, true, "rx_mac_ctrl_frames" }, 120adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 12144c33c66SMichal Schmidt 4, true, "rx_constant_pause_events" }, 122adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 12344c33c66SMichal Schmidt 4, false, "rx_phy_ip_err_discards"}, 124adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 12544c33c66SMichal Schmidt 4, false, "rx_skb_alloc_discard" }, 126adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 12744c33c66SMichal Schmidt 4, false, "rx_csum_offload_errors" }, 1286a531198SYuval Mintz { STATS_OFFSET32(driver_xoff), 12944c33c66SMichal Schmidt 4, false, "tx_exhaustion_events" }, 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 13144c33c66SMichal Schmidt 8, false, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 13344c33c66SMichal Schmidt 8, true, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 13544c33c66SMichal Schmidt 8, false, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 13744c33c66SMichal Schmidt 8, false, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 13944c33c66SMichal Schmidt 8, false, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 14144c33c66SMichal Schmidt 8, true, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 14344c33c66SMichal Schmidt 8, true, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 14544c33c66SMichal Schmidt 8, true, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 14744c33c66SMichal Schmidt 8, true, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 14944c33c66SMichal Schmidt 8, true, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 15144c33c66SMichal Schmidt 8, true, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 15344c33c66SMichal Schmidt 8, true, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 15544c33c66SMichal Schmidt 8, true, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 15744c33c66SMichal Schmidt 8, true, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 15944c33c66SMichal Schmidt 8, true, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 16144c33c66SMichal Schmidt 8, true, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 16344c33c66SMichal Schmidt 8, true, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 16544c33c66SMichal Schmidt 8, true, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 16744c33c66SMichal Schmidt 8, true, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 16944c33c66SMichal Schmidt 8, true, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 17144c33c66SMichal Schmidt 8, true, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 17344c33c66SMichal Schmidt 8, false, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 17544c33c66SMichal Schmidt 8, false, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 17744c33c66SMichal Schmidt 8, false, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 17944c33c66SMichal Schmidt 4, false, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 18144c33c66SMichal Schmidt 4, false, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 18344c33c66SMichal Schmidt 4, false, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 18544c33c66SMichal Schmidt 4, true, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 18907ba6af4SMiriam Shitrit 190adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 191adfc5217SJeff Kirsher { 192adfc5217SJeff Kirsher int port_type; 193adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 195dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 196dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 198adfc5217SJeff Kirsher case ETH_PHY_KR: 199adfc5217SJeff Kirsher case ETH_PHY_CX4: 200adfc5217SJeff Kirsher port_type = PORT_FIBRE; 201adfc5217SJeff Kirsher break; 202adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 203adfc5217SJeff Kirsher port_type = PORT_DA; 204adfc5217SJeff Kirsher break; 205adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 206adfc5217SJeff Kirsher port_type = PORT_TP; 207adfc5217SJeff Kirsher break; 208adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 209adfc5217SJeff Kirsher port_type = PORT_NONE; 210adfc5217SJeff Kirsher break; 211adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 212adfc5217SJeff Kirsher default: 213adfc5217SJeff Kirsher port_type = PORT_OTHER; 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher return port_type; 217adfc5217SJeff Kirsher } 218adfc5217SJeff Kirsher 2198b86b2c1SPhilippe Reynes static int bnx2x_get_vf_link_ksettings(struct net_device *dev, 2208b86b2c1SPhilippe Reynes struct ethtool_link_ksettings *cmd) 2216495d15aSDmitry Kravkov { 2226495d15aSDmitry Kravkov struct bnx2x *bp = netdev_priv(dev); 2238b86b2c1SPhilippe Reynes u32 supported, advertising; 2248b86b2c1SPhilippe Reynes 2258b86b2c1SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&supported, 2268b86b2c1SPhilippe Reynes cmd->link_modes.supported); 2278b86b2c1SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&advertising, 2288b86b2c1SPhilippe Reynes cmd->link_modes.advertising); 2296495d15aSDmitry Kravkov 2306495d15aSDmitry Kravkov if (bp->state == BNX2X_STATE_OPEN) { 2316495d15aSDmitry Kravkov if (test_bit(BNX2X_LINK_REPORT_FD, 2326495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags)) 2338b86b2c1SPhilippe Reynes cmd->base.duplex = DUPLEX_FULL; 2346495d15aSDmitry Kravkov else 2358b86b2c1SPhilippe Reynes cmd->base.duplex = DUPLEX_HALF; 2366495d15aSDmitry Kravkov 2378b86b2c1SPhilippe Reynes cmd->base.speed = bp->vf_link_vars.line_speed; 2386495d15aSDmitry Kravkov } else { 2398b86b2c1SPhilippe Reynes cmd->base.duplex = DUPLEX_UNKNOWN; 2408b86b2c1SPhilippe Reynes cmd->base.speed = SPEED_UNKNOWN; 2416495d15aSDmitry Kravkov } 2426495d15aSDmitry Kravkov 2438b86b2c1SPhilippe Reynes cmd->base.port = PORT_OTHER; 2448b86b2c1SPhilippe Reynes cmd->base.phy_address = 0; 2458b86b2c1SPhilippe Reynes cmd->base.autoneg = AUTONEG_DISABLE; 2466495d15aSDmitry Kravkov 2476495d15aSDmitry Kravkov DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 2486495d15aSDmitry Kravkov " supported 0x%x advertising 0x%x speed %u\n" 2498b86b2c1SPhilippe Reynes " duplex %d port %d phy_address %d\n" 2508b86b2c1SPhilippe Reynes " autoneg %d\n", 2518b86b2c1SPhilippe Reynes cmd->base.cmd, supported, advertising, 2528b86b2c1SPhilippe Reynes cmd->base.speed, 2538b86b2c1SPhilippe Reynes cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 2548b86b2c1SPhilippe Reynes cmd->base.autoneg); 2556495d15aSDmitry Kravkov 2566495d15aSDmitry Kravkov return 0; 2576495d15aSDmitry Kravkov } 2586495d15aSDmitry Kravkov 2598b86b2c1SPhilippe Reynes static int bnx2x_get_link_ksettings(struct net_device *dev, 2608b86b2c1SPhilippe Reynes struct ethtool_link_ksettings *cmd) 261adfc5217SJeff Kirsher { 262adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 263adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2645d67c1c5SYuval Mintz u32 media_type; 2658b86b2c1SPhilippe Reynes u32 supported, advertising, lp_advertising; 2668b86b2c1SPhilippe Reynes 2678b86b2c1SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&lp_advertising, 2688b86b2c1SPhilippe Reynes cmd->link_modes.lp_advertising); 269adfc5217SJeff Kirsher 270adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 2718b86b2c1SPhilippe Reynes supported = bp->port.supported[cfg_idx] | 272adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 273adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 2748b86b2c1SPhilippe Reynes advertising = bp->port.advertising[cfg_idx]; 2755d67c1c5SYuval Mintz media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 2765d67c1c5SYuval Mintz if (media_type == ETH_PHY_SFP_1G_FIBER) { 2778b86b2c1SPhilippe Reynes supported &= ~(SUPPORTED_10000baseT_Full); 2788b86b2c1SPhilippe Reynes advertising &= ~(ADVERTISED_10000baseT_Full); 279dbef807eSYuval Mintz } 280adfc5217SJeff Kirsher 28159694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 28259694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 2838b86b2c1SPhilippe Reynes cmd->base.duplex = bp->link_vars.duplex; 284adfc5217SJeff Kirsher 28538298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 2868b86b2c1SPhilippe Reynes cmd->base.speed = bnx2x_get_mf_speed(bp); 28759694f00SYuval Mintz else 2888b86b2c1SPhilippe Reynes cmd->base.speed = bp->link_vars.line_speed; 28938298461SYuval Mintz } else { 2908b86b2c1SPhilippe Reynes cmd->base.duplex = DUPLEX_UNKNOWN; 2918b86b2c1SPhilippe Reynes cmd->base.speed = SPEED_UNKNOWN; 29238298461SYuval Mintz } 293adfc5217SJeff Kirsher 2948b86b2c1SPhilippe Reynes cmd->base.port = bnx2x_get_port_type(bp); 295adfc5217SJeff Kirsher 2968b86b2c1SPhilippe Reynes cmd->base.phy_address = bp->mdio.prtad; 297adfc5217SJeff Kirsher 298adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 2998b86b2c1SPhilippe Reynes cmd->base.autoneg = AUTONEG_ENABLE; 300adfc5217SJeff Kirsher else 3018b86b2c1SPhilippe Reynes cmd->base.autoneg = AUTONEG_DISABLE; 302adfc5217SJeff Kirsher 3039e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 3049e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3059e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 3069e7e8399SMintz Yuval 3078b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_Autoneg; 3089e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 3098b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_Pause; 3109e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 3118b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_Asym_Pause; 3129e7e8399SMintz Yuval 3139e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 3148b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_10baseT_Half; 3159e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 3168b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_10baseT_Full; 3179e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 3188b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_100baseT_Half; 3199e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 3208b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_100baseT_Full; 3219e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 3228b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_1000baseT_Half; 3235d67c1c5SYuval Mintz if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 3245d67c1c5SYuval Mintz if (media_type == ETH_PHY_KR) { 3258b86b2c1SPhilippe Reynes lp_advertising |= 3265d67c1c5SYuval Mintz ADVERTISED_1000baseKX_Full; 3275d67c1c5SYuval Mintz } else { 3288b86b2c1SPhilippe Reynes lp_advertising |= 3295d67c1c5SYuval Mintz ADVERTISED_1000baseT_Full; 3305d67c1c5SYuval Mintz } 3315d67c1c5SYuval Mintz } 3329e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 3338b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_2500baseX_Full; 3345d67c1c5SYuval Mintz if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 3355d67c1c5SYuval Mintz if (media_type == ETH_PHY_KR) { 3368b86b2c1SPhilippe Reynes lp_advertising |= 3375d67c1c5SYuval Mintz ADVERTISED_10000baseKR_Full; 3385d67c1c5SYuval Mintz } else { 3398b86b2c1SPhilippe Reynes lp_advertising |= 3405d67c1c5SYuval Mintz ADVERTISED_10000baseT_Full; 3415d67c1c5SYuval Mintz } 3425d67c1c5SYuval Mintz } 343be94bea7SYaniv Rosner if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 3448b86b2c1SPhilippe Reynes lp_advertising |= ADVERTISED_20000baseKR2_Full; 3459e7e8399SMintz Yuval } 3469e7e8399SMintz Yuval 3478b86b2c1SPhilippe Reynes ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3488b86b2c1SPhilippe Reynes supported); 3498b86b2c1SPhilippe Reynes ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3508b86b2c1SPhilippe Reynes advertising); 3518b86b2c1SPhilippe Reynes ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3528b86b2c1SPhilippe Reynes lp_advertising); 353adfc5217SJeff Kirsher 35451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 355f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 3568b86b2c1SPhilippe Reynes " duplex %d port %d phy_address %d\n" 3578b86b2c1SPhilippe Reynes " autoneg %d\n", 3588b86b2c1SPhilippe Reynes cmd->base.cmd, supported, advertising, 3598b86b2c1SPhilippe Reynes cmd->base.speed, 3608b86b2c1SPhilippe Reynes cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 3618b86b2c1SPhilippe Reynes cmd->base.autoneg); 362adfc5217SJeff Kirsher 363adfc5217SJeff Kirsher return 0; 364adfc5217SJeff Kirsher } 365adfc5217SJeff Kirsher 3668b86b2c1SPhilippe Reynes static int bnx2x_set_link_ksettings(struct net_device *dev, 3678b86b2c1SPhilippe Reynes const struct ethtool_link_ksettings *cmd) 368adfc5217SJeff Kirsher { 369adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 370adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 371dbef807eSYuval Mintz u32 speed, phy_idx; 3728b86b2c1SPhilippe Reynes u32 supported; 3738b86b2c1SPhilippe Reynes u8 duplex = cmd->base.duplex; 3748b86b2c1SPhilippe Reynes 3758b86b2c1SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&supported, 3768b86b2c1SPhilippe Reynes cmd->link_modes.supported); 3778b86b2c1SPhilippe Reynes ethtool_convert_link_mode_to_legacy_u32(&advertising, 3788b86b2c1SPhilippe Reynes cmd->link_modes.advertising); 379adfc5217SJeff Kirsher 380adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 381adfc5217SJeff Kirsher return 0; 382adfc5217SJeff Kirsher 38351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 384adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 3858b86b2c1SPhilippe Reynes " duplex %d port %d phy_address %d\n" 3868b86b2c1SPhilippe Reynes " autoneg %d\n", 3878b86b2c1SPhilippe Reynes cmd->base.cmd, supported, advertising, 3888b86b2c1SPhilippe Reynes cmd->base.speed, 3898b86b2c1SPhilippe Reynes cmd->base.duplex, cmd->base.port, cmd->base.phy_address, 3908b86b2c1SPhilippe Reynes cmd->base.autoneg); 391adfc5217SJeff Kirsher 3928b86b2c1SPhilippe Reynes speed = cmd->base.speed; 393adfc5217SJeff Kirsher 39416a5fd92SYuval Mintz /* If received a request for an unknown duplex, assume full*/ 3958b86b2c1SPhilippe Reynes if (duplex == DUPLEX_UNKNOWN) 3968b86b2c1SPhilippe Reynes duplex = DUPLEX_FULL; 39738298461SYuval Mintz 398adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 399adfc5217SJeff Kirsher u32 part; 400adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 401adfc5217SJeff Kirsher 402adfc5217SJeff Kirsher /* use 10G if no link detected */ 403adfc5217SJeff Kirsher if (!line_speed) 404adfc5217SJeff Kirsher line_speed = 10000; 405adfc5217SJeff Kirsher 406adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 40751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 40851c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 409adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 410adfc5217SJeff Kirsher return -EINVAL; 411adfc5217SJeff Kirsher } 412adfc5217SJeff Kirsher 413adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 414adfc5217SJeff Kirsher 415adfc5217SJeff Kirsher if (line_speed < speed || !part) { 41651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 41751c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 418adfc5217SJeff Kirsher return -EINVAL; 419adfc5217SJeff Kirsher } 420adfc5217SJeff Kirsher 421adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 422adfc5217SJeff Kirsher /* store value for following "load" */ 423adfc5217SJeff Kirsher bp->pending_max = part; 424adfc5217SJeff Kirsher else 425adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 426adfc5217SJeff Kirsher 427adfc5217SJeff Kirsher return 0; 428adfc5217SJeff Kirsher } 429adfc5217SJeff Kirsher 430adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 431adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 4328b86b2c1SPhilippe Reynes if (cmd->base.port != bnx2x_get_port_type(bp)) { 4338b86b2c1SPhilippe Reynes switch (cmd->base.port) { 434adfc5217SJeff Kirsher case PORT_TP: 435adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 436adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 43733f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 43833f9e6f5SYaniv Rosner "Unsupported port type\n"); 439adfc5217SJeff Kirsher return -EINVAL; 440adfc5217SJeff Kirsher } 441adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 442adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 443adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 444adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 445adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 446adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 447adfc5217SJeff Kirsher else 448adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 449adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 450adfc5217SJeff Kirsher break; 451adfc5217SJeff Kirsher case PORT_FIBRE: 452bfdb5823SYaniv Rosner case PORT_DA: 453042d7654SYaniv Rosner case PORT_NONE: 454adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 455adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 45633f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 45733f9e6f5SYaniv Rosner "Unsupported port type\n"); 458adfc5217SJeff Kirsher return -EINVAL; 459adfc5217SJeff Kirsher } 460adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 461adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 462adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 463adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 464adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 465adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 466adfc5217SJeff Kirsher else 467adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 468adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 469adfc5217SJeff Kirsher break; 470adfc5217SJeff Kirsher default: 47151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 472adfc5217SJeff Kirsher return -EINVAL; 473adfc5217SJeff Kirsher } 47433f9e6f5SYaniv Rosner } 4752de67439SYuval Mintz /* Save new config in case command complete successfully */ 476adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 477adfc5217SJeff Kirsher /* Get the new cfg_idx */ 478adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 479adfc5217SJeff Kirsher /* Restore old config in case command failed */ 480adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 48151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 482adfc5217SJeff Kirsher 4838b86b2c1SPhilippe Reynes if (cmd->base.autoneg == AUTONEG_ENABLE) { 48475318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 48575318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 48675318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 48775318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 48875318327SYaniv Rosner SUPPORTED_100baseT_Full); 489adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 49051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 491adfc5217SJeff Kirsher return -EINVAL; 492adfc5217SJeff Kirsher } 493adfc5217SJeff Kirsher 494adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 4958b86b2c1SPhilippe Reynes if (advertising & ~an_supported_speed) { 49651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 49751c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4988decf868SDavid S. Miller return -EINVAL; 4998decf868SDavid S. Miller } 500adfc5217SJeff Kirsher 501adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 5028b86b2c1SPhilippe Reynes bp->link_params.req_duplex[cfg_idx] = duplex; 5038decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 5048b86b2c1SPhilippe Reynes advertising); 5058b86b2c1SPhilippe Reynes if (advertising) { 506adfc5217SJeff Kirsher 5078decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 5088b86b2c1SPhilippe Reynes if (advertising & ADVERTISED_10baseT_Half) { 5098decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5108decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 5118decf868SDavid S. Miller } 5128b86b2c1SPhilippe Reynes if (advertising & ADVERTISED_10baseT_Full) 5138decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5148decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 5158decf868SDavid S. Miller 5168b86b2c1SPhilippe Reynes if (advertising & ADVERTISED_100baseT_Full) 5178decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5188decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 5198decf868SDavid S. Miller 5208b86b2c1SPhilippe Reynes if (advertising & ADVERTISED_100baseT_Half) { 5218decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5228decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 5238decf868SDavid S. Miller } 5248b86b2c1SPhilippe Reynes if (advertising & ADVERTISED_1000baseT_Half) { 5258decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5268decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 5278decf868SDavid S. Miller } 5288b86b2c1SPhilippe Reynes if (advertising & (ADVERTISED_1000baseT_Full | 5298decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 5308decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5318decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 5328decf868SDavid S. Miller 5338b86b2c1SPhilippe Reynes if (advertising & (ADVERTISED_10000baseT_Full | 5348decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 5358decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 5368decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5378decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 538be94bea7SYaniv Rosner 5398b86b2c1SPhilippe Reynes if (advertising & ADVERTISED_20000baseKR2_Full) 540be94bea7SYaniv Rosner bp->link_params.speed_cap_mask[cfg_idx] |= 541be94bea7SYaniv Rosner PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 5428decf868SDavid S. Miller } 543adfc5217SJeff Kirsher } else { /* forced speed */ 544adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 545adfc5217SJeff Kirsher switch (speed) { 546adfc5217SJeff Kirsher case SPEED_10: 5478b86b2c1SPhilippe Reynes if (duplex == DUPLEX_FULL) { 548adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 549adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 55051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 551adfc5217SJeff Kirsher "10M full not supported\n"); 552adfc5217SJeff Kirsher return -EINVAL; 553adfc5217SJeff Kirsher } 554adfc5217SJeff Kirsher 555adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 556adfc5217SJeff Kirsher ADVERTISED_TP); 557adfc5217SJeff Kirsher } else { 558adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 559adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 56051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 561adfc5217SJeff Kirsher "10M half not supported\n"); 562adfc5217SJeff Kirsher return -EINVAL; 563adfc5217SJeff Kirsher } 564adfc5217SJeff Kirsher 565adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 566adfc5217SJeff Kirsher ADVERTISED_TP); 567adfc5217SJeff Kirsher } 568adfc5217SJeff Kirsher break; 569adfc5217SJeff Kirsher 570adfc5217SJeff Kirsher case SPEED_100: 5718b86b2c1SPhilippe Reynes if (duplex == DUPLEX_FULL) { 572adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 573adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 57451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 575adfc5217SJeff Kirsher "100M full not supported\n"); 576adfc5217SJeff Kirsher return -EINVAL; 577adfc5217SJeff Kirsher } 578adfc5217SJeff Kirsher 579adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 580adfc5217SJeff Kirsher ADVERTISED_TP); 581adfc5217SJeff Kirsher } else { 582adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 583adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 58451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 585adfc5217SJeff Kirsher "100M half not supported\n"); 586adfc5217SJeff Kirsher return -EINVAL; 587adfc5217SJeff Kirsher } 588adfc5217SJeff Kirsher 589adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 590adfc5217SJeff Kirsher ADVERTISED_TP); 591adfc5217SJeff Kirsher } 592adfc5217SJeff Kirsher break; 593adfc5217SJeff Kirsher 594adfc5217SJeff Kirsher case SPEED_1000: 5958b86b2c1SPhilippe Reynes if (duplex != DUPLEX_FULL) { 59651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 59751c1a580SMerav Sicron "1G half not supported\n"); 598adfc5217SJeff Kirsher return -EINVAL; 599adfc5217SJeff Kirsher } 600adfc5217SJeff Kirsher 6015d67c1c5SYuval Mintz if (bp->port.supported[cfg_idx] & 6025d67c1c5SYuval Mintz SUPPORTED_1000baseT_Full) { 6035d67c1c5SYuval Mintz advertising = (ADVERTISED_1000baseT_Full | 6045d67c1c5SYuval Mintz ADVERTISED_TP); 6055d67c1c5SYuval Mintz 6065d67c1c5SYuval Mintz } else if (bp->port.supported[cfg_idx] & 6075d67c1c5SYuval Mintz SUPPORTED_1000baseKX_Full) { 6085d67c1c5SYuval Mintz advertising = ADVERTISED_1000baseKX_Full; 6095d67c1c5SYuval Mintz } else { 61051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 61151c1a580SMerav Sicron "1G full not supported\n"); 612adfc5217SJeff Kirsher return -EINVAL; 613adfc5217SJeff Kirsher } 614adfc5217SJeff Kirsher 615adfc5217SJeff Kirsher break; 616adfc5217SJeff Kirsher 617adfc5217SJeff Kirsher case SPEED_2500: 6188b86b2c1SPhilippe Reynes if (duplex != DUPLEX_FULL) { 61951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 620adfc5217SJeff Kirsher "2.5G half not supported\n"); 621adfc5217SJeff Kirsher return -EINVAL; 622adfc5217SJeff Kirsher } 623adfc5217SJeff Kirsher 624adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 625adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 62651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 627adfc5217SJeff Kirsher "2.5G full not supported\n"); 628adfc5217SJeff Kirsher return -EINVAL; 629adfc5217SJeff Kirsher } 630adfc5217SJeff Kirsher 631adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 632adfc5217SJeff Kirsher ADVERTISED_TP); 633adfc5217SJeff Kirsher break; 634adfc5217SJeff Kirsher 635adfc5217SJeff Kirsher case SPEED_10000: 6368b86b2c1SPhilippe Reynes if (duplex != DUPLEX_FULL) { 63751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 63851c1a580SMerav Sicron "10G half not supported\n"); 639adfc5217SJeff Kirsher return -EINVAL; 640adfc5217SJeff Kirsher } 641dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 6425d67c1c5SYuval Mintz if ((bp->port.supported[cfg_idx] & 6435d67c1c5SYuval Mintz SUPPORTED_10000baseT_Full) && 6445d67c1c5SYuval Mintz (bp->link_params.phy[phy_idx].media_type != 645dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 6465d67c1c5SYuval Mintz advertising = (ADVERTISED_10000baseT_Full | 6475d67c1c5SYuval Mintz ADVERTISED_FIBRE); 6485d67c1c5SYuval Mintz } else if (bp->port.supported[cfg_idx] & 6495d67c1c5SYuval Mintz SUPPORTED_10000baseKR_Full) { 6505d67c1c5SYuval Mintz advertising = (ADVERTISED_10000baseKR_Full | 6515d67c1c5SYuval Mintz ADVERTISED_FIBRE); 6525d67c1c5SYuval Mintz } else { 65351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 65451c1a580SMerav Sicron "10G full not supported\n"); 655adfc5217SJeff Kirsher return -EINVAL; 656adfc5217SJeff Kirsher } 657adfc5217SJeff Kirsher 658adfc5217SJeff Kirsher break; 659adfc5217SJeff Kirsher 660adfc5217SJeff Kirsher default: 66151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 662adfc5217SJeff Kirsher return -EINVAL; 663adfc5217SJeff Kirsher } 664adfc5217SJeff Kirsher 665adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 6668b86b2c1SPhilippe Reynes bp->link_params.req_duplex[cfg_idx] = duplex; 667adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 668adfc5217SJeff Kirsher } 669adfc5217SJeff Kirsher 67051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 671f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 672adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 673adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 674adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 675adfc5217SJeff Kirsher 676adfc5217SJeff Kirsher /* Set new config */ 677adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 678adfc5217SJeff Kirsher if (netif_running(dev)) { 679adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 680dc6a20aaSAriel Elior bnx2x_force_link_reset(bp); 681adfc5217SJeff Kirsher bnx2x_link_set(bp); 682adfc5217SJeff Kirsher } 683adfc5217SJeff Kirsher 684adfc5217SJeff Kirsher return 0; 685adfc5217SJeff Kirsher } 686adfc5217SJeff Kirsher 68707ba6af4SMiriam Shitrit #define DUMP_ALL_PRESETS 0x1FFF 68807ba6af4SMiriam Shitrit #define DUMP_MAX_PRESETS 13 689adfc5217SJeff Kirsher 69007ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 691adfc5217SJeff Kirsher { 692adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 69307ba6af4SMiriam Shitrit return dump_num_registers[0][preset-1]; 694adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 69507ba6af4SMiriam Shitrit return dump_num_registers[1][preset-1]; 696adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 69707ba6af4SMiriam Shitrit return dump_num_registers[2][preset-1]; 698adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 69907ba6af4SMiriam Shitrit return dump_num_registers[3][preset-1]; 700adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 70107ba6af4SMiriam Shitrit return dump_num_registers[4][preset-1]; 702adfc5217SJeff Kirsher else 70307ba6af4SMiriam Shitrit return 0; 704adfc5217SJeff Kirsher } 705adfc5217SJeff Kirsher 70607ba6af4SMiriam Shitrit static int __bnx2x_get_regs_len(struct bnx2x *bp) 70707ba6af4SMiriam Shitrit { 70807ba6af4SMiriam Shitrit u32 preset_idx; 70907ba6af4SMiriam Shitrit int regdump_len = 0; 71007ba6af4SMiriam Shitrit 71107ba6af4SMiriam Shitrit /* Calculate the total preset regs length */ 71207ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 71307ba6af4SMiriam Shitrit regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 71407ba6af4SMiriam Shitrit 71507ba6af4SMiriam Shitrit return regdump_len; 71607ba6af4SMiriam Shitrit } 71707ba6af4SMiriam Shitrit 71807ba6af4SMiriam Shitrit static int bnx2x_get_regs_len(struct net_device *dev) 71907ba6af4SMiriam Shitrit { 72007ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 72107ba6af4SMiriam Shitrit int regdump_len = 0; 72207ba6af4SMiriam Shitrit 72375543741SYuval Mintz if (IS_VF(bp)) 72475543741SYuval Mintz return 0; 72575543741SYuval Mintz 72607ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_regs_len(bp); 72707ba6af4SMiriam Shitrit regdump_len *= 4; 72807ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 72907ba6af4SMiriam Shitrit 73007ba6af4SMiriam Shitrit return regdump_len; 73107ba6af4SMiriam Shitrit } 73207ba6af4SMiriam Shitrit 73307ba6af4SMiriam Shitrit #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 73407ba6af4SMiriam Shitrit #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 73507ba6af4SMiriam Shitrit #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 73607ba6af4SMiriam Shitrit #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 73707ba6af4SMiriam Shitrit #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 73807ba6af4SMiriam Shitrit 73907ba6af4SMiriam Shitrit #define IS_REG_IN_PRESET(presets, idx) \ 74007ba6af4SMiriam Shitrit ((presets & (1 << (idx-1))) == (1 << (idx-1))) 74107ba6af4SMiriam Shitrit 742adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 7431191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 744adfc5217SJeff Kirsher { 745adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 746adfc5217SJeff Kirsher return page_vals_e2; 747adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 748adfc5217SJeff Kirsher return page_vals_e3; 749adfc5217SJeff Kirsher else 750adfc5217SJeff Kirsher return NULL; 751adfc5217SJeff Kirsher } 752adfc5217SJeff Kirsher 7531191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 754adfc5217SJeff Kirsher { 755adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 756adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 757adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 758adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 759adfc5217SJeff Kirsher else 760adfc5217SJeff Kirsher return 0; 761adfc5217SJeff Kirsher } 762adfc5217SJeff Kirsher 7631191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 764adfc5217SJeff Kirsher { 765adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 766adfc5217SJeff Kirsher return page_write_regs_e2; 767adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 768adfc5217SJeff Kirsher return page_write_regs_e3; 769adfc5217SJeff Kirsher else 770adfc5217SJeff Kirsher return NULL; 771adfc5217SJeff Kirsher } 772adfc5217SJeff Kirsher 7731191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 774adfc5217SJeff Kirsher { 775adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 776adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 777adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 778adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 779adfc5217SJeff Kirsher else 780adfc5217SJeff Kirsher return 0; 781adfc5217SJeff Kirsher } 782adfc5217SJeff Kirsher 7831191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 784adfc5217SJeff Kirsher { 785adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 786adfc5217SJeff Kirsher return page_read_regs_e2; 787adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 788adfc5217SJeff Kirsher return page_read_regs_e3; 789adfc5217SJeff Kirsher else 790adfc5217SJeff Kirsher return NULL; 791adfc5217SJeff Kirsher } 792adfc5217SJeff Kirsher 7931191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 794adfc5217SJeff Kirsher { 795adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 796adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 797adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 798adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 799adfc5217SJeff Kirsher else 800adfc5217SJeff Kirsher return 0; 801adfc5217SJeff Kirsher } 802adfc5217SJeff Kirsher 80307ba6af4SMiriam Shitrit static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 80407ba6af4SMiriam Shitrit const struct reg_addr *reg_info) 805adfc5217SJeff Kirsher { 80607ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 80707ba6af4SMiriam Shitrit return IS_E1_REG(reg_info->chips); 80807ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 80907ba6af4SMiriam Shitrit return IS_E1H_REG(reg_info->chips); 81007ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 81107ba6af4SMiriam Shitrit return IS_E2_REG(reg_info->chips); 81207ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 81307ba6af4SMiriam Shitrit return IS_E3A0_REG(reg_info->chips); 81407ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 81507ba6af4SMiriam Shitrit return IS_E3B0_REG(reg_info->chips); 81607ba6af4SMiriam Shitrit else 81707ba6af4SMiriam Shitrit return false; 818adfc5217SJeff Kirsher } 819adfc5217SJeff Kirsher 82007ba6af4SMiriam Shitrit static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 82107ba6af4SMiriam Shitrit const struct wreg_addr *wreg_info) 822adfc5217SJeff Kirsher { 82307ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 82407ba6af4SMiriam Shitrit return IS_E1_REG(wreg_info->chips); 82507ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 82607ba6af4SMiriam Shitrit return IS_E1H_REG(wreg_info->chips); 82707ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 82807ba6af4SMiriam Shitrit return IS_E2_REG(wreg_info->chips); 82907ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 83007ba6af4SMiriam Shitrit return IS_E3A0_REG(wreg_info->chips); 83107ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 83207ba6af4SMiriam Shitrit return IS_E3B0_REG(wreg_info->chips); 83307ba6af4SMiriam Shitrit else 83407ba6af4SMiriam Shitrit return false; 835adfc5217SJeff Kirsher } 836adfc5217SJeff Kirsher 837adfc5217SJeff Kirsher /** 838adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 839adfc5217SJeff Kirsher * 840adfc5217SJeff Kirsher * @bp device handle 841adfc5217SJeff Kirsher * @p output buffer 842adfc5217SJeff Kirsher * 8432de67439SYuval Mintz * Reads "paged" memories: memories that may only be read by first writing to a 8442de67439SYuval Mintz * specific address ("write address") and then reading from a specific address 8452de67439SYuval Mintz * ("read address"). There may be more than one write address per "page" and 8462de67439SYuval Mintz * more than one read address per write address. 847adfc5217SJeff Kirsher */ 84807ba6af4SMiriam Shitrit static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 849adfc5217SJeff Kirsher { 850adfc5217SJeff Kirsher u32 i, j, k, n; 85107ba6af4SMiriam Shitrit 852adfc5217SJeff Kirsher /* addresses of the paged registers */ 853adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 854adfc5217SJeff Kirsher /* number of paged registers */ 855adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 856adfc5217SJeff Kirsher /* write addresses */ 857adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 858adfc5217SJeff Kirsher /* number of write addresses */ 859adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 860adfc5217SJeff Kirsher /* read addresses info */ 861adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 862adfc5217SJeff Kirsher /* number of read addresses */ 863adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 86407ba6af4SMiriam Shitrit u32 addr, size; 865adfc5217SJeff Kirsher 866adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 867adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 868adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 86907ba6af4SMiriam Shitrit 87007ba6af4SMiriam Shitrit for (k = 0; k < read_num; k++) { 87107ba6af4SMiriam Shitrit if (IS_REG_IN_PRESET(read_addr[k].presets, 87207ba6af4SMiriam Shitrit preset)) { 87307ba6af4SMiriam Shitrit size = read_addr[k].size; 87407ba6af4SMiriam Shitrit for (n = 0; n < size; n++) { 87507ba6af4SMiriam Shitrit addr = read_addr[k].addr + n*4; 87607ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr); 877adfc5217SJeff Kirsher } 878adfc5217SJeff Kirsher } 879adfc5217SJeff Kirsher } 88007ba6af4SMiriam Shitrit } 88107ba6af4SMiriam Shitrit } 88207ba6af4SMiriam Shitrit } 88307ba6af4SMiriam Shitrit 88407ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 88507ba6af4SMiriam Shitrit { 88607ba6af4SMiriam Shitrit u32 i, j, addr; 88707ba6af4SMiriam Shitrit const struct wreg_addr *wreg_addr_p = NULL; 88807ba6af4SMiriam Shitrit 88907ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 89007ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1; 89107ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 89207ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1h; 89307ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 89407ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e2; 89507ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 89607ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3; 89707ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 89807ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3b0; 89907ba6af4SMiriam Shitrit 90007ba6af4SMiriam Shitrit /* Read the idle_chk registers */ 90107ba6af4SMiriam Shitrit for (i = 0; i < IDLE_REGS_COUNT; i++) { 90207ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 90307ba6af4SMiriam Shitrit IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 90407ba6af4SMiriam Shitrit for (j = 0; j < idle_reg_addrs[i].size; j++) 90507ba6af4SMiriam Shitrit *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 90607ba6af4SMiriam Shitrit } 90707ba6af4SMiriam Shitrit } 90807ba6af4SMiriam Shitrit 90907ba6af4SMiriam Shitrit /* Read the regular registers */ 91007ba6af4SMiriam Shitrit for (i = 0; i < REGS_COUNT; i++) { 91107ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 91207ba6af4SMiriam Shitrit IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 91307ba6af4SMiriam Shitrit for (j = 0; j < reg_addrs[i].size; j++) 91407ba6af4SMiriam Shitrit *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 91507ba6af4SMiriam Shitrit } 91607ba6af4SMiriam Shitrit } 91707ba6af4SMiriam Shitrit 91807ba6af4SMiriam Shitrit /* Read the CAM registers */ 91907ba6af4SMiriam Shitrit if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 92007ba6af4SMiriam Shitrit IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 92107ba6af4SMiriam Shitrit for (i = 0; i < wreg_addr_p->size; i++) { 92207ba6af4SMiriam Shitrit *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 92307ba6af4SMiriam Shitrit 92407ba6af4SMiriam Shitrit /* In case of wreg_addr register, read additional 92507ba6af4SMiriam Shitrit registers from read_regs array 92607ba6af4SMiriam Shitrit */ 92707ba6af4SMiriam Shitrit for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 92807ba6af4SMiriam Shitrit addr = *(wreg_addr_p->read_regs); 92907ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr + j*4); 93007ba6af4SMiriam Shitrit } 93107ba6af4SMiriam Shitrit } 93207ba6af4SMiriam Shitrit } 93307ba6af4SMiriam Shitrit 93407ba6af4SMiriam Shitrit /* Paged registers are supported in E2 & E3 only */ 93507ba6af4SMiriam Shitrit if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 93616a5fd92SYuval Mintz /* Read "paged" registers */ 93707ba6af4SMiriam Shitrit bnx2x_read_pages_regs(bp, p, preset); 93807ba6af4SMiriam Shitrit } 93907ba6af4SMiriam Shitrit 94007ba6af4SMiriam Shitrit return 0; 94107ba6af4SMiriam Shitrit } 942adfc5217SJeff Kirsher 9431191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 944adfc5217SJeff Kirsher { 94507ba6af4SMiriam Shitrit u32 preset_idx; 946adfc5217SJeff Kirsher 94707ba6af4SMiriam Shitrit /* Read all registers, by reading all preset registers */ 94807ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 94907ba6af4SMiriam Shitrit /* Skip presets with IOR */ 95007ba6af4SMiriam Shitrit if ((preset_idx == 2) || 95107ba6af4SMiriam Shitrit (preset_idx == 5) || 95207ba6af4SMiriam Shitrit (preset_idx == 8) || 95307ba6af4SMiriam Shitrit (preset_idx == 11)) 95407ba6af4SMiriam Shitrit continue; 95507ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, preset_idx); 95607ba6af4SMiriam Shitrit p += __bnx2x_get_preset_regs_len(bp, preset_idx); 95707ba6af4SMiriam Shitrit } 958adfc5217SJeff Kirsher } 959adfc5217SJeff Kirsher 960adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 961adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 962adfc5217SJeff Kirsher { 963adfc5217SJeff Kirsher u32 *p = _p; 964adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 96507ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 966adfc5217SJeff Kirsher 96707ba6af4SMiriam Shitrit regs->version = 2; 968adfc5217SJeff Kirsher memset(p, 0, regs->len); 969adfc5217SJeff Kirsher 970adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 971adfc5217SJeff Kirsher return; 972adfc5217SJeff Kirsher 973adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 974adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 975adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 976adfc5217SJeff Kirsher */ 97707ba6af4SMiriam Shitrit 978adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 979adfc5217SJeff Kirsher 98007ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 98107ba6af4SMiriam Shitrit dump_hdr.preset = DUMP_ALL_PRESETS; 98207ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 98307ba6af4SMiriam Shitrit 98407ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 98507ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 98607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 98707ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 98807ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 98907ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 99007ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 99107ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 99207ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 99307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 99407ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 99507ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 99607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 99707ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 99807ba6af4SMiriam Shitrit } 99907ba6af4SMiriam Shitrit 100007ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 100107ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 1002adfc5217SJeff Kirsher 1003e56270f6SYuval Mintz /* This isn't really an error, but since attention handling is going 1004e56270f6SYuval Mintz * to print the GRC timeouts using this macro, we use the same. 1005e56270f6SYuval Mintz */ 1006e56270f6SYuval Mintz BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n"); 1007e56270f6SYuval Mintz 1008adfc5217SJeff Kirsher /* Actually read the registers */ 1009adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 1010adfc5217SJeff Kirsher 10114293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 1012adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 1013adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 101407ba6af4SMiriam Shitrit } 101507ba6af4SMiriam Shitrit 101607ba6af4SMiriam Shitrit static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 101707ba6af4SMiriam Shitrit { 101807ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 101907ba6af4SMiriam Shitrit int regdump_len = 0; 102007ba6af4SMiriam Shitrit 102107ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 102207ba6af4SMiriam Shitrit regdump_len *= 4; 102307ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 102407ba6af4SMiriam Shitrit 102507ba6af4SMiriam Shitrit return regdump_len; 102607ba6af4SMiriam Shitrit } 102707ba6af4SMiriam Shitrit 102807ba6af4SMiriam Shitrit static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 102907ba6af4SMiriam Shitrit { 103007ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 103107ba6af4SMiriam Shitrit 103207ba6af4SMiriam Shitrit /* Use the ethtool_dump "flag" field as the dump preset index */ 10335bb680d6SMichal Schmidt if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 10345bb680d6SMichal Schmidt return -EINVAL; 10355bb680d6SMichal Schmidt 103607ba6af4SMiriam Shitrit bp->dump_preset_idx = val->flag; 103707ba6af4SMiriam Shitrit return 0; 103807ba6af4SMiriam Shitrit } 103907ba6af4SMiriam Shitrit 104007ba6af4SMiriam Shitrit static int bnx2x_get_dump_flag(struct net_device *dev, 104107ba6af4SMiriam Shitrit struct ethtool_dump *dump) 104207ba6af4SMiriam Shitrit { 104307ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 104407ba6af4SMiriam Shitrit 10458cc2d927SMichal Schmidt dump->version = BNX2X_DUMP_VERSION; 10468cc2d927SMichal Schmidt dump->flag = bp->dump_preset_idx; 104707ba6af4SMiriam Shitrit /* Calculate the requested preset idx length */ 104807ba6af4SMiriam Shitrit dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 104907ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 105007ba6af4SMiriam Shitrit bp->dump_preset_idx, dump->len); 105107ba6af4SMiriam Shitrit return 0; 105207ba6af4SMiriam Shitrit } 105307ba6af4SMiriam Shitrit 105407ba6af4SMiriam Shitrit static int bnx2x_get_dump_data(struct net_device *dev, 105507ba6af4SMiriam Shitrit struct ethtool_dump *dump, 105607ba6af4SMiriam Shitrit void *buffer) 105707ba6af4SMiriam Shitrit { 105807ba6af4SMiriam Shitrit u32 *p = buffer; 105907ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 106007ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 106107ba6af4SMiriam Shitrit 106207ba6af4SMiriam Shitrit /* Disable parity attentions as long as following dump may 106307ba6af4SMiriam Shitrit * cause false alarms by reading never written registers. We 106407ba6af4SMiriam Shitrit * will re-enable parity attentions right after the dump. 106507ba6af4SMiriam Shitrit */ 106607ba6af4SMiriam Shitrit 106707ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 106807ba6af4SMiriam Shitrit 106907ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 107007ba6af4SMiriam Shitrit dump_hdr.preset = bp->dump_preset_idx; 107107ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 107207ba6af4SMiriam Shitrit 107307ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 107407ba6af4SMiriam Shitrit 107507ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 107607ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 107707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 107807ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 107907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 108007ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 108107ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 108207ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 108307ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 108407ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 108507ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 108607ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 108707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 108807ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 108907ba6af4SMiriam Shitrit } 109007ba6af4SMiriam Shitrit 109107ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 109207ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 109307ba6af4SMiriam Shitrit 109407ba6af4SMiriam Shitrit /* Actually read the registers */ 109507ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 109607ba6af4SMiriam Shitrit 10974293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 109807ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 109907ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 110007ba6af4SMiriam Shitrit 110107ba6af4SMiriam Shitrit return 0; 1102adfc5217SJeff Kirsher } 1103adfc5217SJeff Kirsher 1104adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 1105adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 1106adfc5217SJeff Kirsher { 1107adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1108a1bcaf02SSudarsana Reddy Kalluru char version[ETHTOOL_FWVERS_LEN]; 1109a1bcaf02SSudarsana Reddy Kalluru int ext_dev_info_offset; 1110a1bcaf02SSudarsana Reddy Kalluru u32 mbi; 1111adfc5217SJeff Kirsher 111268aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 111368aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1114adfc5217SJeff Kirsher 1115a1bcaf02SSudarsana Reddy Kalluru if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) { 1116a1bcaf02SSudarsana Reddy Kalluru ext_dev_info_offset = SHMEM2_RD(bp, 1117a1bcaf02SSudarsana Reddy Kalluru extended_dev_info_shared_addr); 1118a1bcaf02SSudarsana Reddy Kalluru mbi = REG_RD(bp, ext_dev_info_offset + 1119a1bcaf02SSudarsana Reddy Kalluru offsetof(struct extended_dev_info_shared_cfg, 1120a1bcaf02SSudarsana Reddy Kalluru mbi_version)); 1121a1bcaf02SSudarsana Reddy Kalluru if (mbi) { 1122a1bcaf02SSudarsana Reddy Kalluru memset(version, 0, sizeof(version)); 1123a1bcaf02SSudarsana Reddy Kalluru snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ", 1124a1bcaf02SSudarsana Reddy Kalluru (mbi & 0xff000000) >> 24, 1125a1bcaf02SSudarsana Reddy Kalluru (mbi & 0x00ff0000) >> 16, 1126a1bcaf02SSudarsana Reddy Kalluru (mbi & 0x0000ff00) >> 8); 1127a1bcaf02SSudarsana Reddy Kalluru strlcpy(info->fw_version, version, 1128a1bcaf02SSudarsana Reddy Kalluru sizeof(info->fw_version)); 1129a1bcaf02SSudarsana Reddy Kalluru } 1130a1bcaf02SSudarsana Reddy Kalluru } 1131a1bcaf02SSudarsana Reddy Kalluru 1132a1bcaf02SSudarsana Reddy Kalluru memset(version, 0, sizeof(version)); 1133a1bcaf02SSudarsana Reddy Kalluru bnx2x_fill_fw_str(bp, version, ETHTOOL_FWVERS_LEN); 1134a1bcaf02SSudarsana Reddy Kalluru strlcat(info->fw_version, version, sizeof(info->fw_version)); 11358ca5e17eSAriel Elior 113668aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1137adfc5217SJeff Kirsher } 1138adfc5217SJeff Kirsher 1139adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1140adfc5217SJeff Kirsher { 1141adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 1144adfc5217SJeff Kirsher wol->supported = 0; 1145adfc5217SJeff Kirsher wol->wolopts = 0; 1146adfc5217SJeff Kirsher } else { 1147adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 1148adfc5217SJeff Kirsher if (bp->wol) 1149adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 1150adfc5217SJeff Kirsher else 1151adfc5217SJeff Kirsher wol->wolopts = 0; 1152adfc5217SJeff Kirsher } 1153adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 1154adfc5217SJeff Kirsher } 1155adfc5217SJeff Kirsher 1156adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1157adfc5217SJeff Kirsher { 1158adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1159adfc5217SJeff Kirsher 116051c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 11612de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1162adfc5217SJeff Kirsher return -EINVAL; 116351c1a580SMerav Sicron } 1164adfc5217SJeff Kirsher 1165adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 116651c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 11672de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1168adfc5217SJeff Kirsher return -EINVAL; 116951c1a580SMerav Sicron } 1170adfc5217SJeff Kirsher bp->wol = 1; 1171adfc5217SJeff Kirsher } else 1172adfc5217SJeff Kirsher bp->wol = 0; 1173adfc5217SJeff Kirsher 1174230d00ebSYuval Mintz if (SHMEM2_HAS(bp, curr_cfg)) 1175230d00ebSYuval Mintz SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1176230d00ebSYuval Mintz 1177adfc5217SJeff Kirsher return 0; 1178adfc5217SJeff Kirsher } 1179adfc5217SJeff Kirsher 1180adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 1181adfc5217SJeff Kirsher { 1182adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1183adfc5217SJeff Kirsher 1184adfc5217SJeff Kirsher return bp->msg_enable; 1185adfc5217SJeff Kirsher } 1186adfc5217SJeff Kirsher 1187adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1188adfc5217SJeff Kirsher { 1189adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1190adfc5217SJeff Kirsher 1191adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 1192adfc5217SJeff Kirsher /* dump MCP trace */ 1193ad5afc89SAriel Elior if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1194adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 1195adfc5217SJeff Kirsher bp->msg_enable = level; 1196adfc5217SJeff Kirsher } 1197adfc5217SJeff Kirsher } 1198adfc5217SJeff Kirsher 1199adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 1200adfc5217SJeff Kirsher { 1201adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1202adfc5217SJeff Kirsher 1203adfc5217SJeff Kirsher if (!bp->port.pmf) 1204adfc5217SJeff Kirsher return 0; 1205adfc5217SJeff Kirsher 1206adfc5217SJeff Kirsher if (netif_running(dev)) { 1207adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 12085d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1209adfc5217SJeff Kirsher bnx2x_link_set(bp); 1210adfc5217SJeff Kirsher } 1211adfc5217SJeff Kirsher 1212adfc5217SJeff Kirsher return 0; 1213adfc5217SJeff Kirsher } 1214adfc5217SJeff Kirsher 1215adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 1216adfc5217SJeff Kirsher { 1217adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1218adfc5217SJeff Kirsher 1219adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1220adfc5217SJeff Kirsher return 0; 1221adfc5217SJeff Kirsher 12226495d15aSDmitry Kravkov if (IS_VF(bp)) 12236495d15aSDmitry Kravkov return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 12246495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags); 12256495d15aSDmitry Kravkov 1226adfc5217SJeff Kirsher return bp->link_vars.link_up; 1227adfc5217SJeff Kirsher } 1228adfc5217SJeff Kirsher 1229adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 1230adfc5217SJeff Kirsher { 1231adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1232adfc5217SJeff Kirsher 1233adfc5217SJeff Kirsher return bp->common.flash_size; 1234adfc5217SJeff Kirsher } 1235adfc5217SJeff Kirsher 123616a5fd92SYuval Mintz /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 123716a5fd92SYuval Mintz * had we done things the other way around, if two pfs from the same port would 1238f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 1239f16da43bSAriel Elior * as: 1240f16da43bSAriel Elior * pf A takes the port lock. 1241f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 1242f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 1243f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 1244f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 1245f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 1246f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 12472de67439SYuval Mintz * access corrupted by pf B) 1248f16da43bSAriel Elior */ 1249adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1250adfc5217SJeff Kirsher { 1251adfc5217SJeff Kirsher int port = BP_PORT(bp); 1252adfc5217SJeff Kirsher int count, i; 1253f16da43bSAriel Elior u32 val; 1254f16da43bSAriel Elior 1255f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1256f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1257adfc5217SJeff Kirsher 1258adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1259adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1260adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1261adfc5217SJeff Kirsher count *= 100; 1262adfc5217SJeff Kirsher 1263adfc5217SJeff Kirsher /* request access to nvram interface */ 1264adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1265adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1266adfc5217SJeff Kirsher 1267adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1268adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1269adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1270adfc5217SJeff Kirsher break; 1271adfc5217SJeff Kirsher 1272adfc5217SJeff Kirsher udelay(5); 1273adfc5217SJeff Kirsher } 1274adfc5217SJeff Kirsher 1275adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 127651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 127751c1a580SMerav Sicron "cannot get access to nvram interface\n"); 1278efd38b8fSYuval Mintz bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1279adfc5217SJeff Kirsher return -EBUSY; 1280adfc5217SJeff Kirsher } 1281adfc5217SJeff Kirsher 1282adfc5217SJeff Kirsher return 0; 1283adfc5217SJeff Kirsher } 1284adfc5217SJeff Kirsher 1285adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1286adfc5217SJeff Kirsher { 1287adfc5217SJeff Kirsher int port = BP_PORT(bp); 1288adfc5217SJeff Kirsher int count, i; 1289f16da43bSAriel Elior u32 val; 1290adfc5217SJeff Kirsher 1291adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1292adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1293adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1294adfc5217SJeff Kirsher count *= 100; 1295adfc5217SJeff Kirsher 1296adfc5217SJeff Kirsher /* relinquish nvram interface */ 1297adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1298adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1299adfc5217SJeff Kirsher 1300adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1301adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1302adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1303adfc5217SJeff Kirsher break; 1304adfc5217SJeff Kirsher 1305adfc5217SJeff Kirsher udelay(5); 1306adfc5217SJeff Kirsher } 1307adfc5217SJeff Kirsher 1308adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 130951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 131051c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1311adfc5217SJeff Kirsher return -EBUSY; 1312adfc5217SJeff Kirsher } 1313adfc5217SJeff Kirsher 1314f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1315f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1316adfc5217SJeff Kirsher return 0; 1317adfc5217SJeff Kirsher } 1318adfc5217SJeff Kirsher 1319adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1320adfc5217SJeff Kirsher { 1321adfc5217SJeff Kirsher u32 val; 1322adfc5217SJeff Kirsher 1323adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1324adfc5217SJeff Kirsher 1325adfc5217SJeff Kirsher /* enable both bits, even on read */ 1326adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1327adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1328adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1329adfc5217SJeff Kirsher } 1330adfc5217SJeff Kirsher 1331adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1332adfc5217SJeff Kirsher { 1333adfc5217SJeff Kirsher u32 val; 1334adfc5217SJeff Kirsher 1335adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1336adfc5217SJeff Kirsher 1337adfc5217SJeff Kirsher /* disable both bits, even after read */ 1338adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1339adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1340adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1341adfc5217SJeff Kirsher } 1342adfc5217SJeff Kirsher 1343adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1344adfc5217SJeff Kirsher u32 cmd_flags) 1345adfc5217SJeff Kirsher { 1346adfc5217SJeff Kirsher int count, i, rc; 1347adfc5217SJeff Kirsher u32 val; 1348adfc5217SJeff Kirsher 1349adfc5217SJeff Kirsher /* build the command word */ 1350adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1351adfc5217SJeff Kirsher 1352adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1353adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1354adfc5217SJeff Kirsher 1355adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1356adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1357adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1358adfc5217SJeff Kirsher 1359adfc5217SJeff Kirsher /* issue a read command */ 1360adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1361adfc5217SJeff Kirsher 1362adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1363adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1364adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1365adfc5217SJeff Kirsher count *= 100; 1366adfc5217SJeff Kirsher 1367adfc5217SJeff Kirsher /* wait for completion */ 1368adfc5217SJeff Kirsher *ret_val = 0; 1369adfc5217SJeff Kirsher rc = -EBUSY; 1370adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1371adfc5217SJeff Kirsher udelay(5); 1372adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1373adfc5217SJeff Kirsher 1374adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1375adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1376adfc5217SJeff Kirsher /* we read nvram data in cpu order 1377adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 137807ba6af4SMiriam Shitrit * converting to big-endian will do the work 137907ba6af4SMiriam Shitrit */ 1380adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1381adfc5217SJeff Kirsher rc = 0; 1382adfc5217SJeff Kirsher break; 1383adfc5217SJeff Kirsher } 1384adfc5217SJeff Kirsher } 138551c1a580SMerav Sicron if (rc == -EBUSY) 138651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 138751c1a580SMerav Sicron "nvram read timeout expired\n"); 1388adfc5217SJeff Kirsher return rc; 1389adfc5217SJeff Kirsher } 1390adfc5217SJeff Kirsher 139197ac4ef7SYuval Mintz int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1392adfc5217SJeff Kirsher int buf_size) 1393adfc5217SJeff Kirsher { 1394adfc5217SJeff Kirsher int rc; 1395adfc5217SJeff Kirsher u32 cmd_flags; 1396adfc5217SJeff Kirsher __be32 val; 1397adfc5217SJeff Kirsher 1398adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 139951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1400adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1401adfc5217SJeff Kirsher offset, buf_size); 1402adfc5217SJeff Kirsher return -EINVAL; 1403adfc5217SJeff Kirsher } 1404adfc5217SJeff Kirsher 1405adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 140651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 140751c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1408adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1409adfc5217SJeff Kirsher return -EINVAL; 1410adfc5217SJeff Kirsher } 1411adfc5217SJeff Kirsher 1412adfc5217SJeff Kirsher /* request access to nvram interface */ 1413adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1414adfc5217SJeff Kirsher if (rc) 1415adfc5217SJeff Kirsher return rc; 1416adfc5217SJeff Kirsher 1417adfc5217SJeff Kirsher /* enable access to nvram interface */ 1418adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1419adfc5217SJeff Kirsher 1420adfc5217SJeff Kirsher /* read the first word(s) */ 1421adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1422adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1423adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1424adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1425adfc5217SJeff Kirsher 1426adfc5217SJeff Kirsher /* advance to the next dword */ 1427adfc5217SJeff Kirsher offset += sizeof(u32); 1428adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1429adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1430adfc5217SJeff Kirsher cmd_flags = 0; 1431adfc5217SJeff Kirsher } 1432adfc5217SJeff Kirsher 1433adfc5217SJeff Kirsher if (rc == 0) { 1434adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1435adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1436adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1437adfc5217SJeff Kirsher } 1438adfc5217SJeff Kirsher 1439adfc5217SJeff Kirsher /* disable access to nvram interface */ 1440adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1441adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1442adfc5217SJeff Kirsher 1443adfc5217SJeff Kirsher return rc; 1444adfc5217SJeff Kirsher } 1445adfc5217SJeff Kirsher 144685640952SDmitry Kravkov static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 144785640952SDmitry Kravkov int buf_size) 144885640952SDmitry Kravkov { 144985640952SDmitry Kravkov int rc; 145085640952SDmitry Kravkov 145185640952SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 145285640952SDmitry Kravkov 145385640952SDmitry Kravkov if (!rc) { 145485640952SDmitry Kravkov __be32 *be = (__be32 *)buf; 145585640952SDmitry Kravkov 145685640952SDmitry Kravkov while ((buf_size -= 4) >= 0) 145785640952SDmitry Kravkov *buf++ = be32_to_cpu(*be++); 145885640952SDmitry Kravkov } 145985640952SDmitry Kravkov 146085640952SDmitry Kravkov return rc; 146185640952SDmitry Kravkov } 146285640952SDmitry Kravkov 14633fb43eb2SYuval Mintz static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 14643fb43eb2SYuval Mintz { 14653fb43eb2SYuval Mintz int rc = 1; 14663fb43eb2SYuval Mintz u16 pm = 0; 14673fb43eb2SYuval Mintz struct net_device *dev = pci_get_drvdata(bp->pdev); 14683fb43eb2SYuval Mintz 146929ed74c3SJon Mason if (bp->pdev->pm_cap) 14703fb43eb2SYuval Mintz rc = pci_read_config_word(bp->pdev, 147129ed74c3SJon Mason bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 14723fb43eb2SYuval Mintz 1473829a5071SYuval Mintz if ((rc && !netif_running(dev)) || 1474c957d09fSYuval Mintz (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 14753fb43eb2SYuval Mintz return false; 14763fb43eb2SYuval Mintz 14773fb43eb2SYuval Mintz return true; 14783fb43eb2SYuval Mintz } 14793fb43eb2SYuval Mintz 1480adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1481adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1482adfc5217SJeff Kirsher { 1483adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1484adfc5217SJeff Kirsher 14853fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 148651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 148751c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1488adfc5217SJeff Kirsher return -EAGAIN; 148951c1a580SMerav Sicron } 1490adfc5217SJeff Kirsher 149151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1492f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1493adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1494adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1495adfc5217SJeff Kirsher 1496adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1497adfc5217SJeff Kirsher 1498f1691dc6SDmitry Kravkov return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1499adfc5217SJeff Kirsher } 1500adfc5217SJeff Kirsher 150124ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 150224ea818eSYuval Mintz struct ethtool_eeprom *ee, 150324ea818eSYuval Mintz u8 *data) 150424ea818eSYuval Mintz { 150524ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1506669d6996SYaniv Rosner int rc = -EINVAL, phy_idx; 150724ea818eSYuval Mintz u8 *user_data = data; 1508669d6996SYaniv Rosner unsigned int start_addr = ee->offset, xfer_size = 0; 150924ea818eSYuval Mintz 15103fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 151124ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 151224ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 151324ea818eSYuval Mintz return -EAGAIN; 151424ea818eSYuval Mintz } 151524ea818eSYuval Mintz 151624ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1517669d6996SYaniv Rosner 1518669d6996SYaniv Rosner /* Read A0 section */ 1519669d6996SYaniv Rosner if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1520669d6996SYaniv Rosner /* Limit transfer size to the A0 section boundary */ 1521669d6996SYaniv Rosner if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1522669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1523669d6996SYaniv Rosner else 1524669d6996SYaniv Rosner xfer_size = ee->len; 152524ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 152624ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 152724ea818eSYuval Mintz &bp->link_params, 1528669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1529669d6996SYaniv Rosner start_addr, 153024ea818eSYuval Mintz xfer_size, 153124ea818eSYuval Mintz user_data); 1532669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1533669d6996SYaniv Rosner if (rc) { 1534669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1535669d6996SYaniv Rosner 1536669d6996SYaniv Rosner return -EINVAL; 1537669d6996SYaniv Rosner } 153824ea818eSYuval Mintz user_data += xfer_size; 1539669d6996SYaniv Rosner start_addr += xfer_size; 154024ea818eSYuval Mintz } 154124ea818eSYuval Mintz 1542669d6996SYaniv Rosner /* Read A2 section */ 1543669d6996SYaniv Rosner if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1544669d6996SYaniv Rosner (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1545669d6996SYaniv Rosner xfer_size = ee->len - xfer_size; 1546669d6996SYaniv Rosner /* Limit transfer size to the A2 section boundary */ 1547669d6996SYaniv Rosner if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1548669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1549669d6996SYaniv Rosner start_addr -= ETH_MODULE_SFF_8079_LEN; 1550669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1551669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1552669d6996SYaniv Rosner &bp->link_params, 1553669d6996SYaniv Rosner I2C_DEV_ADDR_A2, 1554669d6996SYaniv Rosner start_addr, 1555669d6996SYaniv Rosner xfer_size, 1556669d6996SYaniv Rosner user_data); 155724ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 1558669d6996SYaniv Rosner if (rc) { 1559669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1560669d6996SYaniv Rosner return -EINVAL; 1561669d6996SYaniv Rosner } 1562669d6996SYaniv Rosner } 156324ea818eSYuval Mintz return rc; 156424ea818eSYuval Mintz } 156524ea818eSYuval Mintz 156624ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 156724ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 156824ea818eSYuval Mintz { 156924ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1570669d6996SYaniv Rosner int phy_idx, rc; 1571669d6996SYaniv Rosner u8 sff8472_comp, diag_type; 1572669d6996SYaniv Rosner 15733fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 157424ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 157524ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 157624ea818eSYuval Mintz return -EAGAIN; 157724ea818eSYuval Mintz } 157824ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1579669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1580669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1581669d6996SYaniv Rosner &bp->link_params, 1582669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1583669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_ADDR, 1584669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_SIZE, 1585669d6996SYaniv Rosner &sff8472_comp); 1586669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1587669d6996SYaniv Rosner if (rc) { 1588669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1589669d6996SYaniv Rosner return -EINVAL; 1590669d6996SYaniv Rosner } 1591669d6996SYaniv Rosner 1592669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1593669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1594669d6996SYaniv Rosner &bp->link_params, 1595669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1596669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_ADDR, 1597669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_SIZE, 1598669d6996SYaniv Rosner &diag_type); 1599669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1600669d6996SYaniv Rosner if (rc) { 1601669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1602669d6996SYaniv Rosner return -EINVAL; 1603669d6996SYaniv Rosner } 1604669d6996SYaniv Rosner 1605669d6996SYaniv Rosner if (!sff8472_comp || 1606669d6996SYaniv Rosner (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 160724ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 160824ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1609669d6996SYaniv Rosner } else { 1610669d6996SYaniv Rosner modinfo->type = ETH_MODULE_SFF_8472; 1611669d6996SYaniv Rosner modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 161224ea818eSYuval Mintz } 1613669d6996SYaniv Rosner return 0; 161424ea818eSYuval Mintz } 161524ea818eSYuval Mintz 1616adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1617adfc5217SJeff Kirsher u32 cmd_flags) 1618adfc5217SJeff Kirsher { 1619adfc5217SJeff Kirsher int count, i, rc; 1620adfc5217SJeff Kirsher 1621adfc5217SJeff Kirsher /* build the command word */ 1622adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1623adfc5217SJeff Kirsher 1624adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1625adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1626adfc5217SJeff Kirsher 1627adfc5217SJeff Kirsher /* write the data */ 1628adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1629adfc5217SJeff Kirsher 1630adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1631adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1632adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1633adfc5217SJeff Kirsher 1634adfc5217SJeff Kirsher /* issue the write command */ 1635adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1636adfc5217SJeff Kirsher 1637adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1638adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1639adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1640adfc5217SJeff Kirsher count *= 100; 1641adfc5217SJeff Kirsher 1642adfc5217SJeff Kirsher /* wait for completion */ 1643adfc5217SJeff Kirsher rc = -EBUSY; 1644adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1645adfc5217SJeff Kirsher udelay(5); 1646adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1647adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1648adfc5217SJeff Kirsher rc = 0; 1649adfc5217SJeff Kirsher break; 1650adfc5217SJeff Kirsher } 1651adfc5217SJeff Kirsher } 1652adfc5217SJeff Kirsher 165351c1a580SMerav Sicron if (rc == -EBUSY) 165451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 165551c1a580SMerav Sicron "nvram write timeout expired\n"); 1656adfc5217SJeff Kirsher return rc; 1657adfc5217SJeff Kirsher } 1658adfc5217SJeff Kirsher 1659adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1660adfc5217SJeff Kirsher 1661adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1662adfc5217SJeff Kirsher int buf_size) 1663adfc5217SJeff Kirsher { 1664adfc5217SJeff Kirsher int rc; 166530c20b67SDmitry Kravkov u32 cmd_flags, align_offset, val; 166630c20b67SDmitry Kravkov __be32 val_be; 1667adfc5217SJeff Kirsher 1668adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 166951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 167051c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1671adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1672adfc5217SJeff Kirsher return -EINVAL; 1673adfc5217SJeff Kirsher } 1674adfc5217SJeff Kirsher 1675adfc5217SJeff Kirsher /* request access to nvram interface */ 1676adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1677adfc5217SJeff Kirsher if (rc) 1678adfc5217SJeff Kirsher return rc; 1679adfc5217SJeff Kirsher 1680adfc5217SJeff Kirsher /* enable access to nvram interface */ 1681adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1682adfc5217SJeff Kirsher 1683adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1684adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 168530c20b67SDmitry Kravkov rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1686adfc5217SJeff Kirsher 1687adfc5217SJeff Kirsher if (rc == 0) { 1688adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 168907ba6af4SMiriam Shitrit * convert it back to cpu order 169007ba6af4SMiriam Shitrit */ 169130c20b67SDmitry Kravkov val = be32_to_cpu(val_be); 169230c20b67SDmitry Kravkov 1693c957d09fSYuval Mintz val &= ~le32_to_cpu((__force __le32) 1694c957d09fSYuval Mintz (0xff << BYTE_OFFSET(offset))); 1695c957d09fSYuval Mintz val |= le32_to_cpu((__force __le32) 1696c957d09fSYuval Mintz (*data_buf << BYTE_OFFSET(offset))); 1697adfc5217SJeff Kirsher 1698adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1699adfc5217SJeff Kirsher cmd_flags); 1700adfc5217SJeff Kirsher } 1701adfc5217SJeff Kirsher 1702adfc5217SJeff Kirsher /* disable access to nvram interface */ 1703adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1704adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1705adfc5217SJeff Kirsher 1706adfc5217SJeff Kirsher return rc; 1707adfc5217SJeff Kirsher } 1708adfc5217SJeff Kirsher 1709adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1710adfc5217SJeff Kirsher int buf_size) 1711adfc5217SJeff Kirsher { 1712adfc5217SJeff Kirsher int rc; 1713adfc5217SJeff Kirsher u32 cmd_flags; 1714adfc5217SJeff Kirsher u32 val; 1715adfc5217SJeff Kirsher u32 written_so_far; 1716adfc5217SJeff Kirsher 1717adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1718adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1719adfc5217SJeff Kirsher 1720adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 172151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1722adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1723adfc5217SJeff Kirsher offset, buf_size); 1724adfc5217SJeff Kirsher return -EINVAL; 1725adfc5217SJeff Kirsher } 1726adfc5217SJeff Kirsher 1727adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 172851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 172951c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1730adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1731adfc5217SJeff Kirsher return -EINVAL; 1732adfc5217SJeff Kirsher } 1733adfc5217SJeff Kirsher 1734adfc5217SJeff Kirsher /* request access to nvram interface */ 1735adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1736adfc5217SJeff Kirsher if (rc) 1737adfc5217SJeff Kirsher return rc; 1738adfc5217SJeff Kirsher 1739adfc5217SJeff Kirsher /* enable access to nvram interface */ 1740adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1741adfc5217SJeff Kirsher 1742adfc5217SJeff Kirsher written_so_far = 0; 1743adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1744adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1745adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1746adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1747adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1748adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1749adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1750adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1751adfc5217SJeff Kirsher 1752adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1753adfc5217SJeff Kirsher 175468bf5a10SYuval Mintz /* Notice unlike bnx2x_nvram_read_dword() this will not 175568bf5a10SYuval Mintz * change val using be32_to_cpu(), which causes data to flip 175668bf5a10SYuval Mintz * if the eeprom is read and then written back. This is due 175768bf5a10SYuval Mintz * to tools utilizing this functionality that would break 175868bf5a10SYuval Mintz * if this would be resolved. 175968bf5a10SYuval Mintz */ 1760adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1761adfc5217SJeff Kirsher 1762adfc5217SJeff Kirsher /* advance to the next dword */ 1763adfc5217SJeff Kirsher offset += sizeof(u32); 1764adfc5217SJeff Kirsher data_buf += sizeof(u32); 1765adfc5217SJeff Kirsher written_so_far += sizeof(u32); 17660ea853dfSYuval Mintz 17670ea853dfSYuval Mintz /* At end of each 4Kb page, release nvram lock to allow MFW 17680ea853dfSYuval Mintz * chance to take it for its own use. 17690ea853dfSYuval Mintz */ 17700ea853dfSYuval Mintz if ((cmd_flags & MCPR_NVM_COMMAND_LAST) && 17710ea853dfSYuval Mintz (written_so_far < buf_size)) { 17720ea853dfSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 17730ea853dfSYuval Mintz "Releasing NVM lock after offset 0x%x\n", 17740ea853dfSYuval Mintz (u32)(offset - sizeof(u32))); 17750ea853dfSYuval Mintz bnx2x_release_nvram_lock(bp); 17760ea853dfSYuval Mintz usleep_range(1000, 2000); 17770ea853dfSYuval Mintz rc = bnx2x_acquire_nvram_lock(bp); 17780ea853dfSYuval Mintz if (rc) 17790ea853dfSYuval Mintz return rc; 17800ea853dfSYuval Mintz } 17810ea853dfSYuval Mintz 1782adfc5217SJeff Kirsher cmd_flags = 0; 1783adfc5217SJeff Kirsher } 1784adfc5217SJeff Kirsher 1785adfc5217SJeff Kirsher /* disable access to nvram interface */ 1786adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1787adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1788adfc5217SJeff Kirsher 1789adfc5217SJeff Kirsher return rc; 1790adfc5217SJeff Kirsher } 1791adfc5217SJeff Kirsher 1792adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1793adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1794adfc5217SJeff Kirsher { 1795adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1796adfc5217SJeff Kirsher int port = BP_PORT(bp); 1797adfc5217SJeff Kirsher int rc = 0; 1798adfc5217SJeff Kirsher u32 ext_phy_config; 17993fb43eb2SYuval Mintz 18003fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 180151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 180251c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1803adfc5217SJeff Kirsher return -EAGAIN; 180451c1a580SMerav Sicron } 1805adfc5217SJeff Kirsher 180651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1807f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1808adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1809adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1810adfc5217SJeff Kirsher 1811adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1812adfc5217SJeff Kirsher 1813adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1814adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 181551c1a580SMerav Sicron !bp->port.pmf) { 181651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 181751c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1818adfc5217SJeff Kirsher return -EINVAL; 181951c1a580SMerav Sicron } 1820adfc5217SJeff Kirsher 1821adfc5217SJeff Kirsher ext_phy_config = 1822adfc5217SJeff Kirsher SHMEM_RD(bp, 1823adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1824adfc5217SJeff Kirsher 1825adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1826adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1827adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1828adfc5217SJeff Kirsher 1829adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1830adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1831adfc5217SJeff Kirsher &bp->link_vars, 0); 1832adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1833adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1834adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1835adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1836adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1837adfc5217SJeff Kirsher bnx2x_link_report(bp); 1838adfc5217SJeff Kirsher 1839adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1840adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1841adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1842adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1843adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1844adfc5217SJeff Kirsher &bp->link_vars, 1); 1845adfc5217SJeff Kirsher 1846adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1847adfc5217SJeff Kirsher &bp->link_vars); 1848adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1849adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1850adfc5217SJeff Kirsher } 1851adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1852adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1853adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1854adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1855adfc5217SJeff Kirsher 1856adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1857adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1858adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1859adfc5217SJeff Kirsher 1860adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1861adfc5217SJeff Kirsher 1862adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1863adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1864adfc5217SJeff Kirsher 1865adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1866adfc5217SJeff Kirsher msleep(500); 1867adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1868adfc5217SJeff Kirsher msleep(500); 1869adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1870adfc5217SJeff Kirsher } 1871adfc5217SJeff Kirsher } else 1872adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1873adfc5217SJeff Kirsher 1874adfc5217SJeff Kirsher return rc; 1875adfc5217SJeff Kirsher } 1876adfc5217SJeff Kirsher 1877adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1878adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1879adfc5217SJeff Kirsher { 1880adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1881adfc5217SJeff Kirsher 1882adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1883adfc5217SJeff Kirsher 1884adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1885adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1886adfc5217SJeff Kirsher 1887adfc5217SJeff Kirsher return 0; 1888adfc5217SJeff Kirsher } 1889adfc5217SJeff Kirsher 1890adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1891adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1892adfc5217SJeff Kirsher { 1893adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1894adfc5217SJeff Kirsher 1895adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1896adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1897adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1898adfc5217SJeff Kirsher 1899adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1900adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1901adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1902adfc5217SJeff Kirsher 1903adfc5217SJeff Kirsher if (netif_running(dev)) 1904adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1905adfc5217SJeff Kirsher 1906adfc5217SJeff Kirsher return 0; 1907adfc5217SJeff Kirsher } 1908adfc5217SJeff Kirsher 1909adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1910adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1911adfc5217SJeff Kirsher { 1912adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1913adfc5217SJeff Kirsher 1914adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1915adfc5217SJeff Kirsher 191665870fa7SMintz, Yuval /* If size isn't already set, we give an estimation of the number 191765870fa7SMintz, Yuval * of buffers we'll have. We're neglecting some possible conditions 191865870fa7SMintz, Yuval * [we couldn't know for certain at this point if number of queues 191965870fa7SMintz, Yuval * might shrink] but the number would be correct for the likely 192065870fa7SMintz, Yuval * scenario. 192165870fa7SMintz, Yuval */ 1922adfc5217SJeff Kirsher if (bp->rx_ring_size) 1923adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 192465870fa7SMintz, Yuval else if (BNX2X_NUM_RX_QUEUES(bp)) 192565870fa7SMintz, Yuval ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp); 1926adfc5217SJeff Kirsher else 1927adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1928adfc5217SJeff Kirsher 1929a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1930adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1931adfc5217SJeff Kirsher } 1932adfc5217SJeff Kirsher 1933adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1934adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1935adfc5217SJeff Kirsher { 1936adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1937adfc5217SJeff Kirsher 193804c46736SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 193904c46736SYuval Mintz "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 194004c46736SYuval Mintz ering->rx_pending, ering->tx_pending); 194104c46736SYuval Mintz 1942909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 1943909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, 1944909d9faaSYuval Mintz "VFs are enabled, can not change ring parameters\n"); 1945909d9faaSYuval Mintz return -EPERM; 1946909d9faaSYuval Mintz } 1947909d9faaSYuval Mintz 1948adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 194951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 195051c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1951adfc5217SJeff Kirsher return -EAGAIN; 1952adfc5217SJeff Kirsher } 1953adfc5217SJeff Kirsher 1954adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1955adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1956adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 19572e98ffc2SDmitry Kravkov (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 195851c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 195951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1960adfc5217SJeff Kirsher return -EINVAL; 196151c1a580SMerav Sicron } 1962adfc5217SJeff Kirsher 1963adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1964adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1965adfc5217SJeff Kirsher 1966adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1967adfc5217SJeff Kirsher } 1968adfc5217SJeff Kirsher 1969adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1970adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1971adfc5217SJeff Kirsher { 1972adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1973adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 19749e7e8399SMintz Yuval int cfg_reg; 19759e7e8399SMintz Yuval 1976adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1977adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1978adfc5217SJeff Kirsher 19799e7e8399SMintz Yuval if (!epause->autoneg) 1980241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 19819e7e8399SMintz Yuval else 19829e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 19839e7e8399SMintz Yuval 19849e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1985adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 19869e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1987adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1988adfc5217SJeff Kirsher 198951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1990f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1991adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1992adfc5217SJeff Kirsher } 1993adfc5217SJeff Kirsher 1994adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1995adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1996adfc5217SJeff Kirsher { 1997adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1998adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1999adfc5217SJeff Kirsher if (IS_MF(bp)) 2000adfc5217SJeff Kirsher return 0; 2001adfc5217SJeff Kirsher 200251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 2003f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 2004adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 2005adfc5217SJeff Kirsher 2006adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 2007adfc5217SJeff Kirsher 2008adfc5217SJeff Kirsher if (epause->rx_pause) 2009adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 2010adfc5217SJeff Kirsher 2011adfc5217SJeff Kirsher if (epause->tx_pause) 2012adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 2013adfc5217SJeff Kirsher 2014adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 2015adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher if (epause->autoneg) { 2018adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 201951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 2020adfc5217SJeff Kirsher return -EINVAL; 2021adfc5217SJeff Kirsher } 2022adfc5217SJeff Kirsher 2023adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 2024adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 2025adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 2026adfc5217SJeff Kirsher } 2027ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv = 0; 20285cd75f0cSYaniv Rosner if (epause->rx_pause) 20295cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 20305cd75f0cSYaniv Rosner 20315cd75f0cSYaniv Rosner if (epause->tx_pause) 20325cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 2033ba35a0fdSYaniv Rosner 2034ba35a0fdSYaniv Rosner if (!bp->link_params.req_fc_auto_adv) 2035ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 2036adfc5217SJeff Kirsher } 2037adfc5217SJeff Kirsher 203851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2039adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 2040adfc5217SJeff Kirsher 2041adfc5217SJeff Kirsher if (netif_running(dev)) { 2042adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2043dc6a20aaSAriel Elior bnx2x_force_link_reset(bp); 2044adfc5217SJeff Kirsher bnx2x_link_set(bp); 2045adfc5217SJeff Kirsher } 2046adfc5217SJeff Kirsher 2047adfc5217SJeff Kirsher return 0; 2048adfc5217SJeff Kirsher } 2049adfc5217SJeff Kirsher 20505889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 2051cf2c1df6SMerav Sicron "register_test (offline) ", 2052cf2c1df6SMerav Sicron "memory_test (offline) ", 2053cf2c1df6SMerav Sicron "int_loopback_test (offline)", 2054cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 2055cf2c1df6SMerav Sicron "nvram_test (online) ", 2056cf2c1df6SMerav Sicron "interrupt_test (online) ", 2057cf2c1df6SMerav Sicron "link_test (online) " 2058adfc5217SJeff Kirsher }; 2059adfc5217SJeff Kirsher 20603521b419SYuval Mintz enum { 20613521b419SYuval Mintz BNX2X_PRI_FLAG_ISCSI, 20623521b419SYuval Mintz BNX2X_PRI_FLAG_FCOE, 20633521b419SYuval Mintz BNX2X_PRI_FLAG_STORAGE, 20643521b419SYuval Mintz BNX2X_PRI_FLAG_LEN, 20653521b419SYuval Mintz }; 20663521b419SYuval Mintz 20673521b419SYuval Mintz static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 20683521b419SYuval Mintz "iSCSI offload support", 20693521b419SYuval Mintz "FCoE offload support", 20703521b419SYuval Mintz "Storage only interface" 20713521b419SYuval Mintz }; 20723521b419SYuval Mintz 2073e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 2074e9939c80SYuval Mintz { 2075e9939c80SYuval Mintz u32 modes = 0; 2076e9939c80SYuval Mintz 2077e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 2078e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 2079e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 2080e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 2081e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 2082e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 2083e9939c80SYuval Mintz 2084e9939c80SYuval Mintz return modes; 2085e9939c80SYuval Mintz } 2086e9939c80SYuval Mintz 2087e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2088e9939c80SYuval Mintz { 2089e9939c80SYuval Mintz u32 eee_adv = 0; 2090e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 2091e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 2092e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 2093e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 2094e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 2095e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 2096e9939c80SYuval Mintz 2097e9939c80SYuval Mintz return eee_adv << shift; 2098e9939c80SYuval Mintz } 2099e9939c80SYuval Mintz 2100e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2101e9939c80SYuval Mintz { 2102e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2103e9939c80SYuval Mintz u32 eee_cfg; 2104e9939c80SYuval Mintz 2105e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2106e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2107e9939c80SYuval Mintz return -EOPNOTSUPP; 2108e9939c80SYuval Mintz } 2109e9939c80SYuval Mintz 211008e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2111e9939c80SYuval Mintz 2112e9939c80SYuval Mintz edata->supported = 2113e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2114e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 2115e9939c80SYuval Mintz 2116e9939c80SYuval Mintz edata->advertised = 2117e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2118e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2119e9939c80SYuval Mintz edata->lp_advertised = 2120e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2121e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2122e9939c80SYuval Mintz 2123e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 2124e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2125e9939c80SYuval Mintz 2126e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2127e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2128e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2129e9939c80SYuval Mintz 2130e9939c80SYuval Mintz return 0; 2131e9939c80SYuval Mintz } 2132e9939c80SYuval Mintz 2133e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2134e9939c80SYuval Mintz { 2135e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2136e9939c80SYuval Mintz u32 eee_cfg; 2137e9939c80SYuval Mintz u32 advertised; 2138e9939c80SYuval Mintz 2139e9939c80SYuval Mintz if (IS_MF(bp)) 2140e9939c80SYuval Mintz return 0; 2141e9939c80SYuval Mintz 2142e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2143e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2144e9939c80SYuval Mintz return -EOPNOTSUPP; 2145e9939c80SYuval Mintz } 2146e9939c80SYuval Mintz 214708e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2148e9939c80SYuval Mintz 2149e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2150e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2151e9939c80SYuval Mintz return -EOPNOTSUPP; 2152e9939c80SYuval Mintz } 2153e9939c80SYuval Mintz 2154e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 2155e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2156e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2157e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2158efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 2159e9939c80SYuval Mintz return -EINVAL; 2160e9939c80SYuval Mintz } 2161e9939c80SYuval Mintz 2162e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2163e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2164e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 2165e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 2166e9939c80SYuval Mintz return -EINVAL; 2167e9939c80SYuval Mintz } 2168e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 2169e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2170e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2171e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 2172e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2173e9939c80SYuval Mintz return -EINVAL; 2174e9939c80SYuval Mintz } 2175e9939c80SYuval Mintz 2176e9939c80SYuval Mintz /* All is well; Apply changes*/ 2177e9939c80SYuval Mintz if (edata->eee_enabled) 2178e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2179e9939c80SYuval Mintz else 2180e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2181e9939c80SYuval Mintz 2182e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 2183e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2184e9939c80SYuval Mintz else 2185e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2186e9939c80SYuval Mintz 2187e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2188e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2189e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 2190e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 2191e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 2192e9939c80SYuval Mintz 219316a5fd92SYuval Mintz /* Restart link to propagate changes */ 2194e9939c80SYuval Mintz if (netif_running(dev)) { 2195e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 21965d07d868SYuval Mintz bnx2x_force_link_reset(bp); 2197e9939c80SYuval Mintz bnx2x_link_set(bp); 2198e9939c80SYuval Mintz } 2199e9939c80SYuval Mintz 2200e9939c80SYuval Mintz return 0; 2201e9939c80SYuval Mintz } 2202e9939c80SYuval Mintz 2203adfc5217SJeff Kirsher enum { 2204adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 2205adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 2206adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 2207adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 2208adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 2209adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 2210adfc5217SJeff Kirsher }; 2211adfc5217SJeff Kirsher 2212adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2213adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2214adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2215adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2216adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2217adfc5217SJeff Kirsher 2218adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2219adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2220adfc5217SJeff Kirsher 2221adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 2222adfc5217SJeff Kirsher { 2223adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 2224adfc5217SJeff Kirsher u32 wr_val = 0, hw; 2225adfc5217SJeff Kirsher int port = BP_PORT(bp); 2226adfc5217SJeff Kirsher static const struct { 2227adfc5217SJeff Kirsher u32 hw; 2228adfc5217SJeff Kirsher u32 offset0; 2229adfc5217SJeff Kirsher u32 offset1; 2230adfc5217SJeff Kirsher u32 mask; 2231adfc5217SJeff Kirsher } reg_tbl[] = { 2232adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 2233adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2234adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2235adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2236adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 2237adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 2238adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2239adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2240adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2241adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2242adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 2243adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2244adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2245adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2246adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2247adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2248adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2249adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2250adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2251adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2252adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 2253adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2254adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2255adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2256adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2257adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 2258adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2259adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2260adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2261adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2262adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2263adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2264adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2265adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2266adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2267adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2268adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2269adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2270adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2271adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2272adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2273adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2274adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2275adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2276adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2277adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2278adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2279adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2280adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2281adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2282adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2283adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2284adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2285adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2286adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2287adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2288adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2289adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2290adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2291adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2292adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 2293adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2294adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2295adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2296adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2297adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2298adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2299adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2300adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2301adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2302adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2303adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2304adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2305adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2306adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2307adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2308adfc5217SJeff Kirsher 2309adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2310adfc5217SJeff Kirsher }; 2311adfc5217SJeff Kirsher 23123fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 231351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 231451c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2315adfc5217SJeff Kirsher return rc; 231651c1a580SMerav Sicron } 2317adfc5217SJeff Kirsher 2318adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2319adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 2320adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2321adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 2322adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2323adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 2324adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 2325adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 2326adfc5217SJeff Kirsher else /* e3 A0 */ 2327adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 2328adfc5217SJeff Kirsher 2329adfc5217SJeff Kirsher /* Repeat the test twice: 233007ba6af4SMiriam Shitrit * First by writing 0x00000000, second by writing 0xffffffff 233107ba6af4SMiriam Shitrit */ 2332adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 2333adfc5217SJeff Kirsher 2334adfc5217SJeff Kirsher switch (idx) { 2335adfc5217SJeff Kirsher case 0: 2336adfc5217SJeff Kirsher wr_val = 0; 2337adfc5217SJeff Kirsher break; 2338adfc5217SJeff Kirsher case 1: 2339adfc5217SJeff Kirsher wr_val = 0xffffffff; 2340adfc5217SJeff Kirsher break; 2341adfc5217SJeff Kirsher } 2342adfc5217SJeff Kirsher 2343adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2344adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 2345adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 2346adfc5217SJeff Kirsher continue; 2347adfc5217SJeff Kirsher 2348adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2349adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 2350adfc5217SJeff Kirsher 2351adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 2352adfc5217SJeff Kirsher 2353adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 2354adfc5217SJeff Kirsher 2355adfc5217SJeff Kirsher val = REG_RD(bp, offset); 2356adfc5217SJeff Kirsher 2357adfc5217SJeff Kirsher /* Restore the original register's value */ 2358adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 2359adfc5217SJeff Kirsher 2360adfc5217SJeff Kirsher /* verify value is as expected */ 2361adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 236251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2363adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2364adfc5217SJeff Kirsher offset, val, wr_val, mask); 2365adfc5217SJeff Kirsher goto test_reg_exit; 2366adfc5217SJeff Kirsher } 2367adfc5217SJeff Kirsher } 2368adfc5217SJeff Kirsher } 2369adfc5217SJeff Kirsher 2370adfc5217SJeff Kirsher rc = 0; 2371adfc5217SJeff Kirsher 2372adfc5217SJeff Kirsher test_reg_exit: 2373adfc5217SJeff Kirsher return rc; 2374adfc5217SJeff Kirsher } 2375adfc5217SJeff Kirsher 2376adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 2377adfc5217SJeff Kirsher { 2378adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 2379adfc5217SJeff Kirsher u32 val, index; 2380adfc5217SJeff Kirsher static const struct { 2381adfc5217SJeff Kirsher u32 offset; 2382adfc5217SJeff Kirsher int size; 2383adfc5217SJeff Kirsher } mem_tbl[] = { 2384adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2385adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2386adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2387adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2388adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2389adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2390adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2391adfc5217SJeff Kirsher 2392adfc5217SJeff Kirsher { 0xffffffff, 0 } 2393adfc5217SJeff Kirsher }; 2394adfc5217SJeff Kirsher 2395adfc5217SJeff Kirsher static const struct { 2396adfc5217SJeff Kirsher char *name; 2397adfc5217SJeff Kirsher u32 offset; 2398adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2399adfc5217SJeff Kirsher } prty_tbl[] = { 2400adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2401adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2402adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2403adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 2404adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2405adfc5217SJeff Kirsher {0, 0, 0, 0} }, 2406adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2407adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2408adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2409adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2410adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2411adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 2412adfc5217SJeff Kirsher 2413adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 2414adfc5217SJeff Kirsher }; 2415adfc5217SJeff Kirsher 24163fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 241751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 241851c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2419adfc5217SJeff Kirsher return rc; 242051c1a580SMerav Sicron } 2421adfc5217SJeff Kirsher 2422adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2423adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 2424adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2425adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 2426adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2427adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 2428adfc5217SJeff Kirsher else /* e3 */ 2429adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 2430adfc5217SJeff Kirsher 2431adfc5217SJeff Kirsher /* pre-Check the parity status */ 2432adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2433adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2434adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 243551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2436adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2437adfc5217SJeff Kirsher goto test_mem_exit; 2438adfc5217SJeff Kirsher } 2439adfc5217SJeff Kirsher } 2440adfc5217SJeff Kirsher 2441adfc5217SJeff Kirsher /* Go through all the memories */ 2442adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2443adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 2444adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 2445adfc5217SJeff Kirsher 2446adfc5217SJeff Kirsher /* Check the parity status */ 2447adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2448adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2449adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 245051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2451adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2452adfc5217SJeff Kirsher goto test_mem_exit; 2453adfc5217SJeff Kirsher } 2454adfc5217SJeff Kirsher } 2455adfc5217SJeff Kirsher 2456adfc5217SJeff Kirsher rc = 0; 2457adfc5217SJeff Kirsher 2458adfc5217SJeff Kirsher test_mem_exit: 2459adfc5217SJeff Kirsher return rc; 2460adfc5217SJeff Kirsher } 2461adfc5217SJeff Kirsher 2462adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2463adfc5217SJeff Kirsher { 2464adfc5217SJeff Kirsher int cnt = 1400; 2465adfc5217SJeff Kirsher 2466adfc5217SJeff Kirsher if (link_up) { 2467adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2468adfc5217SJeff Kirsher msleep(20); 2469adfc5217SJeff Kirsher 2470adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 247151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 24728970b2e4SMerav Sicron 24738970b2e4SMerav Sicron cnt = 1400; 24748970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 24758970b2e4SMerav Sicron msleep(20); 24768970b2e4SMerav Sicron 24778970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 24788970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24798970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2480adfc5217SJeff Kirsher } 2481adfc5217SJeff Kirsher } 2482adfc5217SJeff Kirsher 2483adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2484adfc5217SJeff Kirsher { 2485adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2486adfc5217SJeff Kirsher struct sk_buff *skb; 2487adfc5217SJeff Kirsher unsigned char *packet; 2488adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2489adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 249065565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2491adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2492adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2493b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2494adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2495adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2496adfc5217SJeff Kirsher dma_addr_t mapping; 2497adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2498adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2499adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2500adfc5217SJeff Kirsher u16 len; 2501adfc5217SJeff Kirsher int rc = -ENODEV; 2502e52fcb24SEric Dumazet u8 *data; 25038970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 25048970b2e4SMerav Sicron txdata->txq_index); 2505adfc5217SJeff Kirsher 2506adfc5217SJeff Kirsher /* check the loopback mode */ 2507adfc5217SJeff Kirsher switch (loopback_mode) { 2508adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 25098970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 25108970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2511adfc5217SJeff Kirsher return -EINVAL; 25128970b2e4SMerav Sicron } 2513adfc5217SJeff Kirsher break; 2514adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 251532911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 251632911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 251732911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 251832911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 251932911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 252032911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 252132911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 252232911333SYaniv Rosner else 252332911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 252432911333SYaniv Rosner } else 252532911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 252632911333SYaniv Rosner 2527adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2528adfc5217SJeff Kirsher break; 25298970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 25308970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 25318970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 25328970b2e4SMerav Sicron "Can't configure external loopback\n"); 25338970b2e4SMerav Sicron return -EINVAL; 25348970b2e4SMerav Sicron } 25358970b2e4SMerav Sicron break; 2536adfc5217SJeff Kirsher default: 253751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2538adfc5217SJeff Kirsher return -EINVAL; 2539adfc5217SJeff Kirsher } 2540adfc5217SJeff Kirsher 2541adfc5217SJeff Kirsher /* prepare the loopback packet */ 2542adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2543adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2544adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2545adfc5217SJeff Kirsher if (!skb) { 254651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2547adfc5217SJeff Kirsher rc = -ENOMEM; 2548adfc5217SJeff Kirsher goto test_loopback_exit; 2549adfc5217SJeff Kirsher } 2550adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2551adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2552c7bf7169SJoe Perches eth_zero_addr(packet + ETH_ALEN); 2553adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2554adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2555adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2556adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2557adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2558adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2559adfc5217SJeff Kirsher rc = -ENOMEM; 2560adfc5217SJeff Kirsher dev_kfree_skb(skb); 256151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2562adfc5217SJeff Kirsher goto test_loopback_exit; 2563adfc5217SJeff Kirsher } 2564adfc5217SJeff Kirsher 2565adfc5217SJeff Kirsher /* send the loopback packet */ 2566adfc5217SJeff Kirsher num_pkts = 0; 2567adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2568adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2569adfc5217SJeff Kirsher 257073dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 257173dbb5e1SDmitry Kravkov 2572adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2573adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2574adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2575adfc5217SJeff Kirsher tx_buf->skb = skb; 2576adfc5217SJeff Kirsher tx_buf->flags = 0; 2577adfc5217SJeff Kirsher 2578adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2579adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2580adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2581adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2582adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2583adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2584adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2585adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2586adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2587adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2588adfc5217SJeff Kirsher 1); 258996bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 259096bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 259196bed4b9SYuval Mintz 0); 2592adfc5217SJeff Kirsher 2593adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2594adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2595adfc5217SJeff Kirsher 259696bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 259796bed4b9SYuval Mintz u16 global_data = 0; 259896bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 259996bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2600adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 260196bed4b9SYuval Mintz SET_FLAG(global_data, 260296bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 260396bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 260496bed4b9SYuval Mintz } else { 260596bed4b9SYuval Mintz u32 parsing_data = 0; 260696bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 260796bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 260896bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 260996bed4b9SYuval Mintz SET_FLAG(parsing_data, 261096bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 261196bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 261296bed4b9SYuval Mintz } 2613adfc5217SJeff Kirsher wmb(); 2614adfc5217SJeff Kirsher 2615adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2616edd87423SSinan Kaya /* make sure descriptor update is observed by the HW */ 2617edd87423SSinan Kaya wmb(); 26187f883c77SSinan Kaya DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw); 2619adfc5217SJeff Kirsher 2620adfc5217SJeff Kirsher mmiowb(); 2621adfc5217SJeff Kirsher barrier(); 2622adfc5217SJeff Kirsher 2623adfc5217SJeff Kirsher num_pkts++; 2624adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2625adfc5217SJeff Kirsher 2626adfc5217SJeff Kirsher udelay(100); 2627adfc5217SJeff Kirsher 2628adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2629adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2630adfc5217SJeff Kirsher goto test_loopback_exit; 2631adfc5217SJeff Kirsher 2632adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2633adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2634adfc5217SJeff Kirsher * disabled. 2635adfc5217SJeff Kirsher */ 2636adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2637adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2638adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2639adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2640adfc5217SJeff Kirsher */ 2641adfc5217SJeff Kirsher local_bh_disable(); 2642adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2643adfc5217SJeff Kirsher local_bh_enable(); 2644adfc5217SJeff Kirsher } 2645adfc5217SJeff Kirsher 2646adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2647adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2648adfc5217SJeff Kirsher goto test_loopback_exit; 2649adfc5217SJeff Kirsher 2650b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2651adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2652adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2653adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2654adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2655adfc5217SJeff Kirsher 2656621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2657adfc5217SJeff Kirsher if (len != pkt_size) 2658adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2659adfc5217SJeff Kirsher 2660adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2661adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2662adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2663adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2664e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2665adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2666e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2667adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2668adfc5217SJeff Kirsher 2669adfc5217SJeff Kirsher rc = 0; 2670adfc5217SJeff Kirsher 2671adfc5217SJeff Kirsher test_loopback_rx_exit: 2672adfc5217SJeff Kirsher 2673adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2674adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2675adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2676adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2677adfc5217SJeff Kirsher 2678adfc5217SJeff Kirsher /* Update producers */ 2679adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2680adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2681adfc5217SJeff Kirsher 2682adfc5217SJeff Kirsher test_loopback_exit: 2683adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2684adfc5217SJeff Kirsher 2685adfc5217SJeff Kirsher return rc; 2686adfc5217SJeff Kirsher } 2687adfc5217SJeff Kirsher 2688adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2689adfc5217SJeff Kirsher { 2690adfc5217SJeff Kirsher int rc = 0, res; 2691adfc5217SJeff Kirsher 2692adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2693adfc5217SJeff Kirsher return rc; 2694adfc5217SJeff Kirsher 2695adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2696adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2697adfc5217SJeff Kirsher 2698adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2699adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2700adfc5217SJeff Kirsher 2701adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2702adfc5217SJeff Kirsher if (res) { 270351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2704adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2705adfc5217SJeff Kirsher } 2706adfc5217SJeff Kirsher 2707adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2708adfc5217SJeff Kirsher if (res) { 270951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2710adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2711adfc5217SJeff Kirsher } 2712adfc5217SJeff Kirsher 2713adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2714adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2715adfc5217SJeff Kirsher 2716adfc5217SJeff Kirsher return rc; 2717adfc5217SJeff Kirsher } 2718adfc5217SJeff Kirsher 27198970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 27208970b2e4SMerav Sicron { 27218970b2e4SMerav Sicron int rc; 27228970b2e4SMerav Sicron u8 is_serdes = 27238970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 27248970b2e4SMerav Sicron 27258970b2e4SMerav Sicron if (BP_NOMCP(bp)) 27268970b2e4SMerav Sicron return -ENODEV; 27278970b2e4SMerav Sicron 27288970b2e4SMerav Sicron if (!netif_running(bp->dev)) 27298970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 27308970b2e4SMerav Sicron 27315d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 27328970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 27338970b2e4SMerav Sicron if (rc) { 27348970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27358970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 27368970b2e4SMerav Sicron return -ENODEV; 27378970b2e4SMerav Sicron } 27388970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 27398970b2e4SMerav Sicron 27408970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 27418970b2e4SMerav Sicron 27428970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 27438970b2e4SMerav Sicron if (rc) 27448970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 27458970b2e4SMerav Sicron 27468970b2e4SMerav Sicron bnx2x_netif_start(bp); 27478970b2e4SMerav Sicron 27488970b2e4SMerav Sicron return rc; 27498970b2e4SMerav Sicron } 27508970b2e4SMerav Sicron 2751edb944d2SDmitry Kravkov struct code_entry { 2752edb944d2SDmitry Kravkov u32 sram_start_addr; 2753edb944d2SDmitry Kravkov u32 code_attribute; 2754edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_MASK 0xf0800003 2755edb944d2SDmitry Kravkov #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2756edb944d2SDmitry Kravkov #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2757edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2758edb944d2SDmitry Kravkov u32 nvm_start_addr; 2759edb944d2SDmitry Kravkov }; 2760edb944d2SDmitry Kravkov 2761edb944d2SDmitry Kravkov #define CODE_ENTRY_MAX 16 2762edb944d2SDmitry Kravkov #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2763edb944d2SDmitry Kravkov #define MAX_IMAGES_IN_EXTENDED_DIR 64 2764edb944d2SDmitry Kravkov #define NVRAM_DIR_OFFSET 0x14 2765edb944d2SDmitry Kravkov 2766edb944d2SDmitry Kravkov #define EXTENDED_DIR_EXISTS(code) \ 2767edb944d2SDmitry Kravkov ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2768edb944d2SDmitry Kravkov (code & CODE_IMAGE_LENGTH_MASK) != 0) 2769edb944d2SDmitry Kravkov 2770adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2771edb944d2SDmitry Kravkov #define CRC_BUFF_SIZE 256 2772edb944d2SDmitry Kravkov 2773edb944d2SDmitry Kravkov static int bnx2x_nvram_crc(struct bnx2x *bp, 2774edb944d2SDmitry Kravkov int offset, 2775edb944d2SDmitry Kravkov int size, 2776edb944d2SDmitry Kravkov u8 *buff) 2777edb944d2SDmitry Kravkov { 2778edb944d2SDmitry Kravkov u32 crc = ~0; 2779edb944d2SDmitry Kravkov int rc = 0, done = 0; 2780edb944d2SDmitry Kravkov 2781edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2782edb944d2SDmitry Kravkov "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2783edb944d2SDmitry Kravkov 2784edb944d2SDmitry Kravkov while (done < size) { 2785edb944d2SDmitry Kravkov int count = min_t(int, size - done, CRC_BUFF_SIZE); 2786edb944d2SDmitry Kravkov 2787edb944d2SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2788edb944d2SDmitry Kravkov 2789edb944d2SDmitry Kravkov if (rc) 2790edb944d2SDmitry Kravkov return rc; 2791edb944d2SDmitry Kravkov 2792edb944d2SDmitry Kravkov crc = crc32_le(crc, buff, count); 2793edb944d2SDmitry Kravkov done += count; 2794edb944d2SDmitry Kravkov } 2795edb944d2SDmitry Kravkov 2796edb944d2SDmitry Kravkov if (crc != CRC32_RESIDUAL) 2797edb944d2SDmitry Kravkov rc = -EINVAL; 2798edb944d2SDmitry Kravkov 2799edb944d2SDmitry Kravkov return rc; 2800edb944d2SDmitry Kravkov } 2801edb944d2SDmitry Kravkov 2802edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2803edb944d2SDmitry Kravkov struct code_entry *entry, 2804edb944d2SDmitry Kravkov u8 *buff) 2805edb944d2SDmitry Kravkov { 2806edb944d2SDmitry Kravkov size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2807edb944d2SDmitry Kravkov u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2808edb944d2SDmitry Kravkov int rc; 2809edb944d2SDmitry Kravkov 2810edb944d2SDmitry Kravkov /* Zero-length images and AFEX profiles do not have CRC */ 2811edb944d2SDmitry Kravkov if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2812edb944d2SDmitry Kravkov return 0; 2813edb944d2SDmitry Kravkov 2814edb944d2SDmitry Kravkov rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2815edb944d2SDmitry Kravkov if (rc) 2816edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2817edb944d2SDmitry Kravkov "image %x has failed crc test (rc %d)\n", type, rc); 2818edb944d2SDmitry Kravkov 2819edb944d2SDmitry Kravkov return rc; 2820edb944d2SDmitry Kravkov } 2821edb944d2SDmitry Kravkov 2822edb944d2SDmitry Kravkov static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2823edb944d2SDmitry Kravkov { 2824edb944d2SDmitry Kravkov int rc; 2825edb944d2SDmitry Kravkov struct code_entry entry; 2826edb944d2SDmitry Kravkov 2827edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2828edb944d2SDmitry Kravkov if (rc) 2829edb944d2SDmitry Kravkov return rc; 2830edb944d2SDmitry Kravkov 2831edb944d2SDmitry Kravkov return bnx2x_test_nvram_dir(bp, &entry, buff); 2832edb944d2SDmitry Kravkov } 2833edb944d2SDmitry Kravkov 2834edb944d2SDmitry Kravkov static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2835edb944d2SDmitry Kravkov { 2836edb944d2SDmitry Kravkov u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2837edb944d2SDmitry Kravkov struct code_entry entry; 2838edb944d2SDmitry Kravkov int i; 2839edb944d2SDmitry Kravkov 2840edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 2841edb944d2SDmitry Kravkov dir_offset + 2842edb944d2SDmitry Kravkov sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2843edb944d2SDmitry Kravkov (u32 *)&entry, sizeof(entry)); 2844edb944d2SDmitry Kravkov if (rc) 2845edb944d2SDmitry Kravkov return rc; 2846edb944d2SDmitry Kravkov 2847edb944d2SDmitry Kravkov if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2848edb944d2SDmitry Kravkov return 0; 2849edb944d2SDmitry Kravkov 2850edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2851edb944d2SDmitry Kravkov &cnt, sizeof(u32)); 2852edb944d2SDmitry Kravkov if (rc) 2853edb944d2SDmitry Kravkov return rc; 2854edb944d2SDmitry Kravkov 2855edb944d2SDmitry Kravkov dir_offset = entry.nvm_start_addr + 8; 2856edb944d2SDmitry Kravkov 2857edb944d2SDmitry Kravkov for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2858edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2859edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2860edb944d2SDmitry Kravkov buff); 2861edb944d2SDmitry Kravkov if (rc) 2862edb944d2SDmitry Kravkov return rc; 2863edb944d2SDmitry Kravkov } 2864edb944d2SDmitry Kravkov 2865edb944d2SDmitry Kravkov return 0; 2866edb944d2SDmitry Kravkov } 2867edb944d2SDmitry Kravkov 2868edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2869edb944d2SDmitry Kravkov { 2870edb944d2SDmitry Kravkov u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2871edb944d2SDmitry Kravkov int i; 2872edb944d2SDmitry Kravkov 2873edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2874edb944d2SDmitry Kravkov 2875edb944d2SDmitry Kravkov for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2876edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2877edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2878edb944d2SDmitry Kravkov buff); 2879edb944d2SDmitry Kravkov if (rc) 2880edb944d2SDmitry Kravkov return rc; 2881edb944d2SDmitry Kravkov } 2882edb944d2SDmitry Kravkov 2883edb944d2SDmitry Kravkov return bnx2x_test_nvram_ext_dirs(bp, buff); 2884edb944d2SDmitry Kravkov } 2885edb944d2SDmitry Kravkov 2886edb944d2SDmitry Kravkov struct crc_pair { 2887edb944d2SDmitry Kravkov int offset; 2888edb944d2SDmitry Kravkov int size; 2889edb944d2SDmitry Kravkov }; 2890edb944d2SDmitry Kravkov 2891edb944d2SDmitry Kravkov static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2892edb944d2SDmitry Kravkov const struct crc_pair *nvram_tbl, u8 *buf) 2893edb944d2SDmitry Kravkov { 2894edb944d2SDmitry Kravkov int i; 2895edb944d2SDmitry Kravkov 2896edb944d2SDmitry Kravkov for (i = 0; nvram_tbl[i].size; i++) { 2897edb944d2SDmitry Kravkov int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2898edb944d2SDmitry Kravkov nvram_tbl[i].size, buf); 2899edb944d2SDmitry Kravkov if (rc) { 2900edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2901edb944d2SDmitry Kravkov "nvram_tbl[%d] has failed crc test (rc %d)\n", 2902edb944d2SDmitry Kravkov i, rc); 2903edb944d2SDmitry Kravkov return rc; 2904edb944d2SDmitry Kravkov } 2905edb944d2SDmitry Kravkov } 2906edb944d2SDmitry Kravkov 2907edb944d2SDmitry Kravkov return 0; 2908edb944d2SDmitry Kravkov } 2909adfc5217SJeff Kirsher 2910adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2911adfc5217SJeff Kirsher { 291222c60891SColin Ian King static const struct crc_pair nvram_tbl[] = { 2913adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2914adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2915adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2916adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2917adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2918adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2919adfc5217SJeff Kirsher { 0, 0 } 2920adfc5217SJeff Kirsher }; 292122c60891SColin Ian King static const struct crc_pair nvram_tbl2[] = { 2922edb944d2SDmitry Kravkov { 0x7e8, 0x350 }, /* manuf_info2 */ 2923edb944d2SDmitry Kravkov { 0xb38, 0xf0 }, /* feature_info */ 2924edb944d2SDmitry Kravkov { 0, 0 } 2925edb944d2SDmitry Kravkov }; 2926edb944d2SDmitry Kravkov 292785640952SDmitry Kravkov u8 *buf; 2928edb944d2SDmitry Kravkov int rc; 2929edb944d2SDmitry Kravkov u32 magic; 2930adfc5217SJeff Kirsher 2931adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2932adfc5217SJeff Kirsher return 0; 2933adfc5217SJeff Kirsher 2934edb944d2SDmitry Kravkov buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2935afa13b4bSMintz Yuval if (!buf) { 293651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2937afa13b4bSMintz Yuval rc = -ENOMEM; 2938afa13b4bSMintz Yuval goto test_nvram_exit; 2939afa13b4bSMintz Yuval } 2940afa13b4bSMintz Yuval 294185640952SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2942adfc5217SJeff Kirsher if (rc) { 294351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 294451c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2945adfc5217SJeff Kirsher goto test_nvram_exit; 2946adfc5217SJeff Kirsher } 2947adfc5217SJeff Kirsher 2948adfc5217SJeff Kirsher if (magic != 0x669955aa) { 294951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 295051c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2951adfc5217SJeff Kirsher rc = -ENODEV; 2952adfc5217SJeff Kirsher goto test_nvram_exit; 2953adfc5217SJeff Kirsher } 2954adfc5217SJeff Kirsher 2955edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2956edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2957edb944d2SDmitry Kravkov if (rc) 2958adfc5217SJeff Kirsher goto test_nvram_exit; 2959adfc5217SJeff Kirsher 2960edb944d2SDmitry Kravkov if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2961edb944d2SDmitry Kravkov u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2962edb944d2SDmitry Kravkov SHARED_HW_CFG_HIDE_PORT1; 2963edb944d2SDmitry Kravkov 2964edb944d2SDmitry Kravkov if (!hide) { 296551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2966edb944d2SDmitry Kravkov "Port 1 CRC test-set\n"); 2967edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2968edb944d2SDmitry Kravkov if (rc) 2969adfc5217SJeff Kirsher goto test_nvram_exit; 2970adfc5217SJeff Kirsher } 2971adfc5217SJeff Kirsher } 2972adfc5217SJeff Kirsher 2973edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_dirs(bp, buf); 2974edb944d2SDmitry Kravkov 2975adfc5217SJeff Kirsher test_nvram_exit: 2976afa13b4bSMintz Yuval kfree(buf); 2977adfc5217SJeff Kirsher return rc; 2978adfc5217SJeff Kirsher } 2979adfc5217SJeff Kirsher 2980adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2981adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2982adfc5217SJeff Kirsher { 29833b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2984adfc5217SJeff Kirsher 298551c1a580SMerav Sicron if (!netif_running(bp->dev)) { 298651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 298751c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2988adfc5217SJeff Kirsher return -ENODEV; 298951c1a580SMerav Sicron } 2990adfc5217SJeff Kirsher 299115192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2992adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2993adfc5217SJeff Kirsher 2994adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2995adfc5217SJeff Kirsher 2996adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2997adfc5217SJeff Kirsher } 2998adfc5217SJeff Kirsher 2999adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 3000adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 3001adfc5217SJeff Kirsher { 3002adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3003a336ca7cSYaniv Rosner u8 is_serdes, link_up; 3004a336ca7cSYaniv Rosner int rc, cnt = 0; 3005cf2c1df6SMerav Sicron 3006909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 3007909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, 3008909d9faaSYuval Mintz "VFs are enabled, can not perform self test\n"); 3009909d9faaSYuval Mintz return; 3010909d9faaSYuval Mintz } 3011909d9faaSYuval Mintz 3012adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 301351c1a580SMerav Sicron netdev_err(bp->dev, 301451c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 3015adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3016adfc5217SJeff Kirsher return; 3017adfc5217SJeff Kirsher } 30182de67439SYuval Mintz 30198970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 30208970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 30218970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 30228970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 3023adfc5217SJeff Kirsher 3024cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 3025adfc5217SJeff Kirsher 3026bd8e012bSYuval Mintz if (bnx2x_test_nvram(bp) != 0) { 3027bd8e012bSYuval Mintz if (!IS_MF(bp)) 3028bd8e012bSYuval Mintz buf[4] = 1; 3029bd8e012bSYuval Mintz else 3030bd8e012bSYuval Mintz buf[0] = 1; 3031bd8e012bSYuval Mintz etest->flags |= ETH_TEST_FL_FAILED; 3032bd8e012bSYuval Mintz } 3033bd8e012bSYuval Mintz 3034cf2c1df6SMerav Sicron if (!netif_running(dev)) { 3035bd8e012bSYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 3036adfc5217SJeff Kirsher return; 3037cf2c1df6SMerav Sicron } 3038adfc5217SJeff Kirsher 3039adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 3040a336ca7cSYaniv Rosner link_up = bp->link_vars.link_up; 3041cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 3042cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 3043adfc5217SJeff Kirsher int port = BP_PORT(bp); 3044adfc5217SJeff Kirsher u32 val; 3045adfc5217SJeff Kirsher 3046adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 3047adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 3048adfc5217SJeff Kirsher /* disable input for TX port IF */ 3049adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 3050adfc5217SJeff Kirsher 30515d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3052cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 3053cf2c1df6SMerav Sicron if (rc) { 3054cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 3055cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 3056cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 3057cf2c1df6SMerav Sicron return; 3058cf2c1df6SMerav Sicron } 3059cf2c1df6SMerav Sicron 3060adfc5217SJeff Kirsher /* wait until link state is restored */ 3061adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 3062adfc5217SJeff Kirsher 3063adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 3064adfc5217SJeff Kirsher buf[0] = 1; 3065adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3066adfc5217SJeff Kirsher } 3067adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 3068adfc5217SJeff Kirsher buf[1] = 1; 3069adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3070adfc5217SJeff Kirsher } 3071adfc5217SJeff Kirsher 30728970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3073adfc5217SJeff Kirsher if (buf[2] != 0) 3074adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3075adfc5217SJeff Kirsher 30768970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 30778970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 30788970b2e4SMerav Sicron if (buf[3] != 0) 30798970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 30808970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 30818970b2e4SMerav Sicron } 30828970b2e4SMerav Sicron 30835d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3084adfc5217SJeff Kirsher 3085adfc5217SJeff Kirsher /* restore input for TX port IF */ 3086adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3087cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3088cf2c1df6SMerav Sicron if (rc) { 3089cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 3090cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 3091cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 3092cf2c1df6SMerav Sicron return; 3093cf2c1df6SMerav Sicron } 3094adfc5217SJeff Kirsher /* wait until link state is restored */ 3095adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 3096adfc5217SJeff Kirsher } 3097bd8e012bSYuval Mintz 3098adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 3099cf2c1df6SMerav Sicron if (!IS_MF(bp)) 31008970b2e4SMerav Sicron buf[5] = 1; 3101cf2c1df6SMerav Sicron else 3102cf2c1df6SMerav Sicron buf[1] = 1; 3103adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3104adfc5217SJeff Kirsher } 3105adfc5217SJeff Kirsher 3106a336ca7cSYaniv Rosner if (link_up) { 3107a336ca7cSYaniv Rosner cnt = 100; 3108a336ca7cSYaniv Rosner while (bnx2x_link_test(bp, is_serdes) && --cnt) 3109a336ca7cSYaniv Rosner msleep(20); 3110a336ca7cSYaniv Rosner } 3111a336ca7cSYaniv Rosner 3112a336ca7cSYaniv Rosner if (!cnt) { 3113cf2c1df6SMerav Sicron if (!IS_MF(bp)) 31148970b2e4SMerav Sicron buf[6] = 1; 3115cf2c1df6SMerav Sicron else 3116cf2c1df6SMerav Sicron buf[2] = 1; 3117adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3118adfc5217SJeff Kirsher } 3119adfc5217SJeff Kirsher } 3120adfc5217SJeff Kirsher 312144c33c66SMichal Schmidt #define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat) 31223fb2d492SYuval Mintz #define HIDE_PORT_STAT(bp) IS_VF(bp) 3123adfc5217SJeff Kirsher 3124adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 3125adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 3126adfc5217SJeff Kirsher */ 31271191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 3128adfc5217SJeff Kirsher { 3129adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 3130adfc5217SJeff Kirsher } 3131adfc5217SJeff Kirsher 3132adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3133adfc5217SJeff Kirsher { 3134adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 31353521b419SYuval Mintz int i, num_strings = 0; 3136adfc5217SJeff Kirsher 3137adfc5217SJeff Kirsher switch (stringset) { 3138adfc5217SJeff Kirsher case ETH_SS_STATS: 3139adfc5217SJeff Kirsher if (is_multi(bp)) { 31403521b419SYuval Mintz num_strings = bnx2x_num_stat_queues(bp) * 3141adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 3142d5e83632SYuval Mintz } else 31433521b419SYuval Mintz num_strings = 0; 3144d8361051SYuval Mintz if (HIDE_PORT_STAT(bp)) { 3145adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 314644c33c66SMichal Schmidt if (!IS_PORT_STAT(i)) 31473521b419SYuval Mintz num_strings++; 3148adfc5217SJeff Kirsher } else 31493521b419SYuval Mintz num_strings += BNX2X_NUM_STATS; 3150d5e83632SYuval Mintz 31513521b419SYuval Mintz return num_strings; 3152adfc5217SJeff Kirsher 3153adfc5217SJeff Kirsher case ETH_SS_TEST: 3154cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 3155adfc5217SJeff Kirsher 31563521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 31573521b419SYuval Mintz return BNX2X_PRI_FLAG_LEN; 31583521b419SYuval Mintz 3159adfc5217SJeff Kirsher default: 3160adfc5217SJeff Kirsher return -EINVAL; 3161adfc5217SJeff Kirsher } 3162adfc5217SJeff Kirsher } 3163adfc5217SJeff Kirsher 31643521b419SYuval Mintz static u32 bnx2x_get_private_flags(struct net_device *dev) 31653521b419SYuval Mintz { 31663521b419SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 31673521b419SYuval Mintz u32 flags = 0; 31683521b419SYuval Mintz 31693521b419SYuval Mintz flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 31703521b419SYuval Mintz flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 31713521b419SYuval Mintz flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 31723521b419SYuval Mintz 31733521b419SYuval Mintz return flags; 31743521b419SYuval Mintz } 31753521b419SYuval Mintz 3176adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3177adfc5217SJeff Kirsher { 3178adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 31795889335cSMerav Sicron int i, j, k, start; 3180adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 3181adfc5217SJeff Kirsher 3182adfc5217SJeff Kirsher switch (stringset) { 3183adfc5217SJeff Kirsher case ETH_SS_STATS: 3184adfc5217SJeff Kirsher k = 0; 3185d5e83632SYuval Mintz if (is_multi(bp)) { 3186adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 3187adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 3188be9cdf1bSArnd Bergmann snprintf(queue_name, sizeof(queue_name), 3189be9cdf1bSArnd Bergmann "%d", i); 3190adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3191adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3192adfc5217SJeff Kirsher ETH_GSTRING_LEN, 3193adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 3194adfc5217SJeff Kirsher queue_name); 3195adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3196adfc5217SJeff Kirsher } 3197d5e83632SYuval Mintz } 3198d5e83632SYuval Mintz 3199adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3200d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3201adfc5217SJeff Kirsher continue; 3202d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3203adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 3204adfc5217SJeff Kirsher j++; 3205adfc5217SJeff Kirsher } 3206d5e83632SYuval Mintz 3207adfc5217SJeff Kirsher break; 3208adfc5217SJeff Kirsher 3209adfc5217SJeff Kirsher case ETH_SS_TEST: 3210cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 3211cf2c1df6SMerav Sicron if (!IS_MF(bp)) 3212cf2c1df6SMerav Sicron start = 0; 3213cf2c1df6SMerav Sicron else 3214cf2c1df6SMerav Sicron start = 4; 32155889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 32165889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 32173521b419SYuval Mintz break; 32183521b419SYuval Mintz 32193521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 32203521b419SYuval Mintz memcpy(buf, bnx2x_private_arr, 32213521b419SYuval Mintz ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 32223521b419SYuval Mintz break; 3223adfc5217SJeff Kirsher } 3224adfc5217SJeff Kirsher } 3225adfc5217SJeff Kirsher 3226adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 3227adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 3228adfc5217SJeff Kirsher { 3229adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3230adfc5217SJeff Kirsher u32 *hw_stats, *offset; 3231d5e83632SYuval Mintz int i, j, k = 0; 3232adfc5217SJeff Kirsher 3233adfc5217SJeff Kirsher if (is_multi(bp)) { 3234adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 323515192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3236adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3237adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 3238adfc5217SJeff Kirsher /* skip this counter */ 3239adfc5217SJeff Kirsher buf[k + j] = 0; 3240adfc5217SJeff Kirsher continue; 3241adfc5217SJeff Kirsher } 3242adfc5217SJeff Kirsher offset = (hw_stats + 3243adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 3244adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 3245adfc5217SJeff Kirsher /* 4-byte counter */ 3246adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 3247adfc5217SJeff Kirsher continue; 3248adfc5217SJeff Kirsher } 3249adfc5217SJeff Kirsher /* 8-byte counter */ 3250adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3251adfc5217SJeff Kirsher } 3252adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3253adfc5217SJeff Kirsher } 3254adfc5217SJeff Kirsher } 3255d5e83632SYuval Mintz 3256adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 3257adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3258d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3259adfc5217SJeff Kirsher continue; 3260adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 3261adfc5217SJeff Kirsher /* skip this counter */ 3262d5e83632SYuval Mintz buf[k + j] = 0; 3263adfc5217SJeff Kirsher j++; 3264adfc5217SJeff Kirsher continue; 3265adfc5217SJeff Kirsher } 3266adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 3267adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 3268adfc5217SJeff Kirsher /* 4-byte counter */ 3269d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 3270adfc5217SJeff Kirsher j++; 3271adfc5217SJeff Kirsher continue; 3272adfc5217SJeff Kirsher } 3273adfc5217SJeff Kirsher /* 8-byte counter */ 3274d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3275adfc5217SJeff Kirsher j++; 3276adfc5217SJeff Kirsher } 3277adfc5217SJeff Kirsher } 3278adfc5217SJeff Kirsher 3279adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 3280adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 3281adfc5217SJeff Kirsher { 3282adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3283adfc5217SJeff Kirsher 32843fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 328551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 328651c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 3287adfc5217SJeff Kirsher return -EAGAIN; 328851c1a580SMerav Sicron } 3289adfc5217SJeff Kirsher 3290adfc5217SJeff Kirsher switch (state) { 3291adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 3292adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 3293adfc5217SJeff Kirsher 3294adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 32958203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3296adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3297adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 32988203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3299adfc5217SJeff Kirsher break; 3300adfc5217SJeff Kirsher 3301adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 33028203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3303adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3304adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 33058203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3306adfc5217SJeff Kirsher break; 3307adfc5217SJeff Kirsher 3308adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 33098203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3310adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3311adfc5217SJeff Kirsher LED_MODE_OPER, 3312adfc5217SJeff Kirsher bp->link_vars.line_speed); 33138203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3314adfc5217SJeff Kirsher } 3315adfc5217SJeff Kirsher 3316adfc5217SJeff Kirsher return 0; 3317adfc5217SJeff Kirsher } 3318adfc5217SJeff Kirsher 33195d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 33205d317c6aSMerav Sicron { 33215d317c6aSMerav Sicron switch (info->flow_type) { 33225d317c6aSMerav Sicron case TCP_V4_FLOW: 33235d317c6aSMerav Sicron case TCP_V6_FLOW: 33245d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 33255d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 33265d317c6aSMerav Sicron break; 33275d317c6aSMerav Sicron case UDP_V4_FLOW: 33285d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 33295d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 33305d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 33315d317c6aSMerav Sicron else 33325d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 33335d317c6aSMerav Sicron break; 33345d317c6aSMerav Sicron case UDP_V6_FLOW: 33355d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 33365d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 33375d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 33385d317c6aSMerav Sicron else 33395d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 33405d317c6aSMerav Sicron break; 33415d317c6aSMerav Sicron case IPV4_FLOW: 33425d317c6aSMerav Sicron case IPV6_FLOW: 33435d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 33445d317c6aSMerav Sicron break; 33455d317c6aSMerav Sicron default: 33465d317c6aSMerav Sicron info->data = 0; 33475d317c6aSMerav Sicron break; 33485d317c6aSMerav Sicron } 33495d317c6aSMerav Sicron 33505d317c6aSMerav Sicron return 0; 33515d317c6aSMerav Sicron } 33525d317c6aSMerav Sicron 3353adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3354815c7db5SBen Hutchings u32 *rules __always_unused) 3355adfc5217SJeff Kirsher { 3356adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3357adfc5217SJeff Kirsher 3358adfc5217SJeff Kirsher switch (info->cmd) { 3359adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 3360adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 3361adfc5217SJeff Kirsher return 0; 33625d317c6aSMerav Sicron case ETHTOOL_GRXFH: 33635d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 33645d317c6aSMerav Sicron default: 33655d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 33665d317c6aSMerav Sicron return -EOPNOTSUPP; 33675d317c6aSMerav Sicron } 33685d317c6aSMerav Sicron } 3369adfc5217SJeff Kirsher 33705d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 33715d317c6aSMerav Sicron { 33725d317c6aSMerav Sicron int udp_rss_requested; 33735d317c6aSMerav Sicron 33745d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33755d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 33765d317c6aSMerav Sicron info->flow_type, info->data); 33775d317c6aSMerav Sicron 33785d317c6aSMerav Sicron switch (info->flow_type) { 33795d317c6aSMerav Sicron case TCP_V4_FLOW: 33805d317c6aSMerav Sicron case TCP_V6_FLOW: 33815d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 33825d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 33835d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 33845d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33855d317c6aSMerav Sicron "Command parameters not supported\n"); 33865d317c6aSMerav Sicron return -EINVAL; 33875d317c6aSMerav Sicron } 33882de67439SYuval Mintz return 0; 33895d317c6aSMerav Sicron 33905d317c6aSMerav Sicron case UDP_V4_FLOW: 33915d317c6aSMerav Sicron case UDP_V6_FLOW: 33925d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 33935d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 33945d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 33955d317c6aSMerav Sicron udp_rss_requested = 1; 33965d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 33975d317c6aSMerav Sicron udp_rss_requested = 0; 33985d317c6aSMerav Sicron else 33995d317c6aSMerav Sicron return -EINVAL; 3400f9468e8dSYuval Mintz 3401f9468e8dSYuval Mintz if (CHIP_IS_E1x(bp) && udp_rss_requested) { 3402f9468e8dSYuval Mintz DP(BNX2X_MSG_ETHTOOL, 3403f9468e8dSYuval Mintz "57710, 57711 boards don't support RSS according to UDP 4-tuple\n"); 3404f9468e8dSYuval Mintz return -EINVAL; 3405f9468e8dSYuval Mintz } 3406f9468e8dSYuval Mintz 34075d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 34085d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 34095d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 34105d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34115d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 34125d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 3413ae2dcb28SSudarsana Reddy Kalluru if (bp->state == BNX2X_STATE_OPEN) 3414ae2dcb28SSudarsana Reddy Kalluru return bnx2x_rss(bp, &bp->rss_conf_obj, false, 3415ae2dcb28SSudarsana Reddy Kalluru true); 34165d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 34175d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 34185d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 34195d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34205d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 34215d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 3422ae2dcb28SSudarsana Reddy Kalluru if (bp->state == BNX2X_STATE_OPEN) 3423ae2dcb28SSudarsana Reddy Kalluru return bnx2x_rss(bp, &bp->rss_conf_obj, false, 3424ae2dcb28SSudarsana Reddy Kalluru true); 34255d317c6aSMerav Sicron } 3426924d75abSYuval Mintz return 0; 3427924d75abSYuval Mintz 34285d317c6aSMerav Sicron case IPV4_FLOW: 34295d317c6aSMerav Sicron case IPV6_FLOW: 34305d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 34315d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 34325d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34335d317c6aSMerav Sicron "Command parameters not supported\n"); 34345d317c6aSMerav Sicron return -EINVAL; 34355d317c6aSMerav Sicron } 3436924d75abSYuval Mintz return 0; 3437924d75abSYuval Mintz 34385d317c6aSMerav Sicron case SCTP_V4_FLOW: 34395d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 34405d317c6aSMerav Sicron case AH_V4_FLOW: 34415d317c6aSMerav Sicron case ESP_V4_FLOW: 34425d317c6aSMerav Sicron case SCTP_V6_FLOW: 34435d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 34445d317c6aSMerav Sicron case AH_V6_FLOW: 34455d317c6aSMerav Sicron case ESP_V6_FLOW: 34465d317c6aSMerav Sicron case IP_USER_FLOW: 34475d317c6aSMerav Sicron case ETHER_FLOW: 34485d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 34495d317c6aSMerav Sicron if (info->data) { 34505d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34515d317c6aSMerav Sicron "Command parameters not supported\n"); 34525d317c6aSMerav Sicron return -EINVAL; 34535d317c6aSMerav Sicron } 3454924d75abSYuval Mintz return 0; 3455924d75abSYuval Mintz 34565d317c6aSMerav Sicron default: 34575d317c6aSMerav Sicron return -EINVAL; 34585d317c6aSMerav Sicron } 34595d317c6aSMerav Sicron } 34605d317c6aSMerav Sicron 34615d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 34625d317c6aSMerav Sicron { 34635d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34645d317c6aSMerav Sicron 34655d317c6aSMerav Sicron switch (info->cmd) { 34665d317c6aSMerav Sicron case ETHTOOL_SRXFH: 34675d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 3468adfc5217SJeff Kirsher default: 346951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3470adfc5217SJeff Kirsher return -EOPNOTSUPP; 3471adfc5217SJeff Kirsher } 3472adfc5217SJeff Kirsher } 3473adfc5217SJeff Kirsher 34747850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3475adfc5217SJeff Kirsher { 347696305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 34777850f63fSBen Hutchings } 34787850f63fSBen Hutchings 3479892311f6SEyal Perry static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3480892311f6SEyal Perry u8 *hfunc) 34817850f63fSBen Hutchings { 34827850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 3483adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3484adfc5217SJeff Kirsher size_t i; 3485adfc5217SJeff Kirsher 3486892311f6SEyal Perry if (hfunc) 3487892311f6SEyal Perry *hfunc = ETH_RSS_HASH_TOP; 3488892311f6SEyal Perry if (!indir) 3489892311f6SEyal Perry return 0; 3490892311f6SEyal Perry 3491adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 3492adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3493adfc5217SJeff Kirsher 3494adfc5217SJeff Kirsher /* 3495adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 3496adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 3497adfc5217SJeff Kirsher * points to an array of u32. 3498adfc5217SJeff Kirsher * 3499adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3500adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 3501adfc5217SJeff Kirsher * queue. 3502adfc5217SJeff Kirsher */ 35037850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 35047850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 3505adfc5217SJeff Kirsher 3506adfc5217SJeff Kirsher return 0; 3507adfc5217SJeff Kirsher } 3508adfc5217SJeff Kirsher 3509fe62d001SBen Hutchings static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3510892311f6SEyal Perry const u8 *key, const u8 hfunc) 3511adfc5217SJeff Kirsher { 3512adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3513adfc5217SJeff Kirsher size_t i; 3514adfc5217SJeff Kirsher 3515892311f6SEyal Perry /* We require at least one supported parameter to be changed and no 3516892311f6SEyal Perry * change in any of the unsupported parameters 3517892311f6SEyal Perry */ 3518892311f6SEyal Perry if (key || 3519892311f6SEyal Perry (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3520892311f6SEyal Perry return -EOPNOTSUPP; 3521892311f6SEyal Perry 3522892311f6SEyal Perry if (!indir) 3523892311f6SEyal Perry return 0; 3524892311f6SEyal Perry 3525adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3526adfc5217SJeff Kirsher /* 3527fe62d001SBen Hutchings * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3528adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 3529adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 3530adfc5217SJeff Kirsher * 3531adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3532adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 3533adfc5217SJeff Kirsher * queue 3534adfc5217SJeff Kirsher */ 35355d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3536adfc5217SJeff Kirsher } 3537adfc5217SJeff Kirsher 3538ae2dcb28SSudarsana Reddy Kalluru if (bp->state == BNX2X_STATE_OPEN) 35395d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 3540ae2dcb28SSudarsana Reddy Kalluru 3541ae2dcb28SSudarsana Reddy Kalluru return 0; 3542adfc5217SJeff Kirsher } 3543adfc5217SJeff Kirsher 35440e8d2ec5SMerav Sicron /** 35450e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 35460e8d2ec5SMerav Sicron * 35470e8d2ec5SMerav Sicron * @dev: net device 35480e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 35490e8d2ec5SMerav Sicron */ 35500e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 35510e8d2ec5SMerav Sicron struct ethtool_channels *channels) 35520e8d2ec5SMerav Sicron { 35530e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 35540e8d2ec5SMerav Sicron 35550e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 35560e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 35570e8d2ec5SMerav Sicron } 35580e8d2ec5SMerav Sicron 35590e8d2ec5SMerav Sicron /** 35600e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 35610e8d2ec5SMerav Sicron * 35620e8d2ec5SMerav Sicron * @bp: bnx2x private structure 35630e8d2ec5SMerav Sicron * 35640e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 35650e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 35660e8d2ec5SMerav Sicron */ 35670e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 35680e8d2ec5SMerav Sicron { 35690e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 357055c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 357155c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 357255c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 35730e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 35740e8d2ec5SMerav Sicron } 35750e8d2ec5SMerav Sicron 35760e8d2ec5SMerav Sicron /** 35770e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 35780e8d2ec5SMerav Sicron * 35790e8d2ec5SMerav Sicron * @dev: net device 35800e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 35810e8d2ec5SMerav Sicron */ 35820e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 35830e8d2ec5SMerav Sicron struct ethtool_channels *channels) 35840e8d2ec5SMerav Sicron { 35850e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 35860e8d2ec5SMerav Sicron 35870e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 35880e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 35890e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 35900e8d2ec5SMerav Sicron channels->combined_count); 35910e8d2ec5SMerav Sicron 3592909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 3593909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3594909d9faaSYuval Mintz return -EPERM; 3595909d9faaSYuval Mintz } 3596909d9faaSYuval Mintz 35970e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 35980e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 35990e8d2ec5SMerav Sicron */ 36000e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 36010e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 36020e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 36030e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 36040e8d2ec5SMerav Sicron return -EINVAL; 36050e8d2ec5SMerav Sicron } 36060e8d2ec5SMerav Sicron 36070e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 36080e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 36090e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 36100e8d2ec5SMerav Sicron return 0; 36110e8d2ec5SMerav Sicron } 36120e8d2ec5SMerav Sicron 36130e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 36140e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 36150e8d2ec5SMerav Sicron * less than requested if memory is low. 36160e8d2ec5SMerav Sicron */ 36170e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 36180e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 36190e8d2ec5SMerav Sicron return 0; 36200e8d2ec5SMerav Sicron } 36215d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 36220e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 36230e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 36240e8d2ec5SMerav Sicron } 36250e8d2ec5SMerav Sicron 3626eeed018cSMichal Kalderon static int bnx2x_get_ts_info(struct net_device *dev, 3627eeed018cSMichal Kalderon struct ethtool_ts_info *info) 3628eeed018cSMichal Kalderon { 3629eeed018cSMichal Kalderon struct bnx2x *bp = netdev_priv(dev); 3630eeed018cSMichal Kalderon 3631eeed018cSMichal Kalderon if (bp->flags & PTP_SUPPORTED) { 3632eeed018cSMichal Kalderon info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3633eeed018cSMichal Kalderon SOF_TIMESTAMPING_RX_SOFTWARE | 3634eeed018cSMichal Kalderon SOF_TIMESTAMPING_SOFTWARE | 3635eeed018cSMichal Kalderon SOF_TIMESTAMPING_TX_HARDWARE | 3636eeed018cSMichal Kalderon SOF_TIMESTAMPING_RX_HARDWARE | 3637eeed018cSMichal Kalderon SOF_TIMESTAMPING_RAW_HARDWARE; 3638eeed018cSMichal Kalderon 3639eeed018cSMichal Kalderon if (bp->ptp_clock) 3640eeed018cSMichal Kalderon info->phc_index = ptp_clock_index(bp->ptp_clock); 3641eeed018cSMichal Kalderon else 3642eeed018cSMichal Kalderon info->phc_index = -1; 3643eeed018cSMichal Kalderon 3644eeed018cSMichal Kalderon info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3645eeed018cSMichal Kalderon (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3646eeed018cSMichal Kalderon (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3647dd3950c6SJacob Keller (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3648eeed018cSMichal Kalderon 3649eeed018cSMichal Kalderon info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3650eeed018cSMichal Kalderon 3651eeed018cSMichal Kalderon return 0; 3652eeed018cSMichal Kalderon } 3653eeed018cSMichal Kalderon 3654eeed018cSMichal Kalderon return ethtool_op_get_ts_info(dev, info); 3655eeed018cSMichal Kalderon } 3656eeed018cSMichal Kalderon 3657adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 3658adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 3659adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 3660adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 366107ba6af4SMiriam Shitrit .get_dump_flag = bnx2x_get_dump_flag, 366207ba6af4SMiriam Shitrit .get_dump_data = bnx2x_get_dump_data, 366307ba6af4SMiriam Shitrit .set_dump = bnx2x_set_dump, 3664adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 3665adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 3666adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 3667adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 3668adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 3669adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 3670adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 3671adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 3672adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 3673adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 3674adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 3675adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 3676adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 3677adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 3678adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 3679adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 3680adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 36813521b419SYuval Mintz .get_priv_flags = bnx2x_get_private_flags, 3682adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 3683adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 3684adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 3685adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 36865d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 36877850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3688fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3689fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 36900e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 36910e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 369224ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 369324ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3694e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3695e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3696eeed018cSMichal Kalderon .get_ts_info = bnx2x_get_ts_info, 36978b86b2c1SPhilippe Reynes .get_link_ksettings = bnx2x_get_link_ksettings, 36988b86b2c1SPhilippe Reynes .set_link_ksettings = bnx2x_set_link_ksettings, 3699adfc5217SJeff Kirsher }; 3700adfc5217SJeff Kirsher 3701005a07baSAriel Elior static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3702005a07baSAriel Elior .get_drvinfo = bnx2x_get_drvinfo, 3703005a07baSAriel Elior .get_msglevel = bnx2x_get_msglevel, 3704005a07baSAriel Elior .set_msglevel = bnx2x_set_msglevel, 3705005a07baSAriel Elior .get_link = bnx2x_get_link, 3706005a07baSAriel Elior .get_coalesce = bnx2x_get_coalesce, 3707005a07baSAriel Elior .get_ringparam = bnx2x_get_ringparam, 3708005a07baSAriel Elior .set_ringparam = bnx2x_set_ringparam, 3709005a07baSAriel Elior .get_sset_count = bnx2x_get_sset_count, 3710005a07baSAriel Elior .get_strings = bnx2x_get_strings, 3711005a07baSAriel Elior .get_ethtool_stats = bnx2x_get_ethtool_stats, 3712005a07baSAriel Elior .get_rxnfc = bnx2x_get_rxnfc, 3713005a07baSAriel Elior .set_rxnfc = bnx2x_set_rxnfc, 3714005a07baSAriel Elior .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3715fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3716fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 3717005a07baSAriel Elior .get_channels = bnx2x_get_channels, 3718005a07baSAriel Elior .set_channels = bnx2x_set_channels, 37198b86b2c1SPhilippe Reynes .get_link_ksettings = bnx2x_get_vf_link_ksettings, 3720005a07baSAriel Elior }; 3721005a07baSAriel Elior 3722005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3723adfc5217SJeff Kirsher { 37247ad24ea4SWilfried Klaebe netdev->ethtool_ops = (IS_PF(bp)) ? 37257ad24ea4SWilfried Klaebe &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3726adfc5217SJeff Kirsher } 3727