14ad79e13SYuval Mintz /* bnx2x_ethtool.c: QLogic Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 44ad79e13SYuval Mintz * Copyright (c) 2014 QLogic Corporation 54ad79e13SYuval Mintz * All rights reserved 6adfc5217SJeff Kirsher * 7adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 8adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 9adfc5217SJeff Kirsher * the Free Software Foundation. 10adfc5217SJeff Kirsher * 1108f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12adfc5217SJeff Kirsher * Written by: Eliezer Tamir 13adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 14adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 15adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 16adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19f1deab50SJoe Perches 20f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21f1deab50SJoe Perches 22adfc5217SJeff Kirsher #include <linux/ethtool.h> 23adfc5217SJeff Kirsher #include <linux/netdevice.h> 24adfc5217SJeff Kirsher #include <linux/types.h> 25adfc5217SJeff Kirsher #include <linux/sched.h> 26adfc5217SJeff Kirsher #include <linux/crc32.h> 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_dump.h" 30adfc5217SJeff Kirsher #include "bnx2x_init.h" 31adfc5217SJeff Kirsher 32adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 33adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35adfc5217SJeff Kirsher */ 36adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 37adfc5217SJeff Kirsher static const struct { 38adfc5217SJeff Kirsher long offset; 39adfc5217SJeff Kirsher int size; 40adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 41adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 42adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 49adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 51adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 55adfc5217SJeff Kirsher 56adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 65adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 67c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 70adfc5217SJeff Kirsher }; 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73adfc5217SJeff Kirsher 74adfc5217SJeff Kirsher static const struct { 75adfc5217SJeff Kirsher long offset; 76adfc5217SJeff Kirsher int size; 77adfc5217SJeff Kirsher u32 flags; 78adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 79adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 80adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 81adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 82adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 83adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 97adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 99adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 101adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 104adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 106adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 107adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 108adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 109adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 110adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1110e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1120e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1130e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1140e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 120adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 121adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 122adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 123adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 125adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 127adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 128adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 129adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 130adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 131adfc5217SJeff Kirsher 132adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 144adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 146adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 164adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 166adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 175adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 177adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 178adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1797a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1807a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1817a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1827a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1837a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 184c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 185c96bdc0cSDmitry Kravkov 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 186e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 187e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 188adfc5217SJeff Kirsher }; 189adfc5217SJeff Kirsher 190adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 19107ba6af4SMiriam Shitrit 192adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 193adfc5217SJeff Kirsher { 194adfc5217SJeff Kirsher int port_type; 195adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 196adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 197dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 198dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 199adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 200adfc5217SJeff Kirsher case ETH_PHY_KR: 201adfc5217SJeff Kirsher case ETH_PHY_CX4: 202adfc5217SJeff Kirsher port_type = PORT_FIBRE; 203adfc5217SJeff Kirsher break; 204adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 205adfc5217SJeff Kirsher port_type = PORT_DA; 206adfc5217SJeff Kirsher break; 207adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 208adfc5217SJeff Kirsher port_type = PORT_TP; 209adfc5217SJeff Kirsher break; 210adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 211adfc5217SJeff Kirsher port_type = PORT_NONE; 212adfc5217SJeff Kirsher break; 213adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 214adfc5217SJeff Kirsher default: 215adfc5217SJeff Kirsher port_type = PORT_OTHER; 216adfc5217SJeff Kirsher break; 217adfc5217SJeff Kirsher } 218adfc5217SJeff Kirsher return port_type; 219adfc5217SJeff Kirsher } 220adfc5217SJeff Kirsher 2216495d15aSDmitry Kravkov static int bnx2x_get_vf_settings(struct net_device *dev, 2226495d15aSDmitry Kravkov struct ethtool_cmd *cmd) 2236495d15aSDmitry Kravkov { 2246495d15aSDmitry Kravkov struct bnx2x *bp = netdev_priv(dev); 2256495d15aSDmitry Kravkov 2266495d15aSDmitry Kravkov if (bp->state == BNX2X_STATE_OPEN) { 2276495d15aSDmitry Kravkov if (test_bit(BNX2X_LINK_REPORT_FD, 2286495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags)) 2296495d15aSDmitry Kravkov cmd->duplex = DUPLEX_FULL; 2306495d15aSDmitry Kravkov else 2316495d15aSDmitry Kravkov cmd->duplex = DUPLEX_HALF; 2326495d15aSDmitry Kravkov 2336495d15aSDmitry Kravkov ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed); 2346495d15aSDmitry Kravkov } else { 2356495d15aSDmitry Kravkov cmd->duplex = DUPLEX_UNKNOWN; 2366495d15aSDmitry Kravkov ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 2376495d15aSDmitry Kravkov } 2386495d15aSDmitry Kravkov 2396495d15aSDmitry Kravkov cmd->port = PORT_OTHER; 2406495d15aSDmitry Kravkov cmd->phy_address = 0; 2416495d15aSDmitry Kravkov cmd->transceiver = XCVR_INTERNAL; 2426495d15aSDmitry Kravkov cmd->autoneg = AUTONEG_DISABLE; 2436495d15aSDmitry Kravkov cmd->maxtxpkt = 0; 2446495d15aSDmitry Kravkov cmd->maxrxpkt = 0; 2456495d15aSDmitry Kravkov 2466495d15aSDmitry Kravkov DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 2476495d15aSDmitry Kravkov " supported 0x%x advertising 0x%x speed %u\n" 2486495d15aSDmitry Kravkov " duplex %d port %d phy_address %d transceiver %d\n" 2496495d15aSDmitry Kravkov " autoneg %d maxtxpkt %d maxrxpkt %d\n", 2506495d15aSDmitry Kravkov cmd->cmd, cmd->supported, cmd->advertising, 2516495d15aSDmitry Kravkov ethtool_cmd_speed(cmd), 2526495d15aSDmitry Kravkov cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 2536495d15aSDmitry Kravkov cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 2546495d15aSDmitry Kravkov 2556495d15aSDmitry Kravkov return 0; 2566495d15aSDmitry Kravkov } 2576495d15aSDmitry Kravkov 258adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 259adfc5217SJeff Kirsher { 260adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 261adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2625d67c1c5SYuval Mintz u32 media_type; 263adfc5217SJeff Kirsher 264adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 265adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 266adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 267adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 268adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 2695d67c1c5SYuval Mintz media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 2705d67c1c5SYuval Mintz if (media_type == ETH_PHY_SFP_1G_FIBER) { 271dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 272dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 273dbef807eSYuval Mintz } 274adfc5217SJeff Kirsher 27559694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 27659694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 277adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 278adfc5217SJeff Kirsher 27938298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 280adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 28159694f00SYuval Mintz else 28259694f00SYuval Mintz ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 28338298461SYuval Mintz } else { 28438298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 28538298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 28638298461SYuval Mintz } 287adfc5217SJeff Kirsher 288adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 291adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 292adfc5217SJeff Kirsher 293adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 294adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 295adfc5217SJeff Kirsher else 296adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 297adfc5217SJeff Kirsher 2989e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2999e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3009e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 3019e7e8399SMintz Yuval 3029e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 3039e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 3049e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 3059e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 3069e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 3079e7e8399SMintz Yuval 3089e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 3099e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 3109e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 3119e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 3129e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 3139e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 3149e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 3159e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 3169e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 3179e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 3185d67c1c5SYuval Mintz if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 3195d67c1c5SYuval Mintz if (media_type == ETH_PHY_KR) { 3205d67c1c5SYuval Mintz cmd->lp_advertising |= 3215d67c1c5SYuval Mintz ADVERTISED_1000baseKX_Full; 3225d67c1c5SYuval Mintz } else { 3235d67c1c5SYuval Mintz cmd->lp_advertising |= 3245d67c1c5SYuval Mintz ADVERTISED_1000baseT_Full; 3255d67c1c5SYuval Mintz } 3265d67c1c5SYuval Mintz } 3279e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 3289e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 3295d67c1c5SYuval Mintz if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 3305d67c1c5SYuval Mintz if (media_type == ETH_PHY_KR) { 3315d67c1c5SYuval Mintz cmd->lp_advertising |= 3325d67c1c5SYuval Mintz ADVERTISED_10000baseKR_Full; 3335d67c1c5SYuval Mintz } else { 3345d67c1c5SYuval Mintz cmd->lp_advertising |= 3355d67c1c5SYuval Mintz ADVERTISED_10000baseT_Full; 3365d67c1c5SYuval Mintz } 3375d67c1c5SYuval Mintz } 338be94bea7SYaniv Rosner if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 339be94bea7SYaniv Rosner cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 3409e7e8399SMintz Yuval } 3419e7e8399SMintz Yuval 342adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 343adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 344adfc5217SJeff Kirsher 34551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 346f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 347f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 348f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 349adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 350adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 351adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 352adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 353adfc5217SJeff Kirsher 354adfc5217SJeff Kirsher return 0; 355adfc5217SJeff Kirsher } 356adfc5217SJeff Kirsher 357adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 358adfc5217SJeff Kirsher { 359adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 360adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 361dbef807eSYuval Mintz u32 speed, phy_idx; 362adfc5217SJeff Kirsher 363adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 364adfc5217SJeff Kirsher return 0; 365adfc5217SJeff Kirsher 36651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 367adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 368adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 369adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 370adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 371adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 372adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 373adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 374adfc5217SJeff Kirsher 375adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 376adfc5217SJeff Kirsher 37716a5fd92SYuval Mintz /* If received a request for an unknown duplex, assume full*/ 37838298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 37938298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 38038298461SYuval Mintz 381adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 382adfc5217SJeff Kirsher u32 part; 383adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 384adfc5217SJeff Kirsher 385adfc5217SJeff Kirsher /* use 10G if no link detected */ 386adfc5217SJeff Kirsher if (!line_speed) 387adfc5217SJeff Kirsher line_speed = 10000; 388adfc5217SJeff Kirsher 389adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 39051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 39151c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 392adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 393adfc5217SJeff Kirsher return -EINVAL; 394adfc5217SJeff Kirsher } 395adfc5217SJeff Kirsher 396adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 397adfc5217SJeff Kirsher 398adfc5217SJeff Kirsher if (line_speed < speed || !part) { 39951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 40051c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 401adfc5217SJeff Kirsher return -EINVAL; 402adfc5217SJeff Kirsher } 403adfc5217SJeff Kirsher 404adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 405adfc5217SJeff Kirsher /* store value for following "load" */ 406adfc5217SJeff Kirsher bp->pending_max = part; 407adfc5217SJeff Kirsher else 408adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 409adfc5217SJeff Kirsher 410adfc5217SJeff Kirsher return 0; 411adfc5217SJeff Kirsher } 412adfc5217SJeff Kirsher 413adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 414adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 41533f9e6f5SYaniv Rosner if (cmd->port != bnx2x_get_port_type(bp)) { 416adfc5217SJeff Kirsher switch (cmd->port) { 417adfc5217SJeff Kirsher case PORT_TP: 418adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 419adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 42033f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 42133f9e6f5SYaniv Rosner "Unsupported port type\n"); 422adfc5217SJeff Kirsher return -EINVAL; 423adfc5217SJeff Kirsher } 424adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 425adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 426adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 427adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 428adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 429adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 430adfc5217SJeff Kirsher else 431adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 432adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 433adfc5217SJeff Kirsher break; 434adfc5217SJeff Kirsher case PORT_FIBRE: 435bfdb5823SYaniv Rosner case PORT_DA: 436042d7654SYaniv Rosner case PORT_NONE: 437adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 438adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 43933f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 44033f9e6f5SYaniv Rosner "Unsupported port type\n"); 441adfc5217SJeff Kirsher return -EINVAL; 442adfc5217SJeff Kirsher } 443adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 444adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 445adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 446adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 447adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 448adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 449adfc5217SJeff Kirsher else 450adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 451adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 452adfc5217SJeff Kirsher break; 453adfc5217SJeff Kirsher default: 45451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 455adfc5217SJeff Kirsher return -EINVAL; 456adfc5217SJeff Kirsher } 45733f9e6f5SYaniv Rosner } 4582de67439SYuval Mintz /* Save new config in case command complete successfully */ 459adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 460adfc5217SJeff Kirsher /* Get the new cfg_idx */ 461adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 462adfc5217SJeff Kirsher /* Restore old config in case command failed */ 463adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 46451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 465adfc5217SJeff Kirsher 466adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 46775318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 46875318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 46975318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 47075318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 47175318327SYaniv Rosner SUPPORTED_100baseT_Full); 472adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 47351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 474adfc5217SJeff Kirsher return -EINVAL; 475adfc5217SJeff Kirsher } 476adfc5217SJeff Kirsher 477adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 47875318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 47951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 48051c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4818decf868SDavid S. Miller return -EINVAL; 4828decf868SDavid S. Miller } 483adfc5217SJeff Kirsher 484adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4858decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4868decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 487adfc5217SJeff Kirsher cmd->advertising); 4888decf868SDavid S. Miller if (cmd->advertising) { 489adfc5217SJeff Kirsher 4908decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4918decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4928decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4938decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4948decf868SDavid S. Miller } 4958decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4968decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4978decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4988decf868SDavid S. Miller 4998decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 5008decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5018decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 5028decf868SDavid S. Miller 5038decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 5048decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5058decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 5068decf868SDavid S. Miller } 5078decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 5088decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5098decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 5108decf868SDavid S. Miller } 5118decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 5128decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 5138decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5148decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 5158decf868SDavid S. Miller 5168decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 5178decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 5188decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 5198decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5208decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 521be94bea7SYaniv Rosner 522be94bea7SYaniv Rosner if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 523be94bea7SYaniv Rosner bp->link_params.speed_cap_mask[cfg_idx] |= 524be94bea7SYaniv Rosner PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 5258decf868SDavid S. Miller } 526adfc5217SJeff Kirsher } else { /* forced speed */ 527adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 528adfc5217SJeff Kirsher switch (speed) { 529adfc5217SJeff Kirsher case SPEED_10: 530adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 531adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 532adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 53351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 534adfc5217SJeff Kirsher "10M full not supported\n"); 535adfc5217SJeff Kirsher return -EINVAL; 536adfc5217SJeff Kirsher } 537adfc5217SJeff Kirsher 538adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 539adfc5217SJeff Kirsher ADVERTISED_TP); 540adfc5217SJeff Kirsher } else { 541adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 542adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 54351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 544adfc5217SJeff Kirsher "10M half not supported\n"); 545adfc5217SJeff Kirsher return -EINVAL; 546adfc5217SJeff Kirsher } 547adfc5217SJeff Kirsher 548adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 549adfc5217SJeff Kirsher ADVERTISED_TP); 550adfc5217SJeff Kirsher } 551adfc5217SJeff Kirsher break; 552adfc5217SJeff Kirsher 553adfc5217SJeff Kirsher case SPEED_100: 554adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 555adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 556adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 55751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 558adfc5217SJeff Kirsher "100M full not supported\n"); 559adfc5217SJeff Kirsher return -EINVAL; 560adfc5217SJeff Kirsher } 561adfc5217SJeff Kirsher 562adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 563adfc5217SJeff Kirsher ADVERTISED_TP); 564adfc5217SJeff Kirsher } else { 565adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 566adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 56751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 568adfc5217SJeff Kirsher "100M half not supported\n"); 569adfc5217SJeff Kirsher return -EINVAL; 570adfc5217SJeff Kirsher } 571adfc5217SJeff Kirsher 572adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 573adfc5217SJeff Kirsher ADVERTISED_TP); 574adfc5217SJeff Kirsher } 575adfc5217SJeff Kirsher break; 576adfc5217SJeff Kirsher 577adfc5217SJeff Kirsher case SPEED_1000: 578adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 57951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 58051c1a580SMerav Sicron "1G half not supported\n"); 581adfc5217SJeff Kirsher return -EINVAL; 582adfc5217SJeff Kirsher } 583adfc5217SJeff Kirsher 5845d67c1c5SYuval Mintz if (bp->port.supported[cfg_idx] & 5855d67c1c5SYuval Mintz SUPPORTED_1000baseT_Full) { 5865d67c1c5SYuval Mintz advertising = (ADVERTISED_1000baseT_Full | 5875d67c1c5SYuval Mintz ADVERTISED_TP); 5885d67c1c5SYuval Mintz 5895d67c1c5SYuval Mintz } else if (bp->port.supported[cfg_idx] & 5905d67c1c5SYuval Mintz SUPPORTED_1000baseKX_Full) { 5915d67c1c5SYuval Mintz advertising = ADVERTISED_1000baseKX_Full; 5925d67c1c5SYuval Mintz } else { 59351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 59451c1a580SMerav Sicron "1G full not supported\n"); 595adfc5217SJeff Kirsher return -EINVAL; 596adfc5217SJeff Kirsher } 597adfc5217SJeff Kirsher 598adfc5217SJeff Kirsher break; 599adfc5217SJeff Kirsher 600adfc5217SJeff Kirsher case SPEED_2500: 601adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 60251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 603adfc5217SJeff Kirsher "2.5G half not supported\n"); 604adfc5217SJeff Kirsher return -EINVAL; 605adfc5217SJeff Kirsher } 606adfc5217SJeff Kirsher 607adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 608adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 60951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 610adfc5217SJeff Kirsher "2.5G full not supported\n"); 611adfc5217SJeff Kirsher return -EINVAL; 612adfc5217SJeff Kirsher } 613adfc5217SJeff Kirsher 614adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 615adfc5217SJeff Kirsher ADVERTISED_TP); 616adfc5217SJeff Kirsher break; 617adfc5217SJeff Kirsher 618adfc5217SJeff Kirsher case SPEED_10000: 619adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 62051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 62151c1a580SMerav Sicron "10G half not supported\n"); 622adfc5217SJeff Kirsher return -EINVAL; 623adfc5217SJeff Kirsher } 624dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 6255d67c1c5SYuval Mintz if ((bp->port.supported[cfg_idx] & 6265d67c1c5SYuval Mintz SUPPORTED_10000baseT_Full) && 6275d67c1c5SYuval Mintz (bp->link_params.phy[phy_idx].media_type != 628dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 6295d67c1c5SYuval Mintz advertising = (ADVERTISED_10000baseT_Full | 6305d67c1c5SYuval Mintz ADVERTISED_FIBRE); 6315d67c1c5SYuval Mintz } else if (bp->port.supported[cfg_idx] & 6325d67c1c5SYuval Mintz SUPPORTED_10000baseKR_Full) { 6335d67c1c5SYuval Mintz advertising = (ADVERTISED_10000baseKR_Full | 6345d67c1c5SYuval Mintz ADVERTISED_FIBRE); 6355d67c1c5SYuval Mintz } else { 63651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 63751c1a580SMerav Sicron "10G full not supported\n"); 638adfc5217SJeff Kirsher return -EINVAL; 639adfc5217SJeff Kirsher } 640adfc5217SJeff Kirsher 641adfc5217SJeff Kirsher break; 642adfc5217SJeff Kirsher 643adfc5217SJeff Kirsher default: 64451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 645adfc5217SJeff Kirsher return -EINVAL; 646adfc5217SJeff Kirsher } 647adfc5217SJeff Kirsher 648adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 649adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 650adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 651adfc5217SJeff Kirsher } 652adfc5217SJeff Kirsher 65351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 654f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 655adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 656adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 657adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 658adfc5217SJeff Kirsher 659adfc5217SJeff Kirsher /* Set new config */ 660adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 661adfc5217SJeff Kirsher if (netif_running(dev)) { 662adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 663dc6a20aaSAriel Elior bnx2x_force_link_reset(bp); 664adfc5217SJeff Kirsher bnx2x_link_set(bp); 665adfc5217SJeff Kirsher } 666adfc5217SJeff Kirsher 667adfc5217SJeff Kirsher return 0; 668adfc5217SJeff Kirsher } 669adfc5217SJeff Kirsher 67007ba6af4SMiriam Shitrit #define DUMP_ALL_PRESETS 0x1FFF 67107ba6af4SMiriam Shitrit #define DUMP_MAX_PRESETS 13 672adfc5217SJeff Kirsher 67307ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 674adfc5217SJeff Kirsher { 675adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 67607ba6af4SMiriam Shitrit return dump_num_registers[0][preset-1]; 677adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 67807ba6af4SMiriam Shitrit return dump_num_registers[1][preset-1]; 679adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 68007ba6af4SMiriam Shitrit return dump_num_registers[2][preset-1]; 681adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 68207ba6af4SMiriam Shitrit return dump_num_registers[3][preset-1]; 683adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 68407ba6af4SMiriam Shitrit return dump_num_registers[4][preset-1]; 685adfc5217SJeff Kirsher else 68607ba6af4SMiriam Shitrit return 0; 687adfc5217SJeff Kirsher } 688adfc5217SJeff Kirsher 68907ba6af4SMiriam Shitrit static int __bnx2x_get_regs_len(struct bnx2x *bp) 69007ba6af4SMiriam Shitrit { 69107ba6af4SMiriam Shitrit u32 preset_idx; 69207ba6af4SMiriam Shitrit int regdump_len = 0; 69307ba6af4SMiriam Shitrit 69407ba6af4SMiriam Shitrit /* Calculate the total preset regs length */ 69507ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 69607ba6af4SMiriam Shitrit regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 69707ba6af4SMiriam Shitrit 69807ba6af4SMiriam Shitrit return regdump_len; 69907ba6af4SMiriam Shitrit } 70007ba6af4SMiriam Shitrit 70107ba6af4SMiriam Shitrit static int bnx2x_get_regs_len(struct net_device *dev) 70207ba6af4SMiriam Shitrit { 70307ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 70407ba6af4SMiriam Shitrit int regdump_len = 0; 70507ba6af4SMiriam Shitrit 70675543741SYuval Mintz if (IS_VF(bp)) 70775543741SYuval Mintz return 0; 70875543741SYuval Mintz 70907ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_regs_len(bp); 71007ba6af4SMiriam Shitrit regdump_len *= 4; 71107ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 71207ba6af4SMiriam Shitrit 71307ba6af4SMiriam Shitrit return regdump_len; 71407ba6af4SMiriam Shitrit } 71507ba6af4SMiriam Shitrit 71607ba6af4SMiriam Shitrit #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 71707ba6af4SMiriam Shitrit #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 71807ba6af4SMiriam Shitrit #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 71907ba6af4SMiriam Shitrit #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 72007ba6af4SMiriam Shitrit #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 72107ba6af4SMiriam Shitrit 72207ba6af4SMiriam Shitrit #define IS_REG_IN_PRESET(presets, idx) \ 72307ba6af4SMiriam Shitrit ((presets & (1 << (idx-1))) == (1 << (idx-1))) 72407ba6af4SMiriam Shitrit 725adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 7261191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 727adfc5217SJeff Kirsher { 728adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 729adfc5217SJeff Kirsher return page_vals_e2; 730adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 731adfc5217SJeff Kirsher return page_vals_e3; 732adfc5217SJeff Kirsher else 733adfc5217SJeff Kirsher return NULL; 734adfc5217SJeff Kirsher } 735adfc5217SJeff Kirsher 7361191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 737adfc5217SJeff Kirsher { 738adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 739adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 740adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 741adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 742adfc5217SJeff Kirsher else 743adfc5217SJeff Kirsher return 0; 744adfc5217SJeff Kirsher } 745adfc5217SJeff Kirsher 7461191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 747adfc5217SJeff Kirsher { 748adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 749adfc5217SJeff Kirsher return page_write_regs_e2; 750adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 751adfc5217SJeff Kirsher return page_write_regs_e3; 752adfc5217SJeff Kirsher else 753adfc5217SJeff Kirsher return NULL; 754adfc5217SJeff Kirsher } 755adfc5217SJeff Kirsher 7561191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 757adfc5217SJeff Kirsher { 758adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 759adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 760adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 761adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 762adfc5217SJeff Kirsher else 763adfc5217SJeff Kirsher return 0; 764adfc5217SJeff Kirsher } 765adfc5217SJeff Kirsher 7661191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 767adfc5217SJeff Kirsher { 768adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 769adfc5217SJeff Kirsher return page_read_regs_e2; 770adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 771adfc5217SJeff Kirsher return page_read_regs_e3; 772adfc5217SJeff Kirsher else 773adfc5217SJeff Kirsher return NULL; 774adfc5217SJeff Kirsher } 775adfc5217SJeff Kirsher 7761191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 777adfc5217SJeff Kirsher { 778adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 779adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 780adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 781adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 782adfc5217SJeff Kirsher else 783adfc5217SJeff Kirsher return 0; 784adfc5217SJeff Kirsher } 785adfc5217SJeff Kirsher 78607ba6af4SMiriam Shitrit static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 78707ba6af4SMiriam Shitrit const struct reg_addr *reg_info) 788adfc5217SJeff Kirsher { 78907ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 79007ba6af4SMiriam Shitrit return IS_E1_REG(reg_info->chips); 79107ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 79207ba6af4SMiriam Shitrit return IS_E1H_REG(reg_info->chips); 79307ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 79407ba6af4SMiriam Shitrit return IS_E2_REG(reg_info->chips); 79507ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 79607ba6af4SMiriam Shitrit return IS_E3A0_REG(reg_info->chips); 79707ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 79807ba6af4SMiriam Shitrit return IS_E3B0_REG(reg_info->chips); 79907ba6af4SMiriam Shitrit else 80007ba6af4SMiriam Shitrit return false; 801adfc5217SJeff Kirsher } 802adfc5217SJeff Kirsher 80307ba6af4SMiriam Shitrit static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 80407ba6af4SMiriam Shitrit const struct wreg_addr *wreg_info) 805adfc5217SJeff Kirsher { 80607ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 80707ba6af4SMiriam Shitrit return IS_E1_REG(wreg_info->chips); 80807ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 80907ba6af4SMiriam Shitrit return IS_E1H_REG(wreg_info->chips); 81007ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 81107ba6af4SMiriam Shitrit return IS_E2_REG(wreg_info->chips); 81207ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 81307ba6af4SMiriam Shitrit return IS_E3A0_REG(wreg_info->chips); 81407ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 81507ba6af4SMiriam Shitrit return IS_E3B0_REG(wreg_info->chips); 81607ba6af4SMiriam Shitrit else 81707ba6af4SMiriam Shitrit return false; 818adfc5217SJeff Kirsher } 819adfc5217SJeff Kirsher 820adfc5217SJeff Kirsher /** 821adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 822adfc5217SJeff Kirsher * 823adfc5217SJeff Kirsher * @bp device handle 824adfc5217SJeff Kirsher * @p output buffer 825adfc5217SJeff Kirsher * 8262de67439SYuval Mintz * Reads "paged" memories: memories that may only be read by first writing to a 8272de67439SYuval Mintz * specific address ("write address") and then reading from a specific address 8282de67439SYuval Mintz * ("read address"). There may be more than one write address per "page" and 8292de67439SYuval Mintz * more than one read address per write address. 830adfc5217SJeff Kirsher */ 83107ba6af4SMiriam Shitrit static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 832adfc5217SJeff Kirsher { 833adfc5217SJeff Kirsher u32 i, j, k, n; 83407ba6af4SMiriam Shitrit 835adfc5217SJeff Kirsher /* addresses of the paged registers */ 836adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 837adfc5217SJeff Kirsher /* number of paged registers */ 838adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 839adfc5217SJeff Kirsher /* write addresses */ 840adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 841adfc5217SJeff Kirsher /* number of write addresses */ 842adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 843adfc5217SJeff Kirsher /* read addresses info */ 844adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 845adfc5217SJeff Kirsher /* number of read addresses */ 846adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 84707ba6af4SMiriam Shitrit u32 addr, size; 848adfc5217SJeff Kirsher 849adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 850adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 851adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 85207ba6af4SMiriam Shitrit 85307ba6af4SMiriam Shitrit for (k = 0; k < read_num; k++) { 85407ba6af4SMiriam Shitrit if (IS_REG_IN_PRESET(read_addr[k].presets, 85507ba6af4SMiriam Shitrit preset)) { 85607ba6af4SMiriam Shitrit size = read_addr[k].size; 85707ba6af4SMiriam Shitrit for (n = 0; n < size; n++) { 85807ba6af4SMiriam Shitrit addr = read_addr[k].addr + n*4; 85907ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr); 860adfc5217SJeff Kirsher } 861adfc5217SJeff Kirsher } 862adfc5217SJeff Kirsher } 86307ba6af4SMiriam Shitrit } 86407ba6af4SMiriam Shitrit } 86507ba6af4SMiriam Shitrit } 86607ba6af4SMiriam Shitrit 86707ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 86807ba6af4SMiriam Shitrit { 86907ba6af4SMiriam Shitrit u32 i, j, addr; 87007ba6af4SMiriam Shitrit const struct wreg_addr *wreg_addr_p = NULL; 87107ba6af4SMiriam Shitrit 87207ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 87307ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1; 87407ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 87507ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1h; 87607ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 87707ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e2; 87807ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 87907ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3; 88007ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 88107ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3b0; 88207ba6af4SMiriam Shitrit 88307ba6af4SMiriam Shitrit /* Read the idle_chk registers */ 88407ba6af4SMiriam Shitrit for (i = 0; i < IDLE_REGS_COUNT; i++) { 88507ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 88607ba6af4SMiriam Shitrit IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 88707ba6af4SMiriam Shitrit for (j = 0; j < idle_reg_addrs[i].size; j++) 88807ba6af4SMiriam Shitrit *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 88907ba6af4SMiriam Shitrit } 89007ba6af4SMiriam Shitrit } 89107ba6af4SMiriam Shitrit 89207ba6af4SMiriam Shitrit /* Read the regular registers */ 89307ba6af4SMiriam Shitrit for (i = 0; i < REGS_COUNT; i++) { 89407ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 89507ba6af4SMiriam Shitrit IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 89607ba6af4SMiriam Shitrit for (j = 0; j < reg_addrs[i].size; j++) 89707ba6af4SMiriam Shitrit *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 89807ba6af4SMiriam Shitrit } 89907ba6af4SMiriam Shitrit } 90007ba6af4SMiriam Shitrit 90107ba6af4SMiriam Shitrit /* Read the CAM registers */ 90207ba6af4SMiriam Shitrit if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 90307ba6af4SMiriam Shitrit IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 90407ba6af4SMiriam Shitrit for (i = 0; i < wreg_addr_p->size; i++) { 90507ba6af4SMiriam Shitrit *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 90607ba6af4SMiriam Shitrit 90707ba6af4SMiriam Shitrit /* In case of wreg_addr register, read additional 90807ba6af4SMiriam Shitrit registers from read_regs array 90907ba6af4SMiriam Shitrit */ 91007ba6af4SMiriam Shitrit for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 91107ba6af4SMiriam Shitrit addr = *(wreg_addr_p->read_regs); 91207ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr + j*4); 91307ba6af4SMiriam Shitrit } 91407ba6af4SMiriam Shitrit } 91507ba6af4SMiriam Shitrit } 91607ba6af4SMiriam Shitrit 91707ba6af4SMiriam Shitrit /* Paged registers are supported in E2 & E3 only */ 91807ba6af4SMiriam Shitrit if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 91916a5fd92SYuval Mintz /* Read "paged" registers */ 92007ba6af4SMiriam Shitrit bnx2x_read_pages_regs(bp, p, preset); 92107ba6af4SMiriam Shitrit } 92207ba6af4SMiriam Shitrit 92307ba6af4SMiriam Shitrit return 0; 92407ba6af4SMiriam Shitrit } 925adfc5217SJeff Kirsher 9261191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 927adfc5217SJeff Kirsher { 92807ba6af4SMiriam Shitrit u32 preset_idx; 929adfc5217SJeff Kirsher 93007ba6af4SMiriam Shitrit /* Read all registers, by reading all preset registers */ 93107ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 93207ba6af4SMiriam Shitrit /* Skip presets with IOR */ 93307ba6af4SMiriam Shitrit if ((preset_idx == 2) || 93407ba6af4SMiriam Shitrit (preset_idx == 5) || 93507ba6af4SMiriam Shitrit (preset_idx == 8) || 93607ba6af4SMiriam Shitrit (preset_idx == 11)) 93707ba6af4SMiriam Shitrit continue; 93807ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, preset_idx); 93907ba6af4SMiriam Shitrit p += __bnx2x_get_preset_regs_len(bp, preset_idx); 94007ba6af4SMiriam Shitrit } 941adfc5217SJeff Kirsher } 942adfc5217SJeff Kirsher 943adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 944adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 945adfc5217SJeff Kirsher { 946adfc5217SJeff Kirsher u32 *p = _p; 947adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 94807ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 949adfc5217SJeff Kirsher 95007ba6af4SMiriam Shitrit regs->version = 2; 951adfc5217SJeff Kirsher memset(p, 0, regs->len); 952adfc5217SJeff Kirsher 953adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 954adfc5217SJeff Kirsher return; 955adfc5217SJeff Kirsher 956adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 957adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 958adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 959adfc5217SJeff Kirsher */ 96007ba6af4SMiriam Shitrit 961adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 962adfc5217SJeff Kirsher 96307ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 96407ba6af4SMiriam Shitrit dump_hdr.preset = DUMP_ALL_PRESETS; 96507ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 96607ba6af4SMiriam Shitrit 96707ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 96807ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 96907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 97007ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 97107ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 97207ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 97307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 97407ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 97507ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 97607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 97707ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 97807ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 97907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 98007ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 98107ba6af4SMiriam Shitrit } 98207ba6af4SMiriam Shitrit 98307ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 98407ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 985adfc5217SJeff Kirsher 986adfc5217SJeff Kirsher /* Actually read the registers */ 987adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 988adfc5217SJeff Kirsher 9894293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 990adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 991adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 99207ba6af4SMiriam Shitrit } 99307ba6af4SMiriam Shitrit 99407ba6af4SMiriam Shitrit static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 99507ba6af4SMiriam Shitrit { 99607ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 99707ba6af4SMiriam Shitrit int regdump_len = 0; 99807ba6af4SMiriam Shitrit 99907ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 100007ba6af4SMiriam Shitrit regdump_len *= 4; 100107ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 100207ba6af4SMiriam Shitrit 100307ba6af4SMiriam Shitrit return regdump_len; 100407ba6af4SMiriam Shitrit } 100507ba6af4SMiriam Shitrit 100607ba6af4SMiriam Shitrit static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 100707ba6af4SMiriam Shitrit { 100807ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 100907ba6af4SMiriam Shitrit 101007ba6af4SMiriam Shitrit /* Use the ethtool_dump "flag" field as the dump preset index */ 10115bb680d6SMichal Schmidt if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 10125bb680d6SMichal Schmidt return -EINVAL; 10135bb680d6SMichal Schmidt 101407ba6af4SMiriam Shitrit bp->dump_preset_idx = val->flag; 101507ba6af4SMiriam Shitrit return 0; 101607ba6af4SMiriam Shitrit } 101707ba6af4SMiriam Shitrit 101807ba6af4SMiriam Shitrit static int bnx2x_get_dump_flag(struct net_device *dev, 101907ba6af4SMiriam Shitrit struct ethtool_dump *dump) 102007ba6af4SMiriam Shitrit { 102107ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 102207ba6af4SMiriam Shitrit 10238cc2d927SMichal Schmidt dump->version = BNX2X_DUMP_VERSION; 10248cc2d927SMichal Schmidt dump->flag = bp->dump_preset_idx; 102507ba6af4SMiriam Shitrit /* Calculate the requested preset idx length */ 102607ba6af4SMiriam Shitrit dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 102707ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 102807ba6af4SMiriam Shitrit bp->dump_preset_idx, dump->len); 102907ba6af4SMiriam Shitrit return 0; 103007ba6af4SMiriam Shitrit } 103107ba6af4SMiriam Shitrit 103207ba6af4SMiriam Shitrit static int bnx2x_get_dump_data(struct net_device *dev, 103307ba6af4SMiriam Shitrit struct ethtool_dump *dump, 103407ba6af4SMiriam Shitrit void *buffer) 103507ba6af4SMiriam Shitrit { 103607ba6af4SMiriam Shitrit u32 *p = buffer; 103707ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 103807ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 103907ba6af4SMiriam Shitrit 104007ba6af4SMiriam Shitrit /* Disable parity attentions as long as following dump may 104107ba6af4SMiriam Shitrit * cause false alarms by reading never written registers. We 104207ba6af4SMiriam Shitrit * will re-enable parity attentions right after the dump. 104307ba6af4SMiriam Shitrit */ 104407ba6af4SMiriam Shitrit 104507ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 104607ba6af4SMiriam Shitrit 104707ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 104807ba6af4SMiriam Shitrit dump_hdr.preset = bp->dump_preset_idx; 104907ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 105007ba6af4SMiriam Shitrit 105107ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 105207ba6af4SMiriam Shitrit 105307ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 105407ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 105507ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 105607ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 105707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 105807ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 105907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 106007ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 106107ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 106207ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 106307ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 106407ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 106507ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 106607ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 106707ba6af4SMiriam Shitrit } 106807ba6af4SMiriam Shitrit 106907ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 107007ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 107107ba6af4SMiriam Shitrit 107207ba6af4SMiriam Shitrit /* Actually read the registers */ 107307ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 107407ba6af4SMiriam Shitrit 10754293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 107607ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 107707ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 107807ba6af4SMiriam Shitrit 107907ba6af4SMiriam Shitrit return 0; 1080adfc5217SJeff Kirsher } 1081adfc5217SJeff Kirsher 1082adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 1083adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 1084adfc5217SJeff Kirsher { 1085adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1086adfc5217SJeff Kirsher 108768aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 108868aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1089adfc5217SJeff Kirsher 10908ca5e17eSAriel Elior bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 10918ca5e17eSAriel Elior 109268aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1093adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 1094cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 1095adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 1096adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 1097adfc5217SJeff Kirsher } 1098adfc5217SJeff Kirsher 1099adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1100adfc5217SJeff Kirsher { 1101adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1102adfc5217SJeff Kirsher 1103adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 1104adfc5217SJeff Kirsher wol->supported = 0; 1105adfc5217SJeff Kirsher wol->wolopts = 0; 1106adfc5217SJeff Kirsher } else { 1107adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 1108adfc5217SJeff Kirsher if (bp->wol) 1109adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 1110adfc5217SJeff Kirsher else 1111adfc5217SJeff Kirsher wol->wolopts = 0; 1112adfc5217SJeff Kirsher } 1113adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 1114adfc5217SJeff Kirsher } 1115adfc5217SJeff Kirsher 1116adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1117adfc5217SJeff Kirsher { 1118adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1119adfc5217SJeff Kirsher 112051c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 11212de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1122adfc5217SJeff Kirsher return -EINVAL; 112351c1a580SMerav Sicron } 1124adfc5217SJeff Kirsher 1125adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 112651c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 11272de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1128adfc5217SJeff Kirsher return -EINVAL; 112951c1a580SMerav Sicron } 1130adfc5217SJeff Kirsher bp->wol = 1; 1131adfc5217SJeff Kirsher } else 1132adfc5217SJeff Kirsher bp->wol = 0; 1133adfc5217SJeff Kirsher 1134230d00ebSYuval Mintz if (SHMEM2_HAS(bp, curr_cfg)) 1135230d00ebSYuval Mintz SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1136230d00ebSYuval Mintz 1137adfc5217SJeff Kirsher return 0; 1138adfc5217SJeff Kirsher } 1139adfc5217SJeff Kirsher 1140adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 1141adfc5217SJeff Kirsher { 1142adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1143adfc5217SJeff Kirsher 1144adfc5217SJeff Kirsher return bp->msg_enable; 1145adfc5217SJeff Kirsher } 1146adfc5217SJeff Kirsher 1147adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1148adfc5217SJeff Kirsher { 1149adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1150adfc5217SJeff Kirsher 1151adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 1152adfc5217SJeff Kirsher /* dump MCP trace */ 1153ad5afc89SAriel Elior if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1154adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 1155adfc5217SJeff Kirsher bp->msg_enable = level; 1156adfc5217SJeff Kirsher } 1157adfc5217SJeff Kirsher } 1158adfc5217SJeff Kirsher 1159adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 1160adfc5217SJeff Kirsher { 1161adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1162adfc5217SJeff Kirsher 1163adfc5217SJeff Kirsher if (!bp->port.pmf) 1164adfc5217SJeff Kirsher return 0; 1165adfc5217SJeff Kirsher 1166adfc5217SJeff Kirsher if (netif_running(dev)) { 1167adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11685d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1169adfc5217SJeff Kirsher bnx2x_link_set(bp); 1170adfc5217SJeff Kirsher } 1171adfc5217SJeff Kirsher 1172adfc5217SJeff Kirsher return 0; 1173adfc5217SJeff Kirsher } 1174adfc5217SJeff Kirsher 1175adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 1176adfc5217SJeff Kirsher { 1177adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1178adfc5217SJeff Kirsher 1179adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1180adfc5217SJeff Kirsher return 0; 1181adfc5217SJeff Kirsher 11826495d15aSDmitry Kravkov if (IS_VF(bp)) 11836495d15aSDmitry Kravkov return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 11846495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags); 11856495d15aSDmitry Kravkov 1186adfc5217SJeff Kirsher return bp->link_vars.link_up; 1187adfc5217SJeff Kirsher } 1188adfc5217SJeff Kirsher 1189adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 1190adfc5217SJeff Kirsher { 1191adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1192adfc5217SJeff Kirsher 1193adfc5217SJeff Kirsher return bp->common.flash_size; 1194adfc5217SJeff Kirsher } 1195adfc5217SJeff Kirsher 119616a5fd92SYuval Mintz /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 119716a5fd92SYuval Mintz * had we done things the other way around, if two pfs from the same port would 1198f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 1199f16da43bSAriel Elior * as: 1200f16da43bSAriel Elior * pf A takes the port lock. 1201f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 1202f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 1203f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 1204f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 1205f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 1206f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 12072de67439SYuval Mintz * access corrupted by pf B) 1208f16da43bSAriel Elior */ 1209adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1210adfc5217SJeff Kirsher { 1211adfc5217SJeff Kirsher int port = BP_PORT(bp); 1212adfc5217SJeff Kirsher int count, i; 1213f16da43bSAriel Elior u32 val; 1214f16da43bSAriel Elior 1215f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1216f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1217adfc5217SJeff Kirsher 1218adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1219adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1220adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1221adfc5217SJeff Kirsher count *= 100; 1222adfc5217SJeff Kirsher 1223adfc5217SJeff Kirsher /* request access to nvram interface */ 1224adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1225adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1226adfc5217SJeff Kirsher 1227adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1228adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1229adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1230adfc5217SJeff Kirsher break; 1231adfc5217SJeff Kirsher 1232adfc5217SJeff Kirsher udelay(5); 1233adfc5217SJeff Kirsher } 1234adfc5217SJeff Kirsher 1235adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 123651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 123751c1a580SMerav Sicron "cannot get access to nvram interface\n"); 1238efd38b8fSYuval Mintz bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1239adfc5217SJeff Kirsher return -EBUSY; 1240adfc5217SJeff Kirsher } 1241adfc5217SJeff Kirsher 1242adfc5217SJeff Kirsher return 0; 1243adfc5217SJeff Kirsher } 1244adfc5217SJeff Kirsher 1245adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1246adfc5217SJeff Kirsher { 1247adfc5217SJeff Kirsher int port = BP_PORT(bp); 1248adfc5217SJeff Kirsher int count, i; 1249f16da43bSAriel Elior u32 val; 1250adfc5217SJeff Kirsher 1251adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1252adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1253adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1254adfc5217SJeff Kirsher count *= 100; 1255adfc5217SJeff Kirsher 1256adfc5217SJeff Kirsher /* relinquish nvram interface */ 1257adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1258adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1259adfc5217SJeff Kirsher 1260adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1261adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1262adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1263adfc5217SJeff Kirsher break; 1264adfc5217SJeff Kirsher 1265adfc5217SJeff Kirsher udelay(5); 1266adfc5217SJeff Kirsher } 1267adfc5217SJeff Kirsher 1268adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 126951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 127051c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1271adfc5217SJeff Kirsher return -EBUSY; 1272adfc5217SJeff Kirsher } 1273adfc5217SJeff Kirsher 1274f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1275f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1276adfc5217SJeff Kirsher return 0; 1277adfc5217SJeff Kirsher } 1278adfc5217SJeff Kirsher 1279adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1280adfc5217SJeff Kirsher { 1281adfc5217SJeff Kirsher u32 val; 1282adfc5217SJeff Kirsher 1283adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1284adfc5217SJeff Kirsher 1285adfc5217SJeff Kirsher /* enable both bits, even on read */ 1286adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1287adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1288adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1289adfc5217SJeff Kirsher } 1290adfc5217SJeff Kirsher 1291adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1292adfc5217SJeff Kirsher { 1293adfc5217SJeff Kirsher u32 val; 1294adfc5217SJeff Kirsher 1295adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1296adfc5217SJeff Kirsher 1297adfc5217SJeff Kirsher /* disable both bits, even after read */ 1298adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1299adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1300adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1301adfc5217SJeff Kirsher } 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1304adfc5217SJeff Kirsher u32 cmd_flags) 1305adfc5217SJeff Kirsher { 1306adfc5217SJeff Kirsher int count, i, rc; 1307adfc5217SJeff Kirsher u32 val; 1308adfc5217SJeff Kirsher 1309adfc5217SJeff Kirsher /* build the command word */ 1310adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1311adfc5217SJeff Kirsher 1312adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1313adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1314adfc5217SJeff Kirsher 1315adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1316adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1317adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1318adfc5217SJeff Kirsher 1319adfc5217SJeff Kirsher /* issue a read command */ 1320adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1321adfc5217SJeff Kirsher 1322adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1323adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1324adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1325adfc5217SJeff Kirsher count *= 100; 1326adfc5217SJeff Kirsher 1327adfc5217SJeff Kirsher /* wait for completion */ 1328adfc5217SJeff Kirsher *ret_val = 0; 1329adfc5217SJeff Kirsher rc = -EBUSY; 1330adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1331adfc5217SJeff Kirsher udelay(5); 1332adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1333adfc5217SJeff Kirsher 1334adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1335adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1336adfc5217SJeff Kirsher /* we read nvram data in cpu order 1337adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 133807ba6af4SMiriam Shitrit * converting to big-endian will do the work 133907ba6af4SMiriam Shitrit */ 1340adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1341adfc5217SJeff Kirsher rc = 0; 1342adfc5217SJeff Kirsher break; 1343adfc5217SJeff Kirsher } 1344adfc5217SJeff Kirsher } 134551c1a580SMerav Sicron if (rc == -EBUSY) 134651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 134751c1a580SMerav Sicron "nvram read timeout expired\n"); 1348adfc5217SJeff Kirsher return rc; 1349adfc5217SJeff Kirsher } 1350adfc5217SJeff Kirsher 135197ac4ef7SYuval Mintz int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1352adfc5217SJeff Kirsher int buf_size) 1353adfc5217SJeff Kirsher { 1354adfc5217SJeff Kirsher int rc; 1355adfc5217SJeff Kirsher u32 cmd_flags; 1356adfc5217SJeff Kirsher __be32 val; 1357adfc5217SJeff Kirsher 1358adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 135951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1360adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1361adfc5217SJeff Kirsher offset, buf_size); 1362adfc5217SJeff Kirsher return -EINVAL; 1363adfc5217SJeff Kirsher } 1364adfc5217SJeff Kirsher 1365adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 136651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 136751c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1368adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1369adfc5217SJeff Kirsher return -EINVAL; 1370adfc5217SJeff Kirsher } 1371adfc5217SJeff Kirsher 1372adfc5217SJeff Kirsher /* request access to nvram interface */ 1373adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1374adfc5217SJeff Kirsher if (rc) 1375adfc5217SJeff Kirsher return rc; 1376adfc5217SJeff Kirsher 1377adfc5217SJeff Kirsher /* enable access to nvram interface */ 1378adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1379adfc5217SJeff Kirsher 1380adfc5217SJeff Kirsher /* read the first word(s) */ 1381adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1382adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1383adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1384adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1385adfc5217SJeff Kirsher 1386adfc5217SJeff Kirsher /* advance to the next dword */ 1387adfc5217SJeff Kirsher offset += sizeof(u32); 1388adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1389adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1390adfc5217SJeff Kirsher cmd_flags = 0; 1391adfc5217SJeff Kirsher } 1392adfc5217SJeff Kirsher 1393adfc5217SJeff Kirsher if (rc == 0) { 1394adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1395adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1396adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1397adfc5217SJeff Kirsher } 1398adfc5217SJeff Kirsher 1399adfc5217SJeff Kirsher /* disable access to nvram interface */ 1400adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1401adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1402adfc5217SJeff Kirsher 1403adfc5217SJeff Kirsher return rc; 1404adfc5217SJeff Kirsher } 1405adfc5217SJeff Kirsher 140685640952SDmitry Kravkov static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 140785640952SDmitry Kravkov int buf_size) 140885640952SDmitry Kravkov { 140985640952SDmitry Kravkov int rc; 141085640952SDmitry Kravkov 141185640952SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 141285640952SDmitry Kravkov 141385640952SDmitry Kravkov if (!rc) { 141485640952SDmitry Kravkov __be32 *be = (__be32 *)buf; 141585640952SDmitry Kravkov 141685640952SDmitry Kravkov while ((buf_size -= 4) >= 0) 141785640952SDmitry Kravkov *buf++ = be32_to_cpu(*be++); 141885640952SDmitry Kravkov } 141985640952SDmitry Kravkov 142085640952SDmitry Kravkov return rc; 142185640952SDmitry Kravkov } 142285640952SDmitry Kravkov 14233fb43eb2SYuval Mintz static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 14243fb43eb2SYuval Mintz { 14253fb43eb2SYuval Mintz int rc = 1; 14263fb43eb2SYuval Mintz u16 pm = 0; 14273fb43eb2SYuval Mintz struct net_device *dev = pci_get_drvdata(bp->pdev); 14283fb43eb2SYuval Mintz 142929ed74c3SJon Mason if (bp->pdev->pm_cap) 14303fb43eb2SYuval Mintz rc = pci_read_config_word(bp->pdev, 143129ed74c3SJon Mason bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 14323fb43eb2SYuval Mintz 1433829a5071SYuval Mintz if ((rc && !netif_running(dev)) || 1434c957d09fSYuval Mintz (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 14353fb43eb2SYuval Mintz return false; 14363fb43eb2SYuval Mintz 14373fb43eb2SYuval Mintz return true; 14383fb43eb2SYuval Mintz } 14393fb43eb2SYuval Mintz 1440adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1441adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1442adfc5217SJeff Kirsher { 1443adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1444adfc5217SJeff Kirsher 14453fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 144651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 144751c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1448adfc5217SJeff Kirsher return -EAGAIN; 144951c1a580SMerav Sicron } 1450adfc5217SJeff Kirsher 145151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1452f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1453adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1454adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1455adfc5217SJeff Kirsher 1456adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1457adfc5217SJeff Kirsher 1458f1691dc6SDmitry Kravkov return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1459adfc5217SJeff Kirsher } 1460adfc5217SJeff Kirsher 146124ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 146224ea818eSYuval Mintz struct ethtool_eeprom *ee, 146324ea818eSYuval Mintz u8 *data) 146424ea818eSYuval Mintz { 146524ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1466669d6996SYaniv Rosner int rc = -EINVAL, phy_idx; 146724ea818eSYuval Mintz u8 *user_data = data; 1468669d6996SYaniv Rosner unsigned int start_addr = ee->offset, xfer_size = 0; 146924ea818eSYuval Mintz 14703fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 147124ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 147224ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 147324ea818eSYuval Mintz return -EAGAIN; 147424ea818eSYuval Mintz } 147524ea818eSYuval Mintz 147624ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1477669d6996SYaniv Rosner 1478669d6996SYaniv Rosner /* Read A0 section */ 1479669d6996SYaniv Rosner if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1480669d6996SYaniv Rosner /* Limit transfer size to the A0 section boundary */ 1481669d6996SYaniv Rosner if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1482669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1483669d6996SYaniv Rosner else 1484669d6996SYaniv Rosner xfer_size = ee->len; 148524ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 148624ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 148724ea818eSYuval Mintz &bp->link_params, 1488669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1489669d6996SYaniv Rosner start_addr, 149024ea818eSYuval Mintz xfer_size, 149124ea818eSYuval Mintz user_data); 1492669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1493669d6996SYaniv Rosner if (rc) { 1494669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1495669d6996SYaniv Rosner 1496669d6996SYaniv Rosner return -EINVAL; 1497669d6996SYaniv Rosner } 149824ea818eSYuval Mintz user_data += xfer_size; 1499669d6996SYaniv Rosner start_addr += xfer_size; 150024ea818eSYuval Mintz } 150124ea818eSYuval Mintz 1502669d6996SYaniv Rosner /* Read A2 section */ 1503669d6996SYaniv Rosner if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1504669d6996SYaniv Rosner (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1505669d6996SYaniv Rosner xfer_size = ee->len - xfer_size; 1506669d6996SYaniv Rosner /* Limit transfer size to the A2 section boundary */ 1507669d6996SYaniv Rosner if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1508669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1509669d6996SYaniv Rosner start_addr -= ETH_MODULE_SFF_8079_LEN; 1510669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1511669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1512669d6996SYaniv Rosner &bp->link_params, 1513669d6996SYaniv Rosner I2C_DEV_ADDR_A2, 1514669d6996SYaniv Rosner start_addr, 1515669d6996SYaniv Rosner xfer_size, 1516669d6996SYaniv Rosner user_data); 151724ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 1518669d6996SYaniv Rosner if (rc) { 1519669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1520669d6996SYaniv Rosner return -EINVAL; 1521669d6996SYaniv Rosner } 1522669d6996SYaniv Rosner } 152324ea818eSYuval Mintz return rc; 152424ea818eSYuval Mintz } 152524ea818eSYuval Mintz 152624ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 152724ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 152824ea818eSYuval Mintz { 152924ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1530669d6996SYaniv Rosner int phy_idx, rc; 1531669d6996SYaniv Rosner u8 sff8472_comp, diag_type; 1532669d6996SYaniv Rosner 15333fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 153424ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 153524ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 153624ea818eSYuval Mintz return -EAGAIN; 153724ea818eSYuval Mintz } 153824ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1539669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1540669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1541669d6996SYaniv Rosner &bp->link_params, 1542669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1543669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_ADDR, 1544669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_SIZE, 1545669d6996SYaniv Rosner &sff8472_comp); 1546669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1547669d6996SYaniv Rosner if (rc) { 1548669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1549669d6996SYaniv Rosner return -EINVAL; 1550669d6996SYaniv Rosner } 1551669d6996SYaniv Rosner 1552669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1553669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1554669d6996SYaniv Rosner &bp->link_params, 1555669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1556669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_ADDR, 1557669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_SIZE, 1558669d6996SYaniv Rosner &diag_type); 1559669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1560669d6996SYaniv Rosner if (rc) { 1561669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1562669d6996SYaniv Rosner return -EINVAL; 1563669d6996SYaniv Rosner } 1564669d6996SYaniv Rosner 1565669d6996SYaniv Rosner if (!sff8472_comp || 1566669d6996SYaniv Rosner (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 156724ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 156824ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1569669d6996SYaniv Rosner } else { 1570669d6996SYaniv Rosner modinfo->type = ETH_MODULE_SFF_8472; 1571669d6996SYaniv Rosner modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 157224ea818eSYuval Mintz } 1573669d6996SYaniv Rosner return 0; 157424ea818eSYuval Mintz } 157524ea818eSYuval Mintz 1576adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1577adfc5217SJeff Kirsher u32 cmd_flags) 1578adfc5217SJeff Kirsher { 1579adfc5217SJeff Kirsher int count, i, rc; 1580adfc5217SJeff Kirsher 1581adfc5217SJeff Kirsher /* build the command word */ 1582adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1583adfc5217SJeff Kirsher 1584adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1585adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1586adfc5217SJeff Kirsher 1587adfc5217SJeff Kirsher /* write the data */ 1588adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1589adfc5217SJeff Kirsher 1590adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1591adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1592adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1593adfc5217SJeff Kirsher 1594adfc5217SJeff Kirsher /* issue the write command */ 1595adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1596adfc5217SJeff Kirsher 1597adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1598adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1599adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1600adfc5217SJeff Kirsher count *= 100; 1601adfc5217SJeff Kirsher 1602adfc5217SJeff Kirsher /* wait for completion */ 1603adfc5217SJeff Kirsher rc = -EBUSY; 1604adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1605adfc5217SJeff Kirsher udelay(5); 1606adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1607adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1608adfc5217SJeff Kirsher rc = 0; 1609adfc5217SJeff Kirsher break; 1610adfc5217SJeff Kirsher } 1611adfc5217SJeff Kirsher } 1612adfc5217SJeff Kirsher 161351c1a580SMerav Sicron if (rc == -EBUSY) 161451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 161551c1a580SMerav Sicron "nvram write timeout expired\n"); 1616adfc5217SJeff Kirsher return rc; 1617adfc5217SJeff Kirsher } 1618adfc5217SJeff Kirsher 1619adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1620adfc5217SJeff Kirsher 1621adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1622adfc5217SJeff Kirsher int buf_size) 1623adfc5217SJeff Kirsher { 1624adfc5217SJeff Kirsher int rc; 162530c20b67SDmitry Kravkov u32 cmd_flags, align_offset, val; 162630c20b67SDmitry Kravkov __be32 val_be; 1627adfc5217SJeff Kirsher 1628adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 162951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 163051c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1631adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1632adfc5217SJeff Kirsher return -EINVAL; 1633adfc5217SJeff Kirsher } 1634adfc5217SJeff Kirsher 1635adfc5217SJeff Kirsher /* request access to nvram interface */ 1636adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1637adfc5217SJeff Kirsher if (rc) 1638adfc5217SJeff Kirsher return rc; 1639adfc5217SJeff Kirsher 1640adfc5217SJeff Kirsher /* enable access to nvram interface */ 1641adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1642adfc5217SJeff Kirsher 1643adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1644adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 164530c20b67SDmitry Kravkov rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1646adfc5217SJeff Kirsher 1647adfc5217SJeff Kirsher if (rc == 0) { 1648adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 164907ba6af4SMiriam Shitrit * convert it back to cpu order 165007ba6af4SMiriam Shitrit */ 165130c20b67SDmitry Kravkov val = be32_to_cpu(val_be); 165230c20b67SDmitry Kravkov 1653c957d09fSYuval Mintz val &= ~le32_to_cpu((__force __le32) 1654c957d09fSYuval Mintz (0xff << BYTE_OFFSET(offset))); 1655c957d09fSYuval Mintz val |= le32_to_cpu((__force __le32) 1656c957d09fSYuval Mintz (*data_buf << BYTE_OFFSET(offset))); 1657adfc5217SJeff Kirsher 1658adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1659adfc5217SJeff Kirsher cmd_flags); 1660adfc5217SJeff Kirsher } 1661adfc5217SJeff Kirsher 1662adfc5217SJeff Kirsher /* disable access to nvram interface */ 1663adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1664adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1665adfc5217SJeff Kirsher 1666adfc5217SJeff Kirsher return rc; 1667adfc5217SJeff Kirsher } 1668adfc5217SJeff Kirsher 1669adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1670adfc5217SJeff Kirsher int buf_size) 1671adfc5217SJeff Kirsher { 1672adfc5217SJeff Kirsher int rc; 1673adfc5217SJeff Kirsher u32 cmd_flags; 1674adfc5217SJeff Kirsher u32 val; 1675adfc5217SJeff Kirsher u32 written_so_far; 1676adfc5217SJeff Kirsher 1677adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1678adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1679adfc5217SJeff Kirsher 1680adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 168151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1682adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1683adfc5217SJeff Kirsher offset, buf_size); 1684adfc5217SJeff Kirsher return -EINVAL; 1685adfc5217SJeff Kirsher } 1686adfc5217SJeff Kirsher 1687adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 168851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 168951c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1690adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1691adfc5217SJeff Kirsher return -EINVAL; 1692adfc5217SJeff Kirsher } 1693adfc5217SJeff Kirsher 1694adfc5217SJeff Kirsher /* request access to nvram interface */ 1695adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1696adfc5217SJeff Kirsher if (rc) 1697adfc5217SJeff Kirsher return rc; 1698adfc5217SJeff Kirsher 1699adfc5217SJeff Kirsher /* enable access to nvram interface */ 1700adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1701adfc5217SJeff Kirsher 1702adfc5217SJeff Kirsher written_so_far = 0; 1703adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1704adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1705adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1706adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1707adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1708adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1709adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1710adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1711adfc5217SJeff Kirsher 1712adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1713adfc5217SJeff Kirsher 171468bf5a10SYuval Mintz /* Notice unlike bnx2x_nvram_read_dword() this will not 171568bf5a10SYuval Mintz * change val using be32_to_cpu(), which causes data to flip 171668bf5a10SYuval Mintz * if the eeprom is read and then written back. This is due 171768bf5a10SYuval Mintz * to tools utilizing this functionality that would break 171868bf5a10SYuval Mintz * if this would be resolved. 171968bf5a10SYuval Mintz */ 1720adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1721adfc5217SJeff Kirsher 1722adfc5217SJeff Kirsher /* advance to the next dword */ 1723adfc5217SJeff Kirsher offset += sizeof(u32); 1724adfc5217SJeff Kirsher data_buf += sizeof(u32); 1725adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1726adfc5217SJeff Kirsher cmd_flags = 0; 1727adfc5217SJeff Kirsher } 1728adfc5217SJeff Kirsher 1729adfc5217SJeff Kirsher /* disable access to nvram interface */ 1730adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1731adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1732adfc5217SJeff Kirsher 1733adfc5217SJeff Kirsher return rc; 1734adfc5217SJeff Kirsher } 1735adfc5217SJeff Kirsher 1736adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1737adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1738adfc5217SJeff Kirsher { 1739adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1740adfc5217SJeff Kirsher int port = BP_PORT(bp); 1741adfc5217SJeff Kirsher int rc = 0; 1742adfc5217SJeff Kirsher u32 ext_phy_config; 17433fb43eb2SYuval Mintz 17443fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 174551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 174651c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1747adfc5217SJeff Kirsher return -EAGAIN; 174851c1a580SMerav Sicron } 1749adfc5217SJeff Kirsher 175051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1751f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1752adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1753adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1754adfc5217SJeff Kirsher 1755adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1756adfc5217SJeff Kirsher 1757adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1758adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 175951c1a580SMerav Sicron !bp->port.pmf) { 176051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 176151c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1762adfc5217SJeff Kirsher return -EINVAL; 176351c1a580SMerav Sicron } 1764adfc5217SJeff Kirsher 1765adfc5217SJeff Kirsher ext_phy_config = 1766adfc5217SJeff Kirsher SHMEM_RD(bp, 1767adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1768adfc5217SJeff Kirsher 1769adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1770adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1771adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1772adfc5217SJeff Kirsher 1773adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1774adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1775adfc5217SJeff Kirsher &bp->link_vars, 0); 1776adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1777adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1778adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1779adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1780adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1781adfc5217SJeff Kirsher bnx2x_link_report(bp); 1782adfc5217SJeff Kirsher 1783adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1784adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1785adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1786adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1787adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1788adfc5217SJeff Kirsher &bp->link_vars, 1); 1789adfc5217SJeff Kirsher 1790adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1791adfc5217SJeff Kirsher &bp->link_vars); 1792adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1793adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1794adfc5217SJeff Kirsher } 1795adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1796adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1797adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1798adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1799adfc5217SJeff Kirsher 1800adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1801adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1802adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1803adfc5217SJeff Kirsher 1804adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1805adfc5217SJeff Kirsher 1806adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1807adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1808adfc5217SJeff Kirsher 1809adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1810adfc5217SJeff Kirsher msleep(500); 1811adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1812adfc5217SJeff Kirsher msleep(500); 1813adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1814adfc5217SJeff Kirsher } 1815adfc5217SJeff Kirsher } else 1816adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1817adfc5217SJeff Kirsher 1818adfc5217SJeff Kirsher return rc; 1819adfc5217SJeff Kirsher } 1820adfc5217SJeff Kirsher 1821adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1822adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1823adfc5217SJeff Kirsher { 1824adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1825adfc5217SJeff Kirsher 1826adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1827adfc5217SJeff Kirsher 1828adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1829adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1830adfc5217SJeff Kirsher 1831adfc5217SJeff Kirsher return 0; 1832adfc5217SJeff Kirsher } 1833adfc5217SJeff Kirsher 1834adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1835adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1836adfc5217SJeff Kirsher { 1837adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1838adfc5217SJeff Kirsher 1839adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1840adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1841adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1842adfc5217SJeff Kirsher 1843adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1844adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1845adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1846adfc5217SJeff Kirsher 1847adfc5217SJeff Kirsher if (netif_running(dev)) 1848adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1849adfc5217SJeff Kirsher 1850adfc5217SJeff Kirsher return 0; 1851adfc5217SJeff Kirsher } 1852adfc5217SJeff Kirsher 1853adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1854adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1855adfc5217SJeff Kirsher { 1856adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1857adfc5217SJeff Kirsher 1858adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1859adfc5217SJeff Kirsher 1860adfc5217SJeff Kirsher if (bp->rx_ring_size) 1861adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1862adfc5217SJeff Kirsher else 1863adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1864adfc5217SJeff Kirsher 1865a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1866adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1867adfc5217SJeff Kirsher } 1868adfc5217SJeff Kirsher 1869adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1870adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1871adfc5217SJeff Kirsher { 1872adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1873adfc5217SJeff Kirsher 187404c46736SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 187504c46736SYuval Mintz "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 187604c46736SYuval Mintz ering->rx_pending, ering->tx_pending); 187704c46736SYuval Mintz 1878909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 1879909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, 1880909d9faaSYuval Mintz "VFs are enabled, can not change ring parameters\n"); 1881909d9faaSYuval Mintz return -EPERM; 1882909d9faaSYuval Mintz } 1883909d9faaSYuval Mintz 1884adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 188551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 188651c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1887adfc5217SJeff Kirsher return -EAGAIN; 1888adfc5217SJeff Kirsher } 1889adfc5217SJeff Kirsher 1890adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1891adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1892adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 18932e98ffc2SDmitry Kravkov (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 189451c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 189551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1896adfc5217SJeff Kirsher return -EINVAL; 189751c1a580SMerav Sicron } 1898adfc5217SJeff Kirsher 1899adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1900adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1901adfc5217SJeff Kirsher 1902adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1903adfc5217SJeff Kirsher } 1904adfc5217SJeff Kirsher 1905adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1906adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1907adfc5217SJeff Kirsher { 1908adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1909adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 19109e7e8399SMintz Yuval int cfg_reg; 19119e7e8399SMintz Yuval 1912adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1913adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1914adfc5217SJeff Kirsher 19159e7e8399SMintz Yuval if (!epause->autoneg) 1916241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 19179e7e8399SMintz Yuval else 19189e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 19199e7e8399SMintz Yuval 19209e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1921adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 19229e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1923adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1924adfc5217SJeff Kirsher 192551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1926f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1927adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1928adfc5217SJeff Kirsher } 1929adfc5217SJeff Kirsher 1930adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1931adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1932adfc5217SJeff Kirsher { 1933adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1934adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1935adfc5217SJeff Kirsher if (IS_MF(bp)) 1936adfc5217SJeff Kirsher return 0; 1937adfc5217SJeff Kirsher 193851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1939f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1940adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1941adfc5217SJeff Kirsher 1942adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1943adfc5217SJeff Kirsher 1944adfc5217SJeff Kirsher if (epause->rx_pause) 1945adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1946adfc5217SJeff Kirsher 1947adfc5217SJeff Kirsher if (epause->tx_pause) 1948adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1949adfc5217SJeff Kirsher 1950adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1951adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1952adfc5217SJeff Kirsher 1953adfc5217SJeff Kirsher if (epause->autoneg) { 1954adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 195551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1956adfc5217SJeff Kirsher return -EINVAL; 1957adfc5217SJeff Kirsher } 1958adfc5217SJeff Kirsher 1959adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1960adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1961adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1962adfc5217SJeff Kirsher } 1963ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv = 0; 19645cd75f0cSYaniv Rosner if (epause->rx_pause) 19655cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 19665cd75f0cSYaniv Rosner 19675cd75f0cSYaniv Rosner if (epause->tx_pause) 19685cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1969ba35a0fdSYaniv Rosner 1970ba35a0fdSYaniv Rosner if (!bp->link_params.req_fc_auto_adv) 1971ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1972adfc5217SJeff Kirsher } 1973adfc5217SJeff Kirsher 197451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1975adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1976adfc5217SJeff Kirsher 1977adfc5217SJeff Kirsher if (netif_running(dev)) { 1978adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1979dc6a20aaSAriel Elior bnx2x_force_link_reset(bp); 1980adfc5217SJeff Kirsher bnx2x_link_set(bp); 1981adfc5217SJeff Kirsher } 1982adfc5217SJeff Kirsher 1983adfc5217SJeff Kirsher return 0; 1984adfc5217SJeff Kirsher } 1985adfc5217SJeff Kirsher 19865889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1987cf2c1df6SMerav Sicron "register_test (offline) ", 1988cf2c1df6SMerav Sicron "memory_test (offline) ", 1989cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1990cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1991cf2c1df6SMerav Sicron "nvram_test (online) ", 1992cf2c1df6SMerav Sicron "interrupt_test (online) ", 1993cf2c1df6SMerav Sicron "link_test (online) " 1994adfc5217SJeff Kirsher }; 1995adfc5217SJeff Kirsher 19963521b419SYuval Mintz enum { 19973521b419SYuval Mintz BNX2X_PRI_FLAG_ISCSI, 19983521b419SYuval Mintz BNX2X_PRI_FLAG_FCOE, 19993521b419SYuval Mintz BNX2X_PRI_FLAG_STORAGE, 20003521b419SYuval Mintz BNX2X_PRI_FLAG_LEN, 20013521b419SYuval Mintz }; 20023521b419SYuval Mintz 20033521b419SYuval Mintz static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 20043521b419SYuval Mintz "iSCSI offload support", 20053521b419SYuval Mintz "FCoE offload support", 20063521b419SYuval Mintz "Storage only interface" 20073521b419SYuval Mintz }; 20083521b419SYuval Mintz 2009e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 2010e9939c80SYuval Mintz { 2011e9939c80SYuval Mintz u32 modes = 0; 2012e9939c80SYuval Mintz 2013e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 2014e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 2015e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 2016e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 2017e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 2018e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 2019e9939c80SYuval Mintz 2020e9939c80SYuval Mintz return modes; 2021e9939c80SYuval Mintz } 2022e9939c80SYuval Mintz 2023e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2024e9939c80SYuval Mintz { 2025e9939c80SYuval Mintz u32 eee_adv = 0; 2026e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 2027e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 2028e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 2029e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 2030e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 2031e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 2032e9939c80SYuval Mintz 2033e9939c80SYuval Mintz return eee_adv << shift; 2034e9939c80SYuval Mintz } 2035e9939c80SYuval Mintz 2036e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2037e9939c80SYuval Mintz { 2038e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2039e9939c80SYuval Mintz u32 eee_cfg; 2040e9939c80SYuval Mintz 2041e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2042e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2043e9939c80SYuval Mintz return -EOPNOTSUPP; 2044e9939c80SYuval Mintz } 2045e9939c80SYuval Mintz 204608e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2047e9939c80SYuval Mintz 2048e9939c80SYuval Mintz edata->supported = 2049e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2050e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 2051e9939c80SYuval Mintz 2052e9939c80SYuval Mintz edata->advertised = 2053e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2054e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2055e9939c80SYuval Mintz edata->lp_advertised = 2056e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2057e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2058e9939c80SYuval Mintz 2059e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 2060e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2061e9939c80SYuval Mintz 2062e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2063e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2064e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2065e9939c80SYuval Mintz 2066e9939c80SYuval Mintz return 0; 2067e9939c80SYuval Mintz } 2068e9939c80SYuval Mintz 2069e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2070e9939c80SYuval Mintz { 2071e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2072e9939c80SYuval Mintz u32 eee_cfg; 2073e9939c80SYuval Mintz u32 advertised; 2074e9939c80SYuval Mintz 2075e9939c80SYuval Mintz if (IS_MF(bp)) 2076e9939c80SYuval Mintz return 0; 2077e9939c80SYuval Mintz 2078e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2079e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2080e9939c80SYuval Mintz return -EOPNOTSUPP; 2081e9939c80SYuval Mintz } 2082e9939c80SYuval Mintz 208308e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2084e9939c80SYuval Mintz 2085e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2086e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2087e9939c80SYuval Mintz return -EOPNOTSUPP; 2088e9939c80SYuval Mintz } 2089e9939c80SYuval Mintz 2090e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 2091e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2092e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2093e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2094efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 2095e9939c80SYuval Mintz return -EINVAL; 2096e9939c80SYuval Mintz } 2097e9939c80SYuval Mintz 2098e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2099e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2100e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 2101e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 2102e9939c80SYuval Mintz return -EINVAL; 2103e9939c80SYuval Mintz } 2104e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 2105e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2106e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2107e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 2108e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2109e9939c80SYuval Mintz return -EINVAL; 2110e9939c80SYuval Mintz } 2111e9939c80SYuval Mintz 2112e9939c80SYuval Mintz /* All is well; Apply changes*/ 2113e9939c80SYuval Mintz if (edata->eee_enabled) 2114e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2115e9939c80SYuval Mintz else 2116e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2117e9939c80SYuval Mintz 2118e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 2119e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2120e9939c80SYuval Mintz else 2121e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2122e9939c80SYuval Mintz 2123e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2124e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2125e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 2126e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 2127e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 2128e9939c80SYuval Mintz 212916a5fd92SYuval Mintz /* Restart link to propagate changes */ 2130e9939c80SYuval Mintz if (netif_running(dev)) { 2131e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 21325d07d868SYuval Mintz bnx2x_force_link_reset(bp); 2133e9939c80SYuval Mintz bnx2x_link_set(bp); 2134e9939c80SYuval Mintz } 2135e9939c80SYuval Mintz 2136e9939c80SYuval Mintz return 0; 2137e9939c80SYuval Mintz } 2138e9939c80SYuval Mintz 2139adfc5217SJeff Kirsher enum { 2140adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 2141adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 2142adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 2143adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 2144adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 2145adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 2146adfc5217SJeff Kirsher }; 2147adfc5217SJeff Kirsher 2148adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2149adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2150adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2151adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2152adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2153adfc5217SJeff Kirsher 2154adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2155adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2156adfc5217SJeff Kirsher 2157adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 2158adfc5217SJeff Kirsher { 2159adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 2160adfc5217SJeff Kirsher u32 wr_val = 0, hw; 2161adfc5217SJeff Kirsher int port = BP_PORT(bp); 2162adfc5217SJeff Kirsher static const struct { 2163adfc5217SJeff Kirsher u32 hw; 2164adfc5217SJeff Kirsher u32 offset0; 2165adfc5217SJeff Kirsher u32 offset1; 2166adfc5217SJeff Kirsher u32 mask; 2167adfc5217SJeff Kirsher } reg_tbl[] = { 2168adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 2169adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2170adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2171adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2172adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 2173adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 2174adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2175adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2176adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2177adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2178adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 2179adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2180adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2181adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2182adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2183adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2184adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2185adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2186adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2187adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2188adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 2189adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2190adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2191adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2192adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2193adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 2194adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2195adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2196adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2197adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2198adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2199adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2200adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2201adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2202adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2203adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2204adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2205adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2206adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2207adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2208adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2209adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2210adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2211adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2212adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2213adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2214adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2215adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2216adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2217adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2218adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2219adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2220adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2221adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2222adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2223adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2224adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2225adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2226adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2227adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2228adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 2229adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2230adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2231adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2232adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2233adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2234adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2235adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2236adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2237adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2238adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2239adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2240adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2241adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2242adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2243adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2244adfc5217SJeff Kirsher 2245adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2246adfc5217SJeff Kirsher }; 2247adfc5217SJeff Kirsher 22483fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 224951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 225051c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2251adfc5217SJeff Kirsher return rc; 225251c1a580SMerav Sicron } 2253adfc5217SJeff Kirsher 2254adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2255adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 2256adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2257adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 2258adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2259adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 2260adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 2261adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 2262adfc5217SJeff Kirsher else /* e3 A0 */ 2263adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 2264adfc5217SJeff Kirsher 2265adfc5217SJeff Kirsher /* Repeat the test twice: 226607ba6af4SMiriam Shitrit * First by writing 0x00000000, second by writing 0xffffffff 226707ba6af4SMiriam Shitrit */ 2268adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 2269adfc5217SJeff Kirsher 2270adfc5217SJeff Kirsher switch (idx) { 2271adfc5217SJeff Kirsher case 0: 2272adfc5217SJeff Kirsher wr_val = 0; 2273adfc5217SJeff Kirsher break; 2274adfc5217SJeff Kirsher case 1: 2275adfc5217SJeff Kirsher wr_val = 0xffffffff; 2276adfc5217SJeff Kirsher break; 2277adfc5217SJeff Kirsher } 2278adfc5217SJeff Kirsher 2279adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2280adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 2281adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 2282adfc5217SJeff Kirsher continue; 2283adfc5217SJeff Kirsher 2284adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2285adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 2286adfc5217SJeff Kirsher 2287adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 2288adfc5217SJeff Kirsher 2289adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 2290adfc5217SJeff Kirsher 2291adfc5217SJeff Kirsher val = REG_RD(bp, offset); 2292adfc5217SJeff Kirsher 2293adfc5217SJeff Kirsher /* Restore the original register's value */ 2294adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 2295adfc5217SJeff Kirsher 2296adfc5217SJeff Kirsher /* verify value is as expected */ 2297adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 229851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2299adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2300adfc5217SJeff Kirsher offset, val, wr_val, mask); 2301adfc5217SJeff Kirsher goto test_reg_exit; 2302adfc5217SJeff Kirsher } 2303adfc5217SJeff Kirsher } 2304adfc5217SJeff Kirsher } 2305adfc5217SJeff Kirsher 2306adfc5217SJeff Kirsher rc = 0; 2307adfc5217SJeff Kirsher 2308adfc5217SJeff Kirsher test_reg_exit: 2309adfc5217SJeff Kirsher return rc; 2310adfc5217SJeff Kirsher } 2311adfc5217SJeff Kirsher 2312adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 2313adfc5217SJeff Kirsher { 2314adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 2315adfc5217SJeff Kirsher u32 val, index; 2316adfc5217SJeff Kirsher static const struct { 2317adfc5217SJeff Kirsher u32 offset; 2318adfc5217SJeff Kirsher int size; 2319adfc5217SJeff Kirsher } mem_tbl[] = { 2320adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2321adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2322adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2323adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2324adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2325adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2326adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2327adfc5217SJeff Kirsher 2328adfc5217SJeff Kirsher { 0xffffffff, 0 } 2329adfc5217SJeff Kirsher }; 2330adfc5217SJeff Kirsher 2331adfc5217SJeff Kirsher static const struct { 2332adfc5217SJeff Kirsher char *name; 2333adfc5217SJeff Kirsher u32 offset; 2334adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2335adfc5217SJeff Kirsher } prty_tbl[] = { 2336adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2337adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2338adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2339adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 2340adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2341adfc5217SJeff Kirsher {0, 0, 0, 0} }, 2342adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2343adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2344adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2345adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2346adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2347adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 2348adfc5217SJeff Kirsher 2349adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 2350adfc5217SJeff Kirsher }; 2351adfc5217SJeff Kirsher 23523fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 235351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 235451c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2355adfc5217SJeff Kirsher return rc; 235651c1a580SMerav Sicron } 2357adfc5217SJeff Kirsher 2358adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2359adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 2360adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2361adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 2362adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2363adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 2364adfc5217SJeff Kirsher else /* e3 */ 2365adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 2366adfc5217SJeff Kirsher 2367adfc5217SJeff Kirsher /* pre-Check the parity status */ 2368adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2369adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2370adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 237151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2372adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2373adfc5217SJeff Kirsher goto test_mem_exit; 2374adfc5217SJeff Kirsher } 2375adfc5217SJeff Kirsher } 2376adfc5217SJeff Kirsher 2377adfc5217SJeff Kirsher /* Go through all the memories */ 2378adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2379adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 2380adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 2381adfc5217SJeff Kirsher 2382adfc5217SJeff Kirsher /* Check the parity status */ 2383adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2384adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2385adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 238651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2387adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2388adfc5217SJeff Kirsher goto test_mem_exit; 2389adfc5217SJeff Kirsher } 2390adfc5217SJeff Kirsher } 2391adfc5217SJeff Kirsher 2392adfc5217SJeff Kirsher rc = 0; 2393adfc5217SJeff Kirsher 2394adfc5217SJeff Kirsher test_mem_exit: 2395adfc5217SJeff Kirsher return rc; 2396adfc5217SJeff Kirsher } 2397adfc5217SJeff Kirsher 2398adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2399adfc5217SJeff Kirsher { 2400adfc5217SJeff Kirsher int cnt = 1400; 2401adfc5217SJeff Kirsher 2402adfc5217SJeff Kirsher if (link_up) { 2403adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2404adfc5217SJeff Kirsher msleep(20); 2405adfc5217SJeff Kirsher 2406adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 240751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 24088970b2e4SMerav Sicron 24098970b2e4SMerav Sicron cnt = 1400; 24108970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 24118970b2e4SMerav Sicron msleep(20); 24128970b2e4SMerav Sicron 24138970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 24148970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24158970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2416adfc5217SJeff Kirsher } 2417adfc5217SJeff Kirsher } 2418adfc5217SJeff Kirsher 2419adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2420adfc5217SJeff Kirsher { 2421adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2422adfc5217SJeff Kirsher struct sk_buff *skb; 2423adfc5217SJeff Kirsher unsigned char *packet; 2424adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2425adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 242665565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2427adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2428adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2429b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2430adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2431adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2432adfc5217SJeff Kirsher dma_addr_t mapping; 2433adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2434adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2435adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2436adfc5217SJeff Kirsher u16 len; 2437adfc5217SJeff Kirsher int rc = -ENODEV; 2438e52fcb24SEric Dumazet u8 *data; 24398970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 24408970b2e4SMerav Sicron txdata->txq_index); 2441adfc5217SJeff Kirsher 2442adfc5217SJeff Kirsher /* check the loopback mode */ 2443adfc5217SJeff Kirsher switch (loopback_mode) { 2444adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 24458970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 24468970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2447adfc5217SJeff Kirsher return -EINVAL; 24488970b2e4SMerav Sicron } 2449adfc5217SJeff Kirsher break; 2450adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 245132911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 245232911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 245332911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 245432911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 245532911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 245632911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 245732911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 245832911333SYaniv Rosner else 245932911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 246032911333SYaniv Rosner } else 246132911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 246232911333SYaniv Rosner 2463adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2464adfc5217SJeff Kirsher break; 24658970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 24668970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 24678970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24688970b2e4SMerav Sicron "Can't configure external loopback\n"); 24698970b2e4SMerav Sicron return -EINVAL; 24708970b2e4SMerav Sicron } 24718970b2e4SMerav Sicron break; 2472adfc5217SJeff Kirsher default: 247351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2474adfc5217SJeff Kirsher return -EINVAL; 2475adfc5217SJeff Kirsher } 2476adfc5217SJeff Kirsher 2477adfc5217SJeff Kirsher /* prepare the loopback packet */ 2478adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2479adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2480adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2481adfc5217SJeff Kirsher if (!skb) { 248251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2483adfc5217SJeff Kirsher rc = -ENOMEM; 2484adfc5217SJeff Kirsher goto test_loopback_exit; 2485adfc5217SJeff Kirsher } 2486adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2487adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2488c7bf7169SJoe Perches eth_zero_addr(packet + ETH_ALEN); 2489adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2490adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2491adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2492adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2493adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2494adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2495adfc5217SJeff Kirsher rc = -ENOMEM; 2496adfc5217SJeff Kirsher dev_kfree_skb(skb); 249751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2498adfc5217SJeff Kirsher goto test_loopback_exit; 2499adfc5217SJeff Kirsher } 2500adfc5217SJeff Kirsher 2501adfc5217SJeff Kirsher /* send the loopback packet */ 2502adfc5217SJeff Kirsher num_pkts = 0; 2503adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2504adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2505adfc5217SJeff Kirsher 250673dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 250773dbb5e1SDmitry Kravkov 2508adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2509adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2510adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2511adfc5217SJeff Kirsher tx_buf->skb = skb; 2512adfc5217SJeff Kirsher tx_buf->flags = 0; 2513adfc5217SJeff Kirsher 2514adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2515adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2516adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2517adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2518adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2519adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2520adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2521adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2522adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2523adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2524adfc5217SJeff Kirsher 1); 252596bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 252696bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 252796bed4b9SYuval Mintz 0); 2528adfc5217SJeff Kirsher 2529adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2530adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2531adfc5217SJeff Kirsher 253296bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 253396bed4b9SYuval Mintz u16 global_data = 0; 253496bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 253596bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2536adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 253796bed4b9SYuval Mintz SET_FLAG(global_data, 253896bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 253996bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 254096bed4b9SYuval Mintz } else { 254196bed4b9SYuval Mintz u32 parsing_data = 0; 254296bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 254396bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 254496bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 254596bed4b9SYuval Mintz SET_FLAG(parsing_data, 254696bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 254796bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 254896bed4b9SYuval Mintz } 2549adfc5217SJeff Kirsher wmb(); 2550adfc5217SJeff Kirsher 2551adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2552adfc5217SJeff Kirsher barrier(); 2553adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2554adfc5217SJeff Kirsher 2555adfc5217SJeff Kirsher mmiowb(); 2556adfc5217SJeff Kirsher barrier(); 2557adfc5217SJeff Kirsher 2558adfc5217SJeff Kirsher num_pkts++; 2559adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2560adfc5217SJeff Kirsher 2561adfc5217SJeff Kirsher udelay(100); 2562adfc5217SJeff Kirsher 2563adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2564adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2565adfc5217SJeff Kirsher goto test_loopback_exit; 2566adfc5217SJeff Kirsher 2567adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2568adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2569adfc5217SJeff Kirsher * disabled. 2570adfc5217SJeff Kirsher */ 2571adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2572adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2573adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2574adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2575adfc5217SJeff Kirsher */ 2576adfc5217SJeff Kirsher local_bh_disable(); 2577adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2578adfc5217SJeff Kirsher local_bh_enable(); 2579adfc5217SJeff Kirsher } 2580adfc5217SJeff Kirsher 2581adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2582adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2583adfc5217SJeff Kirsher goto test_loopback_exit; 2584adfc5217SJeff Kirsher 2585b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2586adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2587adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2588adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2589adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2590adfc5217SJeff Kirsher 2591621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2592adfc5217SJeff Kirsher if (len != pkt_size) 2593adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2594adfc5217SJeff Kirsher 2595adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2596adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2597adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2598adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2599e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2600adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2601e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2602adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2603adfc5217SJeff Kirsher 2604adfc5217SJeff Kirsher rc = 0; 2605adfc5217SJeff Kirsher 2606adfc5217SJeff Kirsher test_loopback_rx_exit: 2607adfc5217SJeff Kirsher 2608adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2609adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2610adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2611adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2612adfc5217SJeff Kirsher 2613adfc5217SJeff Kirsher /* Update producers */ 2614adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2615adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2616adfc5217SJeff Kirsher 2617adfc5217SJeff Kirsher test_loopback_exit: 2618adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2619adfc5217SJeff Kirsher 2620adfc5217SJeff Kirsher return rc; 2621adfc5217SJeff Kirsher } 2622adfc5217SJeff Kirsher 2623adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2624adfc5217SJeff Kirsher { 2625adfc5217SJeff Kirsher int rc = 0, res; 2626adfc5217SJeff Kirsher 2627adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2628adfc5217SJeff Kirsher return rc; 2629adfc5217SJeff Kirsher 2630adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2631adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2632adfc5217SJeff Kirsher 2633adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2634adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2635adfc5217SJeff Kirsher 2636adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2637adfc5217SJeff Kirsher if (res) { 263851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2639adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2640adfc5217SJeff Kirsher } 2641adfc5217SJeff Kirsher 2642adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2643adfc5217SJeff Kirsher if (res) { 264451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2645adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2646adfc5217SJeff Kirsher } 2647adfc5217SJeff Kirsher 2648adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2649adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2650adfc5217SJeff Kirsher 2651adfc5217SJeff Kirsher return rc; 2652adfc5217SJeff Kirsher } 2653adfc5217SJeff Kirsher 26548970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 26558970b2e4SMerav Sicron { 26568970b2e4SMerav Sicron int rc; 26578970b2e4SMerav Sicron u8 is_serdes = 26588970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 26598970b2e4SMerav Sicron 26608970b2e4SMerav Sicron if (BP_NOMCP(bp)) 26618970b2e4SMerav Sicron return -ENODEV; 26628970b2e4SMerav Sicron 26638970b2e4SMerav Sicron if (!netif_running(bp->dev)) 26648970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 26658970b2e4SMerav Sicron 26665d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 26678970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 26688970b2e4SMerav Sicron if (rc) { 26698970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26708970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 26718970b2e4SMerav Sicron return -ENODEV; 26728970b2e4SMerav Sicron } 26738970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 26748970b2e4SMerav Sicron 26758970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 26768970b2e4SMerav Sicron 26778970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 26788970b2e4SMerav Sicron if (rc) 26798970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 26808970b2e4SMerav Sicron 26818970b2e4SMerav Sicron bnx2x_netif_start(bp); 26828970b2e4SMerav Sicron 26838970b2e4SMerav Sicron return rc; 26848970b2e4SMerav Sicron } 26858970b2e4SMerav Sicron 2686edb944d2SDmitry Kravkov struct code_entry { 2687edb944d2SDmitry Kravkov u32 sram_start_addr; 2688edb944d2SDmitry Kravkov u32 code_attribute; 2689edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_MASK 0xf0800003 2690edb944d2SDmitry Kravkov #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2691edb944d2SDmitry Kravkov #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2692edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2693edb944d2SDmitry Kravkov u32 nvm_start_addr; 2694edb944d2SDmitry Kravkov }; 2695edb944d2SDmitry Kravkov 2696edb944d2SDmitry Kravkov #define CODE_ENTRY_MAX 16 2697edb944d2SDmitry Kravkov #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2698edb944d2SDmitry Kravkov #define MAX_IMAGES_IN_EXTENDED_DIR 64 2699edb944d2SDmitry Kravkov #define NVRAM_DIR_OFFSET 0x14 2700edb944d2SDmitry Kravkov 2701edb944d2SDmitry Kravkov #define EXTENDED_DIR_EXISTS(code) \ 2702edb944d2SDmitry Kravkov ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2703edb944d2SDmitry Kravkov (code & CODE_IMAGE_LENGTH_MASK) != 0) 2704edb944d2SDmitry Kravkov 2705adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2706edb944d2SDmitry Kravkov #define CRC_BUFF_SIZE 256 2707edb944d2SDmitry Kravkov 2708edb944d2SDmitry Kravkov static int bnx2x_nvram_crc(struct bnx2x *bp, 2709edb944d2SDmitry Kravkov int offset, 2710edb944d2SDmitry Kravkov int size, 2711edb944d2SDmitry Kravkov u8 *buff) 2712edb944d2SDmitry Kravkov { 2713edb944d2SDmitry Kravkov u32 crc = ~0; 2714edb944d2SDmitry Kravkov int rc = 0, done = 0; 2715edb944d2SDmitry Kravkov 2716edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2717edb944d2SDmitry Kravkov "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2718edb944d2SDmitry Kravkov 2719edb944d2SDmitry Kravkov while (done < size) { 2720edb944d2SDmitry Kravkov int count = min_t(int, size - done, CRC_BUFF_SIZE); 2721edb944d2SDmitry Kravkov 2722edb944d2SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2723edb944d2SDmitry Kravkov 2724edb944d2SDmitry Kravkov if (rc) 2725edb944d2SDmitry Kravkov return rc; 2726edb944d2SDmitry Kravkov 2727edb944d2SDmitry Kravkov crc = crc32_le(crc, buff, count); 2728edb944d2SDmitry Kravkov done += count; 2729edb944d2SDmitry Kravkov } 2730edb944d2SDmitry Kravkov 2731edb944d2SDmitry Kravkov if (crc != CRC32_RESIDUAL) 2732edb944d2SDmitry Kravkov rc = -EINVAL; 2733edb944d2SDmitry Kravkov 2734edb944d2SDmitry Kravkov return rc; 2735edb944d2SDmitry Kravkov } 2736edb944d2SDmitry Kravkov 2737edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2738edb944d2SDmitry Kravkov struct code_entry *entry, 2739edb944d2SDmitry Kravkov u8 *buff) 2740edb944d2SDmitry Kravkov { 2741edb944d2SDmitry Kravkov size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2742edb944d2SDmitry Kravkov u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2743edb944d2SDmitry Kravkov int rc; 2744edb944d2SDmitry Kravkov 2745edb944d2SDmitry Kravkov /* Zero-length images and AFEX profiles do not have CRC */ 2746edb944d2SDmitry Kravkov if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2747edb944d2SDmitry Kravkov return 0; 2748edb944d2SDmitry Kravkov 2749edb944d2SDmitry Kravkov rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2750edb944d2SDmitry Kravkov if (rc) 2751edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2752edb944d2SDmitry Kravkov "image %x has failed crc test (rc %d)\n", type, rc); 2753edb944d2SDmitry Kravkov 2754edb944d2SDmitry Kravkov return rc; 2755edb944d2SDmitry Kravkov } 2756edb944d2SDmitry Kravkov 2757edb944d2SDmitry Kravkov static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2758edb944d2SDmitry Kravkov { 2759edb944d2SDmitry Kravkov int rc; 2760edb944d2SDmitry Kravkov struct code_entry entry; 2761edb944d2SDmitry Kravkov 2762edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2763edb944d2SDmitry Kravkov if (rc) 2764edb944d2SDmitry Kravkov return rc; 2765edb944d2SDmitry Kravkov 2766edb944d2SDmitry Kravkov return bnx2x_test_nvram_dir(bp, &entry, buff); 2767edb944d2SDmitry Kravkov } 2768edb944d2SDmitry Kravkov 2769edb944d2SDmitry Kravkov static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2770edb944d2SDmitry Kravkov { 2771edb944d2SDmitry Kravkov u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2772edb944d2SDmitry Kravkov struct code_entry entry; 2773edb944d2SDmitry Kravkov int i; 2774edb944d2SDmitry Kravkov 2775edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 2776edb944d2SDmitry Kravkov dir_offset + 2777edb944d2SDmitry Kravkov sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2778edb944d2SDmitry Kravkov (u32 *)&entry, sizeof(entry)); 2779edb944d2SDmitry Kravkov if (rc) 2780edb944d2SDmitry Kravkov return rc; 2781edb944d2SDmitry Kravkov 2782edb944d2SDmitry Kravkov if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2783edb944d2SDmitry Kravkov return 0; 2784edb944d2SDmitry Kravkov 2785edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2786edb944d2SDmitry Kravkov &cnt, sizeof(u32)); 2787edb944d2SDmitry Kravkov if (rc) 2788edb944d2SDmitry Kravkov return rc; 2789edb944d2SDmitry Kravkov 2790edb944d2SDmitry Kravkov dir_offset = entry.nvm_start_addr + 8; 2791edb944d2SDmitry Kravkov 2792edb944d2SDmitry Kravkov for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2793edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2794edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2795edb944d2SDmitry Kravkov buff); 2796edb944d2SDmitry Kravkov if (rc) 2797edb944d2SDmitry Kravkov return rc; 2798edb944d2SDmitry Kravkov } 2799edb944d2SDmitry Kravkov 2800edb944d2SDmitry Kravkov return 0; 2801edb944d2SDmitry Kravkov } 2802edb944d2SDmitry Kravkov 2803edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2804edb944d2SDmitry Kravkov { 2805edb944d2SDmitry Kravkov u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2806edb944d2SDmitry Kravkov int i; 2807edb944d2SDmitry Kravkov 2808edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2809edb944d2SDmitry Kravkov 2810edb944d2SDmitry Kravkov for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2811edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2812edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2813edb944d2SDmitry Kravkov buff); 2814edb944d2SDmitry Kravkov if (rc) 2815edb944d2SDmitry Kravkov return rc; 2816edb944d2SDmitry Kravkov } 2817edb944d2SDmitry Kravkov 2818edb944d2SDmitry Kravkov return bnx2x_test_nvram_ext_dirs(bp, buff); 2819edb944d2SDmitry Kravkov } 2820edb944d2SDmitry Kravkov 2821edb944d2SDmitry Kravkov struct crc_pair { 2822edb944d2SDmitry Kravkov int offset; 2823edb944d2SDmitry Kravkov int size; 2824edb944d2SDmitry Kravkov }; 2825edb944d2SDmitry Kravkov 2826edb944d2SDmitry Kravkov static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2827edb944d2SDmitry Kravkov const struct crc_pair *nvram_tbl, u8 *buf) 2828edb944d2SDmitry Kravkov { 2829edb944d2SDmitry Kravkov int i; 2830edb944d2SDmitry Kravkov 2831edb944d2SDmitry Kravkov for (i = 0; nvram_tbl[i].size; i++) { 2832edb944d2SDmitry Kravkov int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2833edb944d2SDmitry Kravkov nvram_tbl[i].size, buf); 2834edb944d2SDmitry Kravkov if (rc) { 2835edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2836edb944d2SDmitry Kravkov "nvram_tbl[%d] has failed crc test (rc %d)\n", 2837edb944d2SDmitry Kravkov i, rc); 2838edb944d2SDmitry Kravkov return rc; 2839edb944d2SDmitry Kravkov } 2840edb944d2SDmitry Kravkov } 2841edb944d2SDmitry Kravkov 2842edb944d2SDmitry Kravkov return 0; 2843edb944d2SDmitry Kravkov } 2844adfc5217SJeff Kirsher 2845adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2846adfc5217SJeff Kirsher { 2847edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl[] = { 2848adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2849adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2850adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2851adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2852adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2853adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2854adfc5217SJeff Kirsher { 0, 0 } 2855adfc5217SJeff Kirsher }; 2856edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl2[] = { 2857edb944d2SDmitry Kravkov { 0x7e8, 0x350 }, /* manuf_info2 */ 2858edb944d2SDmitry Kravkov { 0xb38, 0xf0 }, /* feature_info */ 2859edb944d2SDmitry Kravkov { 0, 0 } 2860edb944d2SDmitry Kravkov }; 2861edb944d2SDmitry Kravkov 286285640952SDmitry Kravkov u8 *buf; 2863edb944d2SDmitry Kravkov int rc; 2864edb944d2SDmitry Kravkov u32 magic; 2865adfc5217SJeff Kirsher 2866adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2867adfc5217SJeff Kirsher return 0; 2868adfc5217SJeff Kirsher 2869edb944d2SDmitry Kravkov buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2870afa13b4bSMintz Yuval if (!buf) { 287151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2872afa13b4bSMintz Yuval rc = -ENOMEM; 2873afa13b4bSMintz Yuval goto test_nvram_exit; 2874afa13b4bSMintz Yuval } 2875afa13b4bSMintz Yuval 287685640952SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2877adfc5217SJeff Kirsher if (rc) { 287851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 287951c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2880adfc5217SJeff Kirsher goto test_nvram_exit; 2881adfc5217SJeff Kirsher } 2882adfc5217SJeff Kirsher 2883adfc5217SJeff Kirsher if (magic != 0x669955aa) { 288451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 288551c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2886adfc5217SJeff Kirsher rc = -ENODEV; 2887adfc5217SJeff Kirsher goto test_nvram_exit; 2888adfc5217SJeff Kirsher } 2889adfc5217SJeff Kirsher 2890edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2891edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2892edb944d2SDmitry Kravkov if (rc) 2893adfc5217SJeff Kirsher goto test_nvram_exit; 2894adfc5217SJeff Kirsher 2895edb944d2SDmitry Kravkov if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2896edb944d2SDmitry Kravkov u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2897edb944d2SDmitry Kravkov SHARED_HW_CFG_HIDE_PORT1; 2898edb944d2SDmitry Kravkov 2899edb944d2SDmitry Kravkov if (!hide) { 290051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2901edb944d2SDmitry Kravkov "Port 1 CRC test-set\n"); 2902edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2903edb944d2SDmitry Kravkov if (rc) 2904adfc5217SJeff Kirsher goto test_nvram_exit; 2905adfc5217SJeff Kirsher } 2906adfc5217SJeff Kirsher } 2907adfc5217SJeff Kirsher 2908edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_dirs(bp, buf); 2909edb944d2SDmitry Kravkov 2910adfc5217SJeff Kirsher test_nvram_exit: 2911afa13b4bSMintz Yuval kfree(buf); 2912adfc5217SJeff Kirsher return rc; 2913adfc5217SJeff Kirsher } 2914adfc5217SJeff Kirsher 2915adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2916adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2917adfc5217SJeff Kirsher { 29183b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2919adfc5217SJeff Kirsher 292051c1a580SMerav Sicron if (!netif_running(bp->dev)) { 292151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 292251c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2923adfc5217SJeff Kirsher return -ENODEV; 292451c1a580SMerav Sicron } 2925adfc5217SJeff Kirsher 292615192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2927adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2928adfc5217SJeff Kirsher 2929adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2930adfc5217SJeff Kirsher 2931adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2932adfc5217SJeff Kirsher } 2933adfc5217SJeff Kirsher 2934adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2935adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2936adfc5217SJeff Kirsher { 2937adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2938a336ca7cSYaniv Rosner u8 is_serdes, link_up; 2939a336ca7cSYaniv Rosner int rc, cnt = 0; 2940cf2c1df6SMerav Sicron 2941909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 2942909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, 2943909d9faaSYuval Mintz "VFs are enabled, can not perform self test\n"); 2944909d9faaSYuval Mintz return; 2945909d9faaSYuval Mintz } 2946909d9faaSYuval Mintz 2947adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 294851c1a580SMerav Sicron netdev_err(bp->dev, 294951c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2950adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2951adfc5217SJeff Kirsher return; 2952adfc5217SJeff Kirsher } 29532de67439SYuval Mintz 29548970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29558970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 29568970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 29578970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2958adfc5217SJeff Kirsher 2959cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2960adfc5217SJeff Kirsher 2961bd8e012bSYuval Mintz if (bnx2x_test_nvram(bp) != 0) { 2962bd8e012bSYuval Mintz if (!IS_MF(bp)) 2963bd8e012bSYuval Mintz buf[4] = 1; 2964bd8e012bSYuval Mintz else 2965bd8e012bSYuval Mintz buf[0] = 1; 2966bd8e012bSYuval Mintz etest->flags |= ETH_TEST_FL_FAILED; 2967bd8e012bSYuval Mintz } 2968bd8e012bSYuval Mintz 2969cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2970bd8e012bSYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2971adfc5217SJeff Kirsher return; 2972cf2c1df6SMerav Sicron } 2973adfc5217SJeff Kirsher 2974adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2975a336ca7cSYaniv Rosner link_up = bp->link_vars.link_up; 2976cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2977cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2978adfc5217SJeff Kirsher int port = BP_PORT(bp); 2979adfc5217SJeff Kirsher u32 val; 2980adfc5217SJeff Kirsher 2981adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2982adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2983adfc5217SJeff Kirsher /* disable input for TX port IF */ 2984adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2985adfc5217SJeff Kirsher 29865d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2987cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2988cf2c1df6SMerav Sicron if (rc) { 2989cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2990cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2991cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2992cf2c1df6SMerav Sicron return; 2993cf2c1df6SMerav Sicron } 2994cf2c1df6SMerav Sicron 2995adfc5217SJeff Kirsher /* wait until link state is restored */ 2996adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2997adfc5217SJeff Kirsher 2998adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2999adfc5217SJeff Kirsher buf[0] = 1; 3000adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3001adfc5217SJeff Kirsher } 3002adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 3003adfc5217SJeff Kirsher buf[1] = 1; 3004adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3005adfc5217SJeff Kirsher } 3006adfc5217SJeff Kirsher 30078970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3008adfc5217SJeff Kirsher if (buf[2] != 0) 3009adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3010adfc5217SJeff Kirsher 30118970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 30128970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 30138970b2e4SMerav Sicron if (buf[3] != 0) 30148970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 30158970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 30168970b2e4SMerav Sicron } 30178970b2e4SMerav Sicron 30185d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3019adfc5217SJeff Kirsher 3020adfc5217SJeff Kirsher /* restore input for TX port IF */ 3021adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3022cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3023cf2c1df6SMerav Sicron if (rc) { 3024cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 3025cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 3026cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 3027cf2c1df6SMerav Sicron return; 3028cf2c1df6SMerav Sicron } 3029adfc5217SJeff Kirsher /* wait until link state is restored */ 3030adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 3031adfc5217SJeff Kirsher } 3032bd8e012bSYuval Mintz 3033adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 3034cf2c1df6SMerav Sicron if (!IS_MF(bp)) 30358970b2e4SMerav Sicron buf[5] = 1; 3036cf2c1df6SMerav Sicron else 3037cf2c1df6SMerav Sicron buf[1] = 1; 3038adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3039adfc5217SJeff Kirsher } 3040adfc5217SJeff Kirsher 3041a336ca7cSYaniv Rosner if (link_up) { 3042a336ca7cSYaniv Rosner cnt = 100; 3043a336ca7cSYaniv Rosner while (bnx2x_link_test(bp, is_serdes) && --cnt) 3044a336ca7cSYaniv Rosner msleep(20); 3045a336ca7cSYaniv Rosner } 3046a336ca7cSYaniv Rosner 3047a336ca7cSYaniv Rosner if (!cnt) { 3048cf2c1df6SMerav Sicron if (!IS_MF(bp)) 30498970b2e4SMerav Sicron buf[6] = 1; 3050cf2c1df6SMerav Sicron else 3051cf2c1df6SMerav Sicron buf[2] = 1; 3052adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3053adfc5217SJeff Kirsher } 3054adfc5217SJeff Kirsher } 3055adfc5217SJeff Kirsher 3056adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 3057adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 3058adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 3059d8361051SYuval Mintz #define HIDE_PORT_STAT(bp) \ 3060d8361051SYuval Mintz ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \ 3061d8361051SYuval Mintz IS_VF(bp)) 3062adfc5217SJeff Kirsher 3063adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 3064adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 3065adfc5217SJeff Kirsher */ 30661191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 3067adfc5217SJeff Kirsher { 3068adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 3069adfc5217SJeff Kirsher } 3070adfc5217SJeff Kirsher 3071adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3072adfc5217SJeff Kirsher { 3073adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 30743521b419SYuval Mintz int i, num_strings = 0; 3075adfc5217SJeff Kirsher 3076adfc5217SJeff Kirsher switch (stringset) { 3077adfc5217SJeff Kirsher case ETH_SS_STATS: 3078adfc5217SJeff Kirsher if (is_multi(bp)) { 30793521b419SYuval Mintz num_strings = bnx2x_num_stat_queues(bp) * 3080adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 3081d5e83632SYuval Mintz } else 30823521b419SYuval Mintz num_strings = 0; 3083d8361051SYuval Mintz if (HIDE_PORT_STAT(bp)) { 3084adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 3085adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 30863521b419SYuval Mintz num_strings++; 3087adfc5217SJeff Kirsher } else 30883521b419SYuval Mintz num_strings += BNX2X_NUM_STATS; 3089d5e83632SYuval Mintz 30903521b419SYuval Mintz return num_strings; 3091adfc5217SJeff Kirsher 3092adfc5217SJeff Kirsher case ETH_SS_TEST: 3093cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 3094adfc5217SJeff Kirsher 30953521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 30963521b419SYuval Mintz return BNX2X_PRI_FLAG_LEN; 30973521b419SYuval Mintz 3098adfc5217SJeff Kirsher default: 3099adfc5217SJeff Kirsher return -EINVAL; 3100adfc5217SJeff Kirsher } 3101adfc5217SJeff Kirsher } 3102adfc5217SJeff Kirsher 31033521b419SYuval Mintz static u32 bnx2x_get_private_flags(struct net_device *dev) 31043521b419SYuval Mintz { 31053521b419SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 31063521b419SYuval Mintz u32 flags = 0; 31073521b419SYuval Mintz 31083521b419SYuval Mintz flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 31093521b419SYuval Mintz flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 31103521b419SYuval Mintz flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 31113521b419SYuval Mintz 31123521b419SYuval Mintz return flags; 31133521b419SYuval Mintz } 31143521b419SYuval Mintz 3115adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3116adfc5217SJeff Kirsher { 3117adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 31185889335cSMerav Sicron int i, j, k, start; 3119adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 3120adfc5217SJeff Kirsher 3121adfc5217SJeff Kirsher switch (stringset) { 3122adfc5217SJeff Kirsher case ETH_SS_STATS: 3123adfc5217SJeff Kirsher k = 0; 3124d5e83632SYuval Mintz if (is_multi(bp)) { 3125adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 3126adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 3127adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 3128adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3129adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3130adfc5217SJeff Kirsher ETH_GSTRING_LEN, 3131adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 3132adfc5217SJeff Kirsher queue_name); 3133adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3134adfc5217SJeff Kirsher } 3135d5e83632SYuval Mintz } 3136d5e83632SYuval Mintz 3137adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3138d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3139adfc5217SJeff Kirsher continue; 3140d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3141adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 3142adfc5217SJeff Kirsher j++; 3143adfc5217SJeff Kirsher } 3144d5e83632SYuval Mintz 3145adfc5217SJeff Kirsher break; 3146adfc5217SJeff Kirsher 3147adfc5217SJeff Kirsher case ETH_SS_TEST: 3148cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 3149cf2c1df6SMerav Sicron if (!IS_MF(bp)) 3150cf2c1df6SMerav Sicron start = 0; 3151cf2c1df6SMerav Sicron else 3152cf2c1df6SMerav Sicron start = 4; 31535889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 31545889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 31553521b419SYuval Mintz break; 31563521b419SYuval Mintz 31573521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 31583521b419SYuval Mintz memcpy(buf, bnx2x_private_arr, 31593521b419SYuval Mintz ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 31603521b419SYuval Mintz break; 3161adfc5217SJeff Kirsher } 3162adfc5217SJeff Kirsher } 3163adfc5217SJeff Kirsher 3164adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 3165adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 3166adfc5217SJeff Kirsher { 3167adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3168adfc5217SJeff Kirsher u32 *hw_stats, *offset; 3169d5e83632SYuval Mintz int i, j, k = 0; 3170adfc5217SJeff Kirsher 3171adfc5217SJeff Kirsher if (is_multi(bp)) { 3172adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 317315192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3174adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3175adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 3176adfc5217SJeff Kirsher /* skip this counter */ 3177adfc5217SJeff Kirsher buf[k + j] = 0; 3178adfc5217SJeff Kirsher continue; 3179adfc5217SJeff Kirsher } 3180adfc5217SJeff Kirsher offset = (hw_stats + 3181adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 3182adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 3183adfc5217SJeff Kirsher /* 4-byte counter */ 3184adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 3185adfc5217SJeff Kirsher continue; 3186adfc5217SJeff Kirsher } 3187adfc5217SJeff Kirsher /* 8-byte counter */ 3188adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3189adfc5217SJeff Kirsher } 3190adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3191adfc5217SJeff Kirsher } 3192adfc5217SJeff Kirsher } 3193d5e83632SYuval Mintz 3194adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 3195adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3196d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3197adfc5217SJeff Kirsher continue; 3198adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 3199adfc5217SJeff Kirsher /* skip this counter */ 3200d5e83632SYuval Mintz buf[k + j] = 0; 3201adfc5217SJeff Kirsher j++; 3202adfc5217SJeff Kirsher continue; 3203adfc5217SJeff Kirsher } 3204adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 3205adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 3206adfc5217SJeff Kirsher /* 4-byte counter */ 3207d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 3208adfc5217SJeff Kirsher j++; 3209adfc5217SJeff Kirsher continue; 3210adfc5217SJeff Kirsher } 3211adfc5217SJeff Kirsher /* 8-byte counter */ 3212d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3213adfc5217SJeff Kirsher j++; 3214adfc5217SJeff Kirsher } 3215adfc5217SJeff Kirsher } 3216adfc5217SJeff Kirsher 3217adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 3218adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 3219adfc5217SJeff Kirsher { 3220adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3221adfc5217SJeff Kirsher 32223fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 322351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 322451c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 3225adfc5217SJeff Kirsher return -EAGAIN; 322651c1a580SMerav Sicron } 3227adfc5217SJeff Kirsher 3228adfc5217SJeff Kirsher switch (state) { 3229adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 3230adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 3231adfc5217SJeff Kirsher 3232adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 32338203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3234adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3235adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 32368203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3237adfc5217SJeff Kirsher break; 3238adfc5217SJeff Kirsher 3239adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 32408203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3241adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3242adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 32438203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3244adfc5217SJeff Kirsher break; 3245adfc5217SJeff Kirsher 3246adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 32478203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3248adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3249adfc5217SJeff Kirsher LED_MODE_OPER, 3250adfc5217SJeff Kirsher bp->link_vars.line_speed); 32518203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3252adfc5217SJeff Kirsher } 3253adfc5217SJeff Kirsher 3254adfc5217SJeff Kirsher return 0; 3255adfc5217SJeff Kirsher } 3256adfc5217SJeff Kirsher 32575d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 32585d317c6aSMerav Sicron { 32595d317c6aSMerav Sicron switch (info->flow_type) { 32605d317c6aSMerav Sicron case TCP_V4_FLOW: 32615d317c6aSMerav Sicron case TCP_V6_FLOW: 32625d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32635d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32645d317c6aSMerav Sicron break; 32655d317c6aSMerav Sicron case UDP_V4_FLOW: 32665d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 32675d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32685d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32695d317c6aSMerav Sicron else 32705d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32715d317c6aSMerav Sicron break; 32725d317c6aSMerav Sicron case UDP_V6_FLOW: 32735d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 32745d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32755d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32765d317c6aSMerav Sicron else 32775d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32785d317c6aSMerav Sicron break; 32795d317c6aSMerav Sicron case IPV4_FLOW: 32805d317c6aSMerav Sicron case IPV6_FLOW: 32815d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32825d317c6aSMerav Sicron break; 32835d317c6aSMerav Sicron default: 32845d317c6aSMerav Sicron info->data = 0; 32855d317c6aSMerav Sicron break; 32865d317c6aSMerav Sicron } 32875d317c6aSMerav Sicron 32885d317c6aSMerav Sicron return 0; 32895d317c6aSMerav Sicron } 32905d317c6aSMerav Sicron 3291adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3292815c7db5SBen Hutchings u32 *rules __always_unused) 3293adfc5217SJeff Kirsher { 3294adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3295adfc5217SJeff Kirsher 3296adfc5217SJeff Kirsher switch (info->cmd) { 3297adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 3298adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 3299adfc5217SJeff Kirsher return 0; 33005d317c6aSMerav Sicron case ETHTOOL_GRXFH: 33015d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 33025d317c6aSMerav Sicron default: 33035d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 33045d317c6aSMerav Sicron return -EOPNOTSUPP; 33055d317c6aSMerav Sicron } 33065d317c6aSMerav Sicron } 3307adfc5217SJeff Kirsher 33085d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 33095d317c6aSMerav Sicron { 33105d317c6aSMerav Sicron int udp_rss_requested; 33115d317c6aSMerav Sicron 33125d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33135d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 33145d317c6aSMerav Sicron info->flow_type, info->data); 33155d317c6aSMerav Sicron 33165d317c6aSMerav Sicron switch (info->flow_type) { 33175d317c6aSMerav Sicron case TCP_V4_FLOW: 33185d317c6aSMerav Sicron case TCP_V6_FLOW: 33195d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 33205d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 33215d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 33225d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33235d317c6aSMerav Sicron "Command parameters not supported\n"); 33245d317c6aSMerav Sicron return -EINVAL; 33255d317c6aSMerav Sicron } 33262de67439SYuval Mintz return 0; 33275d317c6aSMerav Sicron 33285d317c6aSMerav Sicron case UDP_V4_FLOW: 33295d317c6aSMerav Sicron case UDP_V6_FLOW: 33305d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 33315d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 33325d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 33335d317c6aSMerav Sicron udp_rss_requested = 1; 33345d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 33355d317c6aSMerav Sicron udp_rss_requested = 0; 33365d317c6aSMerav Sicron else 33375d317c6aSMerav Sicron return -EINVAL; 33385d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 33395d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 33405d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 33415d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33425d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 33435d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 334460cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 33455d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 33465d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 33475d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 33485d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33495d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 33505d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 335160cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 33525d317c6aSMerav Sicron } 3353924d75abSYuval Mintz return 0; 3354924d75abSYuval Mintz 33555d317c6aSMerav Sicron case IPV4_FLOW: 33565d317c6aSMerav Sicron case IPV6_FLOW: 33575d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 33585d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 33595d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33605d317c6aSMerav Sicron "Command parameters not supported\n"); 33615d317c6aSMerav Sicron return -EINVAL; 33625d317c6aSMerav Sicron } 3363924d75abSYuval Mintz return 0; 3364924d75abSYuval Mintz 33655d317c6aSMerav Sicron case SCTP_V4_FLOW: 33665d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 33675d317c6aSMerav Sicron case AH_V4_FLOW: 33685d317c6aSMerav Sicron case ESP_V4_FLOW: 33695d317c6aSMerav Sicron case SCTP_V6_FLOW: 33705d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 33715d317c6aSMerav Sicron case AH_V6_FLOW: 33725d317c6aSMerav Sicron case ESP_V6_FLOW: 33735d317c6aSMerav Sicron case IP_USER_FLOW: 33745d317c6aSMerav Sicron case ETHER_FLOW: 33755d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 33765d317c6aSMerav Sicron if (info->data) { 33775d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33785d317c6aSMerav Sicron "Command parameters not supported\n"); 33795d317c6aSMerav Sicron return -EINVAL; 33805d317c6aSMerav Sicron } 3381924d75abSYuval Mintz return 0; 3382924d75abSYuval Mintz 33835d317c6aSMerav Sicron default: 33845d317c6aSMerav Sicron return -EINVAL; 33855d317c6aSMerav Sicron } 33865d317c6aSMerav Sicron } 33875d317c6aSMerav Sicron 33885d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 33895d317c6aSMerav Sicron { 33905d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 33915d317c6aSMerav Sicron 33925d317c6aSMerav Sicron switch (info->cmd) { 33935d317c6aSMerav Sicron case ETHTOOL_SRXFH: 33945d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 3395adfc5217SJeff Kirsher default: 339651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3397adfc5217SJeff Kirsher return -EOPNOTSUPP; 3398adfc5217SJeff Kirsher } 3399adfc5217SJeff Kirsher } 3400adfc5217SJeff Kirsher 34017850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3402adfc5217SJeff Kirsher { 340396305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 34047850f63fSBen Hutchings } 34057850f63fSBen Hutchings 3406892311f6SEyal Perry static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3407892311f6SEyal Perry u8 *hfunc) 34087850f63fSBen Hutchings { 34097850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 3410adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3411adfc5217SJeff Kirsher size_t i; 3412adfc5217SJeff Kirsher 3413892311f6SEyal Perry if (hfunc) 3414892311f6SEyal Perry *hfunc = ETH_RSS_HASH_TOP; 3415892311f6SEyal Perry if (!indir) 3416892311f6SEyal Perry return 0; 3417892311f6SEyal Perry 3418adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 3419adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3420adfc5217SJeff Kirsher 3421adfc5217SJeff Kirsher /* 3422adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 3423adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 3424adfc5217SJeff Kirsher * points to an array of u32. 3425adfc5217SJeff Kirsher * 3426adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3427adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 3428adfc5217SJeff Kirsher * queue. 3429adfc5217SJeff Kirsher */ 34307850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 34317850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 3432adfc5217SJeff Kirsher 3433adfc5217SJeff Kirsher return 0; 3434adfc5217SJeff Kirsher } 3435adfc5217SJeff Kirsher 3436fe62d001SBen Hutchings static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3437892311f6SEyal Perry const u8 *key, const u8 hfunc) 3438adfc5217SJeff Kirsher { 3439adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3440adfc5217SJeff Kirsher size_t i; 3441adfc5217SJeff Kirsher 3442892311f6SEyal Perry /* We require at least one supported parameter to be changed and no 3443892311f6SEyal Perry * change in any of the unsupported parameters 3444892311f6SEyal Perry */ 3445892311f6SEyal Perry if (key || 3446892311f6SEyal Perry (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3447892311f6SEyal Perry return -EOPNOTSUPP; 3448892311f6SEyal Perry 3449892311f6SEyal Perry if (!indir) 3450892311f6SEyal Perry return 0; 3451892311f6SEyal Perry 3452adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3453adfc5217SJeff Kirsher /* 3454fe62d001SBen Hutchings * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3455adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 3456adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 3457adfc5217SJeff Kirsher * 3458adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3459adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 3460adfc5217SJeff Kirsher * queue 3461adfc5217SJeff Kirsher */ 34625d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3463adfc5217SJeff Kirsher } 3464adfc5217SJeff Kirsher 34655d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 3466adfc5217SJeff Kirsher } 3467adfc5217SJeff Kirsher 34680e8d2ec5SMerav Sicron /** 34690e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 34700e8d2ec5SMerav Sicron * 34710e8d2ec5SMerav Sicron * @dev: net device 34720e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 34730e8d2ec5SMerav Sicron */ 34740e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 34750e8d2ec5SMerav Sicron struct ethtool_channels *channels) 34760e8d2ec5SMerav Sicron { 34770e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34780e8d2ec5SMerav Sicron 34790e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 34800e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 34810e8d2ec5SMerav Sicron } 34820e8d2ec5SMerav Sicron 34830e8d2ec5SMerav Sicron /** 34840e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 34850e8d2ec5SMerav Sicron * 34860e8d2ec5SMerav Sicron * @bp: bnx2x private structure 34870e8d2ec5SMerav Sicron * 34880e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 34890e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 34900e8d2ec5SMerav Sicron */ 34910e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 34920e8d2ec5SMerav Sicron { 34930e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 349455c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 349555c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 349655c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 34970e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 34980e8d2ec5SMerav Sicron } 34990e8d2ec5SMerav Sicron 35000e8d2ec5SMerav Sicron /** 35010e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 35020e8d2ec5SMerav Sicron * 35030e8d2ec5SMerav Sicron * @dev: net device 35040e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 35050e8d2ec5SMerav Sicron */ 35060e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 35070e8d2ec5SMerav Sicron struct ethtool_channels *channels) 35080e8d2ec5SMerav Sicron { 35090e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 35100e8d2ec5SMerav Sicron 35110e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 35120e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 35130e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 35140e8d2ec5SMerav Sicron channels->combined_count); 35150e8d2ec5SMerav Sicron 3516909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 3517909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3518909d9faaSYuval Mintz return -EPERM; 3519909d9faaSYuval Mintz } 3520909d9faaSYuval Mintz 35210e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 35220e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 35230e8d2ec5SMerav Sicron */ 35240e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 35250e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 35260e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 35270e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 35280e8d2ec5SMerav Sicron return -EINVAL; 35290e8d2ec5SMerav Sicron } 35300e8d2ec5SMerav Sicron 35310e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 35320e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 35330e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 35340e8d2ec5SMerav Sicron return 0; 35350e8d2ec5SMerav Sicron } 35360e8d2ec5SMerav Sicron 35370e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 35380e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 35390e8d2ec5SMerav Sicron * less than requested if memory is low. 35400e8d2ec5SMerav Sicron */ 35410e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 35420e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 35430e8d2ec5SMerav Sicron return 0; 35440e8d2ec5SMerav Sicron } 35455d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 35460e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 35470e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 35480e8d2ec5SMerav Sicron } 35490e8d2ec5SMerav Sicron 3550eeed018cSMichal Kalderon static int bnx2x_get_ts_info(struct net_device *dev, 3551eeed018cSMichal Kalderon struct ethtool_ts_info *info) 3552eeed018cSMichal Kalderon { 3553eeed018cSMichal Kalderon struct bnx2x *bp = netdev_priv(dev); 3554eeed018cSMichal Kalderon 3555eeed018cSMichal Kalderon if (bp->flags & PTP_SUPPORTED) { 3556eeed018cSMichal Kalderon info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3557eeed018cSMichal Kalderon SOF_TIMESTAMPING_RX_SOFTWARE | 3558eeed018cSMichal Kalderon SOF_TIMESTAMPING_SOFTWARE | 3559eeed018cSMichal Kalderon SOF_TIMESTAMPING_TX_HARDWARE | 3560eeed018cSMichal Kalderon SOF_TIMESTAMPING_RX_HARDWARE | 3561eeed018cSMichal Kalderon SOF_TIMESTAMPING_RAW_HARDWARE; 3562eeed018cSMichal Kalderon 3563eeed018cSMichal Kalderon if (bp->ptp_clock) 3564eeed018cSMichal Kalderon info->phc_index = ptp_clock_index(bp->ptp_clock); 3565eeed018cSMichal Kalderon else 3566eeed018cSMichal Kalderon info->phc_index = -1; 3567eeed018cSMichal Kalderon 3568eeed018cSMichal Kalderon info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3569eeed018cSMichal Kalderon (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3570eeed018cSMichal Kalderon (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3571dd3950c6SJacob Keller (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3572eeed018cSMichal Kalderon 3573eeed018cSMichal Kalderon info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3574eeed018cSMichal Kalderon 3575eeed018cSMichal Kalderon return 0; 3576eeed018cSMichal Kalderon } 3577eeed018cSMichal Kalderon 3578eeed018cSMichal Kalderon return ethtool_op_get_ts_info(dev, info); 3579eeed018cSMichal Kalderon } 3580eeed018cSMichal Kalderon 3581adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 3582adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 3583adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 3584adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 3585adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 3586adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 358707ba6af4SMiriam Shitrit .get_dump_flag = bnx2x_get_dump_flag, 358807ba6af4SMiriam Shitrit .get_dump_data = bnx2x_get_dump_data, 358907ba6af4SMiriam Shitrit .set_dump = bnx2x_set_dump, 3590adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 3591adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 3592adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 3593adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 3594adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 3595adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 3596adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 3597adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 3598adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 3599adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 3600adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 3601adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 3602adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 3603adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 3604adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 3605adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 3606adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 36073521b419SYuval Mintz .get_priv_flags = bnx2x_get_private_flags, 3608adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 3609adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 3610adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 3611adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 36125d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 36137850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3614fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3615fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 36160e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 36170e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 361824ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 361924ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3620e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3621e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3622eeed018cSMichal Kalderon .get_ts_info = bnx2x_get_ts_info, 3623adfc5217SJeff Kirsher }; 3624adfc5217SJeff Kirsher 3625005a07baSAriel Elior static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 36266495d15aSDmitry Kravkov .get_settings = bnx2x_get_vf_settings, 3627005a07baSAriel Elior .get_drvinfo = bnx2x_get_drvinfo, 3628005a07baSAriel Elior .get_msglevel = bnx2x_get_msglevel, 3629005a07baSAriel Elior .set_msglevel = bnx2x_set_msglevel, 3630005a07baSAriel Elior .get_link = bnx2x_get_link, 3631005a07baSAriel Elior .get_coalesce = bnx2x_get_coalesce, 3632005a07baSAriel Elior .get_ringparam = bnx2x_get_ringparam, 3633005a07baSAriel Elior .set_ringparam = bnx2x_set_ringparam, 3634005a07baSAriel Elior .get_sset_count = bnx2x_get_sset_count, 3635005a07baSAriel Elior .get_strings = bnx2x_get_strings, 3636005a07baSAriel Elior .get_ethtool_stats = bnx2x_get_ethtool_stats, 3637005a07baSAriel Elior .get_rxnfc = bnx2x_get_rxnfc, 3638005a07baSAriel Elior .set_rxnfc = bnx2x_set_rxnfc, 3639005a07baSAriel Elior .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3640fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3641fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 3642005a07baSAriel Elior .get_channels = bnx2x_get_channels, 3643005a07baSAriel Elior .set_channels = bnx2x_set_channels, 3644005a07baSAriel Elior }; 3645005a07baSAriel Elior 3646005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3647adfc5217SJeff Kirsher { 36487ad24ea4SWilfried Klaebe netdev->ethtool_ops = (IS_PF(bp)) ? 36497ad24ea4SWilfried Klaebe &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3650adfc5217SJeff Kirsher } 3651