1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher #include "bnx2x.h" 26adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 27adfc5217SJeff Kirsher #include "bnx2x_dump.h" 28adfc5217SJeff Kirsher #include "bnx2x_init.h" 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 31adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33adfc5217SJeff Kirsher */ 34adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 35adfc5217SJeff Kirsher static const struct { 36adfc5217SJeff Kirsher long offset; 37adfc5217SJeff Kirsher int size; 38adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 39adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 40adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 49adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53adfc5217SJeff Kirsher 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 65c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 68adfc5217SJeff Kirsher }; 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher static const struct { 73adfc5217SJeff Kirsher long offset; 74adfc5217SJeff Kirsher int size; 75adfc5217SJeff Kirsher u32 flags; 76adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 77adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 78adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 80adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 81adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 101adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 104adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 106adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 108adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1090e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1100e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1110e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1120e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 114adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 122adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 128adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129adfc5217SJeff Kirsher 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 131adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1777a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1797a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1817a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 183c96bdc0cSDmitry Kravkov 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 185e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 18907ba6af4SMiriam Shitrit 190adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 191adfc5217SJeff Kirsher { 192adfc5217SJeff Kirsher int port_type; 193adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 195dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 196dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 198adfc5217SJeff Kirsher case ETH_PHY_KR: 199adfc5217SJeff Kirsher case ETH_PHY_CX4: 200adfc5217SJeff Kirsher port_type = PORT_FIBRE; 201adfc5217SJeff Kirsher break; 202adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 203adfc5217SJeff Kirsher port_type = PORT_DA; 204adfc5217SJeff Kirsher break; 205adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 206adfc5217SJeff Kirsher port_type = PORT_TP; 207adfc5217SJeff Kirsher break; 208adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 209adfc5217SJeff Kirsher port_type = PORT_NONE; 210adfc5217SJeff Kirsher break; 211adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 212adfc5217SJeff Kirsher default: 213adfc5217SJeff Kirsher port_type = PORT_OTHER; 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher return port_type; 217adfc5217SJeff Kirsher } 218adfc5217SJeff Kirsher 219adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 220adfc5217SJeff Kirsher { 221adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 222adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 223adfc5217SJeff Kirsher 224adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 225adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 226adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 227adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 228adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 229dbef807eSYuval Mintz if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 230dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER) { 231dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 232dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 233dbef807eSYuval Mintz } 234adfc5217SJeff Kirsher 23559694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 23659694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 237adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 238adfc5217SJeff Kirsher 23938298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 240adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 24159694f00SYuval Mintz else 24259694f00SYuval Mintz ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 24338298461SYuval Mintz } else { 24438298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 24538298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 24638298461SYuval Mintz } 247adfc5217SJeff Kirsher 248adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 249adfc5217SJeff Kirsher 250adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 251adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 254adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 255adfc5217SJeff Kirsher else 256adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 257adfc5217SJeff Kirsher 2589e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2599e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2609e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2619e7e8399SMintz Yuval 2629e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 2639e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 2649e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 2659e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 2669e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 2679e7e8399SMintz Yuval 2689e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 2699e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 2709e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 2719e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 2729e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 2739e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 2749e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 2759e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 2769e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 2779e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 2789e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 2799e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 2809e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 2819e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 2829e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 2839e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 284be94bea7SYaniv Rosner if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 285be94bea7SYaniv Rosner cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 2869e7e8399SMintz Yuval } 2879e7e8399SMintz Yuval 288adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 289adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 290adfc5217SJeff Kirsher 29151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 292f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 293f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 294f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 295adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 296adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 297adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 298adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 299adfc5217SJeff Kirsher 300adfc5217SJeff Kirsher return 0; 301adfc5217SJeff Kirsher } 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 304adfc5217SJeff Kirsher { 305adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 306adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 307dbef807eSYuval Mintz u32 speed, phy_idx; 308adfc5217SJeff Kirsher 309adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 310adfc5217SJeff Kirsher return 0; 311adfc5217SJeff Kirsher 31251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 313adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 314adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 315adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 316adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 317adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 318adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 319adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 320adfc5217SJeff Kirsher 321adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 322adfc5217SJeff Kirsher 32316a5fd92SYuval Mintz /* If received a request for an unknown duplex, assume full*/ 32438298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 32538298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 32638298461SYuval Mintz 327adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 328adfc5217SJeff Kirsher u32 part; 329adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 330adfc5217SJeff Kirsher 331adfc5217SJeff Kirsher /* use 10G if no link detected */ 332adfc5217SJeff Kirsher if (!line_speed) 333adfc5217SJeff Kirsher line_speed = 10000; 334adfc5217SJeff Kirsher 335adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 33651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33751c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 338adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 339adfc5217SJeff Kirsher return -EINVAL; 340adfc5217SJeff Kirsher } 341adfc5217SJeff Kirsher 342adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 343adfc5217SJeff Kirsher 344adfc5217SJeff Kirsher if (line_speed < speed || !part) { 34551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34651c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 347adfc5217SJeff Kirsher return -EINVAL; 348adfc5217SJeff Kirsher } 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 351adfc5217SJeff Kirsher /* store value for following "load" */ 352adfc5217SJeff Kirsher bp->pending_max = part; 353adfc5217SJeff Kirsher else 354adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher return 0; 357adfc5217SJeff Kirsher } 358adfc5217SJeff Kirsher 359adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 360adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 361adfc5217SJeff Kirsher switch (cmd->port) { 362adfc5217SJeff Kirsher case PORT_TP: 363adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 364adfc5217SJeff Kirsher break; /* no port change */ 365adfc5217SJeff Kirsher 366adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 367adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 36851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 369adfc5217SJeff Kirsher return -EINVAL; 370adfc5217SJeff Kirsher } 371adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 372adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 373adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 374adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 375adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 376adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 377adfc5217SJeff Kirsher else 378adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 379adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 380adfc5217SJeff Kirsher break; 381adfc5217SJeff Kirsher case PORT_FIBRE: 382bfdb5823SYaniv Rosner case PORT_DA: 383adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 384adfc5217SJeff Kirsher break; /* no port change */ 385adfc5217SJeff Kirsher 386adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 387adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 38851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 389adfc5217SJeff Kirsher return -EINVAL; 390adfc5217SJeff Kirsher } 391adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 392adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 393adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 394adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 395adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 396adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 397adfc5217SJeff Kirsher else 398adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 399adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 400adfc5217SJeff Kirsher break; 401adfc5217SJeff Kirsher default: 40251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 403adfc5217SJeff Kirsher return -EINVAL; 404adfc5217SJeff Kirsher } 4052de67439SYuval Mintz /* Save new config in case command complete successfully */ 406adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 407adfc5217SJeff Kirsher /* Get the new cfg_idx */ 408adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 409adfc5217SJeff Kirsher /* Restore old config in case command failed */ 410adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 41151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 412adfc5217SJeff Kirsher 413adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 41475318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 41575318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 41675318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 41775318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 41875318327SYaniv Rosner SUPPORTED_100baseT_Full); 419adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 42051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 421adfc5217SJeff Kirsher return -EINVAL; 422adfc5217SJeff Kirsher } 423adfc5217SJeff Kirsher 424adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 42575318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 42651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 42751c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4288decf868SDavid S. Miller return -EINVAL; 4298decf868SDavid S. Miller } 430adfc5217SJeff Kirsher 431adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4328decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4338decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 434adfc5217SJeff Kirsher cmd->advertising); 4358decf868SDavid S. Miller if (cmd->advertising) { 436adfc5217SJeff Kirsher 4378decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4388decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4398decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4408decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4418decf868SDavid S. Miller } 4428decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4438decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4448decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4458decf868SDavid S. Miller 4468decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4478decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4488decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4498decf868SDavid S. Miller 4508decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4518decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4528decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4538decf868SDavid S. Miller } 4548decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4558decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4568decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4578decf868SDavid S. Miller } 4588decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4598decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4608decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4618decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4628decf868SDavid S. Miller 4638decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4648decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 4658decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 4668decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4678decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 468be94bea7SYaniv Rosner 469be94bea7SYaniv Rosner if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 470be94bea7SYaniv Rosner bp->link_params.speed_cap_mask[cfg_idx] |= 471be94bea7SYaniv Rosner PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 4728decf868SDavid S. Miller } 473adfc5217SJeff Kirsher } else { /* forced speed */ 474adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 475adfc5217SJeff Kirsher switch (speed) { 476adfc5217SJeff Kirsher case SPEED_10: 477adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 478adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 479adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 48051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 481adfc5217SJeff Kirsher "10M full not supported\n"); 482adfc5217SJeff Kirsher return -EINVAL; 483adfc5217SJeff Kirsher } 484adfc5217SJeff Kirsher 485adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 486adfc5217SJeff Kirsher ADVERTISED_TP); 487adfc5217SJeff Kirsher } else { 488adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 489adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 49051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 491adfc5217SJeff Kirsher "10M half not supported\n"); 492adfc5217SJeff Kirsher return -EINVAL; 493adfc5217SJeff Kirsher } 494adfc5217SJeff Kirsher 495adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 496adfc5217SJeff Kirsher ADVERTISED_TP); 497adfc5217SJeff Kirsher } 498adfc5217SJeff Kirsher break; 499adfc5217SJeff Kirsher 500adfc5217SJeff Kirsher case SPEED_100: 501adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 502adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 503adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 50451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 505adfc5217SJeff Kirsher "100M full not supported\n"); 506adfc5217SJeff Kirsher return -EINVAL; 507adfc5217SJeff Kirsher } 508adfc5217SJeff Kirsher 509adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 510adfc5217SJeff Kirsher ADVERTISED_TP); 511adfc5217SJeff Kirsher } else { 512adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 513adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 51451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 515adfc5217SJeff Kirsher "100M half not supported\n"); 516adfc5217SJeff Kirsher return -EINVAL; 517adfc5217SJeff Kirsher } 518adfc5217SJeff Kirsher 519adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 520adfc5217SJeff Kirsher ADVERTISED_TP); 521adfc5217SJeff Kirsher } 522adfc5217SJeff Kirsher break; 523adfc5217SJeff Kirsher 524adfc5217SJeff Kirsher case SPEED_1000: 525adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 52651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52751c1a580SMerav Sicron "1G half not supported\n"); 528adfc5217SJeff Kirsher return -EINVAL; 529adfc5217SJeff Kirsher } 530adfc5217SJeff Kirsher 531adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 532adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 53351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 53451c1a580SMerav Sicron "1G full not supported\n"); 535adfc5217SJeff Kirsher return -EINVAL; 536adfc5217SJeff Kirsher } 537adfc5217SJeff Kirsher 538adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 539adfc5217SJeff Kirsher ADVERTISED_TP); 540adfc5217SJeff Kirsher break; 541adfc5217SJeff Kirsher 542adfc5217SJeff Kirsher case SPEED_2500: 543adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 54451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 545adfc5217SJeff Kirsher "2.5G half not supported\n"); 546adfc5217SJeff Kirsher return -EINVAL; 547adfc5217SJeff Kirsher } 548adfc5217SJeff Kirsher 549adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 550adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 55151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 552adfc5217SJeff Kirsher "2.5G full not supported\n"); 553adfc5217SJeff Kirsher return -EINVAL; 554adfc5217SJeff Kirsher } 555adfc5217SJeff Kirsher 556adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 557adfc5217SJeff Kirsher ADVERTISED_TP); 558adfc5217SJeff Kirsher break; 559adfc5217SJeff Kirsher 560adfc5217SJeff Kirsher case SPEED_10000: 561adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 56251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56351c1a580SMerav Sicron "10G half not supported\n"); 564adfc5217SJeff Kirsher return -EINVAL; 565adfc5217SJeff Kirsher } 566dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 567adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 568dbef807eSYuval Mintz & SUPPORTED_10000baseT_Full) || 569dbef807eSYuval Mintz (bp->link_params.phy[phy_idx].media_type == 570dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 57151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 57251c1a580SMerav Sicron "10G full not supported\n"); 573adfc5217SJeff Kirsher return -EINVAL; 574adfc5217SJeff Kirsher } 575adfc5217SJeff Kirsher 576adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 577adfc5217SJeff Kirsher ADVERTISED_FIBRE); 578adfc5217SJeff Kirsher break; 579adfc5217SJeff Kirsher 580adfc5217SJeff Kirsher default: 58151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 582adfc5217SJeff Kirsher return -EINVAL; 583adfc5217SJeff Kirsher } 584adfc5217SJeff Kirsher 585adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 586adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 587adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 588adfc5217SJeff Kirsher } 589adfc5217SJeff Kirsher 59051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 591f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 592adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 593adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 594adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 595adfc5217SJeff Kirsher 596adfc5217SJeff Kirsher /* Set new config */ 597adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 598adfc5217SJeff Kirsher if (netif_running(dev)) { 599adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 600adfc5217SJeff Kirsher bnx2x_link_set(bp); 601adfc5217SJeff Kirsher } 602adfc5217SJeff Kirsher 603adfc5217SJeff Kirsher return 0; 604adfc5217SJeff Kirsher } 605adfc5217SJeff Kirsher 60607ba6af4SMiriam Shitrit #define DUMP_ALL_PRESETS 0x1FFF 60707ba6af4SMiriam Shitrit #define DUMP_MAX_PRESETS 13 608adfc5217SJeff Kirsher 60907ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 610adfc5217SJeff Kirsher { 611adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 61207ba6af4SMiriam Shitrit return dump_num_registers[0][preset-1]; 613adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 61407ba6af4SMiriam Shitrit return dump_num_registers[1][preset-1]; 615adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 61607ba6af4SMiriam Shitrit return dump_num_registers[2][preset-1]; 617adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 61807ba6af4SMiriam Shitrit return dump_num_registers[3][preset-1]; 619adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 62007ba6af4SMiriam Shitrit return dump_num_registers[4][preset-1]; 621adfc5217SJeff Kirsher else 62207ba6af4SMiriam Shitrit return 0; 623adfc5217SJeff Kirsher } 624adfc5217SJeff Kirsher 62507ba6af4SMiriam Shitrit static int __bnx2x_get_regs_len(struct bnx2x *bp) 62607ba6af4SMiriam Shitrit { 62707ba6af4SMiriam Shitrit u32 preset_idx; 62807ba6af4SMiriam Shitrit int regdump_len = 0; 62907ba6af4SMiriam Shitrit 63007ba6af4SMiriam Shitrit /* Calculate the total preset regs length */ 63107ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 63207ba6af4SMiriam Shitrit regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 63307ba6af4SMiriam Shitrit 63407ba6af4SMiriam Shitrit return regdump_len; 63507ba6af4SMiriam Shitrit } 63607ba6af4SMiriam Shitrit 63707ba6af4SMiriam Shitrit static int bnx2x_get_regs_len(struct net_device *dev) 63807ba6af4SMiriam Shitrit { 63907ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 64007ba6af4SMiriam Shitrit int regdump_len = 0; 64107ba6af4SMiriam Shitrit 64207ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_regs_len(bp); 64307ba6af4SMiriam Shitrit regdump_len *= 4; 64407ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 64507ba6af4SMiriam Shitrit 64607ba6af4SMiriam Shitrit return regdump_len; 64707ba6af4SMiriam Shitrit } 64807ba6af4SMiriam Shitrit 64907ba6af4SMiriam Shitrit #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 65007ba6af4SMiriam Shitrit #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 65107ba6af4SMiriam Shitrit #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 65207ba6af4SMiriam Shitrit #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 65307ba6af4SMiriam Shitrit #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 65407ba6af4SMiriam Shitrit 65507ba6af4SMiriam Shitrit #define IS_REG_IN_PRESET(presets, idx) \ 65607ba6af4SMiriam Shitrit ((presets & (1 << (idx-1))) == (1 << (idx-1))) 65707ba6af4SMiriam Shitrit 658adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 6591191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 660adfc5217SJeff Kirsher { 661adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 662adfc5217SJeff Kirsher return page_vals_e2; 663adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 664adfc5217SJeff Kirsher return page_vals_e3; 665adfc5217SJeff Kirsher else 666adfc5217SJeff Kirsher return NULL; 667adfc5217SJeff Kirsher } 668adfc5217SJeff Kirsher 6691191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 670adfc5217SJeff Kirsher { 671adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 672adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 673adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 674adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 675adfc5217SJeff Kirsher else 676adfc5217SJeff Kirsher return 0; 677adfc5217SJeff Kirsher } 678adfc5217SJeff Kirsher 6791191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 680adfc5217SJeff Kirsher { 681adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 682adfc5217SJeff Kirsher return page_write_regs_e2; 683adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 684adfc5217SJeff Kirsher return page_write_regs_e3; 685adfc5217SJeff Kirsher else 686adfc5217SJeff Kirsher return NULL; 687adfc5217SJeff Kirsher } 688adfc5217SJeff Kirsher 6891191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 690adfc5217SJeff Kirsher { 691adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 692adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 693adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 694adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 695adfc5217SJeff Kirsher else 696adfc5217SJeff Kirsher return 0; 697adfc5217SJeff Kirsher } 698adfc5217SJeff Kirsher 6991191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 700adfc5217SJeff Kirsher { 701adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 702adfc5217SJeff Kirsher return page_read_regs_e2; 703adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 704adfc5217SJeff Kirsher return page_read_regs_e3; 705adfc5217SJeff Kirsher else 706adfc5217SJeff Kirsher return NULL; 707adfc5217SJeff Kirsher } 708adfc5217SJeff Kirsher 7091191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 710adfc5217SJeff Kirsher { 711adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 712adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 713adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 714adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 715adfc5217SJeff Kirsher else 716adfc5217SJeff Kirsher return 0; 717adfc5217SJeff Kirsher } 718adfc5217SJeff Kirsher 71907ba6af4SMiriam Shitrit static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 72007ba6af4SMiriam Shitrit const struct reg_addr *reg_info) 721adfc5217SJeff Kirsher { 72207ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 72307ba6af4SMiriam Shitrit return IS_E1_REG(reg_info->chips); 72407ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 72507ba6af4SMiriam Shitrit return IS_E1H_REG(reg_info->chips); 72607ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 72707ba6af4SMiriam Shitrit return IS_E2_REG(reg_info->chips); 72807ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 72907ba6af4SMiriam Shitrit return IS_E3A0_REG(reg_info->chips); 73007ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 73107ba6af4SMiriam Shitrit return IS_E3B0_REG(reg_info->chips); 73207ba6af4SMiriam Shitrit else 73307ba6af4SMiriam Shitrit return false; 734adfc5217SJeff Kirsher } 735adfc5217SJeff Kirsher 73607ba6af4SMiriam Shitrit static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 73707ba6af4SMiriam Shitrit const struct wreg_addr *wreg_info) 738adfc5217SJeff Kirsher { 73907ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 74007ba6af4SMiriam Shitrit return IS_E1_REG(wreg_info->chips); 74107ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 74207ba6af4SMiriam Shitrit return IS_E1H_REG(wreg_info->chips); 74307ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 74407ba6af4SMiriam Shitrit return IS_E2_REG(wreg_info->chips); 74507ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 74607ba6af4SMiriam Shitrit return IS_E3A0_REG(wreg_info->chips); 74707ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 74807ba6af4SMiriam Shitrit return IS_E3B0_REG(wreg_info->chips); 74907ba6af4SMiriam Shitrit else 75007ba6af4SMiriam Shitrit return false; 751adfc5217SJeff Kirsher } 752adfc5217SJeff Kirsher 753adfc5217SJeff Kirsher /** 754adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 755adfc5217SJeff Kirsher * 756adfc5217SJeff Kirsher * @bp device handle 757adfc5217SJeff Kirsher * @p output buffer 758adfc5217SJeff Kirsher * 7592de67439SYuval Mintz * Reads "paged" memories: memories that may only be read by first writing to a 7602de67439SYuval Mintz * specific address ("write address") and then reading from a specific address 7612de67439SYuval Mintz * ("read address"). There may be more than one write address per "page" and 7622de67439SYuval Mintz * more than one read address per write address. 763adfc5217SJeff Kirsher */ 76407ba6af4SMiriam Shitrit static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 765adfc5217SJeff Kirsher { 766adfc5217SJeff Kirsher u32 i, j, k, n; 76707ba6af4SMiriam Shitrit 768adfc5217SJeff Kirsher /* addresses of the paged registers */ 769adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 770adfc5217SJeff Kirsher /* number of paged registers */ 771adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 772adfc5217SJeff Kirsher /* write addresses */ 773adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 774adfc5217SJeff Kirsher /* number of write addresses */ 775adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 776adfc5217SJeff Kirsher /* read addresses info */ 777adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 778adfc5217SJeff Kirsher /* number of read addresses */ 779adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 78007ba6af4SMiriam Shitrit u32 addr, size; 781adfc5217SJeff Kirsher 782adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 783adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 784adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 78507ba6af4SMiriam Shitrit 78607ba6af4SMiriam Shitrit for (k = 0; k < read_num; k++) { 78707ba6af4SMiriam Shitrit if (IS_REG_IN_PRESET(read_addr[k].presets, 78807ba6af4SMiriam Shitrit preset)) { 78907ba6af4SMiriam Shitrit size = read_addr[k].size; 79007ba6af4SMiriam Shitrit for (n = 0; n < size; n++) { 79107ba6af4SMiriam Shitrit addr = read_addr[k].addr + n*4; 79207ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr); 793adfc5217SJeff Kirsher } 794adfc5217SJeff Kirsher } 795adfc5217SJeff Kirsher } 79607ba6af4SMiriam Shitrit } 79707ba6af4SMiriam Shitrit } 79807ba6af4SMiriam Shitrit } 79907ba6af4SMiriam Shitrit 80007ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 80107ba6af4SMiriam Shitrit { 80207ba6af4SMiriam Shitrit u32 i, j, addr; 80307ba6af4SMiriam Shitrit const struct wreg_addr *wreg_addr_p = NULL; 80407ba6af4SMiriam Shitrit 80507ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 80607ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1; 80707ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 80807ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1h; 80907ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 81007ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e2; 81107ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 81207ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3; 81307ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 81407ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3b0; 81507ba6af4SMiriam Shitrit 81607ba6af4SMiriam Shitrit /* Read the idle_chk registers */ 81707ba6af4SMiriam Shitrit for (i = 0; i < IDLE_REGS_COUNT; i++) { 81807ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 81907ba6af4SMiriam Shitrit IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 82007ba6af4SMiriam Shitrit for (j = 0; j < idle_reg_addrs[i].size; j++) 82107ba6af4SMiriam Shitrit *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 82207ba6af4SMiriam Shitrit } 82307ba6af4SMiriam Shitrit } 82407ba6af4SMiriam Shitrit 82507ba6af4SMiriam Shitrit /* Read the regular registers */ 82607ba6af4SMiriam Shitrit for (i = 0; i < REGS_COUNT; i++) { 82707ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 82807ba6af4SMiriam Shitrit IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 82907ba6af4SMiriam Shitrit for (j = 0; j < reg_addrs[i].size; j++) 83007ba6af4SMiriam Shitrit *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 83107ba6af4SMiriam Shitrit } 83207ba6af4SMiriam Shitrit } 83307ba6af4SMiriam Shitrit 83407ba6af4SMiriam Shitrit /* Read the CAM registers */ 83507ba6af4SMiriam Shitrit if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 83607ba6af4SMiriam Shitrit IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 83707ba6af4SMiriam Shitrit for (i = 0; i < wreg_addr_p->size; i++) { 83807ba6af4SMiriam Shitrit *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 83907ba6af4SMiriam Shitrit 84007ba6af4SMiriam Shitrit /* In case of wreg_addr register, read additional 84107ba6af4SMiriam Shitrit registers from read_regs array 84207ba6af4SMiriam Shitrit */ 84307ba6af4SMiriam Shitrit for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 84407ba6af4SMiriam Shitrit addr = *(wreg_addr_p->read_regs); 84507ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr + j*4); 84607ba6af4SMiriam Shitrit } 84707ba6af4SMiriam Shitrit } 84807ba6af4SMiriam Shitrit } 84907ba6af4SMiriam Shitrit 85007ba6af4SMiriam Shitrit /* Paged registers are supported in E2 & E3 only */ 85107ba6af4SMiriam Shitrit if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 85216a5fd92SYuval Mintz /* Read "paged" registers */ 85307ba6af4SMiriam Shitrit bnx2x_read_pages_regs(bp, p, preset); 85407ba6af4SMiriam Shitrit } 85507ba6af4SMiriam Shitrit 85607ba6af4SMiriam Shitrit return 0; 85707ba6af4SMiriam Shitrit } 858adfc5217SJeff Kirsher 8591191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 860adfc5217SJeff Kirsher { 86107ba6af4SMiriam Shitrit u32 preset_idx; 862adfc5217SJeff Kirsher 86307ba6af4SMiriam Shitrit /* Read all registers, by reading all preset registers */ 86407ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 86507ba6af4SMiriam Shitrit /* Skip presets with IOR */ 86607ba6af4SMiriam Shitrit if ((preset_idx == 2) || 86707ba6af4SMiriam Shitrit (preset_idx == 5) || 86807ba6af4SMiriam Shitrit (preset_idx == 8) || 86907ba6af4SMiriam Shitrit (preset_idx == 11)) 87007ba6af4SMiriam Shitrit continue; 87107ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, preset_idx); 87207ba6af4SMiriam Shitrit p += __bnx2x_get_preset_regs_len(bp, preset_idx); 87307ba6af4SMiriam Shitrit } 874adfc5217SJeff Kirsher } 875adfc5217SJeff Kirsher 876adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 877adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 878adfc5217SJeff Kirsher { 879adfc5217SJeff Kirsher u32 *p = _p; 880adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 88107ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 882adfc5217SJeff Kirsher 88307ba6af4SMiriam Shitrit regs->version = 2; 884adfc5217SJeff Kirsher memset(p, 0, regs->len); 885adfc5217SJeff Kirsher 886adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 887adfc5217SJeff Kirsher return; 888adfc5217SJeff Kirsher 889adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 890adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 891adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 892adfc5217SJeff Kirsher */ 89307ba6af4SMiriam Shitrit 89407ba6af4SMiriam Shitrit /* Disable parity on path 0 */ 89507ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 896adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 897adfc5217SJeff Kirsher 89807ba6af4SMiriam Shitrit /* Disable parity on path 1 */ 89907ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 90007ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 901adfc5217SJeff Kirsher 90207ba6af4SMiriam Shitrit /* Return to current function */ 90307ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 904adfc5217SJeff Kirsher 90507ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 90607ba6af4SMiriam Shitrit dump_hdr.preset = DUMP_ALL_PRESETS; 90707ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 90807ba6af4SMiriam Shitrit 90907ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 91007ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 91107ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 91207ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 91307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 91407ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 91507ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 91607ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 91707ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 91807ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 91907ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 92007ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 92107ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 92207ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 92307ba6af4SMiriam Shitrit } 92407ba6af4SMiriam Shitrit 92507ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 92607ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 927adfc5217SJeff Kirsher 928adfc5217SJeff Kirsher /* Actually read the registers */ 929adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 930adfc5217SJeff Kirsher 93107ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 0 */ 93207ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 933adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 934adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 93507ba6af4SMiriam Shitrit 93607ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 1 */ 93707ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 93807ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 93907ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 94007ba6af4SMiriam Shitrit 94107ba6af4SMiriam Shitrit /* Return to current function */ 94207ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 94307ba6af4SMiriam Shitrit } 94407ba6af4SMiriam Shitrit 94507ba6af4SMiriam Shitrit static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 94607ba6af4SMiriam Shitrit { 94707ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 94807ba6af4SMiriam Shitrit int regdump_len = 0; 94907ba6af4SMiriam Shitrit 95007ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 95107ba6af4SMiriam Shitrit regdump_len *= 4; 95207ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 95307ba6af4SMiriam Shitrit 95407ba6af4SMiriam Shitrit return regdump_len; 95507ba6af4SMiriam Shitrit } 95607ba6af4SMiriam Shitrit 95707ba6af4SMiriam Shitrit static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 95807ba6af4SMiriam Shitrit { 95907ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 96007ba6af4SMiriam Shitrit 96107ba6af4SMiriam Shitrit /* Use the ethtool_dump "flag" field as the dump preset index */ 9625bb680d6SMichal Schmidt if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 9635bb680d6SMichal Schmidt return -EINVAL; 9645bb680d6SMichal Schmidt 96507ba6af4SMiriam Shitrit bp->dump_preset_idx = val->flag; 96607ba6af4SMiriam Shitrit return 0; 96707ba6af4SMiriam Shitrit } 96807ba6af4SMiriam Shitrit 96907ba6af4SMiriam Shitrit static int bnx2x_get_dump_flag(struct net_device *dev, 97007ba6af4SMiriam Shitrit struct ethtool_dump *dump) 97107ba6af4SMiriam Shitrit { 97207ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 97307ba6af4SMiriam Shitrit 9748cc2d927SMichal Schmidt dump->version = BNX2X_DUMP_VERSION; 9758cc2d927SMichal Schmidt dump->flag = bp->dump_preset_idx; 97607ba6af4SMiriam Shitrit /* Calculate the requested preset idx length */ 97707ba6af4SMiriam Shitrit dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 97807ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 97907ba6af4SMiriam Shitrit bp->dump_preset_idx, dump->len); 98007ba6af4SMiriam Shitrit return 0; 98107ba6af4SMiriam Shitrit } 98207ba6af4SMiriam Shitrit 98307ba6af4SMiriam Shitrit static int bnx2x_get_dump_data(struct net_device *dev, 98407ba6af4SMiriam Shitrit struct ethtool_dump *dump, 98507ba6af4SMiriam Shitrit void *buffer) 98607ba6af4SMiriam Shitrit { 98707ba6af4SMiriam Shitrit u32 *p = buffer; 98807ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 98907ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 99007ba6af4SMiriam Shitrit 99107ba6af4SMiriam Shitrit /* Disable parity attentions as long as following dump may 99207ba6af4SMiriam Shitrit * cause false alarms by reading never written registers. We 99307ba6af4SMiriam Shitrit * will re-enable parity attentions right after the dump. 99407ba6af4SMiriam Shitrit */ 99507ba6af4SMiriam Shitrit 99607ba6af4SMiriam Shitrit /* Disable parity on path 0 */ 99707ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 99807ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 99907ba6af4SMiriam Shitrit 100007ba6af4SMiriam Shitrit /* Disable parity on path 1 */ 100107ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 100207ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 100307ba6af4SMiriam Shitrit 100407ba6af4SMiriam Shitrit /* Return to current function */ 100507ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 100607ba6af4SMiriam Shitrit 100707ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 100807ba6af4SMiriam Shitrit dump_hdr.preset = bp->dump_preset_idx; 100907ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 101007ba6af4SMiriam Shitrit 101107ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 101207ba6af4SMiriam Shitrit 101307ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 101407ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 101507ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 101607ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 101707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 101807ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 101907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 102007ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 102107ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 102207ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 102307ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 102407ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 102507ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 102607ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 102707ba6af4SMiriam Shitrit } 102807ba6af4SMiriam Shitrit 102907ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 103007ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 103107ba6af4SMiriam Shitrit 103207ba6af4SMiriam Shitrit /* Actually read the registers */ 103307ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 103407ba6af4SMiriam Shitrit 103507ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 0 */ 103607ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 103707ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 103807ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 103907ba6af4SMiriam Shitrit 104007ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 1 */ 104107ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 104207ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 104307ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 104407ba6af4SMiriam Shitrit 104507ba6af4SMiriam Shitrit /* Return to current function */ 104607ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 104707ba6af4SMiriam Shitrit 104807ba6af4SMiriam Shitrit return 0; 1049adfc5217SJeff Kirsher } 1050adfc5217SJeff Kirsher 1051adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 1052adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 1053adfc5217SJeff Kirsher { 1054adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1055adfc5217SJeff Kirsher 105668aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 105768aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1058adfc5217SJeff Kirsher 10598ca5e17eSAriel Elior bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 10608ca5e17eSAriel Elior 106168aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1062adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 1063cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 1064adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 1065adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 1066adfc5217SJeff Kirsher } 1067adfc5217SJeff Kirsher 1068adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1069adfc5217SJeff Kirsher { 1070adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1071adfc5217SJeff Kirsher 1072adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 1073adfc5217SJeff Kirsher wol->supported = 0; 1074adfc5217SJeff Kirsher wol->wolopts = 0; 1075adfc5217SJeff Kirsher } else { 1076adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 1077adfc5217SJeff Kirsher if (bp->wol) 1078adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 1079adfc5217SJeff Kirsher else 1080adfc5217SJeff Kirsher wol->wolopts = 0; 1081adfc5217SJeff Kirsher } 1082adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 1083adfc5217SJeff Kirsher } 1084adfc5217SJeff Kirsher 1085adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1086adfc5217SJeff Kirsher { 1087adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1088adfc5217SJeff Kirsher 108951c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 10902de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1091adfc5217SJeff Kirsher return -EINVAL; 109251c1a580SMerav Sicron } 1093adfc5217SJeff Kirsher 1094adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 109551c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 10962de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1097adfc5217SJeff Kirsher return -EINVAL; 109851c1a580SMerav Sicron } 1099adfc5217SJeff Kirsher bp->wol = 1; 1100adfc5217SJeff Kirsher } else 1101adfc5217SJeff Kirsher bp->wol = 0; 1102adfc5217SJeff Kirsher 1103adfc5217SJeff Kirsher return 0; 1104adfc5217SJeff Kirsher } 1105adfc5217SJeff Kirsher 1106adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 1107adfc5217SJeff Kirsher { 1108adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1109adfc5217SJeff Kirsher 1110adfc5217SJeff Kirsher return bp->msg_enable; 1111adfc5217SJeff Kirsher } 1112adfc5217SJeff Kirsher 1113adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1114adfc5217SJeff Kirsher { 1115adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1116adfc5217SJeff Kirsher 1117adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 1118adfc5217SJeff Kirsher /* dump MCP trace */ 1119ad5afc89SAriel Elior if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1120adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 1121adfc5217SJeff Kirsher bp->msg_enable = level; 1122adfc5217SJeff Kirsher } 1123adfc5217SJeff Kirsher } 1124adfc5217SJeff Kirsher 1125adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 1126adfc5217SJeff Kirsher { 1127adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1128adfc5217SJeff Kirsher 1129adfc5217SJeff Kirsher if (!bp->port.pmf) 1130adfc5217SJeff Kirsher return 0; 1131adfc5217SJeff Kirsher 1132adfc5217SJeff Kirsher if (netif_running(dev)) { 1133adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11345d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1135adfc5217SJeff Kirsher bnx2x_link_set(bp); 1136adfc5217SJeff Kirsher } 1137adfc5217SJeff Kirsher 1138adfc5217SJeff Kirsher return 0; 1139adfc5217SJeff Kirsher } 1140adfc5217SJeff Kirsher 1141adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 1142adfc5217SJeff Kirsher { 1143adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1144adfc5217SJeff Kirsher 1145adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1146adfc5217SJeff Kirsher return 0; 1147adfc5217SJeff Kirsher 1148adfc5217SJeff Kirsher return bp->link_vars.link_up; 1149adfc5217SJeff Kirsher } 1150adfc5217SJeff Kirsher 1151adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 1152adfc5217SJeff Kirsher { 1153adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1154adfc5217SJeff Kirsher 1155adfc5217SJeff Kirsher return bp->common.flash_size; 1156adfc5217SJeff Kirsher } 1157adfc5217SJeff Kirsher 115816a5fd92SYuval Mintz /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 115916a5fd92SYuval Mintz * had we done things the other way around, if two pfs from the same port would 1160f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 1161f16da43bSAriel Elior * as: 1162f16da43bSAriel Elior * pf A takes the port lock. 1163f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 1164f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 1165f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 1166f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 1167f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 1168f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 11692de67439SYuval Mintz * access corrupted by pf B) 1170f16da43bSAriel Elior */ 1171adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1172adfc5217SJeff Kirsher { 1173adfc5217SJeff Kirsher int port = BP_PORT(bp); 1174adfc5217SJeff Kirsher int count, i; 1175f16da43bSAriel Elior u32 val; 1176f16da43bSAriel Elior 1177f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1178f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1179adfc5217SJeff Kirsher 1180adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1181adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1182adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1183adfc5217SJeff Kirsher count *= 100; 1184adfc5217SJeff Kirsher 1185adfc5217SJeff Kirsher /* request access to nvram interface */ 1186adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1187adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1188adfc5217SJeff Kirsher 1189adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1190adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1191adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1192adfc5217SJeff Kirsher break; 1193adfc5217SJeff Kirsher 1194adfc5217SJeff Kirsher udelay(5); 1195adfc5217SJeff Kirsher } 1196adfc5217SJeff Kirsher 1197adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 119851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 119951c1a580SMerav Sicron "cannot get access to nvram interface\n"); 1200adfc5217SJeff Kirsher return -EBUSY; 1201adfc5217SJeff Kirsher } 1202adfc5217SJeff Kirsher 1203adfc5217SJeff Kirsher return 0; 1204adfc5217SJeff Kirsher } 1205adfc5217SJeff Kirsher 1206adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1207adfc5217SJeff Kirsher { 1208adfc5217SJeff Kirsher int port = BP_PORT(bp); 1209adfc5217SJeff Kirsher int count, i; 1210f16da43bSAriel Elior u32 val; 1211adfc5217SJeff Kirsher 1212adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1213adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1214adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1215adfc5217SJeff Kirsher count *= 100; 1216adfc5217SJeff Kirsher 1217adfc5217SJeff Kirsher /* relinquish nvram interface */ 1218adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1219adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1220adfc5217SJeff Kirsher 1221adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1222adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1223adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1224adfc5217SJeff Kirsher break; 1225adfc5217SJeff Kirsher 1226adfc5217SJeff Kirsher udelay(5); 1227adfc5217SJeff Kirsher } 1228adfc5217SJeff Kirsher 1229adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 123051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 123151c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1232adfc5217SJeff Kirsher return -EBUSY; 1233adfc5217SJeff Kirsher } 1234adfc5217SJeff Kirsher 1235f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1236f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1237adfc5217SJeff Kirsher return 0; 1238adfc5217SJeff Kirsher } 1239adfc5217SJeff Kirsher 1240adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1241adfc5217SJeff Kirsher { 1242adfc5217SJeff Kirsher u32 val; 1243adfc5217SJeff Kirsher 1244adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1245adfc5217SJeff Kirsher 1246adfc5217SJeff Kirsher /* enable both bits, even on read */ 1247adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1248adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1249adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1250adfc5217SJeff Kirsher } 1251adfc5217SJeff Kirsher 1252adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1253adfc5217SJeff Kirsher { 1254adfc5217SJeff Kirsher u32 val; 1255adfc5217SJeff Kirsher 1256adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1257adfc5217SJeff Kirsher 1258adfc5217SJeff Kirsher /* disable both bits, even after read */ 1259adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1260adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1261adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1262adfc5217SJeff Kirsher } 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1265adfc5217SJeff Kirsher u32 cmd_flags) 1266adfc5217SJeff Kirsher { 1267adfc5217SJeff Kirsher int count, i, rc; 1268adfc5217SJeff Kirsher u32 val; 1269adfc5217SJeff Kirsher 1270adfc5217SJeff Kirsher /* build the command word */ 1271adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1272adfc5217SJeff Kirsher 1273adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1274adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1277adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1278adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1279adfc5217SJeff Kirsher 1280adfc5217SJeff Kirsher /* issue a read command */ 1281adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1282adfc5217SJeff Kirsher 1283adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1284adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1285adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1286adfc5217SJeff Kirsher count *= 100; 1287adfc5217SJeff Kirsher 1288adfc5217SJeff Kirsher /* wait for completion */ 1289adfc5217SJeff Kirsher *ret_val = 0; 1290adfc5217SJeff Kirsher rc = -EBUSY; 1291adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1292adfc5217SJeff Kirsher udelay(5); 1293adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1294adfc5217SJeff Kirsher 1295adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1296adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1297adfc5217SJeff Kirsher /* we read nvram data in cpu order 1298adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 129907ba6af4SMiriam Shitrit * converting to big-endian will do the work 130007ba6af4SMiriam Shitrit */ 1301adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1302adfc5217SJeff Kirsher rc = 0; 1303adfc5217SJeff Kirsher break; 1304adfc5217SJeff Kirsher } 1305adfc5217SJeff Kirsher } 130651c1a580SMerav Sicron if (rc == -EBUSY) 130751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 130851c1a580SMerav Sicron "nvram read timeout expired\n"); 1309adfc5217SJeff Kirsher return rc; 1310adfc5217SJeff Kirsher } 1311adfc5217SJeff Kirsher 1312adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1313adfc5217SJeff Kirsher int buf_size) 1314adfc5217SJeff Kirsher { 1315adfc5217SJeff Kirsher int rc; 1316adfc5217SJeff Kirsher u32 cmd_flags; 1317adfc5217SJeff Kirsher __be32 val; 1318adfc5217SJeff Kirsher 1319adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 132051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1321adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1322adfc5217SJeff Kirsher offset, buf_size); 1323adfc5217SJeff Kirsher return -EINVAL; 1324adfc5217SJeff Kirsher } 1325adfc5217SJeff Kirsher 1326adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 132751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 132851c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1329adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1330adfc5217SJeff Kirsher return -EINVAL; 1331adfc5217SJeff Kirsher } 1332adfc5217SJeff Kirsher 1333adfc5217SJeff Kirsher /* request access to nvram interface */ 1334adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1335adfc5217SJeff Kirsher if (rc) 1336adfc5217SJeff Kirsher return rc; 1337adfc5217SJeff Kirsher 1338adfc5217SJeff Kirsher /* enable access to nvram interface */ 1339adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1340adfc5217SJeff Kirsher 1341adfc5217SJeff Kirsher /* read the first word(s) */ 1342adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1343adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1344adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1345adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1346adfc5217SJeff Kirsher 1347adfc5217SJeff Kirsher /* advance to the next dword */ 1348adfc5217SJeff Kirsher offset += sizeof(u32); 1349adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1350adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1351adfc5217SJeff Kirsher cmd_flags = 0; 1352adfc5217SJeff Kirsher } 1353adfc5217SJeff Kirsher 1354adfc5217SJeff Kirsher if (rc == 0) { 1355adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1356adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1357adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1358adfc5217SJeff Kirsher } 1359adfc5217SJeff Kirsher 1360adfc5217SJeff Kirsher /* disable access to nvram interface */ 1361adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1362adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1363adfc5217SJeff Kirsher 1364adfc5217SJeff Kirsher return rc; 1365adfc5217SJeff Kirsher } 1366adfc5217SJeff Kirsher 136785640952SDmitry Kravkov static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 136885640952SDmitry Kravkov int buf_size) 136985640952SDmitry Kravkov { 137085640952SDmitry Kravkov int rc; 137185640952SDmitry Kravkov 137285640952SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 137385640952SDmitry Kravkov 137485640952SDmitry Kravkov if (!rc) { 137585640952SDmitry Kravkov __be32 *be = (__be32 *)buf; 137685640952SDmitry Kravkov 137785640952SDmitry Kravkov while ((buf_size -= 4) >= 0) 137885640952SDmitry Kravkov *buf++ = be32_to_cpu(*be++); 137985640952SDmitry Kravkov } 138085640952SDmitry Kravkov 138185640952SDmitry Kravkov return rc; 138285640952SDmitry Kravkov } 138385640952SDmitry Kravkov 13843fb43eb2SYuval Mintz static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 13853fb43eb2SYuval Mintz { 13863fb43eb2SYuval Mintz int rc = 1; 13873fb43eb2SYuval Mintz u16 pm = 0; 13883fb43eb2SYuval Mintz struct net_device *dev = pci_get_drvdata(bp->pdev); 13893fb43eb2SYuval Mintz 13903fb43eb2SYuval Mintz if (bp->pm_cap) 13913fb43eb2SYuval Mintz rc = pci_read_config_word(bp->pdev, 13923fb43eb2SYuval Mintz bp->pm_cap + PCI_PM_CTRL, &pm); 13933fb43eb2SYuval Mintz 1394829a5071SYuval Mintz if ((rc && !netif_running(dev)) || 1395c957d09fSYuval Mintz (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 13963fb43eb2SYuval Mintz return false; 13973fb43eb2SYuval Mintz 13983fb43eb2SYuval Mintz return true; 13993fb43eb2SYuval Mintz } 14003fb43eb2SYuval Mintz 1401adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1402adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1403adfc5217SJeff Kirsher { 1404adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1405adfc5217SJeff Kirsher 14063fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 140751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 140851c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1409adfc5217SJeff Kirsher return -EAGAIN; 141051c1a580SMerav Sicron } 1411adfc5217SJeff Kirsher 141251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1413f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1414adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1415adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1416adfc5217SJeff Kirsher 1417adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1418adfc5217SJeff Kirsher 1419f1691dc6SDmitry Kravkov return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1420adfc5217SJeff Kirsher } 1421adfc5217SJeff Kirsher 142224ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 142324ea818eSYuval Mintz struct ethtool_eeprom *ee, 142424ea818eSYuval Mintz u8 *data) 142524ea818eSYuval Mintz { 142624ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1427669d6996SYaniv Rosner int rc = -EINVAL, phy_idx; 142824ea818eSYuval Mintz u8 *user_data = data; 1429669d6996SYaniv Rosner unsigned int start_addr = ee->offset, xfer_size = 0; 143024ea818eSYuval Mintz 14313fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 143224ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 143324ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 143424ea818eSYuval Mintz return -EAGAIN; 143524ea818eSYuval Mintz } 143624ea818eSYuval Mintz 143724ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1438669d6996SYaniv Rosner 1439669d6996SYaniv Rosner /* Read A0 section */ 1440669d6996SYaniv Rosner if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1441669d6996SYaniv Rosner /* Limit transfer size to the A0 section boundary */ 1442669d6996SYaniv Rosner if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1443669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1444669d6996SYaniv Rosner else 1445669d6996SYaniv Rosner xfer_size = ee->len; 144624ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 144724ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 144824ea818eSYuval Mintz &bp->link_params, 1449669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1450669d6996SYaniv Rosner start_addr, 145124ea818eSYuval Mintz xfer_size, 145224ea818eSYuval Mintz user_data); 1453669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1454669d6996SYaniv Rosner if (rc) { 1455669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1456669d6996SYaniv Rosner 1457669d6996SYaniv Rosner return -EINVAL; 1458669d6996SYaniv Rosner } 145924ea818eSYuval Mintz user_data += xfer_size; 1460669d6996SYaniv Rosner start_addr += xfer_size; 146124ea818eSYuval Mintz } 146224ea818eSYuval Mintz 1463669d6996SYaniv Rosner /* Read A2 section */ 1464669d6996SYaniv Rosner if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1465669d6996SYaniv Rosner (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1466669d6996SYaniv Rosner xfer_size = ee->len - xfer_size; 1467669d6996SYaniv Rosner /* Limit transfer size to the A2 section boundary */ 1468669d6996SYaniv Rosner if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1469669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1470669d6996SYaniv Rosner start_addr -= ETH_MODULE_SFF_8079_LEN; 1471669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1472669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1473669d6996SYaniv Rosner &bp->link_params, 1474669d6996SYaniv Rosner I2C_DEV_ADDR_A2, 1475669d6996SYaniv Rosner start_addr, 1476669d6996SYaniv Rosner xfer_size, 1477669d6996SYaniv Rosner user_data); 147824ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 1479669d6996SYaniv Rosner if (rc) { 1480669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1481669d6996SYaniv Rosner return -EINVAL; 1482669d6996SYaniv Rosner } 1483669d6996SYaniv Rosner } 148424ea818eSYuval Mintz return rc; 148524ea818eSYuval Mintz } 148624ea818eSYuval Mintz 148724ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 148824ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 148924ea818eSYuval Mintz { 149024ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1491669d6996SYaniv Rosner int phy_idx, rc; 1492669d6996SYaniv Rosner u8 sff8472_comp, diag_type; 1493669d6996SYaniv Rosner 14943fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 149524ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 149624ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 149724ea818eSYuval Mintz return -EAGAIN; 149824ea818eSYuval Mintz } 149924ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1500669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1501669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1502669d6996SYaniv Rosner &bp->link_params, 1503669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1504669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_ADDR, 1505669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_SIZE, 1506669d6996SYaniv Rosner &sff8472_comp); 1507669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1508669d6996SYaniv Rosner if (rc) { 1509669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1510669d6996SYaniv Rosner return -EINVAL; 1511669d6996SYaniv Rosner } 1512669d6996SYaniv Rosner 1513669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1514669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1515669d6996SYaniv Rosner &bp->link_params, 1516669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1517669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_ADDR, 1518669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_SIZE, 1519669d6996SYaniv Rosner &diag_type); 1520669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1521669d6996SYaniv Rosner if (rc) { 1522669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1523669d6996SYaniv Rosner return -EINVAL; 1524669d6996SYaniv Rosner } 1525669d6996SYaniv Rosner 1526669d6996SYaniv Rosner if (!sff8472_comp || 1527669d6996SYaniv Rosner (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 152824ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 152924ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1530669d6996SYaniv Rosner } else { 1531669d6996SYaniv Rosner modinfo->type = ETH_MODULE_SFF_8472; 1532669d6996SYaniv Rosner modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 153324ea818eSYuval Mintz } 1534669d6996SYaniv Rosner return 0; 153524ea818eSYuval Mintz } 153624ea818eSYuval Mintz 1537adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1538adfc5217SJeff Kirsher u32 cmd_flags) 1539adfc5217SJeff Kirsher { 1540adfc5217SJeff Kirsher int count, i, rc; 1541adfc5217SJeff Kirsher 1542adfc5217SJeff Kirsher /* build the command word */ 1543adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1544adfc5217SJeff Kirsher 1545adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1546adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1547adfc5217SJeff Kirsher 1548adfc5217SJeff Kirsher /* write the data */ 1549adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1550adfc5217SJeff Kirsher 1551adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1552adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1553adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1554adfc5217SJeff Kirsher 1555adfc5217SJeff Kirsher /* issue the write command */ 1556adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1557adfc5217SJeff Kirsher 1558adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1559adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1560adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1561adfc5217SJeff Kirsher count *= 100; 1562adfc5217SJeff Kirsher 1563adfc5217SJeff Kirsher /* wait for completion */ 1564adfc5217SJeff Kirsher rc = -EBUSY; 1565adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1566adfc5217SJeff Kirsher udelay(5); 1567adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1568adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1569adfc5217SJeff Kirsher rc = 0; 1570adfc5217SJeff Kirsher break; 1571adfc5217SJeff Kirsher } 1572adfc5217SJeff Kirsher } 1573adfc5217SJeff Kirsher 157451c1a580SMerav Sicron if (rc == -EBUSY) 157551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 157651c1a580SMerav Sicron "nvram write timeout expired\n"); 1577adfc5217SJeff Kirsher return rc; 1578adfc5217SJeff Kirsher } 1579adfc5217SJeff Kirsher 1580adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1581adfc5217SJeff Kirsher 1582adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1583adfc5217SJeff Kirsher int buf_size) 1584adfc5217SJeff Kirsher { 1585adfc5217SJeff Kirsher int rc; 158630c20b67SDmitry Kravkov u32 cmd_flags, align_offset, val; 158730c20b67SDmitry Kravkov __be32 val_be; 1588adfc5217SJeff Kirsher 1589adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 159051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 159151c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1592adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1593adfc5217SJeff Kirsher return -EINVAL; 1594adfc5217SJeff Kirsher } 1595adfc5217SJeff Kirsher 1596adfc5217SJeff Kirsher /* request access to nvram interface */ 1597adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1598adfc5217SJeff Kirsher if (rc) 1599adfc5217SJeff Kirsher return rc; 1600adfc5217SJeff Kirsher 1601adfc5217SJeff Kirsher /* enable access to nvram interface */ 1602adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1603adfc5217SJeff Kirsher 1604adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1605adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 160630c20b67SDmitry Kravkov rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1607adfc5217SJeff Kirsher 1608adfc5217SJeff Kirsher if (rc == 0) { 1609adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 161007ba6af4SMiriam Shitrit * convert it back to cpu order 161107ba6af4SMiriam Shitrit */ 161230c20b67SDmitry Kravkov val = be32_to_cpu(val_be); 161330c20b67SDmitry Kravkov 1614c957d09fSYuval Mintz val &= ~le32_to_cpu((__force __le32) 1615c957d09fSYuval Mintz (0xff << BYTE_OFFSET(offset))); 1616c957d09fSYuval Mintz val |= le32_to_cpu((__force __le32) 1617c957d09fSYuval Mintz (*data_buf << BYTE_OFFSET(offset))); 1618adfc5217SJeff Kirsher 1619adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1620adfc5217SJeff Kirsher cmd_flags); 1621adfc5217SJeff Kirsher } 1622adfc5217SJeff Kirsher 1623adfc5217SJeff Kirsher /* disable access to nvram interface */ 1624adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1625adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1626adfc5217SJeff Kirsher 1627adfc5217SJeff Kirsher return rc; 1628adfc5217SJeff Kirsher } 1629adfc5217SJeff Kirsher 1630adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1631adfc5217SJeff Kirsher int buf_size) 1632adfc5217SJeff Kirsher { 1633adfc5217SJeff Kirsher int rc; 1634adfc5217SJeff Kirsher u32 cmd_flags; 1635adfc5217SJeff Kirsher u32 val; 1636adfc5217SJeff Kirsher u32 written_so_far; 1637adfc5217SJeff Kirsher 1638adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1639adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1640adfc5217SJeff Kirsher 1641adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 164251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1643adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1644adfc5217SJeff Kirsher offset, buf_size); 1645adfc5217SJeff Kirsher return -EINVAL; 1646adfc5217SJeff Kirsher } 1647adfc5217SJeff Kirsher 1648adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 164951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 165051c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1651adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1652adfc5217SJeff Kirsher return -EINVAL; 1653adfc5217SJeff Kirsher } 1654adfc5217SJeff Kirsher 1655adfc5217SJeff Kirsher /* request access to nvram interface */ 1656adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1657adfc5217SJeff Kirsher if (rc) 1658adfc5217SJeff Kirsher return rc; 1659adfc5217SJeff Kirsher 1660adfc5217SJeff Kirsher /* enable access to nvram interface */ 1661adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1662adfc5217SJeff Kirsher 1663adfc5217SJeff Kirsher written_so_far = 0; 1664adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1665adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1666adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1667adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1668adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1669adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1670adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1671adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1672adfc5217SJeff Kirsher 1673adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1674adfc5217SJeff Kirsher 1675adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1676adfc5217SJeff Kirsher 1677adfc5217SJeff Kirsher /* advance to the next dword */ 1678adfc5217SJeff Kirsher offset += sizeof(u32); 1679adfc5217SJeff Kirsher data_buf += sizeof(u32); 1680adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1681adfc5217SJeff Kirsher cmd_flags = 0; 1682adfc5217SJeff Kirsher } 1683adfc5217SJeff Kirsher 1684adfc5217SJeff Kirsher /* disable access to nvram interface */ 1685adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1686adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1687adfc5217SJeff Kirsher 1688adfc5217SJeff Kirsher return rc; 1689adfc5217SJeff Kirsher } 1690adfc5217SJeff Kirsher 1691adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1692adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1693adfc5217SJeff Kirsher { 1694adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1695adfc5217SJeff Kirsher int port = BP_PORT(bp); 1696adfc5217SJeff Kirsher int rc = 0; 1697adfc5217SJeff Kirsher u32 ext_phy_config; 16983fb43eb2SYuval Mintz 16993fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 170051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 170151c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1702adfc5217SJeff Kirsher return -EAGAIN; 170351c1a580SMerav Sicron } 1704adfc5217SJeff Kirsher 170551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1706f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1707adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1708adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1709adfc5217SJeff Kirsher 1710adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1711adfc5217SJeff Kirsher 1712adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1713adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 171451c1a580SMerav Sicron !bp->port.pmf) { 171551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 171651c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1717adfc5217SJeff Kirsher return -EINVAL; 171851c1a580SMerav Sicron } 1719adfc5217SJeff Kirsher 1720adfc5217SJeff Kirsher ext_phy_config = 1721adfc5217SJeff Kirsher SHMEM_RD(bp, 1722adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1723adfc5217SJeff Kirsher 1724adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1725adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1726adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1727adfc5217SJeff Kirsher 1728adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1729adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1730adfc5217SJeff Kirsher &bp->link_vars, 0); 1731adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1732adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1733adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1734adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1735adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1736adfc5217SJeff Kirsher bnx2x_link_report(bp); 1737adfc5217SJeff Kirsher 1738adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1739adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1740adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1741adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1742adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1743adfc5217SJeff Kirsher &bp->link_vars, 1); 1744adfc5217SJeff Kirsher 1745adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1746adfc5217SJeff Kirsher &bp->link_vars); 1747adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1748adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1749adfc5217SJeff Kirsher } 1750adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1751adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1752adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1753adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1754adfc5217SJeff Kirsher 1755adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1756adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1757adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1758adfc5217SJeff Kirsher 1759adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1760adfc5217SJeff Kirsher 1761adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1762adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1763adfc5217SJeff Kirsher 1764adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1765adfc5217SJeff Kirsher msleep(500); 1766adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1767adfc5217SJeff Kirsher msleep(500); 1768adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1769adfc5217SJeff Kirsher } 1770adfc5217SJeff Kirsher } else 1771adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1772adfc5217SJeff Kirsher 1773adfc5217SJeff Kirsher return rc; 1774adfc5217SJeff Kirsher } 1775adfc5217SJeff Kirsher 1776adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1777adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1778adfc5217SJeff Kirsher { 1779adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1780adfc5217SJeff Kirsher 1781adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1782adfc5217SJeff Kirsher 1783adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1784adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1785adfc5217SJeff Kirsher 1786adfc5217SJeff Kirsher return 0; 1787adfc5217SJeff Kirsher } 1788adfc5217SJeff Kirsher 1789adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1790adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1791adfc5217SJeff Kirsher { 1792adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1793adfc5217SJeff Kirsher 1794adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1795adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1796adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1797adfc5217SJeff Kirsher 1798adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1799adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1800adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1801adfc5217SJeff Kirsher 1802adfc5217SJeff Kirsher if (netif_running(dev)) 1803adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1804adfc5217SJeff Kirsher 1805adfc5217SJeff Kirsher return 0; 1806adfc5217SJeff Kirsher } 1807adfc5217SJeff Kirsher 1808adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1809adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1810adfc5217SJeff Kirsher { 1811adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1812adfc5217SJeff Kirsher 1813adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1814adfc5217SJeff Kirsher 1815adfc5217SJeff Kirsher if (bp->rx_ring_size) 1816adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1817adfc5217SJeff Kirsher else 1818adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1819adfc5217SJeff Kirsher 1820a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1821adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1822adfc5217SJeff Kirsher } 1823adfc5217SJeff Kirsher 1824adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1825adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1826adfc5217SJeff Kirsher { 1827adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1828adfc5217SJeff Kirsher 182904c46736SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 183004c46736SYuval Mintz "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 183104c46736SYuval Mintz ering->rx_pending, ering->tx_pending); 183204c46736SYuval Mintz 1833adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 183451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 183551c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1836adfc5217SJeff Kirsher return -EAGAIN; 1837adfc5217SJeff Kirsher } 1838adfc5217SJeff Kirsher 1839adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1840adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1841adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1842a3348722SBarak Witkowski (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 184351c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 184451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1845adfc5217SJeff Kirsher return -EINVAL; 184651c1a580SMerav Sicron } 1847adfc5217SJeff Kirsher 1848adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1849adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1850adfc5217SJeff Kirsher 1851adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1852adfc5217SJeff Kirsher } 1853adfc5217SJeff Kirsher 1854adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1855adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1856adfc5217SJeff Kirsher { 1857adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1858adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 18599e7e8399SMintz Yuval int cfg_reg; 18609e7e8399SMintz Yuval 1861adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1862adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1863adfc5217SJeff Kirsher 18649e7e8399SMintz Yuval if (!epause->autoneg) 1865241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 18669e7e8399SMintz Yuval else 18679e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 18689e7e8399SMintz Yuval 18699e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1870adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 18719e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1872adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1873adfc5217SJeff Kirsher 187451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1875f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1876adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1877adfc5217SJeff Kirsher } 1878adfc5217SJeff Kirsher 1879adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1880adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1881adfc5217SJeff Kirsher { 1882adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1883adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1884adfc5217SJeff Kirsher if (IS_MF(bp)) 1885adfc5217SJeff Kirsher return 0; 1886adfc5217SJeff Kirsher 188751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1888f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1889adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1890adfc5217SJeff Kirsher 1891adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1892adfc5217SJeff Kirsher 1893adfc5217SJeff Kirsher if (epause->rx_pause) 1894adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1895adfc5217SJeff Kirsher 1896adfc5217SJeff Kirsher if (epause->tx_pause) 1897adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1898adfc5217SJeff Kirsher 1899adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1900adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1901adfc5217SJeff Kirsher 1902adfc5217SJeff Kirsher if (epause->autoneg) { 1903adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 190451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1905adfc5217SJeff Kirsher return -EINVAL; 1906adfc5217SJeff Kirsher } 1907adfc5217SJeff Kirsher 1908adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1909adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1910adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1911adfc5217SJeff Kirsher } 1912ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv = 0; 19135cd75f0cSYaniv Rosner if (epause->rx_pause) 19145cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 19155cd75f0cSYaniv Rosner 19165cd75f0cSYaniv Rosner if (epause->tx_pause) 19175cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1918ba35a0fdSYaniv Rosner 1919ba35a0fdSYaniv Rosner if (!bp->link_params.req_fc_auto_adv) 1920ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1921adfc5217SJeff Kirsher } 1922adfc5217SJeff Kirsher 192351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1924adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1925adfc5217SJeff Kirsher 1926adfc5217SJeff Kirsher if (netif_running(dev)) { 1927adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1928adfc5217SJeff Kirsher bnx2x_link_set(bp); 1929adfc5217SJeff Kirsher } 1930adfc5217SJeff Kirsher 1931adfc5217SJeff Kirsher return 0; 1932adfc5217SJeff Kirsher } 1933adfc5217SJeff Kirsher 19345889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1935cf2c1df6SMerav Sicron "register_test (offline) ", 1936cf2c1df6SMerav Sicron "memory_test (offline) ", 1937cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1938cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1939cf2c1df6SMerav Sicron "nvram_test (online) ", 1940cf2c1df6SMerav Sicron "interrupt_test (online) ", 1941cf2c1df6SMerav Sicron "link_test (online) " 1942adfc5217SJeff Kirsher }; 1943adfc5217SJeff Kirsher 19443521b419SYuval Mintz enum { 19453521b419SYuval Mintz BNX2X_PRI_FLAG_ISCSI, 19463521b419SYuval Mintz BNX2X_PRI_FLAG_FCOE, 19473521b419SYuval Mintz BNX2X_PRI_FLAG_STORAGE, 19483521b419SYuval Mintz BNX2X_PRI_FLAG_LEN, 19493521b419SYuval Mintz }; 19503521b419SYuval Mintz 19513521b419SYuval Mintz static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 19523521b419SYuval Mintz "iSCSI offload support", 19533521b419SYuval Mintz "FCoE offload support", 19543521b419SYuval Mintz "Storage only interface" 19553521b419SYuval Mintz }; 19563521b419SYuval Mintz 1957e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 1958e9939c80SYuval Mintz { 1959e9939c80SYuval Mintz u32 modes = 0; 1960e9939c80SYuval Mintz 1961e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 1962e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 1963e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 1964e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 1965e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 1966e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 1967e9939c80SYuval Mintz 1968e9939c80SYuval Mintz return modes; 1969e9939c80SYuval Mintz } 1970e9939c80SYuval Mintz 1971e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1972e9939c80SYuval Mintz { 1973e9939c80SYuval Mintz u32 eee_adv = 0; 1974e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 1975e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 1976e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 1977e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 1978e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 1979e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 1980e9939c80SYuval Mintz 1981e9939c80SYuval Mintz return eee_adv << shift; 1982e9939c80SYuval Mintz } 1983e9939c80SYuval Mintz 1984e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1985e9939c80SYuval Mintz { 1986e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1987e9939c80SYuval Mintz u32 eee_cfg; 1988e9939c80SYuval Mintz 1989e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1990e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1991e9939c80SYuval Mintz return -EOPNOTSUPP; 1992e9939c80SYuval Mintz } 1993e9939c80SYuval Mintz 199408e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1995e9939c80SYuval Mintz 1996e9939c80SYuval Mintz edata->supported = 1997e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 1998e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 1999e9939c80SYuval Mintz 2000e9939c80SYuval Mintz edata->advertised = 2001e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2002e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2003e9939c80SYuval Mintz edata->lp_advertised = 2004e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2005e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2006e9939c80SYuval Mintz 2007e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 2008e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2009e9939c80SYuval Mintz 2010e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2011e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2012e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2013e9939c80SYuval Mintz 2014e9939c80SYuval Mintz return 0; 2015e9939c80SYuval Mintz } 2016e9939c80SYuval Mintz 2017e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2018e9939c80SYuval Mintz { 2019e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2020e9939c80SYuval Mintz u32 eee_cfg; 2021e9939c80SYuval Mintz u32 advertised; 2022e9939c80SYuval Mintz 2023e9939c80SYuval Mintz if (IS_MF(bp)) 2024e9939c80SYuval Mintz return 0; 2025e9939c80SYuval Mintz 2026e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2027e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2028e9939c80SYuval Mintz return -EOPNOTSUPP; 2029e9939c80SYuval Mintz } 2030e9939c80SYuval Mintz 203108e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2032e9939c80SYuval Mintz 2033e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2034e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2035e9939c80SYuval Mintz return -EOPNOTSUPP; 2036e9939c80SYuval Mintz } 2037e9939c80SYuval Mintz 2038e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 2039e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2040e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2041e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2042efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 2043e9939c80SYuval Mintz return -EINVAL; 2044e9939c80SYuval Mintz } 2045e9939c80SYuval Mintz 2046e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2047e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2048e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 2049e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 2050e9939c80SYuval Mintz return -EINVAL; 2051e9939c80SYuval Mintz } 2052e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 2053e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2054e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2055e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 2056e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2057e9939c80SYuval Mintz return -EINVAL; 2058e9939c80SYuval Mintz } 2059e9939c80SYuval Mintz 2060e9939c80SYuval Mintz /* All is well; Apply changes*/ 2061e9939c80SYuval Mintz if (edata->eee_enabled) 2062e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2063e9939c80SYuval Mintz else 2064e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2065e9939c80SYuval Mintz 2066e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 2067e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2068e9939c80SYuval Mintz else 2069e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2070e9939c80SYuval Mintz 2071e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2072e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2073e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 2074e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 2075e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 2076e9939c80SYuval Mintz 207716a5fd92SYuval Mintz /* Restart link to propagate changes */ 2078e9939c80SYuval Mintz if (netif_running(dev)) { 2079e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 20805d07d868SYuval Mintz bnx2x_force_link_reset(bp); 2081e9939c80SYuval Mintz bnx2x_link_set(bp); 2082e9939c80SYuval Mintz } 2083e9939c80SYuval Mintz 2084e9939c80SYuval Mintz return 0; 2085e9939c80SYuval Mintz } 2086e9939c80SYuval Mintz 2087adfc5217SJeff Kirsher enum { 2088adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 2089adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 2090adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 2091adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 2092adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 2093adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 2094adfc5217SJeff Kirsher }; 2095adfc5217SJeff Kirsher 2096adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2097adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2098adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2099adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2100adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2101adfc5217SJeff Kirsher 2102adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2103adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2104adfc5217SJeff Kirsher 2105adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 2106adfc5217SJeff Kirsher { 2107adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 2108adfc5217SJeff Kirsher u32 wr_val = 0, hw; 2109adfc5217SJeff Kirsher int port = BP_PORT(bp); 2110adfc5217SJeff Kirsher static const struct { 2111adfc5217SJeff Kirsher u32 hw; 2112adfc5217SJeff Kirsher u32 offset0; 2113adfc5217SJeff Kirsher u32 offset1; 2114adfc5217SJeff Kirsher u32 mask; 2115adfc5217SJeff Kirsher } reg_tbl[] = { 2116adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 2117adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2118adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2119adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2120adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 2121adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 2122adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2123adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2124adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2125adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2126adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 2127adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2128adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2129adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2130adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2131adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2132adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2133adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2134adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2135adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2136adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 2137adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2138adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2139adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2140adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2141adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 2142adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2143adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2144adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2145adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2146adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2147adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2148adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2149adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2150adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2151adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2152adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2153adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2154adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2155adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2156adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2157adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2158adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2159adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2160adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2161adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2162adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2163adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2164adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2165adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2166adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2167adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2168adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2169adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2170adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2171adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2172adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2173adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2174adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2175adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2176adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 2177adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2178adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2179adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2180adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2181adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2182adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2183adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2184adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2185adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2186adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2187adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2188adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2189adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2190adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2191adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2192adfc5217SJeff Kirsher 2193adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2194adfc5217SJeff Kirsher }; 2195adfc5217SJeff Kirsher 21963fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 219751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 219851c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2199adfc5217SJeff Kirsher return rc; 220051c1a580SMerav Sicron } 2201adfc5217SJeff Kirsher 2202adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2203adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 2204adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2205adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 2206adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2207adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 2208adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 2209adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 2210adfc5217SJeff Kirsher else /* e3 A0 */ 2211adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 2212adfc5217SJeff Kirsher 2213adfc5217SJeff Kirsher /* Repeat the test twice: 221407ba6af4SMiriam Shitrit * First by writing 0x00000000, second by writing 0xffffffff 221507ba6af4SMiriam Shitrit */ 2216adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 2217adfc5217SJeff Kirsher 2218adfc5217SJeff Kirsher switch (idx) { 2219adfc5217SJeff Kirsher case 0: 2220adfc5217SJeff Kirsher wr_val = 0; 2221adfc5217SJeff Kirsher break; 2222adfc5217SJeff Kirsher case 1: 2223adfc5217SJeff Kirsher wr_val = 0xffffffff; 2224adfc5217SJeff Kirsher break; 2225adfc5217SJeff Kirsher } 2226adfc5217SJeff Kirsher 2227adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2228adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 2229adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 2230adfc5217SJeff Kirsher continue; 2231adfc5217SJeff Kirsher 2232adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2233adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 2234adfc5217SJeff Kirsher 2235adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 2236adfc5217SJeff Kirsher 2237adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 2238adfc5217SJeff Kirsher 2239adfc5217SJeff Kirsher val = REG_RD(bp, offset); 2240adfc5217SJeff Kirsher 2241adfc5217SJeff Kirsher /* Restore the original register's value */ 2242adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 2243adfc5217SJeff Kirsher 2244adfc5217SJeff Kirsher /* verify value is as expected */ 2245adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 224651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2247adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2248adfc5217SJeff Kirsher offset, val, wr_val, mask); 2249adfc5217SJeff Kirsher goto test_reg_exit; 2250adfc5217SJeff Kirsher } 2251adfc5217SJeff Kirsher } 2252adfc5217SJeff Kirsher } 2253adfc5217SJeff Kirsher 2254adfc5217SJeff Kirsher rc = 0; 2255adfc5217SJeff Kirsher 2256adfc5217SJeff Kirsher test_reg_exit: 2257adfc5217SJeff Kirsher return rc; 2258adfc5217SJeff Kirsher } 2259adfc5217SJeff Kirsher 2260adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 2261adfc5217SJeff Kirsher { 2262adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 2263adfc5217SJeff Kirsher u32 val, index; 2264adfc5217SJeff Kirsher static const struct { 2265adfc5217SJeff Kirsher u32 offset; 2266adfc5217SJeff Kirsher int size; 2267adfc5217SJeff Kirsher } mem_tbl[] = { 2268adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2269adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2270adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2271adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2272adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2273adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2274adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2275adfc5217SJeff Kirsher 2276adfc5217SJeff Kirsher { 0xffffffff, 0 } 2277adfc5217SJeff Kirsher }; 2278adfc5217SJeff Kirsher 2279adfc5217SJeff Kirsher static const struct { 2280adfc5217SJeff Kirsher char *name; 2281adfc5217SJeff Kirsher u32 offset; 2282adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2283adfc5217SJeff Kirsher } prty_tbl[] = { 2284adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2285adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2286adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2287adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 2288adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2289adfc5217SJeff Kirsher {0, 0, 0, 0} }, 2290adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2291adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2292adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2293adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2294adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2295adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 2296adfc5217SJeff Kirsher 2297adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 2298adfc5217SJeff Kirsher }; 2299adfc5217SJeff Kirsher 23003fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 230151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 230251c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2303adfc5217SJeff Kirsher return rc; 230451c1a580SMerav Sicron } 2305adfc5217SJeff Kirsher 2306adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2307adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 2308adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2309adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 2310adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2311adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 2312adfc5217SJeff Kirsher else /* e3 */ 2313adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 2314adfc5217SJeff Kirsher 2315adfc5217SJeff Kirsher /* pre-Check the parity status */ 2316adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2317adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2318adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 231951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2320adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2321adfc5217SJeff Kirsher goto test_mem_exit; 2322adfc5217SJeff Kirsher } 2323adfc5217SJeff Kirsher } 2324adfc5217SJeff Kirsher 2325adfc5217SJeff Kirsher /* Go through all the memories */ 2326adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2327adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 2328adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 2329adfc5217SJeff Kirsher 2330adfc5217SJeff Kirsher /* Check the parity status */ 2331adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2332adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2333adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 233451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2335adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2336adfc5217SJeff Kirsher goto test_mem_exit; 2337adfc5217SJeff Kirsher } 2338adfc5217SJeff Kirsher } 2339adfc5217SJeff Kirsher 2340adfc5217SJeff Kirsher rc = 0; 2341adfc5217SJeff Kirsher 2342adfc5217SJeff Kirsher test_mem_exit: 2343adfc5217SJeff Kirsher return rc; 2344adfc5217SJeff Kirsher } 2345adfc5217SJeff Kirsher 2346adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2347adfc5217SJeff Kirsher { 2348adfc5217SJeff Kirsher int cnt = 1400; 2349adfc5217SJeff Kirsher 2350adfc5217SJeff Kirsher if (link_up) { 2351adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2352adfc5217SJeff Kirsher msleep(20); 2353adfc5217SJeff Kirsher 2354adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 235551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 23568970b2e4SMerav Sicron 23578970b2e4SMerav Sicron cnt = 1400; 23588970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 23598970b2e4SMerav Sicron msleep(20); 23608970b2e4SMerav Sicron 23618970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 23628970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 23638970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2364adfc5217SJeff Kirsher } 2365adfc5217SJeff Kirsher } 2366adfc5217SJeff Kirsher 2367adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2368adfc5217SJeff Kirsher { 2369adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2370adfc5217SJeff Kirsher struct sk_buff *skb; 2371adfc5217SJeff Kirsher unsigned char *packet; 2372adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2373adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 237465565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2375adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2376adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2377b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2378adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2379adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2380adfc5217SJeff Kirsher dma_addr_t mapping; 2381adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2382adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2383adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2384adfc5217SJeff Kirsher u16 len; 2385adfc5217SJeff Kirsher int rc = -ENODEV; 2386e52fcb24SEric Dumazet u8 *data; 23878970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 23888970b2e4SMerav Sicron txdata->txq_index); 2389adfc5217SJeff Kirsher 2390adfc5217SJeff Kirsher /* check the loopback mode */ 2391adfc5217SJeff Kirsher switch (loopback_mode) { 2392adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 23938970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 23948970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2395adfc5217SJeff Kirsher return -EINVAL; 23968970b2e4SMerav Sicron } 2397adfc5217SJeff Kirsher break; 2398adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 239932911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 240032911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 240132911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 240232911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 240332911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 240432911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 240532911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 240632911333SYaniv Rosner else 240732911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 240832911333SYaniv Rosner } else 240932911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 241032911333SYaniv Rosner 2411adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2412adfc5217SJeff Kirsher break; 24138970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 24148970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 24158970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24168970b2e4SMerav Sicron "Can't configure external loopback\n"); 24178970b2e4SMerav Sicron return -EINVAL; 24188970b2e4SMerav Sicron } 24198970b2e4SMerav Sicron break; 2420adfc5217SJeff Kirsher default: 242151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2422adfc5217SJeff Kirsher return -EINVAL; 2423adfc5217SJeff Kirsher } 2424adfc5217SJeff Kirsher 2425adfc5217SJeff Kirsher /* prepare the loopback packet */ 2426adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2427adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2428adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2429adfc5217SJeff Kirsher if (!skb) { 243051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2431adfc5217SJeff Kirsher rc = -ENOMEM; 2432adfc5217SJeff Kirsher goto test_loopback_exit; 2433adfc5217SJeff Kirsher } 2434adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2435adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2436adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 2437adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2438adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2439adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2440adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2441adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2442adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2443adfc5217SJeff Kirsher rc = -ENOMEM; 2444adfc5217SJeff Kirsher dev_kfree_skb(skb); 244551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2446adfc5217SJeff Kirsher goto test_loopback_exit; 2447adfc5217SJeff Kirsher } 2448adfc5217SJeff Kirsher 2449adfc5217SJeff Kirsher /* send the loopback packet */ 2450adfc5217SJeff Kirsher num_pkts = 0; 2451adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2452adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2453adfc5217SJeff Kirsher 245473dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 245573dbb5e1SDmitry Kravkov 2456adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2457adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2458adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2459adfc5217SJeff Kirsher tx_buf->skb = skb; 2460adfc5217SJeff Kirsher tx_buf->flags = 0; 2461adfc5217SJeff Kirsher 2462adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2463adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2464adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2465adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2466adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2467adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2468adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2469adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2470adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2471adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2472adfc5217SJeff Kirsher 1); 247396bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 247496bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 247596bed4b9SYuval Mintz 0); 2476adfc5217SJeff Kirsher 2477adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2478adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2479adfc5217SJeff Kirsher 248096bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 248196bed4b9SYuval Mintz u16 global_data = 0; 248296bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 248396bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2484adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 248596bed4b9SYuval Mintz SET_FLAG(global_data, 248696bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 248796bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 248896bed4b9SYuval Mintz } else { 248996bed4b9SYuval Mintz u32 parsing_data = 0; 249096bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 249196bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 249296bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 249396bed4b9SYuval Mintz SET_FLAG(parsing_data, 249496bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 249596bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 249696bed4b9SYuval Mintz } 2497adfc5217SJeff Kirsher wmb(); 2498adfc5217SJeff Kirsher 2499adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2500adfc5217SJeff Kirsher barrier(); 2501adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2502adfc5217SJeff Kirsher 2503adfc5217SJeff Kirsher mmiowb(); 2504adfc5217SJeff Kirsher barrier(); 2505adfc5217SJeff Kirsher 2506adfc5217SJeff Kirsher num_pkts++; 2507adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2508adfc5217SJeff Kirsher 2509adfc5217SJeff Kirsher udelay(100); 2510adfc5217SJeff Kirsher 2511adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2512adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2513adfc5217SJeff Kirsher goto test_loopback_exit; 2514adfc5217SJeff Kirsher 2515adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2516adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2517adfc5217SJeff Kirsher * disabled. 2518adfc5217SJeff Kirsher */ 2519adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2520adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2521adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2522adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2523adfc5217SJeff Kirsher */ 2524adfc5217SJeff Kirsher local_bh_disable(); 2525adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2526adfc5217SJeff Kirsher local_bh_enable(); 2527adfc5217SJeff Kirsher } 2528adfc5217SJeff Kirsher 2529adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2530adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2531adfc5217SJeff Kirsher goto test_loopback_exit; 2532adfc5217SJeff Kirsher 2533b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2534adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2535adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2536adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2537adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2538adfc5217SJeff Kirsher 2539621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2540adfc5217SJeff Kirsher if (len != pkt_size) 2541adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2542adfc5217SJeff Kirsher 2543adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2544adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2545adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2546adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2547e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2548adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2549e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2550adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2551adfc5217SJeff Kirsher 2552adfc5217SJeff Kirsher rc = 0; 2553adfc5217SJeff Kirsher 2554adfc5217SJeff Kirsher test_loopback_rx_exit: 2555adfc5217SJeff Kirsher 2556adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2557adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2558adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2559adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2560adfc5217SJeff Kirsher 2561adfc5217SJeff Kirsher /* Update producers */ 2562adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2563adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2564adfc5217SJeff Kirsher 2565adfc5217SJeff Kirsher test_loopback_exit: 2566adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2567adfc5217SJeff Kirsher 2568adfc5217SJeff Kirsher return rc; 2569adfc5217SJeff Kirsher } 2570adfc5217SJeff Kirsher 2571adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2572adfc5217SJeff Kirsher { 2573adfc5217SJeff Kirsher int rc = 0, res; 2574adfc5217SJeff Kirsher 2575adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2576adfc5217SJeff Kirsher return rc; 2577adfc5217SJeff Kirsher 2578adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2579adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2580adfc5217SJeff Kirsher 2581adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2582adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2583adfc5217SJeff Kirsher 2584adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2585adfc5217SJeff Kirsher if (res) { 258651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2587adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2588adfc5217SJeff Kirsher } 2589adfc5217SJeff Kirsher 2590adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2591adfc5217SJeff Kirsher if (res) { 259251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2593adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2594adfc5217SJeff Kirsher } 2595adfc5217SJeff Kirsher 2596adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2597adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2598adfc5217SJeff Kirsher 2599adfc5217SJeff Kirsher return rc; 2600adfc5217SJeff Kirsher } 2601adfc5217SJeff Kirsher 26028970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 26038970b2e4SMerav Sicron { 26048970b2e4SMerav Sicron int rc; 26058970b2e4SMerav Sicron u8 is_serdes = 26068970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 26078970b2e4SMerav Sicron 26088970b2e4SMerav Sicron if (BP_NOMCP(bp)) 26098970b2e4SMerav Sicron return -ENODEV; 26108970b2e4SMerav Sicron 26118970b2e4SMerav Sicron if (!netif_running(bp->dev)) 26128970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 26138970b2e4SMerav Sicron 26145d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 26158970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 26168970b2e4SMerav Sicron if (rc) { 26178970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26188970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 26198970b2e4SMerav Sicron return -ENODEV; 26208970b2e4SMerav Sicron } 26218970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 26228970b2e4SMerav Sicron 26238970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 26248970b2e4SMerav Sicron 26258970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 26268970b2e4SMerav Sicron if (rc) 26278970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 26288970b2e4SMerav Sicron 26298970b2e4SMerav Sicron bnx2x_netif_start(bp); 26308970b2e4SMerav Sicron 26318970b2e4SMerav Sicron return rc; 26328970b2e4SMerav Sicron } 26338970b2e4SMerav Sicron 2634edb944d2SDmitry Kravkov struct code_entry { 2635edb944d2SDmitry Kravkov u32 sram_start_addr; 2636edb944d2SDmitry Kravkov u32 code_attribute; 2637edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_MASK 0xf0800003 2638edb944d2SDmitry Kravkov #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2639edb944d2SDmitry Kravkov #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2640edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2641edb944d2SDmitry Kravkov u32 nvm_start_addr; 2642edb944d2SDmitry Kravkov }; 2643edb944d2SDmitry Kravkov 2644edb944d2SDmitry Kravkov #define CODE_ENTRY_MAX 16 2645edb944d2SDmitry Kravkov #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2646edb944d2SDmitry Kravkov #define MAX_IMAGES_IN_EXTENDED_DIR 64 2647edb944d2SDmitry Kravkov #define NVRAM_DIR_OFFSET 0x14 2648edb944d2SDmitry Kravkov 2649edb944d2SDmitry Kravkov #define EXTENDED_DIR_EXISTS(code) \ 2650edb944d2SDmitry Kravkov ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2651edb944d2SDmitry Kravkov (code & CODE_IMAGE_LENGTH_MASK) != 0) 2652edb944d2SDmitry Kravkov 2653adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2654edb944d2SDmitry Kravkov #define CRC_BUFF_SIZE 256 2655edb944d2SDmitry Kravkov 2656edb944d2SDmitry Kravkov static int bnx2x_nvram_crc(struct bnx2x *bp, 2657edb944d2SDmitry Kravkov int offset, 2658edb944d2SDmitry Kravkov int size, 2659edb944d2SDmitry Kravkov u8 *buff) 2660edb944d2SDmitry Kravkov { 2661edb944d2SDmitry Kravkov u32 crc = ~0; 2662edb944d2SDmitry Kravkov int rc = 0, done = 0; 2663edb944d2SDmitry Kravkov 2664edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2665edb944d2SDmitry Kravkov "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2666edb944d2SDmitry Kravkov 2667edb944d2SDmitry Kravkov while (done < size) { 2668edb944d2SDmitry Kravkov int count = min_t(int, size - done, CRC_BUFF_SIZE); 2669edb944d2SDmitry Kravkov 2670edb944d2SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2671edb944d2SDmitry Kravkov 2672edb944d2SDmitry Kravkov if (rc) 2673edb944d2SDmitry Kravkov return rc; 2674edb944d2SDmitry Kravkov 2675edb944d2SDmitry Kravkov crc = crc32_le(crc, buff, count); 2676edb944d2SDmitry Kravkov done += count; 2677edb944d2SDmitry Kravkov } 2678edb944d2SDmitry Kravkov 2679edb944d2SDmitry Kravkov if (crc != CRC32_RESIDUAL) 2680edb944d2SDmitry Kravkov rc = -EINVAL; 2681edb944d2SDmitry Kravkov 2682edb944d2SDmitry Kravkov return rc; 2683edb944d2SDmitry Kravkov } 2684edb944d2SDmitry Kravkov 2685edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2686edb944d2SDmitry Kravkov struct code_entry *entry, 2687edb944d2SDmitry Kravkov u8 *buff) 2688edb944d2SDmitry Kravkov { 2689edb944d2SDmitry Kravkov size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2690edb944d2SDmitry Kravkov u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2691edb944d2SDmitry Kravkov int rc; 2692edb944d2SDmitry Kravkov 2693edb944d2SDmitry Kravkov /* Zero-length images and AFEX profiles do not have CRC */ 2694edb944d2SDmitry Kravkov if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2695edb944d2SDmitry Kravkov return 0; 2696edb944d2SDmitry Kravkov 2697edb944d2SDmitry Kravkov rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2698edb944d2SDmitry Kravkov if (rc) 2699edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2700edb944d2SDmitry Kravkov "image %x has failed crc test (rc %d)\n", type, rc); 2701edb944d2SDmitry Kravkov 2702edb944d2SDmitry Kravkov return rc; 2703edb944d2SDmitry Kravkov } 2704edb944d2SDmitry Kravkov 2705edb944d2SDmitry Kravkov static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2706edb944d2SDmitry Kravkov { 2707edb944d2SDmitry Kravkov int rc; 2708edb944d2SDmitry Kravkov struct code_entry entry; 2709edb944d2SDmitry Kravkov 2710edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2711edb944d2SDmitry Kravkov if (rc) 2712edb944d2SDmitry Kravkov return rc; 2713edb944d2SDmitry Kravkov 2714edb944d2SDmitry Kravkov return bnx2x_test_nvram_dir(bp, &entry, buff); 2715edb944d2SDmitry Kravkov } 2716edb944d2SDmitry Kravkov 2717edb944d2SDmitry Kravkov static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2718edb944d2SDmitry Kravkov { 2719edb944d2SDmitry Kravkov u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2720edb944d2SDmitry Kravkov struct code_entry entry; 2721edb944d2SDmitry Kravkov int i; 2722edb944d2SDmitry Kravkov 2723edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 2724edb944d2SDmitry Kravkov dir_offset + 2725edb944d2SDmitry Kravkov sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2726edb944d2SDmitry Kravkov (u32 *)&entry, sizeof(entry)); 2727edb944d2SDmitry Kravkov if (rc) 2728edb944d2SDmitry Kravkov return rc; 2729edb944d2SDmitry Kravkov 2730edb944d2SDmitry Kravkov if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2731edb944d2SDmitry Kravkov return 0; 2732edb944d2SDmitry Kravkov 2733edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2734edb944d2SDmitry Kravkov &cnt, sizeof(u32)); 2735edb944d2SDmitry Kravkov if (rc) 2736edb944d2SDmitry Kravkov return rc; 2737edb944d2SDmitry Kravkov 2738edb944d2SDmitry Kravkov dir_offset = entry.nvm_start_addr + 8; 2739edb944d2SDmitry Kravkov 2740edb944d2SDmitry Kravkov for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2741edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2742edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2743edb944d2SDmitry Kravkov buff); 2744edb944d2SDmitry Kravkov if (rc) 2745edb944d2SDmitry Kravkov return rc; 2746edb944d2SDmitry Kravkov } 2747edb944d2SDmitry Kravkov 2748edb944d2SDmitry Kravkov return 0; 2749edb944d2SDmitry Kravkov } 2750edb944d2SDmitry Kravkov 2751edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2752edb944d2SDmitry Kravkov { 2753edb944d2SDmitry Kravkov u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2754edb944d2SDmitry Kravkov int i; 2755edb944d2SDmitry Kravkov 2756edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2757edb944d2SDmitry Kravkov 2758edb944d2SDmitry Kravkov for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2759edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2760edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2761edb944d2SDmitry Kravkov buff); 2762edb944d2SDmitry Kravkov if (rc) 2763edb944d2SDmitry Kravkov return rc; 2764edb944d2SDmitry Kravkov } 2765edb944d2SDmitry Kravkov 2766edb944d2SDmitry Kravkov return bnx2x_test_nvram_ext_dirs(bp, buff); 2767edb944d2SDmitry Kravkov } 2768edb944d2SDmitry Kravkov 2769edb944d2SDmitry Kravkov struct crc_pair { 2770edb944d2SDmitry Kravkov int offset; 2771edb944d2SDmitry Kravkov int size; 2772edb944d2SDmitry Kravkov }; 2773edb944d2SDmitry Kravkov 2774edb944d2SDmitry Kravkov static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2775edb944d2SDmitry Kravkov const struct crc_pair *nvram_tbl, u8 *buf) 2776edb944d2SDmitry Kravkov { 2777edb944d2SDmitry Kravkov int i; 2778edb944d2SDmitry Kravkov 2779edb944d2SDmitry Kravkov for (i = 0; nvram_tbl[i].size; i++) { 2780edb944d2SDmitry Kravkov int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2781edb944d2SDmitry Kravkov nvram_tbl[i].size, buf); 2782edb944d2SDmitry Kravkov if (rc) { 2783edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2784edb944d2SDmitry Kravkov "nvram_tbl[%d] has failed crc test (rc %d)\n", 2785edb944d2SDmitry Kravkov i, rc); 2786edb944d2SDmitry Kravkov return rc; 2787edb944d2SDmitry Kravkov } 2788edb944d2SDmitry Kravkov } 2789edb944d2SDmitry Kravkov 2790edb944d2SDmitry Kravkov return 0; 2791edb944d2SDmitry Kravkov } 2792adfc5217SJeff Kirsher 2793adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2794adfc5217SJeff Kirsher { 2795edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl[] = { 2796adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2797adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2798adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2799adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2800adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2801adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2802adfc5217SJeff Kirsher { 0, 0 } 2803adfc5217SJeff Kirsher }; 2804edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl2[] = { 2805edb944d2SDmitry Kravkov { 0x7e8, 0x350 }, /* manuf_info2 */ 2806edb944d2SDmitry Kravkov { 0xb38, 0xf0 }, /* feature_info */ 2807edb944d2SDmitry Kravkov { 0, 0 } 2808edb944d2SDmitry Kravkov }; 2809edb944d2SDmitry Kravkov 281085640952SDmitry Kravkov u8 *buf; 2811edb944d2SDmitry Kravkov int rc; 2812edb944d2SDmitry Kravkov u32 magic; 2813adfc5217SJeff Kirsher 2814adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2815adfc5217SJeff Kirsher return 0; 2816adfc5217SJeff Kirsher 2817edb944d2SDmitry Kravkov buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2818afa13b4bSMintz Yuval if (!buf) { 281951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2820afa13b4bSMintz Yuval rc = -ENOMEM; 2821afa13b4bSMintz Yuval goto test_nvram_exit; 2822afa13b4bSMintz Yuval } 2823afa13b4bSMintz Yuval 282485640952SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2825adfc5217SJeff Kirsher if (rc) { 282651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 282751c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2828adfc5217SJeff Kirsher goto test_nvram_exit; 2829adfc5217SJeff Kirsher } 2830adfc5217SJeff Kirsher 2831adfc5217SJeff Kirsher if (magic != 0x669955aa) { 283251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 283351c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2834adfc5217SJeff Kirsher rc = -ENODEV; 2835adfc5217SJeff Kirsher goto test_nvram_exit; 2836adfc5217SJeff Kirsher } 2837adfc5217SJeff Kirsher 2838edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2839edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2840edb944d2SDmitry Kravkov if (rc) 2841adfc5217SJeff Kirsher goto test_nvram_exit; 2842adfc5217SJeff Kirsher 2843edb944d2SDmitry Kravkov if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2844edb944d2SDmitry Kravkov u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2845edb944d2SDmitry Kravkov SHARED_HW_CFG_HIDE_PORT1; 2846edb944d2SDmitry Kravkov 2847edb944d2SDmitry Kravkov if (!hide) { 284851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2849edb944d2SDmitry Kravkov "Port 1 CRC test-set\n"); 2850edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2851edb944d2SDmitry Kravkov if (rc) 2852adfc5217SJeff Kirsher goto test_nvram_exit; 2853adfc5217SJeff Kirsher } 2854adfc5217SJeff Kirsher } 2855adfc5217SJeff Kirsher 2856edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_dirs(bp, buf); 2857edb944d2SDmitry Kravkov 2858adfc5217SJeff Kirsher test_nvram_exit: 2859afa13b4bSMintz Yuval kfree(buf); 2860adfc5217SJeff Kirsher return rc; 2861adfc5217SJeff Kirsher } 2862adfc5217SJeff Kirsher 2863adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2864adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2865adfc5217SJeff Kirsher { 28663b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2867adfc5217SJeff Kirsher 286851c1a580SMerav Sicron if (!netif_running(bp->dev)) { 286951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 287051c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2871adfc5217SJeff Kirsher return -ENODEV; 287251c1a580SMerav Sicron } 2873adfc5217SJeff Kirsher 287415192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2875adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2876adfc5217SJeff Kirsher 2877adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2878adfc5217SJeff Kirsher 2879adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2880adfc5217SJeff Kirsher } 2881adfc5217SJeff Kirsher 2882adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2883adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2884adfc5217SJeff Kirsher { 2885adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2886a336ca7cSYaniv Rosner u8 is_serdes, link_up; 2887a336ca7cSYaniv Rosner int rc, cnt = 0; 2888cf2c1df6SMerav Sicron 2889adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 289051c1a580SMerav Sicron netdev_err(bp->dev, 289151c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2892adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2893adfc5217SJeff Kirsher return; 2894adfc5217SJeff Kirsher } 28952de67439SYuval Mintz 28968970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 28978970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 28988970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 28998970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2900adfc5217SJeff Kirsher 2901cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2902adfc5217SJeff Kirsher 2903cf2c1df6SMerav Sicron if (!netif_running(dev)) { 290497cd1ee6SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL, 290597cd1ee6SDmitry Kravkov "Can't perform self-test when interface is down\n"); 2906adfc5217SJeff Kirsher return; 2907cf2c1df6SMerav Sicron } 2908adfc5217SJeff Kirsher 2909adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2910a336ca7cSYaniv Rosner link_up = bp->link_vars.link_up; 2911cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2912cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2913adfc5217SJeff Kirsher int port = BP_PORT(bp); 2914adfc5217SJeff Kirsher u32 val; 2915adfc5217SJeff Kirsher 2916adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2917adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2918adfc5217SJeff Kirsher /* disable input for TX port IF */ 2919adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2920adfc5217SJeff Kirsher 29215d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2922cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2923cf2c1df6SMerav Sicron if (rc) { 2924cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2925cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2926cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2927cf2c1df6SMerav Sicron return; 2928cf2c1df6SMerav Sicron } 2929cf2c1df6SMerav Sicron 2930adfc5217SJeff Kirsher /* wait until link state is restored */ 2931adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2932adfc5217SJeff Kirsher 2933adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2934adfc5217SJeff Kirsher buf[0] = 1; 2935adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2936adfc5217SJeff Kirsher } 2937adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2938adfc5217SJeff Kirsher buf[1] = 1; 2939adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2940adfc5217SJeff Kirsher } 2941adfc5217SJeff Kirsher 29428970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2943adfc5217SJeff Kirsher if (buf[2] != 0) 2944adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2945adfc5217SJeff Kirsher 29468970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 29478970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 29488970b2e4SMerav Sicron if (buf[3] != 0) 29498970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 29508970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 29518970b2e4SMerav Sicron } 29528970b2e4SMerav Sicron 29535d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2954adfc5217SJeff Kirsher 2955adfc5217SJeff Kirsher /* restore input for TX port IF */ 2956adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2957cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2958cf2c1df6SMerav Sicron if (rc) { 2959cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2960cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2961cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 2962cf2c1df6SMerav Sicron return; 2963cf2c1df6SMerav Sicron } 2964adfc5217SJeff Kirsher /* wait until link state is restored */ 2965adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2966adfc5217SJeff Kirsher } 296797cd1ee6SDmitry Kravkov if (bnx2x_test_nvram(bp) != 0) { 296897cd1ee6SDmitry Kravkov if (!IS_MF(bp)) 296997cd1ee6SDmitry Kravkov buf[4] = 1; 297097cd1ee6SDmitry Kravkov else 297197cd1ee6SDmitry Kravkov buf[0] = 1; 297297cd1ee6SDmitry Kravkov etest->flags |= ETH_TEST_FL_FAILED; 297397cd1ee6SDmitry Kravkov } 2974adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2975cf2c1df6SMerav Sicron if (!IS_MF(bp)) 29768970b2e4SMerav Sicron buf[5] = 1; 2977cf2c1df6SMerav Sicron else 2978cf2c1df6SMerav Sicron buf[1] = 1; 2979adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2980adfc5217SJeff Kirsher } 2981adfc5217SJeff Kirsher 2982a336ca7cSYaniv Rosner if (link_up) { 2983a336ca7cSYaniv Rosner cnt = 100; 2984a336ca7cSYaniv Rosner while (bnx2x_link_test(bp, is_serdes) && --cnt) 2985a336ca7cSYaniv Rosner msleep(20); 2986a336ca7cSYaniv Rosner } 2987a336ca7cSYaniv Rosner 2988a336ca7cSYaniv Rosner if (!cnt) { 2989cf2c1df6SMerav Sicron if (!IS_MF(bp)) 29908970b2e4SMerav Sicron buf[6] = 1; 2991cf2c1df6SMerav Sicron else 2992cf2c1df6SMerav Sicron buf[2] = 1; 2993adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2994adfc5217SJeff Kirsher } 2995adfc5217SJeff Kirsher } 2996adfc5217SJeff Kirsher 2997adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 2998adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2999adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 3000adfc5217SJeff Kirsher #define IS_MF_MODE_STAT(bp) \ 3001adfc5217SJeff Kirsher (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 3002adfc5217SJeff Kirsher 3003adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 3004adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 3005adfc5217SJeff Kirsher */ 30061191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 3007adfc5217SJeff Kirsher { 3008adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 3009adfc5217SJeff Kirsher } 3010adfc5217SJeff Kirsher 3011adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3012adfc5217SJeff Kirsher { 3013adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 30143521b419SYuval Mintz int i, num_strings = 0; 3015adfc5217SJeff Kirsher 3016adfc5217SJeff Kirsher switch (stringset) { 3017adfc5217SJeff Kirsher case ETH_SS_STATS: 3018adfc5217SJeff Kirsher if (is_multi(bp)) { 30193521b419SYuval Mintz num_strings = bnx2x_num_stat_queues(bp) * 3020adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 3021d5e83632SYuval Mintz } else 30223521b419SYuval Mintz num_strings = 0; 3023d5e83632SYuval Mintz if (IS_MF_MODE_STAT(bp)) { 3024adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 3025adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 30263521b419SYuval Mintz num_strings++; 3027adfc5217SJeff Kirsher } else 30283521b419SYuval Mintz num_strings += BNX2X_NUM_STATS; 3029d5e83632SYuval Mintz 30303521b419SYuval Mintz return num_strings; 3031adfc5217SJeff Kirsher 3032adfc5217SJeff Kirsher case ETH_SS_TEST: 3033cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 3034adfc5217SJeff Kirsher 30353521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 30363521b419SYuval Mintz return BNX2X_PRI_FLAG_LEN; 30373521b419SYuval Mintz 3038adfc5217SJeff Kirsher default: 3039adfc5217SJeff Kirsher return -EINVAL; 3040adfc5217SJeff Kirsher } 3041adfc5217SJeff Kirsher } 3042adfc5217SJeff Kirsher 30433521b419SYuval Mintz static u32 bnx2x_get_private_flags(struct net_device *dev) 30443521b419SYuval Mintz { 30453521b419SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 30463521b419SYuval Mintz u32 flags = 0; 30473521b419SYuval Mintz 30483521b419SYuval Mintz flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 30493521b419SYuval Mintz flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 30503521b419SYuval Mintz flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 30513521b419SYuval Mintz 30523521b419SYuval Mintz return flags; 30533521b419SYuval Mintz } 30543521b419SYuval Mintz 3055adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3056adfc5217SJeff Kirsher { 3057adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 30585889335cSMerav Sicron int i, j, k, start; 3059adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 3060adfc5217SJeff Kirsher 3061adfc5217SJeff Kirsher switch (stringset) { 3062adfc5217SJeff Kirsher case ETH_SS_STATS: 3063adfc5217SJeff Kirsher k = 0; 3064d5e83632SYuval Mintz if (is_multi(bp)) { 3065adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 3066adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 3067adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 3068adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3069adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3070adfc5217SJeff Kirsher ETH_GSTRING_LEN, 3071adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 3072adfc5217SJeff Kirsher queue_name); 3073adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3074adfc5217SJeff Kirsher } 3075d5e83632SYuval Mintz } 3076d5e83632SYuval Mintz 3077adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3078adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 3079adfc5217SJeff Kirsher continue; 3080d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3081adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 3082adfc5217SJeff Kirsher j++; 3083adfc5217SJeff Kirsher } 3084d5e83632SYuval Mintz 3085adfc5217SJeff Kirsher break; 3086adfc5217SJeff Kirsher 3087adfc5217SJeff Kirsher case ETH_SS_TEST: 3088cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 3089cf2c1df6SMerav Sicron if (!IS_MF(bp)) 3090cf2c1df6SMerav Sicron start = 0; 3091cf2c1df6SMerav Sicron else 3092cf2c1df6SMerav Sicron start = 4; 30935889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 30945889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 30953521b419SYuval Mintz break; 30963521b419SYuval Mintz 30973521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 30983521b419SYuval Mintz memcpy(buf, bnx2x_private_arr, 30993521b419SYuval Mintz ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 31003521b419SYuval Mintz break; 3101adfc5217SJeff Kirsher } 3102adfc5217SJeff Kirsher } 3103adfc5217SJeff Kirsher 3104adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 3105adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 3106adfc5217SJeff Kirsher { 3107adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3108adfc5217SJeff Kirsher u32 *hw_stats, *offset; 3109d5e83632SYuval Mintz int i, j, k = 0; 3110adfc5217SJeff Kirsher 3111adfc5217SJeff Kirsher if (is_multi(bp)) { 3112adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 311315192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3114adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3115adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 3116adfc5217SJeff Kirsher /* skip this counter */ 3117adfc5217SJeff Kirsher buf[k + j] = 0; 3118adfc5217SJeff Kirsher continue; 3119adfc5217SJeff Kirsher } 3120adfc5217SJeff Kirsher offset = (hw_stats + 3121adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 3122adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 3123adfc5217SJeff Kirsher /* 4-byte counter */ 3124adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 3125adfc5217SJeff Kirsher continue; 3126adfc5217SJeff Kirsher } 3127adfc5217SJeff Kirsher /* 8-byte counter */ 3128adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3129adfc5217SJeff Kirsher } 3130adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3131adfc5217SJeff Kirsher } 3132adfc5217SJeff Kirsher } 3133d5e83632SYuval Mintz 3134adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 3135adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3136adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 3137adfc5217SJeff Kirsher continue; 3138adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 3139adfc5217SJeff Kirsher /* skip this counter */ 3140d5e83632SYuval Mintz buf[k + j] = 0; 3141adfc5217SJeff Kirsher j++; 3142adfc5217SJeff Kirsher continue; 3143adfc5217SJeff Kirsher } 3144adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 3145adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 3146adfc5217SJeff Kirsher /* 4-byte counter */ 3147d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 3148adfc5217SJeff Kirsher j++; 3149adfc5217SJeff Kirsher continue; 3150adfc5217SJeff Kirsher } 3151adfc5217SJeff Kirsher /* 8-byte counter */ 3152d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3153adfc5217SJeff Kirsher j++; 3154adfc5217SJeff Kirsher } 3155adfc5217SJeff Kirsher } 3156adfc5217SJeff Kirsher 3157adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 3158adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 3159adfc5217SJeff Kirsher { 3160adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3161adfc5217SJeff Kirsher 31623fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 316351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 316451c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 3165adfc5217SJeff Kirsher return -EAGAIN; 316651c1a580SMerav Sicron } 3167adfc5217SJeff Kirsher 3168adfc5217SJeff Kirsher switch (state) { 3169adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 3170adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 3171adfc5217SJeff Kirsher 3172adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 31738203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3174adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3175adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 31768203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3177adfc5217SJeff Kirsher break; 3178adfc5217SJeff Kirsher 3179adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 31808203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3181adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3182adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 31838203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3184adfc5217SJeff Kirsher break; 3185adfc5217SJeff Kirsher 3186adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 31878203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3188adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3189adfc5217SJeff Kirsher LED_MODE_OPER, 3190adfc5217SJeff Kirsher bp->link_vars.line_speed); 31918203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3192adfc5217SJeff Kirsher } 3193adfc5217SJeff Kirsher 3194adfc5217SJeff Kirsher return 0; 3195adfc5217SJeff Kirsher } 3196adfc5217SJeff Kirsher 31975d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 31985d317c6aSMerav Sicron { 31995d317c6aSMerav Sicron switch (info->flow_type) { 32005d317c6aSMerav Sicron case TCP_V4_FLOW: 32015d317c6aSMerav Sicron case TCP_V6_FLOW: 32025d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32035d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32045d317c6aSMerav Sicron break; 32055d317c6aSMerav Sicron case UDP_V4_FLOW: 32065d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 32075d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32085d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32095d317c6aSMerav Sicron else 32105d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32115d317c6aSMerav Sicron break; 32125d317c6aSMerav Sicron case UDP_V6_FLOW: 32135d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 32145d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32155d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32165d317c6aSMerav Sicron else 32175d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32185d317c6aSMerav Sicron break; 32195d317c6aSMerav Sicron case IPV4_FLOW: 32205d317c6aSMerav Sicron case IPV6_FLOW: 32215d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32225d317c6aSMerav Sicron break; 32235d317c6aSMerav Sicron default: 32245d317c6aSMerav Sicron info->data = 0; 32255d317c6aSMerav Sicron break; 32265d317c6aSMerav Sicron } 32275d317c6aSMerav Sicron 32285d317c6aSMerav Sicron return 0; 32295d317c6aSMerav Sicron } 32305d317c6aSMerav Sicron 3231adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3232815c7db5SBen Hutchings u32 *rules __always_unused) 3233adfc5217SJeff Kirsher { 3234adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3235adfc5217SJeff Kirsher 3236adfc5217SJeff Kirsher switch (info->cmd) { 3237adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 3238adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 3239adfc5217SJeff Kirsher return 0; 32405d317c6aSMerav Sicron case ETHTOOL_GRXFH: 32415d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 32425d317c6aSMerav Sicron default: 32435d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 32445d317c6aSMerav Sicron return -EOPNOTSUPP; 32455d317c6aSMerav Sicron } 32465d317c6aSMerav Sicron } 3247adfc5217SJeff Kirsher 32485d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 32495d317c6aSMerav Sicron { 32505d317c6aSMerav Sicron int udp_rss_requested; 32515d317c6aSMerav Sicron 32525d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32535d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 32545d317c6aSMerav Sicron info->flow_type, info->data); 32555d317c6aSMerav Sicron 32565d317c6aSMerav Sicron switch (info->flow_type) { 32575d317c6aSMerav Sicron case TCP_V4_FLOW: 32585d317c6aSMerav Sicron case TCP_V6_FLOW: 32595d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 32605d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 32615d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 32625d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32635d317c6aSMerav Sicron "Command parameters not supported\n"); 32645d317c6aSMerav Sicron return -EINVAL; 32655d317c6aSMerav Sicron } 32662de67439SYuval Mintz return 0; 32675d317c6aSMerav Sicron 32685d317c6aSMerav Sicron case UDP_V4_FLOW: 32695d317c6aSMerav Sicron case UDP_V6_FLOW: 32705d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 32715d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 32725d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 32735d317c6aSMerav Sicron udp_rss_requested = 1; 32745d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 32755d317c6aSMerav Sicron udp_rss_requested = 0; 32765d317c6aSMerav Sicron else 32775d317c6aSMerav Sicron return -EINVAL; 32785d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 32795d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 32805d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 32815d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32825d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 32835d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 32845d317c6aSMerav Sicron return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 32855d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 32865d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 32875d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 32885d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32895d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 32905d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 3291337da3e3SDan Carpenter return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 32925d317c6aSMerav Sicron } 3293924d75abSYuval Mintz return 0; 3294924d75abSYuval Mintz 32955d317c6aSMerav Sicron case IPV4_FLOW: 32965d317c6aSMerav Sicron case IPV6_FLOW: 32975d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 32985d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 32995d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33005d317c6aSMerav Sicron "Command parameters not supported\n"); 33015d317c6aSMerav Sicron return -EINVAL; 33025d317c6aSMerav Sicron } 3303924d75abSYuval Mintz return 0; 3304924d75abSYuval Mintz 33055d317c6aSMerav Sicron case SCTP_V4_FLOW: 33065d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 33075d317c6aSMerav Sicron case AH_V4_FLOW: 33085d317c6aSMerav Sicron case ESP_V4_FLOW: 33095d317c6aSMerav Sicron case SCTP_V6_FLOW: 33105d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 33115d317c6aSMerav Sicron case AH_V6_FLOW: 33125d317c6aSMerav Sicron case ESP_V6_FLOW: 33135d317c6aSMerav Sicron case IP_USER_FLOW: 33145d317c6aSMerav Sicron case ETHER_FLOW: 33155d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 33165d317c6aSMerav Sicron if (info->data) { 33175d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33185d317c6aSMerav Sicron "Command parameters not supported\n"); 33195d317c6aSMerav Sicron return -EINVAL; 33205d317c6aSMerav Sicron } 3321924d75abSYuval Mintz return 0; 3322924d75abSYuval Mintz 33235d317c6aSMerav Sicron default: 33245d317c6aSMerav Sicron return -EINVAL; 33255d317c6aSMerav Sicron } 33265d317c6aSMerav Sicron } 33275d317c6aSMerav Sicron 33285d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 33295d317c6aSMerav Sicron { 33305d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 33315d317c6aSMerav Sicron 33325d317c6aSMerav Sicron switch (info->cmd) { 33335d317c6aSMerav Sicron case ETHTOOL_SRXFH: 33345d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 3335adfc5217SJeff Kirsher default: 333651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3337adfc5217SJeff Kirsher return -EOPNOTSUPP; 3338adfc5217SJeff Kirsher } 3339adfc5217SJeff Kirsher } 3340adfc5217SJeff Kirsher 33417850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3342adfc5217SJeff Kirsher { 334396305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 33447850f63fSBen Hutchings } 33457850f63fSBen Hutchings 33467850f63fSBen Hutchings static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 33477850f63fSBen Hutchings { 33487850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 3349adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3350adfc5217SJeff Kirsher size_t i; 3351adfc5217SJeff Kirsher 3352adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 3353adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3354adfc5217SJeff Kirsher 3355adfc5217SJeff Kirsher /* 3356adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 3357adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 3358adfc5217SJeff Kirsher * points to an array of u32. 3359adfc5217SJeff Kirsher * 3360adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3361adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 3362adfc5217SJeff Kirsher * queue. 3363adfc5217SJeff Kirsher */ 33647850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 33657850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 3366adfc5217SJeff Kirsher 3367adfc5217SJeff Kirsher return 0; 3368adfc5217SJeff Kirsher } 3369adfc5217SJeff Kirsher 33707850f63fSBen Hutchings static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 3371adfc5217SJeff Kirsher { 3372adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3373adfc5217SJeff Kirsher size_t i; 3374adfc5217SJeff Kirsher 3375adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3376adfc5217SJeff Kirsher /* 3377adfc5217SJeff Kirsher * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 3378adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 3379adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 3380adfc5217SJeff Kirsher * 3381adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3382adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 3383adfc5217SJeff Kirsher * queue 3384adfc5217SJeff Kirsher */ 33855d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3386adfc5217SJeff Kirsher } 3387adfc5217SJeff Kirsher 33885d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 3389adfc5217SJeff Kirsher } 3390adfc5217SJeff Kirsher 33910e8d2ec5SMerav Sicron /** 33920e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 33930e8d2ec5SMerav Sicron * 33940e8d2ec5SMerav Sicron * @dev: net device 33950e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 33960e8d2ec5SMerav Sicron */ 33970e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 33980e8d2ec5SMerav Sicron struct ethtool_channels *channels) 33990e8d2ec5SMerav Sicron { 34000e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34010e8d2ec5SMerav Sicron 34020e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 34030e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 34040e8d2ec5SMerav Sicron } 34050e8d2ec5SMerav Sicron 34060e8d2ec5SMerav Sicron /** 34070e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 34080e8d2ec5SMerav Sicron * 34090e8d2ec5SMerav Sicron * @bp: bnx2x private structure 34100e8d2ec5SMerav Sicron * 34110e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 34120e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 34130e8d2ec5SMerav Sicron */ 34140e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 34150e8d2ec5SMerav Sicron { 34160e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 341755c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 341855c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 341955c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 34200e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 34210e8d2ec5SMerav Sicron } 34220e8d2ec5SMerav Sicron 34230e8d2ec5SMerav Sicron /** 34240e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 34250e8d2ec5SMerav Sicron * 34260e8d2ec5SMerav Sicron * @dev: net device 34270e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 34280e8d2ec5SMerav Sicron */ 34290e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 34300e8d2ec5SMerav Sicron struct ethtool_channels *channels) 34310e8d2ec5SMerav Sicron { 34320e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34330e8d2ec5SMerav Sicron 34340e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34350e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 34360e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 34370e8d2ec5SMerav Sicron channels->combined_count); 34380e8d2ec5SMerav Sicron 34390e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 34400e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 34410e8d2ec5SMerav Sicron */ 34420e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 34430e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 34440e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 34450e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 34460e8d2ec5SMerav Sicron return -EINVAL; 34470e8d2ec5SMerav Sicron } 34480e8d2ec5SMerav Sicron 34490e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 34500e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 34510e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 34520e8d2ec5SMerav Sicron return 0; 34530e8d2ec5SMerav Sicron } 34540e8d2ec5SMerav Sicron 34550e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 34560e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 34570e8d2ec5SMerav Sicron * less than requested if memory is low. 34580e8d2ec5SMerav Sicron */ 34590e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 34600e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 34610e8d2ec5SMerav Sicron return 0; 34620e8d2ec5SMerav Sicron } 34635d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 34640e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 34650e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 34660e8d2ec5SMerav Sicron } 34670e8d2ec5SMerav Sicron 3468adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 3469adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 3470adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 3471adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 3472adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 3473adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 347407ba6af4SMiriam Shitrit .get_dump_flag = bnx2x_get_dump_flag, 347507ba6af4SMiriam Shitrit .get_dump_data = bnx2x_get_dump_data, 347607ba6af4SMiriam Shitrit .set_dump = bnx2x_set_dump, 3477adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 3478adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 3479adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 3480adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 3481adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 3482adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 3483adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 3484adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 3485adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 3486adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 3487adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 3488adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 3489adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 3490adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 3491adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 3492adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 3493adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 34943521b419SYuval Mintz .get_priv_flags = bnx2x_get_private_flags, 3495adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 3496adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 3497adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 3498adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 34995d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 35007850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3501adfc5217SJeff Kirsher .get_rxfh_indir = bnx2x_get_rxfh_indir, 3502adfc5217SJeff Kirsher .set_rxfh_indir = bnx2x_set_rxfh_indir, 35030e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 35040e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 350524ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 350624ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3507e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3508e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3509be53ce1eSRichard Cochran .get_ts_info = ethtool_op_get_ts_info, 3510adfc5217SJeff Kirsher }; 3511adfc5217SJeff Kirsher 3512005a07baSAriel Elior static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3513005a07baSAriel Elior .get_settings = bnx2x_get_settings, 3514005a07baSAriel Elior .set_settings = bnx2x_set_settings, 3515005a07baSAriel Elior .get_drvinfo = bnx2x_get_drvinfo, 3516005a07baSAriel Elior .get_msglevel = bnx2x_get_msglevel, 3517005a07baSAriel Elior .set_msglevel = bnx2x_set_msglevel, 3518005a07baSAriel Elior .get_link = bnx2x_get_link, 3519005a07baSAriel Elior .get_coalesce = bnx2x_get_coalesce, 3520005a07baSAriel Elior .get_ringparam = bnx2x_get_ringparam, 3521005a07baSAriel Elior .set_ringparam = bnx2x_set_ringparam, 3522005a07baSAriel Elior .get_sset_count = bnx2x_get_sset_count, 3523005a07baSAriel Elior .get_strings = bnx2x_get_strings, 3524005a07baSAriel Elior .get_ethtool_stats = bnx2x_get_ethtool_stats, 3525005a07baSAriel Elior .get_rxnfc = bnx2x_get_rxnfc, 3526005a07baSAriel Elior .set_rxnfc = bnx2x_set_rxnfc, 3527005a07baSAriel Elior .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3528005a07baSAriel Elior .get_rxfh_indir = bnx2x_get_rxfh_indir, 3529005a07baSAriel Elior .set_rxfh_indir = bnx2x_set_rxfh_indir, 3530005a07baSAriel Elior .get_channels = bnx2x_get_channels, 3531005a07baSAriel Elior .set_channels = bnx2x_set_channels, 3532005a07baSAriel Elior }; 3533005a07baSAriel Elior 3534005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3535adfc5217SJeff Kirsher { 3536005a07baSAriel Elior if (IS_PF(bp)) 3537adfc5217SJeff Kirsher SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 3538005a07baSAriel Elior else /* vf */ 3539005a07baSAriel Elior SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops); 3540adfc5217SJeff Kirsher } 3541