14ad79e13SYuval Mintz /* bnx2x_ethtool.c: QLogic Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 44ad79e13SYuval Mintz * Copyright (c) 2014 QLogic Corporation 54ad79e13SYuval Mintz * All rights reserved 6adfc5217SJeff Kirsher * 7adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 8adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 9adfc5217SJeff Kirsher * the Free Software Foundation. 10adfc5217SJeff Kirsher * 1108f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12adfc5217SJeff Kirsher * Written by: Eliezer Tamir 13adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 14adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 15adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 16adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 17adfc5217SJeff Kirsher * 18adfc5217SJeff Kirsher */ 19f1deab50SJoe Perches 20f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21f1deab50SJoe Perches 22adfc5217SJeff Kirsher #include <linux/ethtool.h> 23adfc5217SJeff Kirsher #include <linux/netdevice.h> 24adfc5217SJeff Kirsher #include <linux/types.h> 25adfc5217SJeff Kirsher #include <linux/sched.h> 26adfc5217SJeff Kirsher #include <linux/crc32.h> 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_dump.h" 30adfc5217SJeff Kirsher #include "bnx2x_init.h" 31adfc5217SJeff Kirsher 32adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 33adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35adfc5217SJeff Kirsher */ 36adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 37adfc5217SJeff Kirsher static const struct { 38adfc5217SJeff Kirsher long offset; 39adfc5217SJeff Kirsher int size; 40adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 41adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 42adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 49adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 51adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 556a531198SYuval Mintz { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" }, 56adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 65adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 67c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 70adfc5217SJeff Kirsher }; 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73adfc5217SJeff Kirsher 74adfc5217SJeff Kirsher static const struct { 75adfc5217SJeff Kirsher long offset; 76adfc5217SJeff Kirsher int size; 7744c33c66SMichal Schmidt bool is_port_stat; 78adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 79adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 80adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 8144c33c66SMichal Schmidt 8, false, "rx_bytes" }, 82adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 8344c33c66SMichal Schmidt 8, false, "rx_error_bytes" }, 84adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 8544c33c66SMichal Schmidt 8, false, "rx_ucast_packets" }, 86adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 8744c33c66SMichal Schmidt 8, false, "rx_mcast_packets" }, 88adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 8944c33c66SMichal Schmidt 8, false, "rx_bcast_packets" }, 90adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 9144c33c66SMichal Schmidt 8, true, "rx_crc_errors" }, 92adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 9344c33c66SMichal Schmidt 8, true, "rx_align_errors" }, 94adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 9544c33c66SMichal Schmidt 8, true, "rx_undersize_packets" }, 96adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 9744c33c66SMichal Schmidt 8, true, "rx_oversize_packets" }, 98adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 9944c33c66SMichal Schmidt 8, true, "rx_fragments" }, 100adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 10144c33c66SMichal Schmidt 8, true, "rx_jabbers" }, 102adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 10344c33c66SMichal Schmidt 8, false, "rx_discards" }, 104adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 10544c33c66SMichal Schmidt 4, true, "rx_filtered_packets" }, 106adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 10744c33c66SMichal Schmidt 4, true, "rx_mf_tag_discard" }, 1080e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 10944c33c66SMichal Schmidt 8, true, "pfc_frames_received" }, 1100e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 11144c33c66SMichal Schmidt 8, true, "pfc_frames_sent" }, 112adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 11344c33c66SMichal Schmidt 8, true, "rx_brb_discard" }, 114adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 11544c33c66SMichal Schmidt 8, true, "rx_brb_truncate" }, 116adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 11744c33c66SMichal Schmidt 8, true, "rx_pause_frames" }, 118adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 11944c33c66SMichal Schmidt 8, true, "rx_mac_ctrl_frames" }, 120adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 12144c33c66SMichal Schmidt 4, true, "rx_constant_pause_events" }, 122adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 12344c33c66SMichal Schmidt 4, false, "rx_phy_ip_err_discards"}, 124adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 12544c33c66SMichal Schmidt 4, false, "rx_skb_alloc_discard" }, 126adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 12744c33c66SMichal Schmidt 4, false, "rx_csum_offload_errors" }, 1286a531198SYuval Mintz { STATS_OFFSET32(driver_xoff), 12944c33c66SMichal Schmidt 4, false, "tx_exhaustion_events" }, 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 13144c33c66SMichal Schmidt 8, false, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 13344c33c66SMichal Schmidt 8, true, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 13544c33c66SMichal Schmidt 8, false, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 13744c33c66SMichal Schmidt 8, false, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 13944c33c66SMichal Schmidt 8, false, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 14144c33c66SMichal Schmidt 8, true, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 14344c33c66SMichal Schmidt 8, true, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 14544c33c66SMichal Schmidt 8, true, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 14744c33c66SMichal Schmidt 8, true, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 14944c33c66SMichal Schmidt 8, true, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 15144c33c66SMichal Schmidt 8, true, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 15344c33c66SMichal Schmidt 8, true, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 15544c33c66SMichal Schmidt 8, true, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 15744c33c66SMichal Schmidt 8, true, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 15944c33c66SMichal Schmidt 8, true, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 16144c33c66SMichal Schmidt 8, true, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 16344c33c66SMichal Schmidt 8, true, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 16544c33c66SMichal Schmidt 8, true, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 16744c33c66SMichal Schmidt 8, true, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 16944c33c66SMichal Schmidt 8, true, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 17144c33c66SMichal Schmidt 8, true, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 17344c33c66SMichal Schmidt 8, false, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 17544c33c66SMichal Schmidt 8, false, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 17744c33c66SMichal Schmidt 8, false, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 17944c33c66SMichal Schmidt 4, false, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 18144c33c66SMichal Schmidt 4, false, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 18344c33c66SMichal Schmidt 4, false, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 18544c33c66SMichal Schmidt 4, true, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 18907ba6af4SMiriam Shitrit 190adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 191adfc5217SJeff Kirsher { 192adfc5217SJeff Kirsher int port_type; 193adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 195dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 196dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 198adfc5217SJeff Kirsher case ETH_PHY_KR: 199adfc5217SJeff Kirsher case ETH_PHY_CX4: 200adfc5217SJeff Kirsher port_type = PORT_FIBRE; 201adfc5217SJeff Kirsher break; 202adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 203adfc5217SJeff Kirsher port_type = PORT_DA; 204adfc5217SJeff Kirsher break; 205adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 206adfc5217SJeff Kirsher port_type = PORT_TP; 207adfc5217SJeff Kirsher break; 208adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 209adfc5217SJeff Kirsher port_type = PORT_NONE; 210adfc5217SJeff Kirsher break; 211adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 212adfc5217SJeff Kirsher default: 213adfc5217SJeff Kirsher port_type = PORT_OTHER; 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher return port_type; 217adfc5217SJeff Kirsher } 218adfc5217SJeff Kirsher 2196495d15aSDmitry Kravkov static int bnx2x_get_vf_settings(struct net_device *dev, 2206495d15aSDmitry Kravkov struct ethtool_cmd *cmd) 2216495d15aSDmitry Kravkov { 2226495d15aSDmitry Kravkov struct bnx2x *bp = netdev_priv(dev); 2236495d15aSDmitry Kravkov 2246495d15aSDmitry Kravkov if (bp->state == BNX2X_STATE_OPEN) { 2256495d15aSDmitry Kravkov if (test_bit(BNX2X_LINK_REPORT_FD, 2266495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags)) 2276495d15aSDmitry Kravkov cmd->duplex = DUPLEX_FULL; 2286495d15aSDmitry Kravkov else 2296495d15aSDmitry Kravkov cmd->duplex = DUPLEX_HALF; 2306495d15aSDmitry Kravkov 2316495d15aSDmitry Kravkov ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed); 2326495d15aSDmitry Kravkov } else { 2336495d15aSDmitry Kravkov cmd->duplex = DUPLEX_UNKNOWN; 2346495d15aSDmitry Kravkov ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 2356495d15aSDmitry Kravkov } 2366495d15aSDmitry Kravkov 2376495d15aSDmitry Kravkov cmd->port = PORT_OTHER; 2386495d15aSDmitry Kravkov cmd->phy_address = 0; 2396495d15aSDmitry Kravkov cmd->transceiver = XCVR_INTERNAL; 2406495d15aSDmitry Kravkov cmd->autoneg = AUTONEG_DISABLE; 2416495d15aSDmitry Kravkov cmd->maxtxpkt = 0; 2426495d15aSDmitry Kravkov cmd->maxrxpkt = 0; 2436495d15aSDmitry Kravkov 2446495d15aSDmitry Kravkov DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 2456495d15aSDmitry Kravkov " supported 0x%x advertising 0x%x speed %u\n" 2466495d15aSDmitry Kravkov " duplex %d port %d phy_address %d transceiver %d\n" 2476495d15aSDmitry Kravkov " autoneg %d maxtxpkt %d maxrxpkt %d\n", 2486495d15aSDmitry Kravkov cmd->cmd, cmd->supported, cmd->advertising, 2496495d15aSDmitry Kravkov ethtool_cmd_speed(cmd), 2506495d15aSDmitry Kravkov cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 2516495d15aSDmitry Kravkov cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 2526495d15aSDmitry Kravkov 2536495d15aSDmitry Kravkov return 0; 2546495d15aSDmitry Kravkov } 2556495d15aSDmitry Kravkov 256adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 257adfc5217SJeff Kirsher { 258adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 259adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2605d67c1c5SYuval Mintz u32 media_type; 261adfc5217SJeff Kirsher 262adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 263adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 264adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 265adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 266adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 2675d67c1c5SYuval Mintz media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 2685d67c1c5SYuval Mintz if (media_type == ETH_PHY_SFP_1G_FIBER) { 269dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 270dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 271dbef807eSYuval Mintz } 272adfc5217SJeff Kirsher 27359694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 27459694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 275adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 276adfc5217SJeff Kirsher 27738298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 278adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 27959694f00SYuval Mintz else 28059694f00SYuval Mintz ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 28138298461SYuval Mintz } else { 28238298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 28338298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 28438298461SYuval Mintz } 285adfc5217SJeff Kirsher 286adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 287adfc5217SJeff Kirsher 288adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 289adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 290adfc5217SJeff Kirsher 291adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 292adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 293adfc5217SJeff Kirsher else 294adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 295adfc5217SJeff Kirsher 2969e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2979e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2989e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2999e7e8399SMintz Yuval 3009e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 3019e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 3029e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 3039e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 3049e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 3059e7e8399SMintz Yuval 3069e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 3079e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 3089e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 3099e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 3109e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 3119e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 3129e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 3139e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 3149e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 3159e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 3165d67c1c5SYuval Mintz if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 3175d67c1c5SYuval Mintz if (media_type == ETH_PHY_KR) { 3185d67c1c5SYuval Mintz cmd->lp_advertising |= 3195d67c1c5SYuval Mintz ADVERTISED_1000baseKX_Full; 3205d67c1c5SYuval Mintz } else { 3215d67c1c5SYuval Mintz cmd->lp_advertising |= 3225d67c1c5SYuval Mintz ADVERTISED_1000baseT_Full; 3235d67c1c5SYuval Mintz } 3245d67c1c5SYuval Mintz } 3259e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 3269e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 3275d67c1c5SYuval Mintz if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 3285d67c1c5SYuval Mintz if (media_type == ETH_PHY_KR) { 3295d67c1c5SYuval Mintz cmd->lp_advertising |= 3305d67c1c5SYuval Mintz ADVERTISED_10000baseKR_Full; 3315d67c1c5SYuval Mintz } else { 3325d67c1c5SYuval Mintz cmd->lp_advertising |= 3335d67c1c5SYuval Mintz ADVERTISED_10000baseT_Full; 3345d67c1c5SYuval Mintz } 3355d67c1c5SYuval Mintz } 336be94bea7SYaniv Rosner if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 337be94bea7SYaniv Rosner cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 3389e7e8399SMintz Yuval } 3399e7e8399SMintz Yuval 340adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 341adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 342adfc5217SJeff Kirsher 34351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 344f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 345f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 346f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 347adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 348adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 349adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 350adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 351adfc5217SJeff Kirsher 352adfc5217SJeff Kirsher return 0; 353adfc5217SJeff Kirsher } 354adfc5217SJeff Kirsher 355adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 356adfc5217SJeff Kirsher { 357adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 358adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 359dbef807eSYuval Mintz u32 speed, phy_idx; 360adfc5217SJeff Kirsher 361adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 362adfc5217SJeff Kirsher return 0; 363adfc5217SJeff Kirsher 36451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 365adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 366adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 367adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 368adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 369adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 370adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 371adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 372adfc5217SJeff Kirsher 373adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 374adfc5217SJeff Kirsher 37516a5fd92SYuval Mintz /* If received a request for an unknown duplex, assume full*/ 37638298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 37738298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 37838298461SYuval Mintz 379adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 380adfc5217SJeff Kirsher u32 part; 381adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 382adfc5217SJeff Kirsher 383adfc5217SJeff Kirsher /* use 10G if no link detected */ 384adfc5217SJeff Kirsher if (!line_speed) 385adfc5217SJeff Kirsher line_speed = 10000; 386adfc5217SJeff Kirsher 387adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 38851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 38951c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 390adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 391adfc5217SJeff Kirsher return -EINVAL; 392adfc5217SJeff Kirsher } 393adfc5217SJeff Kirsher 394adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 395adfc5217SJeff Kirsher 396adfc5217SJeff Kirsher if (line_speed < speed || !part) { 39751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 39851c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 399adfc5217SJeff Kirsher return -EINVAL; 400adfc5217SJeff Kirsher } 401adfc5217SJeff Kirsher 402adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 403adfc5217SJeff Kirsher /* store value for following "load" */ 404adfc5217SJeff Kirsher bp->pending_max = part; 405adfc5217SJeff Kirsher else 406adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 407adfc5217SJeff Kirsher 408adfc5217SJeff Kirsher return 0; 409adfc5217SJeff Kirsher } 410adfc5217SJeff Kirsher 411adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 412adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 41333f9e6f5SYaniv Rosner if (cmd->port != bnx2x_get_port_type(bp)) { 414adfc5217SJeff Kirsher switch (cmd->port) { 415adfc5217SJeff Kirsher case PORT_TP: 416adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 417adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 41833f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 41933f9e6f5SYaniv Rosner "Unsupported port type\n"); 420adfc5217SJeff Kirsher return -EINVAL; 421adfc5217SJeff Kirsher } 422adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 423adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 424adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 425adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 426adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 427adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 428adfc5217SJeff Kirsher else 429adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 430adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 431adfc5217SJeff Kirsher break; 432adfc5217SJeff Kirsher case PORT_FIBRE: 433bfdb5823SYaniv Rosner case PORT_DA: 434042d7654SYaniv Rosner case PORT_NONE: 435adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 436adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 43733f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 43833f9e6f5SYaniv Rosner "Unsupported port type\n"); 439adfc5217SJeff Kirsher return -EINVAL; 440adfc5217SJeff Kirsher } 441adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 442adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 443adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 444adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 445adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 446adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 447adfc5217SJeff Kirsher else 448adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 449adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 450adfc5217SJeff Kirsher break; 451adfc5217SJeff Kirsher default: 45251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 453adfc5217SJeff Kirsher return -EINVAL; 454adfc5217SJeff Kirsher } 45533f9e6f5SYaniv Rosner } 4562de67439SYuval Mintz /* Save new config in case command complete successfully */ 457adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 458adfc5217SJeff Kirsher /* Get the new cfg_idx */ 459adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 460adfc5217SJeff Kirsher /* Restore old config in case command failed */ 461adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 46251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 463adfc5217SJeff Kirsher 464adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 46575318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 46675318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 46775318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 46875318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 46975318327SYaniv Rosner SUPPORTED_100baseT_Full); 470adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 47151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 472adfc5217SJeff Kirsher return -EINVAL; 473adfc5217SJeff Kirsher } 474adfc5217SJeff Kirsher 475adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 47675318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 47751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 47851c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4798decf868SDavid S. Miller return -EINVAL; 4808decf868SDavid S. Miller } 481adfc5217SJeff Kirsher 482adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4838decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4848decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 485adfc5217SJeff Kirsher cmd->advertising); 4868decf868SDavid S. Miller if (cmd->advertising) { 487adfc5217SJeff Kirsher 4888decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4898decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4908decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4918decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4928decf868SDavid S. Miller } 4938decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4948decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4958decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4968decf868SDavid S. Miller 4978decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4988decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4998decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 5008decf868SDavid S. Miller 5018decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 5028decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5038decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 5048decf868SDavid S. Miller } 5058decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 5068decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5078decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 5088decf868SDavid S. Miller } 5098decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 5108decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 5118decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5128decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 5138decf868SDavid S. Miller 5148decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 5158decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 5168decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 5178decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5188decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 519be94bea7SYaniv Rosner 520be94bea7SYaniv Rosner if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 521be94bea7SYaniv Rosner bp->link_params.speed_cap_mask[cfg_idx] |= 522be94bea7SYaniv Rosner PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 5238decf868SDavid S. Miller } 524adfc5217SJeff Kirsher } else { /* forced speed */ 525adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 526adfc5217SJeff Kirsher switch (speed) { 527adfc5217SJeff Kirsher case SPEED_10: 528adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 529adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 530adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 53151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 532adfc5217SJeff Kirsher "10M full not supported\n"); 533adfc5217SJeff Kirsher return -EINVAL; 534adfc5217SJeff Kirsher } 535adfc5217SJeff Kirsher 536adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 537adfc5217SJeff Kirsher ADVERTISED_TP); 538adfc5217SJeff Kirsher } else { 539adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 540adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 54151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 542adfc5217SJeff Kirsher "10M half not supported\n"); 543adfc5217SJeff Kirsher return -EINVAL; 544adfc5217SJeff Kirsher } 545adfc5217SJeff Kirsher 546adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 547adfc5217SJeff Kirsher ADVERTISED_TP); 548adfc5217SJeff Kirsher } 549adfc5217SJeff Kirsher break; 550adfc5217SJeff Kirsher 551adfc5217SJeff Kirsher case SPEED_100: 552adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 553adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 554adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 55551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 556adfc5217SJeff Kirsher "100M full not supported\n"); 557adfc5217SJeff Kirsher return -EINVAL; 558adfc5217SJeff Kirsher } 559adfc5217SJeff Kirsher 560adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 561adfc5217SJeff Kirsher ADVERTISED_TP); 562adfc5217SJeff Kirsher } else { 563adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 564adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 56551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 566adfc5217SJeff Kirsher "100M half not supported\n"); 567adfc5217SJeff Kirsher return -EINVAL; 568adfc5217SJeff Kirsher } 569adfc5217SJeff Kirsher 570adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 571adfc5217SJeff Kirsher ADVERTISED_TP); 572adfc5217SJeff Kirsher } 573adfc5217SJeff Kirsher break; 574adfc5217SJeff Kirsher 575adfc5217SJeff Kirsher case SPEED_1000: 576adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 57751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 57851c1a580SMerav Sicron "1G half not supported\n"); 579adfc5217SJeff Kirsher return -EINVAL; 580adfc5217SJeff Kirsher } 581adfc5217SJeff Kirsher 5825d67c1c5SYuval Mintz if (bp->port.supported[cfg_idx] & 5835d67c1c5SYuval Mintz SUPPORTED_1000baseT_Full) { 5845d67c1c5SYuval Mintz advertising = (ADVERTISED_1000baseT_Full | 5855d67c1c5SYuval Mintz ADVERTISED_TP); 5865d67c1c5SYuval Mintz 5875d67c1c5SYuval Mintz } else if (bp->port.supported[cfg_idx] & 5885d67c1c5SYuval Mintz SUPPORTED_1000baseKX_Full) { 5895d67c1c5SYuval Mintz advertising = ADVERTISED_1000baseKX_Full; 5905d67c1c5SYuval Mintz } else { 59151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 59251c1a580SMerav Sicron "1G full not supported\n"); 593adfc5217SJeff Kirsher return -EINVAL; 594adfc5217SJeff Kirsher } 595adfc5217SJeff Kirsher 596adfc5217SJeff Kirsher break; 597adfc5217SJeff Kirsher 598adfc5217SJeff Kirsher case SPEED_2500: 599adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 60051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 601adfc5217SJeff Kirsher "2.5G half not supported\n"); 602adfc5217SJeff Kirsher return -EINVAL; 603adfc5217SJeff Kirsher } 604adfc5217SJeff Kirsher 605adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 606adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 60751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 608adfc5217SJeff Kirsher "2.5G full not supported\n"); 609adfc5217SJeff Kirsher return -EINVAL; 610adfc5217SJeff Kirsher } 611adfc5217SJeff Kirsher 612adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 613adfc5217SJeff Kirsher ADVERTISED_TP); 614adfc5217SJeff Kirsher break; 615adfc5217SJeff Kirsher 616adfc5217SJeff Kirsher case SPEED_10000: 617adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 61851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 61951c1a580SMerav Sicron "10G half not supported\n"); 620adfc5217SJeff Kirsher return -EINVAL; 621adfc5217SJeff Kirsher } 622dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 6235d67c1c5SYuval Mintz if ((bp->port.supported[cfg_idx] & 6245d67c1c5SYuval Mintz SUPPORTED_10000baseT_Full) && 6255d67c1c5SYuval Mintz (bp->link_params.phy[phy_idx].media_type != 626dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 6275d67c1c5SYuval Mintz advertising = (ADVERTISED_10000baseT_Full | 6285d67c1c5SYuval Mintz ADVERTISED_FIBRE); 6295d67c1c5SYuval Mintz } else if (bp->port.supported[cfg_idx] & 6305d67c1c5SYuval Mintz SUPPORTED_10000baseKR_Full) { 6315d67c1c5SYuval Mintz advertising = (ADVERTISED_10000baseKR_Full | 6325d67c1c5SYuval Mintz ADVERTISED_FIBRE); 6335d67c1c5SYuval Mintz } else { 63451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 63551c1a580SMerav Sicron "10G full not supported\n"); 636adfc5217SJeff Kirsher return -EINVAL; 637adfc5217SJeff Kirsher } 638adfc5217SJeff Kirsher 639adfc5217SJeff Kirsher break; 640adfc5217SJeff Kirsher 641adfc5217SJeff Kirsher default: 64251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 643adfc5217SJeff Kirsher return -EINVAL; 644adfc5217SJeff Kirsher } 645adfc5217SJeff Kirsher 646adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 647adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 648adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 649adfc5217SJeff Kirsher } 650adfc5217SJeff Kirsher 65151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 652f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 653adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 654adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 655adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 656adfc5217SJeff Kirsher 657adfc5217SJeff Kirsher /* Set new config */ 658adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 659adfc5217SJeff Kirsher if (netif_running(dev)) { 660adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 661dc6a20aaSAriel Elior bnx2x_force_link_reset(bp); 662adfc5217SJeff Kirsher bnx2x_link_set(bp); 663adfc5217SJeff Kirsher } 664adfc5217SJeff Kirsher 665adfc5217SJeff Kirsher return 0; 666adfc5217SJeff Kirsher } 667adfc5217SJeff Kirsher 66807ba6af4SMiriam Shitrit #define DUMP_ALL_PRESETS 0x1FFF 66907ba6af4SMiriam Shitrit #define DUMP_MAX_PRESETS 13 670adfc5217SJeff Kirsher 67107ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 672adfc5217SJeff Kirsher { 673adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 67407ba6af4SMiriam Shitrit return dump_num_registers[0][preset-1]; 675adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 67607ba6af4SMiriam Shitrit return dump_num_registers[1][preset-1]; 677adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 67807ba6af4SMiriam Shitrit return dump_num_registers[2][preset-1]; 679adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 68007ba6af4SMiriam Shitrit return dump_num_registers[3][preset-1]; 681adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 68207ba6af4SMiriam Shitrit return dump_num_registers[4][preset-1]; 683adfc5217SJeff Kirsher else 68407ba6af4SMiriam Shitrit return 0; 685adfc5217SJeff Kirsher } 686adfc5217SJeff Kirsher 68707ba6af4SMiriam Shitrit static int __bnx2x_get_regs_len(struct bnx2x *bp) 68807ba6af4SMiriam Shitrit { 68907ba6af4SMiriam Shitrit u32 preset_idx; 69007ba6af4SMiriam Shitrit int regdump_len = 0; 69107ba6af4SMiriam Shitrit 69207ba6af4SMiriam Shitrit /* Calculate the total preset regs length */ 69307ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 69407ba6af4SMiriam Shitrit regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 69507ba6af4SMiriam Shitrit 69607ba6af4SMiriam Shitrit return regdump_len; 69707ba6af4SMiriam Shitrit } 69807ba6af4SMiriam Shitrit 69907ba6af4SMiriam Shitrit static int bnx2x_get_regs_len(struct net_device *dev) 70007ba6af4SMiriam Shitrit { 70107ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 70207ba6af4SMiriam Shitrit int regdump_len = 0; 70307ba6af4SMiriam Shitrit 70475543741SYuval Mintz if (IS_VF(bp)) 70575543741SYuval Mintz return 0; 70675543741SYuval Mintz 70707ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_regs_len(bp); 70807ba6af4SMiriam Shitrit regdump_len *= 4; 70907ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 71007ba6af4SMiriam Shitrit 71107ba6af4SMiriam Shitrit return regdump_len; 71207ba6af4SMiriam Shitrit } 71307ba6af4SMiriam Shitrit 71407ba6af4SMiriam Shitrit #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 71507ba6af4SMiriam Shitrit #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 71607ba6af4SMiriam Shitrit #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 71707ba6af4SMiriam Shitrit #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 71807ba6af4SMiriam Shitrit #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 71907ba6af4SMiriam Shitrit 72007ba6af4SMiriam Shitrit #define IS_REG_IN_PRESET(presets, idx) \ 72107ba6af4SMiriam Shitrit ((presets & (1 << (idx-1))) == (1 << (idx-1))) 72207ba6af4SMiriam Shitrit 723adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 7241191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 725adfc5217SJeff Kirsher { 726adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 727adfc5217SJeff Kirsher return page_vals_e2; 728adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 729adfc5217SJeff Kirsher return page_vals_e3; 730adfc5217SJeff Kirsher else 731adfc5217SJeff Kirsher return NULL; 732adfc5217SJeff Kirsher } 733adfc5217SJeff Kirsher 7341191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 735adfc5217SJeff Kirsher { 736adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 737adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 738adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 739adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 740adfc5217SJeff Kirsher else 741adfc5217SJeff Kirsher return 0; 742adfc5217SJeff Kirsher } 743adfc5217SJeff Kirsher 7441191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 745adfc5217SJeff Kirsher { 746adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 747adfc5217SJeff Kirsher return page_write_regs_e2; 748adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 749adfc5217SJeff Kirsher return page_write_regs_e3; 750adfc5217SJeff Kirsher else 751adfc5217SJeff Kirsher return NULL; 752adfc5217SJeff Kirsher } 753adfc5217SJeff Kirsher 7541191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 755adfc5217SJeff Kirsher { 756adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 757adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 758adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 759adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 760adfc5217SJeff Kirsher else 761adfc5217SJeff Kirsher return 0; 762adfc5217SJeff Kirsher } 763adfc5217SJeff Kirsher 7641191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 765adfc5217SJeff Kirsher { 766adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 767adfc5217SJeff Kirsher return page_read_regs_e2; 768adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 769adfc5217SJeff Kirsher return page_read_regs_e3; 770adfc5217SJeff Kirsher else 771adfc5217SJeff Kirsher return NULL; 772adfc5217SJeff Kirsher } 773adfc5217SJeff Kirsher 7741191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 775adfc5217SJeff Kirsher { 776adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 777adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 778adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 779adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 780adfc5217SJeff Kirsher else 781adfc5217SJeff Kirsher return 0; 782adfc5217SJeff Kirsher } 783adfc5217SJeff Kirsher 78407ba6af4SMiriam Shitrit static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 78507ba6af4SMiriam Shitrit const struct reg_addr *reg_info) 786adfc5217SJeff Kirsher { 78707ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 78807ba6af4SMiriam Shitrit return IS_E1_REG(reg_info->chips); 78907ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 79007ba6af4SMiriam Shitrit return IS_E1H_REG(reg_info->chips); 79107ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 79207ba6af4SMiriam Shitrit return IS_E2_REG(reg_info->chips); 79307ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 79407ba6af4SMiriam Shitrit return IS_E3A0_REG(reg_info->chips); 79507ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 79607ba6af4SMiriam Shitrit return IS_E3B0_REG(reg_info->chips); 79707ba6af4SMiriam Shitrit else 79807ba6af4SMiriam Shitrit return false; 799adfc5217SJeff Kirsher } 800adfc5217SJeff Kirsher 80107ba6af4SMiriam Shitrit static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 80207ba6af4SMiriam Shitrit const struct wreg_addr *wreg_info) 803adfc5217SJeff Kirsher { 80407ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 80507ba6af4SMiriam Shitrit return IS_E1_REG(wreg_info->chips); 80607ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 80707ba6af4SMiriam Shitrit return IS_E1H_REG(wreg_info->chips); 80807ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 80907ba6af4SMiriam Shitrit return IS_E2_REG(wreg_info->chips); 81007ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 81107ba6af4SMiriam Shitrit return IS_E3A0_REG(wreg_info->chips); 81207ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 81307ba6af4SMiriam Shitrit return IS_E3B0_REG(wreg_info->chips); 81407ba6af4SMiriam Shitrit else 81507ba6af4SMiriam Shitrit return false; 816adfc5217SJeff Kirsher } 817adfc5217SJeff Kirsher 818adfc5217SJeff Kirsher /** 819adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 820adfc5217SJeff Kirsher * 821adfc5217SJeff Kirsher * @bp device handle 822adfc5217SJeff Kirsher * @p output buffer 823adfc5217SJeff Kirsher * 8242de67439SYuval Mintz * Reads "paged" memories: memories that may only be read by first writing to a 8252de67439SYuval Mintz * specific address ("write address") and then reading from a specific address 8262de67439SYuval Mintz * ("read address"). There may be more than one write address per "page" and 8272de67439SYuval Mintz * more than one read address per write address. 828adfc5217SJeff Kirsher */ 82907ba6af4SMiriam Shitrit static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 830adfc5217SJeff Kirsher { 831adfc5217SJeff Kirsher u32 i, j, k, n; 83207ba6af4SMiriam Shitrit 833adfc5217SJeff Kirsher /* addresses of the paged registers */ 834adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 835adfc5217SJeff Kirsher /* number of paged registers */ 836adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 837adfc5217SJeff Kirsher /* write addresses */ 838adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 839adfc5217SJeff Kirsher /* number of write addresses */ 840adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 841adfc5217SJeff Kirsher /* read addresses info */ 842adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 843adfc5217SJeff Kirsher /* number of read addresses */ 844adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 84507ba6af4SMiriam Shitrit u32 addr, size; 846adfc5217SJeff Kirsher 847adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 848adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 849adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 85007ba6af4SMiriam Shitrit 85107ba6af4SMiriam Shitrit for (k = 0; k < read_num; k++) { 85207ba6af4SMiriam Shitrit if (IS_REG_IN_PRESET(read_addr[k].presets, 85307ba6af4SMiriam Shitrit preset)) { 85407ba6af4SMiriam Shitrit size = read_addr[k].size; 85507ba6af4SMiriam Shitrit for (n = 0; n < size; n++) { 85607ba6af4SMiriam Shitrit addr = read_addr[k].addr + n*4; 85707ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr); 858adfc5217SJeff Kirsher } 859adfc5217SJeff Kirsher } 860adfc5217SJeff Kirsher } 86107ba6af4SMiriam Shitrit } 86207ba6af4SMiriam Shitrit } 86307ba6af4SMiriam Shitrit } 86407ba6af4SMiriam Shitrit 86507ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 86607ba6af4SMiriam Shitrit { 86707ba6af4SMiriam Shitrit u32 i, j, addr; 86807ba6af4SMiriam Shitrit const struct wreg_addr *wreg_addr_p = NULL; 86907ba6af4SMiriam Shitrit 87007ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 87107ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1; 87207ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 87307ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1h; 87407ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 87507ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e2; 87607ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 87707ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3; 87807ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 87907ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3b0; 88007ba6af4SMiriam Shitrit 88107ba6af4SMiriam Shitrit /* Read the idle_chk registers */ 88207ba6af4SMiriam Shitrit for (i = 0; i < IDLE_REGS_COUNT; i++) { 88307ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 88407ba6af4SMiriam Shitrit IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 88507ba6af4SMiriam Shitrit for (j = 0; j < idle_reg_addrs[i].size; j++) 88607ba6af4SMiriam Shitrit *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 88707ba6af4SMiriam Shitrit } 88807ba6af4SMiriam Shitrit } 88907ba6af4SMiriam Shitrit 89007ba6af4SMiriam Shitrit /* Read the regular registers */ 89107ba6af4SMiriam Shitrit for (i = 0; i < REGS_COUNT; i++) { 89207ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 89307ba6af4SMiriam Shitrit IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 89407ba6af4SMiriam Shitrit for (j = 0; j < reg_addrs[i].size; j++) 89507ba6af4SMiriam Shitrit *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 89607ba6af4SMiriam Shitrit } 89707ba6af4SMiriam Shitrit } 89807ba6af4SMiriam Shitrit 89907ba6af4SMiriam Shitrit /* Read the CAM registers */ 90007ba6af4SMiriam Shitrit if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 90107ba6af4SMiriam Shitrit IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 90207ba6af4SMiriam Shitrit for (i = 0; i < wreg_addr_p->size; i++) { 90307ba6af4SMiriam Shitrit *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 90407ba6af4SMiriam Shitrit 90507ba6af4SMiriam Shitrit /* In case of wreg_addr register, read additional 90607ba6af4SMiriam Shitrit registers from read_regs array 90707ba6af4SMiriam Shitrit */ 90807ba6af4SMiriam Shitrit for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 90907ba6af4SMiriam Shitrit addr = *(wreg_addr_p->read_regs); 91007ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr + j*4); 91107ba6af4SMiriam Shitrit } 91207ba6af4SMiriam Shitrit } 91307ba6af4SMiriam Shitrit } 91407ba6af4SMiriam Shitrit 91507ba6af4SMiriam Shitrit /* Paged registers are supported in E2 & E3 only */ 91607ba6af4SMiriam Shitrit if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 91716a5fd92SYuval Mintz /* Read "paged" registers */ 91807ba6af4SMiriam Shitrit bnx2x_read_pages_regs(bp, p, preset); 91907ba6af4SMiriam Shitrit } 92007ba6af4SMiriam Shitrit 92107ba6af4SMiriam Shitrit return 0; 92207ba6af4SMiriam Shitrit } 923adfc5217SJeff Kirsher 9241191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 925adfc5217SJeff Kirsher { 92607ba6af4SMiriam Shitrit u32 preset_idx; 927adfc5217SJeff Kirsher 92807ba6af4SMiriam Shitrit /* Read all registers, by reading all preset registers */ 92907ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 93007ba6af4SMiriam Shitrit /* Skip presets with IOR */ 93107ba6af4SMiriam Shitrit if ((preset_idx == 2) || 93207ba6af4SMiriam Shitrit (preset_idx == 5) || 93307ba6af4SMiriam Shitrit (preset_idx == 8) || 93407ba6af4SMiriam Shitrit (preset_idx == 11)) 93507ba6af4SMiriam Shitrit continue; 93607ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, preset_idx); 93707ba6af4SMiriam Shitrit p += __bnx2x_get_preset_regs_len(bp, preset_idx); 93807ba6af4SMiriam Shitrit } 939adfc5217SJeff Kirsher } 940adfc5217SJeff Kirsher 941adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 942adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 943adfc5217SJeff Kirsher { 944adfc5217SJeff Kirsher u32 *p = _p; 945adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 94607ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 947adfc5217SJeff Kirsher 94807ba6af4SMiriam Shitrit regs->version = 2; 949adfc5217SJeff Kirsher memset(p, 0, regs->len); 950adfc5217SJeff Kirsher 951adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 952adfc5217SJeff Kirsher return; 953adfc5217SJeff Kirsher 954adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 955adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 956adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 957adfc5217SJeff Kirsher */ 95807ba6af4SMiriam Shitrit 959adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 960adfc5217SJeff Kirsher 96107ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 96207ba6af4SMiriam Shitrit dump_hdr.preset = DUMP_ALL_PRESETS; 96307ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 96407ba6af4SMiriam Shitrit 96507ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 96607ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 96707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 96807ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 96907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 97007ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 97107ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 97207ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 97307ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 97407ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 97507ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 97607ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 97707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 97807ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 97907ba6af4SMiriam Shitrit } 98007ba6af4SMiriam Shitrit 98107ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 98207ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 983adfc5217SJeff Kirsher 984e56270f6SYuval Mintz /* This isn't really an error, but since attention handling is going 985e56270f6SYuval Mintz * to print the GRC timeouts using this macro, we use the same. 986e56270f6SYuval Mintz */ 987e56270f6SYuval Mintz BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n"); 988e56270f6SYuval Mintz 989adfc5217SJeff Kirsher /* Actually read the registers */ 990adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 991adfc5217SJeff Kirsher 9924293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 993adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 994adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 99507ba6af4SMiriam Shitrit } 99607ba6af4SMiriam Shitrit 99707ba6af4SMiriam Shitrit static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 99807ba6af4SMiriam Shitrit { 99907ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 100007ba6af4SMiriam Shitrit int regdump_len = 0; 100107ba6af4SMiriam Shitrit 100207ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 100307ba6af4SMiriam Shitrit regdump_len *= 4; 100407ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 100507ba6af4SMiriam Shitrit 100607ba6af4SMiriam Shitrit return regdump_len; 100707ba6af4SMiriam Shitrit } 100807ba6af4SMiriam Shitrit 100907ba6af4SMiriam Shitrit static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 101007ba6af4SMiriam Shitrit { 101107ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 101207ba6af4SMiriam Shitrit 101307ba6af4SMiriam Shitrit /* Use the ethtool_dump "flag" field as the dump preset index */ 10145bb680d6SMichal Schmidt if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 10155bb680d6SMichal Schmidt return -EINVAL; 10165bb680d6SMichal Schmidt 101707ba6af4SMiriam Shitrit bp->dump_preset_idx = val->flag; 101807ba6af4SMiriam Shitrit return 0; 101907ba6af4SMiriam Shitrit } 102007ba6af4SMiriam Shitrit 102107ba6af4SMiriam Shitrit static int bnx2x_get_dump_flag(struct net_device *dev, 102207ba6af4SMiriam Shitrit struct ethtool_dump *dump) 102307ba6af4SMiriam Shitrit { 102407ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 102507ba6af4SMiriam Shitrit 10268cc2d927SMichal Schmidt dump->version = BNX2X_DUMP_VERSION; 10278cc2d927SMichal Schmidt dump->flag = bp->dump_preset_idx; 102807ba6af4SMiriam Shitrit /* Calculate the requested preset idx length */ 102907ba6af4SMiriam Shitrit dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 103007ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 103107ba6af4SMiriam Shitrit bp->dump_preset_idx, dump->len); 103207ba6af4SMiriam Shitrit return 0; 103307ba6af4SMiriam Shitrit } 103407ba6af4SMiriam Shitrit 103507ba6af4SMiriam Shitrit static int bnx2x_get_dump_data(struct net_device *dev, 103607ba6af4SMiriam Shitrit struct ethtool_dump *dump, 103707ba6af4SMiriam Shitrit void *buffer) 103807ba6af4SMiriam Shitrit { 103907ba6af4SMiriam Shitrit u32 *p = buffer; 104007ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 104107ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 104207ba6af4SMiriam Shitrit 104307ba6af4SMiriam Shitrit /* Disable parity attentions as long as following dump may 104407ba6af4SMiriam Shitrit * cause false alarms by reading never written registers. We 104507ba6af4SMiriam Shitrit * will re-enable parity attentions right after the dump. 104607ba6af4SMiriam Shitrit */ 104707ba6af4SMiriam Shitrit 104807ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 104907ba6af4SMiriam Shitrit 105007ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 105107ba6af4SMiriam Shitrit dump_hdr.preset = bp->dump_preset_idx; 105207ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 105307ba6af4SMiriam Shitrit 105407ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 105507ba6af4SMiriam Shitrit 105607ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 105707ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 105807ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 105907ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 106007ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 106107ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 106207ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 106307ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 106407ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 106507ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 106607ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 106707ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 106807ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 106907ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 107007ba6af4SMiriam Shitrit } 107107ba6af4SMiriam Shitrit 107207ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 107307ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 107407ba6af4SMiriam Shitrit 107507ba6af4SMiriam Shitrit /* Actually read the registers */ 107607ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 107707ba6af4SMiriam Shitrit 10784293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 107907ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 108007ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 108107ba6af4SMiriam Shitrit 108207ba6af4SMiriam Shitrit return 0; 1083adfc5217SJeff Kirsher } 1084adfc5217SJeff Kirsher 1085adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 1086adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 1087adfc5217SJeff Kirsher { 1088adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1089adfc5217SJeff Kirsher 109068aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 109168aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1092adfc5217SJeff Kirsher 10938ca5e17eSAriel Elior bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 10948ca5e17eSAriel Elior 109568aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1096adfc5217SJeff Kirsher } 1097adfc5217SJeff Kirsher 1098adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1099adfc5217SJeff Kirsher { 1100adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 1103adfc5217SJeff Kirsher wol->supported = 0; 1104adfc5217SJeff Kirsher wol->wolopts = 0; 1105adfc5217SJeff Kirsher } else { 1106adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 1107adfc5217SJeff Kirsher if (bp->wol) 1108adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 1109adfc5217SJeff Kirsher else 1110adfc5217SJeff Kirsher wol->wolopts = 0; 1111adfc5217SJeff Kirsher } 1112adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 1113adfc5217SJeff Kirsher } 1114adfc5217SJeff Kirsher 1115adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1116adfc5217SJeff Kirsher { 1117adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1118adfc5217SJeff Kirsher 111951c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 11202de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1121adfc5217SJeff Kirsher return -EINVAL; 112251c1a580SMerav Sicron } 1123adfc5217SJeff Kirsher 1124adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 112551c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 11262de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1127adfc5217SJeff Kirsher return -EINVAL; 112851c1a580SMerav Sicron } 1129adfc5217SJeff Kirsher bp->wol = 1; 1130adfc5217SJeff Kirsher } else 1131adfc5217SJeff Kirsher bp->wol = 0; 1132adfc5217SJeff Kirsher 1133230d00ebSYuval Mintz if (SHMEM2_HAS(bp, curr_cfg)) 1134230d00ebSYuval Mintz SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1135230d00ebSYuval Mintz 1136adfc5217SJeff Kirsher return 0; 1137adfc5217SJeff Kirsher } 1138adfc5217SJeff Kirsher 1139adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 1140adfc5217SJeff Kirsher { 1141adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher return bp->msg_enable; 1144adfc5217SJeff Kirsher } 1145adfc5217SJeff Kirsher 1146adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1147adfc5217SJeff Kirsher { 1148adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1149adfc5217SJeff Kirsher 1150adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 1151adfc5217SJeff Kirsher /* dump MCP trace */ 1152ad5afc89SAriel Elior if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1153adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 1154adfc5217SJeff Kirsher bp->msg_enable = level; 1155adfc5217SJeff Kirsher } 1156adfc5217SJeff Kirsher } 1157adfc5217SJeff Kirsher 1158adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 1159adfc5217SJeff Kirsher { 1160adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1161adfc5217SJeff Kirsher 1162adfc5217SJeff Kirsher if (!bp->port.pmf) 1163adfc5217SJeff Kirsher return 0; 1164adfc5217SJeff Kirsher 1165adfc5217SJeff Kirsher if (netif_running(dev)) { 1166adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11675d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1168adfc5217SJeff Kirsher bnx2x_link_set(bp); 1169adfc5217SJeff Kirsher } 1170adfc5217SJeff Kirsher 1171adfc5217SJeff Kirsher return 0; 1172adfc5217SJeff Kirsher } 1173adfc5217SJeff Kirsher 1174adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 1175adfc5217SJeff Kirsher { 1176adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1177adfc5217SJeff Kirsher 1178adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1179adfc5217SJeff Kirsher return 0; 1180adfc5217SJeff Kirsher 11816495d15aSDmitry Kravkov if (IS_VF(bp)) 11826495d15aSDmitry Kravkov return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 11836495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags); 11846495d15aSDmitry Kravkov 1185adfc5217SJeff Kirsher return bp->link_vars.link_up; 1186adfc5217SJeff Kirsher } 1187adfc5217SJeff Kirsher 1188adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 1189adfc5217SJeff Kirsher { 1190adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1191adfc5217SJeff Kirsher 1192adfc5217SJeff Kirsher return bp->common.flash_size; 1193adfc5217SJeff Kirsher } 1194adfc5217SJeff Kirsher 119516a5fd92SYuval Mintz /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 119616a5fd92SYuval Mintz * had we done things the other way around, if two pfs from the same port would 1197f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 1198f16da43bSAriel Elior * as: 1199f16da43bSAriel Elior * pf A takes the port lock. 1200f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 1201f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 1202f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 1203f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 1204f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 1205f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 12062de67439SYuval Mintz * access corrupted by pf B) 1207f16da43bSAriel Elior */ 1208adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1209adfc5217SJeff Kirsher { 1210adfc5217SJeff Kirsher int port = BP_PORT(bp); 1211adfc5217SJeff Kirsher int count, i; 1212f16da43bSAriel Elior u32 val; 1213f16da43bSAriel Elior 1214f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1215f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1216adfc5217SJeff Kirsher 1217adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1218adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1219adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1220adfc5217SJeff Kirsher count *= 100; 1221adfc5217SJeff Kirsher 1222adfc5217SJeff Kirsher /* request access to nvram interface */ 1223adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1224adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1225adfc5217SJeff Kirsher 1226adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1227adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1228adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1229adfc5217SJeff Kirsher break; 1230adfc5217SJeff Kirsher 1231adfc5217SJeff Kirsher udelay(5); 1232adfc5217SJeff Kirsher } 1233adfc5217SJeff Kirsher 1234adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 123551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 123651c1a580SMerav Sicron "cannot get access to nvram interface\n"); 1237efd38b8fSYuval Mintz bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1238adfc5217SJeff Kirsher return -EBUSY; 1239adfc5217SJeff Kirsher } 1240adfc5217SJeff Kirsher 1241adfc5217SJeff Kirsher return 0; 1242adfc5217SJeff Kirsher } 1243adfc5217SJeff Kirsher 1244adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1245adfc5217SJeff Kirsher { 1246adfc5217SJeff Kirsher int port = BP_PORT(bp); 1247adfc5217SJeff Kirsher int count, i; 1248f16da43bSAriel Elior u32 val; 1249adfc5217SJeff Kirsher 1250adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1251adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1252adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1253adfc5217SJeff Kirsher count *= 100; 1254adfc5217SJeff Kirsher 1255adfc5217SJeff Kirsher /* relinquish nvram interface */ 1256adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1257adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1258adfc5217SJeff Kirsher 1259adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1260adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1261adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1262adfc5217SJeff Kirsher break; 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher udelay(5); 1265adfc5217SJeff Kirsher } 1266adfc5217SJeff Kirsher 1267adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 126851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 126951c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1270adfc5217SJeff Kirsher return -EBUSY; 1271adfc5217SJeff Kirsher } 1272adfc5217SJeff Kirsher 1273f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1274f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1275adfc5217SJeff Kirsher return 0; 1276adfc5217SJeff Kirsher } 1277adfc5217SJeff Kirsher 1278adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1279adfc5217SJeff Kirsher { 1280adfc5217SJeff Kirsher u32 val; 1281adfc5217SJeff Kirsher 1282adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1283adfc5217SJeff Kirsher 1284adfc5217SJeff Kirsher /* enable both bits, even on read */ 1285adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1286adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1287adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1288adfc5217SJeff Kirsher } 1289adfc5217SJeff Kirsher 1290adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1291adfc5217SJeff Kirsher { 1292adfc5217SJeff Kirsher u32 val; 1293adfc5217SJeff Kirsher 1294adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1295adfc5217SJeff Kirsher 1296adfc5217SJeff Kirsher /* disable both bits, even after read */ 1297adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1298adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1299adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1300adfc5217SJeff Kirsher } 1301adfc5217SJeff Kirsher 1302adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1303adfc5217SJeff Kirsher u32 cmd_flags) 1304adfc5217SJeff Kirsher { 1305adfc5217SJeff Kirsher int count, i, rc; 1306adfc5217SJeff Kirsher u32 val; 1307adfc5217SJeff Kirsher 1308adfc5217SJeff Kirsher /* build the command word */ 1309adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1310adfc5217SJeff Kirsher 1311adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1312adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1313adfc5217SJeff Kirsher 1314adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1315adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1316adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1317adfc5217SJeff Kirsher 1318adfc5217SJeff Kirsher /* issue a read command */ 1319adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1320adfc5217SJeff Kirsher 1321adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1322adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1323adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1324adfc5217SJeff Kirsher count *= 100; 1325adfc5217SJeff Kirsher 1326adfc5217SJeff Kirsher /* wait for completion */ 1327adfc5217SJeff Kirsher *ret_val = 0; 1328adfc5217SJeff Kirsher rc = -EBUSY; 1329adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1330adfc5217SJeff Kirsher udelay(5); 1331adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1332adfc5217SJeff Kirsher 1333adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1334adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1335adfc5217SJeff Kirsher /* we read nvram data in cpu order 1336adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 133707ba6af4SMiriam Shitrit * converting to big-endian will do the work 133807ba6af4SMiriam Shitrit */ 1339adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1340adfc5217SJeff Kirsher rc = 0; 1341adfc5217SJeff Kirsher break; 1342adfc5217SJeff Kirsher } 1343adfc5217SJeff Kirsher } 134451c1a580SMerav Sicron if (rc == -EBUSY) 134551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 134651c1a580SMerav Sicron "nvram read timeout expired\n"); 1347adfc5217SJeff Kirsher return rc; 1348adfc5217SJeff Kirsher } 1349adfc5217SJeff Kirsher 135097ac4ef7SYuval Mintz int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1351adfc5217SJeff Kirsher int buf_size) 1352adfc5217SJeff Kirsher { 1353adfc5217SJeff Kirsher int rc; 1354adfc5217SJeff Kirsher u32 cmd_flags; 1355adfc5217SJeff Kirsher __be32 val; 1356adfc5217SJeff Kirsher 1357adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 135851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1359adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1360adfc5217SJeff Kirsher offset, buf_size); 1361adfc5217SJeff Kirsher return -EINVAL; 1362adfc5217SJeff Kirsher } 1363adfc5217SJeff Kirsher 1364adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 136551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 136651c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1367adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1368adfc5217SJeff Kirsher return -EINVAL; 1369adfc5217SJeff Kirsher } 1370adfc5217SJeff Kirsher 1371adfc5217SJeff Kirsher /* request access to nvram interface */ 1372adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1373adfc5217SJeff Kirsher if (rc) 1374adfc5217SJeff Kirsher return rc; 1375adfc5217SJeff Kirsher 1376adfc5217SJeff Kirsher /* enable access to nvram interface */ 1377adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1378adfc5217SJeff Kirsher 1379adfc5217SJeff Kirsher /* read the first word(s) */ 1380adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1381adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1382adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1383adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1384adfc5217SJeff Kirsher 1385adfc5217SJeff Kirsher /* advance to the next dword */ 1386adfc5217SJeff Kirsher offset += sizeof(u32); 1387adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1388adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1389adfc5217SJeff Kirsher cmd_flags = 0; 1390adfc5217SJeff Kirsher } 1391adfc5217SJeff Kirsher 1392adfc5217SJeff Kirsher if (rc == 0) { 1393adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1394adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1395adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1396adfc5217SJeff Kirsher } 1397adfc5217SJeff Kirsher 1398adfc5217SJeff Kirsher /* disable access to nvram interface */ 1399adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1400adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1401adfc5217SJeff Kirsher 1402adfc5217SJeff Kirsher return rc; 1403adfc5217SJeff Kirsher } 1404adfc5217SJeff Kirsher 140585640952SDmitry Kravkov static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 140685640952SDmitry Kravkov int buf_size) 140785640952SDmitry Kravkov { 140885640952SDmitry Kravkov int rc; 140985640952SDmitry Kravkov 141085640952SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 141185640952SDmitry Kravkov 141285640952SDmitry Kravkov if (!rc) { 141385640952SDmitry Kravkov __be32 *be = (__be32 *)buf; 141485640952SDmitry Kravkov 141585640952SDmitry Kravkov while ((buf_size -= 4) >= 0) 141685640952SDmitry Kravkov *buf++ = be32_to_cpu(*be++); 141785640952SDmitry Kravkov } 141885640952SDmitry Kravkov 141985640952SDmitry Kravkov return rc; 142085640952SDmitry Kravkov } 142185640952SDmitry Kravkov 14223fb43eb2SYuval Mintz static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 14233fb43eb2SYuval Mintz { 14243fb43eb2SYuval Mintz int rc = 1; 14253fb43eb2SYuval Mintz u16 pm = 0; 14263fb43eb2SYuval Mintz struct net_device *dev = pci_get_drvdata(bp->pdev); 14273fb43eb2SYuval Mintz 142829ed74c3SJon Mason if (bp->pdev->pm_cap) 14293fb43eb2SYuval Mintz rc = pci_read_config_word(bp->pdev, 143029ed74c3SJon Mason bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 14313fb43eb2SYuval Mintz 1432829a5071SYuval Mintz if ((rc && !netif_running(dev)) || 1433c957d09fSYuval Mintz (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 14343fb43eb2SYuval Mintz return false; 14353fb43eb2SYuval Mintz 14363fb43eb2SYuval Mintz return true; 14373fb43eb2SYuval Mintz } 14383fb43eb2SYuval Mintz 1439adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1440adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1441adfc5217SJeff Kirsher { 1442adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1443adfc5217SJeff Kirsher 14443fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 144551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 144651c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1447adfc5217SJeff Kirsher return -EAGAIN; 144851c1a580SMerav Sicron } 1449adfc5217SJeff Kirsher 145051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1451f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1452adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1453adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1454adfc5217SJeff Kirsher 1455adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1456adfc5217SJeff Kirsher 1457f1691dc6SDmitry Kravkov return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1458adfc5217SJeff Kirsher } 1459adfc5217SJeff Kirsher 146024ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 146124ea818eSYuval Mintz struct ethtool_eeprom *ee, 146224ea818eSYuval Mintz u8 *data) 146324ea818eSYuval Mintz { 146424ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1465669d6996SYaniv Rosner int rc = -EINVAL, phy_idx; 146624ea818eSYuval Mintz u8 *user_data = data; 1467669d6996SYaniv Rosner unsigned int start_addr = ee->offset, xfer_size = 0; 146824ea818eSYuval Mintz 14693fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 147024ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 147124ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 147224ea818eSYuval Mintz return -EAGAIN; 147324ea818eSYuval Mintz } 147424ea818eSYuval Mintz 147524ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1476669d6996SYaniv Rosner 1477669d6996SYaniv Rosner /* Read A0 section */ 1478669d6996SYaniv Rosner if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1479669d6996SYaniv Rosner /* Limit transfer size to the A0 section boundary */ 1480669d6996SYaniv Rosner if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1481669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1482669d6996SYaniv Rosner else 1483669d6996SYaniv Rosner xfer_size = ee->len; 148424ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 148524ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 148624ea818eSYuval Mintz &bp->link_params, 1487669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1488669d6996SYaniv Rosner start_addr, 148924ea818eSYuval Mintz xfer_size, 149024ea818eSYuval Mintz user_data); 1491669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1492669d6996SYaniv Rosner if (rc) { 1493669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1494669d6996SYaniv Rosner 1495669d6996SYaniv Rosner return -EINVAL; 1496669d6996SYaniv Rosner } 149724ea818eSYuval Mintz user_data += xfer_size; 1498669d6996SYaniv Rosner start_addr += xfer_size; 149924ea818eSYuval Mintz } 150024ea818eSYuval Mintz 1501669d6996SYaniv Rosner /* Read A2 section */ 1502669d6996SYaniv Rosner if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1503669d6996SYaniv Rosner (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1504669d6996SYaniv Rosner xfer_size = ee->len - xfer_size; 1505669d6996SYaniv Rosner /* Limit transfer size to the A2 section boundary */ 1506669d6996SYaniv Rosner if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1507669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1508669d6996SYaniv Rosner start_addr -= ETH_MODULE_SFF_8079_LEN; 1509669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1510669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1511669d6996SYaniv Rosner &bp->link_params, 1512669d6996SYaniv Rosner I2C_DEV_ADDR_A2, 1513669d6996SYaniv Rosner start_addr, 1514669d6996SYaniv Rosner xfer_size, 1515669d6996SYaniv Rosner user_data); 151624ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 1517669d6996SYaniv Rosner if (rc) { 1518669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1519669d6996SYaniv Rosner return -EINVAL; 1520669d6996SYaniv Rosner } 1521669d6996SYaniv Rosner } 152224ea818eSYuval Mintz return rc; 152324ea818eSYuval Mintz } 152424ea818eSYuval Mintz 152524ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 152624ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 152724ea818eSYuval Mintz { 152824ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1529669d6996SYaniv Rosner int phy_idx, rc; 1530669d6996SYaniv Rosner u8 sff8472_comp, diag_type; 1531669d6996SYaniv Rosner 15323fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 153324ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 153424ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 153524ea818eSYuval Mintz return -EAGAIN; 153624ea818eSYuval Mintz } 153724ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1538669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1539669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1540669d6996SYaniv Rosner &bp->link_params, 1541669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1542669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_ADDR, 1543669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_SIZE, 1544669d6996SYaniv Rosner &sff8472_comp); 1545669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1546669d6996SYaniv Rosner if (rc) { 1547669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1548669d6996SYaniv Rosner return -EINVAL; 1549669d6996SYaniv Rosner } 1550669d6996SYaniv Rosner 1551669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1552669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1553669d6996SYaniv Rosner &bp->link_params, 1554669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1555669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_ADDR, 1556669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_SIZE, 1557669d6996SYaniv Rosner &diag_type); 1558669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1559669d6996SYaniv Rosner if (rc) { 1560669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1561669d6996SYaniv Rosner return -EINVAL; 1562669d6996SYaniv Rosner } 1563669d6996SYaniv Rosner 1564669d6996SYaniv Rosner if (!sff8472_comp || 1565669d6996SYaniv Rosner (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 156624ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 156724ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1568669d6996SYaniv Rosner } else { 1569669d6996SYaniv Rosner modinfo->type = ETH_MODULE_SFF_8472; 1570669d6996SYaniv Rosner modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 157124ea818eSYuval Mintz } 1572669d6996SYaniv Rosner return 0; 157324ea818eSYuval Mintz } 157424ea818eSYuval Mintz 1575adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1576adfc5217SJeff Kirsher u32 cmd_flags) 1577adfc5217SJeff Kirsher { 1578adfc5217SJeff Kirsher int count, i, rc; 1579adfc5217SJeff Kirsher 1580adfc5217SJeff Kirsher /* build the command word */ 1581adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1582adfc5217SJeff Kirsher 1583adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1584adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1585adfc5217SJeff Kirsher 1586adfc5217SJeff Kirsher /* write the data */ 1587adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1588adfc5217SJeff Kirsher 1589adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1590adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1591adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1592adfc5217SJeff Kirsher 1593adfc5217SJeff Kirsher /* issue the write command */ 1594adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1595adfc5217SJeff Kirsher 1596adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1597adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1598adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1599adfc5217SJeff Kirsher count *= 100; 1600adfc5217SJeff Kirsher 1601adfc5217SJeff Kirsher /* wait for completion */ 1602adfc5217SJeff Kirsher rc = -EBUSY; 1603adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1604adfc5217SJeff Kirsher udelay(5); 1605adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1606adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1607adfc5217SJeff Kirsher rc = 0; 1608adfc5217SJeff Kirsher break; 1609adfc5217SJeff Kirsher } 1610adfc5217SJeff Kirsher } 1611adfc5217SJeff Kirsher 161251c1a580SMerav Sicron if (rc == -EBUSY) 161351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 161451c1a580SMerav Sicron "nvram write timeout expired\n"); 1615adfc5217SJeff Kirsher return rc; 1616adfc5217SJeff Kirsher } 1617adfc5217SJeff Kirsher 1618adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1619adfc5217SJeff Kirsher 1620adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1621adfc5217SJeff Kirsher int buf_size) 1622adfc5217SJeff Kirsher { 1623adfc5217SJeff Kirsher int rc; 162430c20b67SDmitry Kravkov u32 cmd_flags, align_offset, val; 162530c20b67SDmitry Kravkov __be32 val_be; 1626adfc5217SJeff Kirsher 1627adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 162851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 162951c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1630adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1631adfc5217SJeff Kirsher return -EINVAL; 1632adfc5217SJeff Kirsher } 1633adfc5217SJeff Kirsher 1634adfc5217SJeff Kirsher /* request access to nvram interface */ 1635adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1636adfc5217SJeff Kirsher if (rc) 1637adfc5217SJeff Kirsher return rc; 1638adfc5217SJeff Kirsher 1639adfc5217SJeff Kirsher /* enable access to nvram interface */ 1640adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1641adfc5217SJeff Kirsher 1642adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1643adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 164430c20b67SDmitry Kravkov rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1645adfc5217SJeff Kirsher 1646adfc5217SJeff Kirsher if (rc == 0) { 1647adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 164807ba6af4SMiriam Shitrit * convert it back to cpu order 164907ba6af4SMiriam Shitrit */ 165030c20b67SDmitry Kravkov val = be32_to_cpu(val_be); 165130c20b67SDmitry Kravkov 1652c957d09fSYuval Mintz val &= ~le32_to_cpu((__force __le32) 1653c957d09fSYuval Mintz (0xff << BYTE_OFFSET(offset))); 1654c957d09fSYuval Mintz val |= le32_to_cpu((__force __le32) 1655c957d09fSYuval Mintz (*data_buf << BYTE_OFFSET(offset))); 1656adfc5217SJeff Kirsher 1657adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1658adfc5217SJeff Kirsher cmd_flags); 1659adfc5217SJeff Kirsher } 1660adfc5217SJeff Kirsher 1661adfc5217SJeff Kirsher /* disable access to nvram interface */ 1662adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1663adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1664adfc5217SJeff Kirsher 1665adfc5217SJeff Kirsher return rc; 1666adfc5217SJeff Kirsher } 1667adfc5217SJeff Kirsher 1668adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1669adfc5217SJeff Kirsher int buf_size) 1670adfc5217SJeff Kirsher { 1671adfc5217SJeff Kirsher int rc; 1672adfc5217SJeff Kirsher u32 cmd_flags; 1673adfc5217SJeff Kirsher u32 val; 1674adfc5217SJeff Kirsher u32 written_so_far; 1675adfc5217SJeff Kirsher 1676adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1677adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1678adfc5217SJeff Kirsher 1679adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 168051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1681adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1682adfc5217SJeff Kirsher offset, buf_size); 1683adfc5217SJeff Kirsher return -EINVAL; 1684adfc5217SJeff Kirsher } 1685adfc5217SJeff Kirsher 1686adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 168751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 168851c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1689adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1690adfc5217SJeff Kirsher return -EINVAL; 1691adfc5217SJeff Kirsher } 1692adfc5217SJeff Kirsher 1693adfc5217SJeff Kirsher /* request access to nvram interface */ 1694adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1695adfc5217SJeff Kirsher if (rc) 1696adfc5217SJeff Kirsher return rc; 1697adfc5217SJeff Kirsher 1698adfc5217SJeff Kirsher /* enable access to nvram interface */ 1699adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1700adfc5217SJeff Kirsher 1701adfc5217SJeff Kirsher written_so_far = 0; 1702adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1703adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1704adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1705adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1706adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1707adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1708adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1709adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1710adfc5217SJeff Kirsher 1711adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1712adfc5217SJeff Kirsher 171368bf5a10SYuval Mintz /* Notice unlike bnx2x_nvram_read_dword() this will not 171468bf5a10SYuval Mintz * change val using be32_to_cpu(), which causes data to flip 171568bf5a10SYuval Mintz * if the eeprom is read and then written back. This is due 171668bf5a10SYuval Mintz * to tools utilizing this functionality that would break 171768bf5a10SYuval Mintz * if this would be resolved. 171868bf5a10SYuval Mintz */ 1719adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1720adfc5217SJeff Kirsher 1721adfc5217SJeff Kirsher /* advance to the next dword */ 1722adfc5217SJeff Kirsher offset += sizeof(u32); 1723adfc5217SJeff Kirsher data_buf += sizeof(u32); 1724adfc5217SJeff Kirsher written_so_far += sizeof(u32); 17250ea853dfSYuval Mintz 17260ea853dfSYuval Mintz /* At end of each 4Kb page, release nvram lock to allow MFW 17270ea853dfSYuval Mintz * chance to take it for its own use. 17280ea853dfSYuval Mintz */ 17290ea853dfSYuval Mintz if ((cmd_flags & MCPR_NVM_COMMAND_LAST) && 17300ea853dfSYuval Mintz (written_so_far < buf_size)) { 17310ea853dfSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 17320ea853dfSYuval Mintz "Releasing NVM lock after offset 0x%x\n", 17330ea853dfSYuval Mintz (u32)(offset - sizeof(u32))); 17340ea853dfSYuval Mintz bnx2x_release_nvram_lock(bp); 17350ea853dfSYuval Mintz usleep_range(1000, 2000); 17360ea853dfSYuval Mintz rc = bnx2x_acquire_nvram_lock(bp); 17370ea853dfSYuval Mintz if (rc) 17380ea853dfSYuval Mintz return rc; 17390ea853dfSYuval Mintz } 17400ea853dfSYuval Mintz 1741adfc5217SJeff Kirsher cmd_flags = 0; 1742adfc5217SJeff Kirsher } 1743adfc5217SJeff Kirsher 1744adfc5217SJeff Kirsher /* disable access to nvram interface */ 1745adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1746adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1747adfc5217SJeff Kirsher 1748adfc5217SJeff Kirsher return rc; 1749adfc5217SJeff Kirsher } 1750adfc5217SJeff Kirsher 1751adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1752adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1753adfc5217SJeff Kirsher { 1754adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1755adfc5217SJeff Kirsher int port = BP_PORT(bp); 1756adfc5217SJeff Kirsher int rc = 0; 1757adfc5217SJeff Kirsher u32 ext_phy_config; 17583fb43eb2SYuval Mintz 17593fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 176051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 176151c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1762adfc5217SJeff Kirsher return -EAGAIN; 176351c1a580SMerav Sicron } 1764adfc5217SJeff Kirsher 176551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1766f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1767adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1768adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1769adfc5217SJeff Kirsher 1770adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1771adfc5217SJeff Kirsher 1772adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1773adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 177451c1a580SMerav Sicron !bp->port.pmf) { 177551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 177651c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1777adfc5217SJeff Kirsher return -EINVAL; 177851c1a580SMerav Sicron } 1779adfc5217SJeff Kirsher 1780adfc5217SJeff Kirsher ext_phy_config = 1781adfc5217SJeff Kirsher SHMEM_RD(bp, 1782adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1783adfc5217SJeff Kirsher 1784adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1785adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1786adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1787adfc5217SJeff Kirsher 1788adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1789adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1790adfc5217SJeff Kirsher &bp->link_vars, 0); 1791adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1792adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1793adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1794adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1795adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1796adfc5217SJeff Kirsher bnx2x_link_report(bp); 1797adfc5217SJeff Kirsher 1798adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1799adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1800adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1801adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1802adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1803adfc5217SJeff Kirsher &bp->link_vars, 1); 1804adfc5217SJeff Kirsher 1805adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1806adfc5217SJeff Kirsher &bp->link_vars); 1807adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1808adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1809adfc5217SJeff Kirsher } 1810adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1811adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1812adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1813adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1814adfc5217SJeff Kirsher 1815adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1816adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1817adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1818adfc5217SJeff Kirsher 1819adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1820adfc5217SJeff Kirsher 1821adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1822adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1823adfc5217SJeff Kirsher 1824adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1825adfc5217SJeff Kirsher msleep(500); 1826adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1827adfc5217SJeff Kirsher msleep(500); 1828adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1829adfc5217SJeff Kirsher } 1830adfc5217SJeff Kirsher } else 1831adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1832adfc5217SJeff Kirsher 1833adfc5217SJeff Kirsher return rc; 1834adfc5217SJeff Kirsher } 1835adfc5217SJeff Kirsher 1836adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1837adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1838adfc5217SJeff Kirsher { 1839adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1840adfc5217SJeff Kirsher 1841adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1842adfc5217SJeff Kirsher 1843adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1844adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1845adfc5217SJeff Kirsher 1846adfc5217SJeff Kirsher return 0; 1847adfc5217SJeff Kirsher } 1848adfc5217SJeff Kirsher 1849adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1850adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1851adfc5217SJeff Kirsher { 1852adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1853adfc5217SJeff Kirsher 1854adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1855adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1856adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1857adfc5217SJeff Kirsher 1858adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1859adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1860adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1861adfc5217SJeff Kirsher 1862adfc5217SJeff Kirsher if (netif_running(dev)) 1863adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1864adfc5217SJeff Kirsher 1865adfc5217SJeff Kirsher return 0; 1866adfc5217SJeff Kirsher } 1867adfc5217SJeff Kirsher 1868adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1869adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1870adfc5217SJeff Kirsher { 1871adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1874adfc5217SJeff Kirsher 187565870fa7SMintz, Yuval /* If size isn't already set, we give an estimation of the number 187665870fa7SMintz, Yuval * of buffers we'll have. We're neglecting some possible conditions 187765870fa7SMintz, Yuval * [we couldn't know for certain at this point if number of queues 187865870fa7SMintz, Yuval * might shrink] but the number would be correct for the likely 187965870fa7SMintz, Yuval * scenario. 188065870fa7SMintz, Yuval */ 1881adfc5217SJeff Kirsher if (bp->rx_ring_size) 1882adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 188365870fa7SMintz, Yuval else if (BNX2X_NUM_RX_QUEUES(bp)) 188465870fa7SMintz, Yuval ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp); 1885adfc5217SJeff Kirsher else 1886adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1887adfc5217SJeff Kirsher 1888a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1889adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1890adfc5217SJeff Kirsher } 1891adfc5217SJeff Kirsher 1892adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1893adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1894adfc5217SJeff Kirsher { 1895adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1896adfc5217SJeff Kirsher 189704c46736SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 189804c46736SYuval Mintz "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 189904c46736SYuval Mintz ering->rx_pending, ering->tx_pending); 190004c46736SYuval Mintz 1901909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 1902909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, 1903909d9faaSYuval Mintz "VFs are enabled, can not change ring parameters\n"); 1904909d9faaSYuval Mintz return -EPERM; 1905909d9faaSYuval Mintz } 1906909d9faaSYuval Mintz 1907adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 190851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 190951c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1910adfc5217SJeff Kirsher return -EAGAIN; 1911adfc5217SJeff Kirsher } 1912adfc5217SJeff Kirsher 1913adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1914adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1915adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 19162e98ffc2SDmitry Kravkov (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 191751c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 191851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1919adfc5217SJeff Kirsher return -EINVAL; 192051c1a580SMerav Sicron } 1921adfc5217SJeff Kirsher 1922adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1923adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1924adfc5217SJeff Kirsher 1925adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1926adfc5217SJeff Kirsher } 1927adfc5217SJeff Kirsher 1928adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1929adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1930adfc5217SJeff Kirsher { 1931adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1932adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 19339e7e8399SMintz Yuval int cfg_reg; 19349e7e8399SMintz Yuval 1935adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1936adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1937adfc5217SJeff Kirsher 19389e7e8399SMintz Yuval if (!epause->autoneg) 1939241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 19409e7e8399SMintz Yuval else 19419e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 19429e7e8399SMintz Yuval 19439e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1944adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 19459e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1946adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1947adfc5217SJeff Kirsher 194851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1949f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1950adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1951adfc5217SJeff Kirsher } 1952adfc5217SJeff Kirsher 1953adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1954adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1955adfc5217SJeff Kirsher { 1956adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1957adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1958adfc5217SJeff Kirsher if (IS_MF(bp)) 1959adfc5217SJeff Kirsher return 0; 1960adfc5217SJeff Kirsher 196151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1962f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1963adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1964adfc5217SJeff Kirsher 1965adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1966adfc5217SJeff Kirsher 1967adfc5217SJeff Kirsher if (epause->rx_pause) 1968adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1969adfc5217SJeff Kirsher 1970adfc5217SJeff Kirsher if (epause->tx_pause) 1971adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1972adfc5217SJeff Kirsher 1973adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1974adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1975adfc5217SJeff Kirsher 1976adfc5217SJeff Kirsher if (epause->autoneg) { 1977adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 197851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1979adfc5217SJeff Kirsher return -EINVAL; 1980adfc5217SJeff Kirsher } 1981adfc5217SJeff Kirsher 1982adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1983adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1984adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1985adfc5217SJeff Kirsher } 1986ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv = 0; 19875cd75f0cSYaniv Rosner if (epause->rx_pause) 19885cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 19895cd75f0cSYaniv Rosner 19905cd75f0cSYaniv Rosner if (epause->tx_pause) 19915cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1992ba35a0fdSYaniv Rosner 1993ba35a0fdSYaniv Rosner if (!bp->link_params.req_fc_auto_adv) 1994ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1995adfc5217SJeff Kirsher } 1996adfc5217SJeff Kirsher 199751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1998adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1999adfc5217SJeff Kirsher 2000adfc5217SJeff Kirsher if (netif_running(dev)) { 2001adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2002dc6a20aaSAriel Elior bnx2x_force_link_reset(bp); 2003adfc5217SJeff Kirsher bnx2x_link_set(bp); 2004adfc5217SJeff Kirsher } 2005adfc5217SJeff Kirsher 2006adfc5217SJeff Kirsher return 0; 2007adfc5217SJeff Kirsher } 2008adfc5217SJeff Kirsher 20095889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 2010cf2c1df6SMerav Sicron "register_test (offline) ", 2011cf2c1df6SMerav Sicron "memory_test (offline) ", 2012cf2c1df6SMerav Sicron "int_loopback_test (offline)", 2013cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 2014cf2c1df6SMerav Sicron "nvram_test (online) ", 2015cf2c1df6SMerav Sicron "interrupt_test (online) ", 2016cf2c1df6SMerav Sicron "link_test (online) " 2017adfc5217SJeff Kirsher }; 2018adfc5217SJeff Kirsher 20193521b419SYuval Mintz enum { 20203521b419SYuval Mintz BNX2X_PRI_FLAG_ISCSI, 20213521b419SYuval Mintz BNX2X_PRI_FLAG_FCOE, 20223521b419SYuval Mintz BNX2X_PRI_FLAG_STORAGE, 20233521b419SYuval Mintz BNX2X_PRI_FLAG_LEN, 20243521b419SYuval Mintz }; 20253521b419SYuval Mintz 20263521b419SYuval Mintz static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 20273521b419SYuval Mintz "iSCSI offload support", 20283521b419SYuval Mintz "FCoE offload support", 20293521b419SYuval Mintz "Storage only interface" 20303521b419SYuval Mintz }; 20313521b419SYuval Mintz 2032e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 2033e9939c80SYuval Mintz { 2034e9939c80SYuval Mintz u32 modes = 0; 2035e9939c80SYuval Mintz 2036e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 2037e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 2038e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 2039e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 2040e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 2041e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 2042e9939c80SYuval Mintz 2043e9939c80SYuval Mintz return modes; 2044e9939c80SYuval Mintz } 2045e9939c80SYuval Mintz 2046e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2047e9939c80SYuval Mintz { 2048e9939c80SYuval Mintz u32 eee_adv = 0; 2049e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 2050e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 2051e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 2052e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 2053e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 2054e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 2055e9939c80SYuval Mintz 2056e9939c80SYuval Mintz return eee_adv << shift; 2057e9939c80SYuval Mintz } 2058e9939c80SYuval Mintz 2059e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2060e9939c80SYuval Mintz { 2061e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2062e9939c80SYuval Mintz u32 eee_cfg; 2063e9939c80SYuval Mintz 2064e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2065e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2066e9939c80SYuval Mintz return -EOPNOTSUPP; 2067e9939c80SYuval Mintz } 2068e9939c80SYuval Mintz 206908e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2070e9939c80SYuval Mintz 2071e9939c80SYuval Mintz edata->supported = 2072e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2073e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 2074e9939c80SYuval Mintz 2075e9939c80SYuval Mintz edata->advertised = 2076e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2077e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2078e9939c80SYuval Mintz edata->lp_advertised = 2079e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2080e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2081e9939c80SYuval Mintz 2082e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 2083e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2084e9939c80SYuval Mintz 2085e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2086e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2087e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2088e9939c80SYuval Mintz 2089e9939c80SYuval Mintz return 0; 2090e9939c80SYuval Mintz } 2091e9939c80SYuval Mintz 2092e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2093e9939c80SYuval Mintz { 2094e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2095e9939c80SYuval Mintz u32 eee_cfg; 2096e9939c80SYuval Mintz u32 advertised; 2097e9939c80SYuval Mintz 2098e9939c80SYuval Mintz if (IS_MF(bp)) 2099e9939c80SYuval Mintz return 0; 2100e9939c80SYuval Mintz 2101e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2102e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2103e9939c80SYuval Mintz return -EOPNOTSUPP; 2104e9939c80SYuval Mintz } 2105e9939c80SYuval Mintz 210608e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2107e9939c80SYuval Mintz 2108e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2109e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2110e9939c80SYuval Mintz return -EOPNOTSUPP; 2111e9939c80SYuval Mintz } 2112e9939c80SYuval Mintz 2113e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 2114e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2115e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2116e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2117efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 2118e9939c80SYuval Mintz return -EINVAL; 2119e9939c80SYuval Mintz } 2120e9939c80SYuval Mintz 2121e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2122e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2123e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 2124e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 2125e9939c80SYuval Mintz return -EINVAL; 2126e9939c80SYuval Mintz } 2127e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 2128e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2129e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2130e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 2131e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2132e9939c80SYuval Mintz return -EINVAL; 2133e9939c80SYuval Mintz } 2134e9939c80SYuval Mintz 2135e9939c80SYuval Mintz /* All is well; Apply changes*/ 2136e9939c80SYuval Mintz if (edata->eee_enabled) 2137e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2138e9939c80SYuval Mintz else 2139e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2140e9939c80SYuval Mintz 2141e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 2142e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2143e9939c80SYuval Mintz else 2144e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2145e9939c80SYuval Mintz 2146e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2147e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2148e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 2149e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 2150e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 2151e9939c80SYuval Mintz 215216a5fd92SYuval Mintz /* Restart link to propagate changes */ 2153e9939c80SYuval Mintz if (netif_running(dev)) { 2154e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 21555d07d868SYuval Mintz bnx2x_force_link_reset(bp); 2156e9939c80SYuval Mintz bnx2x_link_set(bp); 2157e9939c80SYuval Mintz } 2158e9939c80SYuval Mintz 2159e9939c80SYuval Mintz return 0; 2160e9939c80SYuval Mintz } 2161e9939c80SYuval Mintz 2162adfc5217SJeff Kirsher enum { 2163adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 2164adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 2165adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 2166adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 2167adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 2168adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 2169adfc5217SJeff Kirsher }; 2170adfc5217SJeff Kirsher 2171adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2172adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2173adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2174adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2175adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2176adfc5217SJeff Kirsher 2177adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2178adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2179adfc5217SJeff Kirsher 2180adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 2181adfc5217SJeff Kirsher { 2182adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 2183adfc5217SJeff Kirsher u32 wr_val = 0, hw; 2184adfc5217SJeff Kirsher int port = BP_PORT(bp); 2185adfc5217SJeff Kirsher static const struct { 2186adfc5217SJeff Kirsher u32 hw; 2187adfc5217SJeff Kirsher u32 offset0; 2188adfc5217SJeff Kirsher u32 offset1; 2189adfc5217SJeff Kirsher u32 mask; 2190adfc5217SJeff Kirsher } reg_tbl[] = { 2191adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 2192adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2193adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2194adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2195adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 2196adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 2197adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2198adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2199adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2200adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2201adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 2202adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2203adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2204adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2205adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2206adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2207adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2208adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2209adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2210adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2211adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 2212adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2213adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2214adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2215adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2216adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 2217adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2218adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2219adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2220adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2221adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2222adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2223adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2224adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2225adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2226adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2227adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2228adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2229adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2230adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2231adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2232adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2233adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2234adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2235adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2236adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2237adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2238adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2239adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2240adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2241adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2242adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2243adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2244adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2245adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2246adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2247adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2248adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2249adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2250adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2251adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 2252adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2253adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2254adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2255adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2256adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2257adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2258adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2259adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2260adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2261adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2262adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2263adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2264adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2265adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2266adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2267adfc5217SJeff Kirsher 2268adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2269adfc5217SJeff Kirsher }; 2270adfc5217SJeff Kirsher 22713fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 227251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 227351c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2274adfc5217SJeff Kirsher return rc; 227551c1a580SMerav Sicron } 2276adfc5217SJeff Kirsher 2277adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2278adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 2279adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2280adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 2281adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2282adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 2283adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 2284adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 2285adfc5217SJeff Kirsher else /* e3 A0 */ 2286adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 2287adfc5217SJeff Kirsher 2288adfc5217SJeff Kirsher /* Repeat the test twice: 228907ba6af4SMiriam Shitrit * First by writing 0x00000000, second by writing 0xffffffff 229007ba6af4SMiriam Shitrit */ 2291adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 2292adfc5217SJeff Kirsher 2293adfc5217SJeff Kirsher switch (idx) { 2294adfc5217SJeff Kirsher case 0: 2295adfc5217SJeff Kirsher wr_val = 0; 2296adfc5217SJeff Kirsher break; 2297adfc5217SJeff Kirsher case 1: 2298adfc5217SJeff Kirsher wr_val = 0xffffffff; 2299adfc5217SJeff Kirsher break; 2300adfc5217SJeff Kirsher } 2301adfc5217SJeff Kirsher 2302adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2303adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 2304adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 2305adfc5217SJeff Kirsher continue; 2306adfc5217SJeff Kirsher 2307adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2308adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 2309adfc5217SJeff Kirsher 2310adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 2311adfc5217SJeff Kirsher 2312adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 2313adfc5217SJeff Kirsher 2314adfc5217SJeff Kirsher val = REG_RD(bp, offset); 2315adfc5217SJeff Kirsher 2316adfc5217SJeff Kirsher /* Restore the original register's value */ 2317adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 2318adfc5217SJeff Kirsher 2319adfc5217SJeff Kirsher /* verify value is as expected */ 2320adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 232151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2322adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2323adfc5217SJeff Kirsher offset, val, wr_val, mask); 2324adfc5217SJeff Kirsher goto test_reg_exit; 2325adfc5217SJeff Kirsher } 2326adfc5217SJeff Kirsher } 2327adfc5217SJeff Kirsher } 2328adfc5217SJeff Kirsher 2329adfc5217SJeff Kirsher rc = 0; 2330adfc5217SJeff Kirsher 2331adfc5217SJeff Kirsher test_reg_exit: 2332adfc5217SJeff Kirsher return rc; 2333adfc5217SJeff Kirsher } 2334adfc5217SJeff Kirsher 2335adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 2336adfc5217SJeff Kirsher { 2337adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 2338adfc5217SJeff Kirsher u32 val, index; 2339adfc5217SJeff Kirsher static const struct { 2340adfc5217SJeff Kirsher u32 offset; 2341adfc5217SJeff Kirsher int size; 2342adfc5217SJeff Kirsher } mem_tbl[] = { 2343adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2344adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2345adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2346adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2347adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2348adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2349adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2350adfc5217SJeff Kirsher 2351adfc5217SJeff Kirsher { 0xffffffff, 0 } 2352adfc5217SJeff Kirsher }; 2353adfc5217SJeff Kirsher 2354adfc5217SJeff Kirsher static const struct { 2355adfc5217SJeff Kirsher char *name; 2356adfc5217SJeff Kirsher u32 offset; 2357adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2358adfc5217SJeff Kirsher } prty_tbl[] = { 2359adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2360adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2361adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2362adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 2363adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2364adfc5217SJeff Kirsher {0, 0, 0, 0} }, 2365adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2366adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2367adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2368adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2369adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2370adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 2371adfc5217SJeff Kirsher 2372adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 2373adfc5217SJeff Kirsher }; 2374adfc5217SJeff Kirsher 23753fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 237651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 237751c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2378adfc5217SJeff Kirsher return rc; 237951c1a580SMerav Sicron } 2380adfc5217SJeff Kirsher 2381adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2382adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 2383adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2384adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 2385adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2386adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 2387adfc5217SJeff Kirsher else /* e3 */ 2388adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 2389adfc5217SJeff Kirsher 2390adfc5217SJeff Kirsher /* pre-Check the parity status */ 2391adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2392adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2393adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 239451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2395adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2396adfc5217SJeff Kirsher goto test_mem_exit; 2397adfc5217SJeff Kirsher } 2398adfc5217SJeff Kirsher } 2399adfc5217SJeff Kirsher 2400adfc5217SJeff Kirsher /* Go through all the memories */ 2401adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2402adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 2403adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 2404adfc5217SJeff Kirsher 2405adfc5217SJeff Kirsher /* Check the parity status */ 2406adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2407adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2408adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 240951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2410adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2411adfc5217SJeff Kirsher goto test_mem_exit; 2412adfc5217SJeff Kirsher } 2413adfc5217SJeff Kirsher } 2414adfc5217SJeff Kirsher 2415adfc5217SJeff Kirsher rc = 0; 2416adfc5217SJeff Kirsher 2417adfc5217SJeff Kirsher test_mem_exit: 2418adfc5217SJeff Kirsher return rc; 2419adfc5217SJeff Kirsher } 2420adfc5217SJeff Kirsher 2421adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2422adfc5217SJeff Kirsher { 2423adfc5217SJeff Kirsher int cnt = 1400; 2424adfc5217SJeff Kirsher 2425adfc5217SJeff Kirsher if (link_up) { 2426adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2427adfc5217SJeff Kirsher msleep(20); 2428adfc5217SJeff Kirsher 2429adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 243051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 24318970b2e4SMerav Sicron 24328970b2e4SMerav Sicron cnt = 1400; 24338970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 24348970b2e4SMerav Sicron msleep(20); 24358970b2e4SMerav Sicron 24368970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 24378970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24388970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2439adfc5217SJeff Kirsher } 2440adfc5217SJeff Kirsher } 2441adfc5217SJeff Kirsher 2442adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2443adfc5217SJeff Kirsher { 2444adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2445adfc5217SJeff Kirsher struct sk_buff *skb; 2446adfc5217SJeff Kirsher unsigned char *packet; 2447adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2448adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 244965565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2450adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2451adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2452b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2453adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2454adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2455adfc5217SJeff Kirsher dma_addr_t mapping; 2456adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2457adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2458adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2459adfc5217SJeff Kirsher u16 len; 2460adfc5217SJeff Kirsher int rc = -ENODEV; 2461e52fcb24SEric Dumazet u8 *data; 24628970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 24638970b2e4SMerav Sicron txdata->txq_index); 2464adfc5217SJeff Kirsher 2465adfc5217SJeff Kirsher /* check the loopback mode */ 2466adfc5217SJeff Kirsher switch (loopback_mode) { 2467adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 24688970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 24698970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2470adfc5217SJeff Kirsher return -EINVAL; 24718970b2e4SMerav Sicron } 2472adfc5217SJeff Kirsher break; 2473adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 247432911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 247532911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 247632911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 247732911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 247832911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 247932911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 248032911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 248132911333SYaniv Rosner else 248232911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 248332911333SYaniv Rosner } else 248432911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 248532911333SYaniv Rosner 2486adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2487adfc5217SJeff Kirsher break; 24888970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 24898970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 24908970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24918970b2e4SMerav Sicron "Can't configure external loopback\n"); 24928970b2e4SMerav Sicron return -EINVAL; 24938970b2e4SMerav Sicron } 24948970b2e4SMerav Sicron break; 2495adfc5217SJeff Kirsher default: 249651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2497adfc5217SJeff Kirsher return -EINVAL; 2498adfc5217SJeff Kirsher } 2499adfc5217SJeff Kirsher 2500adfc5217SJeff Kirsher /* prepare the loopback packet */ 2501adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2502adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2503adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2504adfc5217SJeff Kirsher if (!skb) { 250551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2506adfc5217SJeff Kirsher rc = -ENOMEM; 2507adfc5217SJeff Kirsher goto test_loopback_exit; 2508adfc5217SJeff Kirsher } 2509adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2510adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2511c7bf7169SJoe Perches eth_zero_addr(packet + ETH_ALEN); 2512adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2513adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2514adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2515adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2516adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2517adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2518adfc5217SJeff Kirsher rc = -ENOMEM; 2519adfc5217SJeff Kirsher dev_kfree_skb(skb); 252051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2521adfc5217SJeff Kirsher goto test_loopback_exit; 2522adfc5217SJeff Kirsher } 2523adfc5217SJeff Kirsher 2524adfc5217SJeff Kirsher /* send the loopback packet */ 2525adfc5217SJeff Kirsher num_pkts = 0; 2526adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2527adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2528adfc5217SJeff Kirsher 252973dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 253073dbb5e1SDmitry Kravkov 2531adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2532adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2533adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2534adfc5217SJeff Kirsher tx_buf->skb = skb; 2535adfc5217SJeff Kirsher tx_buf->flags = 0; 2536adfc5217SJeff Kirsher 2537adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2538adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2539adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2540adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2541adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2542adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2543adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2544adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2545adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2546adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2547adfc5217SJeff Kirsher 1); 254896bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 254996bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 255096bed4b9SYuval Mintz 0); 2551adfc5217SJeff Kirsher 2552adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2553adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2554adfc5217SJeff Kirsher 255596bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 255696bed4b9SYuval Mintz u16 global_data = 0; 255796bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 255896bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2559adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 256096bed4b9SYuval Mintz SET_FLAG(global_data, 256196bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 256296bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 256396bed4b9SYuval Mintz } else { 256496bed4b9SYuval Mintz u32 parsing_data = 0; 256596bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 256696bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 256796bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 256896bed4b9SYuval Mintz SET_FLAG(parsing_data, 256996bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 257096bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 257196bed4b9SYuval Mintz } 2572adfc5217SJeff Kirsher wmb(); 2573adfc5217SJeff Kirsher 2574adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2575adfc5217SJeff Kirsher barrier(); 2576adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2577adfc5217SJeff Kirsher 2578adfc5217SJeff Kirsher mmiowb(); 2579adfc5217SJeff Kirsher barrier(); 2580adfc5217SJeff Kirsher 2581adfc5217SJeff Kirsher num_pkts++; 2582adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2583adfc5217SJeff Kirsher 2584adfc5217SJeff Kirsher udelay(100); 2585adfc5217SJeff Kirsher 2586adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2587adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2588adfc5217SJeff Kirsher goto test_loopback_exit; 2589adfc5217SJeff Kirsher 2590adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2591adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2592adfc5217SJeff Kirsher * disabled. 2593adfc5217SJeff Kirsher */ 2594adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2595adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2596adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2597adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2598adfc5217SJeff Kirsher */ 2599adfc5217SJeff Kirsher local_bh_disable(); 2600adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2601adfc5217SJeff Kirsher local_bh_enable(); 2602adfc5217SJeff Kirsher } 2603adfc5217SJeff Kirsher 2604adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2605adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2606adfc5217SJeff Kirsher goto test_loopback_exit; 2607adfc5217SJeff Kirsher 2608b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2609adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2610adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2611adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2612adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2613adfc5217SJeff Kirsher 2614621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2615adfc5217SJeff Kirsher if (len != pkt_size) 2616adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2617adfc5217SJeff Kirsher 2618adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2619adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2620adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2621adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2622e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2623adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2624e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2625adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2626adfc5217SJeff Kirsher 2627adfc5217SJeff Kirsher rc = 0; 2628adfc5217SJeff Kirsher 2629adfc5217SJeff Kirsher test_loopback_rx_exit: 2630adfc5217SJeff Kirsher 2631adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2632adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2633adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2634adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2635adfc5217SJeff Kirsher 2636adfc5217SJeff Kirsher /* Update producers */ 2637adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2638adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2639adfc5217SJeff Kirsher 2640adfc5217SJeff Kirsher test_loopback_exit: 2641adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2642adfc5217SJeff Kirsher 2643adfc5217SJeff Kirsher return rc; 2644adfc5217SJeff Kirsher } 2645adfc5217SJeff Kirsher 2646adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2647adfc5217SJeff Kirsher { 2648adfc5217SJeff Kirsher int rc = 0, res; 2649adfc5217SJeff Kirsher 2650adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2651adfc5217SJeff Kirsher return rc; 2652adfc5217SJeff Kirsher 2653adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2654adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2655adfc5217SJeff Kirsher 2656adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2657adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2658adfc5217SJeff Kirsher 2659adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2660adfc5217SJeff Kirsher if (res) { 266151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2662adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2663adfc5217SJeff Kirsher } 2664adfc5217SJeff Kirsher 2665adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2666adfc5217SJeff Kirsher if (res) { 266751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2668adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2669adfc5217SJeff Kirsher } 2670adfc5217SJeff Kirsher 2671adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2672adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2673adfc5217SJeff Kirsher 2674adfc5217SJeff Kirsher return rc; 2675adfc5217SJeff Kirsher } 2676adfc5217SJeff Kirsher 26778970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 26788970b2e4SMerav Sicron { 26798970b2e4SMerav Sicron int rc; 26808970b2e4SMerav Sicron u8 is_serdes = 26818970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 26828970b2e4SMerav Sicron 26838970b2e4SMerav Sicron if (BP_NOMCP(bp)) 26848970b2e4SMerav Sicron return -ENODEV; 26858970b2e4SMerav Sicron 26868970b2e4SMerav Sicron if (!netif_running(bp->dev)) 26878970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 26888970b2e4SMerav Sicron 26895d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 26908970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 26918970b2e4SMerav Sicron if (rc) { 26928970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26938970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 26948970b2e4SMerav Sicron return -ENODEV; 26958970b2e4SMerav Sicron } 26968970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 26978970b2e4SMerav Sicron 26988970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 26998970b2e4SMerav Sicron 27008970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 27018970b2e4SMerav Sicron if (rc) 27028970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 27038970b2e4SMerav Sicron 27048970b2e4SMerav Sicron bnx2x_netif_start(bp); 27058970b2e4SMerav Sicron 27068970b2e4SMerav Sicron return rc; 27078970b2e4SMerav Sicron } 27088970b2e4SMerav Sicron 2709edb944d2SDmitry Kravkov struct code_entry { 2710edb944d2SDmitry Kravkov u32 sram_start_addr; 2711edb944d2SDmitry Kravkov u32 code_attribute; 2712edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_MASK 0xf0800003 2713edb944d2SDmitry Kravkov #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2714edb944d2SDmitry Kravkov #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2715edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2716edb944d2SDmitry Kravkov u32 nvm_start_addr; 2717edb944d2SDmitry Kravkov }; 2718edb944d2SDmitry Kravkov 2719edb944d2SDmitry Kravkov #define CODE_ENTRY_MAX 16 2720edb944d2SDmitry Kravkov #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2721edb944d2SDmitry Kravkov #define MAX_IMAGES_IN_EXTENDED_DIR 64 2722edb944d2SDmitry Kravkov #define NVRAM_DIR_OFFSET 0x14 2723edb944d2SDmitry Kravkov 2724edb944d2SDmitry Kravkov #define EXTENDED_DIR_EXISTS(code) \ 2725edb944d2SDmitry Kravkov ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2726edb944d2SDmitry Kravkov (code & CODE_IMAGE_LENGTH_MASK) != 0) 2727edb944d2SDmitry Kravkov 2728adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2729edb944d2SDmitry Kravkov #define CRC_BUFF_SIZE 256 2730edb944d2SDmitry Kravkov 2731edb944d2SDmitry Kravkov static int bnx2x_nvram_crc(struct bnx2x *bp, 2732edb944d2SDmitry Kravkov int offset, 2733edb944d2SDmitry Kravkov int size, 2734edb944d2SDmitry Kravkov u8 *buff) 2735edb944d2SDmitry Kravkov { 2736edb944d2SDmitry Kravkov u32 crc = ~0; 2737edb944d2SDmitry Kravkov int rc = 0, done = 0; 2738edb944d2SDmitry Kravkov 2739edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2740edb944d2SDmitry Kravkov "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2741edb944d2SDmitry Kravkov 2742edb944d2SDmitry Kravkov while (done < size) { 2743edb944d2SDmitry Kravkov int count = min_t(int, size - done, CRC_BUFF_SIZE); 2744edb944d2SDmitry Kravkov 2745edb944d2SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2746edb944d2SDmitry Kravkov 2747edb944d2SDmitry Kravkov if (rc) 2748edb944d2SDmitry Kravkov return rc; 2749edb944d2SDmitry Kravkov 2750edb944d2SDmitry Kravkov crc = crc32_le(crc, buff, count); 2751edb944d2SDmitry Kravkov done += count; 2752edb944d2SDmitry Kravkov } 2753edb944d2SDmitry Kravkov 2754edb944d2SDmitry Kravkov if (crc != CRC32_RESIDUAL) 2755edb944d2SDmitry Kravkov rc = -EINVAL; 2756edb944d2SDmitry Kravkov 2757edb944d2SDmitry Kravkov return rc; 2758edb944d2SDmitry Kravkov } 2759edb944d2SDmitry Kravkov 2760edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2761edb944d2SDmitry Kravkov struct code_entry *entry, 2762edb944d2SDmitry Kravkov u8 *buff) 2763edb944d2SDmitry Kravkov { 2764edb944d2SDmitry Kravkov size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2765edb944d2SDmitry Kravkov u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2766edb944d2SDmitry Kravkov int rc; 2767edb944d2SDmitry Kravkov 2768edb944d2SDmitry Kravkov /* Zero-length images and AFEX profiles do not have CRC */ 2769edb944d2SDmitry Kravkov if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2770edb944d2SDmitry Kravkov return 0; 2771edb944d2SDmitry Kravkov 2772edb944d2SDmitry Kravkov rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2773edb944d2SDmitry Kravkov if (rc) 2774edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2775edb944d2SDmitry Kravkov "image %x has failed crc test (rc %d)\n", type, rc); 2776edb944d2SDmitry Kravkov 2777edb944d2SDmitry Kravkov return rc; 2778edb944d2SDmitry Kravkov } 2779edb944d2SDmitry Kravkov 2780edb944d2SDmitry Kravkov static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2781edb944d2SDmitry Kravkov { 2782edb944d2SDmitry Kravkov int rc; 2783edb944d2SDmitry Kravkov struct code_entry entry; 2784edb944d2SDmitry Kravkov 2785edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2786edb944d2SDmitry Kravkov if (rc) 2787edb944d2SDmitry Kravkov return rc; 2788edb944d2SDmitry Kravkov 2789edb944d2SDmitry Kravkov return bnx2x_test_nvram_dir(bp, &entry, buff); 2790edb944d2SDmitry Kravkov } 2791edb944d2SDmitry Kravkov 2792edb944d2SDmitry Kravkov static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2793edb944d2SDmitry Kravkov { 2794edb944d2SDmitry Kravkov u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2795edb944d2SDmitry Kravkov struct code_entry entry; 2796edb944d2SDmitry Kravkov int i; 2797edb944d2SDmitry Kravkov 2798edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 2799edb944d2SDmitry Kravkov dir_offset + 2800edb944d2SDmitry Kravkov sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2801edb944d2SDmitry Kravkov (u32 *)&entry, sizeof(entry)); 2802edb944d2SDmitry Kravkov if (rc) 2803edb944d2SDmitry Kravkov return rc; 2804edb944d2SDmitry Kravkov 2805edb944d2SDmitry Kravkov if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2806edb944d2SDmitry Kravkov return 0; 2807edb944d2SDmitry Kravkov 2808edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2809edb944d2SDmitry Kravkov &cnt, sizeof(u32)); 2810edb944d2SDmitry Kravkov if (rc) 2811edb944d2SDmitry Kravkov return rc; 2812edb944d2SDmitry Kravkov 2813edb944d2SDmitry Kravkov dir_offset = entry.nvm_start_addr + 8; 2814edb944d2SDmitry Kravkov 2815edb944d2SDmitry Kravkov for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2816edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2817edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2818edb944d2SDmitry Kravkov buff); 2819edb944d2SDmitry Kravkov if (rc) 2820edb944d2SDmitry Kravkov return rc; 2821edb944d2SDmitry Kravkov } 2822edb944d2SDmitry Kravkov 2823edb944d2SDmitry Kravkov return 0; 2824edb944d2SDmitry Kravkov } 2825edb944d2SDmitry Kravkov 2826edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2827edb944d2SDmitry Kravkov { 2828edb944d2SDmitry Kravkov u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2829edb944d2SDmitry Kravkov int i; 2830edb944d2SDmitry Kravkov 2831edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2832edb944d2SDmitry Kravkov 2833edb944d2SDmitry Kravkov for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2834edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2835edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2836edb944d2SDmitry Kravkov buff); 2837edb944d2SDmitry Kravkov if (rc) 2838edb944d2SDmitry Kravkov return rc; 2839edb944d2SDmitry Kravkov } 2840edb944d2SDmitry Kravkov 2841edb944d2SDmitry Kravkov return bnx2x_test_nvram_ext_dirs(bp, buff); 2842edb944d2SDmitry Kravkov } 2843edb944d2SDmitry Kravkov 2844edb944d2SDmitry Kravkov struct crc_pair { 2845edb944d2SDmitry Kravkov int offset; 2846edb944d2SDmitry Kravkov int size; 2847edb944d2SDmitry Kravkov }; 2848edb944d2SDmitry Kravkov 2849edb944d2SDmitry Kravkov static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2850edb944d2SDmitry Kravkov const struct crc_pair *nvram_tbl, u8 *buf) 2851edb944d2SDmitry Kravkov { 2852edb944d2SDmitry Kravkov int i; 2853edb944d2SDmitry Kravkov 2854edb944d2SDmitry Kravkov for (i = 0; nvram_tbl[i].size; i++) { 2855edb944d2SDmitry Kravkov int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2856edb944d2SDmitry Kravkov nvram_tbl[i].size, buf); 2857edb944d2SDmitry Kravkov if (rc) { 2858edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2859edb944d2SDmitry Kravkov "nvram_tbl[%d] has failed crc test (rc %d)\n", 2860edb944d2SDmitry Kravkov i, rc); 2861edb944d2SDmitry Kravkov return rc; 2862edb944d2SDmitry Kravkov } 2863edb944d2SDmitry Kravkov } 2864edb944d2SDmitry Kravkov 2865edb944d2SDmitry Kravkov return 0; 2866edb944d2SDmitry Kravkov } 2867adfc5217SJeff Kirsher 2868adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2869adfc5217SJeff Kirsher { 2870edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl[] = { 2871adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2872adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2873adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2874adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2875adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2876adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2877adfc5217SJeff Kirsher { 0, 0 } 2878adfc5217SJeff Kirsher }; 2879edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl2[] = { 2880edb944d2SDmitry Kravkov { 0x7e8, 0x350 }, /* manuf_info2 */ 2881edb944d2SDmitry Kravkov { 0xb38, 0xf0 }, /* feature_info */ 2882edb944d2SDmitry Kravkov { 0, 0 } 2883edb944d2SDmitry Kravkov }; 2884edb944d2SDmitry Kravkov 288585640952SDmitry Kravkov u8 *buf; 2886edb944d2SDmitry Kravkov int rc; 2887edb944d2SDmitry Kravkov u32 magic; 2888adfc5217SJeff Kirsher 2889adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2890adfc5217SJeff Kirsher return 0; 2891adfc5217SJeff Kirsher 2892edb944d2SDmitry Kravkov buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2893afa13b4bSMintz Yuval if (!buf) { 289451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2895afa13b4bSMintz Yuval rc = -ENOMEM; 2896afa13b4bSMintz Yuval goto test_nvram_exit; 2897afa13b4bSMintz Yuval } 2898afa13b4bSMintz Yuval 289985640952SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2900adfc5217SJeff Kirsher if (rc) { 290151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 290251c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2903adfc5217SJeff Kirsher goto test_nvram_exit; 2904adfc5217SJeff Kirsher } 2905adfc5217SJeff Kirsher 2906adfc5217SJeff Kirsher if (magic != 0x669955aa) { 290751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 290851c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2909adfc5217SJeff Kirsher rc = -ENODEV; 2910adfc5217SJeff Kirsher goto test_nvram_exit; 2911adfc5217SJeff Kirsher } 2912adfc5217SJeff Kirsher 2913edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2914edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2915edb944d2SDmitry Kravkov if (rc) 2916adfc5217SJeff Kirsher goto test_nvram_exit; 2917adfc5217SJeff Kirsher 2918edb944d2SDmitry Kravkov if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2919edb944d2SDmitry Kravkov u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2920edb944d2SDmitry Kravkov SHARED_HW_CFG_HIDE_PORT1; 2921edb944d2SDmitry Kravkov 2922edb944d2SDmitry Kravkov if (!hide) { 292351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2924edb944d2SDmitry Kravkov "Port 1 CRC test-set\n"); 2925edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2926edb944d2SDmitry Kravkov if (rc) 2927adfc5217SJeff Kirsher goto test_nvram_exit; 2928adfc5217SJeff Kirsher } 2929adfc5217SJeff Kirsher } 2930adfc5217SJeff Kirsher 2931edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_dirs(bp, buf); 2932edb944d2SDmitry Kravkov 2933adfc5217SJeff Kirsher test_nvram_exit: 2934afa13b4bSMintz Yuval kfree(buf); 2935adfc5217SJeff Kirsher return rc; 2936adfc5217SJeff Kirsher } 2937adfc5217SJeff Kirsher 2938adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2939adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2940adfc5217SJeff Kirsher { 29413b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2942adfc5217SJeff Kirsher 294351c1a580SMerav Sicron if (!netif_running(bp->dev)) { 294451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 294551c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2946adfc5217SJeff Kirsher return -ENODEV; 294751c1a580SMerav Sicron } 2948adfc5217SJeff Kirsher 294915192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2950adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2951adfc5217SJeff Kirsher 2952adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2953adfc5217SJeff Kirsher 2954adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2955adfc5217SJeff Kirsher } 2956adfc5217SJeff Kirsher 2957adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2958adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2959adfc5217SJeff Kirsher { 2960adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2961a336ca7cSYaniv Rosner u8 is_serdes, link_up; 2962a336ca7cSYaniv Rosner int rc, cnt = 0; 2963cf2c1df6SMerav Sicron 2964909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 2965909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, 2966909d9faaSYuval Mintz "VFs are enabled, can not perform self test\n"); 2967909d9faaSYuval Mintz return; 2968909d9faaSYuval Mintz } 2969909d9faaSYuval Mintz 2970adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 297151c1a580SMerav Sicron netdev_err(bp->dev, 297251c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2973adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2974adfc5217SJeff Kirsher return; 2975adfc5217SJeff Kirsher } 29762de67439SYuval Mintz 29778970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29788970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 29798970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 29808970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2981adfc5217SJeff Kirsher 2982cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2983adfc5217SJeff Kirsher 2984bd8e012bSYuval Mintz if (bnx2x_test_nvram(bp) != 0) { 2985bd8e012bSYuval Mintz if (!IS_MF(bp)) 2986bd8e012bSYuval Mintz buf[4] = 1; 2987bd8e012bSYuval Mintz else 2988bd8e012bSYuval Mintz buf[0] = 1; 2989bd8e012bSYuval Mintz etest->flags |= ETH_TEST_FL_FAILED; 2990bd8e012bSYuval Mintz } 2991bd8e012bSYuval Mintz 2992cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2993bd8e012bSYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2994adfc5217SJeff Kirsher return; 2995cf2c1df6SMerav Sicron } 2996adfc5217SJeff Kirsher 2997adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2998a336ca7cSYaniv Rosner link_up = bp->link_vars.link_up; 2999cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 3000cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 3001adfc5217SJeff Kirsher int port = BP_PORT(bp); 3002adfc5217SJeff Kirsher u32 val; 3003adfc5217SJeff Kirsher 3004adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 3005adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 3006adfc5217SJeff Kirsher /* disable input for TX port IF */ 3007adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 3008adfc5217SJeff Kirsher 30095d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3010cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 3011cf2c1df6SMerav Sicron if (rc) { 3012cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 3013cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 3014cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 3015cf2c1df6SMerav Sicron return; 3016cf2c1df6SMerav Sicron } 3017cf2c1df6SMerav Sicron 3018adfc5217SJeff Kirsher /* wait until link state is restored */ 3019adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 3020adfc5217SJeff Kirsher 3021adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 3022adfc5217SJeff Kirsher buf[0] = 1; 3023adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3024adfc5217SJeff Kirsher } 3025adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 3026adfc5217SJeff Kirsher buf[1] = 1; 3027adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3028adfc5217SJeff Kirsher } 3029adfc5217SJeff Kirsher 30308970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3031adfc5217SJeff Kirsher if (buf[2] != 0) 3032adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3033adfc5217SJeff Kirsher 30348970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 30358970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 30368970b2e4SMerav Sicron if (buf[3] != 0) 30378970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 30388970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 30398970b2e4SMerav Sicron } 30408970b2e4SMerav Sicron 30415d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3042adfc5217SJeff Kirsher 3043adfc5217SJeff Kirsher /* restore input for TX port IF */ 3044adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3045cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3046cf2c1df6SMerav Sicron if (rc) { 3047cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 3048cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 3049cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 3050cf2c1df6SMerav Sicron return; 3051cf2c1df6SMerav Sicron } 3052adfc5217SJeff Kirsher /* wait until link state is restored */ 3053adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 3054adfc5217SJeff Kirsher } 3055bd8e012bSYuval Mintz 3056adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 3057cf2c1df6SMerav Sicron if (!IS_MF(bp)) 30588970b2e4SMerav Sicron buf[5] = 1; 3059cf2c1df6SMerav Sicron else 3060cf2c1df6SMerav Sicron buf[1] = 1; 3061adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3062adfc5217SJeff Kirsher } 3063adfc5217SJeff Kirsher 3064a336ca7cSYaniv Rosner if (link_up) { 3065a336ca7cSYaniv Rosner cnt = 100; 3066a336ca7cSYaniv Rosner while (bnx2x_link_test(bp, is_serdes) && --cnt) 3067a336ca7cSYaniv Rosner msleep(20); 3068a336ca7cSYaniv Rosner } 3069a336ca7cSYaniv Rosner 3070a336ca7cSYaniv Rosner if (!cnt) { 3071cf2c1df6SMerav Sicron if (!IS_MF(bp)) 30728970b2e4SMerav Sicron buf[6] = 1; 3073cf2c1df6SMerav Sicron else 3074cf2c1df6SMerav Sicron buf[2] = 1; 3075adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3076adfc5217SJeff Kirsher } 3077adfc5217SJeff Kirsher } 3078adfc5217SJeff Kirsher 307944c33c66SMichal Schmidt #define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat) 30803fb2d492SYuval Mintz #define HIDE_PORT_STAT(bp) IS_VF(bp) 3081adfc5217SJeff Kirsher 3082adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 3083adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 3084adfc5217SJeff Kirsher */ 30851191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 3086adfc5217SJeff Kirsher { 3087adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 3088adfc5217SJeff Kirsher } 3089adfc5217SJeff Kirsher 3090adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3091adfc5217SJeff Kirsher { 3092adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 30933521b419SYuval Mintz int i, num_strings = 0; 3094adfc5217SJeff Kirsher 3095adfc5217SJeff Kirsher switch (stringset) { 3096adfc5217SJeff Kirsher case ETH_SS_STATS: 3097adfc5217SJeff Kirsher if (is_multi(bp)) { 30983521b419SYuval Mintz num_strings = bnx2x_num_stat_queues(bp) * 3099adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 3100d5e83632SYuval Mintz } else 31013521b419SYuval Mintz num_strings = 0; 3102d8361051SYuval Mintz if (HIDE_PORT_STAT(bp)) { 3103adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 310444c33c66SMichal Schmidt if (!IS_PORT_STAT(i)) 31053521b419SYuval Mintz num_strings++; 3106adfc5217SJeff Kirsher } else 31073521b419SYuval Mintz num_strings += BNX2X_NUM_STATS; 3108d5e83632SYuval Mintz 31093521b419SYuval Mintz return num_strings; 3110adfc5217SJeff Kirsher 3111adfc5217SJeff Kirsher case ETH_SS_TEST: 3112cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 3113adfc5217SJeff Kirsher 31143521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 31153521b419SYuval Mintz return BNX2X_PRI_FLAG_LEN; 31163521b419SYuval Mintz 3117adfc5217SJeff Kirsher default: 3118adfc5217SJeff Kirsher return -EINVAL; 3119adfc5217SJeff Kirsher } 3120adfc5217SJeff Kirsher } 3121adfc5217SJeff Kirsher 31223521b419SYuval Mintz static u32 bnx2x_get_private_flags(struct net_device *dev) 31233521b419SYuval Mintz { 31243521b419SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 31253521b419SYuval Mintz u32 flags = 0; 31263521b419SYuval Mintz 31273521b419SYuval Mintz flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 31283521b419SYuval Mintz flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 31293521b419SYuval Mintz flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 31303521b419SYuval Mintz 31313521b419SYuval Mintz return flags; 31323521b419SYuval Mintz } 31333521b419SYuval Mintz 3134adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3135adfc5217SJeff Kirsher { 3136adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 31375889335cSMerav Sicron int i, j, k, start; 3138adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 3139adfc5217SJeff Kirsher 3140adfc5217SJeff Kirsher switch (stringset) { 3141adfc5217SJeff Kirsher case ETH_SS_STATS: 3142adfc5217SJeff Kirsher k = 0; 3143d5e83632SYuval Mintz if (is_multi(bp)) { 3144adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 3145adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 3146adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 3147adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3148adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3149adfc5217SJeff Kirsher ETH_GSTRING_LEN, 3150adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 3151adfc5217SJeff Kirsher queue_name); 3152adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3153adfc5217SJeff Kirsher } 3154d5e83632SYuval Mintz } 3155d5e83632SYuval Mintz 3156adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3157d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3158adfc5217SJeff Kirsher continue; 3159d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3160adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 3161adfc5217SJeff Kirsher j++; 3162adfc5217SJeff Kirsher } 3163d5e83632SYuval Mintz 3164adfc5217SJeff Kirsher break; 3165adfc5217SJeff Kirsher 3166adfc5217SJeff Kirsher case ETH_SS_TEST: 3167cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 3168cf2c1df6SMerav Sicron if (!IS_MF(bp)) 3169cf2c1df6SMerav Sicron start = 0; 3170cf2c1df6SMerav Sicron else 3171cf2c1df6SMerav Sicron start = 4; 31725889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 31735889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 31743521b419SYuval Mintz break; 31753521b419SYuval Mintz 31763521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 31773521b419SYuval Mintz memcpy(buf, bnx2x_private_arr, 31783521b419SYuval Mintz ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 31793521b419SYuval Mintz break; 3180adfc5217SJeff Kirsher } 3181adfc5217SJeff Kirsher } 3182adfc5217SJeff Kirsher 3183adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 3184adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 3185adfc5217SJeff Kirsher { 3186adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3187adfc5217SJeff Kirsher u32 *hw_stats, *offset; 3188d5e83632SYuval Mintz int i, j, k = 0; 3189adfc5217SJeff Kirsher 3190adfc5217SJeff Kirsher if (is_multi(bp)) { 3191adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 319215192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3193adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3194adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 3195adfc5217SJeff Kirsher /* skip this counter */ 3196adfc5217SJeff Kirsher buf[k + j] = 0; 3197adfc5217SJeff Kirsher continue; 3198adfc5217SJeff Kirsher } 3199adfc5217SJeff Kirsher offset = (hw_stats + 3200adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 3201adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 3202adfc5217SJeff Kirsher /* 4-byte counter */ 3203adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 3204adfc5217SJeff Kirsher continue; 3205adfc5217SJeff Kirsher } 3206adfc5217SJeff Kirsher /* 8-byte counter */ 3207adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3208adfc5217SJeff Kirsher } 3209adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3210adfc5217SJeff Kirsher } 3211adfc5217SJeff Kirsher } 3212d5e83632SYuval Mintz 3213adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 3214adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3215d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3216adfc5217SJeff Kirsher continue; 3217adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 3218adfc5217SJeff Kirsher /* skip this counter */ 3219d5e83632SYuval Mintz buf[k + j] = 0; 3220adfc5217SJeff Kirsher j++; 3221adfc5217SJeff Kirsher continue; 3222adfc5217SJeff Kirsher } 3223adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 3224adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 3225adfc5217SJeff Kirsher /* 4-byte counter */ 3226d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 3227adfc5217SJeff Kirsher j++; 3228adfc5217SJeff Kirsher continue; 3229adfc5217SJeff Kirsher } 3230adfc5217SJeff Kirsher /* 8-byte counter */ 3231d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3232adfc5217SJeff Kirsher j++; 3233adfc5217SJeff Kirsher } 3234adfc5217SJeff Kirsher } 3235adfc5217SJeff Kirsher 3236adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 3237adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 3238adfc5217SJeff Kirsher { 3239adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3240adfc5217SJeff Kirsher 32413fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 324251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 324351c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 3244adfc5217SJeff Kirsher return -EAGAIN; 324551c1a580SMerav Sicron } 3246adfc5217SJeff Kirsher 3247adfc5217SJeff Kirsher switch (state) { 3248adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 3249adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 3250adfc5217SJeff Kirsher 3251adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 32528203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3253adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3254adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 32558203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3256adfc5217SJeff Kirsher break; 3257adfc5217SJeff Kirsher 3258adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 32598203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3260adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3261adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 32628203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3263adfc5217SJeff Kirsher break; 3264adfc5217SJeff Kirsher 3265adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 32668203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3267adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3268adfc5217SJeff Kirsher LED_MODE_OPER, 3269adfc5217SJeff Kirsher bp->link_vars.line_speed); 32708203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3271adfc5217SJeff Kirsher } 3272adfc5217SJeff Kirsher 3273adfc5217SJeff Kirsher return 0; 3274adfc5217SJeff Kirsher } 3275adfc5217SJeff Kirsher 32765d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 32775d317c6aSMerav Sicron { 32785d317c6aSMerav Sicron switch (info->flow_type) { 32795d317c6aSMerav Sicron case TCP_V4_FLOW: 32805d317c6aSMerav Sicron case TCP_V6_FLOW: 32815d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32825d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32835d317c6aSMerav Sicron break; 32845d317c6aSMerav Sicron case UDP_V4_FLOW: 32855d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 32865d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32875d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32885d317c6aSMerav Sicron else 32895d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32905d317c6aSMerav Sicron break; 32915d317c6aSMerav Sicron case UDP_V6_FLOW: 32925d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 32935d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32945d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32955d317c6aSMerav Sicron else 32965d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32975d317c6aSMerav Sicron break; 32985d317c6aSMerav Sicron case IPV4_FLOW: 32995d317c6aSMerav Sicron case IPV6_FLOW: 33005d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 33015d317c6aSMerav Sicron break; 33025d317c6aSMerav Sicron default: 33035d317c6aSMerav Sicron info->data = 0; 33045d317c6aSMerav Sicron break; 33055d317c6aSMerav Sicron } 33065d317c6aSMerav Sicron 33075d317c6aSMerav Sicron return 0; 33085d317c6aSMerav Sicron } 33095d317c6aSMerav Sicron 3310adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3311815c7db5SBen Hutchings u32 *rules __always_unused) 3312adfc5217SJeff Kirsher { 3313adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3314adfc5217SJeff Kirsher 3315adfc5217SJeff Kirsher switch (info->cmd) { 3316adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 3317adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 3318adfc5217SJeff Kirsher return 0; 33195d317c6aSMerav Sicron case ETHTOOL_GRXFH: 33205d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 33215d317c6aSMerav Sicron default: 33225d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 33235d317c6aSMerav Sicron return -EOPNOTSUPP; 33245d317c6aSMerav Sicron } 33255d317c6aSMerav Sicron } 3326adfc5217SJeff Kirsher 33275d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 33285d317c6aSMerav Sicron { 33295d317c6aSMerav Sicron int udp_rss_requested; 33305d317c6aSMerav Sicron 33315d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33325d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 33335d317c6aSMerav Sicron info->flow_type, info->data); 33345d317c6aSMerav Sicron 33355d317c6aSMerav Sicron switch (info->flow_type) { 33365d317c6aSMerav Sicron case TCP_V4_FLOW: 33375d317c6aSMerav Sicron case TCP_V6_FLOW: 33385d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 33395d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 33405d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 33415d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33425d317c6aSMerav Sicron "Command parameters not supported\n"); 33435d317c6aSMerav Sicron return -EINVAL; 33445d317c6aSMerav Sicron } 33452de67439SYuval Mintz return 0; 33465d317c6aSMerav Sicron 33475d317c6aSMerav Sicron case UDP_V4_FLOW: 33485d317c6aSMerav Sicron case UDP_V6_FLOW: 33495d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 33505d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 33515d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 33525d317c6aSMerav Sicron udp_rss_requested = 1; 33535d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 33545d317c6aSMerav Sicron udp_rss_requested = 0; 33555d317c6aSMerav Sicron else 33565d317c6aSMerav Sicron return -EINVAL; 3357f9468e8dSYuval Mintz 3358f9468e8dSYuval Mintz if (CHIP_IS_E1x(bp) && udp_rss_requested) { 3359f9468e8dSYuval Mintz DP(BNX2X_MSG_ETHTOOL, 3360f9468e8dSYuval Mintz "57710, 57711 boards don't support RSS according to UDP 4-tuple\n"); 3361f9468e8dSYuval Mintz return -EINVAL; 3362f9468e8dSYuval Mintz } 3363f9468e8dSYuval Mintz 33645d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 33655d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 33665d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 33675d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33685d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 33695d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 337060cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 33715d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 33725d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 33735d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 33745d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33755d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 33765d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 337760cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 33785d317c6aSMerav Sicron } 3379924d75abSYuval Mintz return 0; 3380924d75abSYuval Mintz 33815d317c6aSMerav Sicron case IPV4_FLOW: 33825d317c6aSMerav Sicron case IPV6_FLOW: 33835d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 33845d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 33855d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33865d317c6aSMerav Sicron "Command parameters not supported\n"); 33875d317c6aSMerav Sicron return -EINVAL; 33885d317c6aSMerav Sicron } 3389924d75abSYuval Mintz return 0; 3390924d75abSYuval Mintz 33915d317c6aSMerav Sicron case SCTP_V4_FLOW: 33925d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 33935d317c6aSMerav Sicron case AH_V4_FLOW: 33945d317c6aSMerav Sicron case ESP_V4_FLOW: 33955d317c6aSMerav Sicron case SCTP_V6_FLOW: 33965d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 33975d317c6aSMerav Sicron case AH_V6_FLOW: 33985d317c6aSMerav Sicron case ESP_V6_FLOW: 33995d317c6aSMerav Sicron case IP_USER_FLOW: 34005d317c6aSMerav Sicron case ETHER_FLOW: 34015d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 34025d317c6aSMerav Sicron if (info->data) { 34035d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34045d317c6aSMerav Sicron "Command parameters not supported\n"); 34055d317c6aSMerav Sicron return -EINVAL; 34065d317c6aSMerav Sicron } 3407924d75abSYuval Mintz return 0; 3408924d75abSYuval Mintz 34095d317c6aSMerav Sicron default: 34105d317c6aSMerav Sicron return -EINVAL; 34115d317c6aSMerav Sicron } 34125d317c6aSMerav Sicron } 34135d317c6aSMerav Sicron 34145d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 34155d317c6aSMerav Sicron { 34165d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34175d317c6aSMerav Sicron 34185d317c6aSMerav Sicron switch (info->cmd) { 34195d317c6aSMerav Sicron case ETHTOOL_SRXFH: 34205d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 3421adfc5217SJeff Kirsher default: 342251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3423adfc5217SJeff Kirsher return -EOPNOTSUPP; 3424adfc5217SJeff Kirsher } 3425adfc5217SJeff Kirsher } 3426adfc5217SJeff Kirsher 34277850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3428adfc5217SJeff Kirsher { 342996305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 34307850f63fSBen Hutchings } 34317850f63fSBen Hutchings 3432892311f6SEyal Perry static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3433892311f6SEyal Perry u8 *hfunc) 34347850f63fSBen Hutchings { 34357850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 3436adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3437adfc5217SJeff Kirsher size_t i; 3438adfc5217SJeff Kirsher 3439892311f6SEyal Perry if (hfunc) 3440892311f6SEyal Perry *hfunc = ETH_RSS_HASH_TOP; 3441892311f6SEyal Perry if (!indir) 3442892311f6SEyal Perry return 0; 3443892311f6SEyal Perry 3444adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 3445adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3446adfc5217SJeff Kirsher 3447adfc5217SJeff Kirsher /* 3448adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 3449adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 3450adfc5217SJeff Kirsher * points to an array of u32. 3451adfc5217SJeff Kirsher * 3452adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3453adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 3454adfc5217SJeff Kirsher * queue. 3455adfc5217SJeff Kirsher */ 34567850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 34577850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 3458adfc5217SJeff Kirsher 3459adfc5217SJeff Kirsher return 0; 3460adfc5217SJeff Kirsher } 3461adfc5217SJeff Kirsher 3462fe62d001SBen Hutchings static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3463892311f6SEyal Perry const u8 *key, const u8 hfunc) 3464adfc5217SJeff Kirsher { 3465adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3466adfc5217SJeff Kirsher size_t i; 3467adfc5217SJeff Kirsher 3468892311f6SEyal Perry /* We require at least one supported parameter to be changed and no 3469892311f6SEyal Perry * change in any of the unsupported parameters 3470892311f6SEyal Perry */ 3471892311f6SEyal Perry if (key || 3472892311f6SEyal Perry (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3473892311f6SEyal Perry return -EOPNOTSUPP; 3474892311f6SEyal Perry 3475892311f6SEyal Perry if (!indir) 3476892311f6SEyal Perry return 0; 3477892311f6SEyal Perry 3478adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3479adfc5217SJeff Kirsher /* 3480fe62d001SBen Hutchings * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3481adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 3482adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 3483adfc5217SJeff Kirsher * 3484adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3485adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 3486adfc5217SJeff Kirsher * queue 3487adfc5217SJeff Kirsher */ 34885d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3489adfc5217SJeff Kirsher } 3490adfc5217SJeff Kirsher 34915d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 3492adfc5217SJeff Kirsher } 3493adfc5217SJeff Kirsher 34940e8d2ec5SMerav Sicron /** 34950e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 34960e8d2ec5SMerav Sicron * 34970e8d2ec5SMerav Sicron * @dev: net device 34980e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 34990e8d2ec5SMerav Sicron */ 35000e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 35010e8d2ec5SMerav Sicron struct ethtool_channels *channels) 35020e8d2ec5SMerav Sicron { 35030e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 35040e8d2ec5SMerav Sicron 35050e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 35060e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 35070e8d2ec5SMerav Sicron } 35080e8d2ec5SMerav Sicron 35090e8d2ec5SMerav Sicron /** 35100e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 35110e8d2ec5SMerav Sicron * 35120e8d2ec5SMerav Sicron * @bp: bnx2x private structure 35130e8d2ec5SMerav Sicron * 35140e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 35150e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 35160e8d2ec5SMerav Sicron */ 35170e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 35180e8d2ec5SMerav Sicron { 35190e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 352055c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 352155c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 352255c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 35230e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 35240e8d2ec5SMerav Sicron } 35250e8d2ec5SMerav Sicron 35260e8d2ec5SMerav Sicron /** 35270e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 35280e8d2ec5SMerav Sicron * 35290e8d2ec5SMerav Sicron * @dev: net device 35300e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 35310e8d2ec5SMerav Sicron */ 35320e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 35330e8d2ec5SMerav Sicron struct ethtool_channels *channels) 35340e8d2ec5SMerav Sicron { 35350e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 35360e8d2ec5SMerav Sicron 35370e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 35380e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 35390e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 35400e8d2ec5SMerav Sicron channels->combined_count); 35410e8d2ec5SMerav Sicron 3542909d9faaSYuval Mintz if (pci_num_vf(bp->pdev)) { 3543909d9faaSYuval Mintz DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3544909d9faaSYuval Mintz return -EPERM; 3545909d9faaSYuval Mintz } 3546909d9faaSYuval Mintz 35470e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 35480e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 35490e8d2ec5SMerav Sicron */ 35500e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 35510e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 35520e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 35530e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 35540e8d2ec5SMerav Sicron return -EINVAL; 35550e8d2ec5SMerav Sicron } 35560e8d2ec5SMerav Sicron 35570e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 35580e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 35590e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 35600e8d2ec5SMerav Sicron return 0; 35610e8d2ec5SMerav Sicron } 35620e8d2ec5SMerav Sicron 35630e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 35640e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 35650e8d2ec5SMerav Sicron * less than requested if memory is low. 35660e8d2ec5SMerav Sicron */ 35670e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 35680e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 35690e8d2ec5SMerav Sicron return 0; 35700e8d2ec5SMerav Sicron } 35715d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 35720e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 35730e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 35740e8d2ec5SMerav Sicron } 35750e8d2ec5SMerav Sicron 3576eeed018cSMichal Kalderon static int bnx2x_get_ts_info(struct net_device *dev, 3577eeed018cSMichal Kalderon struct ethtool_ts_info *info) 3578eeed018cSMichal Kalderon { 3579eeed018cSMichal Kalderon struct bnx2x *bp = netdev_priv(dev); 3580eeed018cSMichal Kalderon 3581eeed018cSMichal Kalderon if (bp->flags & PTP_SUPPORTED) { 3582eeed018cSMichal Kalderon info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3583eeed018cSMichal Kalderon SOF_TIMESTAMPING_RX_SOFTWARE | 3584eeed018cSMichal Kalderon SOF_TIMESTAMPING_SOFTWARE | 3585eeed018cSMichal Kalderon SOF_TIMESTAMPING_TX_HARDWARE | 3586eeed018cSMichal Kalderon SOF_TIMESTAMPING_RX_HARDWARE | 3587eeed018cSMichal Kalderon SOF_TIMESTAMPING_RAW_HARDWARE; 3588eeed018cSMichal Kalderon 3589eeed018cSMichal Kalderon if (bp->ptp_clock) 3590eeed018cSMichal Kalderon info->phc_index = ptp_clock_index(bp->ptp_clock); 3591eeed018cSMichal Kalderon else 3592eeed018cSMichal Kalderon info->phc_index = -1; 3593eeed018cSMichal Kalderon 3594eeed018cSMichal Kalderon info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3595eeed018cSMichal Kalderon (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3596eeed018cSMichal Kalderon (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3597dd3950c6SJacob Keller (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3598eeed018cSMichal Kalderon 3599eeed018cSMichal Kalderon info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3600eeed018cSMichal Kalderon 3601eeed018cSMichal Kalderon return 0; 3602eeed018cSMichal Kalderon } 3603eeed018cSMichal Kalderon 3604eeed018cSMichal Kalderon return ethtool_op_get_ts_info(dev, info); 3605eeed018cSMichal Kalderon } 3606eeed018cSMichal Kalderon 3607adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 3608adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 3609adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 3610adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 3611adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 3612adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 361307ba6af4SMiriam Shitrit .get_dump_flag = bnx2x_get_dump_flag, 361407ba6af4SMiriam Shitrit .get_dump_data = bnx2x_get_dump_data, 361507ba6af4SMiriam Shitrit .set_dump = bnx2x_set_dump, 3616adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 3617adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 3618adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 3619adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 3620adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 3621adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 3622adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 3623adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 3624adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 3625adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 3626adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 3627adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 3628adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 3629adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 3630adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 3631adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 3632adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 36333521b419SYuval Mintz .get_priv_flags = bnx2x_get_private_flags, 3634adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 3635adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 3636adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 3637adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 36385d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 36397850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3640fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3641fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 36420e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 36430e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 364424ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 364524ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3646e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3647e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3648eeed018cSMichal Kalderon .get_ts_info = bnx2x_get_ts_info, 3649adfc5217SJeff Kirsher }; 3650adfc5217SJeff Kirsher 3651005a07baSAriel Elior static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 36526495d15aSDmitry Kravkov .get_settings = bnx2x_get_vf_settings, 3653005a07baSAriel Elior .get_drvinfo = bnx2x_get_drvinfo, 3654005a07baSAriel Elior .get_msglevel = bnx2x_get_msglevel, 3655005a07baSAriel Elior .set_msglevel = bnx2x_set_msglevel, 3656005a07baSAriel Elior .get_link = bnx2x_get_link, 3657005a07baSAriel Elior .get_coalesce = bnx2x_get_coalesce, 3658005a07baSAriel Elior .get_ringparam = bnx2x_get_ringparam, 3659005a07baSAriel Elior .set_ringparam = bnx2x_set_ringparam, 3660005a07baSAriel Elior .get_sset_count = bnx2x_get_sset_count, 3661005a07baSAriel Elior .get_strings = bnx2x_get_strings, 3662005a07baSAriel Elior .get_ethtool_stats = bnx2x_get_ethtool_stats, 3663005a07baSAriel Elior .get_rxnfc = bnx2x_get_rxnfc, 3664005a07baSAriel Elior .set_rxnfc = bnx2x_set_rxnfc, 3665005a07baSAriel Elior .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3666fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3667fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 3668005a07baSAriel Elior .get_channels = bnx2x_get_channels, 3669005a07baSAriel Elior .set_channels = bnx2x_set_channels, 3670005a07baSAriel Elior }; 3671005a07baSAriel Elior 3672005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3673adfc5217SJeff Kirsher { 36747ad24ea4SWilfried Klaebe netdev->ethtool_ops = (IS_PF(bp)) ? 36757ad24ea4SWilfried Klaebe &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3676adfc5217SJeff Kirsher } 3677