1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 908f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher #include "bnx2x.h" 26adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 27adfc5217SJeff Kirsher #include "bnx2x_dump.h" 28adfc5217SJeff Kirsher #include "bnx2x_init.h" 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 31adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33adfc5217SJeff Kirsher */ 34adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 35adfc5217SJeff Kirsher static const struct { 36adfc5217SJeff Kirsher long offset; 37adfc5217SJeff Kirsher int size; 38adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 39adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 40adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 49adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53adfc5217SJeff Kirsher 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 65c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 68adfc5217SJeff Kirsher }; 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher static const struct { 73adfc5217SJeff Kirsher long offset; 74adfc5217SJeff Kirsher int size; 75adfc5217SJeff Kirsher u32 flags; 76adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 77adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 78adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 80adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 81adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 101adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 104adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 106adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 108adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1090e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1100e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1110e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1120e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 114adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 122adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 128adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129adfc5217SJeff Kirsher 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 131adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1777a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1797a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1817a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 183c96bdc0cSDmitry Kravkov 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 185e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 18907ba6af4SMiriam Shitrit 190adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 191adfc5217SJeff Kirsher { 192adfc5217SJeff Kirsher int port_type; 193adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 195dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 196dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 198adfc5217SJeff Kirsher case ETH_PHY_KR: 199adfc5217SJeff Kirsher case ETH_PHY_CX4: 200adfc5217SJeff Kirsher port_type = PORT_FIBRE; 201adfc5217SJeff Kirsher break; 202adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 203adfc5217SJeff Kirsher port_type = PORT_DA; 204adfc5217SJeff Kirsher break; 205adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 206adfc5217SJeff Kirsher port_type = PORT_TP; 207adfc5217SJeff Kirsher break; 208adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 209adfc5217SJeff Kirsher port_type = PORT_NONE; 210adfc5217SJeff Kirsher break; 211adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 212adfc5217SJeff Kirsher default: 213adfc5217SJeff Kirsher port_type = PORT_OTHER; 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher return port_type; 217adfc5217SJeff Kirsher } 218adfc5217SJeff Kirsher 2196495d15aSDmitry Kravkov static int bnx2x_get_vf_settings(struct net_device *dev, 2206495d15aSDmitry Kravkov struct ethtool_cmd *cmd) 2216495d15aSDmitry Kravkov { 2226495d15aSDmitry Kravkov struct bnx2x *bp = netdev_priv(dev); 2236495d15aSDmitry Kravkov 2246495d15aSDmitry Kravkov if (bp->state == BNX2X_STATE_OPEN) { 2256495d15aSDmitry Kravkov if (test_bit(BNX2X_LINK_REPORT_FD, 2266495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags)) 2276495d15aSDmitry Kravkov cmd->duplex = DUPLEX_FULL; 2286495d15aSDmitry Kravkov else 2296495d15aSDmitry Kravkov cmd->duplex = DUPLEX_HALF; 2306495d15aSDmitry Kravkov 2316495d15aSDmitry Kravkov ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed); 2326495d15aSDmitry Kravkov } else { 2336495d15aSDmitry Kravkov cmd->duplex = DUPLEX_UNKNOWN; 2346495d15aSDmitry Kravkov ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 2356495d15aSDmitry Kravkov } 2366495d15aSDmitry Kravkov 2376495d15aSDmitry Kravkov cmd->port = PORT_OTHER; 2386495d15aSDmitry Kravkov cmd->phy_address = 0; 2396495d15aSDmitry Kravkov cmd->transceiver = XCVR_INTERNAL; 2406495d15aSDmitry Kravkov cmd->autoneg = AUTONEG_DISABLE; 2416495d15aSDmitry Kravkov cmd->maxtxpkt = 0; 2426495d15aSDmitry Kravkov cmd->maxrxpkt = 0; 2436495d15aSDmitry Kravkov 2446495d15aSDmitry Kravkov DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 2456495d15aSDmitry Kravkov " supported 0x%x advertising 0x%x speed %u\n" 2466495d15aSDmitry Kravkov " duplex %d port %d phy_address %d transceiver %d\n" 2476495d15aSDmitry Kravkov " autoneg %d maxtxpkt %d maxrxpkt %d\n", 2486495d15aSDmitry Kravkov cmd->cmd, cmd->supported, cmd->advertising, 2496495d15aSDmitry Kravkov ethtool_cmd_speed(cmd), 2506495d15aSDmitry Kravkov cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 2516495d15aSDmitry Kravkov cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 2526495d15aSDmitry Kravkov 2536495d15aSDmitry Kravkov return 0; 2546495d15aSDmitry Kravkov } 2556495d15aSDmitry Kravkov 256adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 257adfc5217SJeff Kirsher { 258adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 259adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 260adfc5217SJeff Kirsher 261adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 262adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 263adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 264adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 265adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 266dbef807eSYuval Mintz if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 267dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER) { 268dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 269dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 270dbef807eSYuval Mintz } 271adfc5217SJeff Kirsher 27259694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 27359694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 274adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 275adfc5217SJeff Kirsher 27638298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 277adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 27859694f00SYuval Mintz else 27959694f00SYuval Mintz ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 28038298461SYuval Mintz } else { 28138298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 28238298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 28338298461SYuval Mintz } 284adfc5217SJeff Kirsher 285adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 286adfc5217SJeff Kirsher 287adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 288adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 289adfc5217SJeff Kirsher 290adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 291adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 292adfc5217SJeff Kirsher else 293adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 294adfc5217SJeff Kirsher 2959e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2969e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2979e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2989e7e8399SMintz Yuval 2999e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 3009e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 3019e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 3029e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 3039e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 3049e7e8399SMintz Yuval 3059e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 3069e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 3079e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 3089e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 3099e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 3109e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 3119e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 3129e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 3139e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 3149e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 3159e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 3169e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 3179e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 3189e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 3199e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 3209e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 321be94bea7SYaniv Rosner if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 322be94bea7SYaniv Rosner cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 3239e7e8399SMintz Yuval } 3249e7e8399SMintz Yuval 325adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 326adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 327adfc5217SJeff Kirsher 32851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 329f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 330f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 331f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 332adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 333adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 334adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 335adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 336adfc5217SJeff Kirsher 337adfc5217SJeff Kirsher return 0; 338adfc5217SJeff Kirsher } 339adfc5217SJeff Kirsher 340adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 341adfc5217SJeff Kirsher { 342adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 343adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 344dbef807eSYuval Mintz u32 speed, phy_idx; 345adfc5217SJeff Kirsher 346adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 347adfc5217SJeff Kirsher return 0; 348adfc5217SJeff Kirsher 34951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 350adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 351adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 352adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 353adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 354adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 355adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 356adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 357adfc5217SJeff Kirsher 358adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 359adfc5217SJeff Kirsher 36016a5fd92SYuval Mintz /* If received a request for an unknown duplex, assume full*/ 36138298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 36238298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 36338298461SYuval Mintz 364adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 365adfc5217SJeff Kirsher u32 part; 366adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 367adfc5217SJeff Kirsher 368adfc5217SJeff Kirsher /* use 10G if no link detected */ 369adfc5217SJeff Kirsher if (!line_speed) 370adfc5217SJeff Kirsher line_speed = 10000; 371adfc5217SJeff Kirsher 372adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 37351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 37451c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 375adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 376adfc5217SJeff Kirsher return -EINVAL; 377adfc5217SJeff Kirsher } 378adfc5217SJeff Kirsher 379adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 380adfc5217SJeff Kirsher 381adfc5217SJeff Kirsher if (line_speed < speed || !part) { 38251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 38351c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 384adfc5217SJeff Kirsher return -EINVAL; 385adfc5217SJeff Kirsher } 386adfc5217SJeff Kirsher 387adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 388adfc5217SJeff Kirsher /* store value for following "load" */ 389adfc5217SJeff Kirsher bp->pending_max = part; 390adfc5217SJeff Kirsher else 391adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 392adfc5217SJeff Kirsher 393adfc5217SJeff Kirsher return 0; 394adfc5217SJeff Kirsher } 395adfc5217SJeff Kirsher 396adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 397adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 39833f9e6f5SYaniv Rosner if (cmd->port != bnx2x_get_port_type(bp)) { 399adfc5217SJeff Kirsher switch (cmd->port) { 400adfc5217SJeff Kirsher case PORT_TP: 401adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 402adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 40333f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 40433f9e6f5SYaniv Rosner "Unsupported port type\n"); 405adfc5217SJeff Kirsher return -EINVAL; 406adfc5217SJeff Kirsher } 407adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 408adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 409adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 410adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 411adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 412adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 413adfc5217SJeff Kirsher else 414adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 415adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 416adfc5217SJeff Kirsher break; 417adfc5217SJeff Kirsher case PORT_FIBRE: 418bfdb5823SYaniv Rosner case PORT_DA: 419adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 420adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 42133f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 42233f9e6f5SYaniv Rosner "Unsupported port type\n"); 423adfc5217SJeff Kirsher return -EINVAL; 424adfc5217SJeff Kirsher } 425adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 426adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 427adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 428adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 429adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 430adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 431adfc5217SJeff Kirsher else 432adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 433adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 434adfc5217SJeff Kirsher break; 435adfc5217SJeff Kirsher default: 43651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 437adfc5217SJeff Kirsher return -EINVAL; 438adfc5217SJeff Kirsher } 43933f9e6f5SYaniv Rosner } 4402de67439SYuval Mintz /* Save new config in case command complete successfully */ 441adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 442adfc5217SJeff Kirsher /* Get the new cfg_idx */ 443adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 444adfc5217SJeff Kirsher /* Restore old config in case command failed */ 445adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 44651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 447adfc5217SJeff Kirsher 448adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 44975318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 45075318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 45175318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 45275318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 45375318327SYaniv Rosner SUPPORTED_100baseT_Full); 454adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 45551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 456adfc5217SJeff Kirsher return -EINVAL; 457adfc5217SJeff Kirsher } 458adfc5217SJeff Kirsher 459adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 46075318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 46151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 46251c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4638decf868SDavid S. Miller return -EINVAL; 4648decf868SDavid S. Miller } 465adfc5217SJeff Kirsher 466adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4678decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4688decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 469adfc5217SJeff Kirsher cmd->advertising); 4708decf868SDavid S. Miller if (cmd->advertising) { 471adfc5217SJeff Kirsher 4728decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4738decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4748decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4758decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4768decf868SDavid S. Miller } 4778decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4788decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4798decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4808decf868SDavid S. Miller 4818decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4828decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4838decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4848decf868SDavid S. Miller 4858decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4868decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4878decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4888decf868SDavid S. Miller } 4898decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4908decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4918decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4928decf868SDavid S. Miller } 4938decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4948decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4958decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4968decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4978decf868SDavid S. Miller 4988decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4998decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 5008decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 5018decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 5028decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 503be94bea7SYaniv Rosner 504be94bea7SYaniv Rosner if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 505be94bea7SYaniv Rosner bp->link_params.speed_cap_mask[cfg_idx] |= 506be94bea7SYaniv Rosner PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 5078decf868SDavid S. Miller } 508adfc5217SJeff Kirsher } else { /* forced speed */ 509adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 510adfc5217SJeff Kirsher switch (speed) { 511adfc5217SJeff Kirsher case SPEED_10: 512adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 513adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 514adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 51551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 516adfc5217SJeff Kirsher "10M full not supported\n"); 517adfc5217SJeff Kirsher return -EINVAL; 518adfc5217SJeff Kirsher } 519adfc5217SJeff Kirsher 520adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 521adfc5217SJeff Kirsher ADVERTISED_TP); 522adfc5217SJeff Kirsher } else { 523adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 524adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 52551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 526adfc5217SJeff Kirsher "10M half not supported\n"); 527adfc5217SJeff Kirsher return -EINVAL; 528adfc5217SJeff Kirsher } 529adfc5217SJeff Kirsher 530adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 531adfc5217SJeff Kirsher ADVERTISED_TP); 532adfc5217SJeff Kirsher } 533adfc5217SJeff Kirsher break; 534adfc5217SJeff Kirsher 535adfc5217SJeff Kirsher case SPEED_100: 536adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 537adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 538adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 53951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 540adfc5217SJeff Kirsher "100M full not supported\n"); 541adfc5217SJeff Kirsher return -EINVAL; 542adfc5217SJeff Kirsher } 543adfc5217SJeff Kirsher 544adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 545adfc5217SJeff Kirsher ADVERTISED_TP); 546adfc5217SJeff Kirsher } else { 547adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 548adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 54951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 550adfc5217SJeff Kirsher "100M half not supported\n"); 551adfc5217SJeff Kirsher return -EINVAL; 552adfc5217SJeff Kirsher } 553adfc5217SJeff Kirsher 554adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 555adfc5217SJeff Kirsher ADVERTISED_TP); 556adfc5217SJeff Kirsher } 557adfc5217SJeff Kirsher break; 558adfc5217SJeff Kirsher 559adfc5217SJeff Kirsher case SPEED_1000: 560adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 56151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56251c1a580SMerav Sicron "1G half not supported\n"); 563adfc5217SJeff Kirsher return -EINVAL; 564adfc5217SJeff Kirsher } 565adfc5217SJeff Kirsher 566adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 567adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 56851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56951c1a580SMerav Sicron "1G full not supported\n"); 570adfc5217SJeff Kirsher return -EINVAL; 571adfc5217SJeff Kirsher } 572adfc5217SJeff Kirsher 573adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 574adfc5217SJeff Kirsher ADVERTISED_TP); 575adfc5217SJeff Kirsher break; 576adfc5217SJeff Kirsher 577adfc5217SJeff Kirsher case SPEED_2500: 578adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 57951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 580adfc5217SJeff Kirsher "2.5G half not supported\n"); 581adfc5217SJeff Kirsher return -EINVAL; 582adfc5217SJeff Kirsher } 583adfc5217SJeff Kirsher 584adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 585adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 58651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 587adfc5217SJeff Kirsher "2.5G full not supported\n"); 588adfc5217SJeff Kirsher return -EINVAL; 589adfc5217SJeff Kirsher } 590adfc5217SJeff Kirsher 591adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 592adfc5217SJeff Kirsher ADVERTISED_TP); 593adfc5217SJeff Kirsher break; 594adfc5217SJeff Kirsher 595adfc5217SJeff Kirsher case SPEED_10000: 596adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 59751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 59851c1a580SMerav Sicron "10G half not supported\n"); 599adfc5217SJeff Kirsher return -EINVAL; 600adfc5217SJeff Kirsher } 601dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 602adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 603dbef807eSYuval Mintz & SUPPORTED_10000baseT_Full) || 604dbef807eSYuval Mintz (bp->link_params.phy[phy_idx].media_type == 605dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 60651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 60751c1a580SMerav Sicron "10G full not supported\n"); 608adfc5217SJeff Kirsher return -EINVAL; 609adfc5217SJeff Kirsher } 610adfc5217SJeff Kirsher 611adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 612adfc5217SJeff Kirsher ADVERTISED_FIBRE); 613adfc5217SJeff Kirsher break; 614adfc5217SJeff Kirsher 615adfc5217SJeff Kirsher default: 61651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 617adfc5217SJeff Kirsher return -EINVAL; 618adfc5217SJeff Kirsher } 619adfc5217SJeff Kirsher 620adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 621adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 622adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 623adfc5217SJeff Kirsher } 624adfc5217SJeff Kirsher 62551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 626f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 627adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 628adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 629adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 630adfc5217SJeff Kirsher 631adfc5217SJeff Kirsher /* Set new config */ 632adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 633adfc5217SJeff Kirsher if (netif_running(dev)) { 634adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 635adfc5217SJeff Kirsher bnx2x_link_set(bp); 636adfc5217SJeff Kirsher } 637adfc5217SJeff Kirsher 638adfc5217SJeff Kirsher return 0; 639adfc5217SJeff Kirsher } 640adfc5217SJeff Kirsher 64107ba6af4SMiriam Shitrit #define DUMP_ALL_PRESETS 0x1FFF 64207ba6af4SMiriam Shitrit #define DUMP_MAX_PRESETS 13 643adfc5217SJeff Kirsher 64407ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 645adfc5217SJeff Kirsher { 646adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 64707ba6af4SMiriam Shitrit return dump_num_registers[0][preset-1]; 648adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 64907ba6af4SMiriam Shitrit return dump_num_registers[1][preset-1]; 650adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 65107ba6af4SMiriam Shitrit return dump_num_registers[2][preset-1]; 652adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 65307ba6af4SMiriam Shitrit return dump_num_registers[3][preset-1]; 654adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 65507ba6af4SMiriam Shitrit return dump_num_registers[4][preset-1]; 656adfc5217SJeff Kirsher else 65707ba6af4SMiriam Shitrit return 0; 658adfc5217SJeff Kirsher } 659adfc5217SJeff Kirsher 66007ba6af4SMiriam Shitrit static int __bnx2x_get_regs_len(struct bnx2x *bp) 66107ba6af4SMiriam Shitrit { 66207ba6af4SMiriam Shitrit u32 preset_idx; 66307ba6af4SMiriam Shitrit int regdump_len = 0; 66407ba6af4SMiriam Shitrit 66507ba6af4SMiriam Shitrit /* Calculate the total preset regs length */ 66607ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 66707ba6af4SMiriam Shitrit regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 66807ba6af4SMiriam Shitrit 66907ba6af4SMiriam Shitrit return regdump_len; 67007ba6af4SMiriam Shitrit } 67107ba6af4SMiriam Shitrit 67207ba6af4SMiriam Shitrit static int bnx2x_get_regs_len(struct net_device *dev) 67307ba6af4SMiriam Shitrit { 67407ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 67507ba6af4SMiriam Shitrit int regdump_len = 0; 67607ba6af4SMiriam Shitrit 67775543741SYuval Mintz if (IS_VF(bp)) 67875543741SYuval Mintz return 0; 67975543741SYuval Mintz 68007ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_regs_len(bp); 68107ba6af4SMiriam Shitrit regdump_len *= 4; 68207ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 68307ba6af4SMiriam Shitrit 68407ba6af4SMiriam Shitrit return regdump_len; 68507ba6af4SMiriam Shitrit } 68607ba6af4SMiriam Shitrit 68707ba6af4SMiriam Shitrit #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 68807ba6af4SMiriam Shitrit #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 68907ba6af4SMiriam Shitrit #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 69007ba6af4SMiriam Shitrit #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 69107ba6af4SMiriam Shitrit #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 69207ba6af4SMiriam Shitrit 69307ba6af4SMiriam Shitrit #define IS_REG_IN_PRESET(presets, idx) \ 69407ba6af4SMiriam Shitrit ((presets & (1 << (idx-1))) == (1 << (idx-1))) 69507ba6af4SMiriam Shitrit 696adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 6971191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 698adfc5217SJeff Kirsher { 699adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 700adfc5217SJeff Kirsher return page_vals_e2; 701adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 702adfc5217SJeff Kirsher return page_vals_e3; 703adfc5217SJeff Kirsher else 704adfc5217SJeff Kirsher return NULL; 705adfc5217SJeff Kirsher } 706adfc5217SJeff Kirsher 7071191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 708adfc5217SJeff Kirsher { 709adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 710adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 711adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 712adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 713adfc5217SJeff Kirsher else 714adfc5217SJeff Kirsher return 0; 715adfc5217SJeff Kirsher } 716adfc5217SJeff Kirsher 7171191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 718adfc5217SJeff Kirsher { 719adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 720adfc5217SJeff Kirsher return page_write_regs_e2; 721adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 722adfc5217SJeff Kirsher return page_write_regs_e3; 723adfc5217SJeff Kirsher else 724adfc5217SJeff Kirsher return NULL; 725adfc5217SJeff Kirsher } 726adfc5217SJeff Kirsher 7271191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 728adfc5217SJeff Kirsher { 729adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 730adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 731adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 732adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 733adfc5217SJeff Kirsher else 734adfc5217SJeff Kirsher return 0; 735adfc5217SJeff Kirsher } 736adfc5217SJeff Kirsher 7371191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 738adfc5217SJeff Kirsher { 739adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 740adfc5217SJeff Kirsher return page_read_regs_e2; 741adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 742adfc5217SJeff Kirsher return page_read_regs_e3; 743adfc5217SJeff Kirsher else 744adfc5217SJeff Kirsher return NULL; 745adfc5217SJeff Kirsher } 746adfc5217SJeff Kirsher 7471191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 748adfc5217SJeff Kirsher { 749adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 750adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 751adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 752adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 753adfc5217SJeff Kirsher else 754adfc5217SJeff Kirsher return 0; 755adfc5217SJeff Kirsher } 756adfc5217SJeff Kirsher 75707ba6af4SMiriam Shitrit static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 75807ba6af4SMiriam Shitrit const struct reg_addr *reg_info) 759adfc5217SJeff Kirsher { 76007ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 76107ba6af4SMiriam Shitrit return IS_E1_REG(reg_info->chips); 76207ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 76307ba6af4SMiriam Shitrit return IS_E1H_REG(reg_info->chips); 76407ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 76507ba6af4SMiriam Shitrit return IS_E2_REG(reg_info->chips); 76607ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 76707ba6af4SMiriam Shitrit return IS_E3A0_REG(reg_info->chips); 76807ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 76907ba6af4SMiriam Shitrit return IS_E3B0_REG(reg_info->chips); 77007ba6af4SMiriam Shitrit else 77107ba6af4SMiriam Shitrit return false; 772adfc5217SJeff Kirsher } 773adfc5217SJeff Kirsher 77407ba6af4SMiriam Shitrit static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 77507ba6af4SMiriam Shitrit const struct wreg_addr *wreg_info) 776adfc5217SJeff Kirsher { 77707ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 77807ba6af4SMiriam Shitrit return IS_E1_REG(wreg_info->chips); 77907ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 78007ba6af4SMiriam Shitrit return IS_E1H_REG(wreg_info->chips); 78107ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 78207ba6af4SMiriam Shitrit return IS_E2_REG(wreg_info->chips); 78307ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 78407ba6af4SMiriam Shitrit return IS_E3A0_REG(wreg_info->chips); 78507ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 78607ba6af4SMiriam Shitrit return IS_E3B0_REG(wreg_info->chips); 78707ba6af4SMiriam Shitrit else 78807ba6af4SMiriam Shitrit return false; 789adfc5217SJeff Kirsher } 790adfc5217SJeff Kirsher 791adfc5217SJeff Kirsher /** 792adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 793adfc5217SJeff Kirsher * 794adfc5217SJeff Kirsher * @bp device handle 795adfc5217SJeff Kirsher * @p output buffer 796adfc5217SJeff Kirsher * 7972de67439SYuval Mintz * Reads "paged" memories: memories that may only be read by first writing to a 7982de67439SYuval Mintz * specific address ("write address") and then reading from a specific address 7992de67439SYuval Mintz * ("read address"). There may be more than one write address per "page" and 8002de67439SYuval Mintz * more than one read address per write address. 801adfc5217SJeff Kirsher */ 80207ba6af4SMiriam Shitrit static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 803adfc5217SJeff Kirsher { 804adfc5217SJeff Kirsher u32 i, j, k, n; 80507ba6af4SMiriam Shitrit 806adfc5217SJeff Kirsher /* addresses of the paged registers */ 807adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 808adfc5217SJeff Kirsher /* number of paged registers */ 809adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 810adfc5217SJeff Kirsher /* write addresses */ 811adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 812adfc5217SJeff Kirsher /* number of write addresses */ 813adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 814adfc5217SJeff Kirsher /* read addresses info */ 815adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 816adfc5217SJeff Kirsher /* number of read addresses */ 817adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 81807ba6af4SMiriam Shitrit u32 addr, size; 819adfc5217SJeff Kirsher 820adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 821adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 822adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 82307ba6af4SMiriam Shitrit 82407ba6af4SMiriam Shitrit for (k = 0; k < read_num; k++) { 82507ba6af4SMiriam Shitrit if (IS_REG_IN_PRESET(read_addr[k].presets, 82607ba6af4SMiriam Shitrit preset)) { 82707ba6af4SMiriam Shitrit size = read_addr[k].size; 82807ba6af4SMiriam Shitrit for (n = 0; n < size; n++) { 82907ba6af4SMiriam Shitrit addr = read_addr[k].addr + n*4; 83007ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr); 831adfc5217SJeff Kirsher } 832adfc5217SJeff Kirsher } 833adfc5217SJeff Kirsher } 83407ba6af4SMiriam Shitrit } 83507ba6af4SMiriam Shitrit } 83607ba6af4SMiriam Shitrit } 83707ba6af4SMiriam Shitrit 83807ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 83907ba6af4SMiriam Shitrit { 84007ba6af4SMiriam Shitrit u32 i, j, addr; 84107ba6af4SMiriam Shitrit const struct wreg_addr *wreg_addr_p = NULL; 84207ba6af4SMiriam Shitrit 84307ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 84407ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1; 84507ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 84607ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1h; 84707ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 84807ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e2; 84907ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 85007ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3; 85107ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 85207ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3b0; 85307ba6af4SMiriam Shitrit 85407ba6af4SMiriam Shitrit /* Read the idle_chk registers */ 85507ba6af4SMiriam Shitrit for (i = 0; i < IDLE_REGS_COUNT; i++) { 85607ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 85707ba6af4SMiriam Shitrit IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 85807ba6af4SMiriam Shitrit for (j = 0; j < idle_reg_addrs[i].size; j++) 85907ba6af4SMiriam Shitrit *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 86007ba6af4SMiriam Shitrit } 86107ba6af4SMiriam Shitrit } 86207ba6af4SMiriam Shitrit 86307ba6af4SMiriam Shitrit /* Read the regular registers */ 86407ba6af4SMiriam Shitrit for (i = 0; i < REGS_COUNT; i++) { 86507ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 86607ba6af4SMiriam Shitrit IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 86707ba6af4SMiriam Shitrit for (j = 0; j < reg_addrs[i].size; j++) 86807ba6af4SMiriam Shitrit *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 86907ba6af4SMiriam Shitrit } 87007ba6af4SMiriam Shitrit } 87107ba6af4SMiriam Shitrit 87207ba6af4SMiriam Shitrit /* Read the CAM registers */ 87307ba6af4SMiriam Shitrit if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 87407ba6af4SMiriam Shitrit IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 87507ba6af4SMiriam Shitrit for (i = 0; i < wreg_addr_p->size; i++) { 87607ba6af4SMiriam Shitrit *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 87707ba6af4SMiriam Shitrit 87807ba6af4SMiriam Shitrit /* In case of wreg_addr register, read additional 87907ba6af4SMiriam Shitrit registers from read_regs array 88007ba6af4SMiriam Shitrit */ 88107ba6af4SMiriam Shitrit for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 88207ba6af4SMiriam Shitrit addr = *(wreg_addr_p->read_regs); 88307ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr + j*4); 88407ba6af4SMiriam Shitrit } 88507ba6af4SMiriam Shitrit } 88607ba6af4SMiriam Shitrit } 88707ba6af4SMiriam Shitrit 88807ba6af4SMiriam Shitrit /* Paged registers are supported in E2 & E3 only */ 88907ba6af4SMiriam Shitrit if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 89016a5fd92SYuval Mintz /* Read "paged" registers */ 89107ba6af4SMiriam Shitrit bnx2x_read_pages_regs(bp, p, preset); 89207ba6af4SMiriam Shitrit } 89307ba6af4SMiriam Shitrit 89407ba6af4SMiriam Shitrit return 0; 89507ba6af4SMiriam Shitrit } 896adfc5217SJeff Kirsher 8971191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 898adfc5217SJeff Kirsher { 89907ba6af4SMiriam Shitrit u32 preset_idx; 900adfc5217SJeff Kirsher 90107ba6af4SMiriam Shitrit /* Read all registers, by reading all preset registers */ 90207ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 90307ba6af4SMiriam Shitrit /* Skip presets with IOR */ 90407ba6af4SMiriam Shitrit if ((preset_idx == 2) || 90507ba6af4SMiriam Shitrit (preset_idx == 5) || 90607ba6af4SMiriam Shitrit (preset_idx == 8) || 90707ba6af4SMiriam Shitrit (preset_idx == 11)) 90807ba6af4SMiriam Shitrit continue; 90907ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, preset_idx); 91007ba6af4SMiriam Shitrit p += __bnx2x_get_preset_regs_len(bp, preset_idx); 91107ba6af4SMiriam Shitrit } 912adfc5217SJeff Kirsher } 913adfc5217SJeff Kirsher 914adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 915adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 916adfc5217SJeff Kirsher { 917adfc5217SJeff Kirsher u32 *p = _p; 918adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 91907ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 920adfc5217SJeff Kirsher 92107ba6af4SMiriam Shitrit regs->version = 2; 922adfc5217SJeff Kirsher memset(p, 0, regs->len); 923adfc5217SJeff Kirsher 924adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 925adfc5217SJeff Kirsher return; 926adfc5217SJeff Kirsher 927adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 928adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 929adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 930adfc5217SJeff Kirsher */ 93107ba6af4SMiriam Shitrit 932adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 933adfc5217SJeff Kirsher 93407ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 93507ba6af4SMiriam Shitrit dump_hdr.preset = DUMP_ALL_PRESETS; 93607ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 93707ba6af4SMiriam Shitrit 93807ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 93907ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 94007ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 94107ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 94207ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 94307ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 94407ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 94507ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 94607ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 94707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 94807ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 94907ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 95007ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 95107ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 95207ba6af4SMiriam Shitrit } 95307ba6af4SMiriam Shitrit 95407ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 95507ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 956adfc5217SJeff Kirsher 957adfc5217SJeff Kirsher /* Actually read the registers */ 958adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 959adfc5217SJeff Kirsher 9604293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 961adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 962adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 96307ba6af4SMiriam Shitrit } 96407ba6af4SMiriam Shitrit 96507ba6af4SMiriam Shitrit static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 96607ba6af4SMiriam Shitrit { 96707ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 96807ba6af4SMiriam Shitrit int regdump_len = 0; 96907ba6af4SMiriam Shitrit 97007ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 97107ba6af4SMiriam Shitrit regdump_len *= 4; 97207ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 97307ba6af4SMiriam Shitrit 97407ba6af4SMiriam Shitrit return regdump_len; 97507ba6af4SMiriam Shitrit } 97607ba6af4SMiriam Shitrit 97707ba6af4SMiriam Shitrit static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 97807ba6af4SMiriam Shitrit { 97907ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 98007ba6af4SMiriam Shitrit 98107ba6af4SMiriam Shitrit /* Use the ethtool_dump "flag" field as the dump preset index */ 9825bb680d6SMichal Schmidt if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 9835bb680d6SMichal Schmidt return -EINVAL; 9845bb680d6SMichal Schmidt 98507ba6af4SMiriam Shitrit bp->dump_preset_idx = val->flag; 98607ba6af4SMiriam Shitrit return 0; 98707ba6af4SMiriam Shitrit } 98807ba6af4SMiriam Shitrit 98907ba6af4SMiriam Shitrit static int bnx2x_get_dump_flag(struct net_device *dev, 99007ba6af4SMiriam Shitrit struct ethtool_dump *dump) 99107ba6af4SMiriam Shitrit { 99207ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 99307ba6af4SMiriam Shitrit 9948cc2d927SMichal Schmidt dump->version = BNX2X_DUMP_VERSION; 9958cc2d927SMichal Schmidt dump->flag = bp->dump_preset_idx; 99607ba6af4SMiriam Shitrit /* Calculate the requested preset idx length */ 99707ba6af4SMiriam Shitrit dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 99807ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 99907ba6af4SMiriam Shitrit bp->dump_preset_idx, dump->len); 100007ba6af4SMiriam Shitrit return 0; 100107ba6af4SMiriam Shitrit } 100207ba6af4SMiriam Shitrit 100307ba6af4SMiriam Shitrit static int bnx2x_get_dump_data(struct net_device *dev, 100407ba6af4SMiriam Shitrit struct ethtool_dump *dump, 100507ba6af4SMiriam Shitrit void *buffer) 100607ba6af4SMiriam Shitrit { 100707ba6af4SMiriam Shitrit u32 *p = buffer; 100807ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 100907ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 101007ba6af4SMiriam Shitrit 101107ba6af4SMiriam Shitrit /* Disable parity attentions as long as following dump may 101207ba6af4SMiriam Shitrit * cause false alarms by reading never written registers. We 101307ba6af4SMiriam Shitrit * will re-enable parity attentions right after the dump. 101407ba6af4SMiriam Shitrit */ 101507ba6af4SMiriam Shitrit 101607ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 101707ba6af4SMiriam Shitrit 101807ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 101907ba6af4SMiriam Shitrit dump_hdr.preset = bp->dump_preset_idx; 102007ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 102107ba6af4SMiriam Shitrit 102207ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 102307ba6af4SMiriam Shitrit 102407ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 102507ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 102607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 102707ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 102807ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 102907ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 103007ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 103107ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 103207ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 103307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 103407ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 103507ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 103607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 103707ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 103807ba6af4SMiriam Shitrit } 103907ba6af4SMiriam Shitrit 104007ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 104107ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 104207ba6af4SMiriam Shitrit 104307ba6af4SMiriam Shitrit /* Actually read the registers */ 104407ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 104507ba6af4SMiriam Shitrit 10464293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 104707ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 104807ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 104907ba6af4SMiriam Shitrit 105007ba6af4SMiriam Shitrit return 0; 1051adfc5217SJeff Kirsher } 1052adfc5217SJeff Kirsher 1053adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 1054adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 1055adfc5217SJeff Kirsher { 1056adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1057adfc5217SJeff Kirsher 105868aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 105968aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1060adfc5217SJeff Kirsher 10618ca5e17eSAriel Elior bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 10628ca5e17eSAriel Elior 106368aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1064adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 1065cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 1066adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 1067adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 1068adfc5217SJeff Kirsher } 1069adfc5217SJeff Kirsher 1070adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1071adfc5217SJeff Kirsher { 1072adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1073adfc5217SJeff Kirsher 1074adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 1075adfc5217SJeff Kirsher wol->supported = 0; 1076adfc5217SJeff Kirsher wol->wolopts = 0; 1077adfc5217SJeff Kirsher } else { 1078adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 1079adfc5217SJeff Kirsher if (bp->wol) 1080adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 1081adfc5217SJeff Kirsher else 1082adfc5217SJeff Kirsher wol->wolopts = 0; 1083adfc5217SJeff Kirsher } 1084adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 1085adfc5217SJeff Kirsher } 1086adfc5217SJeff Kirsher 1087adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1088adfc5217SJeff Kirsher { 1089adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1090adfc5217SJeff Kirsher 109151c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 10922de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1093adfc5217SJeff Kirsher return -EINVAL; 109451c1a580SMerav Sicron } 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 109751c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 10982de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1099adfc5217SJeff Kirsher return -EINVAL; 110051c1a580SMerav Sicron } 1101adfc5217SJeff Kirsher bp->wol = 1; 1102adfc5217SJeff Kirsher } else 1103adfc5217SJeff Kirsher bp->wol = 0; 1104adfc5217SJeff Kirsher 1105adfc5217SJeff Kirsher return 0; 1106adfc5217SJeff Kirsher } 1107adfc5217SJeff Kirsher 1108adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 1109adfc5217SJeff Kirsher { 1110adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1111adfc5217SJeff Kirsher 1112adfc5217SJeff Kirsher return bp->msg_enable; 1113adfc5217SJeff Kirsher } 1114adfc5217SJeff Kirsher 1115adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1116adfc5217SJeff Kirsher { 1117adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1118adfc5217SJeff Kirsher 1119adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 1120adfc5217SJeff Kirsher /* dump MCP trace */ 1121ad5afc89SAriel Elior if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1122adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 1123adfc5217SJeff Kirsher bp->msg_enable = level; 1124adfc5217SJeff Kirsher } 1125adfc5217SJeff Kirsher } 1126adfc5217SJeff Kirsher 1127adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 1128adfc5217SJeff Kirsher { 1129adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1130adfc5217SJeff Kirsher 1131adfc5217SJeff Kirsher if (!bp->port.pmf) 1132adfc5217SJeff Kirsher return 0; 1133adfc5217SJeff Kirsher 1134adfc5217SJeff Kirsher if (netif_running(dev)) { 1135adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11365d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1137adfc5217SJeff Kirsher bnx2x_link_set(bp); 1138adfc5217SJeff Kirsher } 1139adfc5217SJeff Kirsher 1140adfc5217SJeff Kirsher return 0; 1141adfc5217SJeff Kirsher } 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 1144adfc5217SJeff Kirsher { 1145adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1146adfc5217SJeff Kirsher 1147adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1148adfc5217SJeff Kirsher return 0; 1149adfc5217SJeff Kirsher 11506495d15aSDmitry Kravkov if (IS_VF(bp)) 11516495d15aSDmitry Kravkov return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 11526495d15aSDmitry Kravkov &bp->vf_link_vars.link_report_flags); 11536495d15aSDmitry Kravkov 1154adfc5217SJeff Kirsher return bp->link_vars.link_up; 1155adfc5217SJeff Kirsher } 1156adfc5217SJeff Kirsher 1157adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 1158adfc5217SJeff Kirsher { 1159adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1160adfc5217SJeff Kirsher 1161adfc5217SJeff Kirsher return bp->common.flash_size; 1162adfc5217SJeff Kirsher } 1163adfc5217SJeff Kirsher 116416a5fd92SYuval Mintz /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 116516a5fd92SYuval Mintz * had we done things the other way around, if two pfs from the same port would 1166f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 1167f16da43bSAriel Elior * as: 1168f16da43bSAriel Elior * pf A takes the port lock. 1169f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 1170f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 1171f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 1172f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 1173f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 1174f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 11752de67439SYuval Mintz * access corrupted by pf B) 1176f16da43bSAriel Elior */ 1177adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1178adfc5217SJeff Kirsher { 1179adfc5217SJeff Kirsher int port = BP_PORT(bp); 1180adfc5217SJeff Kirsher int count, i; 1181f16da43bSAriel Elior u32 val; 1182f16da43bSAriel Elior 1183f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1184f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1185adfc5217SJeff Kirsher 1186adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1187adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1188adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1189adfc5217SJeff Kirsher count *= 100; 1190adfc5217SJeff Kirsher 1191adfc5217SJeff Kirsher /* request access to nvram interface */ 1192adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1193adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1194adfc5217SJeff Kirsher 1195adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1196adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1197adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1198adfc5217SJeff Kirsher break; 1199adfc5217SJeff Kirsher 1200adfc5217SJeff Kirsher udelay(5); 1201adfc5217SJeff Kirsher } 1202adfc5217SJeff Kirsher 1203adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 120451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 120551c1a580SMerav Sicron "cannot get access to nvram interface\n"); 1206adfc5217SJeff Kirsher return -EBUSY; 1207adfc5217SJeff Kirsher } 1208adfc5217SJeff Kirsher 1209adfc5217SJeff Kirsher return 0; 1210adfc5217SJeff Kirsher } 1211adfc5217SJeff Kirsher 1212adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1213adfc5217SJeff Kirsher { 1214adfc5217SJeff Kirsher int port = BP_PORT(bp); 1215adfc5217SJeff Kirsher int count, i; 1216f16da43bSAriel Elior u32 val; 1217adfc5217SJeff Kirsher 1218adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1219adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1220adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1221adfc5217SJeff Kirsher count *= 100; 1222adfc5217SJeff Kirsher 1223adfc5217SJeff Kirsher /* relinquish nvram interface */ 1224adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1225adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1226adfc5217SJeff Kirsher 1227adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1228adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1229adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1230adfc5217SJeff Kirsher break; 1231adfc5217SJeff Kirsher 1232adfc5217SJeff Kirsher udelay(5); 1233adfc5217SJeff Kirsher } 1234adfc5217SJeff Kirsher 1235adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 123651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 123751c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1238adfc5217SJeff Kirsher return -EBUSY; 1239adfc5217SJeff Kirsher } 1240adfc5217SJeff Kirsher 1241f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1242f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1243adfc5217SJeff Kirsher return 0; 1244adfc5217SJeff Kirsher } 1245adfc5217SJeff Kirsher 1246adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1247adfc5217SJeff Kirsher { 1248adfc5217SJeff Kirsher u32 val; 1249adfc5217SJeff Kirsher 1250adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1251adfc5217SJeff Kirsher 1252adfc5217SJeff Kirsher /* enable both bits, even on read */ 1253adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1254adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1255adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1256adfc5217SJeff Kirsher } 1257adfc5217SJeff Kirsher 1258adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1259adfc5217SJeff Kirsher { 1260adfc5217SJeff Kirsher u32 val; 1261adfc5217SJeff Kirsher 1262adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher /* disable both bits, even after read */ 1265adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1266adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1267adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1268adfc5217SJeff Kirsher } 1269adfc5217SJeff Kirsher 1270adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1271adfc5217SJeff Kirsher u32 cmd_flags) 1272adfc5217SJeff Kirsher { 1273adfc5217SJeff Kirsher int count, i, rc; 1274adfc5217SJeff Kirsher u32 val; 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher /* build the command word */ 1277adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1278adfc5217SJeff Kirsher 1279adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1280adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1281adfc5217SJeff Kirsher 1282adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1283adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1284adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1285adfc5217SJeff Kirsher 1286adfc5217SJeff Kirsher /* issue a read command */ 1287adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1288adfc5217SJeff Kirsher 1289adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1290adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1291adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1292adfc5217SJeff Kirsher count *= 100; 1293adfc5217SJeff Kirsher 1294adfc5217SJeff Kirsher /* wait for completion */ 1295adfc5217SJeff Kirsher *ret_val = 0; 1296adfc5217SJeff Kirsher rc = -EBUSY; 1297adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1298adfc5217SJeff Kirsher udelay(5); 1299adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1300adfc5217SJeff Kirsher 1301adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1302adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1303adfc5217SJeff Kirsher /* we read nvram data in cpu order 1304adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 130507ba6af4SMiriam Shitrit * converting to big-endian will do the work 130607ba6af4SMiriam Shitrit */ 1307adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1308adfc5217SJeff Kirsher rc = 0; 1309adfc5217SJeff Kirsher break; 1310adfc5217SJeff Kirsher } 1311adfc5217SJeff Kirsher } 131251c1a580SMerav Sicron if (rc == -EBUSY) 131351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 131451c1a580SMerav Sicron "nvram read timeout expired\n"); 1315adfc5217SJeff Kirsher return rc; 1316adfc5217SJeff Kirsher } 1317adfc5217SJeff Kirsher 1318adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1319adfc5217SJeff Kirsher int buf_size) 1320adfc5217SJeff Kirsher { 1321adfc5217SJeff Kirsher int rc; 1322adfc5217SJeff Kirsher u32 cmd_flags; 1323adfc5217SJeff Kirsher __be32 val; 1324adfc5217SJeff Kirsher 1325adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 132651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1327adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1328adfc5217SJeff Kirsher offset, buf_size); 1329adfc5217SJeff Kirsher return -EINVAL; 1330adfc5217SJeff Kirsher } 1331adfc5217SJeff Kirsher 1332adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 133351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 133451c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1335adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1336adfc5217SJeff Kirsher return -EINVAL; 1337adfc5217SJeff Kirsher } 1338adfc5217SJeff Kirsher 1339adfc5217SJeff Kirsher /* request access to nvram interface */ 1340adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1341adfc5217SJeff Kirsher if (rc) 1342adfc5217SJeff Kirsher return rc; 1343adfc5217SJeff Kirsher 1344adfc5217SJeff Kirsher /* enable access to nvram interface */ 1345adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1346adfc5217SJeff Kirsher 1347adfc5217SJeff Kirsher /* read the first word(s) */ 1348adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1349adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1350adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1351adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1352adfc5217SJeff Kirsher 1353adfc5217SJeff Kirsher /* advance to the next dword */ 1354adfc5217SJeff Kirsher offset += sizeof(u32); 1355adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1356adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1357adfc5217SJeff Kirsher cmd_flags = 0; 1358adfc5217SJeff Kirsher } 1359adfc5217SJeff Kirsher 1360adfc5217SJeff Kirsher if (rc == 0) { 1361adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1362adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1363adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1364adfc5217SJeff Kirsher } 1365adfc5217SJeff Kirsher 1366adfc5217SJeff Kirsher /* disable access to nvram interface */ 1367adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1368adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1369adfc5217SJeff Kirsher 1370adfc5217SJeff Kirsher return rc; 1371adfc5217SJeff Kirsher } 1372adfc5217SJeff Kirsher 137385640952SDmitry Kravkov static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 137485640952SDmitry Kravkov int buf_size) 137585640952SDmitry Kravkov { 137685640952SDmitry Kravkov int rc; 137785640952SDmitry Kravkov 137885640952SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 137985640952SDmitry Kravkov 138085640952SDmitry Kravkov if (!rc) { 138185640952SDmitry Kravkov __be32 *be = (__be32 *)buf; 138285640952SDmitry Kravkov 138385640952SDmitry Kravkov while ((buf_size -= 4) >= 0) 138485640952SDmitry Kravkov *buf++ = be32_to_cpu(*be++); 138585640952SDmitry Kravkov } 138685640952SDmitry Kravkov 138785640952SDmitry Kravkov return rc; 138885640952SDmitry Kravkov } 138985640952SDmitry Kravkov 13903fb43eb2SYuval Mintz static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 13913fb43eb2SYuval Mintz { 13923fb43eb2SYuval Mintz int rc = 1; 13933fb43eb2SYuval Mintz u16 pm = 0; 13943fb43eb2SYuval Mintz struct net_device *dev = pci_get_drvdata(bp->pdev); 13953fb43eb2SYuval Mintz 139629ed74c3SJon Mason if (bp->pdev->pm_cap) 13973fb43eb2SYuval Mintz rc = pci_read_config_word(bp->pdev, 139829ed74c3SJon Mason bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 13993fb43eb2SYuval Mintz 1400829a5071SYuval Mintz if ((rc && !netif_running(dev)) || 1401c957d09fSYuval Mintz (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 14023fb43eb2SYuval Mintz return false; 14033fb43eb2SYuval Mintz 14043fb43eb2SYuval Mintz return true; 14053fb43eb2SYuval Mintz } 14063fb43eb2SYuval Mintz 1407adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1408adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1409adfc5217SJeff Kirsher { 1410adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1411adfc5217SJeff Kirsher 14123fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 141351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 141451c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1415adfc5217SJeff Kirsher return -EAGAIN; 141651c1a580SMerav Sicron } 1417adfc5217SJeff Kirsher 141851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1419f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1420adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1421adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1422adfc5217SJeff Kirsher 1423adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1424adfc5217SJeff Kirsher 1425f1691dc6SDmitry Kravkov return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1426adfc5217SJeff Kirsher } 1427adfc5217SJeff Kirsher 142824ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 142924ea818eSYuval Mintz struct ethtool_eeprom *ee, 143024ea818eSYuval Mintz u8 *data) 143124ea818eSYuval Mintz { 143224ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1433669d6996SYaniv Rosner int rc = -EINVAL, phy_idx; 143424ea818eSYuval Mintz u8 *user_data = data; 1435669d6996SYaniv Rosner unsigned int start_addr = ee->offset, xfer_size = 0; 143624ea818eSYuval Mintz 14373fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 143824ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 143924ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 144024ea818eSYuval Mintz return -EAGAIN; 144124ea818eSYuval Mintz } 144224ea818eSYuval Mintz 144324ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1444669d6996SYaniv Rosner 1445669d6996SYaniv Rosner /* Read A0 section */ 1446669d6996SYaniv Rosner if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1447669d6996SYaniv Rosner /* Limit transfer size to the A0 section boundary */ 1448669d6996SYaniv Rosner if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1449669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1450669d6996SYaniv Rosner else 1451669d6996SYaniv Rosner xfer_size = ee->len; 145224ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 145324ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 145424ea818eSYuval Mintz &bp->link_params, 1455669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1456669d6996SYaniv Rosner start_addr, 145724ea818eSYuval Mintz xfer_size, 145824ea818eSYuval Mintz user_data); 1459669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1460669d6996SYaniv Rosner if (rc) { 1461669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1462669d6996SYaniv Rosner 1463669d6996SYaniv Rosner return -EINVAL; 1464669d6996SYaniv Rosner } 146524ea818eSYuval Mintz user_data += xfer_size; 1466669d6996SYaniv Rosner start_addr += xfer_size; 146724ea818eSYuval Mintz } 146824ea818eSYuval Mintz 1469669d6996SYaniv Rosner /* Read A2 section */ 1470669d6996SYaniv Rosner if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1471669d6996SYaniv Rosner (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1472669d6996SYaniv Rosner xfer_size = ee->len - xfer_size; 1473669d6996SYaniv Rosner /* Limit transfer size to the A2 section boundary */ 1474669d6996SYaniv Rosner if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1475669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1476669d6996SYaniv Rosner start_addr -= ETH_MODULE_SFF_8079_LEN; 1477669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1478669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1479669d6996SYaniv Rosner &bp->link_params, 1480669d6996SYaniv Rosner I2C_DEV_ADDR_A2, 1481669d6996SYaniv Rosner start_addr, 1482669d6996SYaniv Rosner xfer_size, 1483669d6996SYaniv Rosner user_data); 148424ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 1485669d6996SYaniv Rosner if (rc) { 1486669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1487669d6996SYaniv Rosner return -EINVAL; 1488669d6996SYaniv Rosner } 1489669d6996SYaniv Rosner } 149024ea818eSYuval Mintz return rc; 149124ea818eSYuval Mintz } 149224ea818eSYuval Mintz 149324ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 149424ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 149524ea818eSYuval Mintz { 149624ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1497669d6996SYaniv Rosner int phy_idx, rc; 1498669d6996SYaniv Rosner u8 sff8472_comp, diag_type; 1499669d6996SYaniv Rosner 15003fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 150124ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 150224ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 150324ea818eSYuval Mintz return -EAGAIN; 150424ea818eSYuval Mintz } 150524ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1506669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1507669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1508669d6996SYaniv Rosner &bp->link_params, 1509669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1510669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_ADDR, 1511669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_SIZE, 1512669d6996SYaniv Rosner &sff8472_comp); 1513669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1514669d6996SYaniv Rosner if (rc) { 1515669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1516669d6996SYaniv Rosner return -EINVAL; 1517669d6996SYaniv Rosner } 1518669d6996SYaniv Rosner 1519669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1520669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1521669d6996SYaniv Rosner &bp->link_params, 1522669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1523669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_ADDR, 1524669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_SIZE, 1525669d6996SYaniv Rosner &diag_type); 1526669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1527669d6996SYaniv Rosner if (rc) { 1528669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1529669d6996SYaniv Rosner return -EINVAL; 1530669d6996SYaniv Rosner } 1531669d6996SYaniv Rosner 1532669d6996SYaniv Rosner if (!sff8472_comp || 1533669d6996SYaniv Rosner (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 153424ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 153524ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1536669d6996SYaniv Rosner } else { 1537669d6996SYaniv Rosner modinfo->type = ETH_MODULE_SFF_8472; 1538669d6996SYaniv Rosner modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 153924ea818eSYuval Mintz } 1540669d6996SYaniv Rosner return 0; 154124ea818eSYuval Mintz } 154224ea818eSYuval Mintz 1543adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1544adfc5217SJeff Kirsher u32 cmd_flags) 1545adfc5217SJeff Kirsher { 1546adfc5217SJeff Kirsher int count, i, rc; 1547adfc5217SJeff Kirsher 1548adfc5217SJeff Kirsher /* build the command word */ 1549adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1550adfc5217SJeff Kirsher 1551adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1552adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1553adfc5217SJeff Kirsher 1554adfc5217SJeff Kirsher /* write the data */ 1555adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1556adfc5217SJeff Kirsher 1557adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1558adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1559adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1560adfc5217SJeff Kirsher 1561adfc5217SJeff Kirsher /* issue the write command */ 1562adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1563adfc5217SJeff Kirsher 1564adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1565adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1566adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1567adfc5217SJeff Kirsher count *= 100; 1568adfc5217SJeff Kirsher 1569adfc5217SJeff Kirsher /* wait for completion */ 1570adfc5217SJeff Kirsher rc = -EBUSY; 1571adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1572adfc5217SJeff Kirsher udelay(5); 1573adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1574adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1575adfc5217SJeff Kirsher rc = 0; 1576adfc5217SJeff Kirsher break; 1577adfc5217SJeff Kirsher } 1578adfc5217SJeff Kirsher } 1579adfc5217SJeff Kirsher 158051c1a580SMerav Sicron if (rc == -EBUSY) 158151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 158251c1a580SMerav Sicron "nvram write timeout expired\n"); 1583adfc5217SJeff Kirsher return rc; 1584adfc5217SJeff Kirsher } 1585adfc5217SJeff Kirsher 1586adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1587adfc5217SJeff Kirsher 1588adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1589adfc5217SJeff Kirsher int buf_size) 1590adfc5217SJeff Kirsher { 1591adfc5217SJeff Kirsher int rc; 159230c20b67SDmitry Kravkov u32 cmd_flags, align_offset, val; 159330c20b67SDmitry Kravkov __be32 val_be; 1594adfc5217SJeff Kirsher 1595adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 159651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 159751c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1598adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1599adfc5217SJeff Kirsher return -EINVAL; 1600adfc5217SJeff Kirsher } 1601adfc5217SJeff Kirsher 1602adfc5217SJeff Kirsher /* request access to nvram interface */ 1603adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1604adfc5217SJeff Kirsher if (rc) 1605adfc5217SJeff Kirsher return rc; 1606adfc5217SJeff Kirsher 1607adfc5217SJeff Kirsher /* enable access to nvram interface */ 1608adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1609adfc5217SJeff Kirsher 1610adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1611adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 161230c20b67SDmitry Kravkov rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1613adfc5217SJeff Kirsher 1614adfc5217SJeff Kirsher if (rc == 0) { 1615adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 161607ba6af4SMiriam Shitrit * convert it back to cpu order 161707ba6af4SMiriam Shitrit */ 161830c20b67SDmitry Kravkov val = be32_to_cpu(val_be); 161930c20b67SDmitry Kravkov 1620c957d09fSYuval Mintz val &= ~le32_to_cpu((__force __le32) 1621c957d09fSYuval Mintz (0xff << BYTE_OFFSET(offset))); 1622c957d09fSYuval Mintz val |= le32_to_cpu((__force __le32) 1623c957d09fSYuval Mintz (*data_buf << BYTE_OFFSET(offset))); 1624adfc5217SJeff Kirsher 1625adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1626adfc5217SJeff Kirsher cmd_flags); 1627adfc5217SJeff Kirsher } 1628adfc5217SJeff Kirsher 1629adfc5217SJeff Kirsher /* disable access to nvram interface */ 1630adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1631adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1632adfc5217SJeff Kirsher 1633adfc5217SJeff Kirsher return rc; 1634adfc5217SJeff Kirsher } 1635adfc5217SJeff Kirsher 1636adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1637adfc5217SJeff Kirsher int buf_size) 1638adfc5217SJeff Kirsher { 1639adfc5217SJeff Kirsher int rc; 1640adfc5217SJeff Kirsher u32 cmd_flags; 1641adfc5217SJeff Kirsher u32 val; 1642adfc5217SJeff Kirsher u32 written_so_far; 1643adfc5217SJeff Kirsher 1644adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1645adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1646adfc5217SJeff Kirsher 1647adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 164851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1649adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1650adfc5217SJeff Kirsher offset, buf_size); 1651adfc5217SJeff Kirsher return -EINVAL; 1652adfc5217SJeff Kirsher } 1653adfc5217SJeff Kirsher 1654adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 165551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 165651c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1657adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1658adfc5217SJeff Kirsher return -EINVAL; 1659adfc5217SJeff Kirsher } 1660adfc5217SJeff Kirsher 1661adfc5217SJeff Kirsher /* request access to nvram interface */ 1662adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1663adfc5217SJeff Kirsher if (rc) 1664adfc5217SJeff Kirsher return rc; 1665adfc5217SJeff Kirsher 1666adfc5217SJeff Kirsher /* enable access to nvram interface */ 1667adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1668adfc5217SJeff Kirsher 1669adfc5217SJeff Kirsher written_so_far = 0; 1670adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1671adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1672adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1673adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1674adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1675adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1676adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1677adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1678adfc5217SJeff Kirsher 1679adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1680adfc5217SJeff Kirsher 168168bf5a10SYuval Mintz /* Notice unlike bnx2x_nvram_read_dword() this will not 168268bf5a10SYuval Mintz * change val using be32_to_cpu(), which causes data to flip 168368bf5a10SYuval Mintz * if the eeprom is read and then written back. This is due 168468bf5a10SYuval Mintz * to tools utilizing this functionality that would break 168568bf5a10SYuval Mintz * if this would be resolved. 168668bf5a10SYuval Mintz */ 1687adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1688adfc5217SJeff Kirsher 1689adfc5217SJeff Kirsher /* advance to the next dword */ 1690adfc5217SJeff Kirsher offset += sizeof(u32); 1691adfc5217SJeff Kirsher data_buf += sizeof(u32); 1692adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1693adfc5217SJeff Kirsher cmd_flags = 0; 1694adfc5217SJeff Kirsher } 1695adfc5217SJeff Kirsher 1696adfc5217SJeff Kirsher /* disable access to nvram interface */ 1697adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1698adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1699adfc5217SJeff Kirsher 1700adfc5217SJeff Kirsher return rc; 1701adfc5217SJeff Kirsher } 1702adfc5217SJeff Kirsher 1703adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1704adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1705adfc5217SJeff Kirsher { 1706adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1707adfc5217SJeff Kirsher int port = BP_PORT(bp); 1708adfc5217SJeff Kirsher int rc = 0; 1709adfc5217SJeff Kirsher u32 ext_phy_config; 17103fb43eb2SYuval Mintz 17113fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 171251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 171351c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1714adfc5217SJeff Kirsher return -EAGAIN; 171551c1a580SMerav Sicron } 1716adfc5217SJeff Kirsher 171751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1718f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1719adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1720adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1721adfc5217SJeff Kirsher 1722adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1723adfc5217SJeff Kirsher 1724adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1725adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 172651c1a580SMerav Sicron !bp->port.pmf) { 172751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 172851c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1729adfc5217SJeff Kirsher return -EINVAL; 173051c1a580SMerav Sicron } 1731adfc5217SJeff Kirsher 1732adfc5217SJeff Kirsher ext_phy_config = 1733adfc5217SJeff Kirsher SHMEM_RD(bp, 1734adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1735adfc5217SJeff Kirsher 1736adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1737adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1738adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1739adfc5217SJeff Kirsher 1740adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1741adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1742adfc5217SJeff Kirsher &bp->link_vars, 0); 1743adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1744adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1745adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1746adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1747adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1748adfc5217SJeff Kirsher bnx2x_link_report(bp); 1749adfc5217SJeff Kirsher 1750adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1751adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1752adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1753adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1754adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1755adfc5217SJeff Kirsher &bp->link_vars, 1); 1756adfc5217SJeff Kirsher 1757adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1758adfc5217SJeff Kirsher &bp->link_vars); 1759adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1760adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1761adfc5217SJeff Kirsher } 1762adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1763adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1764adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1765adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1766adfc5217SJeff Kirsher 1767adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1768adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1769adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1770adfc5217SJeff Kirsher 1771adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1772adfc5217SJeff Kirsher 1773adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1774adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1775adfc5217SJeff Kirsher 1776adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1777adfc5217SJeff Kirsher msleep(500); 1778adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1779adfc5217SJeff Kirsher msleep(500); 1780adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1781adfc5217SJeff Kirsher } 1782adfc5217SJeff Kirsher } else 1783adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1784adfc5217SJeff Kirsher 1785adfc5217SJeff Kirsher return rc; 1786adfc5217SJeff Kirsher } 1787adfc5217SJeff Kirsher 1788adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1789adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1790adfc5217SJeff Kirsher { 1791adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1792adfc5217SJeff Kirsher 1793adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1794adfc5217SJeff Kirsher 1795adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1796adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1797adfc5217SJeff Kirsher 1798adfc5217SJeff Kirsher return 0; 1799adfc5217SJeff Kirsher } 1800adfc5217SJeff Kirsher 1801adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1802adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1803adfc5217SJeff Kirsher { 1804adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1805adfc5217SJeff Kirsher 1806adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1807adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1808adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1809adfc5217SJeff Kirsher 1810adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1811adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1812adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1813adfc5217SJeff Kirsher 1814adfc5217SJeff Kirsher if (netif_running(dev)) 1815adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1816adfc5217SJeff Kirsher 1817adfc5217SJeff Kirsher return 0; 1818adfc5217SJeff Kirsher } 1819adfc5217SJeff Kirsher 1820adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1821adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1822adfc5217SJeff Kirsher { 1823adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1824adfc5217SJeff Kirsher 1825adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1826adfc5217SJeff Kirsher 1827adfc5217SJeff Kirsher if (bp->rx_ring_size) 1828adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1829adfc5217SJeff Kirsher else 1830adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1831adfc5217SJeff Kirsher 1832a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1833adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1834adfc5217SJeff Kirsher } 1835adfc5217SJeff Kirsher 1836adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1837adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1838adfc5217SJeff Kirsher { 1839adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1840adfc5217SJeff Kirsher 184104c46736SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 184204c46736SYuval Mintz "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 184304c46736SYuval Mintz ering->rx_pending, ering->tx_pending); 184404c46736SYuval Mintz 1845adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 184651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 184751c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1848adfc5217SJeff Kirsher return -EAGAIN; 1849adfc5217SJeff Kirsher } 1850adfc5217SJeff Kirsher 1851adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1852adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1853adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1854a3348722SBarak Witkowski (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 185551c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 185651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1857adfc5217SJeff Kirsher return -EINVAL; 185851c1a580SMerav Sicron } 1859adfc5217SJeff Kirsher 1860adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1861adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1862adfc5217SJeff Kirsher 1863adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1864adfc5217SJeff Kirsher } 1865adfc5217SJeff Kirsher 1866adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1867adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1868adfc5217SJeff Kirsher { 1869adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1870adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 18719e7e8399SMintz Yuval int cfg_reg; 18729e7e8399SMintz Yuval 1873adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1874adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1875adfc5217SJeff Kirsher 18769e7e8399SMintz Yuval if (!epause->autoneg) 1877241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 18789e7e8399SMintz Yuval else 18799e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 18809e7e8399SMintz Yuval 18819e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1882adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 18839e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1884adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1885adfc5217SJeff Kirsher 188651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1887f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1888adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1889adfc5217SJeff Kirsher } 1890adfc5217SJeff Kirsher 1891adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1892adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1893adfc5217SJeff Kirsher { 1894adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1895adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1896adfc5217SJeff Kirsher if (IS_MF(bp)) 1897adfc5217SJeff Kirsher return 0; 1898adfc5217SJeff Kirsher 189951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1900f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1901adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1902adfc5217SJeff Kirsher 1903adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1904adfc5217SJeff Kirsher 1905adfc5217SJeff Kirsher if (epause->rx_pause) 1906adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1907adfc5217SJeff Kirsher 1908adfc5217SJeff Kirsher if (epause->tx_pause) 1909adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1910adfc5217SJeff Kirsher 1911adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1912adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1913adfc5217SJeff Kirsher 1914adfc5217SJeff Kirsher if (epause->autoneg) { 1915adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 191651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1917adfc5217SJeff Kirsher return -EINVAL; 1918adfc5217SJeff Kirsher } 1919adfc5217SJeff Kirsher 1920adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1921adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1922adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1923adfc5217SJeff Kirsher } 1924ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv = 0; 19255cd75f0cSYaniv Rosner if (epause->rx_pause) 19265cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 19275cd75f0cSYaniv Rosner 19285cd75f0cSYaniv Rosner if (epause->tx_pause) 19295cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1930ba35a0fdSYaniv Rosner 1931ba35a0fdSYaniv Rosner if (!bp->link_params.req_fc_auto_adv) 1932ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1933adfc5217SJeff Kirsher } 1934adfc5217SJeff Kirsher 193551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1936adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1937adfc5217SJeff Kirsher 1938adfc5217SJeff Kirsher if (netif_running(dev)) { 1939adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1940adfc5217SJeff Kirsher bnx2x_link_set(bp); 1941adfc5217SJeff Kirsher } 1942adfc5217SJeff Kirsher 1943adfc5217SJeff Kirsher return 0; 1944adfc5217SJeff Kirsher } 1945adfc5217SJeff Kirsher 19465889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1947cf2c1df6SMerav Sicron "register_test (offline) ", 1948cf2c1df6SMerav Sicron "memory_test (offline) ", 1949cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1950cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1951cf2c1df6SMerav Sicron "nvram_test (online) ", 1952cf2c1df6SMerav Sicron "interrupt_test (online) ", 1953cf2c1df6SMerav Sicron "link_test (online) " 1954adfc5217SJeff Kirsher }; 1955adfc5217SJeff Kirsher 19563521b419SYuval Mintz enum { 19573521b419SYuval Mintz BNX2X_PRI_FLAG_ISCSI, 19583521b419SYuval Mintz BNX2X_PRI_FLAG_FCOE, 19593521b419SYuval Mintz BNX2X_PRI_FLAG_STORAGE, 19603521b419SYuval Mintz BNX2X_PRI_FLAG_LEN, 19613521b419SYuval Mintz }; 19623521b419SYuval Mintz 19633521b419SYuval Mintz static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 19643521b419SYuval Mintz "iSCSI offload support", 19653521b419SYuval Mintz "FCoE offload support", 19663521b419SYuval Mintz "Storage only interface" 19673521b419SYuval Mintz }; 19683521b419SYuval Mintz 1969e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 1970e9939c80SYuval Mintz { 1971e9939c80SYuval Mintz u32 modes = 0; 1972e9939c80SYuval Mintz 1973e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 1974e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 1975e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 1976e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 1977e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 1978e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 1979e9939c80SYuval Mintz 1980e9939c80SYuval Mintz return modes; 1981e9939c80SYuval Mintz } 1982e9939c80SYuval Mintz 1983e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1984e9939c80SYuval Mintz { 1985e9939c80SYuval Mintz u32 eee_adv = 0; 1986e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 1987e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 1988e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 1989e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 1990e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 1991e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 1992e9939c80SYuval Mintz 1993e9939c80SYuval Mintz return eee_adv << shift; 1994e9939c80SYuval Mintz } 1995e9939c80SYuval Mintz 1996e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1997e9939c80SYuval Mintz { 1998e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1999e9939c80SYuval Mintz u32 eee_cfg; 2000e9939c80SYuval Mintz 2001e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2002e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2003e9939c80SYuval Mintz return -EOPNOTSUPP; 2004e9939c80SYuval Mintz } 2005e9939c80SYuval Mintz 200608e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2007e9939c80SYuval Mintz 2008e9939c80SYuval Mintz edata->supported = 2009e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2010e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 2011e9939c80SYuval Mintz 2012e9939c80SYuval Mintz edata->advertised = 2013e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2014e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2015e9939c80SYuval Mintz edata->lp_advertised = 2016e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2017e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2018e9939c80SYuval Mintz 2019e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 2020e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2021e9939c80SYuval Mintz 2022e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2023e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2024e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2025e9939c80SYuval Mintz 2026e9939c80SYuval Mintz return 0; 2027e9939c80SYuval Mintz } 2028e9939c80SYuval Mintz 2029e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2030e9939c80SYuval Mintz { 2031e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 2032e9939c80SYuval Mintz u32 eee_cfg; 2033e9939c80SYuval Mintz u32 advertised; 2034e9939c80SYuval Mintz 2035e9939c80SYuval Mintz if (IS_MF(bp)) 2036e9939c80SYuval Mintz return 0; 2037e9939c80SYuval Mintz 2038e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2039e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2040e9939c80SYuval Mintz return -EOPNOTSUPP; 2041e9939c80SYuval Mintz } 2042e9939c80SYuval Mintz 204308e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2044e9939c80SYuval Mintz 2045e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2046e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2047e9939c80SYuval Mintz return -EOPNOTSUPP; 2048e9939c80SYuval Mintz } 2049e9939c80SYuval Mintz 2050e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 2051e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2052e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2053e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2054efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 2055e9939c80SYuval Mintz return -EINVAL; 2056e9939c80SYuval Mintz } 2057e9939c80SYuval Mintz 2058e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2059e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2060e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 2061e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 2062e9939c80SYuval Mintz return -EINVAL; 2063e9939c80SYuval Mintz } 2064e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 2065e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2066e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2067e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 2068e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2069e9939c80SYuval Mintz return -EINVAL; 2070e9939c80SYuval Mintz } 2071e9939c80SYuval Mintz 2072e9939c80SYuval Mintz /* All is well; Apply changes*/ 2073e9939c80SYuval Mintz if (edata->eee_enabled) 2074e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2075e9939c80SYuval Mintz else 2076e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2077e9939c80SYuval Mintz 2078e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 2079e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2080e9939c80SYuval Mintz else 2081e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2082e9939c80SYuval Mintz 2083e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2084e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2085e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 2086e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 2087e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 2088e9939c80SYuval Mintz 208916a5fd92SYuval Mintz /* Restart link to propagate changes */ 2090e9939c80SYuval Mintz if (netif_running(dev)) { 2091e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 20925d07d868SYuval Mintz bnx2x_force_link_reset(bp); 2093e9939c80SYuval Mintz bnx2x_link_set(bp); 2094e9939c80SYuval Mintz } 2095e9939c80SYuval Mintz 2096e9939c80SYuval Mintz return 0; 2097e9939c80SYuval Mintz } 2098e9939c80SYuval Mintz 2099adfc5217SJeff Kirsher enum { 2100adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 2101adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 2102adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 2103adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 2104adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 2105adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 2106adfc5217SJeff Kirsher }; 2107adfc5217SJeff Kirsher 2108adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2109adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2110adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2111adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2112adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2113adfc5217SJeff Kirsher 2114adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2115adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2116adfc5217SJeff Kirsher 2117adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 2118adfc5217SJeff Kirsher { 2119adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 2120adfc5217SJeff Kirsher u32 wr_val = 0, hw; 2121adfc5217SJeff Kirsher int port = BP_PORT(bp); 2122adfc5217SJeff Kirsher static const struct { 2123adfc5217SJeff Kirsher u32 hw; 2124adfc5217SJeff Kirsher u32 offset0; 2125adfc5217SJeff Kirsher u32 offset1; 2126adfc5217SJeff Kirsher u32 mask; 2127adfc5217SJeff Kirsher } reg_tbl[] = { 2128adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 2129adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2130adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2131adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2132adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 2133adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 2134adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2135adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2136adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2137adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2138adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 2139adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2140adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2141adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2142adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2143adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2144adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2145adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2146adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2147adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2148adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 2149adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2150adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2151adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2152adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2153adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 2154adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2155adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2156adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2157adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2158adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2159adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2160adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2161adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2162adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2163adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2164adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2165adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2166adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2167adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2168adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2169adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2170adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2171adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2172adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2173adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2174adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2175adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2176adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2177adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2178adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2179adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2180adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2181adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2182adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2183adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2184adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2185adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2186adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2187adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2188adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 2189adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2190adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2191adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2192adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2193adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2194adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2195adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2196adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2197adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2198adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2199adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2200adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2201adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2202adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2203adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2204adfc5217SJeff Kirsher 2205adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2206adfc5217SJeff Kirsher }; 2207adfc5217SJeff Kirsher 22083fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 220951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 221051c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2211adfc5217SJeff Kirsher return rc; 221251c1a580SMerav Sicron } 2213adfc5217SJeff Kirsher 2214adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2215adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 2216adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2217adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 2218adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2219adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 2220adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 2221adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 2222adfc5217SJeff Kirsher else /* e3 A0 */ 2223adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 2224adfc5217SJeff Kirsher 2225adfc5217SJeff Kirsher /* Repeat the test twice: 222607ba6af4SMiriam Shitrit * First by writing 0x00000000, second by writing 0xffffffff 222707ba6af4SMiriam Shitrit */ 2228adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 2229adfc5217SJeff Kirsher 2230adfc5217SJeff Kirsher switch (idx) { 2231adfc5217SJeff Kirsher case 0: 2232adfc5217SJeff Kirsher wr_val = 0; 2233adfc5217SJeff Kirsher break; 2234adfc5217SJeff Kirsher case 1: 2235adfc5217SJeff Kirsher wr_val = 0xffffffff; 2236adfc5217SJeff Kirsher break; 2237adfc5217SJeff Kirsher } 2238adfc5217SJeff Kirsher 2239adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2240adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 2241adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 2242adfc5217SJeff Kirsher continue; 2243adfc5217SJeff Kirsher 2244adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2245adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 2246adfc5217SJeff Kirsher 2247adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 2248adfc5217SJeff Kirsher 2249adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 2250adfc5217SJeff Kirsher 2251adfc5217SJeff Kirsher val = REG_RD(bp, offset); 2252adfc5217SJeff Kirsher 2253adfc5217SJeff Kirsher /* Restore the original register's value */ 2254adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 2255adfc5217SJeff Kirsher 2256adfc5217SJeff Kirsher /* verify value is as expected */ 2257adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 225851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2259adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2260adfc5217SJeff Kirsher offset, val, wr_val, mask); 2261adfc5217SJeff Kirsher goto test_reg_exit; 2262adfc5217SJeff Kirsher } 2263adfc5217SJeff Kirsher } 2264adfc5217SJeff Kirsher } 2265adfc5217SJeff Kirsher 2266adfc5217SJeff Kirsher rc = 0; 2267adfc5217SJeff Kirsher 2268adfc5217SJeff Kirsher test_reg_exit: 2269adfc5217SJeff Kirsher return rc; 2270adfc5217SJeff Kirsher } 2271adfc5217SJeff Kirsher 2272adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 2273adfc5217SJeff Kirsher { 2274adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 2275adfc5217SJeff Kirsher u32 val, index; 2276adfc5217SJeff Kirsher static const struct { 2277adfc5217SJeff Kirsher u32 offset; 2278adfc5217SJeff Kirsher int size; 2279adfc5217SJeff Kirsher } mem_tbl[] = { 2280adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2281adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2282adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2283adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2284adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2285adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2286adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2287adfc5217SJeff Kirsher 2288adfc5217SJeff Kirsher { 0xffffffff, 0 } 2289adfc5217SJeff Kirsher }; 2290adfc5217SJeff Kirsher 2291adfc5217SJeff Kirsher static const struct { 2292adfc5217SJeff Kirsher char *name; 2293adfc5217SJeff Kirsher u32 offset; 2294adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2295adfc5217SJeff Kirsher } prty_tbl[] = { 2296adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2297adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2298adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2299adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 2300adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2301adfc5217SJeff Kirsher {0, 0, 0, 0} }, 2302adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2303adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2304adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2305adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2306adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2307adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 2308adfc5217SJeff Kirsher 2309adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 2310adfc5217SJeff Kirsher }; 2311adfc5217SJeff Kirsher 23123fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 231351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 231451c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2315adfc5217SJeff Kirsher return rc; 231651c1a580SMerav Sicron } 2317adfc5217SJeff Kirsher 2318adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2319adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 2320adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2321adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 2322adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2323adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 2324adfc5217SJeff Kirsher else /* e3 */ 2325adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 2326adfc5217SJeff Kirsher 2327adfc5217SJeff Kirsher /* pre-Check the parity status */ 2328adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2329adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2330adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 233151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2332adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2333adfc5217SJeff Kirsher goto test_mem_exit; 2334adfc5217SJeff Kirsher } 2335adfc5217SJeff Kirsher } 2336adfc5217SJeff Kirsher 2337adfc5217SJeff Kirsher /* Go through all the memories */ 2338adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2339adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 2340adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 2341adfc5217SJeff Kirsher 2342adfc5217SJeff Kirsher /* Check the parity status */ 2343adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2344adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2345adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 234651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2347adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2348adfc5217SJeff Kirsher goto test_mem_exit; 2349adfc5217SJeff Kirsher } 2350adfc5217SJeff Kirsher } 2351adfc5217SJeff Kirsher 2352adfc5217SJeff Kirsher rc = 0; 2353adfc5217SJeff Kirsher 2354adfc5217SJeff Kirsher test_mem_exit: 2355adfc5217SJeff Kirsher return rc; 2356adfc5217SJeff Kirsher } 2357adfc5217SJeff Kirsher 2358adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2359adfc5217SJeff Kirsher { 2360adfc5217SJeff Kirsher int cnt = 1400; 2361adfc5217SJeff Kirsher 2362adfc5217SJeff Kirsher if (link_up) { 2363adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2364adfc5217SJeff Kirsher msleep(20); 2365adfc5217SJeff Kirsher 2366adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 236751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 23688970b2e4SMerav Sicron 23698970b2e4SMerav Sicron cnt = 1400; 23708970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 23718970b2e4SMerav Sicron msleep(20); 23728970b2e4SMerav Sicron 23738970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 23748970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 23758970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2376adfc5217SJeff Kirsher } 2377adfc5217SJeff Kirsher } 2378adfc5217SJeff Kirsher 2379adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2380adfc5217SJeff Kirsher { 2381adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2382adfc5217SJeff Kirsher struct sk_buff *skb; 2383adfc5217SJeff Kirsher unsigned char *packet; 2384adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2385adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 238665565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2387adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2388adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2389b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2390adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2391adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2392adfc5217SJeff Kirsher dma_addr_t mapping; 2393adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2394adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2395adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2396adfc5217SJeff Kirsher u16 len; 2397adfc5217SJeff Kirsher int rc = -ENODEV; 2398e52fcb24SEric Dumazet u8 *data; 23998970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 24008970b2e4SMerav Sicron txdata->txq_index); 2401adfc5217SJeff Kirsher 2402adfc5217SJeff Kirsher /* check the loopback mode */ 2403adfc5217SJeff Kirsher switch (loopback_mode) { 2404adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 24058970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 24068970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2407adfc5217SJeff Kirsher return -EINVAL; 24088970b2e4SMerav Sicron } 2409adfc5217SJeff Kirsher break; 2410adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 241132911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 241232911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 241332911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 241432911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 241532911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 241632911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 241732911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 241832911333SYaniv Rosner else 241932911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 242032911333SYaniv Rosner } else 242132911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 242232911333SYaniv Rosner 2423adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2424adfc5217SJeff Kirsher break; 24258970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 24268970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 24278970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24288970b2e4SMerav Sicron "Can't configure external loopback\n"); 24298970b2e4SMerav Sicron return -EINVAL; 24308970b2e4SMerav Sicron } 24318970b2e4SMerav Sicron break; 2432adfc5217SJeff Kirsher default: 243351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2434adfc5217SJeff Kirsher return -EINVAL; 2435adfc5217SJeff Kirsher } 2436adfc5217SJeff Kirsher 2437adfc5217SJeff Kirsher /* prepare the loopback packet */ 2438adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2439adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2440adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2441adfc5217SJeff Kirsher if (!skb) { 244251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2443adfc5217SJeff Kirsher rc = -ENOMEM; 2444adfc5217SJeff Kirsher goto test_loopback_exit; 2445adfc5217SJeff Kirsher } 2446adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2447adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2448adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 2449adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2450adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2451adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2452adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2453adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2454adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2455adfc5217SJeff Kirsher rc = -ENOMEM; 2456adfc5217SJeff Kirsher dev_kfree_skb(skb); 245751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2458adfc5217SJeff Kirsher goto test_loopback_exit; 2459adfc5217SJeff Kirsher } 2460adfc5217SJeff Kirsher 2461adfc5217SJeff Kirsher /* send the loopback packet */ 2462adfc5217SJeff Kirsher num_pkts = 0; 2463adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2464adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2465adfc5217SJeff Kirsher 246673dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 246773dbb5e1SDmitry Kravkov 2468adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2469adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2470adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2471adfc5217SJeff Kirsher tx_buf->skb = skb; 2472adfc5217SJeff Kirsher tx_buf->flags = 0; 2473adfc5217SJeff Kirsher 2474adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2475adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2476adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2477adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2478adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2479adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2480adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2481adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2482adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2483adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2484adfc5217SJeff Kirsher 1); 248596bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 248696bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 248796bed4b9SYuval Mintz 0); 2488adfc5217SJeff Kirsher 2489adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2490adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2491adfc5217SJeff Kirsher 249296bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 249396bed4b9SYuval Mintz u16 global_data = 0; 249496bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 249596bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2496adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 249796bed4b9SYuval Mintz SET_FLAG(global_data, 249896bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 249996bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 250096bed4b9SYuval Mintz } else { 250196bed4b9SYuval Mintz u32 parsing_data = 0; 250296bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 250396bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 250496bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 250596bed4b9SYuval Mintz SET_FLAG(parsing_data, 250696bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 250796bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 250896bed4b9SYuval Mintz } 2509adfc5217SJeff Kirsher wmb(); 2510adfc5217SJeff Kirsher 2511adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2512adfc5217SJeff Kirsher barrier(); 2513adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2514adfc5217SJeff Kirsher 2515adfc5217SJeff Kirsher mmiowb(); 2516adfc5217SJeff Kirsher barrier(); 2517adfc5217SJeff Kirsher 2518adfc5217SJeff Kirsher num_pkts++; 2519adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2520adfc5217SJeff Kirsher 2521adfc5217SJeff Kirsher udelay(100); 2522adfc5217SJeff Kirsher 2523adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2524adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2525adfc5217SJeff Kirsher goto test_loopback_exit; 2526adfc5217SJeff Kirsher 2527adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2528adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2529adfc5217SJeff Kirsher * disabled. 2530adfc5217SJeff Kirsher */ 2531adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2532adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2533adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2534adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2535adfc5217SJeff Kirsher */ 2536adfc5217SJeff Kirsher local_bh_disable(); 2537adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2538adfc5217SJeff Kirsher local_bh_enable(); 2539adfc5217SJeff Kirsher } 2540adfc5217SJeff Kirsher 2541adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2542adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2543adfc5217SJeff Kirsher goto test_loopback_exit; 2544adfc5217SJeff Kirsher 2545b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2546adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2547adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2548adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2549adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2550adfc5217SJeff Kirsher 2551621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2552adfc5217SJeff Kirsher if (len != pkt_size) 2553adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2554adfc5217SJeff Kirsher 2555adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2556adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2557adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2558adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2559e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2560adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2561e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2562adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2563adfc5217SJeff Kirsher 2564adfc5217SJeff Kirsher rc = 0; 2565adfc5217SJeff Kirsher 2566adfc5217SJeff Kirsher test_loopback_rx_exit: 2567adfc5217SJeff Kirsher 2568adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2569adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2570adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2571adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2572adfc5217SJeff Kirsher 2573adfc5217SJeff Kirsher /* Update producers */ 2574adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2575adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2576adfc5217SJeff Kirsher 2577adfc5217SJeff Kirsher test_loopback_exit: 2578adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2579adfc5217SJeff Kirsher 2580adfc5217SJeff Kirsher return rc; 2581adfc5217SJeff Kirsher } 2582adfc5217SJeff Kirsher 2583adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2584adfc5217SJeff Kirsher { 2585adfc5217SJeff Kirsher int rc = 0, res; 2586adfc5217SJeff Kirsher 2587adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2588adfc5217SJeff Kirsher return rc; 2589adfc5217SJeff Kirsher 2590adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2591adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2592adfc5217SJeff Kirsher 2593adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2594adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2595adfc5217SJeff Kirsher 2596adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2597adfc5217SJeff Kirsher if (res) { 259851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2599adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2600adfc5217SJeff Kirsher } 2601adfc5217SJeff Kirsher 2602adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2603adfc5217SJeff Kirsher if (res) { 260451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2605adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2606adfc5217SJeff Kirsher } 2607adfc5217SJeff Kirsher 2608adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2609adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2610adfc5217SJeff Kirsher 2611adfc5217SJeff Kirsher return rc; 2612adfc5217SJeff Kirsher } 2613adfc5217SJeff Kirsher 26148970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 26158970b2e4SMerav Sicron { 26168970b2e4SMerav Sicron int rc; 26178970b2e4SMerav Sicron u8 is_serdes = 26188970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 26198970b2e4SMerav Sicron 26208970b2e4SMerav Sicron if (BP_NOMCP(bp)) 26218970b2e4SMerav Sicron return -ENODEV; 26228970b2e4SMerav Sicron 26238970b2e4SMerav Sicron if (!netif_running(bp->dev)) 26248970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 26258970b2e4SMerav Sicron 26265d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 26278970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 26288970b2e4SMerav Sicron if (rc) { 26298970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26308970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 26318970b2e4SMerav Sicron return -ENODEV; 26328970b2e4SMerav Sicron } 26338970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 26348970b2e4SMerav Sicron 26358970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 26368970b2e4SMerav Sicron 26378970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 26388970b2e4SMerav Sicron if (rc) 26398970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 26408970b2e4SMerav Sicron 26418970b2e4SMerav Sicron bnx2x_netif_start(bp); 26428970b2e4SMerav Sicron 26438970b2e4SMerav Sicron return rc; 26448970b2e4SMerav Sicron } 26458970b2e4SMerav Sicron 2646edb944d2SDmitry Kravkov struct code_entry { 2647edb944d2SDmitry Kravkov u32 sram_start_addr; 2648edb944d2SDmitry Kravkov u32 code_attribute; 2649edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_MASK 0xf0800003 2650edb944d2SDmitry Kravkov #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2651edb944d2SDmitry Kravkov #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2652edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2653edb944d2SDmitry Kravkov u32 nvm_start_addr; 2654edb944d2SDmitry Kravkov }; 2655edb944d2SDmitry Kravkov 2656edb944d2SDmitry Kravkov #define CODE_ENTRY_MAX 16 2657edb944d2SDmitry Kravkov #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2658edb944d2SDmitry Kravkov #define MAX_IMAGES_IN_EXTENDED_DIR 64 2659edb944d2SDmitry Kravkov #define NVRAM_DIR_OFFSET 0x14 2660edb944d2SDmitry Kravkov 2661edb944d2SDmitry Kravkov #define EXTENDED_DIR_EXISTS(code) \ 2662edb944d2SDmitry Kravkov ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2663edb944d2SDmitry Kravkov (code & CODE_IMAGE_LENGTH_MASK) != 0) 2664edb944d2SDmitry Kravkov 2665adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2666edb944d2SDmitry Kravkov #define CRC_BUFF_SIZE 256 2667edb944d2SDmitry Kravkov 2668edb944d2SDmitry Kravkov static int bnx2x_nvram_crc(struct bnx2x *bp, 2669edb944d2SDmitry Kravkov int offset, 2670edb944d2SDmitry Kravkov int size, 2671edb944d2SDmitry Kravkov u8 *buff) 2672edb944d2SDmitry Kravkov { 2673edb944d2SDmitry Kravkov u32 crc = ~0; 2674edb944d2SDmitry Kravkov int rc = 0, done = 0; 2675edb944d2SDmitry Kravkov 2676edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2677edb944d2SDmitry Kravkov "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2678edb944d2SDmitry Kravkov 2679edb944d2SDmitry Kravkov while (done < size) { 2680edb944d2SDmitry Kravkov int count = min_t(int, size - done, CRC_BUFF_SIZE); 2681edb944d2SDmitry Kravkov 2682edb944d2SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2683edb944d2SDmitry Kravkov 2684edb944d2SDmitry Kravkov if (rc) 2685edb944d2SDmitry Kravkov return rc; 2686edb944d2SDmitry Kravkov 2687edb944d2SDmitry Kravkov crc = crc32_le(crc, buff, count); 2688edb944d2SDmitry Kravkov done += count; 2689edb944d2SDmitry Kravkov } 2690edb944d2SDmitry Kravkov 2691edb944d2SDmitry Kravkov if (crc != CRC32_RESIDUAL) 2692edb944d2SDmitry Kravkov rc = -EINVAL; 2693edb944d2SDmitry Kravkov 2694edb944d2SDmitry Kravkov return rc; 2695edb944d2SDmitry Kravkov } 2696edb944d2SDmitry Kravkov 2697edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2698edb944d2SDmitry Kravkov struct code_entry *entry, 2699edb944d2SDmitry Kravkov u8 *buff) 2700edb944d2SDmitry Kravkov { 2701edb944d2SDmitry Kravkov size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2702edb944d2SDmitry Kravkov u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2703edb944d2SDmitry Kravkov int rc; 2704edb944d2SDmitry Kravkov 2705edb944d2SDmitry Kravkov /* Zero-length images and AFEX profiles do not have CRC */ 2706edb944d2SDmitry Kravkov if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2707edb944d2SDmitry Kravkov return 0; 2708edb944d2SDmitry Kravkov 2709edb944d2SDmitry Kravkov rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2710edb944d2SDmitry Kravkov if (rc) 2711edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2712edb944d2SDmitry Kravkov "image %x has failed crc test (rc %d)\n", type, rc); 2713edb944d2SDmitry Kravkov 2714edb944d2SDmitry Kravkov return rc; 2715edb944d2SDmitry Kravkov } 2716edb944d2SDmitry Kravkov 2717edb944d2SDmitry Kravkov static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2718edb944d2SDmitry Kravkov { 2719edb944d2SDmitry Kravkov int rc; 2720edb944d2SDmitry Kravkov struct code_entry entry; 2721edb944d2SDmitry Kravkov 2722edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2723edb944d2SDmitry Kravkov if (rc) 2724edb944d2SDmitry Kravkov return rc; 2725edb944d2SDmitry Kravkov 2726edb944d2SDmitry Kravkov return bnx2x_test_nvram_dir(bp, &entry, buff); 2727edb944d2SDmitry Kravkov } 2728edb944d2SDmitry Kravkov 2729edb944d2SDmitry Kravkov static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2730edb944d2SDmitry Kravkov { 2731edb944d2SDmitry Kravkov u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2732edb944d2SDmitry Kravkov struct code_entry entry; 2733edb944d2SDmitry Kravkov int i; 2734edb944d2SDmitry Kravkov 2735edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 2736edb944d2SDmitry Kravkov dir_offset + 2737edb944d2SDmitry Kravkov sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2738edb944d2SDmitry Kravkov (u32 *)&entry, sizeof(entry)); 2739edb944d2SDmitry Kravkov if (rc) 2740edb944d2SDmitry Kravkov return rc; 2741edb944d2SDmitry Kravkov 2742edb944d2SDmitry Kravkov if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2743edb944d2SDmitry Kravkov return 0; 2744edb944d2SDmitry Kravkov 2745edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2746edb944d2SDmitry Kravkov &cnt, sizeof(u32)); 2747edb944d2SDmitry Kravkov if (rc) 2748edb944d2SDmitry Kravkov return rc; 2749edb944d2SDmitry Kravkov 2750edb944d2SDmitry Kravkov dir_offset = entry.nvm_start_addr + 8; 2751edb944d2SDmitry Kravkov 2752edb944d2SDmitry Kravkov for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2753edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2754edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2755edb944d2SDmitry Kravkov buff); 2756edb944d2SDmitry Kravkov if (rc) 2757edb944d2SDmitry Kravkov return rc; 2758edb944d2SDmitry Kravkov } 2759edb944d2SDmitry Kravkov 2760edb944d2SDmitry Kravkov return 0; 2761edb944d2SDmitry Kravkov } 2762edb944d2SDmitry Kravkov 2763edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2764edb944d2SDmitry Kravkov { 2765edb944d2SDmitry Kravkov u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2766edb944d2SDmitry Kravkov int i; 2767edb944d2SDmitry Kravkov 2768edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2769edb944d2SDmitry Kravkov 2770edb944d2SDmitry Kravkov for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2771edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2772edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2773edb944d2SDmitry Kravkov buff); 2774edb944d2SDmitry Kravkov if (rc) 2775edb944d2SDmitry Kravkov return rc; 2776edb944d2SDmitry Kravkov } 2777edb944d2SDmitry Kravkov 2778edb944d2SDmitry Kravkov return bnx2x_test_nvram_ext_dirs(bp, buff); 2779edb944d2SDmitry Kravkov } 2780edb944d2SDmitry Kravkov 2781edb944d2SDmitry Kravkov struct crc_pair { 2782edb944d2SDmitry Kravkov int offset; 2783edb944d2SDmitry Kravkov int size; 2784edb944d2SDmitry Kravkov }; 2785edb944d2SDmitry Kravkov 2786edb944d2SDmitry Kravkov static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2787edb944d2SDmitry Kravkov const struct crc_pair *nvram_tbl, u8 *buf) 2788edb944d2SDmitry Kravkov { 2789edb944d2SDmitry Kravkov int i; 2790edb944d2SDmitry Kravkov 2791edb944d2SDmitry Kravkov for (i = 0; nvram_tbl[i].size; i++) { 2792edb944d2SDmitry Kravkov int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2793edb944d2SDmitry Kravkov nvram_tbl[i].size, buf); 2794edb944d2SDmitry Kravkov if (rc) { 2795edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2796edb944d2SDmitry Kravkov "nvram_tbl[%d] has failed crc test (rc %d)\n", 2797edb944d2SDmitry Kravkov i, rc); 2798edb944d2SDmitry Kravkov return rc; 2799edb944d2SDmitry Kravkov } 2800edb944d2SDmitry Kravkov } 2801edb944d2SDmitry Kravkov 2802edb944d2SDmitry Kravkov return 0; 2803edb944d2SDmitry Kravkov } 2804adfc5217SJeff Kirsher 2805adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2806adfc5217SJeff Kirsher { 2807edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl[] = { 2808adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2809adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2810adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2811adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2812adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2813adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2814adfc5217SJeff Kirsher { 0, 0 } 2815adfc5217SJeff Kirsher }; 2816edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl2[] = { 2817edb944d2SDmitry Kravkov { 0x7e8, 0x350 }, /* manuf_info2 */ 2818edb944d2SDmitry Kravkov { 0xb38, 0xf0 }, /* feature_info */ 2819edb944d2SDmitry Kravkov { 0, 0 } 2820edb944d2SDmitry Kravkov }; 2821edb944d2SDmitry Kravkov 282285640952SDmitry Kravkov u8 *buf; 2823edb944d2SDmitry Kravkov int rc; 2824edb944d2SDmitry Kravkov u32 magic; 2825adfc5217SJeff Kirsher 2826adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2827adfc5217SJeff Kirsher return 0; 2828adfc5217SJeff Kirsher 2829edb944d2SDmitry Kravkov buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2830afa13b4bSMintz Yuval if (!buf) { 283151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2832afa13b4bSMintz Yuval rc = -ENOMEM; 2833afa13b4bSMintz Yuval goto test_nvram_exit; 2834afa13b4bSMintz Yuval } 2835afa13b4bSMintz Yuval 283685640952SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2837adfc5217SJeff Kirsher if (rc) { 283851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 283951c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2840adfc5217SJeff Kirsher goto test_nvram_exit; 2841adfc5217SJeff Kirsher } 2842adfc5217SJeff Kirsher 2843adfc5217SJeff Kirsher if (magic != 0x669955aa) { 284451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 284551c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2846adfc5217SJeff Kirsher rc = -ENODEV; 2847adfc5217SJeff Kirsher goto test_nvram_exit; 2848adfc5217SJeff Kirsher } 2849adfc5217SJeff Kirsher 2850edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2851edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2852edb944d2SDmitry Kravkov if (rc) 2853adfc5217SJeff Kirsher goto test_nvram_exit; 2854adfc5217SJeff Kirsher 2855edb944d2SDmitry Kravkov if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2856edb944d2SDmitry Kravkov u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2857edb944d2SDmitry Kravkov SHARED_HW_CFG_HIDE_PORT1; 2858edb944d2SDmitry Kravkov 2859edb944d2SDmitry Kravkov if (!hide) { 286051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2861edb944d2SDmitry Kravkov "Port 1 CRC test-set\n"); 2862edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2863edb944d2SDmitry Kravkov if (rc) 2864adfc5217SJeff Kirsher goto test_nvram_exit; 2865adfc5217SJeff Kirsher } 2866adfc5217SJeff Kirsher } 2867adfc5217SJeff Kirsher 2868edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_dirs(bp, buf); 2869edb944d2SDmitry Kravkov 2870adfc5217SJeff Kirsher test_nvram_exit: 2871afa13b4bSMintz Yuval kfree(buf); 2872adfc5217SJeff Kirsher return rc; 2873adfc5217SJeff Kirsher } 2874adfc5217SJeff Kirsher 2875adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2876adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2877adfc5217SJeff Kirsher { 28783b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2879adfc5217SJeff Kirsher 288051c1a580SMerav Sicron if (!netif_running(bp->dev)) { 288151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 288251c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2883adfc5217SJeff Kirsher return -ENODEV; 288451c1a580SMerav Sicron } 2885adfc5217SJeff Kirsher 288615192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2887adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2888adfc5217SJeff Kirsher 2889adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2890adfc5217SJeff Kirsher 2891adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2892adfc5217SJeff Kirsher } 2893adfc5217SJeff Kirsher 2894adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2895adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2896adfc5217SJeff Kirsher { 2897adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2898a336ca7cSYaniv Rosner u8 is_serdes, link_up; 2899a336ca7cSYaniv Rosner int rc, cnt = 0; 2900cf2c1df6SMerav Sicron 2901adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 290251c1a580SMerav Sicron netdev_err(bp->dev, 290351c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2904adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2905adfc5217SJeff Kirsher return; 2906adfc5217SJeff Kirsher } 29072de67439SYuval Mintz 29088970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29098970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 29108970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 29118970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2912adfc5217SJeff Kirsher 2913cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2914adfc5217SJeff Kirsher 2915bd8e012bSYuval Mintz if (bnx2x_test_nvram(bp) != 0) { 2916bd8e012bSYuval Mintz if (!IS_MF(bp)) 2917bd8e012bSYuval Mintz buf[4] = 1; 2918bd8e012bSYuval Mintz else 2919bd8e012bSYuval Mintz buf[0] = 1; 2920bd8e012bSYuval Mintz etest->flags |= ETH_TEST_FL_FAILED; 2921bd8e012bSYuval Mintz } 2922bd8e012bSYuval Mintz 2923cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2924bd8e012bSYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2925adfc5217SJeff Kirsher return; 2926cf2c1df6SMerav Sicron } 2927adfc5217SJeff Kirsher 2928adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2929a336ca7cSYaniv Rosner link_up = bp->link_vars.link_up; 2930cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2931cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2932adfc5217SJeff Kirsher int port = BP_PORT(bp); 2933adfc5217SJeff Kirsher u32 val; 2934adfc5217SJeff Kirsher 2935adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2936adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2937adfc5217SJeff Kirsher /* disable input for TX port IF */ 2938adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2939adfc5217SJeff Kirsher 29405d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2941cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2942cf2c1df6SMerav Sicron if (rc) { 2943cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2944cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2945cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2946cf2c1df6SMerav Sicron return; 2947cf2c1df6SMerav Sicron } 2948cf2c1df6SMerav Sicron 2949adfc5217SJeff Kirsher /* wait until link state is restored */ 2950adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2951adfc5217SJeff Kirsher 2952adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2953adfc5217SJeff Kirsher buf[0] = 1; 2954adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2955adfc5217SJeff Kirsher } 2956adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2957adfc5217SJeff Kirsher buf[1] = 1; 2958adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2959adfc5217SJeff Kirsher } 2960adfc5217SJeff Kirsher 29618970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2962adfc5217SJeff Kirsher if (buf[2] != 0) 2963adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2964adfc5217SJeff Kirsher 29658970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 29668970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 29678970b2e4SMerav Sicron if (buf[3] != 0) 29688970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 29698970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 29708970b2e4SMerav Sicron } 29718970b2e4SMerav Sicron 29725d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2973adfc5217SJeff Kirsher 2974adfc5217SJeff Kirsher /* restore input for TX port IF */ 2975adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2976cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2977cf2c1df6SMerav Sicron if (rc) { 2978cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2979cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2980cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 2981cf2c1df6SMerav Sicron return; 2982cf2c1df6SMerav Sicron } 2983adfc5217SJeff Kirsher /* wait until link state is restored */ 2984adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2985adfc5217SJeff Kirsher } 2986bd8e012bSYuval Mintz 2987adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2988cf2c1df6SMerav Sicron if (!IS_MF(bp)) 29898970b2e4SMerav Sicron buf[5] = 1; 2990cf2c1df6SMerav Sicron else 2991cf2c1df6SMerav Sicron buf[1] = 1; 2992adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2993adfc5217SJeff Kirsher } 2994adfc5217SJeff Kirsher 2995a336ca7cSYaniv Rosner if (link_up) { 2996a336ca7cSYaniv Rosner cnt = 100; 2997a336ca7cSYaniv Rosner while (bnx2x_link_test(bp, is_serdes) && --cnt) 2998a336ca7cSYaniv Rosner msleep(20); 2999a336ca7cSYaniv Rosner } 3000a336ca7cSYaniv Rosner 3001a336ca7cSYaniv Rosner if (!cnt) { 3002cf2c1df6SMerav Sicron if (!IS_MF(bp)) 30038970b2e4SMerav Sicron buf[6] = 1; 3004cf2c1df6SMerav Sicron else 3005cf2c1df6SMerav Sicron buf[2] = 1; 3006adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 3007adfc5217SJeff Kirsher } 3008adfc5217SJeff Kirsher } 3009adfc5217SJeff Kirsher 3010adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 3011adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 3012adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 3013d8361051SYuval Mintz #define HIDE_PORT_STAT(bp) \ 3014d8361051SYuval Mintz ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \ 3015d8361051SYuval Mintz IS_VF(bp)) 3016adfc5217SJeff Kirsher 3017adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 3018adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 3019adfc5217SJeff Kirsher */ 30201191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 3021adfc5217SJeff Kirsher { 3022adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 3023adfc5217SJeff Kirsher } 3024adfc5217SJeff Kirsher 3025adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3026adfc5217SJeff Kirsher { 3027adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 30283521b419SYuval Mintz int i, num_strings = 0; 3029adfc5217SJeff Kirsher 3030adfc5217SJeff Kirsher switch (stringset) { 3031adfc5217SJeff Kirsher case ETH_SS_STATS: 3032adfc5217SJeff Kirsher if (is_multi(bp)) { 30333521b419SYuval Mintz num_strings = bnx2x_num_stat_queues(bp) * 3034adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 3035d5e83632SYuval Mintz } else 30363521b419SYuval Mintz num_strings = 0; 3037d8361051SYuval Mintz if (HIDE_PORT_STAT(bp)) { 3038adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 3039adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 30403521b419SYuval Mintz num_strings++; 3041adfc5217SJeff Kirsher } else 30423521b419SYuval Mintz num_strings += BNX2X_NUM_STATS; 3043d5e83632SYuval Mintz 30443521b419SYuval Mintz return num_strings; 3045adfc5217SJeff Kirsher 3046adfc5217SJeff Kirsher case ETH_SS_TEST: 3047cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 3048adfc5217SJeff Kirsher 30493521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 30503521b419SYuval Mintz return BNX2X_PRI_FLAG_LEN; 30513521b419SYuval Mintz 3052adfc5217SJeff Kirsher default: 3053adfc5217SJeff Kirsher return -EINVAL; 3054adfc5217SJeff Kirsher } 3055adfc5217SJeff Kirsher } 3056adfc5217SJeff Kirsher 30573521b419SYuval Mintz static u32 bnx2x_get_private_flags(struct net_device *dev) 30583521b419SYuval Mintz { 30593521b419SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 30603521b419SYuval Mintz u32 flags = 0; 30613521b419SYuval Mintz 30623521b419SYuval Mintz flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 30633521b419SYuval Mintz flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 30643521b419SYuval Mintz flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 30653521b419SYuval Mintz 30663521b419SYuval Mintz return flags; 30673521b419SYuval Mintz } 30683521b419SYuval Mintz 3069adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3070adfc5217SJeff Kirsher { 3071adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 30725889335cSMerav Sicron int i, j, k, start; 3073adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 3074adfc5217SJeff Kirsher 3075adfc5217SJeff Kirsher switch (stringset) { 3076adfc5217SJeff Kirsher case ETH_SS_STATS: 3077adfc5217SJeff Kirsher k = 0; 3078d5e83632SYuval Mintz if (is_multi(bp)) { 3079adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 3080adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 3081adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 3082adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3083adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3084adfc5217SJeff Kirsher ETH_GSTRING_LEN, 3085adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 3086adfc5217SJeff Kirsher queue_name); 3087adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3088adfc5217SJeff Kirsher } 3089d5e83632SYuval Mintz } 3090d5e83632SYuval Mintz 3091adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3092d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3093adfc5217SJeff Kirsher continue; 3094d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3095adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 3096adfc5217SJeff Kirsher j++; 3097adfc5217SJeff Kirsher } 3098d5e83632SYuval Mintz 3099adfc5217SJeff Kirsher break; 3100adfc5217SJeff Kirsher 3101adfc5217SJeff Kirsher case ETH_SS_TEST: 3102cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 3103cf2c1df6SMerav Sicron if (!IS_MF(bp)) 3104cf2c1df6SMerav Sicron start = 0; 3105cf2c1df6SMerav Sicron else 3106cf2c1df6SMerav Sicron start = 4; 31075889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 31085889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 31093521b419SYuval Mintz break; 31103521b419SYuval Mintz 31113521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 31123521b419SYuval Mintz memcpy(buf, bnx2x_private_arr, 31133521b419SYuval Mintz ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 31143521b419SYuval Mintz break; 3115adfc5217SJeff Kirsher } 3116adfc5217SJeff Kirsher } 3117adfc5217SJeff Kirsher 3118adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 3119adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 3120adfc5217SJeff Kirsher { 3121adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3122adfc5217SJeff Kirsher u32 *hw_stats, *offset; 3123d5e83632SYuval Mintz int i, j, k = 0; 3124adfc5217SJeff Kirsher 3125adfc5217SJeff Kirsher if (is_multi(bp)) { 3126adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 312715192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3128adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3129adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 3130adfc5217SJeff Kirsher /* skip this counter */ 3131adfc5217SJeff Kirsher buf[k + j] = 0; 3132adfc5217SJeff Kirsher continue; 3133adfc5217SJeff Kirsher } 3134adfc5217SJeff Kirsher offset = (hw_stats + 3135adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 3136adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 3137adfc5217SJeff Kirsher /* 4-byte counter */ 3138adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 3139adfc5217SJeff Kirsher continue; 3140adfc5217SJeff Kirsher } 3141adfc5217SJeff Kirsher /* 8-byte counter */ 3142adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3143adfc5217SJeff Kirsher } 3144adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3145adfc5217SJeff Kirsher } 3146adfc5217SJeff Kirsher } 3147d5e83632SYuval Mintz 3148adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 3149adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3150d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3151adfc5217SJeff Kirsher continue; 3152adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 3153adfc5217SJeff Kirsher /* skip this counter */ 3154d5e83632SYuval Mintz buf[k + j] = 0; 3155adfc5217SJeff Kirsher j++; 3156adfc5217SJeff Kirsher continue; 3157adfc5217SJeff Kirsher } 3158adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 3159adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 3160adfc5217SJeff Kirsher /* 4-byte counter */ 3161d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 3162adfc5217SJeff Kirsher j++; 3163adfc5217SJeff Kirsher continue; 3164adfc5217SJeff Kirsher } 3165adfc5217SJeff Kirsher /* 8-byte counter */ 3166d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3167adfc5217SJeff Kirsher j++; 3168adfc5217SJeff Kirsher } 3169adfc5217SJeff Kirsher } 3170adfc5217SJeff Kirsher 3171adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 3172adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 3173adfc5217SJeff Kirsher { 3174adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3175adfc5217SJeff Kirsher 31763fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 317751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 317851c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 3179adfc5217SJeff Kirsher return -EAGAIN; 318051c1a580SMerav Sicron } 3181adfc5217SJeff Kirsher 3182adfc5217SJeff Kirsher switch (state) { 3183adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 3184adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 3185adfc5217SJeff Kirsher 3186adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 31878203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3188adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3189adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 31908203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3191adfc5217SJeff Kirsher break; 3192adfc5217SJeff Kirsher 3193adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 31948203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3195adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3196adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 31978203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3198adfc5217SJeff Kirsher break; 3199adfc5217SJeff Kirsher 3200adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 32018203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3202adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3203adfc5217SJeff Kirsher LED_MODE_OPER, 3204adfc5217SJeff Kirsher bp->link_vars.line_speed); 32058203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3206adfc5217SJeff Kirsher } 3207adfc5217SJeff Kirsher 3208adfc5217SJeff Kirsher return 0; 3209adfc5217SJeff Kirsher } 3210adfc5217SJeff Kirsher 32115d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 32125d317c6aSMerav Sicron { 32135d317c6aSMerav Sicron switch (info->flow_type) { 32145d317c6aSMerav Sicron case TCP_V4_FLOW: 32155d317c6aSMerav Sicron case TCP_V6_FLOW: 32165d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32175d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32185d317c6aSMerav Sicron break; 32195d317c6aSMerav Sicron case UDP_V4_FLOW: 32205d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 32215d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32225d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32235d317c6aSMerav Sicron else 32245d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32255d317c6aSMerav Sicron break; 32265d317c6aSMerav Sicron case UDP_V6_FLOW: 32275d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 32285d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 32295d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 32305d317c6aSMerav Sicron else 32315d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32325d317c6aSMerav Sicron break; 32335d317c6aSMerav Sicron case IPV4_FLOW: 32345d317c6aSMerav Sicron case IPV6_FLOW: 32355d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 32365d317c6aSMerav Sicron break; 32375d317c6aSMerav Sicron default: 32385d317c6aSMerav Sicron info->data = 0; 32395d317c6aSMerav Sicron break; 32405d317c6aSMerav Sicron } 32415d317c6aSMerav Sicron 32425d317c6aSMerav Sicron return 0; 32435d317c6aSMerav Sicron } 32445d317c6aSMerav Sicron 3245adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3246815c7db5SBen Hutchings u32 *rules __always_unused) 3247adfc5217SJeff Kirsher { 3248adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3249adfc5217SJeff Kirsher 3250adfc5217SJeff Kirsher switch (info->cmd) { 3251adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 3252adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 3253adfc5217SJeff Kirsher return 0; 32545d317c6aSMerav Sicron case ETHTOOL_GRXFH: 32555d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 32565d317c6aSMerav Sicron default: 32575d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 32585d317c6aSMerav Sicron return -EOPNOTSUPP; 32595d317c6aSMerav Sicron } 32605d317c6aSMerav Sicron } 3261adfc5217SJeff Kirsher 32625d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 32635d317c6aSMerav Sicron { 32645d317c6aSMerav Sicron int udp_rss_requested; 32655d317c6aSMerav Sicron 32665d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32675d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 32685d317c6aSMerav Sicron info->flow_type, info->data); 32695d317c6aSMerav Sicron 32705d317c6aSMerav Sicron switch (info->flow_type) { 32715d317c6aSMerav Sicron case TCP_V4_FLOW: 32725d317c6aSMerav Sicron case TCP_V6_FLOW: 32735d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 32745d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 32755d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 32765d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32775d317c6aSMerav Sicron "Command parameters not supported\n"); 32785d317c6aSMerav Sicron return -EINVAL; 32795d317c6aSMerav Sicron } 32802de67439SYuval Mintz return 0; 32815d317c6aSMerav Sicron 32825d317c6aSMerav Sicron case UDP_V4_FLOW: 32835d317c6aSMerav Sicron case UDP_V6_FLOW: 32845d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 32855d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 32865d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 32875d317c6aSMerav Sicron udp_rss_requested = 1; 32885d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 32895d317c6aSMerav Sicron udp_rss_requested = 0; 32905d317c6aSMerav Sicron else 32915d317c6aSMerav Sicron return -EINVAL; 32925d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 32935d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 32945d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 32955d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32965d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 32975d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 329860cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 32995d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 33005d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 33015d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 33025d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33035d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 33045d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 330560cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 33065d317c6aSMerav Sicron } 3307924d75abSYuval Mintz return 0; 3308924d75abSYuval Mintz 33095d317c6aSMerav Sicron case IPV4_FLOW: 33105d317c6aSMerav Sicron case IPV6_FLOW: 33115d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 33125d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 33135d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33145d317c6aSMerav Sicron "Command parameters not supported\n"); 33155d317c6aSMerav Sicron return -EINVAL; 33165d317c6aSMerav Sicron } 3317924d75abSYuval Mintz return 0; 3318924d75abSYuval Mintz 33195d317c6aSMerav Sicron case SCTP_V4_FLOW: 33205d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 33215d317c6aSMerav Sicron case AH_V4_FLOW: 33225d317c6aSMerav Sicron case ESP_V4_FLOW: 33235d317c6aSMerav Sicron case SCTP_V6_FLOW: 33245d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 33255d317c6aSMerav Sicron case AH_V6_FLOW: 33265d317c6aSMerav Sicron case ESP_V6_FLOW: 33275d317c6aSMerav Sicron case IP_USER_FLOW: 33285d317c6aSMerav Sicron case ETHER_FLOW: 33295d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 33305d317c6aSMerav Sicron if (info->data) { 33315d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33325d317c6aSMerav Sicron "Command parameters not supported\n"); 33335d317c6aSMerav Sicron return -EINVAL; 33345d317c6aSMerav Sicron } 3335924d75abSYuval Mintz return 0; 3336924d75abSYuval Mintz 33375d317c6aSMerav Sicron default: 33385d317c6aSMerav Sicron return -EINVAL; 33395d317c6aSMerav Sicron } 33405d317c6aSMerav Sicron } 33415d317c6aSMerav Sicron 33425d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 33435d317c6aSMerav Sicron { 33445d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 33455d317c6aSMerav Sicron 33465d317c6aSMerav Sicron switch (info->cmd) { 33475d317c6aSMerav Sicron case ETHTOOL_SRXFH: 33485d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 3349adfc5217SJeff Kirsher default: 335051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3351adfc5217SJeff Kirsher return -EOPNOTSUPP; 3352adfc5217SJeff Kirsher } 3353adfc5217SJeff Kirsher } 3354adfc5217SJeff Kirsher 33557850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3356adfc5217SJeff Kirsher { 335796305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 33587850f63fSBen Hutchings } 33597850f63fSBen Hutchings 3360fe62d001SBen Hutchings static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key) 33617850f63fSBen Hutchings { 33627850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 3363adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3364adfc5217SJeff Kirsher size_t i; 3365adfc5217SJeff Kirsher 3366adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 3367adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3368adfc5217SJeff Kirsher 3369adfc5217SJeff Kirsher /* 3370adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 3371adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 3372adfc5217SJeff Kirsher * points to an array of u32. 3373adfc5217SJeff Kirsher * 3374adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3375adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 3376adfc5217SJeff Kirsher * queue. 3377adfc5217SJeff Kirsher */ 33787850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 33797850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 3380adfc5217SJeff Kirsher 3381adfc5217SJeff Kirsher return 0; 3382adfc5217SJeff Kirsher } 3383adfc5217SJeff Kirsher 3384fe62d001SBen Hutchings static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3385fe62d001SBen Hutchings const u8 *key) 3386adfc5217SJeff Kirsher { 3387adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3388adfc5217SJeff Kirsher size_t i; 3389adfc5217SJeff Kirsher 3390adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3391adfc5217SJeff Kirsher /* 3392fe62d001SBen Hutchings * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3393adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 3394adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 3395adfc5217SJeff Kirsher * 3396adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3397adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 3398adfc5217SJeff Kirsher * queue 3399adfc5217SJeff Kirsher */ 34005d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3401adfc5217SJeff Kirsher } 3402adfc5217SJeff Kirsher 34035d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 3404adfc5217SJeff Kirsher } 3405adfc5217SJeff Kirsher 34060e8d2ec5SMerav Sicron /** 34070e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 34080e8d2ec5SMerav Sicron * 34090e8d2ec5SMerav Sicron * @dev: net device 34100e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 34110e8d2ec5SMerav Sicron */ 34120e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 34130e8d2ec5SMerav Sicron struct ethtool_channels *channels) 34140e8d2ec5SMerav Sicron { 34150e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34160e8d2ec5SMerav Sicron 34170e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 34180e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 34190e8d2ec5SMerav Sicron } 34200e8d2ec5SMerav Sicron 34210e8d2ec5SMerav Sicron /** 34220e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 34230e8d2ec5SMerav Sicron * 34240e8d2ec5SMerav Sicron * @bp: bnx2x private structure 34250e8d2ec5SMerav Sicron * 34260e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 34270e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 34280e8d2ec5SMerav Sicron */ 34290e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 34300e8d2ec5SMerav Sicron { 34310e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 343255c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 343355c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 343455c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 34350e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 34360e8d2ec5SMerav Sicron } 34370e8d2ec5SMerav Sicron 34380e8d2ec5SMerav Sicron /** 34390e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 34400e8d2ec5SMerav Sicron * 34410e8d2ec5SMerav Sicron * @dev: net device 34420e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 34430e8d2ec5SMerav Sicron */ 34440e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 34450e8d2ec5SMerav Sicron struct ethtool_channels *channels) 34460e8d2ec5SMerav Sicron { 34470e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34480e8d2ec5SMerav Sicron 34490e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34500e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 34510e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 34520e8d2ec5SMerav Sicron channels->combined_count); 34530e8d2ec5SMerav Sicron 34540e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 34550e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 34560e8d2ec5SMerav Sicron */ 34570e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 34580e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 34590e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 34600e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 34610e8d2ec5SMerav Sicron return -EINVAL; 34620e8d2ec5SMerav Sicron } 34630e8d2ec5SMerav Sicron 34640e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 34650e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 34660e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 34670e8d2ec5SMerav Sicron return 0; 34680e8d2ec5SMerav Sicron } 34690e8d2ec5SMerav Sicron 34700e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 34710e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 34720e8d2ec5SMerav Sicron * less than requested if memory is low. 34730e8d2ec5SMerav Sicron */ 34740e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 34750e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 34760e8d2ec5SMerav Sicron return 0; 34770e8d2ec5SMerav Sicron } 34785d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 34790e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 34800e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 34810e8d2ec5SMerav Sicron } 34820e8d2ec5SMerav Sicron 3483adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 3484adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 3485adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 3486adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 3487adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 3488adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 348907ba6af4SMiriam Shitrit .get_dump_flag = bnx2x_get_dump_flag, 349007ba6af4SMiriam Shitrit .get_dump_data = bnx2x_get_dump_data, 349107ba6af4SMiriam Shitrit .set_dump = bnx2x_set_dump, 3492adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 3493adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 3494adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 3495adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 3496adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 3497adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 3498adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 3499adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 3500adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 3501adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 3502adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 3503adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 3504adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 3505adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 3506adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 3507adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 3508adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 35093521b419SYuval Mintz .get_priv_flags = bnx2x_get_private_flags, 3510adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 3511adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 3512adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 3513adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 35145d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 35157850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3516fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3517fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 35180e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 35190e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 352024ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 352124ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3522e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3523e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3524be53ce1eSRichard Cochran .get_ts_info = ethtool_op_get_ts_info, 3525adfc5217SJeff Kirsher }; 3526adfc5217SJeff Kirsher 3527005a07baSAriel Elior static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 35286495d15aSDmitry Kravkov .get_settings = bnx2x_get_vf_settings, 3529005a07baSAriel Elior .get_drvinfo = bnx2x_get_drvinfo, 3530005a07baSAriel Elior .get_msglevel = bnx2x_get_msglevel, 3531005a07baSAriel Elior .set_msglevel = bnx2x_set_msglevel, 3532005a07baSAriel Elior .get_link = bnx2x_get_link, 3533005a07baSAriel Elior .get_coalesce = bnx2x_get_coalesce, 3534005a07baSAriel Elior .get_ringparam = bnx2x_get_ringparam, 3535005a07baSAriel Elior .set_ringparam = bnx2x_set_ringparam, 3536005a07baSAriel Elior .get_sset_count = bnx2x_get_sset_count, 3537005a07baSAriel Elior .get_strings = bnx2x_get_strings, 3538005a07baSAriel Elior .get_ethtool_stats = bnx2x_get_ethtool_stats, 3539005a07baSAriel Elior .get_rxnfc = bnx2x_get_rxnfc, 3540005a07baSAriel Elior .set_rxnfc = bnx2x_set_rxnfc, 3541005a07baSAriel Elior .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3542fe62d001SBen Hutchings .get_rxfh = bnx2x_get_rxfh, 3543fe62d001SBen Hutchings .set_rxfh = bnx2x_set_rxfh, 3544005a07baSAriel Elior .get_channels = bnx2x_get_channels, 3545005a07baSAriel Elior .set_channels = bnx2x_set_channels, 3546005a07baSAriel Elior }; 3547005a07baSAriel Elior 3548005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3549adfc5217SJeff Kirsher { 35507ad24ea4SWilfried Klaebe netdev->ethtool_ops = (IS_PF(bp)) ? 35517ad24ea4SWilfried Klaebe &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3552adfc5217SJeff Kirsher } 3553