1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 385b26ea1SAriel Elior * Copyright (c) 2007-2012 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher #include "bnx2x.h" 26adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 27adfc5217SJeff Kirsher #include "bnx2x_dump.h" 28adfc5217SJeff Kirsher #include "bnx2x_init.h" 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 31adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33adfc5217SJeff Kirsher */ 34adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 35adfc5217SJeff Kirsher static const struct { 36adfc5217SJeff Kirsher long offset; 37adfc5217SJeff Kirsher int size; 38adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 39adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 40adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 49adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53adfc5217SJeff Kirsher 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 65adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"} 66adfc5217SJeff Kirsher }; 67adfc5217SJeff Kirsher 68adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher static const struct { 71adfc5217SJeff Kirsher long offset; 72adfc5217SJeff Kirsher int size; 73adfc5217SJeff Kirsher u32 flags; 74adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 75adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 76adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 77adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 78adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 79adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 80adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 81adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 82adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 83adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 97adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 99adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 101adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 104adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 106adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1070e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1080e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1090e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1100e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 111adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 112adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 113adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 114adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 120adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 121adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 122adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 123adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 125adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 127adfc5217SJeff Kirsher 128adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 129adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 130adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 131adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 142adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 144adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 162adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 164adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1757a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1767a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1777a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1787a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1797a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 180e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 181e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 182adfc5217SJeff Kirsher }; 183adfc5217SJeff Kirsher 184adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 185adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 186adfc5217SJeff Kirsher { 187adfc5217SJeff Kirsher int port_type; 188adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 189adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 190adfc5217SJeff Kirsher case ETH_PHY_SFP_FIBER: 191adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 192adfc5217SJeff Kirsher case ETH_PHY_KR: 193adfc5217SJeff Kirsher case ETH_PHY_CX4: 194adfc5217SJeff Kirsher port_type = PORT_FIBRE; 195adfc5217SJeff Kirsher break; 196adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 197adfc5217SJeff Kirsher port_type = PORT_DA; 198adfc5217SJeff Kirsher break; 199adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 200adfc5217SJeff Kirsher port_type = PORT_TP; 201adfc5217SJeff Kirsher break; 202adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 203adfc5217SJeff Kirsher port_type = PORT_NONE; 204adfc5217SJeff Kirsher break; 205adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 206adfc5217SJeff Kirsher default: 207adfc5217SJeff Kirsher port_type = PORT_OTHER; 208adfc5217SJeff Kirsher break; 209adfc5217SJeff Kirsher } 210adfc5217SJeff Kirsher return port_type; 211adfc5217SJeff Kirsher } 212adfc5217SJeff Kirsher 213adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 214adfc5217SJeff Kirsher { 215adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 216adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 217adfc5217SJeff Kirsher 218adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 219adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 220adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 221adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 222adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 223adfc5217SJeff Kirsher 22438298461SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) { 22538298461SYuval Mintz if (!(bp->flags & MF_FUNC_DIS)) { 226adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 227adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 228adfc5217SJeff Kirsher } else { 229adfc5217SJeff Kirsher ethtool_cmd_speed_set( 230adfc5217SJeff Kirsher cmd, bp->link_params.req_line_speed[cfg_idx]); 231adfc5217SJeff Kirsher cmd->duplex = bp->link_params.req_duplex[cfg_idx]; 232adfc5217SJeff Kirsher } 233adfc5217SJeff Kirsher 23438298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 235adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 23638298461SYuval Mintz } else { 23738298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 23838298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 23938298461SYuval Mintz } 240adfc5217SJeff Kirsher 241adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 242adfc5217SJeff Kirsher 243adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 244adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 245adfc5217SJeff Kirsher 246adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 247adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 248adfc5217SJeff Kirsher else 249adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 250adfc5217SJeff Kirsher 2519e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2529e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2539e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2549e7e8399SMintz Yuval 2559e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 2569e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 2579e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 2589e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 2599e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 2609e7e8399SMintz Yuval 2619e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 2629e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 2639e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 2649e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 2659e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 2669e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 2679e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 2689e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 2699e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 2709e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 2719e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 2729e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 2739e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 2749e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 2759e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 2769e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 2779e7e8399SMintz Yuval } 2789e7e8399SMintz Yuval 279adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 280adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 281adfc5217SJeff Kirsher 28251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 283f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 284f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 285f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 286adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 287adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 288adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 289adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 290adfc5217SJeff Kirsher 291adfc5217SJeff Kirsher return 0; 292adfc5217SJeff Kirsher } 293adfc5217SJeff Kirsher 294adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 295adfc5217SJeff Kirsher { 296adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 297adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 298adfc5217SJeff Kirsher u32 speed; 299adfc5217SJeff Kirsher 300adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 301adfc5217SJeff Kirsher return 0; 302adfc5217SJeff Kirsher 30351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 304adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 305adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 306adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 307adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 308adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 309adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 310adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 311adfc5217SJeff Kirsher 312adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 313adfc5217SJeff Kirsher 31438298461SYuval Mintz /* If recieved a request for an unknown duplex, assume full*/ 31538298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 31638298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 31738298461SYuval Mintz 318adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 319adfc5217SJeff Kirsher u32 part; 320adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 321adfc5217SJeff Kirsher 322adfc5217SJeff Kirsher /* use 10G if no link detected */ 323adfc5217SJeff Kirsher if (!line_speed) 324adfc5217SJeff Kirsher line_speed = 10000; 325adfc5217SJeff Kirsher 326adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 32751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32851c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 329adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 330adfc5217SJeff Kirsher return -EINVAL; 331adfc5217SJeff Kirsher } 332adfc5217SJeff Kirsher 333adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 334adfc5217SJeff Kirsher 335adfc5217SJeff Kirsher if (line_speed < speed || !part) { 33651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33751c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 338adfc5217SJeff Kirsher return -EINVAL; 339adfc5217SJeff Kirsher } 340adfc5217SJeff Kirsher 341adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 342adfc5217SJeff Kirsher /* store value for following "load" */ 343adfc5217SJeff Kirsher bp->pending_max = part; 344adfc5217SJeff Kirsher else 345adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 346adfc5217SJeff Kirsher 347adfc5217SJeff Kirsher return 0; 348adfc5217SJeff Kirsher } 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 351adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 352adfc5217SJeff Kirsher switch (cmd->port) { 353adfc5217SJeff Kirsher case PORT_TP: 354adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 355adfc5217SJeff Kirsher break; /* no port change */ 356adfc5217SJeff Kirsher 357adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 358adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 35951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 360adfc5217SJeff Kirsher return -EINVAL; 361adfc5217SJeff Kirsher } 362adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 363adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 364adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 365adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 366adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 367adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 368adfc5217SJeff Kirsher else 369adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 370adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 371adfc5217SJeff Kirsher break; 372adfc5217SJeff Kirsher case PORT_FIBRE: 373bfdb5823SYaniv Rosner case PORT_DA: 374adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 375adfc5217SJeff Kirsher break; /* no port change */ 376adfc5217SJeff Kirsher 377adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 378adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 37951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 380adfc5217SJeff Kirsher return -EINVAL; 381adfc5217SJeff Kirsher } 382adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 383adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 384adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 385adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 386adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 387adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 388adfc5217SJeff Kirsher else 389adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 390adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 391adfc5217SJeff Kirsher break; 392adfc5217SJeff Kirsher default: 39351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 394adfc5217SJeff Kirsher return -EINVAL; 395adfc5217SJeff Kirsher } 3962f751a80SYaniv Rosner /* Save new config in case command complete successully */ 397adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 398adfc5217SJeff Kirsher /* Get the new cfg_idx */ 399adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 400adfc5217SJeff Kirsher /* Restore old config in case command failed */ 401adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 40251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 403adfc5217SJeff Kirsher 404adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 40575318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 40675318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 40775318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 40875318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 40975318327SYaniv Rosner SUPPORTED_100baseT_Full); 410adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 41151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 412adfc5217SJeff Kirsher return -EINVAL; 413adfc5217SJeff Kirsher } 414adfc5217SJeff Kirsher 415adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 41675318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 41751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 41851c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4198decf868SDavid S. Miller return -EINVAL; 4208decf868SDavid S. Miller } 421adfc5217SJeff Kirsher 422adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4238decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4248decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 425adfc5217SJeff Kirsher cmd->advertising); 4268decf868SDavid S. Miller if (cmd->advertising) { 427adfc5217SJeff Kirsher 4288decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4298decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4308decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4318decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4328decf868SDavid S. Miller } 4338decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4348decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4358decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4368decf868SDavid S. Miller 4378decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4388decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4398decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4408decf868SDavid S. Miller 4418decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4428decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4438decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4448decf868SDavid S. Miller } 4458decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4468decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4478decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4488decf868SDavid S. Miller } 4498decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4508decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4518decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4528decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4538decf868SDavid S. Miller 4548decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4558decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 4568decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 4578decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4588decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 4598decf868SDavid S. Miller } 460adfc5217SJeff Kirsher } else { /* forced speed */ 461adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 462adfc5217SJeff Kirsher switch (speed) { 463adfc5217SJeff Kirsher case SPEED_10: 464adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 465adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 466adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 46751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 468adfc5217SJeff Kirsher "10M full not supported\n"); 469adfc5217SJeff Kirsher return -EINVAL; 470adfc5217SJeff Kirsher } 471adfc5217SJeff Kirsher 472adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 473adfc5217SJeff Kirsher ADVERTISED_TP); 474adfc5217SJeff Kirsher } else { 475adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 476adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 47751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 478adfc5217SJeff Kirsher "10M half not supported\n"); 479adfc5217SJeff Kirsher return -EINVAL; 480adfc5217SJeff Kirsher } 481adfc5217SJeff Kirsher 482adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 483adfc5217SJeff Kirsher ADVERTISED_TP); 484adfc5217SJeff Kirsher } 485adfc5217SJeff Kirsher break; 486adfc5217SJeff Kirsher 487adfc5217SJeff Kirsher case SPEED_100: 488adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 489adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 490adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 49151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 492adfc5217SJeff Kirsher "100M full not supported\n"); 493adfc5217SJeff Kirsher return -EINVAL; 494adfc5217SJeff Kirsher } 495adfc5217SJeff Kirsher 496adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 497adfc5217SJeff Kirsher ADVERTISED_TP); 498adfc5217SJeff Kirsher } else { 499adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 500adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 50151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 502adfc5217SJeff Kirsher "100M half not supported\n"); 503adfc5217SJeff Kirsher return -EINVAL; 504adfc5217SJeff Kirsher } 505adfc5217SJeff Kirsher 506adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 507adfc5217SJeff Kirsher ADVERTISED_TP); 508adfc5217SJeff Kirsher } 509adfc5217SJeff Kirsher break; 510adfc5217SJeff Kirsher 511adfc5217SJeff Kirsher case SPEED_1000: 512adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 51351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 51451c1a580SMerav Sicron "1G half not supported\n"); 515adfc5217SJeff Kirsher return -EINVAL; 516adfc5217SJeff Kirsher } 517adfc5217SJeff Kirsher 518adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 519adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 52051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52151c1a580SMerav Sicron "1G full not supported\n"); 522adfc5217SJeff Kirsher return -EINVAL; 523adfc5217SJeff Kirsher } 524adfc5217SJeff Kirsher 525adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 526adfc5217SJeff Kirsher ADVERTISED_TP); 527adfc5217SJeff Kirsher break; 528adfc5217SJeff Kirsher 529adfc5217SJeff Kirsher case SPEED_2500: 530adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 53151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 532adfc5217SJeff Kirsher "2.5G half not supported\n"); 533adfc5217SJeff Kirsher return -EINVAL; 534adfc5217SJeff Kirsher } 535adfc5217SJeff Kirsher 536adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 537adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 53851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 539adfc5217SJeff Kirsher "2.5G full not supported\n"); 540adfc5217SJeff Kirsher return -EINVAL; 541adfc5217SJeff Kirsher } 542adfc5217SJeff Kirsher 543adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 544adfc5217SJeff Kirsher ADVERTISED_TP); 545adfc5217SJeff Kirsher break; 546adfc5217SJeff Kirsher 547adfc5217SJeff Kirsher case SPEED_10000: 548adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 54951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 55051c1a580SMerav Sicron "10G half not supported\n"); 551adfc5217SJeff Kirsher return -EINVAL; 552adfc5217SJeff Kirsher } 553adfc5217SJeff Kirsher 554adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 555adfc5217SJeff Kirsher & SUPPORTED_10000baseT_Full)) { 55651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 55751c1a580SMerav Sicron "10G full not supported\n"); 558adfc5217SJeff Kirsher return -EINVAL; 559adfc5217SJeff Kirsher } 560adfc5217SJeff Kirsher 561adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 562adfc5217SJeff Kirsher ADVERTISED_FIBRE); 563adfc5217SJeff Kirsher break; 564adfc5217SJeff Kirsher 565adfc5217SJeff Kirsher default: 56651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 567adfc5217SJeff Kirsher return -EINVAL; 568adfc5217SJeff Kirsher } 569adfc5217SJeff Kirsher 570adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 571adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 572adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 573adfc5217SJeff Kirsher } 574adfc5217SJeff Kirsher 57551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 576f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 577adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 578adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 579adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 580adfc5217SJeff Kirsher 581adfc5217SJeff Kirsher /* Set new config */ 582adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 583adfc5217SJeff Kirsher if (netif_running(dev)) { 584adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 585adfc5217SJeff Kirsher bnx2x_link_set(bp); 586adfc5217SJeff Kirsher } 587adfc5217SJeff Kirsher 588adfc5217SJeff Kirsher return 0; 589adfc5217SJeff Kirsher } 590adfc5217SJeff Kirsher 591adfc5217SJeff Kirsher #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) 592adfc5217SJeff Kirsher #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) 593adfc5217SJeff Kirsher #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) 594adfc5217SJeff Kirsher #define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE) 595adfc5217SJeff Kirsher #define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE) 596adfc5217SJeff Kirsher 5971191cb83SEric Dumazet static bool bnx2x_is_reg_online(struct bnx2x *bp, 598adfc5217SJeff Kirsher const struct reg_addr *reg_info) 599adfc5217SJeff Kirsher { 600adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 601adfc5217SJeff Kirsher return IS_E1_ONLINE(reg_info->info); 602adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 603adfc5217SJeff Kirsher return IS_E1H_ONLINE(reg_info->info); 604adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 605adfc5217SJeff Kirsher return IS_E2_ONLINE(reg_info->info); 606adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 607adfc5217SJeff Kirsher return IS_E3_ONLINE(reg_info->info); 608adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 609adfc5217SJeff Kirsher return IS_E3B0_ONLINE(reg_info->info); 610adfc5217SJeff Kirsher else 611adfc5217SJeff Kirsher return false; 612adfc5217SJeff Kirsher } 613adfc5217SJeff Kirsher 614adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 6151191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 616adfc5217SJeff Kirsher { 617adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 618adfc5217SJeff Kirsher return page_vals_e2; 619adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 620adfc5217SJeff Kirsher return page_vals_e3; 621adfc5217SJeff Kirsher else 622adfc5217SJeff Kirsher return NULL; 623adfc5217SJeff Kirsher } 624adfc5217SJeff Kirsher 6251191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 626adfc5217SJeff Kirsher { 627adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 628adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 629adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 630adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 631adfc5217SJeff Kirsher else 632adfc5217SJeff Kirsher return 0; 633adfc5217SJeff Kirsher } 634adfc5217SJeff Kirsher 6351191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 636adfc5217SJeff Kirsher { 637adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 638adfc5217SJeff Kirsher return page_write_regs_e2; 639adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 640adfc5217SJeff Kirsher return page_write_regs_e3; 641adfc5217SJeff Kirsher else 642adfc5217SJeff Kirsher return NULL; 643adfc5217SJeff Kirsher } 644adfc5217SJeff Kirsher 6451191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 646adfc5217SJeff Kirsher { 647adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 648adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 649adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 650adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 651adfc5217SJeff Kirsher else 652adfc5217SJeff Kirsher return 0; 653adfc5217SJeff Kirsher } 654adfc5217SJeff Kirsher 6551191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 656adfc5217SJeff Kirsher { 657adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 658adfc5217SJeff Kirsher return page_read_regs_e2; 659adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 660adfc5217SJeff Kirsher return page_read_regs_e3; 661adfc5217SJeff Kirsher else 662adfc5217SJeff Kirsher return NULL; 663adfc5217SJeff Kirsher } 664adfc5217SJeff Kirsher 6651191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 666adfc5217SJeff Kirsher { 667adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 668adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 669adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 670adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 671adfc5217SJeff Kirsher else 672adfc5217SJeff Kirsher return 0; 673adfc5217SJeff Kirsher } 674adfc5217SJeff Kirsher 6751191cb83SEric Dumazet static int __bnx2x_get_regs_len(struct bnx2x *bp) 676adfc5217SJeff Kirsher { 677adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 678adfc5217SJeff Kirsher int page_write_num = __bnx2x_get_page_write_num(bp); 679adfc5217SJeff Kirsher const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp); 680adfc5217SJeff Kirsher int page_read_num = __bnx2x_get_page_read_num(bp); 681adfc5217SJeff Kirsher int regdump_len = 0; 682adfc5217SJeff Kirsher int i, j, k; 683adfc5217SJeff Kirsher 684adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 685adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 686adfc5217SJeff Kirsher regdump_len += reg_addrs[i].size; 687adfc5217SJeff Kirsher 688adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) 689adfc5217SJeff Kirsher for (j = 0; j < page_write_num; j++) 690adfc5217SJeff Kirsher for (k = 0; k < page_read_num; k++) 691adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &page_read_addr[k])) 692adfc5217SJeff Kirsher regdump_len += page_read_addr[k].size; 693adfc5217SJeff Kirsher 694adfc5217SJeff Kirsher return regdump_len; 695adfc5217SJeff Kirsher } 696adfc5217SJeff Kirsher 697adfc5217SJeff Kirsher static int bnx2x_get_regs_len(struct net_device *dev) 698adfc5217SJeff Kirsher { 699adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 700adfc5217SJeff Kirsher int regdump_len = 0; 701adfc5217SJeff Kirsher 702adfc5217SJeff Kirsher regdump_len = __bnx2x_get_regs_len(bp); 703adfc5217SJeff Kirsher regdump_len *= 4; 704adfc5217SJeff Kirsher regdump_len += sizeof(struct dump_hdr); 705adfc5217SJeff Kirsher 706adfc5217SJeff Kirsher return regdump_len; 707adfc5217SJeff Kirsher } 708adfc5217SJeff Kirsher 709adfc5217SJeff Kirsher /** 710adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 711adfc5217SJeff Kirsher * 712adfc5217SJeff Kirsher * @bp device handle 713adfc5217SJeff Kirsher * @p output buffer 714adfc5217SJeff Kirsher * 715adfc5217SJeff Kirsher * Reads "paged" memories: memories that may only be read by first writing to a 716adfc5217SJeff Kirsher * specific address ("write address") and then reading from a specific address 717adfc5217SJeff Kirsher * ("read address"). There may be more than one write address per "page" and 718adfc5217SJeff Kirsher * more than one read address per write address. 719adfc5217SJeff Kirsher */ 7201191cb83SEric Dumazet static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p) 721adfc5217SJeff Kirsher { 722adfc5217SJeff Kirsher u32 i, j, k, n; 723adfc5217SJeff Kirsher /* addresses of the paged registers */ 724adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 725adfc5217SJeff Kirsher /* number of paged registers */ 726adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 727adfc5217SJeff Kirsher /* write addresses */ 728adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 729adfc5217SJeff Kirsher /* number of write addresses */ 730adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 731adfc5217SJeff Kirsher /* read addresses info */ 732adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 733adfc5217SJeff Kirsher /* number of read addresses */ 734adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 735adfc5217SJeff Kirsher 736adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 737adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 738adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 739adfc5217SJeff Kirsher for (k = 0; k < read_num; k++) 740adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &read_addr[k])) 741adfc5217SJeff Kirsher for (n = 0; n < 742adfc5217SJeff Kirsher read_addr[k].size; n++) 743adfc5217SJeff Kirsher *p++ = REG_RD(bp, 744adfc5217SJeff Kirsher read_addr[k].addr + n*4); 745adfc5217SJeff Kirsher } 746adfc5217SJeff Kirsher } 747adfc5217SJeff Kirsher } 748adfc5217SJeff Kirsher 7491191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 750adfc5217SJeff Kirsher { 751adfc5217SJeff Kirsher u32 i, j; 752adfc5217SJeff Kirsher 753adfc5217SJeff Kirsher /* Read the regular registers */ 754adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 755adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 756adfc5217SJeff Kirsher for (j = 0; j < reg_addrs[i].size; j++) 757adfc5217SJeff Kirsher *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 758adfc5217SJeff Kirsher 759adfc5217SJeff Kirsher /* Read "paged" registes */ 760adfc5217SJeff Kirsher bnx2x_read_pages_regs(bp, p); 761adfc5217SJeff Kirsher } 762adfc5217SJeff Kirsher 763adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 764adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 765adfc5217SJeff Kirsher { 766adfc5217SJeff Kirsher u32 *p = _p; 767adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 768adfc5217SJeff Kirsher struct dump_hdr dump_hdr = {0}; 769adfc5217SJeff Kirsher 770adfc5217SJeff Kirsher regs->version = 0; 771adfc5217SJeff Kirsher memset(p, 0, regs->len); 772adfc5217SJeff Kirsher 773adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 774adfc5217SJeff Kirsher return; 775adfc5217SJeff Kirsher 776adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 777adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 778adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 779adfc5217SJeff Kirsher */ 780adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 781adfc5217SJeff Kirsher 782adfc5217SJeff Kirsher dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; 783adfc5217SJeff Kirsher dump_hdr.dump_sign = dump_sign_all; 784adfc5217SJeff Kirsher dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); 785adfc5217SJeff Kirsher dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); 786adfc5217SJeff Kirsher dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); 787adfc5217SJeff Kirsher dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); 788adfc5217SJeff Kirsher 789adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 790adfc5217SJeff Kirsher dump_hdr.info = RI_E1_ONLINE; 791adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 792adfc5217SJeff Kirsher dump_hdr.info = RI_E1H_ONLINE; 793adfc5217SJeff Kirsher else if (!CHIP_IS_E1x(bp)) 794adfc5217SJeff Kirsher dump_hdr.info = RI_E2_ONLINE | 795adfc5217SJeff Kirsher (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); 796adfc5217SJeff Kirsher 797adfc5217SJeff Kirsher memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); 798adfc5217SJeff Kirsher p += dump_hdr.hdr_size + 1; 799adfc5217SJeff Kirsher 800adfc5217SJeff Kirsher /* Actually read the registers */ 801adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 802adfc5217SJeff Kirsher 803adfc5217SJeff Kirsher /* Re-enable parity attentions */ 804adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 805adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 806adfc5217SJeff Kirsher } 807adfc5217SJeff Kirsher 808adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 809adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 810adfc5217SJeff Kirsher { 811adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 812adfc5217SJeff Kirsher u8 phy_fw_ver[PHY_FW_VER_LEN]; 813adfc5217SJeff Kirsher 81468aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 81568aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 816adfc5217SJeff Kirsher 817adfc5217SJeff Kirsher phy_fw_ver[0] = '\0'; 818adfc5217SJeff Kirsher bnx2x_get_ext_phy_fw_version(&bp->link_params, 819adfc5217SJeff Kirsher phy_fw_ver, PHY_FW_VER_LEN); 82068aad78cSRick Jones strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version)); 821adfc5217SJeff Kirsher snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), 822adfc5217SJeff Kirsher "bc %d.%d.%d%s%s", 823adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff0000) >> 16, 824adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff00) >> 8, 825adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff), 826adfc5217SJeff Kirsher ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); 82768aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 828adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 829cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 830adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 831adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 832adfc5217SJeff Kirsher } 833adfc5217SJeff Kirsher 834adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 835adfc5217SJeff Kirsher { 836adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 837adfc5217SJeff Kirsher 838adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 839adfc5217SJeff Kirsher wol->supported = 0; 840adfc5217SJeff Kirsher wol->wolopts = 0; 841adfc5217SJeff Kirsher } else { 842adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 843adfc5217SJeff Kirsher if (bp->wol) 844adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 845adfc5217SJeff Kirsher else 846adfc5217SJeff Kirsher wol->wolopts = 0; 847adfc5217SJeff Kirsher } 848adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 849adfc5217SJeff Kirsher } 850adfc5217SJeff Kirsher 851adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 852adfc5217SJeff Kirsher { 853adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 854adfc5217SJeff Kirsher 85551c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 85651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); 857adfc5217SJeff Kirsher return -EINVAL; 85851c1a580SMerav Sicron } 859adfc5217SJeff Kirsher 860adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 86151c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 86251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); 863adfc5217SJeff Kirsher return -EINVAL; 86451c1a580SMerav Sicron } 865adfc5217SJeff Kirsher bp->wol = 1; 866adfc5217SJeff Kirsher } else 867adfc5217SJeff Kirsher bp->wol = 0; 868adfc5217SJeff Kirsher 869adfc5217SJeff Kirsher return 0; 870adfc5217SJeff Kirsher } 871adfc5217SJeff Kirsher 872adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 873adfc5217SJeff Kirsher { 874adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 875adfc5217SJeff Kirsher 876adfc5217SJeff Kirsher return bp->msg_enable; 877adfc5217SJeff Kirsher } 878adfc5217SJeff Kirsher 879adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 880adfc5217SJeff Kirsher { 881adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 882adfc5217SJeff Kirsher 883adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 884adfc5217SJeff Kirsher /* dump MCP trace */ 885adfc5217SJeff Kirsher if (level & BNX2X_MSG_MCP) 886adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 887adfc5217SJeff Kirsher bp->msg_enable = level; 888adfc5217SJeff Kirsher } 889adfc5217SJeff Kirsher } 890adfc5217SJeff Kirsher 891adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 892adfc5217SJeff Kirsher { 893adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 894adfc5217SJeff Kirsher 895adfc5217SJeff Kirsher if (!bp->port.pmf) 896adfc5217SJeff Kirsher return 0; 897adfc5217SJeff Kirsher 898adfc5217SJeff Kirsher if (netif_running(dev)) { 899adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 900adfc5217SJeff Kirsher bnx2x_link_set(bp); 901adfc5217SJeff Kirsher } 902adfc5217SJeff Kirsher 903adfc5217SJeff Kirsher return 0; 904adfc5217SJeff Kirsher } 905adfc5217SJeff Kirsher 906adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 907adfc5217SJeff Kirsher { 908adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 909adfc5217SJeff Kirsher 910adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 911adfc5217SJeff Kirsher return 0; 912adfc5217SJeff Kirsher 913adfc5217SJeff Kirsher return bp->link_vars.link_up; 914adfc5217SJeff Kirsher } 915adfc5217SJeff Kirsher 916adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 917adfc5217SJeff Kirsher { 918adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 919adfc5217SJeff Kirsher 920adfc5217SJeff Kirsher return bp->common.flash_size; 921adfc5217SJeff Kirsher } 922adfc5217SJeff Kirsher 923f16da43bSAriel Elior /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had 924f16da43bSAriel Elior * we done things the other way around, if two pfs from the same port would 925f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 926f16da43bSAriel Elior * as: 927f16da43bSAriel Elior * pf A takes the port lock. 928f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 929f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 930f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 931f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 932f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 933f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 934f16da43bSAriel Elior * acess corrupted by pf B).* 935f16da43bSAriel Elior */ 936adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 937adfc5217SJeff Kirsher { 938adfc5217SJeff Kirsher int port = BP_PORT(bp); 939adfc5217SJeff Kirsher int count, i; 940f16da43bSAriel Elior u32 val; 941f16da43bSAriel Elior 942f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 943f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 944adfc5217SJeff Kirsher 945adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 946adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 947adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 948adfc5217SJeff Kirsher count *= 100; 949adfc5217SJeff Kirsher 950adfc5217SJeff Kirsher /* request access to nvram interface */ 951adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 952adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 953adfc5217SJeff Kirsher 954adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 955adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 956adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 957adfc5217SJeff Kirsher break; 958adfc5217SJeff Kirsher 959adfc5217SJeff Kirsher udelay(5); 960adfc5217SJeff Kirsher } 961adfc5217SJeff Kirsher 962adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 96351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 96451c1a580SMerav Sicron "cannot get access to nvram interface\n"); 965adfc5217SJeff Kirsher return -EBUSY; 966adfc5217SJeff Kirsher } 967adfc5217SJeff Kirsher 968adfc5217SJeff Kirsher return 0; 969adfc5217SJeff Kirsher } 970adfc5217SJeff Kirsher 971adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 972adfc5217SJeff Kirsher { 973adfc5217SJeff Kirsher int port = BP_PORT(bp); 974adfc5217SJeff Kirsher int count, i; 975f16da43bSAriel Elior u32 val; 976adfc5217SJeff Kirsher 977adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 978adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 979adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 980adfc5217SJeff Kirsher count *= 100; 981adfc5217SJeff Kirsher 982adfc5217SJeff Kirsher /* relinquish nvram interface */ 983adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 984adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 985adfc5217SJeff Kirsher 986adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 987adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 988adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 989adfc5217SJeff Kirsher break; 990adfc5217SJeff Kirsher 991adfc5217SJeff Kirsher udelay(5); 992adfc5217SJeff Kirsher } 993adfc5217SJeff Kirsher 994adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 99551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 99651c1a580SMerav Sicron "cannot free access to nvram interface\n"); 997adfc5217SJeff Kirsher return -EBUSY; 998adfc5217SJeff Kirsher } 999adfc5217SJeff Kirsher 1000f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1001f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1002adfc5217SJeff Kirsher return 0; 1003adfc5217SJeff Kirsher } 1004adfc5217SJeff Kirsher 1005adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1006adfc5217SJeff Kirsher { 1007adfc5217SJeff Kirsher u32 val; 1008adfc5217SJeff Kirsher 1009adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1010adfc5217SJeff Kirsher 1011adfc5217SJeff Kirsher /* enable both bits, even on read */ 1012adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1013adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1014adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1015adfc5217SJeff Kirsher } 1016adfc5217SJeff Kirsher 1017adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1018adfc5217SJeff Kirsher { 1019adfc5217SJeff Kirsher u32 val; 1020adfc5217SJeff Kirsher 1021adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1022adfc5217SJeff Kirsher 1023adfc5217SJeff Kirsher /* disable both bits, even after read */ 1024adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1025adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1026adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1027adfc5217SJeff Kirsher } 1028adfc5217SJeff Kirsher 1029adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1030adfc5217SJeff Kirsher u32 cmd_flags) 1031adfc5217SJeff Kirsher { 1032adfc5217SJeff Kirsher int count, i, rc; 1033adfc5217SJeff Kirsher u32 val; 1034adfc5217SJeff Kirsher 1035adfc5217SJeff Kirsher /* build the command word */ 1036adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1037adfc5217SJeff Kirsher 1038adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1039adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1040adfc5217SJeff Kirsher 1041adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1042adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1043adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1044adfc5217SJeff Kirsher 1045adfc5217SJeff Kirsher /* issue a read command */ 1046adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1047adfc5217SJeff Kirsher 1048adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1049adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1050adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1051adfc5217SJeff Kirsher count *= 100; 1052adfc5217SJeff Kirsher 1053adfc5217SJeff Kirsher /* wait for completion */ 1054adfc5217SJeff Kirsher *ret_val = 0; 1055adfc5217SJeff Kirsher rc = -EBUSY; 1056adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1057adfc5217SJeff Kirsher udelay(5); 1058adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1059adfc5217SJeff Kirsher 1060adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1061adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1062adfc5217SJeff Kirsher /* we read nvram data in cpu order 1063adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 1064adfc5217SJeff Kirsher * converting to big-endian will do the work */ 1065adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1066adfc5217SJeff Kirsher rc = 0; 1067adfc5217SJeff Kirsher break; 1068adfc5217SJeff Kirsher } 1069adfc5217SJeff Kirsher } 107051c1a580SMerav Sicron if (rc == -EBUSY) 107151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 107251c1a580SMerav Sicron "nvram read timeout expired\n"); 1073adfc5217SJeff Kirsher return rc; 1074adfc5217SJeff Kirsher } 1075adfc5217SJeff Kirsher 1076adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1077adfc5217SJeff Kirsher int buf_size) 1078adfc5217SJeff Kirsher { 1079adfc5217SJeff Kirsher int rc; 1080adfc5217SJeff Kirsher u32 cmd_flags; 1081adfc5217SJeff Kirsher __be32 val; 1082adfc5217SJeff Kirsher 1083adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 108451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1085adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1086adfc5217SJeff Kirsher offset, buf_size); 1087adfc5217SJeff Kirsher return -EINVAL; 1088adfc5217SJeff Kirsher } 1089adfc5217SJeff Kirsher 1090adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 109151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 109251c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1093adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1094adfc5217SJeff Kirsher return -EINVAL; 1095adfc5217SJeff Kirsher } 1096adfc5217SJeff Kirsher 1097adfc5217SJeff Kirsher /* request access to nvram interface */ 1098adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1099adfc5217SJeff Kirsher if (rc) 1100adfc5217SJeff Kirsher return rc; 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher /* enable access to nvram interface */ 1103adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1104adfc5217SJeff Kirsher 1105adfc5217SJeff Kirsher /* read the first word(s) */ 1106adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1107adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1108adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1109adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1110adfc5217SJeff Kirsher 1111adfc5217SJeff Kirsher /* advance to the next dword */ 1112adfc5217SJeff Kirsher offset += sizeof(u32); 1113adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1114adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1115adfc5217SJeff Kirsher cmd_flags = 0; 1116adfc5217SJeff Kirsher } 1117adfc5217SJeff Kirsher 1118adfc5217SJeff Kirsher if (rc == 0) { 1119adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1120adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1121adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1122adfc5217SJeff Kirsher } 1123adfc5217SJeff Kirsher 1124adfc5217SJeff Kirsher /* disable access to nvram interface */ 1125adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1126adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1127adfc5217SJeff Kirsher 1128adfc5217SJeff Kirsher return rc; 1129adfc5217SJeff Kirsher } 1130adfc5217SJeff Kirsher 1131adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1132adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1133adfc5217SJeff Kirsher { 1134adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1135adfc5217SJeff Kirsher int rc; 1136adfc5217SJeff Kirsher 113751c1a580SMerav Sicron if (!netif_running(dev)) { 113851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 113951c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1140adfc5217SJeff Kirsher return -EAGAIN; 114151c1a580SMerav Sicron } 1142adfc5217SJeff Kirsher 114351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1144f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1145adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1146adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1147adfc5217SJeff Kirsher 1148adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1149adfc5217SJeff Kirsher 1150adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1151adfc5217SJeff Kirsher 1152adfc5217SJeff Kirsher return rc; 1153adfc5217SJeff Kirsher } 1154adfc5217SJeff Kirsher 1155adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1156adfc5217SJeff Kirsher u32 cmd_flags) 1157adfc5217SJeff Kirsher { 1158adfc5217SJeff Kirsher int count, i, rc; 1159adfc5217SJeff Kirsher 1160adfc5217SJeff Kirsher /* build the command word */ 1161adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1162adfc5217SJeff Kirsher 1163adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1164adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1165adfc5217SJeff Kirsher 1166adfc5217SJeff Kirsher /* write the data */ 1167adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1168adfc5217SJeff Kirsher 1169adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1170adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1171adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1172adfc5217SJeff Kirsher 1173adfc5217SJeff Kirsher /* issue the write command */ 1174adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1175adfc5217SJeff Kirsher 1176adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1177adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1178adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1179adfc5217SJeff Kirsher count *= 100; 1180adfc5217SJeff Kirsher 1181adfc5217SJeff Kirsher /* wait for completion */ 1182adfc5217SJeff Kirsher rc = -EBUSY; 1183adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1184adfc5217SJeff Kirsher udelay(5); 1185adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1186adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1187adfc5217SJeff Kirsher rc = 0; 1188adfc5217SJeff Kirsher break; 1189adfc5217SJeff Kirsher } 1190adfc5217SJeff Kirsher } 1191adfc5217SJeff Kirsher 119251c1a580SMerav Sicron if (rc == -EBUSY) 119351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 119451c1a580SMerav Sicron "nvram write timeout expired\n"); 1195adfc5217SJeff Kirsher return rc; 1196adfc5217SJeff Kirsher } 1197adfc5217SJeff Kirsher 1198adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1199adfc5217SJeff Kirsher 1200adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1201adfc5217SJeff Kirsher int buf_size) 1202adfc5217SJeff Kirsher { 1203adfc5217SJeff Kirsher int rc; 1204adfc5217SJeff Kirsher u32 cmd_flags; 1205adfc5217SJeff Kirsher u32 align_offset; 1206adfc5217SJeff Kirsher __be32 val; 1207adfc5217SJeff Kirsher 1208adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 120951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 121051c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1211adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1212adfc5217SJeff Kirsher return -EINVAL; 1213adfc5217SJeff Kirsher } 1214adfc5217SJeff Kirsher 1215adfc5217SJeff Kirsher /* request access to nvram interface */ 1216adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1217adfc5217SJeff Kirsher if (rc) 1218adfc5217SJeff Kirsher return rc; 1219adfc5217SJeff Kirsher 1220adfc5217SJeff Kirsher /* enable access to nvram interface */ 1221adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1222adfc5217SJeff Kirsher 1223adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1224adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 1225adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); 1226adfc5217SJeff Kirsher 1227adfc5217SJeff Kirsher if (rc == 0) { 1228adfc5217SJeff Kirsher val &= ~(0xff << BYTE_OFFSET(offset)); 1229adfc5217SJeff Kirsher val |= (*data_buf << BYTE_OFFSET(offset)); 1230adfc5217SJeff Kirsher 1231adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 1232adfc5217SJeff Kirsher * convert it back to cpu order */ 1233adfc5217SJeff Kirsher val = be32_to_cpu(val); 1234adfc5217SJeff Kirsher 1235adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1236adfc5217SJeff Kirsher cmd_flags); 1237adfc5217SJeff Kirsher } 1238adfc5217SJeff Kirsher 1239adfc5217SJeff Kirsher /* disable access to nvram interface */ 1240adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1241adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1242adfc5217SJeff Kirsher 1243adfc5217SJeff Kirsher return rc; 1244adfc5217SJeff Kirsher } 1245adfc5217SJeff Kirsher 1246adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1247adfc5217SJeff Kirsher int buf_size) 1248adfc5217SJeff Kirsher { 1249adfc5217SJeff Kirsher int rc; 1250adfc5217SJeff Kirsher u32 cmd_flags; 1251adfc5217SJeff Kirsher u32 val; 1252adfc5217SJeff Kirsher u32 written_so_far; 1253adfc5217SJeff Kirsher 1254adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1255adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1256adfc5217SJeff Kirsher 1257adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 125851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1259adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1260adfc5217SJeff Kirsher offset, buf_size); 1261adfc5217SJeff Kirsher return -EINVAL; 1262adfc5217SJeff Kirsher } 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 126551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 126651c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1267adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1268adfc5217SJeff Kirsher return -EINVAL; 1269adfc5217SJeff Kirsher } 1270adfc5217SJeff Kirsher 1271adfc5217SJeff Kirsher /* request access to nvram interface */ 1272adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1273adfc5217SJeff Kirsher if (rc) 1274adfc5217SJeff Kirsher return rc; 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher /* enable access to nvram interface */ 1277adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1278adfc5217SJeff Kirsher 1279adfc5217SJeff Kirsher written_so_far = 0; 1280adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1281adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1282adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1283adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1284adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1285adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1286adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1287adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1288adfc5217SJeff Kirsher 1289adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1290adfc5217SJeff Kirsher 1291adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1292adfc5217SJeff Kirsher 1293adfc5217SJeff Kirsher /* advance to the next dword */ 1294adfc5217SJeff Kirsher offset += sizeof(u32); 1295adfc5217SJeff Kirsher data_buf += sizeof(u32); 1296adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1297adfc5217SJeff Kirsher cmd_flags = 0; 1298adfc5217SJeff Kirsher } 1299adfc5217SJeff Kirsher 1300adfc5217SJeff Kirsher /* disable access to nvram interface */ 1301adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1302adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1303adfc5217SJeff Kirsher 1304adfc5217SJeff Kirsher return rc; 1305adfc5217SJeff Kirsher } 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1308adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1309adfc5217SJeff Kirsher { 1310adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1311adfc5217SJeff Kirsher int port = BP_PORT(bp); 1312adfc5217SJeff Kirsher int rc = 0; 1313adfc5217SJeff Kirsher u32 ext_phy_config; 131451c1a580SMerav Sicron if (!netif_running(dev)) { 131551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 131651c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1317adfc5217SJeff Kirsher return -EAGAIN; 131851c1a580SMerav Sicron } 1319adfc5217SJeff Kirsher 132051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1321f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1322adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1323adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1324adfc5217SJeff Kirsher 1325adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1326adfc5217SJeff Kirsher 1327adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1328adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 132951c1a580SMerav Sicron !bp->port.pmf) { 133051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 133151c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1332adfc5217SJeff Kirsher return -EINVAL; 133351c1a580SMerav Sicron } 1334adfc5217SJeff Kirsher 1335adfc5217SJeff Kirsher ext_phy_config = 1336adfc5217SJeff Kirsher SHMEM_RD(bp, 1337adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1338adfc5217SJeff Kirsher 1339adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1340adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1341adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1342adfc5217SJeff Kirsher 1343adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1344adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1345adfc5217SJeff Kirsher &bp->link_vars, 0); 1346adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1347adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1348adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1349adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1350adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1351adfc5217SJeff Kirsher bnx2x_link_report(bp); 1352adfc5217SJeff Kirsher 1353adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1354adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1355adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1356adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1357adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1358adfc5217SJeff Kirsher &bp->link_vars, 1); 1359adfc5217SJeff Kirsher 1360adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1361adfc5217SJeff Kirsher &bp->link_vars); 1362adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1363adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1364adfc5217SJeff Kirsher } 1365adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1366adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1367adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1368adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1369adfc5217SJeff Kirsher 1370adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1371adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1372adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1373adfc5217SJeff Kirsher 1374adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1375adfc5217SJeff Kirsher 1376adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1377adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1378adfc5217SJeff Kirsher 1379adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1380adfc5217SJeff Kirsher msleep(500); 1381adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1382adfc5217SJeff Kirsher msleep(500); 1383adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1384adfc5217SJeff Kirsher } 1385adfc5217SJeff Kirsher } else 1386adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1387adfc5217SJeff Kirsher 1388adfc5217SJeff Kirsher return rc; 1389adfc5217SJeff Kirsher } 1390adfc5217SJeff Kirsher 1391adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1392adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1393adfc5217SJeff Kirsher { 1394adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1395adfc5217SJeff Kirsher 1396adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1397adfc5217SJeff Kirsher 1398adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1399adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1400adfc5217SJeff Kirsher 1401adfc5217SJeff Kirsher return 0; 1402adfc5217SJeff Kirsher } 1403adfc5217SJeff Kirsher 1404adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1405adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1406adfc5217SJeff Kirsher { 1407adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1408adfc5217SJeff Kirsher 1409adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1410adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1411adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1412adfc5217SJeff Kirsher 1413adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1414adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1415adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1416adfc5217SJeff Kirsher 1417adfc5217SJeff Kirsher if (netif_running(dev)) 1418adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1419adfc5217SJeff Kirsher 1420adfc5217SJeff Kirsher return 0; 1421adfc5217SJeff Kirsher } 1422adfc5217SJeff Kirsher 1423adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1424adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1425adfc5217SJeff Kirsher { 1426adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1427adfc5217SJeff Kirsher 1428adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1429adfc5217SJeff Kirsher 1430adfc5217SJeff Kirsher if (bp->rx_ring_size) 1431adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1432adfc5217SJeff Kirsher else 1433adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1434adfc5217SJeff Kirsher 1435a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1436adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1437adfc5217SJeff Kirsher } 1438adfc5217SJeff Kirsher 1439adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1440adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1441adfc5217SJeff Kirsher { 1442adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1443adfc5217SJeff Kirsher 1444adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 144551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 144651c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1447adfc5217SJeff Kirsher return -EAGAIN; 1448adfc5217SJeff Kirsher } 1449adfc5217SJeff Kirsher 1450adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1451adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1452adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1453a3348722SBarak Witkowski (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 145451c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 145551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1456adfc5217SJeff Kirsher return -EINVAL; 145751c1a580SMerav Sicron } 1458adfc5217SJeff Kirsher 1459adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1460adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1461adfc5217SJeff Kirsher 1462adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1463adfc5217SJeff Kirsher } 1464adfc5217SJeff Kirsher 1465adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1466adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1467adfc5217SJeff Kirsher { 1468adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1469adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 14709e7e8399SMintz Yuval int cfg_reg; 14719e7e8399SMintz Yuval 1472adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1473adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1474adfc5217SJeff Kirsher 14759e7e8399SMintz Yuval if (!epause->autoneg) 1476241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 14779e7e8399SMintz Yuval else 14789e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 14799e7e8399SMintz Yuval 14809e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1481adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 14829e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1483adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1484adfc5217SJeff Kirsher 148551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1486f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1487adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1488adfc5217SJeff Kirsher } 1489adfc5217SJeff Kirsher 1490adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1491adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1492adfc5217SJeff Kirsher { 1493adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1494adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1495adfc5217SJeff Kirsher if (IS_MF(bp)) 1496adfc5217SJeff Kirsher return 0; 1497adfc5217SJeff Kirsher 149851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1499f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1500adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1501adfc5217SJeff Kirsher 1502adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1503adfc5217SJeff Kirsher 1504adfc5217SJeff Kirsher if (epause->rx_pause) 1505adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1506adfc5217SJeff Kirsher 1507adfc5217SJeff Kirsher if (epause->tx_pause) 1508adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1509adfc5217SJeff Kirsher 1510adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1511adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1512adfc5217SJeff Kirsher 1513adfc5217SJeff Kirsher if (epause->autoneg) { 1514adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 151551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1516adfc5217SJeff Kirsher return -EINVAL; 1517adfc5217SJeff Kirsher } 1518adfc5217SJeff Kirsher 1519adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1520adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1521adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1522adfc5217SJeff Kirsher } 1523adfc5217SJeff Kirsher } 1524adfc5217SJeff Kirsher 152551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1526adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1527adfc5217SJeff Kirsher 1528adfc5217SJeff Kirsher if (netif_running(dev)) { 1529adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1530adfc5217SJeff Kirsher bnx2x_link_set(bp); 1531adfc5217SJeff Kirsher } 1532adfc5217SJeff Kirsher 1533adfc5217SJeff Kirsher return 0; 1534adfc5217SJeff Kirsher } 1535adfc5217SJeff Kirsher 1536cf2c1df6SMerav Sicron char *bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF] = { 1537cf2c1df6SMerav Sicron "register_test (offline) ", 1538cf2c1df6SMerav Sicron "memory_test (offline) ", 1539cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1540cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1541cf2c1df6SMerav Sicron "nvram_test (online) ", 1542cf2c1df6SMerav Sicron "interrupt_test (online) ", 1543cf2c1df6SMerav Sicron "link_test (online) " 1544adfc5217SJeff Kirsher }; 1545adfc5217SJeff Kirsher 1546e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 1547e9939c80SYuval Mintz { 1548e9939c80SYuval Mintz u32 modes = 0; 1549e9939c80SYuval Mintz 1550e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 1551e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 1552e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 1553e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 1554e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 1555e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 1556e9939c80SYuval Mintz 1557e9939c80SYuval Mintz return modes; 1558e9939c80SYuval Mintz } 1559e9939c80SYuval Mintz 1560e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1561e9939c80SYuval Mintz { 1562e9939c80SYuval Mintz u32 eee_adv = 0; 1563e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 1564e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 1565e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 1566e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 1567e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 1568e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 1569e9939c80SYuval Mintz 1570e9939c80SYuval Mintz return eee_adv << shift; 1571e9939c80SYuval Mintz } 1572e9939c80SYuval Mintz 1573e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1574e9939c80SYuval Mintz { 1575e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1576e9939c80SYuval Mintz u32 eee_cfg; 1577e9939c80SYuval Mintz 1578e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1579e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1580e9939c80SYuval Mintz return -EOPNOTSUPP; 1581e9939c80SYuval Mintz } 1582e9939c80SYuval Mintz 1583e9939c80SYuval Mintz eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]); 1584e9939c80SYuval Mintz 1585e9939c80SYuval Mintz edata->supported = 1586e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 1587e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 1588e9939c80SYuval Mintz 1589e9939c80SYuval Mintz edata->advertised = 1590e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 1591e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1592e9939c80SYuval Mintz edata->lp_advertised = 1593e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 1594e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 1595e9939c80SYuval Mintz 1596e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 1597e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 1598e9939c80SYuval Mintz 1599e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 1600e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 1601e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 1602e9939c80SYuval Mintz 1603e9939c80SYuval Mintz return 0; 1604e9939c80SYuval Mintz } 1605e9939c80SYuval Mintz 1606e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 1607e9939c80SYuval Mintz { 1608e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1609e9939c80SYuval Mintz u32 eee_cfg; 1610e9939c80SYuval Mintz u32 advertised; 1611e9939c80SYuval Mintz 1612e9939c80SYuval Mintz if (IS_MF(bp)) 1613e9939c80SYuval Mintz return 0; 1614e9939c80SYuval Mintz 1615e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1616e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1617e9939c80SYuval Mintz return -EOPNOTSUPP; 1618e9939c80SYuval Mintz } 1619e9939c80SYuval Mintz 1620e9939c80SYuval Mintz eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]); 1621e9939c80SYuval Mintz 1622e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 1623e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 1624e9939c80SYuval Mintz return -EOPNOTSUPP; 1625e9939c80SYuval Mintz } 1626e9939c80SYuval Mintz 1627e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 1628e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1629e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 1630e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1631e9939c80SYuval Mintz "Direct manipulation of EEE advertisment is not supported\n"); 1632e9939c80SYuval Mintz return -EINVAL; 1633e9939c80SYuval Mintz } 1634e9939c80SYuval Mintz 1635e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 1636e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1637e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 1638e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 1639e9939c80SYuval Mintz return -EINVAL; 1640e9939c80SYuval Mintz } 1641e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 1642e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 1643e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1644e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 1645e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 1646e9939c80SYuval Mintz return -EINVAL; 1647e9939c80SYuval Mintz } 1648e9939c80SYuval Mintz 1649e9939c80SYuval Mintz /* All is well; Apply changes*/ 1650e9939c80SYuval Mintz if (edata->eee_enabled) 1651e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 1652e9939c80SYuval Mintz else 1653e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 1654e9939c80SYuval Mintz 1655e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 1656e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 1657e9939c80SYuval Mintz else 1658e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 1659e9939c80SYuval Mintz 1660e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 1661e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 1662e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 1663e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 1664e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 1665e9939c80SYuval Mintz 1666e9939c80SYuval Mintz /* Restart link to propogate changes */ 1667e9939c80SYuval Mintz if (netif_running(dev)) { 1668e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1669e9939c80SYuval Mintz bnx2x_link_set(bp); 1670e9939c80SYuval Mintz } 1671e9939c80SYuval Mintz 1672e9939c80SYuval Mintz return 0; 1673e9939c80SYuval Mintz } 1674e9939c80SYuval Mintz 1675e9939c80SYuval Mintz 1676adfc5217SJeff Kirsher enum { 1677adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 1678adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 1679adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 1680adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 1681adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 1682adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 1683adfc5217SJeff Kirsher }; 1684adfc5217SJeff Kirsher 1685adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 1686adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 1687adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 1688adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 1689adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 1690adfc5217SJeff Kirsher 1691adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 1692adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 1693adfc5217SJeff Kirsher 1694adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 1695adfc5217SJeff Kirsher { 1696adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 1697adfc5217SJeff Kirsher u32 wr_val = 0, hw; 1698adfc5217SJeff Kirsher int port = BP_PORT(bp); 1699adfc5217SJeff Kirsher static const struct { 1700adfc5217SJeff Kirsher u32 hw; 1701adfc5217SJeff Kirsher u32 offset0; 1702adfc5217SJeff Kirsher u32 offset1; 1703adfc5217SJeff Kirsher u32 mask; 1704adfc5217SJeff Kirsher } reg_tbl[] = { 1705adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 1706adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 1707adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1708adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 1709adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 1710adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 1711adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1712adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 1713adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 1714adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 1715adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 1716adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 1717adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1718adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 1719adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1720adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 1721adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1722adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1723adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1724adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 1725adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 1726adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1727adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1728adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 1729adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1730adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 1731adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1732adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 1733adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1734adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 1735adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1736adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 1737adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1738adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 1739adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1740adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 1741adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1742adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 1743adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1744adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 1745adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1746adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 1747adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1748adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 1749adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1750adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 1751adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1752adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 1753adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1754adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 1755adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1756adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 1757adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1758adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 1759adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1760adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 1761adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1762adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 1763adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1764adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 1765adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 1766adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 1767adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1768adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 1769adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1770adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 1771adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1772adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 1773adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1774adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 1775adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1776adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 1777adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1778adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 1779adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1780adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 1781adfc5217SJeff Kirsher 1782adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 1783adfc5217SJeff Kirsher }; 1784adfc5217SJeff Kirsher 178551c1a580SMerav Sicron if (!netif_running(bp->dev)) { 178651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 178751c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1788adfc5217SJeff Kirsher return rc; 178951c1a580SMerav Sicron } 1790adfc5217SJeff Kirsher 1791adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1792adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 1793adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1794adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 1795adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1796adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 1797adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 1798adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 1799adfc5217SJeff Kirsher else /* e3 A0 */ 1800adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 1801adfc5217SJeff Kirsher 1802adfc5217SJeff Kirsher /* Repeat the test twice: 1803adfc5217SJeff Kirsher First by writing 0x00000000, second by writing 0xffffffff */ 1804adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 1805adfc5217SJeff Kirsher 1806adfc5217SJeff Kirsher switch (idx) { 1807adfc5217SJeff Kirsher case 0: 1808adfc5217SJeff Kirsher wr_val = 0; 1809adfc5217SJeff Kirsher break; 1810adfc5217SJeff Kirsher case 1: 1811adfc5217SJeff Kirsher wr_val = 0xffffffff; 1812adfc5217SJeff Kirsher break; 1813adfc5217SJeff Kirsher } 1814adfc5217SJeff Kirsher 1815adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 1816adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 1817adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 1818adfc5217SJeff Kirsher continue; 1819adfc5217SJeff Kirsher 1820adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 1821adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 1822adfc5217SJeff Kirsher 1823adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 1824adfc5217SJeff Kirsher 1825adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 1826adfc5217SJeff Kirsher 1827adfc5217SJeff Kirsher val = REG_RD(bp, offset); 1828adfc5217SJeff Kirsher 1829adfc5217SJeff Kirsher /* Restore the original register's value */ 1830adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 1831adfc5217SJeff Kirsher 1832adfc5217SJeff Kirsher /* verify value is as expected */ 1833adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 183451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1835adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 1836adfc5217SJeff Kirsher offset, val, wr_val, mask); 1837adfc5217SJeff Kirsher goto test_reg_exit; 1838adfc5217SJeff Kirsher } 1839adfc5217SJeff Kirsher } 1840adfc5217SJeff Kirsher } 1841adfc5217SJeff Kirsher 1842adfc5217SJeff Kirsher rc = 0; 1843adfc5217SJeff Kirsher 1844adfc5217SJeff Kirsher test_reg_exit: 1845adfc5217SJeff Kirsher return rc; 1846adfc5217SJeff Kirsher } 1847adfc5217SJeff Kirsher 1848adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 1849adfc5217SJeff Kirsher { 1850adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 1851adfc5217SJeff Kirsher u32 val, index; 1852adfc5217SJeff Kirsher static const struct { 1853adfc5217SJeff Kirsher u32 offset; 1854adfc5217SJeff Kirsher int size; 1855adfc5217SJeff Kirsher } mem_tbl[] = { 1856adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 1857adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 1858adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 1859adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 1860adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 1861adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 1862adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 1863adfc5217SJeff Kirsher 1864adfc5217SJeff Kirsher { 0xffffffff, 0 } 1865adfc5217SJeff Kirsher }; 1866adfc5217SJeff Kirsher 1867adfc5217SJeff Kirsher static const struct { 1868adfc5217SJeff Kirsher char *name; 1869adfc5217SJeff Kirsher u32 offset; 1870adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 1871adfc5217SJeff Kirsher } prty_tbl[] = { 1872adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 1873adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1874adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 1875adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 1876adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 1877adfc5217SJeff Kirsher {0, 0, 0, 0} }, 1878adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 1879adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1880adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 1881adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1882adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 1883adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 1884adfc5217SJeff Kirsher 1885adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 1886adfc5217SJeff Kirsher }; 1887adfc5217SJeff Kirsher 188851c1a580SMerav Sicron if (!netif_running(bp->dev)) { 188951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 189051c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1891adfc5217SJeff Kirsher return rc; 189251c1a580SMerav Sicron } 1893adfc5217SJeff Kirsher 1894adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1895adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 1896adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1897adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 1898adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1899adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 1900adfc5217SJeff Kirsher else /* e3 */ 1901adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 1902adfc5217SJeff Kirsher 1903adfc5217SJeff Kirsher /* pre-Check the parity status */ 1904adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1905adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 1906adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 190751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1908adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 1909adfc5217SJeff Kirsher goto test_mem_exit; 1910adfc5217SJeff Kirsher } 1911adfc5217SJeff Kirsher } 1912adfc5217SJeff Kirsher 1913adfc5217SJeff Kirsher /* Go through all the memories */ 1914adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 1915adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 1916adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 1917adfc5217SJeff Kirsher 1918adfc5217SJeff Kirsher /* Check the parity status */ 1919adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1920adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 1921adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 192251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1923adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 1924adfc5217SJeff Kirsher goto test_mem_exit; 1925adfc5217SJeff Kirsher } 1926adfc5217SJeff Kirsher } 1927adfc5217SJeff Kirsher 1928adfc5217SJeff Kirsher rc = 0; 1929adfc5217SJeff Kirsher 1930adfc5217SJeff Kirsher test_mem_exit: 1931adfc5217SJeff Kirsher return rc; 1932adfc5217SJeff Kirsher } 1933adfc5217SJeff Kirsher 1934adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 1935adfc5217SJeff Kirsher { 1936adfc5217SJeff Kirsher int cnt = 1400; 1937adfc5217SJeff Kirsher 1938adfc5217SJeff Kirsher if (link_up) { 1939adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 1940adfc5217SJeff Kirsher msleep(20); 1941adfc5217SJeff Kirsher 1942adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 194351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 19448970b2e4SMerav Sicron 19458970b2e4SMerav Sicron cnt = 1400; 19468970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 19478970b2e4SMerav Sicron msleep(20); 19488970b2e4SMerav Sicron 19498970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 19508970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 19518970b2e4SMerav Sicron "Timeout waiting for link init\n"); 1952adfc5217SJeff Kirsher } 1953adfc5217SJeff Kirsher } 1954adfc5217SJeff Kirsher 1955adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 1956adfc5217SJeff Kirsher { 1957adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 1958adfc5217SJeff Kirsher struct sk_buff *skb; 1959adfc5217SJeff Kirsher unsigned char *packet; 1960adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 1961adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 1962adfc5217SJeff Kirsher struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0]; 1963adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 1964adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 1965b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 1966adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 1967adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 1968adfc5217SJeff Kirsher struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; 1969adfc5217SJeff Kirsher struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; 1970adfc5217SJeff Kirsher dma_addr_t mapping; 1971adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 1972adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 1973adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 1974adfc5217SJeff Kirsher u16 len; 1975adfc5217SJeff Kirsher int rc = -ENODEV; 1976e52fcb24SEric Dumazet u8 *data; 19778970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 19788970b2e4SMerav Sicron txdata->txq_index); 1979adfc5217SJeff Kirsher 1980adfc5217SJeff Kirsher /* check the loopback mode */ 1981adfc5217SJeff Kirsher switch (loopback_mode) { 1982adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 19838970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 19848970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 1985adfc5217SJeff Kirsher return -EINVAL; 19868970b2e4SMerav Sicron } 1987adfc5217SJeff Kirsher break; 1988adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 198932911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 199032911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 199132911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 199232911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 199332911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 199432911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 199532911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 199632911333SYaniv Rosner else 199732911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 199832911333SYaniv Rosner } else 199932911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 200032911333SYaniv Rosner 2001adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2002adfc5217SJeff Kirsher break; 20038970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 20048970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 20058970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 20068970b2e4SMerav Sicron "Can't configure external loopback\n"); 20078970b2e4SMerav Sicron return -EINVAL; 20088970b2e4SMerav Sicron } 20098970b2e4SMerav Sicron break; 2010adfc5217SJeff Kirsher default: 201151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2012adfc5217SJeff Kirsher return -EINVAL; 2013adfc5217SJeff Kirsher } 2014adfc5217SJeff Kirsher 2015adfc5217SJeff Kirsher /* prepare the loopback packet */ 2016adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2017adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2018adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2019adfc5217SJeff Kirsher if (!skb) { 202051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2021adfc5217SJeff Kirsher rc = -ENOMEM; 2022adfc5217SJeff Kirsher goto test_loopback_exit; 2023adfc5217SJeff Kirsher } 2024adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2025adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2026adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 2027adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2028adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2029adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2030adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2031adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2032adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2033adfc5217SJeff Kirsher rc = -ENOMEM; 2034adfc5217SJeff Kirsher dev_kfree_skb(skb); 203551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2036adfc5217SJeff Kirsher goto test_loopback_exit; 2037adfc5217SJeff Kirsher } 2038adfc5217SJeff Kirsher 2039adfc5217SJeff Kirsher /* send the loopback packet */ 2040adfc5217SJeff Kirsher num_pkts = 0; 2041adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2042adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2043adfc5217SJeff Kirsher 204473dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 204573dbb5e1SDmitry Kravkov 2046adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2047adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2048adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2049adfc5217SJeff Kirsher tx_buf->skb = skb; 2050adfc5217SJeff Kirsher tx_buf->flags = 0; 2051adfc5217SJeff Kirsher 2052adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2053adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2054adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2055adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2056adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2057adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2058adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2059adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2060adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2061adfc5217SJeff Kirsher ETH_TX_START_BD_ETH_ADDR_TYPE, 2062adfc5217SJeff Kirsher UNICAST_ADDRESS); 2063adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2064adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2065adfc5217SJeff Kirsher 1); 2066adfc5217SJeff Kirsher 2067adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2068adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2069adfc5217SJeff Kirsher 2070adfc5217SJeff Kirsher pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2071adfc5217SJeff Kirsher pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2072adfc5217SJeff Kirsher 2073adfc5217SJeff Kirsher memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2074adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2075adfc5217SJeff Kirsher 2076adfc5217SJeff Kirsher wmb(); 2077adfc5217SJeff Kirsher 2078adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2079adfc5217SJeff Kirsher barrier(); 2080adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2081adfc5217SJeff Kirsher 2082adfc5217SJeff Kirsher mmiowb(); 2083adfc5217SJeff Kirsher barrier(); 2084adfc5217SJeff Kirsher 2085adfc5217SJeff Kirsher num_pkts++; 2086adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2087adfc5217SJeff Kirsher 2088adfc5217SJeff Kirsher udelay(100); 2089adfc5217SJeff Kirsher 2090adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2091adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2092adfc5217SJeff Kirsher goto test_loopback_exit; 2093adfc5217SJeff Kirsher 2094adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2095adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2096adfc5217SJeff Kirsher * disabled. 2097adfc5217SJeff Kirsher */ 2098adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2099adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2100adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2101adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2102adfc5217SJeff Kirsher */ 2103adfc5217SJeff Kirsher local_bh_disable(); 2104adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2105adfc5217SJeff Kirsher local_bh_enable(); 2106adfc5217SJeff Kirsher } 2107adfc5217SJeff Kirsher 2108adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2109adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2110adfc5217SJeff Kirsher goto test_loopback_exit; 2111adfc5217SJeff Kirsher 2112b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2113adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2114adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2115adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2116adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2117adfc5217SJeff Kirsher 2118621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2119adfc5217SJeff Kirsher if (len != pkt_size) 2120adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2121adfc5217SJeff Kirsher 2122adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2123adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2124adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2125adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2126e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2127adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2128e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2129adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2130adfc5217SJeff Kirsher 2131adfc5217SJeff Kirsher rc = 0; 2132adfc5217SJeff Kirsher 2133adfc5217SJeff Kirsher test_loopback_rx_exit: 2134adfc5217SJeff Kirsher 2135adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2136adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2137adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2138adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2139adfc5217SJeff Kirsher 2140adfc5217SJeff Kirsher /* Update producers */ 2141adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2142adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2143adfc5217SJeff Kirsher 2144adfc5217SJeff Kirsher test_loopback_exit: 2145adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2146adfc5217SJeff Kirsher 2147adfc5217SJeff Kirsher return rc; 2148adfc5217SJeff Kirsher } 2149adfc5217SJeff Kirsher 2150adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2151adfc5217SJeff Kirsher { 2152adfc5217SJeff Kirsher int rc = 0, res; 2153adfc5217SJeff Kirsher 2154adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2155adfc5217SJeff Kirsher return rc; 2156adfc5217SJeff Kirsher 2157adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2158adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2159adfc5217SJeff Kirsher 2160adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2161adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2162adfc5217SJeff Kirsher 2163adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2164adfc5217SJeff Kirsher if (res) { 216551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2166adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2167adfc5217SJeff Kirsher } 2168adfc5217SJeff Kirsher 2169adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2170adfc5217SJeff Kirsher if (res) { 217151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2172adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2173adfc5217SJeff Kirsher } 2174adfc5217SJeff Kirsher 2175adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2176adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2177adfc5217SJeff Kirsher 2178adfc5217SJeff Kirsher return rc; 2179adfc5217SJeff Kirsher } 2180adfc5217SJeff Kirsher 21818970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 21828970b2e4SMerav Sicron { 21838970b2e4SMerav Sicron int rc; 21848970b2e4SMerav Sicron u8 is_serdes = 21858970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 21868970b2e4SMerav Sicron 21878970b2e4SMerav Sicron if (BP_NOMCP(bp)) 21888970b2e4SMerav Sicron return -ENODEV; 21898970b2e4SMerav Sicron 21908970b2e4SMerav Sicron if (!netif_running(bp->dev)) 21918970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 21928970b2e4SMerav Sicron 21938970b2e4SMerav Sicron bnx2x_nic_unload(bp, UNLOAD_NORMAL); 21948970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 21958970b2e4SMerav Sicron if (rc) { 21968970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 21978970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 21988970b2e4SMerav Sicron return -ENODEV; 21998970b2e4SMerav Sicron } 22008970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 22018970b2e4SMerav Sicron 22028970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 22038970b2e4SMerav Sicron 22048970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 22058970b2e4SMerav Sicron if (rc) 22068970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 22078970b2e4SMerav Sicron 22088970b2e4SMerav Sicron bnx2x_netif_start(bp); 22098970b2e4SMerav Sicron 22108970b2e4SMerav Sicron return rc; 22118970b2e4SMerav Sicron } 22128970b2e4SMerav Sicron 2213adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2214adfc5217SJeff Kirsher 2215adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2216adfc5217SJeff Kirsher { 2217adfc5217SJeff Kirsher static const struct { 2218adfc5217SJeff Kirsher int offset; 2219adfc5217SJeff Kirsher int size; 2220adfc5217SJeff Kirsher } nvram_tbl[] = { 2221adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2222adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2223adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2224adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2225adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2226adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2227adfc5217SJeff Kirsher { 0, 0 } 2228adfc5217SJeff Kirsher }; 2229afa13b4bSMintz Yuval __be32 *buf; 2230afa13b4bSMintz Yuval u8 *data; 2231adfc5217SJeff Kirsher int i, rc; 2232adfc5217SJeff Kirsher u32 magic, crc; 2233adfc5217SJeff Kirsher 2234adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2235adfc5217SJeff Kirsher return 0; 2236adfc5217SJeff Kirsher 2237afa13b4bSMintz Yuval buf = kmalloc(0x350, GFP_KERNEL); 2238afa13b4bSMintz Yuval if (!buf) { 223951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2240afa13b4bSMintz Yuval rc = -ENOMEM; 2241afa13b4bSMintz Yuval goto test_nvram_exit; 2242afa13b4bSMintz Yuval } 2243afa13b4bSMintz Yuval data = (u8 *)buf; 2244afa13b4bSMintz Yuval 2245adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, 0, data, 4); 2246adfc5217SJeff Kirsher if (rc) { 224751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 224851c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2249adfc5217SJeff Kirsher goto test_nvram_exit; 2250adfc5217SJeff Kirsher } 2251adfc5217SJeff Kirsher 2252adfc5217SJeff Kirsher magic = be32_to_cpu(buf[0]); 2253adfc5217SJeff Kirsher if (magic != 0x669955aa) { 225451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 225551c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2256adfc5217SJeff Kirsher rc = -ENODEV; 2257adfc5217SJeff Kirsher goto test_nvram_exit; 2258adfc5217SJeff Kirsher } 2259adfc5217SJeff Kirsher 2260adfc5217SJeff Kirsher for (i = 0; nvram_tbl[i].size; i++) { 2261adfc5217SJeff Kirsher 2262adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 2263adfc5217SJeff Kirsher nvram_tbl[i].size); 2264adfc5217SJeff Kirsher if (rc) { 226551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2266adfc5217SJeff Kirsher "nvram_tbl[%d] read data (rc %d)\n", i, rc); 2267adfc5217SJeff Kirsher goto test_nvram_exit; 2268adfc5217SJeff Kirsher } 2269adfc5217SJeff Kirsher 2270adfc5217SJeff Kirsher crc = ether_crc_le(nvram_tbl[i].size, data); 2271adfc5217SJeff Kirsher if (crc != CRC32_RESIDUAL) { 227251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 227351c1a580SMerav Sicron "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc); 2274adfc5217SJeff Kirsher rc = -ENODEV; 2275adfc5217SJeff Kirsher goto test_nvram_exit; 2276adfc5217SJeff Kirsher } 2277adfc5217SJeff Kirsher } 2278adfc5217SJeff Kirsher 2279adfc5217SJeff Kirsher test_nvram_exit: 2280afa13b4bSMintz Yuval kfree(buf); 2281adfc5217SJeff Kirsher return rc; 2282adfc5217SJeff Kirsher } 2283adfc5217SJeff Kirsher 2284adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2285adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2286adfc5217SJeff Kirsher { 22873b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2288adfc5217SJeff Kirsher 228951c1a580SMerav Sicron if (!netif_running(bp->dev)) { 229051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 229151c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2292adfc5217SJeff Kirsher return -ENODEV; 229351c1a580SMerav Sicron } 2294adfc5217SJeff Kirsher 2295adfc5217SJeff Kirsher params.q_obj = &bp->fp->q_obj; 2296adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2297adfc5217SJeff Kirsher 2298adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2299adfc5217SJeff Kirsher 2300adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2301adfc5217SJeff Kirsher } 2302adfc5217SJeff Kirsher 2303adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2304adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2305adfc5217SJeff Kirsher { 2306adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2307adfc5217SJeff Kirsher u8 is_serdes; 2308cf2c1df6SMerav Sicron int rc; 2309cf2c1df6SMerav Sicron 2310adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 231151c1a580SMerav Sicron netdev_err(bp->dev, 231251c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2313adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2314adfc5217SJeff Kirsher return; 2315adfc5217SJeff Kirsher } 23168970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 23178970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 23188970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 23198970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2320adfc5217SJeff Kirsher 2321cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2322adfc5217SJeff Kirsher 2323cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2324cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2325cf2c1df6SMerav Sicron "Can't perform self-test when interface is down\n"); 2326adfc5217SJeff Kirsher return; 2327cf2c1df6SMerav Sicron } 2328adfc5217SJeff Kirsher 2329adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2330adfc5217SJeff Kirsher 2331cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2332cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2333adfc5217SJeff Kirsher int port = BP_PORT(bp); 2334adfc5217SJeff Kirsher u32 val; 2335adfc5217SJeff Kirsher u8 link_up; 2336adfc5217SJeff Kirsher 2337adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2338adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2339adfc5217SJeff Kirsher /* disable input for TX port IF */ 2340adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2341adfc5217SJeff Kirsher 2342adfc5217SJeff Kirsher link_up = bp->link_vars.link_up; 2343adfc5217SJeff Kirsher 2344adfc5217SJeff Kirsher bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2345cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2346cf2c1df6SMerav Sicron if (rc) { 2347cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2348cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2349cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2350cf2c1df6SMerav Sicron return; 2351cf2c1df6SMerav Sicron } 2352cf2c1df6SMerav Sicron 2353adfc5217SJeff Kirsher /* wait until link state is restored */ 2354adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2355adfc5217SJeff Kirsher 2356adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2357adfc5217SJeff Kirsher buf[0] = 1; 2358adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2359adfc5217SJeff Kirsher } 2360adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2361adfc5217SJeff Kirsher buf[1] = 1; 2362adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2363adfc5217SJeff Kirsher } 2364adfc5217SJeff Kirsher 23658970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2366adfc5217SJeff Kirsher if (buf[2] != 0) 2367adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2368adfc5217SJeff Kirsher 23698970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 23708970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 23718970b2e4SMerav Sicron if (buf[3] != 0) 23728970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 23738970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 23748970b2e4SMerav Sicron } 23758970b2e4SMerav Sicron 2376adfc5217SJeff Kirsher bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2377adfc5217SJeff Kirsher 2378adfc5217SJeff Kirsher /* restore input for TX port IF */ 2379adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2380cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2381cf2c1df6SMerav Sicron if (rc) { 2382cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2383cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2384cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 2385cf2c1df6SMerav Sicron return; 2386cf2c1df6SMerav Sicron } 2387adfc5217SJeff Kirsher /* wait until link state is restored */ 2388adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2389adfc5217SJeff Kirsher } 2390adfc5217SJeff Kirsher if (bnx2x_test_nvram(bp) != 0) { 2391cf2c1df6SMerav Sicron if (!IS_MF(bp)) 23928970b2e4SMerav Sicron buf[4] = 1; 2393cf2c1df6SMerav Sicron else 2394cf2c1df6SMerav Sicron buf[0] = 1; 2395adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2396adfc5217SJeff Kirsher } 2397adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2398cf2c1df6SMerav Sicron if (!IS_MF(bp)) 23998970b2e4SMerav Sicron buf[5] = 1; 2400cf2c1df6SMerav Sicron else 2401cf2c1df6SMerav Sicron buf[1] = 1; 2402adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2403adfc5217SJeff Kirsher } 2404adfc5217SJeff Kirsher 2405adfc5217SJeff Kirsher if (bnx2x_link_test(bp, is_serdes) != 0) { 2406cf2c1df6SMerav Sicron if (!IS_MF(bp)) 24078970b2e4SMerav Sicron buf[6] = 1; 2408cf2c1df6SMerav Sicron else 2409cf2c1df6SMerav Sicron buf[2] = 1; 2410adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2411adfc5217SJeff Kirsher } 2412adfc5217SJeff Kirsher 2413adfc5217SJeff Kirsher #ifdef BNX2X_EXTRA_DEBUG 2414adfc5217SJeff Kirsher bnx2x_panic_dump(bp); 2415adfc5217SJeff Kirsher #endif 2416adfc5217SJeff Kirsher } 2417adfc5217SJeff Kirsher 2418adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 2419adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2420adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2421adfc5217SJeff Kirsher #define IS_MF_MODE_STAT(bp) \ 2422adfc5217SJeff Kirsher (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2423adfc5217SJeff Kirsher 2424adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 2425adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 2426adfc5217SJeff Kirsher */ 24271191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 2428adfc5217SJeff Kirsher { 2429adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 2430adfc5217SJeff Kirsher } 2431adfc5217SJeff Kirsher 2432adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2433adfc5217SJeff Kirsher { 2434adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2435adfc5217SJeff Kirsher int i, num_stats; 2436adfc5217SJeff Kirsher 2437adfc5217SJeff Kirsher switch (stringset) { 2438adfc5217SJeff Kirsher case ETH_SS_STATS: 2439adfc5217SJeff Kirsher if (is_multi(bp)) { 2440adfc5217SJeff Kirsher num_stats = bnx2x_num_stat_queues(bp) * 2441adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 2442d5e83632SYuval Mintz } else 2443adfc5217SJeff Kirsher num_stats = 0; 2444d5e83632SYuval Mintz if (IS_MF_MODE_STAT(bp)) { 2445adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 2446adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 2447adfc5217SJeff Kirsher num_stats++; 2448adfc5217SJeff Kirsher } else 2449d5e83632SYuval Mintz num_stats += BNX2X_NUM_STATS; 2450d5e83632SYuval Mintz 2451adfc5217SJeff Kirsher return num_stats; 2452adfc5217SJeff Kirsher 2453adfc5217SJeff Kirsher case ETH_SS_TEST: 2454cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 2455adfc5217SJeff Kirsher 2456adfc5217SJeff Kirsher default: 2457adfc5217SJeff Kirsher return -EINVAL; 2458adfc5217SJeff Kirsher } 2459adfc5217SJeff Kirsher } 2460adfc5217SJeff Kirsher 2461adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 2462adfc5217SJeff Kirsher { 2463adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2464cf2c1df6SMerav Sicron int i, j, k, offset, start; 2465adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 2466adfc5217SJeff Kirsher 2467adfc5217SJeff Kirsher switch (stringset) { 2468adfc5217SJeff Kirsher case ETH_SS_STATS: 2469adfc5217SJeff Kirsher k = 0; 2470d5e83632SYuval Mintz if (is_multi(bp)) { 2471adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 2472adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 2473adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 2474adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 2475adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 2476adfc5217SJeff Kirsher ETH_GSTRING_LEN, 2477adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 2478adfc5217SJeff Kirsher queue_name); 2479adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2480adfc5217SJeff Kirsher } 2481d5e83632SYuval Mintz } 2482d5e83632SYuval Mintz 2483d5e83632SYuval Mintz 2484adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2485adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2486adfc5217SJeff Kirsher continue; 2487d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 2488adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 2489adfc5217SJeff Kirsher j++; 2490adfc5217SJeff Kirsher } 2491d5e83632SYuval Mintz 2492adfc5217SJeff Kirsher break; 2493adfc5217SJeff Kirsher 2494adfc5217SJeff Kirsher case ETH_SS_TEST: 2495cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 2496cf2c1df6SMerav Sicron if (!IS_MF(bp)) 2497cf2c1df6SMerav Sicron start = 0; 2498cf2c1df6SMerav Sicron else 2499cf2c1df6SMerav Sicron start = 4; 2500cf2c1df6SMerav Sicron for (i = 0, j = start; j < (start + BNX2X_NUM_TESTS(bp)); 2501cf2c1df6SMerav Sicron i++, j++) { 2502cf2c1df6SMerav Sicron offset = sprintf(buf+32*i, "%s", 2503cf2c1df6SMerav Sicron bnx2x_tests_str_arr[j]); 2504cf2c1df6SMerav Sicron *(buf+offset) = '\0'; 2505cf2c1df6SMerav Sicron } 2506adfc5217SJeff Kirsher break; 2507adfc5217SJeff Kirsher } 2508adfc5217SJeff Kirsher } 2509adfc5217SJeff Kirsher 2510adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 2511adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 2512adfc5217SJeff Kirsher { 2513adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2514adfc5217SJeff Kirsher u32 *hw_stats, *offset; 2515d5e83632SYuval Mintz int i, j, k = 0; 2516adfc5217SJeff Kirsher 2517adfc5217SJeff Kirsher if (is_multi(bp)) { 2518adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 2519adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->fp[i].eth_q_stats; 2520adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 2521adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 2522adfc5217SJeff Kirsher /* skip this counter */ 2523adfc5217SJeff Kirsher buf[k + j] = 0; 2524adfc5217SJeff Kirsher continue; 2525adfc5217SJeff Kirsher } 2526adfc5217SJeff Kirsher offset = (hw_stats + 2527adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 2528adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 2529adfc5217SJeff Kirsher /* 4-byte counter */ 2530adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 2531adfc5217SJeff Kirsher continue; 2532adfc5217SJeff Kirsher } 2533adfc5217SJeff Kirsher /* 8-byte counter */ 2534adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2535adfc5217SJeff Kirsher } 2536adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2537adfc5217SJeff Kirsher } 2538adfc5217SJeff Kirsher } 2539d5e83632SYuval Mintz 2540adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 2541adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2542adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2543adfc5217SJeff Kirsher continue; 2544adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 2545adfc5217SJeff Kirsher /* skip this counter */ 2546d5e83632SYuval Mintz buf[k + j] = 0; 2547adfc5217SJeff Kirsher j++; 2548adfc5217SJeff Kirsher continue; 2549adfc5217SJeff Kirsher } 2550adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 2551adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 2552adfc5217SJeff Kirsher /* 4-byte counter */ 2553d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 2554adfc5217SJeff Kirsher j++; 2555adfc5217SJeff Kirsher continue; 2556adfc5217SJeff Kirsher } 2557adfc5217SJeff Kirsher /* 8-byte counter */ 2558d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2559adfc5217SJeff Kirsher j++; 2560adfc5217SJeff Kirsher } 2561adfc5217SJeff Kirsher } 2562adfc5217SJeff Kirsher 2563adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 2564adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 2565adfc5217SJeff Kirsher { 2566adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2567adfc5217SJeff Kirsher 256851c1a580SMerav Sicron if (!netif_running(dev)) { 256951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 257051c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2571adfc5217SJeff Kirsher return -EAGAIN; 257251c1a580SMerav Sicron } 2573adfc5217SJeff Kirsher 257451c1a580SMerav Sicron if (!bp->port.pmf) { 257551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n"); 2576adfc5217SJeff Kirsher return -EOPNOTSUPP; 257751c1a580SMerav Sicron } 2578adfc5217SJeff Kirsher 2579adfc5217SJeff Kirsher switch (state) { 2580adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 2581adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 2582adfc5217SJeff Kirsher 2583adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 2584adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2585adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 2586adfc5217SJeff Kirsher break; 2587adfc5217SJeff Kirsher 2588adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 2589adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2590adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 2591adfc5217SJeff Kirsher 2592adfc5217SJeff Kirsher break; 2593adfc5217SJeff Kirsher 2594adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 2595adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2596adfc5217SJeff Kirsher LED_MODE_OPER, 2597adfc5217SJeff Kirsher bp->link_vars.line_speed); 2598adfc5217SJeff Kirsher } 2599adfc5217SJeff Kirsher 2600adfc5217SJeff Kirsher return 0; 2601adfc5217SJeff Kirsher } 2602adfc5217SJeff Kirsher 26035d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 26045d317c6aSMerav Sicron { 26055d317c6aSMerav Sicron 26065d317c6aSMerav Sicron switch (info->flow_type) { 26075d317c6aSMerav Sicron case TCP_V4_FLOW: 26085d317c6aSMerav Sicron case TCP_V6_FLOW: 26095d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 26105d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 26115d317c6aSMerav Sicron break; 26125d317c6aSMerav Sicron case UDP_V4_FLOW: 26135d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 26145d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 26155d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 26165d317c6aSMerav Sicron else 26175d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 26185d317c6aSMerav Sicron break; 26195d317c6aSMerav Sicron case UDP_V6_FLOW: 26205d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 26215d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 26225d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 26235d317c6aSMerav Sicron else 26245d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 26255d317c6aSMerav Sicron break; 26265d317c6aSMerav Sicron case IPV4_FLOW: 26275d317c6aSMerav Sicron case IPV6_FLOW: 26285d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 26295d317c6aSMerav Sicron break; 26305d317c6aSMerav Sicron default: 26315d317c6aSMerav Sicron info->data = 0; 26325d317c6aSMerav Sicron break; 26335d317c6aSMerav Sicron } 26345d317c6aSMerav Sicron 26355d317c6aSMerav Sicron return 0; 26365d317c6aSMerav Sicron } 26375d317c6aSMerav Sicron 2638adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2639815c7db5SBen Hutchings u32 *rules __always_unused) 2640adfc5217SJeff Kirsher { 2641adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2642adfc5217SJeff Kirsher 2643adfc5217SJeff Kirsher switch (info->cmd) { 2644adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 2645adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 2646adfc5217SJeff Kirsher return 0; 26475d317c6aSMerav Sicron case ETHTOOL_GRXFH: 26485d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 26495d317c6aSMerav Sicron default: 26505d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 26515d317c6aSMerav Sicron return -EOPNOTSUPP; 26525d317c6aSMerav Sicron } 26535d317c6aSMerav Sicron } 2654adfc5217SJeff Kirsher 26555d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 26565d317c6aSMerav Sicron { 26575d317c6aSMerav Sicron int udp_rss_requested; 26585d317c6aSMerav Sicron 26595d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26605d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 26615d317c6aSMerav Sicron info->flow_type, info->data); 26625d317c6aSMerav Sicron 26635d317c6aSMerav Sicron switch (info->flow_type) { 26645d317c6aSMerav Sicron case TCP_V4_FLOW: 26655d317c6aSMerav Sicron case TCP_V6_FLOW: 26665d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 26675d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 26685d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 26695d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26705d317c6aSMerav Sicron "Command parameters not supported\n"); 26715d317c6aSMerav Sicron return -EINVAL; 26725d317c6aSMerav Sicron } else { 26735d317c6aSMerav Sicron return 0; 26745d317c6aSMerav Sicron } 26755d317c6aSMerav Sicron 26765d317c6aSMerav Sicron case UDP_V4_FLOW: 26775d317c6aSMerav Sicron case UDP_V6_FLOW: 26785d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 26795d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 26805d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 26815d317c6aSMerav Sicron udp_rss_requested = 1; 26825d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 26835d317c6aSMerav Sicron udp_rss_requested = 0; 26845d317c6aSMerav Sicron else 26855d317c6aSMerav Sicron return -EINVAL; 26865d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 26875d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 26885d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 26895d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26905d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 26915d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 26925d317c6aSMerav Sicron return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 26935d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 26945d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 26955d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 26965d317c6aSMerav Sicron return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 26975d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26985d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 26995d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 27005d317c6aSMerav Sicron } else { 27015d317c6aSMerav Sicron return 0; 27025d317c6aSMerav Sicron } 27035d317c6aSMerav Sicron case IPV4_FLOW: 27045d317c6aSMerav Sicron case IPV6_FLOW: 27055d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 27065d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 27075d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27085d317c6aSMerav Sicron "Command parameters not supported\n"); 27095d317c6aSMerav Sicron return -EINVAL; 27105d317c6aSMerav Sicron } else { 27115d317c6aSMerav Sicron return 0; 27125d317c6aSMerav Sicron } 27135d317c6aSMerav Sicron case SCTP_V4_FLOW: 27145d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 27155d317c6aSMerav Sicron case AH_V4_FLOW: 27165d317c6aSMerav Sicron case ESP_V4_FLOW: 27175d317c6aSMerav Sicron case SCTP_V6_FLOW: 27185d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 27195d317c6aSMerav Sicron case AH_V6_FLOW: 27205d317c6aSMerav Sicron case ESP_V6_FLOW: 27215d317c6aSMerav Sicron case IP_USER_FLOW: 27225d317c6aSMerav Sicron case ETHER_FLOW: 27235d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 27245d317c6aSMerav Sicron if (info->data) { 27255d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27265d317c6aSMerav Sicron "Command parameters not supported\n"); 27275d317c6aSMerav Sicron return -EINVAL; 27285d317c6aSMerav Sicron } else { 27295d317c6aSMerav Sicron return 0; 27305d317c6aSMerav Sicron } 27315d317c6aSMerav Sicron default: 27325d317c6aSMerav Sicron return -EINVAL; 27335d317c6aSMerav Sicron } 27345d317c6aSMerav Sicron } 27355d317c6aSMerav Sicron 27365d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 27375d317c6aSMerav Sicron { 27385d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 27395d317c6aSMerav Sicron 27405d317c6aSMerav Sicron switch (info->cmd) { 27415d317c6aSMerav Sicron case ETHTOOL_SRXFH: 27425d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 2743adfc5217SJeff Kirsher default: 274451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2745adfc5217SJeff Kirsher return -EOPNOTSUPP; 2746adfc5217SJeff Kirsher } 2747adfc5217SJeff Kirsher } 2748adfc5217SJeff Kirsher 27497850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 2750adfc5217SJeff Kirsher { 275196305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 27527850f63fSBen Hutchings } 27537850f63fSBen Hutchings 27547850f63fSBen Hutchings static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 27557850f63fSBen Hutchings { 27567850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 2757adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2758adfc5217SJeff Kirsher size_t i; 2759adfc5217SJeff Kirsher 2760adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 2761adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 2762adfc5217SJeff Kirsher 2763adfc5217SJeff Kirsher /* 2764adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 2765adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 2766adfc5217SJeff Kirsher * points to an array of u32. 2767adfc5217SJeff Kirsher * 2768adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2769adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 2770adfc5217SJeff Kirsher * queue. 2771adfc5217SJeff Kirsher */ 27727850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 27737850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 2774adfc5217SJeff Kirsher 2775adfc5217SJeff Kirsher return 0; 2776adfc5217SJeff Kirsher } 2777adfc5217SJeff Kirsher 27787850f63fSBen Hutchings static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 2779adfc5217SJeff Kirsher { 2780adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2781adfc5217SJeff Kirsher size_t i; 2782adfc5217SJeff Kirsher 2783adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2784adfc5217SJeff Kirsher /* 2785adfc5217SJeff Kirsher * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 2786adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 2787adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 2788adfc5217SJeff Kirsher * 2789adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2790adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 2791adfc5217SJeff Kirsher * queue 2792adfc5217SJeff Kirsher */ 27935d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 2794adfc5217SJeff Kirsher } 2795adfc5217SJeff Kirsher 27965d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 2797adfc5217SJeff Kirsher } 2798adfc5217SJeff Kirsher 2799adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 2800adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 2801adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 2802adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 2803adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 2804adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 2805adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 2806adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 2807adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 2808adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 2809adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 2810adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 2811adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 2812adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 2813adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 2814adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 2815adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 2816adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 2817adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 2818adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 2819adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 2820adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 2821adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 2822adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 2823adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 2824adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 2825adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 28265d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 28277850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 2828adfc5217SJeff Kirsher .get_rxfh_indir = bnx2x_get_rxfh_indir, 2829adfc5217SJeff Kirsher .set_rxfh_indir = bnx2x_set_rxfh_indir, 2830e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 2831e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 2832adfc5217SJeff Kirsher }; 2833adfc5217SJeff Kirsher 2834adfc5217SJeff Kirsher void bnx2x_set_ethtool_ops(struct net_device *netdev) 2835adfc5217SJeff Kirsher { 2836adfc5217SJeff Kirsher SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 2837adfc5217SJeff Kirsher } 2838