1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 385b26ea1SAriel Elior * Copyright (c) 2007-2012 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher 26adfc5217SJeff Kirsher 27adfc5217SJeff Kirsher #include "bnx2x.h" 28adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 29adfc5217SJeff Kirsher #include "bnx2x_dump.h" 30adfc5217SJeff Kirsher #include "bnx2x_init.h" 31adfc5217SJeff Kirsher #include "bnx2x_sp.h" 32adfc5217SJeff Kirsher 33adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 34adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 35adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 36adfc5217SJeff Kirsher */ 37adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 38adfc5217SJeff Kirsher static const struct { 39adfc5217SJeff Kirsher long offset; 40adfc5217SJeff Kirsher int size; 41adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 42adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 43adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 44adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 45adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 46adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 47adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 49adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 51adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 52adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 53adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 54adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 55adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 56adfc5217SJeff Kirsher 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 58adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 59adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 60adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 61adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 62adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 63adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 64adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 65adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 66adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 67adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 68adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"} 69adfc5217SJeff Kirsher }; 70adfc5217SJeff Kirsher 71adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 72adfc5217SJeff Kirsher 73adfc5217SJeff Kirsher static const struct { 74adfc5217SJeff Kirsher long offset; 75adfc5217SJeff Kirsher int size; 76adfc5217SJeff Kirsher u32 flags; 77adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 78adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 79adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 80adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 81adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 82adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 83adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 84adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 85adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 86adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 87adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 88adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 89adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 90adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 91adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 92adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 93adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 94adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 95adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 96adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 97adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 98adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 99adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 100adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 101adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 102adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 103adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 104adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 105adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 106adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 107adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 108adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 109adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1100e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1110e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1120e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1130e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 114adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 115adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 116adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 117adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 118adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 119adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 120adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 121adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 122adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 123adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 124adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 125adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 126adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 127adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 128adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 129adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 130adfc5217SJeff Kirsher 131adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 132adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 133adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 134adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 135adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 136adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 137adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 138adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 139adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 140adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 141adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 142adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 143adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 144adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 145adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 146adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 147adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 148adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 149adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 150adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 151adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 152adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 153adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 154adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 155adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 156adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 157adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 158adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 159adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 160adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 161adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 162adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 163adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 164adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 165adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 166adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 167adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 168adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 169adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 170adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 171adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 172adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 173adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 174adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 175adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 176adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 177adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1787a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1797a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1807a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1817a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1827a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 183adfc5217SJeff Kirsher }; 184adfc5217SJeff Kirsher 185adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 186adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 187adfc5217SJeff Kirsher { 188adfc5217SJeff Kirsher int port_type; 189adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 190adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 191adfc5217SJeff Kirsher case ETH_PHY_SFP_FIBER: 192adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 193adfc5217SJeff Kirsher case ETH_PHY_KR: 194adfc5217SJeff Kirsher case ETH_PHY_CX4: 195adfc5217SJeff Kirsher port_type = PORT_FIBRE; 196adfc5217SJeff Kirsher break; 197adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 198adfc5217SJeff Kirsher port_type = PORT_DA; 199adfc5217SJeff Kirsher break; 200adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 201adfc5217SJeff Kirsher port_type = PORT_TP; 202adfc5217SJeff Kirsher break; 203adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 204adfc5217SJeff Kirsher port_type = PORT_NONE; 205adfc5217SJeff Kirsher break; 206adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 207adfc5217SJeff Kirsher default: 208adfc5217SJeff Kirsher port_type = PORT_OTHER; 209adfc5217SJeff Kirsher break; 210adfc5217SJeff Kirsher } 211adfc5217SJeff Kirsher return port_type; 212adfc5217SJeff Kirsher } 213adfc5217SJeff Kirsher 214adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 215adfc5217SJeff Kirsher { 216adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 217adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 218adfc5217SJeff Kirsher 219adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 220adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 221adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 222adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 223adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 224adfc5217SJeff Kirsher 22538298461SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) { 22638298461SYuval Mintz if (!(bp->flags & MF_FUNC_DIS)) { 227adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 228adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 229adfc5217SJeff Kirsher } else { 230adfc5217SJeff Kirsher ethtool_cmd_speed_set( 231adfc5217SJeff Kirsher cmd, bp->link_params.req_line_speed[cfg_idx]); 232adfc5217SJeff Kirsher cmd->duplex = bp->link_params.req_duplex[cfg_idx]; 233adfc5217SJeff Kirsher } 234adfc5217SJeff Kirsher 23538298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 236adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 23738298461SYuval Mintz } else { 23838298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 23938298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 24038298461SYuval Mintz } 241adfc5217SJeff Kirsher 242adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 243adfc5217SJeff Kirsher 244adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 245adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 246adfc5217SJeff Kirsher 247adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 248adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 249adfc5217SJeff Kirsher else 250adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 251adfc5217SJeff Kirsher 2529e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2539e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2549e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2559e7e8399SMintz Yuval 2569e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 2579e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 2589e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 2599e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 2609e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 2619e7e8399SMintz Yuval 2629e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 2639e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 2649e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 2659e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 2669e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 2679e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 2689e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 2699e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 2709e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 2719e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 2729e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 2739e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 2749e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 2759e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 2769e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 2779e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 2789e7e8399SMintz Yuval } 2799e7e8399SMintz Yuval 280adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 281adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 282adfc5217SJeff Kirsher 283adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 284f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 285f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 286f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 287adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 288adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 289adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 290adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 291adfc5217SJeff Kirsher 292adfc5217SJeff Kirsher return 0; 293adfc5217SJeff Kirsher } 294adfc5217SJeff Kirsher 295adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 296adfc5217SJeff Kirsher { 297adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 298adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 299adfc5217SJeff Kirsher u32 speed; 300adfc5217SJeff Kirsher 301adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 302adfc5217SJeff Kirsher return 0; 303adfc5217SJeff Kirsher 304adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 305adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 306adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 307adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 308adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 309adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 310adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 311adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 312adfc5217SJeff Kirsher 313adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 314adfc5217SJeff Kirsher 31538298461SYuval Mintz /* If recieved a request for an unknown duplex, assume full*/ 31638298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 31738298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 31838298461SYuval Mintz 319adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 320adfc5217SJeff Kirsher u32 part; 321adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 322adfc5217SJeff Kirsher 323adfc5217SJeff Kirsher /* use 10G if no link detected */ 324adfc5217SJeff Kirsher if (!line_speed) 325adfc5217SJeff Kirsher line_speed = 10000; 326adfc5217SJeff Kirsher 327adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 328adfc5217SJeff Kirsher BNX2X_DEV_INFO("To set speed BC %X or higher " 329adfc5217SJeff Kirsher "is required, please upgrade BC\n", 330adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 331adfc5217SJeff Kirsher return -EINVAL; 332adfc5217SJeff Kirsher } 333adfc5217SJeff Kirsher 334adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 335adfc5217SJeff Kirsher 336adfc5217SJeff Kirsher if (line_speed < speed || !part) { 337adfc5217SJeff Kirsher BNX2X_DEV_INFO("Speed setting should be in a range " 338adfc5217SJeff Kirsher "from 1%% to 100%% " 339adfc5217SJeff Kirsher "of actual line speed\n"); 340adfc5217SJeff Kirsher return -EINVAL; 341adfc5217SJeff Kirsher } 342adfc5217SJeff Kirsher 343adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 344adfc5217SJeff Kirsher /* store value for following "load" */ 345adfc5217SJeff Kirsher bp->pending_max = part; 346adfc5217SJeff Kirsher else 347adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 348adfc5217SJeff Kirsher 349adfc5217SJeff Kirsher return 0; 350adfc5217SJeff Kirsher } 351adfc5217SJeff Kirsher 352adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 353adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 354adfc5217SJeff Kirsher switch (cmd->port) { 355adfc5217SJeff Kirsher case PORT_TP: 356adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 357adfc5217SJeff Kirsher break; /* no port change */ 358adfc5217SJeff Kirsher 359adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 360adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 361adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "Unsupported port type\n"); 362adfc5217SJeff Kirsher return -EINVAL; 363adfc5217SJeff Kirsher } 364adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 365adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 366adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 367adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 368adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 369adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 370adfc5217SJeff Kirsher else 371adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 372adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 373adfc5217SJeff Kirsher break; 374adfc5217SJeff Kirsher case PORT_FIBRE: 375bfdb5823SYaniv Rosner case PORT_DA: 376adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 377adfc5217SJeff Kirsher break; /* no port change */ 378adfc5217SJeff Kirsher 379adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 380adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 381adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "Unsupported port type\n"); 382adfc5217SJeff Kirsher return -EINVAL; 383adfc5217SJeff Kirsher } 384adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 385adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 386adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 387adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 388adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 389adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 390adfc5217SJeff Kirsher else 391adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 392adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 393adfc5217SJeff Kirsher break; 394adfc5217SJeff Kirsher default: 395adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "Unsupported port type\n"); 396adfc5217SJeff Kirsher return -EINVAL; 397adfc5217SJeff Kirsher } 3982f751a80SYaniv Rosner /* Save new config in case command complete successully */ 399adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 400adfc5217SJeff Kirsher /* Get the new cfg_idx */ 401adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 402adfc5217SJeff Kirsher /* Restore old config in case command failed */ 403adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 404adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx); 405adfc5217SJeff Kirsher 406adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 40775318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 40875318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 40975318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 41075318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 41175318327SYaniv Rosner SUPPORTED_100baseT_Full); 412adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 413adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "Autoneg not supported\n"); 414adfc5217SJeff Kirsher return -EINVAL; 415adfc5217SJeff Kirsher } 416adfc5217SJeff Kirsher 417adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 41875318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 4198decf868SDavid S. Miller DP(NETIF_MSG_LINK, "Advertisement parameters " 4208decf868SDavid S. Miller "are not supported\n"); 4218decf868SDavid S. Miller return -EINVAL; 4228decf868SDavid S. Miller } 423adfc5217SJeff Kirsher 424adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4258decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4268decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 427adfc5217SJeff Kirsher cmd->advertising); 4288decf868SDavid S. Miller if (cmd->advertising) { 429adfc5217SJeff Kirsher 4308decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4318decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4328decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4338decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4348decf868SDavid S. Miller } 4358decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4368decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4378decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4388decf868SDavid S. Miller 4398decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4408decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4418decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4428decf868SDavid S. Miller 4438decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4448decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4458decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4468decf868SDavid S. Miller } 4478decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4488decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4498decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4508decf868SDavid S. Miller } 4518decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4528decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4538decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4548decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4558decf868SDavid S. Miller 4568decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4578decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 4588decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 4598decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4608decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 4618decf868SDavid S. Miller } 462adfc5217SJeff Kirsher } else { /* forced speed */ 463adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 464adfc5217SJeff Kirsher switch (speed) { 465adfc5217SJeff Kirsher case SPEED_10: 466adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 467adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 468adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 469adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, 470adfc5217SJeff Kirsher "10M full not supported\n"); 471adfc5217SJeff Kirsher return -EINVAL; 472adfc5217SJeff Kirsher } 473adfc5217SJeff Kirsher 474adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 475adfc5217SJeff Kirsher ADVERTISED_TP); 476adfc5217SJeff Kirsher } else { 477adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 478adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 479adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, 480adfc5217SJeff Kirsher "10M half not supported\n"); 481adfc5217SJeff Kirsher return -EINVAL; 482adfc5217SJeff Kirsher } 483adfc5217SJeff Kirsher 484adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 485adfc5217SJeff Kirsher ADVERTISED_TP); 486adfc5217SJeff Kirsher } 487adfc5217SJeff Kirsher break; 488adfc5217SJeff Kirsher 489adfc5217SJeff Kirsher case SPEED_100: 490adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 491adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 492adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 493adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, 494adfc5217SJeff Kirsher "100M full not supported\n"); 495adfc5217SJeff Kirsher return -EINVAL; 496adfc5217SJeff Kirsher } 497adfc5217SJeff Kirsher 498adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 499adfc5217SJeff Kirsher ADVERTISED_TP); 500adfc5217SJeff Kirsher } else { 501adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 502adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 503adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, 504adfc5217SJeff Kirsher "100M half not supported\n"); 505adfc5217SJeff Kirsher return -EINVAL; 506adfc5217SJeff Kirsher } 507adfc5217SJeff Kirsher 508adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 509adfc5217SJeff Kirsher ADVERTISED_TP); 510adfc5217SJeff Kirsher } 511adfc5217SJeff Kirsher break; 512adfc5217SJeff Kirsher 513adfc5217SJeff Kirsher case SPEED_1000: 514adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 515adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "1G half not supported\n"); 516adfc5217SJeff Kirsher return -EINVAL; 517adfc5217SJeff Kirsher } 518adfc5217SJeff Kirsher 519adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 520adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 521adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "1G full not supported\n"); 522adfc5217SJeff Kirsher return -EINVAL; 523adfc5217SJeff Kirsher } 524adfc5217SJeff Kirsher 525adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 526adfc5217SJeff Kirsher ADVERTISED_TP); 527adfc5217SJeff Kirsher break; 528adfc5217SJeff Kirsher 529adfc5217SJeff Kirsher case SPEED_2500: 530adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 531adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, 532adfc5217SJeff Kirsher "2.5G half not supported\n"); 533adfc5217SJeff Kirsher return -EINVAL; 534adfc5217SJeff Kirsher } 535adfc5217SJeff Kirsher 536adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 537adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 538adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, 539adfc5217SJeff Kirsher "2.5G full not supported\n"); 540adfc5217SJeff Kirsher return -EINVAL; 541adfc5217SJeff Kirsher } 542adfc5217SJeff Kirsher 543adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 544adfc5217SJeff Kirsher ADVERTISED_TP); 545adfc5217SJeff Kirsher break; 546adfc5217SJeff Kirsher 547adfc5217SJeff Kirsher case SPEED_10000: 548adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 549adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "10G half not supported\n"); 550adfc5217SJeff Kirsher return -EINVAL; 551adfc5217SJeff Kirsher } 552adfc5217SJeff Kirsher 553adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 554adfc5217SJeff Kirsher & SUPPORTED_10000baseT_Full)) { 555adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "10G full not supported\n"); 556adfc5217SJeff Kirsher return -EINVAL; 557adfc5217SJeff Kirsher } 558adfc5217SJeff Kirsher 559adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 560adfc5217SJeff Kirsher ADVERTISED_FIBRE); 561adfc5217SJeff Kirsher break; 562adfc5217SJeff Kirsher 563adfc5217SJeff Kirsher default: 564adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed); 565adfc5217SJeff Kirsher return -EINVAL; 566adfc5217SJeff Kirsher } 567adfc5217SJeff Kirsher 568adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 569adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 570adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 571adfc5217SJeff Kirsher } 572adfc5217SJeff Kirsher 573adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "req_line_speed %d\n" 574f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 575adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 576adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 577adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 578adfc5217SJeff Kirsher 579adfc5217SJeff Kirsher /* Set new config */ 580adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 581adfc5217SJeff Kirsher if (netif_running(dev)) { 582adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 583adfc5217SJeff Kirsher bnx2x_link_set(bp); 584adfc5217SJeff Kirsher } 585adfc5217SJeff Kirsher 586adfc5217SJeff Kirsher return 0; 587adfc5217SJeff Kirsher } 588adfc5217SJeff Kirsher 589adfc5217SJeff Kirsher #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) 590adfc5217SJeff Kirsher #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) 591adfc5217SJeff Kirsher #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) 592adfc5217SJeff Kirsher #define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE) 593adfc5217SJeff Kirsher #define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE) 594adfc5217SJeff Kirsher 595adfc5217SJeff Kirsher static inline bool bnx2x_is_reg_online(struct bnx2x *bp, 596adfc5217SJeff Kirsher const struct reg_addr *reg_info) 597adfc5217SJeff Kirsher { 598adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 599adfc5217SJeff Kirsher return IS_E1_ONLINE(reg_info->info); 600adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 601adfc5217SJeff Kirsher return IS_E1H_ONLINE(reg_info->info); 602adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 603adfc5217SJeff Kirsher return IS_E2_ONLINE(reg_info->info); 604adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 605adfc5217SJeff Kirsher return IS_E3_ONLINE(reg_info->info); 606adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 607adfc5217SJeff Kirsher return IS_E3B0_ONLINE(reg_info->info); 608adfc5217SJeff Kirsher else 609adfc5217SJeff Kirsher return false; 610adfc5217SJeff Kirsher } 611adfc5217SJeff Kirsher 612adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 613adfc5217SJeff Kirsher static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 614adfc5217SJeff Kirsher { 615adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 616adfc5217SJeff Kirsher return page_vals_e2; 617adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 618adfc5217SJeff Kirsher return page_vals_e3; 619adfc5217SJeff Kirsher else 620adfc5217SJeff Kirsher return NULL; 621adfc5217SJeff Kirsher } 622adfc5217SJeff Kirsher 623adfc5217SJeff Kirsher static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 624adfc5217SJeff Kirsher { 625adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 626adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 627adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 628adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 629adfc5217SJeff Kirsher else 630adfc5217SJeff Kirsher return 0; 631adfc5217SJeff Kirsher } 632adfc5217SJeff Kirsher 633adfc5217SJeff Kirsher static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 634adfc5217SJeff Kirsher { 635adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 636adfc5217SJeff Kirsher return page_write_regs_e2; 637adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 638adfc5217SJeff Kirsher return page_write_regs_e3; 639adfc5217SJeff Kirsher else 640adfc5217SJeff Kirsher return NULL; 641adfc5217SJeff Kirsher } 642adfc5217SJeff Kirsher 643adfc5217SJeff Kirsher static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 644adfc5217SJeff Kirsher { 645adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 646adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 647adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 648adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 649adfc5217SJeff Kirsher else 650adfc5217SJeff Kirsher return 0; 651adfc5217SJeff Kirsher } 652adfc5217SJeff Kirsher 653adfc5217SJeff Kirsher static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 654adfc5217SJeff Kirsher { 655adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 656adfc5217SJeff Kirsher return page_read_regs_e2; 657adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 658adfc5217SJeff Kirsher return page_read_regs_e3; 659adfc5217SJeff Kirsher else 660adfc5217SJeff Kirsher return NULL; 661adfc5217SJeff Kirsher } 662adfc5217SJeff Kirsher 663adfc5217SJeff Kirsher static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 664adfc5217SJeff Kirsher { 665adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 666adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 667adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 668adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 669adfc5217SJeff Kirsher else 670adfc5217SJeff Kirsher return 0; 671adfc5217SJeff Kirsher } 672adfc5217SJeff Kirsher 673adfc5217SJeff Kirsher static inline int __bnx2x_get_regs_len(struct bnx2x *bp) 674adfc5217SJeff Kirsher { 675adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 676adfc5217SJeff Kirsher int page_write_num = __bnx2x_get_page_write_num(bp); 677adfc5217SJeff Kirsher const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp); 678adfc5217SJeff Kirsher int page_read_num = __bnx2x_get_page_read_num(bp); 679adfc5217SJeff Kirsher int regdump_len = 0; 680adfc5217SJeff Kirsher int i, j, k; 681adfc5217SJeff Kirsher 682adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 683adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 684adfc5217SJeff Kirsher regdump_len += reg_addrs[i].size; 685adfc5217SJeff Kirsher 686adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) 687adfc5217SJeff Kirsher for (j = 0; j < page_write_num; j++) 688adfc5217SJeff Kirsher for (k = 0; k < page_read_num; k++) 689adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &page_read_addr[k])) 690adfc5217SJeff Kirsher regdump_len += page_read_addr[k].size; 691adfc5217SJeff Kirsher 692adfc5217SJeff Kirsher return regdump_len; 693adfc5217SJeff Kirsher } 694adfc5217SJeff Kirsher 695adfc5217SJeff Kirsher static int bnx2x_get_regs_len(struct net_device *dev) 696adfc5217SJeff Kirsher { 697adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 698adfc5217SJeff Kirsher int regdump_len = 0; 699adfc5217SJeff Kirsher 700adfc5217SJeff Kirsher regdump_len = __bnx2x_get_regs_len(bp); 701adfc5217SJeff Kirsher regdump_len *= 4; 702adfc5217SJeff Kirsher regdump_len += sizeof(struct dump_hdr); 703adfc5217SJeff Kirsher 704adfc5217SJeff Kirsher return regdump_len; 705adfc5217SJeff Kirsher } 706adfc5217SJeff Kirsher 707adfc5217SJeff Kirsher /** 708adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 709adfc5217SJeff Kirsher * 710adfc5217SJeff Kirsher * @bp device handle 711adfc5217SJeff Kirsher * @p output buffer 712adfc5217SJeff Kirsher * 713adfc5217SJeff Kirsher * Reads "paged" memories: memories that may only be read by first writing to a 714adfc5217SJeff Kirsher * specific address ("write address") and then reading from a specific address 715adfc5217SJeff Kirsher * ("read address"). There may be more than one write address per "page" and 716adfc5217SJeff Kirsher * more than one read address per write address. 717adfc5217SJeff Kirsher */ 718adfc5217SJeff Kirsher static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p) 719adfc5217SJeff Kirsher { 720adfc5217SJeff Kirsher u32 i, j, k, n; 721adfc5217SJeff Kirsher /* addresses of the paged registers */ 722adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 723adfc5217SJeff Kirsher /* number of paged registers */ 724adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 725adfc5217SJeff Kirsher /* write addresses */ 726adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 727adfc5217SJeff Kirsher /* number of write addresses */ 728adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 729adfc5217SJeff Kirsher /* read addresses info */ 730adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 731adfc5217SJeff Kirsher /* number of read addresses */ 732adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 733adfc5217SJeff Kirsher 734adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 735adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 736adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 737adfc5217SJeff Kirsher for (k = 0; k < read_num; k++) 738adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &read_addr[k])) 739adfc5217SJeff Kirsher for (n = 0; n < 740adfc5217SJeff Kirsher read_addr[k].size; n++) 741adfc5217SJeff Kirsher *p++ = REG_RD(bp, 742adfc5217SJeff Kirsher read_addr[k].addr + n*4); 743adfc5217SJeff Kirsher } 744adfc5217SJeff Kirsher } 745adfc5217SJeff Kirsher } 746adfc5217SJeff Kirsher 747adfc5217SJeff Kirsher static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 748adfc5217SJeff Kirsher { 749adfc5217SJeff Kirsher u32 i, j; 750adfc5217SJeff Kirsher 751adfc5217SJeff Kirsher /* Read the regular registers */ 752adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 753adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 754adfc5217SJeff Kirsher for (j = 0; j < reg_addrs[i].size; j++) 755adfc5217SJeff Kirsher *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 756adfc5217SJeff Kirsher 757adfc5217SJeff Kirsher /* Read "paged" registes */ 758adfc5217SJeff Kirsher bnx2x_read_pages_regs(bp, p); 759adfc5217SJeff Kirsher } 760adfc5217SJeff Kirsher 761adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 762adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 763adfc5217SJeff Kirsher { 764adfc5217SJeff Kirsher u32 *p = _p; 765adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 766adfc5217SJeff Kirsher struct dump_hdr dump_hdr = {0}; 767adfc5217SJeff Kirsher 768adfc5217SJeff Kirsher regs->version = 0; 769adfc5217SJeff Kirsher memset(p, 0, regs->len); 770adfc5217SJeff Kirsher 771adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 772adfc5217SJeff Kirsher return; 773adfc5217SJeff Kirsher 774adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 775adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 776adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 777adfc5217SJeff Kirsher */ 778adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 779adfc5217SJeff Kirsher 780adfc5217SJeff Kirsher dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; 781adfc5217SJeff Kirsher dump_hdr.dump_sign = dump_sign_all; 782adfc5217SJeff Kirsher dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); 783adfc5217SJeff Kirsher dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); 784adfc5217SJeff Kirsher dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); 785adfc5217SJeff Kirsher dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); 786adfc5217SJeff Kirsher 787adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 788adfc5217SJeff Kirsher dump_hdr.info = RI_E1_ONLINE; 789adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 790adfc5217SJeff Kirsher dump_hdr.info = RI_E1H_ONLINE; 791adfc5217SJeff Kirsher else if (!CHIP_IS_E1x(bp)) 792adfc5217SJeff Kirsher dump_hdr.info = RI_E2_ONLINE | 793adfc5217SJeff Kirsher (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); 794adfc5217SJeff Kirsher 795adfc5217SJeff Kirsher memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); 796adfc5217SJeff Kirsher p += dump_hdr.hdr_size + 1; 797adfc5217SJeff Kirsher 798adfc5217SJeff Kirsher /* Actually read the registers */ 799adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 800adfc5217SJeff Kirsher 801adfc5217SJeff Kirsher /* Re-enable parity attentions */ 802adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 803adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 804adfc5217SJeff Kirsher } 805adfc5217SJeff Kirsher 806adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 807adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 808adfc5217SJeff Kirsher { 809adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 810adfc5217SJeff Kirsher u8 phy_fw_ver[PHY_FW_VER_LEN]; 811adfc5217SJeff Kirsher 81268aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 81368aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 814adfc5217SJeff Kirsher 815adfc5217SJeff Kirsher phy_fw_ver[0] = '\0'; 816adfc5217SJeff Kirsher bnx2x_get_ext_phy_fw_version(&bp->link_params, 817adfc5217SJeff Kirsher phy_fw_ver, PHY_FW_VER_LEN); 81868aad78cSRick Jones strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version)); 819adfc5217SJeff Kirsher snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), 820adfc5217SJeff Kirsher "bc %d.%d.%d%s%s", 821adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff0000) >> 16, 822adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff00) >> 8, 823adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff), 824adfc5217SJeff Kirsher ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); 82568aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 826adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 827adfc5217SJeff Kirsher info->testinfo_len = BNX2X_NUM_TESTS; 828adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 829adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 830adfc5217SJeff Kirsher } 831adfc5217SJeff Kirsher 832adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 833adfc5217SJeff Kirsher { 834adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 835adfc5217SJeff Kirsher 836adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 837adfc5217SJeff Kirsher wol->supported = 0; 838adfc5217SJeff Kirsher wol->wolopts = 0; 839adfc5217SJeff Kirsher } else { 840adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 841adfc5217SJeff Kirsher if (bp->wol) 842adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 843adfc5217SJeff Kirsher else 844adfc5217SJeff Kirsher wol->wolopts = 0; 845adfc5217SJeff Kirsher } 846adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 847adfc5217SJeff Kirsher } 848adfc5217SJeff Kirsher 849adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 850adfc5217SJeff Kirsher { 851adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 852adfc5217SJeff Kirsher 853adfc5217SJeff Kirsher if (wol->wolopts & ~WAKE_MAGIC) 854adfc5217SJeff Kirsher return -EINVAL; 855adfc5217SJeff Kirsher 856adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 857adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) 858adfc5217SJeff Kirsher return -EINVAL; 859adfc5217SJeff Kirsher 860adfc5217SJeff Kirsher bp->wol = 1; 861adfc5217SJeff Kirsher } else 862adfc5217SJeff Kirsher bp->wol = 0; 863adfc5217SJeff Kirsher 864adfc5217SJeff Kirsher return 0; 865adfc5217SJeff Kirsher } 866adfc5217SJeff Kirsher 867adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 868adfc5217SJeff Kirsher { 869adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 870adfc5217SJeff Kirsher 871adfc5217SJeff Kirsher return bp->msg_enable; 872adfc5217SJeff Kirsher } 873adfc5217SJeff Kirsher 874adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 875adfc5217SJeff Kirsher { 876adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 877adfc5217SJeff Kirsher 878adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 879adfc5217SJeff Kirsher /* dump MCP trace */ 880adfc5217SJeff Kirsher if (level & BNX2X_MSG_MCP) 881adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 882adfc5217SJeff Kirsher bp->msg_enable = level; 883adfc5217SJeff Kirsher } 884adfc5217SJeff Kirsher } 885adfc5217SJeff Kirsher 886adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 887adfc5217SJeff Kirsher { 888adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 889adfc5217SJeff Kirsher 890adfc5217SJeff Kirsher if (!bp->port.pmf) 891adfc5217SJeff Kirsher return 0; 892adfc5217SJeff Kirsher 893adfc5217SJeff Kirsher if (netif_running(dev)) { 894adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 895adfc5217SJeff Kirsher bnx2x_link_set(bp); 896adfc5217SJeff Kirsher } 897adfc5217SJeff Kirsher 898adfc5217SJeff Kirsher return 0; 899adfc5217SJeff Kirsher } 900adfc5217SJeff Kirsher 901adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 902adfc5217SJeff Kirsher { 903adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 904adfc5217SJeff Kirsher 905adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 906adfc5217SJeff Kirsher return 0; 907adfc5217SJeff Kirsher 908adfc5217SJeff Kirsher return bp->link_vars.link_up; 909adfc5217SJeff Kirsher } 910adfc5217SJeff Kirsher 911adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 912adfc5217SJeff Kirsher { 913adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 914adfc5217SJeff Kirsher 915adfc5217SJeff Kirsher return bp->common.flash_size; 916adfc5217SJeff Kirsher } 917adfc5217SJeff Kirsher 918f16da43bSAriel Elior /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had 919f16da43bSAriel Elior * we done things the other way around, if two pfs from the same port would 920f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 921f16da43bSAriel Elior * as: 922f16da43bSAriel Elior * pf A takes the port lock. 923f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 924f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 925f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 926f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 927f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 928f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 929f16da43bSAriel Elior * acess corrupted by pf B).* 930f16da43bSAriel Elior */ 931adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 932adfc5217SJeff Kirsher { 933adfc5217SJeff Kirsher int port = BP_PORT(bp); 934adfc5217SJeff Kirsher int count, i; 935f16da43bSAriel Elior u32 val; 936f16da43bSAriel Elior 937f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 938f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 939adfc5217SJeff Kirsher 940adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 941adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 942adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 943adfc5217SJeff Kirsher count *= 100; 944adfc5217SJeff Kirsher 945adfc5217SJeff Kirsher /* request access to nvram interface */ 946adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 947adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 948adfc5217SJeff Kirsher 949adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 950adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 951adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 952adfc5217SJeff Kirsher break; 953adfc5217SJeff Kirsher 954adfc5217SJeff Kirsher udelay(5); 955adfc5217SJeff Kirsher } 956adfc5217SJeff Kirsher 957adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 958adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n"); 959adfc5217SJeff Kirsher return -EBUSY; 960adfc5217SJeff Kirsher } 961adfc5217SJeff Kirsher 962adfc5217SJeff Kirsher return 0; 963adfc5217SJeff Kirsher } 964adfc5217SJeff Kirsher 965adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 966adfc5217SJeff Kirsher { 967adfc5217SJeff Kirsher int port = BP_PORT(bp); 968adfc5217SJeff Kirsher int count, i; 969f16da43bSAriel Elior u32 val; 970adfc5217SJeff Kirsher 971adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 972adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 973adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 974adfc5217SJeff Kirsher count *= 100; 975adfc5217SJeff Kirsher 976adfc5217SJeff Kirsher /* relinquish nvram interface */ 977adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 978adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 979adfc5217SJeff Kirsher 980adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 981adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 982adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 983adfc5217SJeff Kirsher break; 984adfc5217SJeff Kirsher 985adfc5217SJeff Kirsher udelay(5); 986adfc5217SJeff Kirsher } 987adfc5217SJeff Kirsher 988adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 989adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n"); 990adfc5217SJeff Kirsher return -EBUSY; 991adfc5217SJeff Kirsher } 992adfc5217SJeff Kirsher 993f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 994f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 995adfc5217SJeff Kirsher return 0; 996adfc5217SJeff Kirsher } 997adfc5217SJeff Kirsher 998adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 999adfc5217SJeff Kirsher { 1000adfc5217SJeff Kirsher u32 val; 1001adfc5217SJeff Kirsher 1002adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1003adfc5217SJeff Kirsher 1004adfc5217SJeff Kirsher /* enable both bits, even on read */ 1005adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1006adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1007adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1008adfc5217SJeff Kirsher } 1009adfc5217SJeff Kirsher 1010adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1011adfc5217SJeff Kirsher { 1012adfc5217SJeff Kirsher u32 val; 1013adfc5217SJeff Kirsher 1014adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1015adfc5217SJeff Kirsher 1016adfc5217SJeff Kirsher /* disable both bits, even after read */ 1017adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1018adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1019adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1020adfc5217SJeff Kirsher } 1021adfc5217SJeff Kirsher 1022adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1023adfc5217SJeff Kirsher u32 cmd_flags) 1024adfc5217SJeff Kirsher { 1025adfc5217SJeff Kirsher int count, i, rc; 1026adfc5217SJeff Kirsher u32 val; 1027adfc5217SJeff Kirsher 1028adfc5217SJeff Kirsher /* build the command word */ 1029adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1030adfc5217SJeff Kirsher 1031adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1032adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1033adfc5217SJeff Kirsher 1034adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1035adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1036adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1037adfc5217SJeff Kirsher 1038adfc5217SJeff Kirsher /* issue a read command */ 1039adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1040adfc5217SJeff Kirsher 1041adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1042adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1043adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1044adfc5217SJeff Kirsher count *= 100; 1045adfc5217SJeff Kirsher 1046adfc5217SJeff Kirsher /* wait for completion */ 1047adfc5217SJeff Kirsher *ret_val = 0; 1048adfc5217SJeff Kirsher rc = -EBUSY; 1049adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1050adfc5217SJeff Kirsher udelay(5); 1051adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1052adfc5217SJeff Kirsher 1053adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1054adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1055adfc5217SJeff Kirsher /* we read nvram data in cpu order 1056adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 1057adfc5217SJeff Kirsher * converting to big-endian will do the work */ 1058adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1059adfc5217SJeff Kirsher rc = 0; 1060adfc5217SJeff Kirsher break; 1061adfc5217SJeff Kirsher } 1062adfc5217SJeff Kirsher } 1063adfc5217SJeff Kirsher 1064adfc5217SJeff Kirsher return rc; 1065adfc5217SJeff Kirsher } 1066adfc5217SJeff Kirsher 1067adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1068adfc5217SJeff Kirsher int buf_size) 1069adfc5217SJeff Kirsher { 1070adfc5217SJeff Kirsher int rc; 1071adfc5217SJeff Kirsher u32 cmd_flags; 1072adfc5217SJeff Kirsher __be32 val; 1073adfc5217SJeff Kirsher 1074adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1075adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, 1076adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1077adfc5217SJeff Kirsher offset, buf_size); 1078adfc5217SJeff Kirsher return -EINVAL; 1079adfc5217SJeff Kirsher } 1080adfc5217SJeff Kirsher 1081adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 1082adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1083adfc5217SJeff Kirsher " buf_size (0x%x) > flash_size (0x%x)\n", 1084adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1085adfc5217SJeff Kirsher return -EINVAL; 1086adfc5217SJeff Kirsher } 1087adfc5217SJeff Kirsher 1088adfc5217SJeff Kirsher /* request access to nvram interface */ 1089adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1090adfc5217SJeff Kirsher if (rc) 1091adfc5217SJeff Kirsher return rc; 1092adfc5217SJeff Kirsher 1093adfc5217SJeff Kirsher /* enable access to nvram interface */ 1094adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1095adfc5217SJeff Kirsher 1096adfc5217SJeff Kirsher /* read the first word(s) */ 1097adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1098adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1099adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1100adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher /* advance to the next dword */ 1103adfc5217SJeff Kirsher offset += sizeof(u32); 1104adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1105adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1106adfc5217SJeff Kirsher cmd_flags = 0; 1107adfc5217SJeff Kirsher } 1108adfc5217SJeff Kirsher 1109adfc5217SJeff Kirsher if (rc == 0) { 1110adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1111adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1112adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1113adfc5217SJeff Kirsher } 1114adfc5217SJeff Kirsher 1115adfc5217SJeff Kirsher /* disable access to nvram interface */ 1116adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1117adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1118adfc5217SJeff Kirsher 1119adfc5217SJeff Kirsher return rc; 1120adfc5217SJeff Kirsher } 1121adfc5217SJeff Kirsher 1122adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1123adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1124adfc5217SJeff Kirsher { 1125adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1126adfc5217SJeff Kirsher int rc; 1127adfc5217SJeff Kirsher 1128adfc5217SJeff Kirsher if (!netif_running(dev)) 1129adfc5217SJeff Kirsher return -EAGAIN; 1130adfc5217SJeff Kirsher 1131adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1132f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1133adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1134adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1135adfc5217SJeff Kirsher 1136adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1137adfc5217SJeff Kirsher 1138adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1139adfc5217SJeff Kirsher 1140adfc5217SJeff Kirsher return rc; 1141adfc5217SJeff Kirsher } 1142adfc5217SJeff Kirsher 1143adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1144adfc5217SJeff Kirsher u32 cmd_flags) 1145adfc5217SJeff Kirsher { 1146adfc5217SJeff Kirsher int count, i, rc; 1147adfc5217SJeff Kirsher 1148adfc5217SJeff Kirsher /* build the command word */ 1149adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1150adfc5217SJeff Kirsher 1151adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1152adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1153adfc5217SJeff Kirsher 1154adfc5217SJeff Kirsher /* write the data */ 1155adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1156adfc5217SJeff Kirsher 1157adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1158adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1159adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1160adfc5217SJeff Kirsher 1161adfc5217SJeff Kirsher /* issue the write command */ 1162adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1163adfc5217SJeff Kirsher 1164adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1165adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1166adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1167adfc5217SJeff Kirsher count *= 100; 1168adfc5217SJeff Kirsher 1169adfc5217SJeff Kirsher /* wait for completion */ 1170adfc5217SJeff Kirsher rc = -EBUSY; 1171adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1172adfc5217SJeff Kirsher udelay(5); 1173adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1174adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1175adfc5217SJeff Kirsher rc = 0; 1176adfc5217SJeff Kirsher break; 1177adfc5217SJeff Kirsher } 1178adfc5217SJeff Kirsher } 1179adfc5217SJeff Kirsher 1180adfc5217SJeff Kirsher return rc; 1181adfc5217SJeff Kirsher } 1182adfc5217SJeff Kirsher 1183adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1184adfc5217SJeff Kirsher 1185adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1186adfc5217SJeff Kirsher int buf_size) 1187adfc5217SJeff Kirsher { 1188adfc5217SJeff Kirsher int rc; 1189adfc5217SJeff Kirsher u32 cmd_flags; 1190adfc5217SJeff Kirsher u32 align_offset; 1191adfc5217SJeff Kirsher __be32 val; 1192adfc5217SJeff Kirsher 1193adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 1194adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1195adfc5217SJeff Kirsher " buf_size (0x%x) > flash_size (0x%x)\n", 1196adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1197adfc5217SJeff Kirsher return -EINVAL; 1198adfc5217SJeff Kirsher } 1199adfc5217SJeff Kirsher 1200adfc5217SJeff Kirsher /* request access to nvram interface */ 1201adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1202adfc5217SJeff Kirsher if (rc) 1203adfc5217SJeff Kirsher return rc; 1204adfc5217SJeff Kirsher 1205adfc5217SJeff Kirsher /* enable access to nvram interface */ 1206adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1207adfc5217SJeff Kirsher 1208adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1209adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 1210adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); 1211adfc5217SJeff Kirsher 1212adfc5217SJeff Kirsher if (rc == 0) { 1213adfc5217SJeff Kirsher val &= ~(0xff << BYTE_OFFSET(offset)); 1214adfc5217SJeff Kirsher val |= (*data_buf << BYTE_OFFSET(offset)); 1215adfc5217SJeff Kirsher 1216adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 1217adfc5217SJeff Kirsher * convert it back to cpu order */ 1218adfc5217SJeff Kirsher val = be32_to_cpu(val); 1219adfc5217SJeff Kirsher 1220adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1221adfc5217SJeff Kirsher cmd_flags); 1222adfc5217SJeff Kirsher } 1223adfc5217SJeff Kirsher 1224adfc5217SJeff Kirsher /* disable access to nvram interface */ 1225adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1226adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1227adfc5217SJeff Kirsher 1228adfc5217SJeff Kirsher return rc; 1229adfc5217SJeff Kirsher } 1230adfc5217SJeff Kirsher 1231adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1232adfc5217SJeff Kirsher int buf_size) 1233adfc5217SJeff Kirsher { 1234adfc5217SJeff Kirsher int rc; 1235adfc5217SJeff Kirsher u32 cmd_flags; 1236adfc5217SJeff Kirsher u32 val; 1237adfc5217SJeff Kirsher u32 written_so_far; 1238adfc5217SJeff Kirsher 1239adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1240adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1241adfc5217SJeff Kirsher 1242adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1243adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, 1244adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1245adfc5217SJeff Kirsher offset, buf_size); 1246adfc5217SJeff Kirsher return -EINVAL; 1247adfc5217SJeff Kirsher } 1248adfc5217SJeff Kirsher 1249adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 1250adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1251adfc5217SJeff Kirsher " buf_size (0x%x) > flash_size (0x%x)\n", 1252adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1253adfc5217SJeff Kirsher return -EINVAL; 1254adfc5217SJeff Kirsher } 1255adfc5217SJeff Kirsher 1256adfc5217SJeff Kirsher /* request access to nvram interface */ 1257adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1258adfc5217SJeff Kirsher if (rc) 1259adfc5217SJeff Kirsher return rc; 1260adfc5217SJeff Kirsher 1261adfc5217SJeff Kirsher /* enable access to nvram interface */ 1262adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher written_so_far = 0; 1265adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1266adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1267adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1268adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1269adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1270adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1271adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1272adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1273adfc5217SJeff Kirsher 1274adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1277adfc5217SJeff Kirsher 1278adfc5217SJeff Kirsher /* advance to the next dword */ 1279adfc5217SJeff Kirsher offset += sizeof(u32); 1280adfc5217SJeff Kirsher data_buf += sizeof(u32); 1281adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1282adfc5217SJeff Kirsher cmd_flags = 0; 1283adfc5217SJeff Kirsher } 1284adfc5217SJeff Kirsher 1285adfc5217SJeff Kirsher /* disable access to nvram interface */ 1286adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1287adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1288adfc5217SJeff Kirsher 1289adfc5217SJeff Kirsher return rc; 1290adfc5217SJeff Kirsher } 1291adfc5217SJeff Kirsher 1292adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1293adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1294adfc5217SJeff Kirsher { 1295adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1296adfc5217SJeff Kirsher int port = BP_PORT(bp); 1297adfc5217SJeff Kirsher int rc = 0; 1298adfc5217SJeff Kirsher u32 ext_phy_config; 1299adfc5217SJeff Kirsher if (!netif_running(dev)) 1300adfc5217SJeff Kirsher return -EAGAIN; 1301adfc5217SJeff Kirsher 1302adfc5217SJeff Kirsher DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1303f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1304adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1305adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1308adfc5217SJeff Kirsher 1309adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1310adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1311adfc5217SJeff Kirsher !bp->port.pmf) 1312adfc5217SJeff Kirsher return -EINVAL; 1313adfc5217SJeff Kirsher 1314adfc5217SJeff Kirsher ext_phy_config = 1315adfc5217SJeff Kirsher SHMEM_RD(bp, 1316adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1317adfc5217SJeff Kirsher 1318adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1319adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1320adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1321adfc5217SJeff Kirsher 1322adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1323adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1324adfc5217SJeff Kirsher &bp->link_vars, 0); 1325adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1326adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1327adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1328adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1329adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1330adfc5217SJeff Kirsher bnx2x_link_report(bp); 1331adfc5217SJeff Kirsher 1332adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1333adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1334adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1335adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1336adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1337adfc5217SJeff Kirsher &bp->link_vars, 1); 1338adfc5217SJeff Kirsher 1339adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1340adfc5217SJeff Kirsher &bp->link_vars); 1341adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1342adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1343adfc5217SJeff Kirsher } 1344adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1345adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1346adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1347adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1348adfc5217SJeff Kirsher 1349adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1350adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1351adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1352adfc5217SJeff Kirsher 1353adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1354adfc5217SJeff Kirsher 1355adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1356adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1357adfc5217SJeff Kirsher 1358adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1359adfc5217SJeff Kirsher msleep(500); 1360adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1361adfc5217SJeff Kirsher msleep(500); 1362adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1363adfc5217SJeff Kirsher } 1364adfc5217SJeff Kirsher } else 1365adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1366adfc5217SJeff Kirsher 1367adfc5217SJeff Kirsher return rc; 1368adfc5217SJeff Kirsher } 1369adfc5217SJeff Kirsher 1370adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1371adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1372adfc5217SJeff Kirsher { 1373adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1374adfc5217SJeff Kirsher 1375adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1376adfc5217SJeff Kirsher 1377adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1378adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1379adfc5217SJeff Kirsher 1380adfc5217SJeff Kirsher return 0; 1381adfc5217SJeff Kirsher } 1382adfc5217SJeff Kirsher 1383adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1384adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1385adfc5217SJeff Kirsher { 1386adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1387adfc5217SJeff Kirsher 1388adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1389adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1390adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1391adfc5217SJeff Kirsher 1392adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1393adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1394adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1395adfc5217SJeff Kirsher 1396adfc5217SJeff Kirsher if (netif_running(dev)) 1397adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1398adfc5217SJeff Kirsher 1399adfc5217SJeff Kirsher return 0; 1400adfc5217SJeff Kirsher } 1401adfc5217SJeff Kirsher 1402adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1403adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1404adfc5217SJeff Kirsher { 1405adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1406adfc5217SJeff Kirsher 1407adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1408adfc5217SJeff Kirsher 1409adfc5217SJeff Kirsher if (bp->rx_ring_size) 1410adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1411adfc5217SJeff Kirsher else 1412adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1413adfc5217SJeff Kirsher 1414adfc5217SJeff Kirsher ering->tx_max_pending = MAX_TX_AVAIL; 1415adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1416adfc5217SJeff Kirsher } 1417adfc5217SJeff Kirsher 1418adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1419adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1420adfc5217SJeff Kirsher { 1421adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1422adfc5217SJeff Kirsher 1423adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 14247a752993SAriel Elior netdev_err(dev, "Handling parity error recovery. " 14257a752993SAriel Elior "Try again later\n"); 1426adfc5217SJeff Kirsher return -EAGAIN; 1427adfc5217SJeff Kirsher } 1428adfc5217SJeff Kirsher 1429adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1430adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1431adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1432adfc5217SJeff Kirsher (ering->tx_pending > MAX_TX_AVAIL) || 1433adfc5217SJeff Kirsher (ering->tx_pending <= MAX_SKB_FRAGS + 4)) 1434adfc5217SJeff Kirsher return -EINVAL; 1435adfc5217SJeff Kirsher 1436adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1437adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1438adfc5217SJeff Kirsher 1439adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1440adfc5217SJeff Kirsher } 1441adfc5217SJeff Kirsher 1442adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1443adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1444adfc5217SJeff Kirsher { 1445adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1446adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 14479e7e8399SMintz Yuval int cfg_reg; 14489e7e8399SMintz Yuval 1449adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1450adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1451adfc5217SJeff Kirsher 14529e7e8399SMintz Yuval if (!epause->autoneg) 14539e7e8399SMintz Yuval cfg_reg = bp->link_vars.flow_ctrl; 14549e7e8399SMintz Yuval else 14559e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 14569e7e8399SMintz Yuval 14579e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1458adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 14599e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1460adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1461adfc5217SJeff Kirsher 1462adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1463f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1464adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1465adfc5217SJeff Kirsher } 1466adfc5217SJeff Kirsher 1467adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1468adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1469adfc5217SJeff Kirsher { 1470adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1471adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1472adfc5217SJeff Kirsher if (IS_MF(bp)) 1473adfc5217SJeff Kirsher return 0; 1474adfc5217SJeff Kirsher 1475adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1476f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1477adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1478adfc5217SJeff Kirsher 1479adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1480adfc5217SJeff Kirsher 1481adfc5217SJeff Kirsher if (epause->rx_pause) 1482adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1483adfc5217SJeff Kirsher 1484adfc5217SJeff Kirsher if (epause->tx_pause) 1485adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1486adfc5217SJeff Kirsher 1487adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1488adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1489adfc5217SJeff Kirsher 1490adfc5217SJeff Kirsher if (epause->autoneg) { 1491adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1492adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "autoneg not supported\n"); 1493adfc5217SJeff Kirsher return -EINVAL; 1494adfc5217SJeff Kirsher } 1495adfc5217SJeff Kirsher 1496adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1497adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1498adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1499adfc5217SJeff Kirsher } 1500adfc5217SJeff Kirsher } 1501adfc5217SJeff Kirsher 1502adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, 1503adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1504adfc5217SJeff Kirsher 1505adfc5217SJeff Kirsher if (netif_running(dev)) { 1506adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1507adfc5217SJeff Kirsher bnx2x_link_set(bp); 1508adfc5217SJeff Kirsher } 1509adfc5217SJeff Kirsher 1510adfc5217SJeff Kirsher return 0; 1511adfc5217SJeff Kirsher } 1512adfc5217SJeff Kirsher 1513adfc5217SJeff Kirsher static const struct { 1514adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 1515adfc5217SJeff Kirsher } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = { 1516adfc5217SJeff Kirsher { "register_test (offline)" }, 1517adfc5217SJeff Kirsher { "memory_test (offline)" }, 1518adfc5217SJeff Kirsher { "loopback_test (offline)" }, 1519adfc5217SJeff Kirsher { "nvram_test (online)" }, 1520adfc5217SJeff Kirsher { "interrupt_test (online)" }, 1521adfc5217SJeff Kirsher { "link_test (online)" }, 1522adfc5217SJeff Kirsher { "idle check (online)" } 1523adfc5217SJeff Kirsher }; 1524adfc5217SJeff Kirsher 1525adfc5217SJeff Kirsher enum { 1526adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 1527adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 1528adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 1529adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 1530adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 1531adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 1532adfc5217SJeff Kirsher }; 1533adfc5217SJeff Kirsher 1534adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 1535adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 1536adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 1537adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 1538adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 1539adfc5217SJeff Kirsher 1540adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 1541adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 1542adfc5217SJeff Kirsher 1543adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 1544adfc5217SJeff Kirsher { 1545adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 1546adfc5217SJeff Kirsher u32 wr_val = 0, hw; 1547adfc5217SJeff Kirsher int port = BP_PORT(bp); 1548adfc5217SJeff Kirsher static const struct { 1549adfc5217SJeff Kirsher u32 hw; 1550adfc5217SJeff Kirsher u32 offset0; 1551adfc5217SJeff Kirsher u32 offset1; 1552adfc5217SJeff Kirsher u32 mask; 1553adfc5217SJeff Kirsher } reg_tbl[] = { 1554adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 1555adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 1556adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1557adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 1558adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 1559adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 1560adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1561adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 1562adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 1563adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 1564adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 1565adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 1566adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1567adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 1568adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1569adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 1570adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1571adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1572adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1573adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 1574adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 1575adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1576adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1577adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 1578adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1579adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 1580adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1581adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 1582adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1583adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 1584adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1585adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 1586adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1587adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 1588adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1589adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 1590adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1591adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 1592adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1593adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 1594adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1595adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 1596adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1597adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 1598adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1599adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 1600adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1601adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 1602adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1603adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 1604adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1605adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 1606adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1607adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 1608adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1609adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 1610adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1611adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 1612adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1613adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 1614adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 1615adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 1616adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1617adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 1618adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1619adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 1620adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1621adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 1622adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1623adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 1624adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1625adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 1626adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1627adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 1628adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1629adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 1630adfc5217SJeff Kirsher 1631adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 1632adfc5217SJeff Kirsher }; 1633adfc5217SJeff Kirsher 1634adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 1635adfc5217SJeff Kirsher return rc; 1636adfc5217SJeff Kirsher 1637adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1638adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 1639adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1640adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 1641adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1642adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 1643adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 1644adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 1645adfc5217SJeff Kirsher else /* e3 A0 */ 1646adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 1647adfc5217SJeff Kirsher 1648adfc5217SJeff Kirsher /* Repeat the test twice: 1649adfc5217SJeff Kirsher First by writing 0x00000000, second by writing 0xffffffff */ 1650adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 1651adfc5217SJeff Kirsher 1652adfc5217SJeff Kirsher switch (idx) { 1653adfc5217SJeff Kirsher case 0: 1654adfc5217SJeff Kirsher wr_val = 0; 1655adfc5217SJeff Kirsher break; 1656adfc5217SJeff Kirsher case 1: 1657adfc5217SJeff Kirsher wr_val = 0xffffffff; 1658adfc5217SJeff Kirsher break; 1659adfc5217SJeff Kirsher } 1660adfc5217SJeff Kirsher 1661adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 1662adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 1663adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 1664adfc5217SJeff Kirsher continue; 1665adfc5217SJeff Kirsher 1666adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 1667adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 1668adfc5217SJeff Kirsher 1669adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 1670adfc5217SJeff Kirsher 1671adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 1672adfc5217SJeff Kirsher 1673adfc5217SJeff Kirsher val = REG_RD(bp, offset); 1674adfc5217SJeff Kirsher 1675adfc5217SJeff Kirsher /* Restore the original register's value */ 1676adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 1677adfc5217SJeff Kirsher 1678adfc5217SJeff Kirsher /* verify value is as expected */ 1679adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 1680adfc5217SJeff Kirsher DP(NETIF_MSG_HW, 1681adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 1682adfc5217SJeff Kirsher offset, val, wr_val, mask); 1683adfc5217SJeff Kirsher goto test_reg_exit; 1684adfc5217SJeff Kirsher } 1685adfc5217SJeff Kirsher } 1686adfc5217SJeff Kirsher } 1687adfc5217SJeff Kirsher 1688adfc5217SJeff Kirsher rc = 0; 1689adfc5217SJeff Kirsher 1690adfc5217SJeff Kirsher test_reg_exit: 1691adfc5217SJeff Kirsher return rc; 1692adfc5217SJeff Kirsher } 1693adfc5217SJeff Kirsher 1694adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 1695adfc5217SJeff Kirsher { 1696adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 1697adfc5217SJeff Kirsher u32 val, index; 1698adfc5217SJeff Kirsher static const struct { 1699adfc5217SJeff Kirsher u32 offset; 1700adfc5217SJeff Kirsher int size; 1701adfc5217SJeff Kirsher } mem_tbl[] = { 1702adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 1703adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 1704adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 1705adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 1706adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 1707adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 1708adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 1709adfc5217SJeff Kirsher 1710adfc5217SJeff Kirsher { 0xffffffff, 0 } 1711adfc5217SJeff Kirsher }; 1712adfc5217SJeff Kirsher 1713adfc5217SJeff Kirsher static const struct { 1714adfc5217SJeff Kirsher char *name; 1715adfc5217SJeff Kirsher u32 offset; 1716adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 1717adfc5217SJeff Kirsher } prty_tbl[] = { 1718adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 1719adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1720adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 1721adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 1722adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 1723adfc5217SJeff Kirsher {0, 0, 0, 0} }, 1724adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 1725adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1726adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 1727adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1728adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 1729adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 1730adfc5217SJeff Kirsher 1731adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 1732adfc5217SJeff Kirsher }; 1733adfc5217SJeff Kirsher 1734adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 1735adfc5217SJeff Kirsher return rc; 1736adfc5217SJeff Kirsher 1737adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1738adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 1739adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1740adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 1741adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1742adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 1743adfc5217SJeff Kirsher else /* e3 */ 1744adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 1745adfc5217SJeff Kirsher 1746adfc5217SJeff Kirsher /* pre-Check the parity status */ 1747adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1748adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 1749adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 1750adfc5217SJeff Kirsher DP(NETIF_MSG_HW, 1751adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 1752adfc5217SJeff Kirsher goto test_mem_exit; 1753adfc5217SJeff Kirsher } 1754adfc5217SJeff Kirsher } 1755adfc5217SJeff Kirsher 1756adfc5217SJeff Kirsher /* Go through all the memories */ 1757adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 1758adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 1759adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 1760adfc5217SJeff Kirsher 1761adfc5217SJeff Kirsher /* Check the parity status */ 1762adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1763adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 1764adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 1765adfc5217SJeff Kirsher DP(NETIF_MSG_HW, 1766adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 1767adfc5217SJeff Kirsher goto test_mem_exit; 1768adfc5217SJeff Kirsher } 1769adfc5217SJeff Kirsher } 1770adfc5217SJeff Kirsher 1771adfc5217SJeff Kirsher rc = 0; 1772adfc5217SJeff Kirsher 1773adfc5217SJeff Kirsher test_mem_exit: 1774adfc5217SJeff Kirsher return rc; 1775adfc5217SJeff Kirsher } 1776adfc5217SJeff Kirsher 1777adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 1778adfc5217SJeff Kirsher { 1779adfc5217SJeff Kirsher int cnt = 1400; 1780adfc5217SJeff Kirsher 1781adfc5217SJeff Kirsher if (link_up) { 1782adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 1783adfc5217SJeff Kirsher msleep(20); 1784adfc5217SJeff Kirsher 1785adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 1786adfc5217SJeff Kirsher DP(NETIF_MSG_LINK, "Timeout waiting for link up\n"); 1787adfc5217SJeff Kirsher } 1788adfc5217SJeff Kirsher } 1789adfc5217SJeff Kirsher 1790adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 1791adfc5217SJeff Kirsher { 1792adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 1793adfc5217SJeff Kirsher struct sk_buff *skb; 1794adfc5217SJeff Kirsher unsigned char *packet; 1795adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 1796adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 1797adfc5217SJeff Kirsher struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0]; 1798adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 1799adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 1800b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 1801adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 1802adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 1803adfc5217SJeff Kirsher struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; 1804adfc5217SJeff Kirsher struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; 1805adfc5217SJeff Kirsher dma_addr_t mapping; 1806adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 1807adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 1808adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 1809adfc5217SJeff Kirsher u16 len; 1810adfc5217SJeff Kirsher int rc = -ENODEV; 1811e52fcb24SEric Dumazet u8 *data; 181273dbb5e1SDmitry Kravkov struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txdata->txq_index); 1813adfc5217SJeff Kirsher 1814adfc5217SJeff Kirsher /* check the loopback mode */ 1815adfc5217SJeff Kirsher switch (loopback_mode) { 1816adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 1817adfc5217SJeff Kirsher if (bp->link_params.loopback_mode != LOOPBACK_XGXS) 1818adfc5217SJeff Kirsher return -EINVAL; 1819adfc5217SJeff Kirsher break; 1820adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 182132911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 182232911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 182332911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 182432911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 182532911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 182632911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 182732911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 182832911333SYaniv Rosner else 182932911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 183032911333SYaniv Rosner } else 183132911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 183232911333SYaniv Rosner 1833adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1834adfc5217SJeff Kirsher break; 1835adfc5217SJeff Kirsher default: 1836adfc5217SJeff Kirsher return -EINVAL; 1837adfc5217SJeff Kirsher } 1838adfc5217SJeff Kirsher 1839adfc5217SJeff Kirsher /* prepare the loopback packet */ 1840adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 1841adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 1842adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 1843adfc5217SJeff Kirsher if (!skb) { 1844adfc5217SJeff Kirsher rc = -ENOMEM; 1845adfc5217SJeff Kirsher goto test_loopback_exit; 1846adfc5217SJeff Kirsher } 1847adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 1848adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 1849adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 1850adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 1851adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 1852adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 1853adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 1854adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 1855adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 1856adfc5217SJeff Kirsher rc = -ENOMEM; 1857adfc5217SJeff Kirsher dev_kfree_skb(skb); 1858adfc5217SJeff Kirsher BNX2X_ERR("Unable to map SKB\n"); 1859adfc5217SJeff Kirsher goto test_loopback_exit; 1860adfc5217SJeff Kirsher } 1861adfc5217SJeff Kirsher 1862adfc5217SJeff Kirsher /* send the loopback packet */ 1863adfc5217SJeff Kirsher num_pkts = 0; 1864adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 1865adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 1866adfc5217SJeff Kirsher 186773dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 186873dbb5e1SDmitry Kravkov 1869adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 1870adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 1871adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 1872adfc5217SJeff Kirsher tx_buf->skb = skb; 1873adfc5217SJeff Kirsher tx_buf->flags = 0; 1874adfc5217SJeff Kirsher 1875adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 1876adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 1877adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 1878adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 1879adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 1880adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 1881adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 1882adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 1883adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 1884adfc5217SJeff Kirsher ETH_TX_START_BD_ETH_ADDR_TYPE, 1885adfc5217SJeff Kirsher UNICAST_ADDRESS); 1886adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 1887adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 1888adfc5217SJeff Kirsher 1); 1889adfc5217SJeff Kirsher 1890adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 1891adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 1892adfc5217SJeff Kirsher 1893adfc5217SJeff Kirsher pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 1894adfc5217SJeff Kirsher pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 1895adfc5217SJeff Kirsher 1896adfc5217SJeff Kirsher memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 1897adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 1898adfc5217SJeff Kirsher 1899adfc5217SJeff Kirsher wmb(); 1900adfc5217SJeff Kirsher 1901adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 1902adfc5217SJeff Kirsher barrier(); 1903adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 1904adfc5217SJeff Kirsher 1905adfc5217SJeff Kirsher mmiowb(); 1906adfc5217SJeff Kirsher barrier(); 1907adfc5217SJeff Kirsher 1908adfc5217SJeff Kirsher num_pkts++; 1909adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 1910adfc5217SJeff Kirsher 1911adfc5217SJeff Kirsher udelay(100); 1912adfc5217SJeff Kirsher 1913adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 1914adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 1915adfc5217SJeff Kirsher goto test_loopback_exit; 1916adfc5217SJeff Kirsher 1917adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 1918adfc5217SJeff Kirsher * updates that have been performed while interrupts were 1919adfc5217SJeff Kirsher * disabled. 1920adfc5217SJeff Kirsher */ 1921adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 1922adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 1923adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 1924adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 1925adfc5217SJeff Kirsher */ 1926adfc5217SJeff Kirsher local_bh_disable(); 1927adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 1928adfc5217SJeff Kirsher local_bh_enable(); 1929adfc5217SJeff Kirsher } 1930adfc5217SJeff Kirsher 1931adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 1932adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 1933adfc5217SJeff Kirsher goto test_loopback_exit; 1934adfc5217SJeff Kirsher 1935b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 1936adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 1937adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 1938adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 1939adfc5217SJeff Kirsher goto test_loopback_rx_exit; 1940adfc5217SJeff Kirsher 1941621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 1942adfc5217SJeff Kirsher if (len != pkt_size) 1943adfc5217SJeff Kirsher goto test_loopback_rx_exit; 1944adfc5217SJeff Kirsher 1945adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 1946adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 1947adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 1948adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 1949e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 1950adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 1951e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 1952adfc5217SJeff Kirsher goto test_loopback_rx_exit; 1953adfc5217SJeff Kirsher 1954adfc5217SJeff Kirsher rc = 0; 1955adfc5217SJeff Kirsher 1956adfc5217SJeff Kirsher test_loopback_rx_exit: 1957adfc5217SJeff Kirsher 1958adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 1959adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 1960adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 1961adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 1962adfc5217SJeff Kirsher 1963adfc5217SJeff Kirsher /* Update producers */ 1964adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 1965adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 1966adfc5217SJeff Kirsher 1967adfc5217SJeff Kirsher test_loopback_exit: 1968adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 1969adfc5217SJeff Kirsher 1970adfc5217SJeff Kirsher return rc; 1971adfc5217SJeff Kirsher } 1972adfc5217SJeff Kirsher 1973adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 1974adfc5217SJeff Kirsher { 1975adfc5217SJeff Kirsher int rc = 0, res; 1976adfc5217SJeff Kirsher 1977adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 1978adfc5217SJeff Kirsher return rc; 1979adfc5217SJeff Kirsher 1980adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 1981adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 1982adfc5217SJeff Kirsher 1983adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 1984adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1985adfc5217SJeff Kirsher 1986adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 1987adfc5217SJeff Kirsher if (res) { 1988adfc5217SJeff Kirsher DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res); 1989adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 1990adfc5217SJeff Kirsher } 1991adfc5217SJeff Kirsher 1992adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 1993adfc5217SJeff Kirsher if (res) { 1994adfc5217SJeff Kirsher DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res); 1995adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 1996adfc5217SJeff Kirsher } 1997adfc5217SJeff Kirsher 1998adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1999adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2000adfc5217SJeff Kirsher 2001adfc5217SJeff Kirsher return rc; 2002adfc5217SJeff Kirsher } 2003adfc5217SJeff Kirsher 2004adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2005adfc5217SJeff Kirsher 2006adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2007adfc5217SJeff Kirsher { 2008adfc5217SJeff Kirsher static const struct { 2009adfc5217SJeff Kirsher int offset; 2010adfc5217SJeff Kirsher int size; 2011adfc5217SJeff Kirsher } nvram_tbl[] = { 2012adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2013adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2014adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2015adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2016adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2017adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2018adfc5217SJeff Kirsher { 0, 0 } 2019adfc5217SJeff Kirsher }; 2020afa13b4bSMintz Yuval __be32 *buf; 2021afa13b4bSMintz Yuval u8 *data; 2022adfc5217SJeff Kirsher int i, rc; 2023adfc5217SJeff Kirsher u32 magic, crc; 2024adfc5217SJeff Kirsher 2025adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2026adfc5217SJeff Kirsher return 0; 2027adfc5217SJeff Kirsher 2028afa13b4bSMintz Yuval buf = kmalloc(0x350, GFP_KERNEL); 2029afa13b4bSMintz Yuval if (!buf) { 2030afa13b4bSMintz Yuval DP(NETIF_MSG_PROBE, "kmalloc failed\n"); 2031afa13b4bSMintz Yuval rc = -ENOMEM; 2032afa13b4bSMintz Yuval goto test_nvram_exit; 2033afa13b4bSMintz Yuval } 2034afa13b4bSMintz Yuval data = (u8 *)buf; 2035afa13b4bSMintz Yuval 2036adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, 0, data, 4); 2037adfc5217SJeff Kirsher if (rc) { 2038adfc5217SJeff Kirsher DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc); 2039adfc5217SJeff Kirsher goto test_nvram_exit; 2040adfc5217SJeff Kirsher } 2041adfc5217SJeff Kirsher 2042adfc5217SJeff Kirsher magic = be32_to_cpu(buf[0]); 2043adfc5217SJeff Kirsher if (magic != 0x669955aa) { 2044adfc5217SJeff Kirsher DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic); 2045adfc5217SJeff Kirsher rc = -ENODEV; 2046adfc5217SJeff Kirsher goto test_nvram_exit; 2047adfc5217SJeff Kirsher } 2048adfc5217SJeff Kirsher 2049adfc5217SJeff Kirsher for (i = 0; nvram_tbl[i].size; i++) { 2050adfc5217SJeff Kirsher 2051adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 2052adfc5217SJeff Kirsher nvram_tbl[i].size); 2053adfc5217SJeff Kirsher if (rc) { 2054adfc5217SJeff Kirsher DP(NETIF_MSG_PROBE, 2055adfc5217SJeff Kirsher "nvram_tbl[%d] read data (rc %d)\n", i, rc); 2056adfc5217SJeff Kirsher goto test_nvram_exit; 2057adfc5217SJeff Kirsher } 2058adfc5217SJeff Kirsher 2059adfc5217SJeff Kirsher crc = ether_crc_le(nvram_tbl[i].size, data); 2060adfc5217SJeff Kirsher if (crc != CRC32_RESIDUAL) { 2061adfc5217SJeff Kirsher DP(NETIF_MSG_PROBE, 2062adfc5217SJeff Kirsher "nvram_tbl[%d] crc value (0x%08x)\n", i, crc); 2063adfc5217SJeff Kirsher rc = -ENODEV; 2064adfc5217SJeff Kirsher goto test_nvram_exit; 2065adfc5217SJeff Kirsher } 2066adfc5217SJeff Kirsher } 2067adfc5217SJeff Kirsher 2068adfc5217SJeff Kirsher test_nvram_exit: 2069afa13b4bSMintz Yuval kfree(buf); 2070adfc5217SJeff Kirsher return rc; 2071adfc5217SJeff Kirsher } 2072adfc5217SJeff Kirsher 2073adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2074adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2075adfc5217SJeff Kirsher { 2076adfc5217SJeff Kirsher struct bnx2x_queue_state_params params = {0}; 2077adfc5217SJeff Kirsher 2078adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2079adfc5217SJeff Kirsher return -ENODEV; 2080adfc5217SJeff Kirsher 2081adfc5217SJeff Kirsher params.q_obj = &bp->fp->q_obj; 2082adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2083adfc5217SJeff Kirsher 2084adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2085adfc5217SJeff Kirsher 2086adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2087adfc5217SJeff Kirsher } 2088adfc5217SJeff Kirsher 2089adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2090adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2091adfc5217SJeff Kirsher { 2092adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2093adfc5217SJeff Kirsher u8 is_serdes; 2094adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 20957a752993SAriel Elior netdev_err(bp->dev, "Handling parity error recovery. " 20967a752993SAriel Elior "Try again later\n"); 2097adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2098adfc5217SJeff Kirsher return; 2099adfc5217SJeff Kirsher } 2100adfc5217SJeff Kirsher 2101adfc5217SJeff Kirsher memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS); 2102adfc5217SJeff Kirsher 2103adfc5217SJeff Kirsher if (!netif_running(dev)) 2104adfc5217SJeff Kirsher return; 2105adfc5217SJeff Kirsher 2106adfc5217SJeff Kirsher /* offline tests are not supported in MF mode */ 2107adfc5217SJeff Kirsher if (IS_MF(bp)) 2108adfc5217SJeff Kirsher etest->flags &= ~ETH_TEST_FL_OFFLINE; 2109adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2110adfc5217SJeff Kirsher 2111adfc5217SJeff Kirsher if (etest->flags & ETH_TEST_FL_OFFLINE) { 2112adfc5217SJeff Kirsher int port = BP_PORT(bp); 2113adfc5217SJeff Kirsher u32 val; 2114adfc5217SJeff Kirsher u8 link_up; 2115adfc5217SJeff Kirsher 2116adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2117adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2118adfc5217SJeff Kirsher /* disable input for TX port IF */ 2119adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2120adfc5217SJeff Kirsher 2121adfc5217SJeff Kirsher link_up = bp->link_vars.link_up; 2122adfc5217SJeff Kirsher 2123adfc5217SJeff Kirsher bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2124adfc5217SJeff Kirsher bnx2x_nic_load(bp, LOAD_DIAG); 2125adfc5217SJeff Kirsher /* wait until link state is restored */ 2126adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2127adfc5217SJeff Kirsher 2128adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2129adfc5217SJeff Kirsher buf[0] = 1; 2130adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2131adfc5217SJeff Kirsher } 2132adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2133adfc5217SJeff Kirsher buf[1] = 1; 2134adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2135adfc5217SJeff Kirsher } 2136adfc5217SJeff Kirsher 2137adfc5217SJeff Kirsher buf[2] = bnx2x_test_loopback(bp); 2138adfc5217SJeff Kirsher if (buf[2] != 0) 2139adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2140adfc5217SJeff Kirsher 2141adfc5217SJeff Kirsher bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2142adfc5217SJeff Kirsher 2143adfc5217SJeff Kirsher /* restore input for TX port IF */ 2144adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2145adfc5217SJeff Kirsher 2146adfc5217SJeff Kirsher bnx2x_nic_load(bp, LOAD_NORMAL); 2147adfc5217SJeff Kirsher /* wait until link state is restored */ 2148adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2149adfc5217SJeff Kirsher } 2150adfc5217SJeff Kirsher if (bnx2x_test_nvram(bp) != 0) { 2151adfc5217SJeff Kirsher buf[3] = 1; 2152adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2153adfc5217SJeff Kirsher } 2154adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2155adfc5217SJeff Kirsher buf[4] = 1; 2156adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2157adfc5217SJeff Kirsher } 2158adfc5217SJeff Kirsher 2159adfc5217SJeff Kirsher if (bnx2x_link_test(bp, is_serdes) != 0) { 2160adfc5217SJeff Kirsher buf[5] = 1; 2161adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2162adfc5217SJeff Kirsher } 2163adfc5217SJeff Kirsher 2164adfc5217SJeff Kirsher #ifdef BNX2X_EXTRA_DEBUG 2165adfc5217SJeff Kirsher bnx2x_panic_dump(bp); 2166adfc5217SJeff Kirsher #endif 2167adfc5217SJeff Kirsher } 2168adfc5217SJeff Kirsher 2169adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 2170adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2171adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2172adfc5217SJeff Kirsher #define IS_MF_MODE_STAT(bp) \ 2173adfc5217SJeff Kirsher (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2174adfc5217SJeff Kirsher 2175adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 2176adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 2177adfc5217SJeff Kirsher */ 2178adfc5217SJeff Kirsher static inline int bnx2x_num_stat_queues(struct bnx2x *bp) 2179adfc5217SJeff Kirsher { 2180adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 2181adfc5217SJeff Kirsher } 2182adfc5217SJeff Kirsher 2183adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2184adfc5217SJeff Kirsher { 2185adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2186adfc5217SJeff Kirsher int i, num_stats; 2187adfc5217SJeff Kirsher 2188adfc5217SJeff Kirsher switch (stringset) { 2189adfc5217SJeff Kirsher case ETH_SS_STATS: 2190adfc5217SJeff Kirsher if (is_multi(bp)) { 2191adfc5217SJeff Kirsher num_stats = bnx2x_num_stat_queues(bp) * 2192adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 2193d5e83632SYuval Mintz } else 2194adfc5217SJeff Kirsher num_stats = 0; 2195d5e83632SYuval Mintz if (IS_MF_MODE_STAT(bp)) { 2196adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 2197adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 2198adfc5217SJeff Kirsher num_stats++; 2199adfc5217SJeff Kirsher } else 2200d5e83632SYuval Mintz num_stats += BNX2X_NUM_STATS; 2201d5e83632SYuval Mintz 2202adfc5217SJeff Kirsher return num_stats; 2203adfc5217SJeff Kirsher 2204adfc5217SJeff Kirsher case ETH_SS_TEST: 2205adfc5217SJeff Kirsher return BNX2X_NUM_TESTS; 2206adfc5217SJeff Kirsher 2207adfc5217SJeff Kirsher default: 2208adfc5217SJeff Kirsher return -EINVAL; 2209adfc5217SJeff Kirsher } 2210adfc5217SJeff Kirsher } 2211adfc5217SJeff Kirsher 2212adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 2213adfc5217SJeff Kirsher { 2214adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2215adfc5217SJeff Kirsher int i, j, k; 2216adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 2217adfc5217SJeff Kirsher 2218adfc5217SJeff Kirsher switch (stringset) { 2219adfc5217SJeff Kirsher case ETH_SS_STATS: 2220adfc5217SJeff Kirsher k = 0; 2221d5e83632SYuval Mintz if (is_multi(bp)) { 2222adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 2223adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 2224adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 2225adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 2226adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 2227adfc5217SJeff Kirsher ETH_GSTRING_LEN, 2228adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 2229adfc5217SJeff Kirsher queue_name); 2230adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2231adfc5217SJeff Kirsher } 2232d5e83632SYuval Mintz } 2233d5e83632SYuval Mintz 2234d5e83632SYuval Mintz 2235adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2236adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2237adfc5217SJeff Kirsher continue; 2238d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 2239adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 2240adfc5217SJeff Kirsher j++; 2241adfc5217SJeff Kirsher } 2242d5e83632SYuval Mintz 2243adfc5217SJeff Kirsher break; 2244adfc5217SJeff Kirsher 2245adfc5217SJeff Kirsher case ETH_SS_TEST: 2246adfc5217SJeff Kirsher memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr)); 2247adfc5217SJeff Kirsher break; 2248adfc5217SJeff Kirsher } 2249adfc5217SJeff Kirsher } 2250adfc5217SJeff Kirsher 2251adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 2252adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 2253adfc5217SJeff Kirsher { 2254adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2255adfc5217SJeff Kirsher u32 *hw_stats, *offset; 2256d5e83632SYuval Mintz int i, j, k = 0; 2257adfc5217SJeff Kirsher 2258adfc5217SJeff Kirsher if (is_multi(bp)) { 2259adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 2260adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->fp[i].eth_q_stats; 2261adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 2262adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 2263adfc5217SJeff Kirsher /* skip this counter */ 2264adfc5217SJeff Kirsher buf[k + j] = 0; 2265adfc5217SJeff Kirsher continue; 2266adfc5217SJeff Kirsher } 2267adfc5217SJeff Kirsher offset = (hw_stats + 2268adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 2269adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 2270adfc5217SJeff Kirsher /* 4-byte counter */ 2271adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 2272adfc5217SJeff Kirsher continue; 2273adfc5217SJeff Kirsher } 2274adfc5217SJeff Kirsher /* 8-byte counter */ 2275adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2276adfc5217SJeff Kirsher } 2277adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2278adfc5217SJeff Kirsher } 2279adfc5217SJeff Kirsher } 2280d5e83632SYuval Mintz 2281adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 2282adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2283adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2284adfc5217SJeff Kirsher continue; 2285adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 2286adfc5217SJeff Kirsher /* skip this counter */ 2287d5e83632SYuval Mintz buf[k + j] = 0; 2288adfc5217SJeff Kirsher j++; 2289adfc5217SJeff Kirsher continue; 2290adfc5217SJeff Kirsher } 2291adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 2292adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 2293adfc5217SJeff Kirsher /* 4-byte counter */ 2294d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 2295adfc5217SJeff Kirsher j++; 2296adfc5217SJeff Kirsher continue; 2297adfc5217SJeff Kirsher } 2298adfc5217SJeff Kirsher /* 8-byte counter */ 2299d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2300adfc5217SJeff Kirsher j++; 2301adfc5217SJeff Kirsher } 2302adfc5217SJeff Kirsher } 2303adfc5217SJeff Kirsher 2304adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 2305adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 2306adfc5217SJeff Kirsher { 2307adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2308adfc5217SJeff Kirsher 2309adfc5217SJeff Kirsher if (!netif_running(dev)) 2310adfc5217SJeff Kirsher return -EAGAIN; 2311adfc5217SJeff Kirsher 2312adfc5217SJeff Kirsher if (!bp->port.pmf) 2313adfc5217SJeff Kirsher return -EOPNOTSUPP; 2314adfc5217SJeff Kirsher 2315adfc5217SJeff Kirsher switch (state) { 2316adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 2317adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 2318adfc5217SJeff Kirsher 2319adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 2320adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2321adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 2322adfc5217SJeff Kirsher break; 2323adfc5217SJeff Kirsher 2324adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 2325adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2326adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 2327adfc5217SJeff Kirsher 2328adfc5217SJeff Kirsher break; 2329adfc5217SJeff Kirsher 2330adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 2331adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2332adfc5217SJeff Kirsher LED_MODE_OPER, 2333adfc5217SJeff Kirsher bp->link_vars.line_speed); 2334adfc5217SJeff Kirsher } 2335adfc5217SJeff Kirsher 2336adfc5217SJeff Kirsher return 0; 2337adfc5217SJeff Kirsher } 2338adfc5217SJeff Kirsher 2339adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2340815c7db5SBen Hutchings u32 *rules __always_unused) 2341adfc5217SJeff Kirsher { 2342adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2343adfc5217SJeff Kirsher 2344adfc5217SJeff Kirsher switch (info->cmd) { 2345adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 2346adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 2347adfc5217SJeff Kirsher return 0; 2348adfc5217SJeff Kirsher 2349adfc5217SJeff Kirsher default: 2350adfc5217SJeff Kirsher return -EOPNOTSUPP; 2351adfc5217SJeff Kirsher } 2352adfc5217SJeff Kirsher } 2353adfc5217SJeff Kirsher 23547850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 2355adfc5217SJeff Kirsher { 2356adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 23577850f63fSBen Hutchings 23587850f63fSBen Hutchings return (bp->multi_mode == ETH_RSS_MODE_DISABLED ? 23597850f63fSBen Hutchings 0 : T_ETH_INDIRECTION_TABLE_SIZE); 23607850f63fSBen Hutchings } 23617850f63fSBen Hutchings 23627850f63fSBen Hutchings static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 23637850f63fSBen Hutchings { 23647850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 2365adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2366adfc5217SJeff Kirsher size_t i; 2367adfc5217SJeff Kirsher 2368adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 2369adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 2370adfc5217SJeff Kirsher 2371adfc5217SJeff Kirsher /* 2372adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 2373adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 2374adfc5217SJeff Kirsher * points to an array of u32. 2375adfc5217SJeff Kirsher * 2376adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2377adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 2378adfc5217SJeff Kirsher * queue. 2379adfc5217SJeff Kirsher */ 23807850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 23817850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 2382adfc5217SJeff Kirsher 2383adfc5217SJeff Kirsher return 0; 2384adfc5217SJeff Kirsher } 2385adfc5217SJeff Kirsher 23867850f63fSBen Hutchings static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 2387adfc5217SJeff Kirsher { 2388adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2389adfc5217SJeff Kirsher size_t i; 2390adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2391adfc5217SJeff Kirsher 2392adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2393adfc5217SJeff Kirsher /* 2394adfc5217SJeff Kirsher * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 2395adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 2396adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 2397adfc5217SJeff Kirsher * 2398adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2399adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 2400adfc5217SJeff Kirsher * queue 2401adfc5217SJeff Kirsher */ 24027850f63fSBen Hutchings ind_table[i] = indir[i] + bp->fp->cl_id; 2403adfc5217SJeff Kirsher } 2404adfc5217SJeff Kirsher 2405adfc5217SJeff Kirsher return bnx2x_config_rss_pf(bp, ind_table, false); 2406adfc5217SJeff Kirsher } 2407adfc5217SJeff Kirsher 2408adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 2409adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 2410adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 2411adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 2412adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 2413adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 2414adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 2415adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 2416adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 2417adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 2418adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 2419adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 2420adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 2421adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 2422adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 2423adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 2424adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 2425adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 2426adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 2427adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 2428adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 2429adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 2430adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 2431adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 2432adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 2433adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 2434adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 24357850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 2436adfc5217SJeff Kirsher .get_rxfh_indir = bnx2x_get_rxfh_indir, 2437adfc5217SJeff Kirsher .set_rxfh_indir = bnx2x_set_rxfh_indir, 2438adfc5217SJeff Kirsher }; 2439adfc5217SJeff Kirsher 2440adfc5217SJeff Kirsher void bnx2x_set_ethtool_ops(struct net_device *netdev) 2441adfc5217SJeff Kirsher { 2442adfc5217SJeff Kirsher SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 2443adfc5217SJeff Kirsher } 2444