1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 385b26ea1SAriel Elior * Copyright (c) 2007-2012 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher #include "bnx2x.h" 26adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 27adfc5217SJeff Kirsher #include "bnx2x_dump.h" 28adfc5217SJeff Kirsher #include "bnx2x_init.h" 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 31adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33adfc5217SJeff Kirsher */ 34adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 35adfc5217SJeff Kirsher static const struct { 36adfc5217SJeff Kirsher long offset; 37adfc5217SJeff Kirsher int size; 38adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 39adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 40adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 49adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53adfc5217SJeff Kirsher 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 65c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 68adfc5217SJeff Kirsher }; 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher static const struct { 73adfc5217SJeff Kirsher long offset; 74adfc5217SJeff Kirsher int size; 75adfc5217SJeff Kirsher u32 flags; 76adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 77adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 78adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 80adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 81adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 101adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 104adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 106adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 108adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1090e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1100e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1110e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1120e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 114adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 122adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 128adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129adfc5217SJeff Kirsher 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 131adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1777a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1797a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1817a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 183c96bdc0cSDmitry Kravkov 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 185e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 189adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 190adfc5217SJeff Kirsher { 191adfc5217SJeff Kirsher int port_type; 192adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 193adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 194dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 195dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 196adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_KR: 198adfc5217SJeff Kirsher case ETH_PHY_CX4: 199adfc5217SJeff Kirsher port_type = PORT_FIBRE; 200adfc5217SJeff Kirsher break; 201adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 202adfc5217SJeff Kirsher port_type = PORT_DA; 203adfc5217SJeff Kirsher break; 204adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 205adfc5217SJeff Kirsher port_type = PORT_TP; 206adfc5217SJeff Kirsher break; 207adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 208adfc5217SJeff Kirsher port_type = PORT_NONE; 209adfc5217SJeff Kirsher break; 210adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 211adfc5217SJeff Kirsher default: 212adfc5217SJeff Kirsher port_type = PORT_OTHER; 213adfc5217SJeff Kirsher break; 214adfc5217SJeff Kirsher } 215adfc5217SJeff Kirsher return port_type; 216adfc5217SJeff Kirsher } 217adfc5217SJeff Kirsher 218adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 219adfc5217SJeff Kirsher { 220adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 221adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 222adfc5217SJeff Kirsher 223adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 224adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 225adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 226adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 227adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 228dbef807eSYuval Mintz if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 229dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER) { 230dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 231dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 232dbef807eSYuval Mintz } 233adfc5217SJeff Kirsher 23459694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 23559694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 236adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 237adfc5217SJeff Kirsher 23838298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 239adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 24059694f00SYuval Mintz else 24159694f00SYuval Mintz ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 24238298461SYuval Mintz } else { 24338298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 24438298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 24538298461SYuval Mintz } 246adfc5217SJeff Kirsher 247adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 248adfc5217SJeff Kirsher 249adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 250adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 251adfc5217SJeff Kirsher 252adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 253adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 254adfc5217SJeff Kirsher else 255adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 256adfc5217SJeff Kirsher 2579e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2589e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2599e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2609e7e8399SMintz Yuval 2619e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 2629e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 2639e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 2649e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 2659e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 2669e7e8399SMintz Yuval 2679e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 2689e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 2699e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 2709e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 2719e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 2729e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 2739e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 2749e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 2759e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 2769e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 2779e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 2789e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 2799e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 2809e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 2819e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 2829e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 2839e7e8399SMintz Yuval } 2849e7e8399SMintz Yuval 285adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 286adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 287adfc5217SJeff Kirsher 28851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 289f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 290f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 291f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 292adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 293adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 294adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 295adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 296adfc5217SJeff Kirsher 297adfc5217SJeff Kirsher return 0; 298adfc5217SJeff Kirsher } 299adfc5217SJeff Kirsher 300adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 301adfc5217SJeff Kirsher { 302adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 303adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 304dbef807eSYuval Mintz u32 speed, phy_idx; 305adfc5217SJeff Kirsher 306adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 307adfc5217SJeff Kirsher return 0; 308adfc5217SJeff Kirsher 30951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 310adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 311adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 312adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 313adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 314adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 315adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 316adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 317adfc5217SJeff Kirsher 318adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 319adfc5217SJeff Kirsher 32038298461SYuval Mintz /* If recieved a request for an unknown duplex, assume full*/ 32138298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 32238298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 32338298461SYuval Mintz 324adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 325adfc5217SJeff Kirsher u32 part; 326adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 327adfc5217SJeff Kirsher 328adfc5217SJeff Kirsher /* use 10G if no link detected */ 329adfc5217SJeff Kirsher if (!line_speed) 330adfc5217SJeff Kirsher line_speed = 10000; 331adfc5217SJeff Kirsher 332adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 33351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33451c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 335adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 336adfc5217SJeff Kirsher return -EINVAL; 337adfc5217SJeff Kirsher } 338adfc5217SJeff Kirsher 339adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 340adfc5217SJeff Kirsher 341adfc5217SJeff Kirsher if (line_speed < speed || !part) { 34251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34351c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 344adfc5217SJeff Kirsher return -EINVAL; 345adfc5217SJeff Kirsher } 346adfc5217SJeff Kirsher 347adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 348adfc5217SJeff Kirsher /* store value for following "load" */ 349adfc5217SJeff Kirsher bp->pending_max = part; 350adfc5217SJeff Kirsher else 351adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 352adfc5217SJeff Kirsher 353adfc5217SJeff Kirsher return 0; 354adfc5217SJeff Kirsher } 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 357adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 358adfc5217SJeff Kirsher switch (cmd->port) { 359adfc5217SJeff Kirsher case PORT_TP: 360adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 361adfc5217SJeff Kirsher break; /* no port change */ 362adfc5217SJeff Kirsher 363adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 364adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 36551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 366adfc5217SJeff Kirsher return -EINVAL; 367adfc5217SJeff Kirsher } 368adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 369adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 370adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 371adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 372adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 373adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 374adfc5217SJeff Kirsher else 375adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 376adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 377adfc5217SJeff Kirsher break; 378adfc5217SJeff Kirsher case PORT_FIBRE: 379bfdb5823SYaniv Rosner case PORT_DA: 380adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 381adfc5217SJeff Kirsher break; /* no port change */ 382adfc5217SJeff Kirsher 383adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 384adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 38551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 386adfc5217SJeff Kirsher return -EINVAL; 387adfc5217SJeff Kirsher } 388adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 389adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 390adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 391adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 392adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 393adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 394adfc5217SJeff Kirsher else 395adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 396adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 397adfc5217SJeff Kirsher break; 398adfc5217SJeff Kirsher default: 39951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 400adfc5217SJeff Kirsher return -EINVAL; 401adfc5217SJeff Kirsher } 4022f751a80SYaniv Rosner /* Save new config in case command complete successully */ 403adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 404adfc5217SJeff Kirsher /* Get the new cfg_idx */ 405adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 406adfc5217SJeff Kirsher /* Restore old config in case command failed */ 407adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 40851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 409adfc5217SJeff Kirsher 410adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 41175318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 41275318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 41375318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 41475318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 41575318327SYaniv Rosner SUPPORTED_100baseT_Full); 416adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 41751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 418adfc5217SJeff Kirsher return -EINVAL; 419adfc5217SJeff Kirsher } 420adfc5217SJeff Kirsher 421adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 42275318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 42351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 42451c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4258decf868SDavid S. Miller return -EINVAL; 4268decf868SDavid S. Miller } 427adfc5217SJeff Kirsher 428adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4298decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4308decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 431adfc5217SJeff Kirsher cmd->advertising); 4328decf868SDavid S. Miller if (cmd->advertising) { 433adfc5217SJeff Kirsher 4348decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4358decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4368decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4378decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4388decf868SDavid S. Miller } 4398decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4408decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4418decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4428decf868SDavid S. Miller 4438decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4448decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4458decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4468decf868SDavid S. Miller 4478decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4488decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4498decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4508decf868SDavid S. Miller } 4518decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4528decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4538decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4548decf868SDavid S. Miller } 4558decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4568decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4578decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4588decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4598decf868SDavid S. Miller 4608decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4618decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 4628decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 4638decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4648decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 4658decf868SDavid S. Miller } 466adfc5217SJeff Kirsher } else { /* forced speed */ 467adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 468adfc5217SJeff Kirsher switch (speed) { 469adfc5217SJeff Kirsher case SPEED_10: 470adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 471adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 472adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 47351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 474adfc5217SJeff Kirsher "10M full not supported\n"); 475adfc5217SJeff Kirsher return -EINVAL; 476adfc5217SJeff Kirsher } 477adfc5217SJeff Kirsher 478adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 479adfc5217SJeff Kirsher ADVERTISED_TP); 480adfc5217SJeff Kirsher } else { 481adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 482adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 48351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 484adfc5217SJeff Kirsher "10M half not supported\n"); 485adfc5217SJeff Kirsher return -EINVAL; 486adfc5217SJeff Kirsher } 487adfc5217SJeff Kirsher 488adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 489adfc5217SJeff Kirsher ADVERTISED_TP); 490adfc5217SJeff Kirsher } 491adfc5217SJeff Kirsher break; 492adfc5217SJeff Kirsher 493adfc5217SJeff Kirsher case SPEED_100: 494adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 495adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 496adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 49751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 498adfc5217SJeff Kirsher "100M full not supported\n"); 499adfc5217SJeff Kirsher return -EINVAL; 500adfc5217SJeff Kirsher } 501adfc5217SJeff Kirsher 502adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 503adfc5217SJeff Kirsher ADVERTISED_TP); 504adfc5217SJeff Kirsher } else { 505adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 506adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 50751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 508adfc5217SJeff Kirsher "100M half not supported\n"); 509adfc5217SJeff Kirsher return -EINVAL; 510adfc5217SJeff Kirsher } 511adfc5217SJeff Kirsher 512adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 513adfc5217SJeff Kirsher ADVERTISED_TP); 514adfc5217SJeff Kirsher } 515adfc5217SJeff Kirsher break; 516adfc5217SJeff Kirsher 517adfc5217SJeff Kirsher case SPEED_1000: 518adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 51951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52051c1a580SMerav Sicron "1G half not supported\n"); 521adfc5217SJeff Kirsher return -EINVAL; 522adfc5217SJeff Kirsher } 523adfc5217SJeff Kirsher 524adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 525adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 52651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52751c1a580SMerav Sicron "1G full not supported\n"); 528adfc5217SJeff Kirsher return -EINVAL; 529adfc5217SJeff Kirsher } 530adfc5217SJeff Kirsher 531adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 532adfc5217SJeff Kirsher ADVERTISED_TP); 533adfc5217SJeff Kirsher break; 534adfc5217SJeff Kirsher 535adfc5217SJeff Kirsher case SPEED_2500: 536adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 53751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 538adfc5217SJeff Kirsher "2.5G half not supported\n"); 539adfc5217SJeff Kirsher return -EINVAL; 540adfc5217SJeff Kirsher } 541adfc5217SJeff Kirsher 542adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 543adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 54451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 545adfc5217SJeff Kirsher "2.5G full not supported\n"); 546adfc5217SJeff Kirsher return -EINVAL; 547adfc5217SJeff Kirsher } 548adfc5217SJeff Kirsher 549adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 550adfc5217SJeff Kirsher ADVERTISED_TP); 551adfc5217SJeff Kirsher break; 552adfc5217SJeff Kirsher 553adfc5217SJeff Kirsher case SPEED_10000: 554adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 55551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 55651c1a580SMerav Sicron "10G half not supported\n"); 557adfc5217SJeff Kirsher return -EINVAL; 558adfc5217SJeff Kirsher } 559dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 560adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 561dbef807eSYuval Mintz & SUPPORTED_10000baseT_Full) || 562dbef807eSYuval Mintz (bp->link_params.phy[phy_idx].media_type == 563dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 56451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56551c1a580SMerav Sicron "10G full not supported\n"); 566adfc5217SJeff Kirsher return -EINVAL; 567adfc5217SJeff Kirsher } 568adfc5217SJeff Kirsher 569adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 570adfc5217SJeff Kirsher ADVERTISED_FIBRE); 571adfc5217SJeff Kirsher break; 572adfc5217SJeff Kirsher 573adfc5217SJeff Kirsher default: 57451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 575adfc5217SJeff Kirsher return -EINVAL; 576adfc5217SJeff Kirsher } 577adfc5217SJeff Kirsher 578adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 579adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 580adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 581adfc5217SJeff Kirsher } 582adfc5217SJeff Kirsher 58351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 584f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 585adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 586adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 587adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 588adfc5217SJeff Kirsher 589adfc5217SJeff Kirsher /* Set new config */ 590adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 591adfc5217SJeff Kirsher if (netif_running(dev)) { 592adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 593adfc5217SJeff Kirsher bnx2x_link_set(bp); 594adfc5217SJeff Kirsher } 595adfc5217SJeff Kirsher 596adfc5217SJeff Kirsher return 0; 597adfc5217SJeff Kirsher } 598adfc5217SJeff Kirsher 599adfc5217SJeff Kirsher #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) 600adfc5217SJeff Kirsher #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) 601adfc5217SJeff Kirsher #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) 602adfc5217SJeff Kirsher #define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE) 603adfc5217SJeff Kirsher #define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE) 604adfc5217SJeff Kirsher 6051191cb83SEric Dumazet static bool bnx2x_is_reg_online(struct bnx2x *bp, 606adfc5217SJeff Kirsher const struct reg_addr *reg_info) 607adfc5217SJeff Kirsher { 608adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 609adfc5217SJeff Kirsher return IS_E1_ONLINE(reg_info->info); 610adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 611adfc5217SJeff Kirsher return IS_E1H_ONLINE(reg_info->info); 612adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 613adfc5217SJeff Kirsher return IS_E2_ONLINE(reg_info->info); 614adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 615adfc5217SJeff Kirsher return IS_E3_ONLINE(reg_info->info); 616adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 617adfc5217SJeff Kirsher return IS_E3B0_ONLINE(reg_info->info); 618adfc5217SJeff Kirsher else 619adfc5217SJeff Kirsher return false; 620adfc5217SJeff Kirsher } 621adfc5217SJeff Kirsher 622adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 6231191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 624adfc5217SJeff Kirsher { 625adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 626adfc5217SJeff Kirsher return page_vals_e2; 627adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 628adfc5217SJeff Kirsher return page_vals_e3; 629adfc5217SJeff Kirsher else 630adfc5217SJeff Kirsher return NULL; 631adfc5217SJeff Kirsher } 632adfc5217SJeff Kirsher 6331191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 634adfc5217SJeff Kirsher { 635adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 636adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 637adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 638adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 639adfc5217SJeff Kirsher else 640adfc5217SJeff Kirsher return 0; 641adfc5217SJeff Kirsher } 642adfc5217SJeff Kirsher 6431191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 644adfc5217SJeff Kirsher { 645adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 646adfc5217SJeff Kirsher return page_write_regs_e2; 647adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 648adfc5217SJeff Kirsher return page_write_regs_e3; 649adfc5217SJeff Kirsher else 650adfc5217SJeff Kirsher return NULL; 651adfc5217SJeff Kirsher } 652adfc5217SJeff Kirsher 6531191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 654adfc5217SJeff Kirsher { 655adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 656adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 657adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 658adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 659adfc5217SJeff Kirsher else 660adfc5217SJeff Kirsher return 0; 661adfc5217SJeff Kirsher } 662adfc5217SJeff Kirsher 6631191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 664adfc5217SJeff Kirsher { 665adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 666adfc5217SJeff Kirsher return page_read_regs_e2; 667adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 668adfc5217SJeff Kirsher return page_read_regs_e3; 669adfc5217SJeff Kirsher else 670adfc5217SJeff Kirsher return NULL; 671adfc5217SJeff Kirsher } 672adfc5217SJeff Kirsher 6731191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 674adfc5217SJeff Kirsher { 675adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 676adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 677adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 678adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 679adfc5217SJeff Kirsher else 680adfc5217SJeff Kirsher return 0; 681adfc5217SJeff Kirsher } 682adfc5217SJeff Kirsher 6831191cb83SEric Dumazet static int __bnx2x_get_regs_len(struct bnx2x *bp) 684adfc5217SJeff Kirsher { 685adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 686adfc5217SJeff Kirsher int page_write_num = __bnx2x_get_page_write_num(bp); 687adfc5217SJeff Kirsher const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp); 688adfc5217SJeff Kirsher int page_read_num = __bnx2x_get_page_read_num(bp); 689adfc5217SJeff Kirsher int regdump_len = 0; 690adfc5217SJeff Kirsher int i, j, k; 691adfc5217SJeff Kirsher 692adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 693adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 694adfc5217SJeff Kirsher regdump_len += reg_addrs[i].size; 695adfc5217SJeff Kirsher 696adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) 697adfc5217SJeff Kirsher for (j = 0; j < page_write_num; j++) 698adfc5217SJeff Kirsher for (k = 0; k < page_read_num; k++) 699adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &page_read_addr[k])) 700adfc5217SJeff Kirsher regdump_len += page_read_addr[k].size; 701adfc5217SJeff Kirsher 702adfc5217SJeff Kirsher return regdump_len; 703adfc5217SJeff Kirsher } 704adfc5217SJeff Kirsher 705adfc5217SJeff Kirsher static int bnx2x_get_regs_len(struct net_device *dev) 706adfc5217SJeff Kirsher { 707adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 708adfc5217SJeff Kirsher int regdump_len = 0; 709adfc5217SJeff Kirsher 710adfc5217SJeff Kirsher regdump_len = __bnx2x_get_regs_len(bp); 711adfc5217SJeff Kirsher regdump_len *= 4; 712adfc5217SJeff Kirsher regdump_len += sizeof(struct dump_hdr); 713adfc5217SJeff Kirsher 714adfc5217SJeff Kirsher return regdump_len; 715adfc5217SJeff Kirsher } 716adfc5217SJeff Kirsher 717adfc5217SJeff Kirsher /** 718adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 719adfc5217SJeff Kirsher * 720adfc5217SJeff Kirsher * @bp device handle 721adfc5217SJeff Kirsher * @p output buffer 722adfc5217SJeff Kirsher * 723adfc5217SJeff Kirsher * Reads "paged" memories: memories that may only be read by first writing to a 724adfc5217SJeff Kirsher * specific address ("write address") and then reading from a specific address 725adfc5217SJeff Kirsher * ("read address"). There may be more than one write address per "page" and 726adfc5217SJeff Kirsher * more than one read address per write address. 727adfc5217SJeff Kirsher */ 7281191cb83SEric Dumazet static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p) 729adfc5217SJeff Kirsher { 730adfc5217SJeff Kirsher u32 i, j, k, n; 731adfc5217SJeff Kirsher /* addresses of the paged registers */ 732adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 733adfc5217SJeff Kirsher /* number of paged registers */ 734adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 735adfc5217SJeff Kirsher /* write addresses */ 736adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 737adfc5217SJeff Kirsher /* number of write addresses */ 738adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 739adfc5217SJeff Kirsher /* read addresses info */ 740adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 741adfc5217SJeff Kirsher /* number of read addresses */ 742adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 743adfc5217SJeff Kirsher 744adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 745adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 746adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 747adfc5217SJeff Kirsher for (k = 0; k < read_num; k++) 748adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, &read_addr[k])) 749adfc5217SJeff Kirsher for (n = 0; n < 750adfc5217SJeff Kirsher read_addr[k].size; n++) 751adfc5217SJeff Kirsher *p++ = REG_RD(bp, 752adfc5217SJeff Kirsher read_addr[k].addr + n*4); 753adfc5217SJeff Kirsher } 754adfc5217SJeff Kirsher } 755adfc5217SJeff Kirsher } 756adfc5217SJeff Kirsher 7571191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 758adfc5217SJeff Kirsher { 759adfc5217SJeff Kirsher u32 i, j; 760adfc5217SJeff Kirsher 761adfc5217SJeff Kirsher /* Read the regular registers */ 762adfc5217SJeff Kirsher for (i = 0; i < REGS_COUNT; i++) 763adfc5217SJeff Kirsher if (bnx2x_is_reg_online(bp, ®_addrs[i])) 764adfc5217SJeff Kirsher for (j = 0; j < reg_addrs[i].size; j++) 765adfc5217SJeff Kirsher *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 766adfc5217SJeff Kirsher 767adfc5217SJeff Kirsher /* Read "paged" registes */ 768adfc5217SJeff Kirsher bnx2x_read_pages_regs(bp, p); 769adfc5217SJeff Kirsher } 770adfc5217SJeff Kirsher 771adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 772adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 773adfc5217SJeff Kirsher { 774adfc5217SJeff Kirsher u32 *p = _p; 775adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 776adfc5217SJeff Kirsher struct dump_hdr dump_hdr = {0}; 777adfc5217SJeff Kirsher 7782ace9510SDmitry Kravkov regs->version = 1; 779adfc5217SJeff Kirsher memset(p, 0, regs->len); 780adfc5217SJeff Kirsher 781adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 782adfc5217SJeff Kirsher return; 783adfc5217SJeff Kirsher 784adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 785adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 786adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 787adfc5217SJeff Kirsher */ 788adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 789adfc5217SJeff Kirsher 790adfc5217SJeff Kirsher dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; 791adfc5217SJeff Kirsher dump_hdr.dump_sign = dump_sign_all; 792adfc5217SJeff Kirsher dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); 793adfc5217SJeff Kirsher dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); 794adfc5217SJeff Kirsher dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); 795adfc5217SJeff Kirsher dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); 796adfc5217SJeff Kirsher 797adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 798adfc5217SJeff Kirsher dump_hdr.info = RI_E1_ONLINE; 799adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 800adfc5217SJeff Kirsher dump_hdr.info = RI_E1H_ONLINE; 801adfc5217SJeff Kirsher else if (!CHIP_IS_E1x(bp)) 802adfc5217SJeff Kirsher dump_hdr.info = RI_E2_ONLINE | 803adfc5217SJeff Kirsher (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); 804adfc5217SJeff Kirsher 805adfc5217SJeff Kirsher memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); 806adfc5217SJeff Kirsher p += dump_hdr.hdr_size + 1; 807adfc5217SJeff Kirsher 808adfc5217SJeff Kirsher /* Actually read the registers */ 809adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 810adfc5217SJeff Kirsher 811adfc5217SJeff Kirsher /* Re-enable parity attentions */ 812adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 813adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 814adfc5217SJeff Kirsher } 815adfc5217SJeff Kirsher 816adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 817adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 818adfc5217SJeff Kirsher { 819adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 820adfc5217SJeff Kirsher u8 phy_fw_ver[PHY_FW_VER_LEN]; 821adfc5217SJeff Kirsher 82268aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 82368aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 824adfc5217SJeff Kirsher 825adfc5217SJeff Kirsher phy_fw_ver[0] = '\0'; 826adfc5217SJeff Kirsher bnx2x_get_ext_phy_fw_version(&bp->link_params, 827adfc5217SJeff Kirsher phy_fw_ver, PHY_FW_VER_LEN); 82868aad78cSRick Jones strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version)); 829adfc5217SJeff Kirsher snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), 830adfc5217SJeff Kirsher "bc %d.%d.%d%s%s", 831adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff0000) >> 16, 832adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff00) >> 8, 833adfc5217SJeff Kirsher (bp->common.bc_ver & 0xff), 834adfc5217SJeff Kirsher ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); 83568aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 836adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 837cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 838adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 839adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 840adfc5217SJeff Kirsher } 841adfc5217SJeff Kirsher 842adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 843adfc5217SJeff Kirsher { 844adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 845adfc5217SJeff Kirsher 846adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 847adfc5217SJeff Kirsher wol->supported = 0; 848adfc5217SJeff Kirsher wol->wolopts = 0; 849adfc5217SJeff Kirsher } else { 850adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 851adfc5217SJeff Kirsher if (bp->wol) 852adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 853adfc5217SJeff Kirsher else 854adfc5217SJeff Kirsher wol->wolopts = 0; 855adfc5217SJeff Kirsher } 856adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 857adfc5217SJeff Kirsher } 858adfc5217SJeff Kirsher 859adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 860adfc5217SJeff Kirsher { 861adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 862adfc5217SJeff Kirsher 86351c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 86451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); 865adfc5217SJeff Kirsher return -EINVAL; 86651c1a580SMerav Sicron } 867adfc5217SJeff Kirsher 868adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 86951c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 87051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); 871adfc5217SJeff Kirsher return -EINVAL; 87251c1a580SMerav Sicron } 873adfc5217SJeff Kirsher bp->wol = 1; 874adfc5217SJeff Kirsher } else 875adfc5217SJeff Kirsher bp->wol = 0; 876adfc5217SJeff Kirsher 877adfc5217SJeff Kirsher return 0; 878adfc5217SJeff Kirsher } 879adfc5217SJeff Kirsher 880adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 881adfc5217SJeff Kirsher { 882adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 883adfc5217SJeff Kirsher 884adfc5217SJeff Kirsher return bp->msg_enable; 885adfc5217SJeff Kirsher } 886adfc5217SJeff Kirsher 887adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 888adfc5217SJeff Kirsher { 889adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 890adfc5217SJeff Kirsher 891adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 892adfc5217SJeff Kirsher /* dump MCP trace */ 893adfc5217SJeff Kirsher if (level & BNX2X_MSG_MCP) 894adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 895adfc5217SJeff Kirsher bp->msg_enable = level; 896adfc5217SJeff Kirsher } 897adfc5217SJeff Kirsher } 898adfc5217SJeff Kirsher 899adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 900adfc5217SJeff Kirsher { 901adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 902adfc5217SJeff Kirsher 903adfc5217SJeff Kirsher if (!bp->port.pmf) 904adfc5217SJeff Kirsher return 0; 905adfc5217SJeff Kirsher 906adfc5217SJeff Kirsher if (netif_running(dev)) { 907adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 9085d07d868SYuval Mintz bnx2x_force_link_reset(bp); 909adfc5217SJeff Kirsher bnx2x_link_set(bp); 910adfc5217SJeff Kirsher } 911adfc5217SJeff Kirsher 912adfc5217SJeff Kirsher return 0; 913adfc5217SJeff Kirsher } 914adfc5217SJeff Kirsher 915adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 916adfc5217SJeff Kirsher { 917adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 918adfc5217SJeff Kirsher 919adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 920adfc5217SJeff Kirsher return 0; 921adfc5217SJeff Kirsher 922adfc5217SJeff Kirsher return bp->link_vars.link_up; 923adfc5217SJeff Kirsher } 924adfc5217SJeff Kirsher 925adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 926adfc5217SJeff Kirsher { 927adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 928adfc5217SJeff Kirsher 929adfc5217SJeff Kirsher return bp->common.flash_size; 930adfc5217SJeff Kirsher } 931adfc5217SJeff Kirsher 932f16da43bSAriel Elior /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had 933f16da43bSAriel Elior * we done things the other way around, if two pfs from the same port would 934f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 935f16da43bSAriel Elior * as: 936f16da43bSAriel Elior * pf A takes the port lock. 937f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 938f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 939f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 940f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 941f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 942f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 943f16da43bSAriel Elior * acess corrupted by pf B).* 944f16da43bSAriel Elior */ 945adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 946adfc5217SJeff Kirsher { 947adfc5217SJeff Kirsher int port = BP_PORT(bp); 948adfc5217SJeff Kirsher int count, i; 949f16da43bSAriel Elior u32 val; 950f16da43bSAriel Elior 951f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 952f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 953adfc5217SJeff Kirsher 954adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 955adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 956adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 957adfc5217SJeff Kirsher count *= 100; 958adfc5217SJeff Kirsher 959adfc5217SJeff Kirsher /* request access to nvram interface */ 960adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 961adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 962adfc5217SJeff Kirsher 963adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 964adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 965adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 966adfc5217SJeff Kirsher break; 967adfc5217SJeff Kirsher 968adfc5217SJeff Kirsher udelay(5); 969adfc5217SJeff Kirsher } 970adfc5217SJeff Kirsher 971adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 97251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 97351c1a580SMerav Sicron "cannot get access to nvram interface\n"); 974adfc5217SJeff Kirsher return -EBUSY; 975adfc5217SJeff Kirsher } 976adfc5217SJeff Kirsher 977adfc5217SJeff Kirsher return 0; 978adfc5217SJeff Kirsher } 979adfc5217SJeff Kirsher 980adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 981adfc5217SJeff Kirsher { 982adfc5217SJeff Kirsher int port = BP_PORT(bp); 983adfc5217SJeff Kirsher int count, i; 984f16da43bSAriel Elior u32 val; 985adfc5217SJeff Kirsher 986adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 987adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 988adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 989adfc5217SJeff Kirsher count *= 100; 990adfc5217SJeff Kirsher 991adfc5217SJeff Kirsher /* relinquish nvram interface */ 992adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 993adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 994adfc5217SJeff Kirsher 995adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 996adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 997adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 998adfc5217SJeff Kirsher break; 999adfc5217SJeff Kirsher 1000adfc5217SJeff Kirsher udelay(5); 1001adfc5217SJeff Kirsher } 1002adfc5217SJeff Kirsher 1003adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 100451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 100551c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1006adfc5217SJeff Kirsher return -EBUSY; 1007adfc5217SJeff Kirsher } 1008adfc5217SJeff Kirsher 1009f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1010f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1011adfc5217SJeff Kirsher return 0; 1012adfc5217SJeff Kirsher } 1013adfc5217SJeff Kirsher 1014adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1015adfc5217SJeff Kirsher { 1016adfc5217SJeff Kirsher u32 val; 1017adfc5217SJeff Kirsher 1018adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1019adfc5217SJeff Kirsher 1020adfc5217SJeff Kirsher /* enable both bits, even on read */ 1021adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1022adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1023adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1024adfc5217SJeff Kirsher } 1025adfc5217SJeff Kirsher 1026adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1027adfc5217SJeff Kirsher { 1028adfc5217SJeff Kirsher u32 val; 1029adfc5217SJeff Kirsher 1030adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1031adfc5217SJeff Kirsher 1032adfc5217SJeff Kirsher /* disable both bits, even after read */ 1033adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1034adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1035adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1036adfc5217SJeff Kirsher } 1037adfc5217SJeff Kirsher 1038adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1039adfc5217SJeff Kirsher u32 cmd_flags) 1040adfc5217SJeff Kirsher { 1041adfc5217SJeff Kirsher int count, i, rc; 1042adfc5217SJeff Kirsher u32 val; 1043adfc5217SJeff Kirsher 1044adfc5217SJeff Kirsher /* build the command word */ 1045adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1046adfc5217SJeff Kirsher 1047adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1048adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1049adfc5217SJeff Kirsher 1050adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1051adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1052adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1053adfc5217SJeff Kirsher 1054adfc5217SJeff Kirsher /* issue a read command */ 1055adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1056adfc5217SJeff Kirsher 1057adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1058adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1059adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1060adfc5217SJeff Kirsher count *= 100; 1061adfc5217SJeff Kirsher 1062adfc5217SJeff Kirsher /* wait for completion */ 1063adfc5217SJeff Kirsher *ret_val = 0; 1064adfc5217SJeff Kirsher rc = -EBUSY; 1065adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1066adfc5217SJeff Kirsher udelay(5); 1067adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1068adfc5217SJeff Kirsher 1069adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1070adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1071adfc5217SJeff Kirsher /* we read nvram data in cpu order 1072adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 1073adfc5217SJeff Kirsher * converting to big-endian will do the work */ 1074adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1075adfc5217SJeff Kirsher rc = 0; 1076adfc5217SJeff Kirsher break; 1077adfc5217SJeff Kirsher } 1078adfc5217SJeff Kirsher } 107951c1a580SMerav Sicron if (rc == -EBUSY) 108051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 108151c1a580SMerav Sicron "nvram read timeout expired\n"); 1082adfc5217SJeff Kirsher return rc; 1083adfc5217SJeff Kirsher } 1084adfc5217SJeff Kirsher 1085adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1086adfc5217SJeff Kirsher int buf_size) 1087adfc5217SJeff Kirsher { 1088adfc5217SJeff Kirsher int rc; 1089adfc5217SJeff Kirsher u32 cmd_flags; 1090adfc5217SJeff Kirsher __be32 val; 1091adfc5217SJeff Kirsher 1092adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 109351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1094adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1095adfc5217SJeff Kirsher offset, buf_size); 1096adfc5217SJeff Kirsher return -EINVAL; 1097adfc5217SJeff Kirsher } 1098adfc5217SJeff Kirsher 1099adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 110051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 110151c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1102adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1103adfc5217SJeff Kirsher return -EINVAL; 1104adfc5217SJeff Kirsher } 1105adfc5217SJeff Kirsher 1106adfc5217SJeff Kirsher /* request access to nvram interface */ 1107adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1108adfc5217SJeff Kirsher if (rc) 1109adfc5217SJeff Kirsher return rc; 1110adfc5217SJeff Kirsher 1111adfc5217SJeff Kirsher /* enable access to nvram interface */ 1112adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1113adfc5217SJeff Kirsher 1114adfc5217SJeff Kirsher /* read the first word(s) */ 1115adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1116adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1117adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1118adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1119adfc5217SJeff Kirsher 1120adfc5217SJeff Kirsher /* advance to the next dword */ 1121adfc5217SJeff Kirsher offset += sizeof(u32); 1122adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1123adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1124adfc5217SJeff Kirsher cmd_flags = 0; 1125adfc5217SJeff Kirsher } 1126adfc5217SJeff Kirsher 1127adfc5217SJeff Kirsher if (rc == 0) { 1128adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1129adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1130adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1131adfc5217SJeff Kirsher } 1132adfc5217SJeff Kirsher 1133adfc5217SJeff Kirsher /* disable access to nvram interface */ 1134adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1135adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1136adfc5217SJeff Kirsher 1137adfc5217SJeff Kirsher return rc; 1138adfc5217SJeff Kirsher } 1139adfc5217SJeff Kirsher 1140adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1141adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1142adfc5217SJeff Kirsher { 1143adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1144adfc5217SJeff Kirsher int rc; 1145adfc5217SJeff Kirsher 114651c1a580SMerav Sicron if (!netif_running(dev)) { 114751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 114851c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1149adfc5217SJeff Kirsher return -EAGAIN; 115051c1a580SMerav Sicron } 1151adfc5217SJeff Kirsher 115251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1153f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1154adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1155adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1156adfc5217SJeff Kirsher 1157adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1158adfc5217SJeff Kirsher 1159adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1160adfc5217SJeff Kirsher 1161adfc5217SJeff Kirsher return rc; 1162adfc5217SJeff Kirsher } 1163adfc5217SJeff Kirsher 116424ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 116524ea818eSYuval Mintz struct ethtool_eeprom *ee, 116624ea818eSYuval Mintz u8 *data) 116724ea818eSYuval Mintz { 116824ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 116924ea818eSYuval Mintz int rc = 0, phy_idx; 117024ea818eSYuval Mintz u8 *user_data = data; 117124ea818eSYuval Mintz int remaining_len = ee->len, xfer_size; 117224ea818eSYuval Mintz unsigned int page_off = ee->offset; 117324ea818eSYuval Mintz 117424ea818eSYuval Mintz if (!netif_running(dev)) { 117524ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 117624ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 117724ea818eSYuval Mintz return -EAGAIN; 117824ea818eSYuval Mintz } 117924ea818eSYuval Mintz 118024ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 118124ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 118224ea818eSYuval Mintz while (!rc && remaining_len > 0) { 118324ea818eSYuval Mintz xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ? 118424ea818eSYuval Mintz SFP_EEPROM_PAGE_SIZE : remaining_len; 118524ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 118624ea818eSYuval Mintz &bp->link_params, 118724ea818eSYuval Mintz page_off, 118824ea818eSYuval Mintz xfer_size, 118924ea818eSYuval Mintz user_data); 119024ea818eSYuval Mintz remaining_len -= xfer_size; 119124ea818eSYuval Mintz user_data += xfer_size; 119224ea818eSYuval Mintz page_off += xfer_size; 119324ea818eSYuval Mintz } 119424ea818eSYuval Mintz 119524ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 119624ea818eSYuval Mintz return rc; 119724ea818eSYuval Mintz } 119824ea818eSYuval Mintz 119924ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 120024ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 120124ea818eSYuval Mintz { 120224ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 120324ea818eSYuval Mintz int phy_idx; 120424ea818eSYuval Mintz if (!netif_running(dev)) { 120524ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 120624ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 120724ea818eSYuval Mintz return -EAGAIN; 120824ea818eSYuval Mintz } 120924ea818eSYuval Mintz 121024ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 121124ea818eSYuval Mintz switch (bp->link_params.phy[phy_idx].media_type) { 121224ea818eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 121324ea818eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 121424ea818eSYuval Mintz case ETH_PHY_DA_TWINAX: 121524ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 121624ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 121724ea818eSYuval Mintz return 0; 121824ea818eSYuval Mintz default: 121924ea818eSYuval Mintz return -EOPNOTSUPP; 122024ea818eSYuval Mintz } 122124ea818eSYuval Mintz } 122224ea818eSYuval Mintz 1223adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1224adfc5217SJeff Kirsher u32 cmd_flags) 1225adfc5217SJeff Kirsher { 1226adfc5217SJeff Kirsher int count, i, rc; 1227adfc5217SJeff Kirsher 1228adfc5217SJeff Kirsher /* build the command word */ 1229adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1230adfc5217SJeff Kirsher 1231adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1232adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1233adfc5217SJeff Kirsher 1234adfc5217SJeff Kirsher /* write the data */ 1235adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1236adfc5217SJeff Kirsher 1237adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1238adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1239adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1240adfc5217SJeff Kirsher 1241adfc5217SJeff Kirsher /* issue the write command */ 1242adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1243adfc5217SJeff Kirsher 1244adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1245adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1246adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1247adfc5217SJeff Kirsher count *= 100; 1248adfc5217SJeff Kirsher 1249adfc5217SJeff Kirsher /* wait for completion */ 1250adfc5217SJeff Kirsher rc = -EBUSY; 1251adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1252adfc5217SJeff Kirsher udelay(5); 1253adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1254adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1255adfc5217SJeff Kirsher rc = 0; 1256adfc5217SJeff Kirsher break; 1257adfc5217SJeff Kirsher } 1258adfc5217SJeff Kirsher } 1259adfc5217SJeff Kirsher 126051c1a580SMerav Sicron if (rc == -EBUSY) 126151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 126251c1a580SMerav Sicron "nvram write timeout expired\n"); 1263adfc5217SJeff Kirsher return rc; 1264adfc5217SJeff Kirsher } 1265adfc5217SJeff Kirsher 1266adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1267adfc5217SJeff Kirsher 1268adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1269adfc5217SJeff Kirsher int buf_size) 1270adfc5217SJeff Kirsher { 1271adfc5217SJeff Kirsher int rc; 1272adfc5217SJeff Kirsher u32 cmd_flags; 1273adfc5217SJeff Kirsher u32 align_offset; 1274adfc5217SJeff Kirsher __be32 val; 1275adfc5217SJeff Kirsher 1276adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 127751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 127851c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1279adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1280adfc5217SJeff Kirsher return -EINVAL; 1281adfc5217SJeff Kirsher } 1282adfc5217SJeff Kirsher 1283adfc5217SJeff Kirsher /* request access to nvram interface */ 1284adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1285adfc5217SJeff Kirsher if (rc) 1286adfc5217SJeff Kirsher return rc; 1287adfc5217SJeff Kirsher 1288adfc5217SJeff Kirsher /* enable access to nvram interface */ 1289adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1290adfc5217SJeff Kirsher 1291adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1292adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 1293adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); 1294adfc5217SJeff Kirsher 1295adfc5217SJeff Kirsher if (rc == 0) { 1296adfc5217SJeff Kirsher val &= ~(0xff << BYTE_OFFSET(offset)); 1297adfc5217SJeff Kirsher val |= (*data_buf << BYTE_OFFSET(offset)); 1298adfc5217SJeff Kirsher 1299adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 1300adfc5217SJeff Kirsher * convert it back to cpu order */ 1301adfc5217SJeff Kirsher val = be32_to_cpu(val); 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1304adfc5217SJeff Kirsher cmd_flags); 1305adfc5217SJeff Kirsher } 1306adfc5217SJeff Kirsher 1307adfc5217SJeff Kirsher /* disable access to nvram interface */ 1308adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1309adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1310adfc5217SJeff Kirsher 1311adfc5217SJeff Kirsher return rc; 1312adfc5217SJeff Kirsher } 1313adfc5217SJeff Kirsher 1314adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1315adfc5217SJeff Kirsher int buf_size) 1316adfc5217SJeff Kirsher { 1317adfc5217SJeff Kirsher int rc; 1318adfc5217SJeff Kirsher u32 cmd_flags; 1319adfc5217SJeff Kirsher u32 val; 1320adfc5217SJeff Kirsher u32 written_so_far; 1321adfc5217SJeff Kirsher 1322adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1323adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1324adfc5217SJeff Kirsher 1325adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 132651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1327adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1328adfc5217SJeff Kirsher offset, buf_size); 1329adfc5217SJeff Kirsher return -EINVAL; 1330adfc5217SJeff Kirsher } 1331adfc5217SJeff Kirsher 1332adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 133351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 133451c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1335adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1336adfc5217SJeff Kirsher return -EINVAL; 1337adfc5217SJeff Kirsher } 1338adfc5217SJeff Kirsher 1339adfc5217SJeff Kirsher /* request access to nvram interface */ 1340adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1341adfc5217SJeff Kirsher if (rc) 1342adfc5217SJeff Kirsher return rc; 1343adfc5217SJeff Kirsher 1344adfc5217SJeff Kirsher /* enable access to nvram interface */ 1345adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1346adfc5217SJeff Kirsher 1347adfc5217SJeff Kirsher written_so_far = 0; 1348adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1349adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1350adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1351adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1352adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1353adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1354adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1355adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1356adfc5217SJeff Kirsher 1357adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1358adfc5217SJeff Kirsher 1359adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1360adfc5217SJeff Kirsher 1361adfc5217SJeff Kirsher /* advance to the next dword */ 1362adfc5217SJeff Kirsher offset += sizeof(u32); 1363adfc5217SJeff Kirsher data_buf += sizeof(u32); 1364adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1365adfc5217SJeff Kirsher cmd_flags = 0; 1366adfc5217SJeff Kirsher } 1367adfc5217SJeff Kirsher 1368adfc5217SJeff Kirsher /* disable access to nvram interface */ 1369adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1370adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1371adfc5217SJeff Kirsher 1372adfc5217SJeff Kirsher return rc; 1373adfc5217SJeff Kirsher } 1374adfc5217SJeff Kirsher 1375adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1376adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1377adfc5217SJeff Kirsher { 1378adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1379adfc5217SJeff Kirsher int port = BP_PORT(bp); 1380adfc5217SJeff Kirsher int rc = 0; 1381adfc5217SJeff Kirsher u32 ext_phy_config; 138251c1a580SMerav Sicron if (!netif_running(dev)) { 138351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 138451c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1385adfc5217SJeff Kirsher return -EAGAIN; 138651c1a580SMerav Sicron } 1387adfc5217SJeff Kirsher 138851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1389f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1390adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1391adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1392adfc5217SJeff Kirsher 1393adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1394adfc5217SJeff Kirsher 1395adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1396adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 139751c1a580SMerav Sicron !bp->port.pmf) { 139851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 139951c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1400adfc5217SJeff Kirsher return -EINVAL; 140151c1a580SMerav Sicron } 1402adfc5217SJeff Kirsher 1403adfc5217SJeff Kirsher ext_phy_config = 1404adfc5217SJeff Kirsher SHMEM_RD(bp, 1405adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1406adfc5217SJeff Kirsher 1407adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1408adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1409adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1410adfc5217SJeff Kirsher 1411adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1412adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1413adfc5217SJeff Kirsher &bp->link_vars, 0); 1414adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1415adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1416adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1417adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1418adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1419adfc5217SJeff Kirsher bnx2x_link_report(bp); 1420adfc5217SJeff Kirsher 1421adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1422adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1423adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1424adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1425adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1426adfc5217SJeff Kirsher &bp->link_vars, 1); 1427adfc5217SJeff Kirsher 1428adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1429adfc5217SJeff Kirsher &bp->link_vars); 1430adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1431adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1432adfc5217SJeff Kirsher } 1433adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1434adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1435adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1436adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1437adfc5217SJeff Kirsher 1438adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1439adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1440adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1441adfc5217SJeff Kirsher 1442adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1443adfc5217SJeff Kirsher 1444adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1445adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1446adfc5217SJeff Kirsher 1447adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1448adfc5217SJeff Kirsher msleep(500); 1449adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1450adfc5217SJeff Kirsher msleep(500); 1451adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1452adfc5217SJeff Kirsher } 1453adfc5217SJeff Kirsher } else 1454adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1455adfc5217SJeff Kirsher 1456adfc5217SJeff Kirsher return rc; 1457adfc5217SJeff Kirsher } 1458adfc5217SJeff Kirsher 1459adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1460adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1461adfc5217SJeff Kirsher { 1462adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1463adfc5217SJeff Kirsher 1464adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1465adfc5217SJeff Kirsher 1466adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1467adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1468adfc5217SJeff Kirsher 1469adfc5217SJeff Kirsher return 0; 1470adfc5217SJeff Kirsher } 1471adfc5217SJeff Kirsher 1472adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1473adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1474adfc5217SJeff Kirsher { 1475adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1476adfc5217SJeff Kirsher 1477adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1478adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1479adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1480adfc5217SJeff Kirsher 1481adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1482adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1483adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1484adfc5217SJeff Kirsher 1485adfc5217SJeff Kirsher if (netif_running(dev)) 1486adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1487adfc5217SJeff Kirsher 1488adfc5217SJeff Kirsher return 0; 1489adfc5217SJeff Kirsher } 1490adfc5217SJeff Kirsher 1491adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1492adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1493adfc5217SJeff Kirsher { 1494adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1495adfc5217SJeff Kirsher 1496adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1497adfc5217SJeff Kirsher 1498adfc5217SJeff Kirsher if (bp->rx_ring_size) 1499adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1500adfc5217SJeff Kirsher else 1501adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1502adfc5217SJeff Kirsher 1503a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1504adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1505adfc5217SJeff Kirsher } 1506adfc5217SJeff Kirsher 1507adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1508adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1509adfc5217SJeff Kirsher { 1510adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1511adfc5217SJeff Kirsher 1512adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 151351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 151451c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1515adfc5217SJeff Kirsher return -EAGAIN; 1516adfc5217SJeff Kirsher } 1517adfc5217SJeff Kirsher 1518adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1519adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1520adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1521a3348722SBarak Witkowski (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 152251c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 152351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1524adfc5217SJeff Kirsher return -EINVAL; 152551c1a580SMerav Sicron } 1526adfc5217SJeff Kirsher 1527adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1528adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1529adfc5217SJeff Kirsher 1530adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1531adfc5217SJeff Kirsher } 1532adfc5217SJeff Kirsher 1533adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1534adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1535adfc5217SJeff Kirsher { 1536adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1537adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 15389e7e8399SMintz Yuval int cfg_reg; 15399e7e8399SMintz Yuval 1540adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1541adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1542adfc5217SJeff Kirsher 15439e7e8399SMintz Yuval if (!epause->autoneg) 1544241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 15459e7e8399SMintz Yuval else 15469e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 15479e7e8399SMintz Yuval 15489e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1549adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 15509e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1551adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1552adfc5217SJeff Kirsher 155351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1554f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1555adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1556adfc5217SJeff Kirsher } 1557adfc5217SJeff Kirsher 1558adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1559adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1560adfc5217SJeff Kirsher { 1561adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1562adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1563adfc5217SJeff Kirsher if (IS_MF(bp)) 1564adfc5217SJeff Kirsher return 0; 1565adfc5217SJeff Kirsher 156651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1567f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1568adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1569adfc5217SJeff Kirsher 1570adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1571adfc5217SJeff Kirsher 1572adfc5217SJeff Kirsher if (epause->rx_pause) 1573adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1574adfc5217SJeff Kirsher 1575adfc5217SJeff Kirsher if (epause->tx_pause) 1576adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1577adfc5217SJeff Kirsher 1578adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1579adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1580adfc5217SJeff Kirsher 1581adfc5217SJeff Kirsher if (epause->autoneg) { 1582adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 158351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1584adfc5217SJeff Kirsher return -EINVAL; 1585adfc5217SJeff Kirsher } 1586adfc5217SJeff Kirsher 1587adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1588adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1589adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1590adfc5217SJeff Kirsher } 15915cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE; 15925cd75f0cSYaniv Rosner if (epause->rx_pause) 15935cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 15945cd75f0cSYaniv Rosner 15955cd75f0cSYaniv Rosner if (epause->tx_pause) 15965cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1597adfc5217SJeff Kirsher } 1598adfc5217SJeff Kirsher 159951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1600adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1601adfc5217SJeff Kirsher 1602adfc5217SJeff Kirsher if (netif_running(dev)) { 1603adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1604adfc5217SJeff Kirsher bnx2x_link_set(bp); 1605adfc5217SJeff Kirsher } 1606adfc5217SJeff Kirsher 1607adfc5217SJeff Kirsher return 0; 1608adfc5217SJeff Kirsher } 1609adfc5217SJeff Kirsher 16105889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1611cf2c1df6SMerav Sicron "register_test (offline) ", 1612cf2c1df6SMerav Sicron "memory_test (offline) ", 1613cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1614cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1615cf2c1df6SMerav Sicron "nvram_test (online) ", 1616cf2c1df6SMerav Sicron "interrupt_test (online) ", 1617cf2c1df6SMerav Sicron "link_test (online) " 1618adfc5217SJeff Kirsher }; 1619adfc5217SJeff Kirsher 1620e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 1621e9939c80SYuval Mintz { 1622e9939c80SYuval Mintz u32 modes = 0; 1623e9939c80SYuval Mintz 1624e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 1625e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 1626e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 1627e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 1628e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 1629e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 1630e9939c80SYuval Mintz 1631e9939c80SYuval Mintz return modes; 1632e9939c80SYuval Mintz } 1633e9939c80SYuval Mintz 1634e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1635e9939c80SYuval Mintz { 1636e9939c80SYuval Mintz u32 eee_adv = 0; 1637e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 1638e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 1639e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 1640e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 1641e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 1642e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 1643e9939c80SYuval Mintz 1644e9939c80SYuval Mintz return eee_adv << shift; 1645e9939c80SYuval Mintz } 1646e9939c80SYuval Mintz 1647e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1648e9939c80SYuval Mintz { 1649e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1650e9939c80SYuval Mintz u32 eee_cfg; 1651e9939c80SYuval Mintz 1652e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1653e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1654e9939c80SYuval Mintz return -EOPNOTSUPP; 1655e9939c80SYuval Mintz } 1656e9939c80SYuval Mintz 165708e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1658e9939c80SYuval Mintz 1659e9939c80SYuval Mintz edata->supported = 1660e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 1661e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 1662e9939c80SYuval Mintz 1663e9939c80SYuval Mintz edata->advertised = 1664e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 1665e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1666e9939c80SYuval Mintz edata->lp_advertised = 1667e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 1668e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 1669e9939c80SYuval Mintz 1670e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 1671e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 1672e9939c80SYuval Mintz 1673e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 1674e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 1675e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 1676e9939c80SYuval Mintz 1677e9939c80SYuval Mintz return 0; 1678e9939c80SYuval Mintz } 1679e9939c80SYuval Mintz 1680e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 1681e9939c80SYuval Mintz { 1682e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1683e9939c80SYuval Mintz u32 eee_cfg; 1684e9939c80SYuval Mintz u32 advertised; 1685e9939c80SYuval Mintz 1686e9939c80SYuval Mintz if (IS_MF(bp)) 1687e9939c80SYuval Mintz return 0; 1688e9939c80SYuval Mintz 1689e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1690e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1691e9939c80SYuval Mintz return -EOPNOTSUPP; 1692e9939c80SYuval Mintz } 1693e9939c80SYuval Mintz 169408e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1695e9939c80SYuval Mintz 1696e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 1697e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 1698e9939c80SYuval Mintz return -EOPNOTSUPP; 1699e9939c80SYuval Mintz } 1700e9939c80SYuval Mintz 1701e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 1702e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1703e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 1704e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1705efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 1706e9939c80SYuval Mintz return -EINVAL; 1707e9939c80SYuval Mintz } 1708e9939c80SYuval Mintz 1709e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 1710e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1711e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 1712e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 1713e9939c80SYuval Mintz return -EINVAL; 1714e9939c80SYuval Mintz } 1715e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 1716e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 1717e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1718e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 1719e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 1720e9939c80SYuval Mintz return -EINVAL; 1721e9939c80SYuval Mintz } 1722e9939c80SYuval Mintz 1723e9939c80SYuval Mintz /* All is well; Apply changes*/ 1724e9939c80SYuval Mintz if (edata->eee_enabled) 1725e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 1726e9939c80SYuval Mintz else 1727e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 1728e9939c80SYuval Mintz 1729e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 1730e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 1731e9939c80SYuval Mintz else 1732e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 1733e9939c80SYuval Mintz 1734e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 1735e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 1736e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 1737e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 1738e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 1739e9939c80SYuval Mintz 1740e9939c80SYuval Mintz /* Restart link to propogate changes */ 1741e9939c80SYuval Mintz if (netif_running(dev)) { 1742e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 17435d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1744e9939c80SYuval Mintz bnx2x_link_set(bp); 1745e9939c80SYuval Mintz } 1746e9939c80SYuval Mintz 1747e9939c80SYuval Mintz return 0; 1748e9939c80SYuval Mintz } 1749e9939c80SYuval Mintz 1750e9939c80SYuval Mintz 1751adfc5217SJeff Kirsher enum { 1752adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 1753adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 1754adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 1755adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 1756adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 1757adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 1758adfc5217SJeff Kirsher }; 1759adfc5217SJeff Kirsher 1760adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 1761adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 1762adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 1763adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 1764adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 1765adfc5217SJeff Kirsher 1766adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 1767adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 1768adfc5217SJeff Kirsher 1769adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 1770adfc5217SJeff Kirsher { 1771adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 1772adfc5217SJeff Kirsher u32 wr_val = 0, hw; 1773adfc5217SJeff Kirsher int port = BP_PORT(bp); 1774adfc5217SJeff Kirsher static const struct { 1775adfc5217SJeff Kirsher u32 hw; 1776adfc5217SJeff Kirsher u32 offset0; 1777adfc5217SJeff Kirsher u32 offset1; 1778adfc5217SJeff Kirsher u32 mask; 1779adfc5217SJeff Kirsher } reg_tbl[] = { 1780adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 1781adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 1782adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1783adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 1784adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 1785adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 1786adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1787adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 1788adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 1789adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 1790adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 1791adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 1792adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1793adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 1794adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1795adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 1796adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1797adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1798adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1799adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 1800adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 1801adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 1802adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1803adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 1804adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1805adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 1806adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1807adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 1808adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1809adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 1810adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1811adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 1812adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1813adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 1814adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1815adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 1816adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1817adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 1818adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1819adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 1820adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1821adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 1822adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1823adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 1824adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1825adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 1826adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1827adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 1828adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1829adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 1830adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1831adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 1832adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1833adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 1834adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1835adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 1836adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1837adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 1838adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1839adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 1840adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 1841adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 1842adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1843adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 1844adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1845adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 1846adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1847adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 1848adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1849adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 1850adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 1851adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 1852adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1853adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 1854adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 1855adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 1856adfc5217SJeff Kirsher 1857adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 1858adfc5217SJeff Kirsher }; 1859adfc5217SJeff Kirsher 186051c1a580SMerav Sicron if (!netif_running(bp->dev)) { 186151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 186251c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1863adfc5217SJeff Kirsher return rc; 186451c1a580SMerav Sicron } 1865adfc5217SJeff Kirsher 1866adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1867adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 1868adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1869adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 1870adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1871adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 1872adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 1873adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 1874adfc5217SJeff Kirsher else /* e3 A0 */ 1875adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 1876adfc5217SJeff Kirsher 1877adfc5217SJeff Kirsher /* Repeat the test twice: 1878adfc5217SJeff Kirsher First by writing 0x00000000, second by writing 0xffffffff */ 1879adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 1880adfc5217SJeff Kirsher 1881adfc5217SJeff Kirsher switch (idx) { 1882adfc5217SJeff Kirsher case 0: 1883adfc5217SJeff Kirsher wr_val = 0; 1884adfc5217SJeff Kirsher break; 1885adfc5217SJeff Kirsher case 1: 1886adfc5217SJeff Kirsher wr_val = 0xffffffff; 1887adfc5217SJeff Kirsher break; 1888adfc5217SJeff Kirsher } 1889adfc5217SJeff Kirsher 1890adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 1891adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 1892adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 1893adfc5217SJeff Kirsher continue; 1894adfc5217SJeff Kirsher 1895adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 1896adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 1897adfc5217SJeff Kirsher 1898adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 1899adfc5217SJeff Kirsher 1900adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 1901adfc5217SJeff Kirsher 1902adfc5217SJeff Kirsher val = REG_RD(bp, offset); 1903adfc5217SJeff Kirsher 1904adfc5217SJeff Kirsher /* Restore the original register's value */ 1905adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 1906adfc5217SJeff Kirsher 1907adfc5217SJeff Kirsher /* verify value is as expected */ 1908adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 190951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1910adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 1911adfc5217SJeff Kirsher offset, val, wr_val, mask); 1912adfc5217SJeff Kirsher goto test_reg_exit; 1913adfc5217SJeff Kirsher } 1914adfc5217SJeff Kirsher } 1915adfc5217SJeff Kirsher } 1916adfc5217SJeff Kirsher 1917adfc5217SJeff Kirsher rc = 0; 1918adfc5217SJeff Kirsher 1919adfc5217SJeff Kirsher test_reg_exit: 1920adfc5217SJeff Kirsher return rc; 1921adfc5217SJeff Kirsher } 1922adfc5217SJeff Kirsher 1923adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 1924adfc5217SJeff Kirsher { 1925adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 1926adfc5217SJeff Kirsher u32 val, index; 1927adfc5217SJeff Kirsher static const struct { 1928adfc5217SJeff Kirsher u32 offset; 1929adfc5217SJeff Kirsher int size; 1930adfc5217SJeff Kirsher } mem_tbl[] = { 1931adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 1932adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 1933adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 1934adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 1935adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 1936adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 1937adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 1938adfc5217SJeff Kirsher 1939adfc5217SJeff Kirsher { 0xffffffff, 0 } 1940adfc5217SJeff Kirsher }; 1941adfc5217SJeff Kirsher 1942adfc5217SJeff Kirsher static const struct { 1943adfc5217SJeff Kirsher char *name; 1944adfc5217SJeff Kirsher u32 offset; 1945adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 1946adfc5217SJeff Kirsher } prty_tbl[] = { 1947adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 1948adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1949adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 1950adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 1951adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 1952adfc5217SJeff Kirsher {0, 0, 0, 0} }, 1953adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 1954adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1955adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 1956adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 1957adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 1958adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 1959adfc5217SJeff Kirsher 1960adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 1961adfc5217SJeff Kirsher }; 1962adfc5217SJeff Kirsher 196351c1a580SMerav Sicron if (!netif_running(bp->dev)) { 196451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 196551c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1966adfc5217SJeff Kirsher return rc; 196751c1a580SMerav Sicron } 1968adfc5217SJeff Kirsher 1969adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 1970adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 1971adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 1972adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 1973adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 1974adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 1975adfc5217SJeff Kirsher else /* e3 */ 1976adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 1977adfc5217SJeff Kirsher 1978adfc5217SJeff Kirsher /* pre-Check the parity status */ 1979adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1980adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 1981adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 198251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1983adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 1984adfc5217SJeff Kirsher goto test_mem_exit; 1985adfc5217SJeff Kirsher } 1986adfc5217SJeff Kirsher } 1987adfc5217SJeff Kirsher 1988adfc5217SJeff Kirsher /* Go through all the memories */ 1989adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 1990adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 1991adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 1992adfc5217SJeff Kirsher 1993adfc5217SJeff Kirsher /* Check the parity status */ 1994adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1995adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 1996adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 199751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1998adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 1999adfc5217SJeff Kirsher goto test_mem_exit; 2000adfc5217SJeff Kirsher } 2001adfc5217SJeff Kirsher } 2002adfc5217SJeff Kirsher 2003adfc5217SJeff Kirsher rc = 0; 2004adfc5217SJeff Kirsher 2005adfc5217SJeff Kirsher test_mem_exit: 2006adfc5217SJeff Kirsher return rc; 2007adfc5217SJeff Kirsher } 2008adfc5217SJeff Kirsher 2009adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2010adfc5217SJeff Kirsher { 2011adfc5217SJeff Kirsher int cnt = 1400; 2012adfc5217SJeff Kirsher 2013adfc5217SJeff Kirsher if (link_up) { 2014adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2015adfc5217SJeff Kirsher msleep(20); 2016adfc5217SJeff Kirsher 2017adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 201851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 20198970b2e4SMerav Sicron 20208970b2e4SMerav Sicron cnt = 1400; 20218970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 20228970b2e4SMerav Sicron msleep(20); 20238970b2e4SMerav Sicron 20248970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 20258970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 20268970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2027adfc5217SJeff Kirsher } 2028adfc5217SJeff Kirsher } 2029adfc5217SJeff Kirsher 2030adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2031adfc5217SJeff Kirsher { 2032adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2033adfc5217SJeff Kirsher struct sk_buff *skb; 2034adfc5217SJeff Kirsher unsigned char *packet; 2035adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2036adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 203765565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2038adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2039adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2040b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2041adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2042adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2043adfc5217SJeff Kirsher dma_addr_t mapping; 2044adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2045adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2046adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2047adfc5217SJeff Kirsher u16 len; 2048adfc5217SJeff Kirsher int rc = -ENODEV; 2049e52fcb24SEric Dumazet u8 *data; 20508970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 20518970b2e4SMerav Sicron txdata->txq_index); 2052adfc5217SJeff Kirsher 2053adfc5217SJeff Kirsher /* check the loopback mode */ 2054adfc5217SJeff Kirsher switch (loopback_mode) { 2055adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 20568970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 20578970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2058adfc5217SJeff Kirsher return -EINVAL; 20598970b2e4SMerav Sicron } 2060adfc5217SJeff Kirsher break; 2061adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 206232911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 206332911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 206432911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 206532911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 206632911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 206732911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 206832911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 206932911333SYaniv Rosner else 207032911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 207132911333SYaniv Rosner } else 207232911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 207332911333SYaniv Rosner 2074adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2075adfc5217SJeff Kirsher break; 20768970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 20778970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 20788970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 20798970b2e4SMerav Sicron "Can't configure external loopback\n"); 20808970b2e4SMerav Sicron return -EINVAL; 20818970b2e4SMerav Sicron } 20828970b2e4SMerav Sicron break; 2083adfc5217SJeff Kirsher default: 208451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2085adfc5217SJeff Kirsher return -EINVAL; 2086adfc5217SJeff Kirsher } 2087adfc5217SJeff Kirsher 2088adfc5217SJeff Kirsher /* prepare the loopback packet */ 2089adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2090adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2091adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2092adfc5217SJeff Kirsher if (!skb) { 209351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2094adfc5217SJeff Kirsher rc = -ENOMEM; 2095adfc5217SJeff Kirsher goto test_loopback_exit; 2096adfc5217SJeff Kirsher } 2097adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2098adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2099adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 2100adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2101adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2102adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2103adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2104adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2105adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2106adfc5217SJeff Kirsher rc = -ENOMEM; 2107adfc5217SJeff Kirsher dev_kfree_skb(skb); 210851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2109adfc5217SJeff Kirsher goto test_loopback_exit; 2110adfc5217SJeff Kirsher } 2111adfc5217SJeff Kirsher 2112adfc5217SJeff Kirsher /* send the loopback packet */ 2113adfc5217SJeff Kirsher num_pkts = 0; 2114adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2115adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2116adfc5217SJeff Kirsher 211773dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 211873dbb5e1SDmitry Kravkov 2119adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2120adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2121adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2122adfc5217SJeff Kirsher tx_buf->skb = skb; 2123adfc5217SJeff Kirsher tx_buf->flags = 0; 2124adfc5217SJeff Kirsher 2125adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2126adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2127adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2128adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2129adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2130adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2131adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2132adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2133adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2134adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2135adfc5217SJeff Kirsher 1); 213696bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 213796bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 213896bed4b9SYuval Mintz 0); 2139adfc5217SJeff Kirsher 2140adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2141adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2142adfc5217SJeff Kirsher 214396bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 214496bed4b9SYuval Mintz u16 global_data = 0; 214596bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 214696bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2147adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 214896bed4b9SYuval Mintz SET_FLAG(global_data, 214996bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 215096bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 215196bed4b9SYuval Mintz } else { 215296bed4b9SYuval Mintz u32 parsing_data = 0; 215396bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 215496bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 215596bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 215696bed4b9SYuval Mintz SET_FLAG(parsing_data, 215796bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 215896bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 215996bed4b9SYuval Mintz } 2160adfc5217SJeff Kirsher wmb(); 2161adfc5217SJeff Kirsher 2162adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2163adfc5217SJeff Kirsher barrier(); 2164adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2165adfc5217SJeff Kirsher 2166adfc5217SJeff Kirsher mmiowb(); 2167adfc5217SJeff Kirsher barrier(); 2168adfc5217SJeff Kirsher 2169adfc5217SJeff Kirsher num_pkts++; 2170adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2171adfc5217SJeff Kirsher 2172adfc5217SJeff Kirsher udelay(100); 2173adfc5217SJeff Kirsher 2174adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2175adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2176adfc5217SJeff Kirsher goto test_loopback_exit; 2177adfc5217SJeff Kirsher 2178adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2179adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2180adfc5217SJeff Kirsher * disabled. 2181adfc5217SJeff Kirsher */ 2182adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2183adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2184adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2185adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2186adfc5217SJeff Kirsher */ 2187adfc5217SJeff Kirsher local_bh_disable(); 2188adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2189adfc5217SJeff Kirsher local_bh_enable(); 2190adfc5217SJeff Kirsher } 2191adfc5217SJeff Kirsher 2192adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2193adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2194adfc5217SJeff Kirsher goto test_loopback_exit; 2195adfc5217SJeff Kirsher 2196b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2197adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2198adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2199adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2200adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2201adfc5217SJeff Kirsher 2202621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2203adfc5217SJeff Kirsher if (len != pkt_size) 2204adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2205adfc5217SJeff Kirsher 2206adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2207adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2208adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2209adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2210e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2211adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2212e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2213adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2214adfc5217SJeff Kirsher 2215adfc5217SJeff Kirsher rc = 0; 2216adfc5217SJeff Kirsher 2217adfc5217SJeff Kirsher test_loopback_rx_exit: 2218adfc5217SJeff Kirsher 2219adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2220adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2221adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2222adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2223adfc5217SJeff Kirsher 2224adfc5217SJeff Kirsher /* Update producers */ 2225adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2226adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2227adfc5217SJeff Kirsher 2228adfc5217SJeff Kirsher test_loopback_exit: 2229adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2230adfc5217SJeff Kirsher 2231adfc5217SJeff Kirsher return rc; 2232adfc5217SJeff Kirsher } 2233adfc5217SJeff Kirsher 2234adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2235adfc5217SJeff Kirsher { 2236adfc5217SJeff Kirsher int rc = 0, res; 2237adfc5217SJeff Kirsher 2238adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2239adfc5217SJeff Kirsher return rc; 2240adfc5217SJeff Kirsher 2241adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2242adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2243adfc5217SJeff Kirsher 2244adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2245adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2246adfc5217SJeff Kirsher 2247adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2248adfc5217SJeff Kirsher if (res) { 224951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2250adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2251adfc5217SJeff Kirsher } 2252adfc5217SJeff Kirsher 2253adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2254adfc5217SJeff Kirsher if (res) { 225551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2256adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2257adfc5217SJeff Kirsher } 2258adfc5217SJeff Kirsher 2259adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2260adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2261adfc5217SJeff Kirsher 2262adfc5217SJeff Kirsher return rc; 2263adfc5217SJeff Kirsher } 2264adfc5217SJeff Kirsher 22658970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 22668970b2e4SMerav Sicron { 22678970b2e4SMerav Sicron int rc; 22688970b2e4SMerav Sicron u8 is_serdes = 22698970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 22708970b2e4SMerav Sicron 22718970b2e4SMerav Sicron if (BP_NOMCP(bp)) 22728970b2e4SMerav Sicron return -ENODEV; 22738970b2e4SMerav Sicron 22748970b2e4SMerav Sicron if (!netif_running(bp->dev)) 22758970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 22768970b2e4SMerav Sicron 22775d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 22788970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 22798970b2e4SMerav Sicron if (rc) { 22808970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 22818970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 22828970b2e4SMerav Sicron return -ENODEV; 22838970b2e4SMerav Sicron } 22848970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 22858970b2e4SMerav Sicron 22868970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 22878970b2e4SMerav Sicron 22888970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 22898970b2e4SMerav Sicron if (rc) 22908970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 22918970b2e4SMerav Sicron 22928970b2e4SMerav Sicron bnx2x_netif_start(bp); 22938970b2e4SMerav Sicron 22948970b2e4SMerav Sicron return rc; 22958970b2e4SMerav Sicron } 22968970b2e4SMerav Sicron 2297adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2298adfc5217SJeff Kirsher 2299adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2300adfc5217SJeff Kirsher { 2301adfc5217SJeff Kirsher static const struct { 2302adfc5217SJeff Kirsher int offset; 2303adfc5217SJeff Kirsher int size; 2304adfc5217SJeff Kirsher } nvram_tbl[] = { 2305adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2306adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2307adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2308adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2309adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2310adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2311adfc5217SJeff Kirsher { 0, 0 } 2312adfc5217SJeff Kirsher }; 2313afa13b4bSMintz Yuval __be32 *buf; 2314afa13b4bSMintz Yuval u8 *data; 2315adfc5217SJeff Kirsher int i, rc; 2316adfc5217SJeff Kirsher u32 magic, crc; 2317adfc5217SJeff Kirsher 2318adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2319adfc5217SJeff Kirsher return 0; 2320adfc5217SJeff Kirsher 2321afa13b4bSMintz Yuval buf = kmalloc(0x350, GFP_KERNEL); 2322afa13b4bSMintz Yuval if (!buf) { 232351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2324afa13b4bSMintz Yuval rc = -ENOMEM; 2325afa13b4bSMintz Yuval goto test_nvram_exit; 2326afa13b4bSMintz Yuval } 2327afa13b4bSMintz Yuval data = (u8 *)buf; 2328afa13b4bSMintz Yuval 2329adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, 0, data, 4); 2330adfc5217SJeff Kirsher if (rc) { 233151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 233251c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2333adfc5217SJeff Kirsher goto test_nvram_exit; 2334adfc5217SJeff Kirsher } 2335adfc5217SJeff Kirsher 2336adfc5217SJeff Kirsher magic = be32_to_cpu(buf[0]); 2337adfc5217SJeff Kirsher if (magic != 0x669955aa) { 233851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 233951c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2340adfc5217SJeff Kirsher rc = -ENODEV; 2341adfc5217SJeff Kirsher goto test_nvram_exit; 2342adfc5217SJeff Kirsher } 2343adfc5217SJeff Kirsher 2344adfc5217SJeff Kirsher for (i = 0; nvram_tbl[i].size; i++) { 2345adfc5217SJeff Kirsher 2346adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 2347adfc5217SJeff Kirsher nvram_tbl[i].size); 2348adfc5217SJeff Kirsher if (rc) { 234951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2350adfc5217SJeff Kirsher "nvram_tbl[%d] read data (rc %d)\n", i, rc); 2351adfc5217SJeff Kirsher goto test_nvram_exit; 2352adfc5217SJeff Kirsher } 2353adfc5217SJeff Kirsher 2354adfc5217SJeff Kirsher crc = ether_crc_le(nvram_tbl[i].size, data); 2355adfc5217SJeff Kirsher if (crc != CRC32_RESIDUAL) { 235651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 235751c1a580SMerav Sicron "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc); 2358adfc5217SJeff Kirsher rc = -ENODEV; 2359adfc5217SJeff Kirsher goto test_nvram_exit; 2360adfc5217SJeff Kirsher } 2361adfc5217SJeff Kirsher } 2362adfc5217SJeff Kirsher 2363adfc5217SJeff Kirsher test_nvram_exit: 2364afa13b4bSMintz Yuval kfree(buf); 2365adfc5217SJeff Kirsher return rc; 2366adfc5217SJeff Kirsher } 2367adfc5217SJeff Kirsher 2368adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2369adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2370adfc5217SJeff Kirsher { 23713b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2372adfc5217SJeff Kirsher 237351c1a580SMerav Sicron if (!netif_running(bp->dev)) { 237451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 237551c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2376adfc5217SJeff Kirsher return -ENODEV; 237751c1a580SMerav Sicron } 2378adfc5217SJeff Kirsher 237915192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2380adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2381adfc5217SJeff Kirsher 2382adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2383adfc5217SJeff Kirsher 2384adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2385adfc5217SJeff Kirsher } 2386adfc5217SJeff Kirsher 2387adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2388adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2389adfc5217SJeff Kirsher { 2390adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2391adfc5217SJeff Kirsher u8 is_serdes; 2392cf2c1df6SMerav Sicron int rc; 2393cf2c1df6SMerav Sicron 2394adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 239551c1a580SMerav Sicron netdev_err(bp->dev, 239651c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2397adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2398adfc5217SJeff Kirsher return; 2399adfc5217SJeff Kirsher } 24008970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 24018970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 24028970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 24038970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2404adfc5217SJeff Kirsher 2405cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2406adfc5217SJeff Kirsher 2407cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2408cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2409cf2c1df6SMerav Sicron "Can't perform self-test when interface is down\n"); 2410adfc5217SJeff Kirsher return; 2411cf2c1df6SMerav Sicron } 2412adfc5217SJeff Kirsher 2413adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2414adfc5217SJeff Kirsher 2415cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2416cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2417adfc5217SJeff Kirsher int port = BP_PORT(bp); 2418adfc5217SJeff Kirsher u32 val; 2419adfc5217SJeff Kirsher u8 link_up; 2420adfc5217SJeff Kirsher 2421adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2422adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2423adfc5217SJeff Kirsher /* disable input for TX port IF */ 2424adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2425adfc5217SJeff Kirsher 2426adfc5217SJeff Kirsher link_up = bp->link_vars.link_up; 2427adfc5217SJeff Kirsher 24285d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2429cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2430cf2c1df6SMerav Sicron if (rc) { 2431cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2432cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2433cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2434cf2c1df6SMerav Sicron return; 2435cf2c1df6SMerav Sicron } 2436cf2c1df6SMerav Sicron 2437adfc5217SJeff Kirsher /* wait until link state is restored */ 2438adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2439adfc5217SJeff Kirsher 2440adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2441adfc5217SJeff Kirsher buf[0] = 1; 2442adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2443adfc5217SJeff Kirsher } 2444adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2445adfc5217SJeff Kirsher buf[1] = 1; 2446adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2447adfc5217SJeff Kirsher } 2448adfc5217SJeff Kirsher 24498970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2450adfc5217SJeff Kirsher if (buf[2] != 0) 2451adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2452adfc5217SJeff Kirsher 24538970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 24548970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 24558970b2e4SMerav Sicron if (buf[3] != 0) 24568970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 24578970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 24588970b2e4SMerav Sicron } 24598970b2e4SMerav Sicron 24605d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2461adfc5217SJeff Kirsher 2462adfc5217SJeff Kirsher /* restore input for TX port IF */ 2463adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2464cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2465cf2c1df6SMerav Sicron if (rc) { 2466cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2467cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2468cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 2469cf2c1df6SMerav Sicron return; 2470cf2c1df6SMerav Sicron } 2471adfc5217SJeff Kirsher /* wait until link state is restored */ 2472adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2473adfc5217SJeff Kirsher } 2474adfc5217SJeff Kirsher if (bnx2x_test_nvram(bp) != 0) { 2475cf2c1df6SMerav Sicron if (!IS_MF(bp)) 24768970b2e4SMerav Sicron buf[4] = 1; 2477cf2c1df6SMerav Sicron else 2478cf2c1df6SMerav Sicron buf[0] = 1; 2479adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2480adfc5217SJeff Kirsher } 2481adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2482cf2c1df6SMerav Sicron if (!IS_MF(bp)) 24838970b2e4SMerav Sicron buf[5] = 1; 2484cf2c1df6SMerav Sicron else 2485cf2c1df6SMerav Sicron buf[1] = 1; 2486adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2487adfc5217SJeff Kirsher } 2488adfc5217SJeff Kirsher 2489adfc5217SJeff Kirsher if (bnx2x_link_test(bp, is_serdes) != 0) { 2490cf2c1df6SMerav Sicron if (!IS_MF(bp)) 24918970b2e4SMerav Sicron buf[6] = 1; 2492cf2c1df6SMerav Sicron else 2493cf2c1df6SMerav Sicron buf[2] = 1; 2494adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2495adfc5217SJeff Kirsher } 2496adfc5217SJeff Kirsher 2497adfc5217SJeff Kirsher #ifdef BNX2X_EXTRA_DEBUG 2498adfc5217SJeff Kirsher bnx2x_panic_dump(bp); 2499adfc5217SJeff Kirsher #endif 2500adfc5217SJeff Kirsher } 2501adfc5217SJeff Kirsher 2502adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 2503adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2504adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2505adfc5217SJeff Kirsher #define IS_MF_MODE_STAT(bp) \ 2506adfc5217SJeff Kirsher (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2507adfc5217SJeff Kirsher 2508adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 2509adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 2510adfc5217SJeff Kirsher */ 25111191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 2512adfc5217SJeff Kirsher { 2513adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 2514adfc5217SJeff Kirsher } 2515adfc5217SJeff Kirsher 2516adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2517adfc5217SJeff Kirsher { 2518adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2519adfc5217SJeff Kirsher int i, num_stats; 2520adfc5217SJeff Kirsher 2521adfc5217SJeff Kirsher switch (stringset) { 2522adfc5217SJeff Kirsher case ETH_SS_STATS: 2523adfc5217SJeff Kirsher if (is_multi(bp)) { 2524adfc5217SJeff Kirsher num_stats = bnx2x_num_stat_queues(bp) * 2525adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 2526d5e83632SYuval Mintz } else 2527adfc5217SJeff Kirsher num_stats = 0; 2528d5e83632SYuval Mintz if (IS_MF_MODE_STAT(bp)) { 2529adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 2530adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 2531adfc5217SJeff Kirsher num_stats++; 2532adfc5217SJeff Kirsher } else 2533d5e83632SYuval Mintz num_stats += BNX2X_NUM_STATS; 2534d5e83632SYuval Mintz 2535adfc5217SJeff Kirsher return num_stats; 2536adfc5217SJeff Kirsher 2537adfc5217SJeff Kirsher case ETH_SS_TEST: 2538cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 2539adfc5217SJeff Kirsher 2540adfc5217SJeff Kirsher default: 2541adfc5217SJeff Kirsher return -EINVAL; 2542adfc5217SJeff Kirsher } 2543adfc5217SJeff Kirsher } 2544adfc5217SJeff Kirsher 2545adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 2546adfc5217SJeff Kirsher { 2547adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 25485889335cSMerav Sicron int i, j, k, start; 2549adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 2550adfc5217SJeff Kirsher 2551adfc5217SJeff Kirsher switch (stringset) { 2552adfc5217SJeff Kirsher case ETH_SS_STATS: 2553adfc5217SJeff Kirsher k = 0; 2554d5e83632SYuval Mintz if (is_multi(bp)) { 2555adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 2556adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 2557adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 2558adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 2559adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 2560adfc5217SJeff Kirsher ETH_GSTRING_LEN, 2561adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 2562adfc5217SJeff Kirsher queue_name); 2563adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2564adfc5217SJeff Kirsher } 2565d5e83632SYuval Mintz } 2566d5e83632SYuval Mintz 2567d5e83632SYuval Mintz 2568adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2569adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2570adfc5217SJeff Kirsher continue; 2571d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 2572adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 2573adfc5217SJeff Kirsher j++; 2574adfc5217SJeff Kirsher } 2575d5e83632SYuval Mintz 2576adfc5217SJeff Kirsher break; 2577adfc5217SJeff Kirsher 2578adfc5217SJeff Kirsher case ETH_SS_TEST: 2579cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 2580cf2c1df6SMerav Sicron if (!IS_MF(bp)) 2581cf2c1df6SMerav Sicron start = 0; 2582cf2c1df6SMerav Sicron else 2583cf2c1df6SMerav Sicron start = 4; 25845889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 25855889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 2586adfc5217SJeff Kirsher } 2587adfc5217SJeff Kirsher } 2588adfc5217SJeff Kirsher 2589adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 2590adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 2591adfc5217SJeff Kirsher { 2592adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2593adfc5217SJeff Kirsher u32 *hw_stats, *offset; 2594d5e83632SYuval Mintz int i, j, k = 0; 2595adfc5217SJeff Kirsher 2596adfc5217SJeff Kirsher if (is_multi(bp)) { 2597adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 259815192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 2599adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 2600adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 2601adfc5217SJeff Kirsher /* skip this counter */ 2602adfc5217SJeff Kirsher buf[k + j] = 0; 2603adfc5217SJeff Kirsher continue; 2604adfc5217SJeff Kirsher } 2605adfc5217SJeff Kirsher offset = (hw_stats + 2606adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 2607adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 2608adfc5217SJeff Kirsher /* 4-byte counter */ 2609adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 2610adfc5217SJeff Kirsher continue; 2611adfc5217SJeff Kirsher } 2612adfc5217SJeff Kirsher /* 8-byte counter */ 2613adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2614adfc5217SJeff Kirsher } 2615adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2616adfc5217SJeff Kirsher } 2617adfc5217SJeff Kirsher } 2618d5e83632SYuval Mintz 2619adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 2620adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2621adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2622adfc5217SJeff Kirsher continue; 2623adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 2624adfc5217SJeff Kirsher /* skip this counter */ 2625d5e83632SYuval Mintz buf[k + j] = 0; 2626adfc5217SJeff Kirsher j++; 2627adfc5217SJeff Kirsher continue; 2628adfc5217SJeff Kirsher } 2629adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 2630adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 2631adfc5217SJeff Kirsher /* 4-byte counter */ 2632d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 2633adfc5217SJeff Kirsher j++; 2634adfc5217SJeff Kirsher continue; 2635adfc5217SJeff Kirsher } 2636adfc5217SJeff Kirsher /* 8-byte counter */ 2637d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2638adfc5217SJeff Kirsher j++; 2639adfc5217SJeff Kirsher } 2640adfc5217SJeff Kirsher } 2641adfc5217SJeff Kirsher 2642adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 2643adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 2644adfc5217SJeff Kirsher { 2645adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2646adfc5217SJeff Kirsher 264751c1a580SMerav Sicron if (!netif_running(dev)) { 264851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 264951c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2650adfc5217SJeff Kirsher return -EAGAIN; 265151c1a580SMerav Sicron } 2652adfc5217SJeff Kirsher 265351c1a580SMerav Sicron if (!bp->port.pmf) { 265451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n"); 2655adfc5217SJeff Kirsher return -EOPNOTSUPP; 265651c1a580SMerav Sicron } 2657adfc5217SJeff Kirsher 2658adfc5217SJeff Kirsher switch (state) { 2659adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 2660adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 2661adfc5217SJeff Kirsher 2662adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 26638203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2664adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2665adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 26668203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2667adfc5217SJeff Kirsher break; 2668adfc5217SJeff Kirsher 2669adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 26708203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2671adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2672adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 26738203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2674adfc5217SJeff Kirsher break; 2675adfc5217SJeff Kirsher 2676adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 26778203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2678adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2679adfc5217SJeff Kirsher LED_MODE_OPER, 2680adfc5217SJeff Kirsher bp->link_vars.line_speed); 26818203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2682adfc5217SJeff Kirsher } 2683adfc5217SJeff Kirsher 2684adfc5217SJeff Kirsher return 0; 2685adfc5217SJeff Kirsher } 2686adfc5217SJeff Kirsher 26875d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 26885d317c6aSMerav Sicron { 26895d317c6aSMerav Sicron 26905d317c6aSMerav Sicron switch (info->flow_type) { 26915d317c6aSMerav Sicron case TCP_V4_FLOW: 26925d317c6aSMerav Sicron case TCP_V6_FLOW: 26935d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 26945d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 26955d317c6aSMerav Sicron break; 26965d317c6aSMerav Sicron case UDP_V4_FLOW: 26975d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 26985d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 26995d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 27005d317c6aSMerav Sicron else 27015d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 27025d317c6aSMerav Sicron break; 27035d317c6aSMerav Sicron case UDP_V6_FLOW: 27045d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 27055d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 27065d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 27075d317c6aSMerav Sicron else 27085d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 27095d317c6aSMerav Sicron break; 27105d317c6aSMerav Sicron case IPV4_FLOW: 27115d317c6aSMerav Sicron case IPV6_FLOW: 27125d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 27135d317c6aSMerav Sicron break; 27145d317c6aSMerav Sicron default: 27155d317c6aSMerav Sicron info->data = 0; 27165d317c6aSMerav Sicron break; 27175d317c6aSMerav Sicron } 27185d317c6aSMerav Sicron 27195d317c6aSMerav Sicron return 0; 27205d317c6aSMerav Sicron } 27215d317c6aSMerav Sicron 2722adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2723815c7db5SBen Hutchings u32 *rules __always_unused) 2724adfc5217SJeff Kirsher { 2725adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2726adfc5217SJeff Kirsher 2727adfc5217SJeff Kirsher switch (info->cmd) { 2728adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 2729adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 2730adfc5217SJeff Kirsher return 0; 27315d317c6aSMerav Sicron case ETHTOOL_GRXFH: 27325d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 27335d317c6aSMerav Sicron default: 27345d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 27355d317c6aSMerav Sicron return -EOPNOTSUPP; 27365d317c6aSMerav Sicron } 27375d317c6aSMerav Sicron } 2738adfc5217SJeff Kirsher 27395d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 27405d317c6aSMerav Sicron { 27415d317c6aSMerav Sicron int udp_rss_requested; 27425d317c6aSMerav Sicron 27435d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27445d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 27455d317c6aSMerav Sicron info->flow_type, info->data); 27465d317c6aSMerav Sicron 27475d317c6aSMerav Sicron switch (info->flow_type) { 27485d317c6aSMerav Sicron case TCP_V4_FLOW: 27495d317c6aSMerav Sicron case TCP_V6_FLOW: 27505d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 27515d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 27525d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 27535d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27545d317c6aSMerav Sicron "Command parameters not supported\n"); 27555d317c6aSMerav Sicron return -EINVAL; 27565d317c6aSMerav Sicron } else { 27575d317c6aSMerav Sicron return 0; 27585d317c6aSMerav Sicron } 27595d317c6aSMerav Sicron 27605d317c6aSMerav Sicron case UDP_V4_FLOW: 27615d317c6aSMerav Sicron case UDP_V6_FLOW: 27625d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 27635d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 27645d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 27655d317c6aSMerav Sicron udp_rss_requested = 1; 27665d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 27675d317c6aSMerav Sicron udp_rss_requested = 0; 27685d317c6aSMerav Sicron else 27695d317c6aSMerav Sicron return -EINVAL; 27705d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 27715d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 27725d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 27735d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27745d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 27755d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 27765d317c6aSMerav Sicron return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 27775d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 27785d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 27795d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 27805d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27815d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 27825d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 2783337da3e3SDan Carpenter return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 27845d317c6aSMerav Sicron } else { 27855d317c6aSMerav Sicron return 0; 27865d317c6aSMerav Sicron } 27875d317c6aSMerav Sicron case IPV4_FLOW: 27885d317c6aSMerav Sicron case IPV6_FLOW: 27895d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 27905d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 27915d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 27925d317c6aSMerav Sicron "Command parameters not supported\n"); 27935d317c6aSMerav Sicron return -EINVAL; 27945d317c6aSMerav Sicron } else { 27955d317c6aSMerav Sicron return 0; 27965d317c6aSMerav Sicron } 27975d317c6aSMerav Sicron case SCTP_V4_FLOW: 27985d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 27995d317c6aSMerav Sicron case AH_V4_FLOW: 28005d317c6aSMerav Sicron case ESP_V4_FLOW: 28015d317c6aSMerav Sicron case SCTP_V6_FLOW: 28025d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 28035d317c6aSMerav Sicron case AH_V6_FLOW: 28045d317c6aSMerav Sicron case ESP_V6_FLOW: 28055d317c6aSMerav Sicron case IP_USER_FLOW: 28065d317c6aSMerav Sicron case ETHER_FLOW: 28075d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 28085d317c6aSMerav Sicron if (info->data) { 28095d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 28105d317c6aSMerav Sicron "Command parameters not supported\n"); 28115d317c6aSMerav Sicron return -EINVAL; 28125d317c6aSMerav Sicron } else { 28135d317c6aSMerav Sicron return 0; 28145d317c6aSMerav Sicron } 28155d317c6aSMerav Sicron default: 28165d317c6aSMerav Sicron return -EINVAL; 28175d317c6aSMerav Sicron } 28185d317c6aSMerav Sicron } 28195d317c6aSMerav Sicron 28205d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 28215d317c6aSMerav Sicron { 28225d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 28235d317c6aSMerav Sicron 28245d317c6aSMerav Sicron switch (info->cmd) { 28255d317c6aSMerav Sicron case ETHTOOL_SRXFH: 28265d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 2827adfc5217SJeff Kirsher default: 282851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2829adfc5217SJeff Kirsher return -EOPNOTSUPP; 2830adfc5217SJeff Kirsher } 2831adfc5217SJeff Kirsher } 2832adfc5217SJeff Kirsher 28337850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 2834adfc5217SJeff Kirsher { 283596305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 28367850f63fSBen Hutchings } 28377850f63fSBen Hutchings 28387850f63fSBen Hutchings static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 28397850f63fSBen Hutchings { 28407850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 2841adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 2842adfc5217SJeff Kirsher size_t i; 2843adfc5217SJeff Kirsher 2844adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 2845adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 2846adfc5217SJeff Kirsher 2847adfc5217SJeff Kirsher /* 2848adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 2849adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 2850adfc5217SJeff Kirsher * points to an array of u32. 2851adfc5217SJeff Kirsher * 2852adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2853adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 2854adfc5217SJeff Kirsher * queue. 2855adfc5217SJeff Kirsher */ 28567850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 28577850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 2858adfc5217SJeff Kirsher 2859adfc5217SJeff Kirsher return 0; 2860adfc5217SJeff Kirsher } 2861adfc5217SJeff Kirsher 28627850f63fSBen Hutchings static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 2863adfc5217SJeff Kirsher { 2864adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2865adfc5217SJeff Kirsher size_t i; 2866adfc5217SJeff Kirsher 2867adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2868adfc5217SJeff Kirsher /* 2869adfc5217SJeff Kirsher * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 2870adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 2871adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 2872adfc5217SJeff Kirsher * 2873adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 2874adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 2875adfc5217SJeff Kirsher * queue 2876adfc5217SJeff Kirsher */ 28775d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 2878adfc5217SJeff Kirsher } 2879adfc5217SJeff Kirsher 28805d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 2881adfc5217SJeff Kirsher } 2882adfc5217SJeff Kirsher 28830e8d2ec5SMerav Sicron /** 28840e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 28850e8d2ec5SMerav Sicron * 28860e8d2ec5SMerav Sicron * @dev: net device 28870e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 28880e8d2ec5SMerav Sicron */ 28890e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 28900e8d2ec5SMerav Sicron struct ethtool_channels *channels) 28910e8d2ec5SMerav Sicron { 28920e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 28930e8d2ec5SMerav Sicron 28940e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 28950e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 28960e8d2ec5SMerav Sicron } 28970e8d2ec5SMerav Sicron 28980e8d2ec5SMerav Sicron /** 28990e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 29000e8d2ec5SMerav Sicron * 29010e8d2ec5SMerav Sicron * @bp: bnx2x private structure 29020e8d2ec5SMerav Sicron * 29030e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 29040e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 29050e8d2ec5SMerav Sicron */ 29060e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 29070e8d2ec5SMerav Sicron { 29080e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 290955c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 291055c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 291155c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 29120e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 29130e8d2ec5SMerav Sicron } 29140e8d2ec5SMerav Sicron 29150e8d2ec5SMerav Sicron /** 29160e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 29170e8d2ec5SMerav Sicron * 29180e8d2ec5SMerav Sicron * @dev: net device 29190e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 29200e8d2ec5SMerav Sicron */ 29210e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 29220e8d2ec5SMerav Sicron struct ethtool_channels *channels) 29230e8d2ec5SMerav Sicron { 29240e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 29250e8d2ec5SMerav Sicron 29260e8d2ec5SMerav Sicron 29270e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29280e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 29290e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 29300e8d2ec5SMerav Sicron channels->combined_count); 29310e8d2ec5SMerav Sicron 29320e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 29330e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 29340e8d2ec5SMerav Sicron */ 29350e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 29360e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 29370e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 29380e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 29390e8d2ec5SMerav Sicron return -EINVAL; 29400e8d2ec5SMerav Sicron } 29410e8d2ec5SMerav Sicron 29420e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 29430e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 29440e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 29450e8d2ec5SMerav Sicron return 0; 29460e8d2ec5SMerav Sicron } 29470e8d2ec5SMerav Sicron 29480e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 29490e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 29500e8d2ec5SMerav Sicron * less than requested if memory is low. 29510e8d2ec5SMerav Sicron */ 29520e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 29530e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 29540e8d2ec5SMerav Sicron return 0; 29550e8d2ec5SMerav Sicron } 29565d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 29570e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 29580e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 29590e8d2ec5SMerav Sicron } 29600e8d2ec5SMerav Sicron 2961adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 2962adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 2963adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 2964adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 2965adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 2966adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 2967adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 2968adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 2969adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 2970adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 2971adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 2972adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 2973adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 2974adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 2975adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 2976adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 2977adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 2978adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 2979adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 2980adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 2981adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 2982adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 2983adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 2984adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 2985adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 2986adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 2987adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 29885d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 29897850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 2990adfc5217SJeff Kirsher .get_rxfh_indir = bnx2x_get_rxfh_indir, 2991adfc5217SJeff Kirsher .set_rxfh_indir = bnx2x_set_rxfh_indir, 29920e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 29930e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 299424ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 299524ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 2996e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 2997e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 2998be53ce1eSRichard Cochran .get_ts_info = ethtool_op_get_ts_info, 2999adfc5217SJeff Kirsher }; 3000adfc5217SJeff Kirsher 3001adfc5217SJeff Kirsher void bnx2x_set_ethtool_ops(struct net_device *netdev) 3002adfc5217SJeff Kirsher { 3003adfc5217SJeff Kirsher SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 3004adfc5217SJeff Kirsher } 3005