1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 908f6dd89SAriel Elior * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher #include "bnx2x.h" 26adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 27adfc5217SJeff Kirsher #include "bnx2x_dump.h" 28adfc5217SJeff Kirsher #include "bnx2x_init.h" 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 31adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33adfc5217SJeff Kirsher */ 34adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 35adfc5217SJeff Kirsher static const struct { 36adfc5217SJeff Kirsher long offset; 37adfc5217SJeff Kirsher int size; 38adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 39adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 40adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 49adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53adfc5217SJeff Kirsher 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 65c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 68adfc5217SJeff Kirsher }; 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher static const struct { 73adfc5217SJeff Kirsher long offset; 74adfc5217SJeff Kirsher int size; 75adfc5217SJeff Kirsher u32 flags; 76adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 77adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 78adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 80adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 81adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 101adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 104adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 106adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 108adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1090e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1100e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1110e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1120e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 114adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 122adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 128adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129adfc5217SJeff Kirsher 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 131adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1777a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1797a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1817a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 183c96bdc0cSDmitry Kravkov 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 185e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 18907ba6af4SMiriam Shitrit 190adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 191adfc5217SJeff Kirsher { 192adfc5217SJeff Kirsher int port_type; 193adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 195dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 196dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 198adfc5217SJeff Kirsher case ETH_PHY_KR: 199adfc5217SJeff Kirsher case ETH_PHY_CX4: 200adfc5217SJeff Kirsher port_type = PORT_FIBRE; 201adfc5217SJeff Kirsher break; 202adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 203adfc5217SJeff Kirsher port_type = PORT_DA; 204adfc5217SJeff Kirsher break; 205adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 206adfc5217SJeff Kirsher port_type = PORT_TP; 207adfc5217SJeff Kirsher break; 208adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 209adfc5217SJeff Kirsher port_type = PORT_NONE; 210adfc5217SJeff Kirsher break; 211adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 212adfc5217SJeff Kirsher default: 213adfc5217SJeff Kirsher port_type = PORT_OTHER; 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher return port_type; 217adfc5217SJeff Kirsher } 218adfc5217SJeff Kirsher 219adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 220adfc5217SJeff Kirsher { 221adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 222adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 223adfc5217SJeff Kirsher 224adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 225adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 226adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 227adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 228adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 229dbef807eSYuval Mintz if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 230dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER) { 231dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 232dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 233dbef807eSYuval Mintz } 234adfc5217SJeff Kirsher 23559694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 23659694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 237adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 238adfc5217SJeff Kirsher 23938298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 240adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 24159694f00SYuval Mintz else 24259694f00SYuval Mintz ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 24338298461SYuval Mintz } else { 24438298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 24538298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 24638298461SYuval Mintz } 247adfc5217SJeff Kirsher 248adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 249adfc5217SJeff Kirsher 250adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 251adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 254adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 255adfc5217SJeff Kirsher else 256adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 257adfc5217SJeff Kirsher 2589e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2599e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2609e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2619e7e8399SMintz Yuval 2629e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 2639e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 2649e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 2659e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 2669e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 2679e7e8399SMintz Yuval 2689e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 2699e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 2709e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 2719e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 2729e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 2739e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 2749e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 2759e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 2769e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 2779e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 2789e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 2799e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 2809e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 2819e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 2829e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 2839e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 284be94bea7SYaniv Rosner if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 285be94bea7SYaniv Rosner cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 2869e7e8399SMintz Yuval } 2879e7e8399SMintz Yuval 288adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 289adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 290adfc5217SJeff Kirsher 29151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 292f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 293f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 294f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 295adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 296adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 297adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 298adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 299adfc5217SJeff Kirsher 300adfc5217SJeff Kirsher return 0; 301adfc5217SJeff Kirsher } 302adfc5217SJeff Kirsher 303adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 304adfc5217SJeff Kirsher { 305adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 306adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 307dbef807eSYuval Mintz u32 speed, phy_idx; 308adfc5217SJeff Kirsher 309adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 310adfc5217SJeff Kirsher return 0; 311adfc5217SJeff Kirsher 31251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 313adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 314adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 315adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 316adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 317adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 318adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 319adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 320adfc5217SJeff Kirsher 321adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 322adfc5217SJeff Kirsher 32316a5fd92SYuval Mintz /* If received a request for an unknown duplex, assume full*/ 32438298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 32538298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 32638298461SYuval Mintz 327adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 328adfc5217SJeff Kirsher u32 part; 329adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 330adfc5217SJeff Kirsher 331adfc5217SJeff Kirsher /* use 10G if no link detected */ 332adfc5217SJeff Kirsher if (!line_speed) 333adfc5217SJeff Kirsher line_speed = 10000; 334adfc5217SJeff Kirsher 335adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 33651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33751c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 338adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 339adfc5217SJeff Kirsher return -EINVAL; 340adfc5217SJeff Kirsher } 341adfc5217SJeff Kirsher 342adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 343adfc5217SJeff Kirsher 344adfc5217SJeff Kirsher if (line_speed < speed || !part) { 34551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34651c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 347adfc5217SJeff Kirsher return -EINVAL; 348adfc5217SJeff Kirsher } 349adfc5217SJeff Kirsher 350adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 351adfc5217SJeff Kirsher /* store value for following "load" */ 352adfc5217SJeff Kirsher bp->pending_max = part; 353adfc5217SJeff Kirsher else 354adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 355adfc5217SJeff Kirsher 356adfc5217SJeff Kirsher return 0; 357adfc5217SJeff Kirsher } 358adfc5217SJeff Kirsher 359adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 360adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 36133f9e6f5SYaniv Rosner if (cmd->port != bnx2x_get_port_type(bp)) { 362adfc5217SJeff Kirsher switch (cmd->port) { 363adfc5217SJeff Kirsher case PORT_TP: 364adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 365adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 36633f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 36733f9e6f5SYaniv Rosner "Unsupported port type\n"); 368adfc5217SJeff Kirsher return -EINVAL; 369adfc5217SJeff Kirsher } 370adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 371adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 372adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 373adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 374adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 375adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 376adfc5217SJeff Kirsher else 377adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 378adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 379adfc5217SJeff Kirsher break; 380adfc5217SJeff Kirsher case PORT_FIBRE: 381bfdb5823SYaniv Rosner case PORT_DA: 382adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 383adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 38433f9e6f5SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, 38533f9e6f5SYaniv Rosner "Unsupported port type\n"); 386adfc5217SJeff Kirsher return -EINVAL; 387adfc5217SJeff Kirsher } 388adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 389adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 390adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 391adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 392adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 393adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 394adfc5217SJeff Kirsher else 395adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 396adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 397adfc5217SJeff Kirsher break; 398adfc5217SJeff Kirsher default: 39951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 400adfc5217SJeff Kirsher return -EINVAL; 401adfc5217SJeff Kirsher } 40233f9e6f5SYaniv Rosner } 4032de67439SYuval Mintz /* Save new config in case command complete successfully */ 404adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 405adfc5217SJeff Kirsher /* Get the new cfg_idx */ 406adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 407adfc5217SJeff Kirsher /* Restore old config in case command failed */ 408adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 40951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 410adfc5217SJeff Kirsher 411adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 41275318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 41375318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 41475318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 41575318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 41675318327SYaniv Rosner SUPPORTED_100baseT_Full); 417adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 41851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 419adfc5217SJeff Kirsher return -EINVAL; 420adfc5217SJeff Kirsher } 421adfc5217SJeff Kirsher 422adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 42375318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 42451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 42551c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4268decf868SDavid S. Miller return -EINVAL; 4278decf868SDavid S. Miller } 428adfc5217SJeff Kirsher 429adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4308decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4318decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 432adfc5217SJeff Kirsher cmd->advertising); 4338decf868SDavid S. Miller if (cmd->advertising) { 434adfc5217SJeff Kirsher 4358decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4368decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4378decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4388decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4398decf868SDavid S. Miller } 4408decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4418decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4428decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4438decf868SDavid S. Miller 4448decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4458decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4468decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4478decf868SDavid S. Miller 4488decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4498decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4508decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4518decf868SDavid S. Miller } 4528decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4538decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4548decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4558decf868SDavid S. Miller } 4568decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4578decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4588decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4598decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4608decf868SDavid S. Miller 4618decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4628decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 4638decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 4648decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4658decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 466be94bea7SYaniv Rosner 467be94bea7SYaniv Rosner if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 468be94bea7SYaniv Rosner bp->link_params.speed_cap_mask[cfg_idx] |= 469be94bea7SYaniv Rosner PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 4708decf868SDavid S. Miller } 471adfc5217SJeff Kirsher } else { /* forced speed */ 472adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 473adfc5217SJeff Kirsher switch (speed) { 474adfc5217SJeff Kirsher case SPEED_10: 475adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 476adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 477adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 47851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 479adfc5217SJeff Kirsher "10M full not supported\n"); 480adfc5217SJeff Kirsher return -EINVAL; 481adfc5217SJeff Kirsher } 482adfc5217SJeff Kirsher 483adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 484adfc5217SJeff Kirsher ADVERTISED_TP); 485adfc5217SJeff Kirsher } else { 486adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 487adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 48851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 489adfc5217SJeff Kirsher "10M half not supported\n"); 490adfc5217SJeff Kirsher return -EINVAL; 491adfc5217SJeff Kirsher } 492adfc5217SJeff Kirsher 493adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 494adfc5217SJeff Kirsher ADVERTISED_TP); 495adfc5217SJeff Kirsher } 496adfc5217SJeff Kirsher break; 497adfc5217SJeff Kirsher 498adfc5217SJeff Kirsher case SPEED_100: 499adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 500adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 501adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 50251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 503adfc5217SJeff Kirsher "100M full not supported\n"); 504adfc5217SJeff Kirsher return -EINVAL; 505adfc5217SJeff Kirsher } 506adfc5217SJeff Kirsher 507adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 508adfc5217SJeff Kirsher ADVERTISED_TP); 509adfc5217SJeff Kirsher } else { 510adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 511adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 51251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 513adfc5217SJeff Kirsher "100M half not supported\n"); 514adfc5217SJeff Kirsher return -EINVAL; 515adfc5217SJeff Kirsher } 516adfc5217SJeff Kirsher 517adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 518adfc5217SJeff Kirsher ADVERTISED_TP); 519adfc5217SJeff Kirsher } 520adfc5217SJeff Kirsher break; 521adfc5217SJeff Kirsher 522adfc5217SJeff Kirsher case SPEED_1000: 523adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 52451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52551c1a580SMerav Sicron "1G half not supported\n"); 526adfc5217SJeff Kirsher return -EINVAL; 527adfc5217SJeff Kirsher } 528adfc5217SJeff Kirsher 529adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 530adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 53151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 53251c1a580SMerav Sicron "1G full not supported\n"); 533adfc5217SJeff Kirsher return -EINVAL; 534adfc5217SJeff Kirsher } 535adfc5217SJeff Kirsher 536adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 537adfc5217SJeff Kirsher ADVERTISED_TP); 538adfc5217SJeff Kirsher break; 539adfc5217SJeff Kirsher 540adfc5217SJeff Kirsher case SPEED_2500: 541adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 54251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 543adfc5217SJeff Kirsher "2.5G half not supported\n"); 544adfc5217SJeff Kirsher return -EINVAL; 545adfc5217SJeff Kirsher } 546adfc5217SJeff Kirsher 547adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 548adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 54951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 550adfc5217SJeff Kirsher "2.5G full not supported\n"); 551adfc5217SJeff Kirsher return -EINVAL; 552adfc5217SJeff Kirsher } 553adfc5217SJeff Kirsher 554adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 555adfc5217SJeff Kirsher ADVERTISED_TP); 556adfc5217SJeff Kirsher break; 557adfc5217SJeff Kirsher 558adfc5217SJeff Kirsher case SPEED_10000: 559adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 56051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56151c1a580SMerav Sicron "10G half not supported\n"); 562adfc5217SJeff Kirsher return -EINVAL; 563adfc5217SJeff Kirsher } 564dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 565adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 566dbef807eSYuval Mintz & SUPPORTED_10000baseT_Full) || 567dbef807eSYuval Mintz (bp->link_params.phy[phy_idx].media_type == 568dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 56951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 57051c1a580SMerav Sicron "10G full not supported\n"); 571adfc5217SJeff Kirsher return -EINVAL; 572adfc5217SJeff Kirsher } 573adfc5217SJeff Kirsher 574adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 575adfc5217SJeff Kirsher ADVERTISED_FIBRE); 576adfc5217SJeff Kirsher break; 577adfc5217SJeff Kirsher 578adfc5217SJeff Kirsher default: 57951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 580adfc5217SJeff Kirsher return -EINVAL; 581adfc5217SJeff Kirsher } 582adfc5217SJeff Kirsher 583adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 584adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 585adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 586adfc5217SJeff Kirsher } 587adfc5217SJeff Kirsher 58851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 589f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 590adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 591adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 592adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 593adfc5217SJeff Kirsher 594adfc5217SJeff Kirsher /* Set new config */ 595adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 596adfc5217SJeff Kirsher if (netif_running(dev)) { 597adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 598adfc5217SJeff Kirsher bnx2x_link_set(bp); 599adfc5217SJeff Kirsher } 600adfc5217SJeff Kirsher 601adfc5217SJeff Kirsher return 0; 602adfc5217SJeff Kirsher } 603adfc5217SJeff Kirsher 60407ba6af4SMiriam Shitrit #define DUMP_ALL_PRESETS 0x1FFF 60507ba6af4SMiriam Shitrit #define DUMP_MAX_PRESETS 13 606adfc5217SJeff Kirsher 60707ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 608adfc5217SJeff Kirsher { 609adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 61007ba6af4SMiriam Shitrit return dump_num_registers[0][preset-1]; 611adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 61207ba6af4SMiriam Shitrit return dump_num_registers[1][preset-1]; 613adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 61407ba6af4SMiriam Shitrit return dump_num_registers[2][preset-1]; 615adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 61607ba6af4SMiriam Shitrit return dump_num_registers[3][preset-1]; 617adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 61807ba6af4SMiriam Shitrit return dump_num_registers[4][preset-1]; 619adfc5217SJeff Kirsher else 62007ba6af4SMiriam Shitrit return 0; 621adfc5217SJeff Kirsher } 622adfc5217SJeff Kirsher 62307ba6af4SMiriam Shitrit static int __bnx2x_get_regs_len(struct bnx2x *bp) 62407ba6af4SMiriam Shitrit { 62507ba6af4SMiriam Shitrit u32 preset_idx; 62607ba6af4SMiriam Shitrit int regdump_len = 0; 62707ba6af4SMiriam Shitrit 62807ba6af4SMiriam Shitrit /* Calculate the total preset regs length */ 62907ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 63007ba6af4SMiriam Shitrit regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 63107ba6af4SMiriam Shitrit 63207ba6af4SMiriam Shitrit return regdump_len; 63307ba6af4SMiriam Shitrit } 63407ba6af4SMiriam Shitrit 63507ba6af4SMiriam Shitrit static int bnx2x_get_regs_len(struct net_device *dev) 63607ba6af4SMiriam Shitrit { 63707ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 63807ba6af4SMiriam Shitrit int regdump_len = 0; 63907ba6af4SMiriam Shitrit 64075543741SYuval Mintz if (IS_VF(bp)) 64175543741SYuval Mintz return 0; 64275543741SYuval Mintz 64307ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_regs_len(bp); 64407ba6af4SMiriam Shitrit regdump_len *= 4; 64507ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 64607ba6af4SMiriam Shitrit 64707ba6af4SMiriam Shitrit return regdump_len; 64807ba6af4SMiriam Shitrit } 64907ba6af4SMiriam Shitrit 65007ba6af4SMiriam Shitrit #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 65107ba6af4SMiriam Shitrit #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 65207ba6af4SMiriam Shitrit #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 65307ba6af4SMiriam Shitrit #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 65407ba6af4SMiriam Shitrit #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 65507ba6af4SMiriam Shitrit 65607ba6af4SMiriam Shitrit #define IS_REG_IN_PRESET(presets, idx) \ 65707ba6af4SMiriam Shitrit ((presets & (1 << (idx-1))) == (1 << (idx-1))) 65807ba6af4SMiriam Shitrit 659adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 6601191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 661adfc5217SJeff Kirsher { 662adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 663adfc5217SJeff Kirsher return page_vals_e2; 664adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 665adfc5217SJeff Kirsher return page_vals_e3; 666adfc5217SJeff Kirsher else 667adfc5217SJeff Kirsher return NULL; 668adfc5217SJeff Kirsher } 669adfc5217SJeff Kirsher 6701191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 671adfc5217SJeff Kirsher { 672adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 673adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 674adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 675adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 676adfc5217SJeff Kirsher else 677adfc5217SJeff Kirsher return 0; 678adfc5217SJeff Kirsher } 679adfc5217SJeff Kirsher 6801191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 681adfc5217SJeff Kirsher { 682adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 683adfc5217SJeff Kirsher return page_write_regs_e2; 684adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 685adfc5217SJeff Kirsher return page_write_regs_e3; 686adfc5217SJeff Kirsher else 687adfc5217SJeff Kirsher return NULL; 688adfc5217SJeff Kirsher } 689adfc5217SJeff Kirsher 6901191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 691adfc5217SJeff Kirsher { 692adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 693adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 694adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 695adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 696adfc5217SJeff Kirsher else 697adfc5217SJeff Kirsher return 0; 698adfc5217SJeff Kirsher } 699adfc5217SJeff Kirsher 7001191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 701adfc5217SJeff Kirsher { 702adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 703adfc5217SJeff Kirsher return page_read_regs_e2; 704adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 705adfc5217SJeff Kirsher return page_read_regs_e3; 706adfc5217SJeff Kirsher else 707adfc5217SJeff Kirsher return NULL; 708adfc5217SJeff Kirsher } 709adfc5217SJeff Kirsher 7101191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 711adfc5217SJeff Kirsher { 712adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 713adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 714adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 715adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 716adfc5217SJeff Kirsher else 717adfc5217SJeff Kirsher return 0; 718adfc5217SJeff Kirsher } 719adfc5217SJeff Kirsher 72007ba6af4SMiriam Shitrit static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 72107ba6af4SMiriam Shitrit const struct reg_addr *reg_info) 722adfc5217SJeff Kirsher { 72307ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 72407ba6af4SMiriam Shitrit return IS_E1_REG(reg_info->chips); 72507ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 72607ba6af4SMiriam Shitrit return IS_E1H_REG(reg_info->chips); 72707ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 72807ba6af4SMiriam Shitrit return IS_E2_REG(reg_info->chips); 72907ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 73007ba6af4SMiriam Shitrit return IS_E3A0_REG(reg_info->chips); 73107ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 73207ba6af4SMiriam Shitrit return IS_E3B0_REG(reg_info->chips); 73307ba6af4SMiriam Shitrit else 73407ba6af4SMiriam Shitrit return false; 735adfc5217SJeff Kirsher } 736adfc5217SJeff Kirsher 73707ba6af4SMiriam Shitrit static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 73807ba6af4SMiriam Shitrit const struct wreg_addr *wreg_info) 739adfc5217SJeff Kirsher { 74007ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 74107ba6af4SMiriam Shitrit return IS_E1_REG(wreg_info->chips); 74207ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 74307ba6af4SMiriam Shitrit return IS_E1H_REG(wreg_info->chips); 74407ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 74507ba6af4SMiriam Shitrit return IS_E2_REG(wreg_info->chips); 74607ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 74707ba6af4SMiriam Shitrit return IS_E3A0_REG(wreg_info->chips); 74807ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 74907ba6af4SMiriam Shitrit return IS_E3B0_REG(wreg_info->chips); 75007ba6af4SMiriam Shitrit else 75107ba6af4SMiriam Shitrit return false; 752adfc5217SJeff Kirsher } 753adfc5217SJeff Kirsher 754adfc5217SJeff Kirsher /** 755adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 756adfc5217SJeff Kirsher * 757adfc5217SJeff Kirsher * @bp device handle 758adfc5217SJeff Kirsher * @p output buffer 759adfc5217SJeff Kirsher * 7602de67439SYuval Mintz * Reads "paged" memories: memories that may only be read by first writing to a 7612de67439SYuval Mintz * specific address ("write address") and then reading from a specific address 7622de67439SYuval Mintz * ("read address"). There may be more than one write address per "page" and 7632de67439SYuval Mintz * more than one read address per write address. 764adfc5217SJeff Kirsher */ 76507ba6af4SMiriam Shitrit static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 766adfc5217SJeff Kirsher { 767adfc5217SJeff Kirsher u32 i, j, k, n; 76807ba6af4SMiriam Shitrit 769adfc5217SJeff Kirsher /* addresses of the paged registers */ 770adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 771adfc5217SJeff Kirsher /* number of paged registers */ 772adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 773adfc5217SJeff Kirsher /* write addresses */ 774adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 775adfc5217SJeff Kirsher /* number of write addresses */ 776adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 777adfc5217SJeff Kirsher /* read addresses info */ 778adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 779adfc5217SJeff Kirsher /* number of read addresses */ 780adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 78107ba6af4SMiriam Shitrit u32 addr, size; 782adfc5217SJeff Kirsher 783adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 784adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 785adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 78607ba6af4SMiriam Shitrit 78707ba6af4SMiriam Shitrit for (k = 0; k < read_num; k++) { 78807ba6af4SMiriam Shitrit if (IS_REG_IN_PRESET(read_addr[k].presets, 78907ba6af4SMiriam Shitrit preset)) { 79007ba6af4SMiriam Shitrit size = read_addr[k].size; 79107ba6af4SMiriam Shitrit for (n = 0; n < size; n++) { 79207ba6af4SMiriam Shitrit addr = read_addr[k].addr + n*4; 79307ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr); 794adfc5217SJeff Kirsher } 795adfc5217SJeff Kirsher } 796adfc5217SJeff Kirsher } 79707ba6af4SMiriam Shitrit } 79807ba6af4SMiriam Shitrit } 79907ba6af4SMiriam Shitrit } 80007ba6af4SMiriam Shitrit 80107ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 80207ba6af4SMiriam Shitrit { 80307ba6af4SMiriam Shitrit u32 i, j, addr; 80407ba6af4SMiriam Shitrit const struct wreg_addr *wreg_addr_p = NULL; 80507ba6af4SMiriam Shitrit 80607ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 80707ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1; 80807ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 80907ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1h; 81007ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 81107ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e2; 81207ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 81307ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3; 81407ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 81507ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3b0; 81607ba6af4SMiriam Shitrit 81707ba6af4SMiriam Shitrit /* Read the idle_chk registers */ 81807ba6af4SMiriam Shitrit for (i = 0; i < IDLE_REGS_COUNT; i++) { 81907ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 82007ba6af4SMiriam Shitrit IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 82107ba6af4SMiriam Shitrit for (j = 0; j < idle_reg_addrs[i].size; j++) 82207ba6af4SMiriam Shitrit *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 82307ba6af4SMiriam Shitrit } 82407ba6af4SMiriam Shitrit } 82507ba6af4SMiriam Shitrit 82607ba6af4SMiriam Shitrit /* Read the regular registers */ 82707ba6af4SMiriam Shitrit for (i = 0; i < REGS_COUNT; i++) { 82807ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 82907ba6af4SMiriam Shitrit IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 83007ba6af4SMiriam Shitrit for (j = 0; j < reg_addrs[i].size; j++) 83107ba6af4SMiriam Shitrit *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 83207ba6af4SMiriam Shitrit } 83307ba6af4SMiriam Shitrit } 83407ba6af4SMiriam Shitrit 83507ba6af4SMiriam Shitrit /* Read the CAM registers */ 83607ba6af4SMiriam Shitrit if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 83707ba6af4SMiriam Shitrit IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 83807ba6af4SMiriam Shitrit for (i = 0; i < wreg_addr_p->size; i++) { 83907ba6af4SMiriam Shitrit *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 84007ba6af4SMiriam Shitrit 84107ba6af4SMiriam Shitrit /* In case of wreg_addr register, read additional 84207ba6af4SMiriam Shitrit registers from read_regs array 84307ba6af4SMiriam Shitrit */ 84407ba6af4SMiriam Shitrit for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 84507ba6af4SMiriam Shitrit addr = *(wreg_addr_p->read_regs); 84607ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr + j*4); 84707ba6af4SMiriam Shitrit } 84807ba6af4SMiriam Shitrit } 84907ba6af4SMiriam Shitrit } 85007ba6af4SMiriam Shitrit 85107ba6af4SMiriam Shitrit /* Paged registers are supported in E2 & E3 only */ 85207ba6af4SMiriam Shitrit if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 85316a5fd92SYuval Mintz /* Read "paged" registers */ 85407ba6af4SMiriam Shitrit bnx2x_read_pages_regs(bp, p, preset); 85507ba6af4SMiriam Shitrit } 85607ba6af4SMiriam Shitrit 85707ba6af4SMiriam Shitrit return 0; 85807ba6af4SMiriam Shitrit } 859adfc5217SJeff Kirsher 8601191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 861adfc5217SJeff Kirsher { 86207ba6af4SMiriam Shitrit u32 preset_idx; 863adfc5217SJeff Kirsher 86407ba6af4SMiriam Shitrit /* Read all registers, by reading all preset registers */ 86507ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 86607ba6af4SMiriam Shitrit /* Skip presets with IOR */ 86707ba6af4SMiriam Shitrit if ((preset_idx == 2) || 86807ba6af4SMiriam Shitrit (preset_idx == 5) || 86907ba6af4SMiriam Shitrit (preset_idx == 8) || 87007ba6af4SMiriam Shitrit (preset_idx == 11)) 87107ba6af4SMiriam Shitrit continue; 87207ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, preset_idx); 87307ba6af4SMiriam Shitrit p += __bnx2x_get_preset_regs_len(bp, preset_idx); 87407ba6af4SMiriam Shitrit } 875adfc5217SJeff Kirsher } 876adfc5217SJeff Kirsher 877adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 878adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 879adfc5217SJeff Kirsher { 880adfc5217SJeff Kirsher u32 *p = _p; 881adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 88207ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 883adfc5217SJeff Kirsher 88407ba6af4SMiriam Shitrit regs->version = 2; 885adfc5217SJeff Kirsher memset(p, 0, regs->len); 886adfc5217SJeff Kirsher 887adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 888adfc5217SJeff Kirsher return; 889adfc5217SJeff Kirsher 890adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 891adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 892adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 893adfc5217SJeff Kirsher */ 89407ba6af4SMiriam Shitrit 895adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 896adfc5217SJeff Kirsher 89707ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 89807ba6af4SMiriam Shitrit dump_hdr.preset = DUMP_ALL_PRESETS; 89907ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 90007ba6af4SMiriam Shitrit 90107ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 90207ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 90307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 90407ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 90507ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 90607ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 90707ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 90807ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 90907ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 91007ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 91107ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 91207ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 91307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 91407ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 91507ba6af4SMiriam Shitrit } 91607ba6af4SMiriam Shitrit 91707ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 91807ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 919adfc5217SJeff Kirsher 920adfc5217SJeff Kirsher /* Actually read the registers */ 921adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 922adfc5217SJeff Kirsher 9234293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 924adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 925adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 92607ba6af4SMiriam Shitrit } 92707ba6af4SMiriam Shitrit 92807ba6af4SMiriam Shitrit static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 92907ba6af4SMiriam Shitrit { 93007ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 93107ba6af4SMiriam Shitrit int regdump_len = 0; 93207ba6af4SMiriam Shitrit 93307ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 93407ba6af4SMiriam Shitrit regdump_len *= 4; 93507ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 93607ba6af4SMiriam Shitrit 93707ba6af4SMiriam Shitrit return regdump_len; 93807ba6af4SMiriam Shitrit } 93907ba6af4SMiriam Shitrit 94007ba6af4SMiriam Shitrit static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 94107ba6af4SMiriam Shitrit { 94207ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 94307ba6af4SMiriam Shitrit 94407ba6af4SMiriam Shitrit /* Use the ethtool_dump "flag" field as the dump preset index */ 9455bb680d6SMichal Schmidt if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 9465bb680d6SMichal Schmidt return -EINVAL; 9475bb680d6SMichal Schmidt 94807ba6af4SMiriam Shitrit bp->dump_preset_idx = val->flag; 94907ba6af4SMiriam Shitrit return 0; 95007ba6af4SMiriam Shitrit } 95107ba6af4SMiriam Shitrit 95207ba6af4SMiriam Shitrit static int bnx2x_get_dump_flag(struct net_device *dev, 95307ba6af4SMiriam Shitrit struct ethtool_dump *dump) 95407ba6af4SMiriam Shitrit { 95507ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 95607ba6af4SMiriam Shitrit 9578cc2d927SMichal Schmidt dump->version = BNX2X_DUMP_VERSION; 9588cc2d927SMichal Schmidt dump->flag = bp->dump_preset_idx; 95907ba6af4SMiriam Shitrit /* Calculate the requested preset idx length */ 96007ba6af4SMiriam Shitrit dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 96107ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 96207ba6af4SMiriam Shitrit bp->dump_preset_idx, dump->len); 96307ba6af4SMiriam Shitrit return 0; 96407ba6af4SMiriam Shitrit } 96507ba6af4SMiriam Shitrit 96607ba6af4SMiriam Shitrit static int bnx2x_get_dump_data(struct net_device *dev, 96707ba6af4SMiriam Shitrit struct ethtool_dump *dump, 96807ba6af4SMiriam Shitrit void *buffer) 96907ba6af4SMiriam Shitrit { 97007ba6af4SMiriam Shitrit u32 *p = buffer; 97107ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 97207ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 97307ba6af4SMiriam Shitrit 97407ba6af4SMiriam Shitrit /* Disable parity attentions as long as following dump may 97507ba6af4SMiriam Shitrit * cause false alarms by reading never written registers. We 97607ba6af4SMiriam Shitrit * will re-enable parity attentions right after the dump. 97707ba6af4SMiriam Shitrit */ 97807ba6af4SMiriam Shitrit 97907ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 98007ba6af4SMiriam Shitrit 98107ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 98207ba6af4SMiriam Shitrit dump_hdr.preset = bp->dump_preset_idx; 98307ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 98407ba6af4SMiriam Shitrit 98507ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 98607ba6af4SMiriam Shitrit 98707ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 98807ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 98907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 99007ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 99107ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 99207ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 99307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 99407ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 99507ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 99607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 99707ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 99807ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 99907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 100007ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 100107ba6af4SMiriam Shitrit } 100207ba6af4SMiriam Shitrit 100307ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 100407ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 100507ba6af4SMiriam Shitrit 100607ba6af4SMiriam Shitrit /* Actually read the registers */ 100707ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 100807ba6af4SMiriam Shitrit 10094293b9f5SDmitry Kravkov /* Re-enable parity attentions */ 101007ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 101107ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 101207ba6af4SMiriam Shitrit 101307ba6af4SMiriam Shitrit return 0; 1014adfc5217SJeff Kirsher } 1015adfc5217SJeff Kirsher 1016adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 1017adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 1018adfc5217SJeff Kirsher { 1019adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1020adfc5217SJeff Kirsher 102168aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 102268aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1023adfc5217SJeff Kirsher 10248ca5e17eSAriel Elior bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 10258ca5e17eSAriel Elior 102668aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1027adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 1028cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 1029adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 1030adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 1031adfc5217SJeff Kirsher } 1032adfc5217SJeff Kirsher 1033adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1034adfc5217SJeff Kirsher { 1035adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1036adfc5217SJeff Kirsher 1037adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 1038adfc5217SJeff Kirsher wol->supported = 0; 1039adfc5217SJeff Kirsher wol->wolopts = 0; 1040adfc5217SJeff Kirsher } else { 1041adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 1042adfc5217SJeff Kirsher if (bp->wol) 1043adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 1044adfc5217SJeff Kirsher else 1045adfc5217SJeff Kirsher wol->wolopts = 0; 1046adfc5217SJeff Kirsher } 1047adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 1048adfc5217SJeff Kirsher } 1049adfc5217SJeff Kirsher 1050adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1051adfc5217SJeff Kirsher { 1052adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1053adfc5217SJeff Kirsher 105451c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 10552de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1056adfc5217SJeff Kirsher return -EINVAL; 105751c1a580SMerav Sicron } 1058adfc5217SJeff Kirsher 1059adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 106051c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 10612de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1062adfc5217SJeff Kirsher return -EINVAL; 106351c1a580SMerav Sicron } 1064adfc5217SJeff Kirsher bp->wol = 1; 1065adfc5217SJeff Kirsher } else 1066adfc5217SJeff Kirsher bp->wol = 0; 1067adfc5217SJeff Kirsher 1068adfc5217SJeff Kirsher return 0; 1069adfc5217SJeff Kirsher } 1070adfc5217SJeff Kirsher 1071adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 1072adfc5217SJeff Kirsher { 1073adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1074adfc5217SJeff Kirsher 1075adfc5217SJeff Kirsher return bp->msg_enable; 1076adfc5217SJeff Kirsher } 1077adfc5217SJeff Kirsher 1078adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1079adfc5217SJeff Kirsher { 1080adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1081adfc5217SJeff Kirsher 1082adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 1083adfc5217SJeff Kirsher /* dump MCP trace */ 1084ad5afc89SAriel Elior if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1085adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 1086adfc5217SJeff Kirsher bp->msg_enable = level; 1087adfc5217SJeff Kirsher } 1088adfc5217SJeff Kirsher } 1089adfc5217SJeff Kirsher 1090adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 1091adfc5217SJeff Kirsher { 1092adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1093adfc5217SJeff Kirsher 1094adfc5217SJeff Kirsher if (!bp->port.pmf) 1095adfc5217SJeff Kirsher return 0; 1096adfc5217SJeff Kirsher 1097adfc5217SJeff Kirsher if (netif_running(dev)) { 1098adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 10995d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1100adfc5217SJeff Kirsher bnx2x_link_set(bp); 1101adfc5217SJeff Kirsher } 1102adfc5217SJeff Kirsher 1103adfc5217SJeff Kirsher return 0; 1104adfc5217SJeff Kirsher } 1105adfc5217SJeff Kirsher 1106adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 1107adfc5217SJeff Kirsher { 1108adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1109adfc5217SJeff Kirsher 1110adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1111adfc5217SJeff Kirsher return 0; 1112adfc5217SJeff Kirsher 1113adfc5217SJeff Kirsher return bp->link_vars.link_up; 1114adfc5217SJeff Kirsher } 1115adfc5217SJeff Kirsher 1116adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 1117adfc5217SJeff Kirsher { 1118adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1119adfc5217SJeff Kirsher 1120adfc5217SJeff Kirsher return bp->common.flash_size; 1121adfc5217SJeff Kirsher } 1122adfc5217SJeff Kirsher 112316a5fd92SYuval Mintz /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 112416a5fd92SYuval Mintz * had we done things the other way around, if two pfs from the same port would 1125f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 1126f16da43bSAriel Elior * as: 1127f16da43bSAriel Elior * pf A takes the port lock. 1128f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 1129f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 1130f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 1131f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 1132f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 1133f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 11342de67439SYuval Mintz * access corrupted by pf B) 1135f16da43bSAriel Elior */ 1136adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1137adfc5217SJeff Kirsher { 1138adfc5217SJeff Kirsher int port = BP_PORT(bp); 1139adfc5217SJeff Kirsher int count, i; 1140f16da43bSAriel Elior u32 val; 1141f16da43bSAriel Elior 1142f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1143f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1144adfc5217SJeff Kirsher 1145adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1146adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1147adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1148adfc5217SJeff Kirsher count *= 100; 1149adfc5217SJeff Kirsher 1150adfc5217SJeff Kirsher /* request access to nvram interface */ 1151adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1152adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1153adfc5217SJeff Kirsher 1154adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1155adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1156adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1157adfc5217SJeff Kirsher break; 1158adfc5217SJeff Kirsher 1159adfc5217SJeff Kirsher udelay(5); 1160adfc5217SJeff Kirsher } 1161adfc5217SJeff Kirsher 1162adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 116351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 116451c1a580SMerav Sicron "cannot get access to nvram interface\n"); 1165adfc5217SJeff Kirsher return -EBUSY; 1166adfc5217SJeff Kirsher } 1167adfc5217SJeff Kirsher 1168adfc5217SJeff Kirsher return 0; 1169adfc5217SJeff Kirsher } 1170adfc5217SJeff Kirsher 1171adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1172adfc5217SJeff Kirsher { 1173adfc5217SJeff Kirsher int port = BP_PORT(bp); 1174adfc5217SJeff Kirsher int count, i; 1175f16da43bSAriel Elior u32 val; 1176adfc5217SJeff Kirsher 1177adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1178adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1179adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1180adfc5217SJeff Kirsher count *= 100; 1181adfc5217SJeff Kirsher 1182adfc5217SJeff Kirsher /* relinquish nvram interface */ 1183adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1184adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1185adfc5217SJeff Kirsher 1186adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1187adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1188adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1189adfc5217SJeff Kirsher break; 1190adfc5217SJeff Kirsher 1191adfc5217SJeff Kirsher udelay(5); 1192adfc5217SJeff Kirsher } 1193adfc5217SJeff Kirsher 1194adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 119551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 119651c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1197adfc5217SJeff Kirsher return -EBUSY; 1198adfc5217SJeff Kirsher } 1199adfc5217SJeff Kirsher 1200f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1201f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1202adfc5217SJeff Kirsher return 0; 1203adfc5217SJeff Kirsher } 1204adfc5217SJeff Kirsher 1205adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1206adfc5217SJeff Kirsher { 1207adfc5217SJeff Kirsher u32 val; 1208adfc5217SJeff Kirsher 1209adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1210adfc5217SJeff Kirsher 1211adfc5217SJeff Kirsher /* enable both bits, even on read */ 1212adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1213adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1214adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1215adfc5217SJeff Kirsher } 1216adfc5217SJeff Kirsher 1217adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1218adfc5217SJeff Kirsher { 1219adfc5217SJeff Kirsher u32 val; 1220adfc5217SJeff Kirsher 1221adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1222adfc5217SJeff Kirsher 1223adfc5217SJeff Kirsher /* disable both bits, even after read */ 1224adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1225adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1226adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1227adfc5217SJeff Kirsher } 1228adfc5217SJeff Kirsher 1229adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1230adfc5217SJeff Kirsher u32 cmd_flags) 1231adfc5217SJeff Kirsher { 1232adfc5217SJeff Kirsher int count, i, rc; 1233adfc5217SJeff Kirsher u32 val; 1234adfc5217SJeff Kirsher 1235adfc5217SJeff Kirsher /* build the command word */ 1236adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1237adfc5217SJeff Kirsher 1238adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1239adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1240adfc5217SJeff Kirsher 1241adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1242adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1243adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1244adfc5217SJeff Kirsher 1245adfc5217SJeff Kirsher /* issue a read command */ 1246adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1247adfc5217SJeff Kirsher 1248adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1249adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1250adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1251adfc5217SJeff Kirsher count *= 100; 1252adfc5217SJeff Kirsher 1253adfc5217SJeff Kirsher /* wait for completion */ 1254adfc5217SJeff Kirsher *ret_val = 0; 1255adfc5217SJeff Kirsher rc = -EBUSY; 1256adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1257adfc5217SJeff Kirsher udelay(5); 1258adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1259adfc5217SJeff Kirsher 1260adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1261adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1262adfc5217SJeff Kirsher /* we read nvram data in cpu order 1263adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 126407ba6af4SMiriam Shitrit * converting to big-endian will do the work 126507ba6af4SMiriam Shitrit */ 1266adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1267adfc5217SJeff Kirsher rc = 0; 1268adfc5217SJeff Kirsher break; 1269adfc5217SJeff Kirsher } 1270adfc5217SJeff Kirsher } 127151c1a580SMerav Sicron if (rc == -EBUSY) 127251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 127351c1a580SMerav Sicron "nvram read timeout expired\n"); 1274adfc5217SJeff Kirsher return rc; 1275adfc5217SJeff Kirsher } 1276adfc5217SJeff Kirsher 1277adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1278adfc5217SJeff Kirsher int buf_size) 1279adfc5217SJeff Kirsher { 1280adfc5217SJeff Kirsher int rc; 1281adfc5217SJeff Kirsher u32 cmd_flags; 1282adfc5217SJeff Kirsher __be32 val; 1283adfc5217SJeff Kirsher 1284adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 128551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1286adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1287adfc5217SJeff Kirsher offset, buf_size); 1288adfc5217SJeff Kirsher return -EINVAL; 1289adfc5217SJeff Kirsher } 1290adfc5217SJeff Kirsher 1291adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 129251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 129351c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1294adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1295adfc5217SJeff Kirsher return -EINVAL; 1296adfc5217SJeff Kirsher } 1297adfc5217SJeff Kirsher 1298adfc5217SJeff Kirsher /* request access to nvram interface */ 1299adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1300adfc5217SJeff Kirsher if (rc) 1301adfc5217SJeff Kirsher return rc; 1302adfc5217SJeff Kirsher 1303adfc5217SJeff Kirsher /* enable access to nvram interface */ 1304adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1305adfc5217SJeff Kirsher 1306adfc5217SJeff Kirsher /* read the first word(s) */ 1307adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1308adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1309adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1310adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1311adfc5217SJeff Kirsher 1312adfc5217SJeff Kirsher /* advance to the next dword */ 1313adfc5217SJeff Kirsher offset += sizeof(u32); 1314adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1315adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1316adfc5217SJeff Kirsher cmd_flags = 0; 1317adfc5217SJeff Kirsher } 1318adfc5217SJeff Kirsher 1319adfc5217SJeff Kirsher if (rc == 0) { 1320adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1321adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1322adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1323adfc5217SJeff Kirsher } 1324adfc5217SJeff Kirsher 1325adfc5217SJeff Kirsher /* disable access to nvram interface */ 1326adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1327adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1328adfc5217SJeff Kirsher 1329adfc5217SJeff Kirsher return rc; 1330adfc5217SJeff Kirsher } 1331adfc5217SJeff Kirsher 133285640952SDmitry Kravkov static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 133385640952SDmitry Kravkov int buf_size) 133485640952SDmitry Kravkov { 133585640952SDmitry Kravkov int rc; 133685640952SDmitry Kravkov 133785640952SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 133885640952SDmitry Kravkov 133985640952SDmitry Kravkov if (!rc) { 134085640952SDmitry Kravkov __be32 *be = (__be32 *)buf; 134185640952SDmitry Kravkov 134285640952SDmitry Kravkov while ((buf_size -= 4) >= 0) 134385640952SDmitry Kravkov *buf++ = be32_to_cpu(*be++); 134485640952SDmitry Kravkov } 134585640952SDmitry Kravkov 134685640952SDmitry Kravkov return rc; 134785640952SDmitry Kravkov } 134885640952SDmitry Kravkov 13493fb43eb2SYuval Mintz static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 13503fb43eb2SYuval Mintz { 13513fb43eb2SYuval Mintz int rc = 1; 13523fb43eb2SYuval Mintz u16 pm = 0; 13533fb43eb2SYuval Mintz struct net_device *dev = pci_get_drvdata(bp->pdev); 13543fb43eb2SYuval Mintz 135529ed74c3SJon Mason if (bp->pdev->pm_cap) 13563fb43eb2SYuval Mintz rc = pci_read_config_word(bp->pdev, 135729ed74c3SJon Mason bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 13583fb43eb2SYuval Mintz 1359829a5071SYuval Mintz if ((rc && !netif_running(dev)) || 1360c957d09fSYuval Mintz (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 13613fb43eb2SYuval Mintz return false; 13623fb43eb2SYuval Mintz 13633fb43eb2SYuval Mintz return true; 13643fb43eb2SYuval Mintz } 13653fb43eb2SYuval Mintz 1366adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1367adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1368adfc5217SJeff Kirsher { 1369adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1370adfc5217SJeff Kirsher 13713fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 137251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 137351c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1374adfc5217SJeff Kirsher return -EAGAIN; 137551c1a580SMerav Sicron } 1376adfc5217SJeff Kirsher 137751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1378f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1379adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1380adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1381adfc5217SJeff Kirsher 1382adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1383adfc5217SJeff Kirsher 1384f1691dc6SDmitry Kravkov return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1385adfc5217SJeff Kirsher } 1386adfc5217SJeff Kirsher 138724ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 138824ea818eSYuval Mintz struct ethtool_eeprom *ee, 138924ea818eSYuval Mintz u8 *data) 139024ea818eSYuval Mintz { 139124ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1392669d6996SYaniv Rosner int rc = -EINVAL, phy_idx; 139324ea818eSYuval Mintz u8 *user_data = data; 1394669d6996SYaniv Rosner unsigned int start_addr = ee->offset, xfer_size = 0; 139524ea818eSYuval Mintz 13963fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 139724ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 139824ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 139924ea818eSYuval Mintz return -EAGAIN; 140024ea818eSYuval Mintz } 140124ea818eSYuval Mintz 140224ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1403669d6996SYaniv Rosner 1404669d6996SYaniv Rosner /* Read A0 section */ 1405669d6996SYaniv Rosner if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1406669d6996SYaniv Rosner /* Limit transfer size to the A0 section boundary */ 1407669d6996SYaniv Rosner if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1408669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1409669d6996SYaniv Rosner else 1410669d6996SYaniv Rosner xfer_size = ee->len; 141124ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 141224ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 141324ea818eSYuval Mintz &bp->link_params, 1414669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1415669d6996SYaniv Rosner start_addr, 141624ea818eSYuval Mintz xfer_size, 141724ea818eSYuval Mintz user_data); 1418669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1419669d6996SYaniv Rosner if (rc) { 1420669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1421669d6996SYaniv Rosner 1422669d6996SYaniv Rosner return -EINVAL; 1423669d6996SYaniv Rosner } 142424ea818eSYuval Mintz user_data += xfer_size; 1425669d6996SYaniv Rosner start_addr += xfer_size; 142624ea818eSYuval Mintz } 142724ea818eSYuval Mintz 1428669d6996SYaniv Rosner /* Read A2 section */ 1429669d6996SYaniv Rosner if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1430669d6996SYaniv Rosner (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1431669d6996SYaniv Rosner xfer_size = ee->len - xfer_size; 1432669d6996SYaniv Rosner /* Limit transfer size to the A2 section boundary */ 1433669d6996SYaniv Rosner if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1434669d6996SYaniv Rosner xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1435669d6996SYaniv Rosner start_addr -= ETH_MODULE_SFF_8079_LEN; 1436669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1437669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1438669d6996SYaniv Rosner &bp->link_params, 1439669d6996SYaniv Rosner I2C_DEV_ADDR_A2, 1440669d6996SYaniv Rosner start_addr, 1441669d6996SYaniv Rosner xfer_size, 1442669d6996SYaniv Rosner user_data); 144324ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 1444669d6996SYaniv Rosner if (rc) { 1445669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1446669d6996SYaniv Rosner return -EINVAL; 1447669d6996SYaniv Rosner } 1448669d6996SYaniv Rosner } 144924ea818eSYuval Mintz return rc; 145024ea818eSYuval Mintz } 145124ea818eSYuval Mintz 145224ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 145324ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 145424ea818eSYuval Mintz { 145524ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1456669d6996SYaniv Rosner int phy_idx, rc; 1457669d6996SYaniv Rosner u8 sff8472_comp, diag_type; 1458669d6996SYaniv Rosner 14593fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 146024ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 146124ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 146224ea818eSYuval Mintz return -EAGAIN; 146324ea818eSYuval Mintz } 146424ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 1465669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1466669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1467669d6996SYaniv Rosner &bp->link_params, 1468669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1469669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_ADDR, 1470669d6996SYaniv Rosner SFP_EEPROM_SFF_8472_COMP_SIZE, 1471669d6996SYaniv Rosner &sff8472_comp); 1472669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1473669d6996SYaniv Rosner if (rc) { 1474669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1475669d6996SYaniv Rosner return -EINVAL; 1476669d6996SYaniv Rosner } 1477669d6996SYaniv Rosner 1478669d6996SYaniv Rosner bnx2x_acquire_phy_lock(bp); 1479669d6996SYaniv Rosner rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1480669d6996SYaniv Rosner &bp->link_params, 1481669d6996SYaniv Rosner I2C_DEV_ADDR_A0, 1482669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_ADDR, 1483669d6996SYaniv Rosner SFP_EEPROM_DIAG_TYPE_SIZE, 1484669d6996SYaniv Rosner &diag_type); 1485669d6996SYaniv Rosner bnx2x_release_phy_lock(bp); 1486669d6996SYaniv Rosner if (rc) { 1487669d6996SYaniv Rosner DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1488669d6996SYaniv Rosner return -EINVAL; 1489669d6996SYaniv Rosner } 1490669d6996SYaniv Rosner 1491669d6996SYaniv Rosner if (!sff8472_comp || 1492669d6996SYaniv Rosner (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 149324ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 149424ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1495669d6996SYaniv Rosner } else { 1496669d6996SYaniv Rosner modinfo->type = ETH_MODULE_SFF_8472; 1497669d6996SYaniv Rosner modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 149824ea818eSYuval Mintz } 1499669d6996SYaniv Rosner return 0; 150024ea818eSYuval Mintz } 150124ea818eSYuval Mintz 1502adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1503adfc5217SJeff Kirsher u32 cmd_flags) 1504adfc5217SJeff Kirsher { 1505adfc5217SJeff Kirsher int count, i, rc; 1506adfc5217SJeff Kirsher 1507adfc5217SJeff Kirsher /* build the command word */ 1508adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1509adfc5217SJeff Kirsher 1510adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1511adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1512adfc5217SJeff Kirsher 1513adfc5217SJeff Kirsher /* write the data */ 1514adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1515adfc5217SJeff Kirsher 1516adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1517adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1518adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1519adfc5217SJeff Kirsher 1520adfc5217SJeff Kirsher /* issue the write command */ 1521adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1522adfc5217SJeff Kirsher 1523adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1524adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1525adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1526adfc5217SJeff Kirsher count *= 100; 1527adfc5217SJeff Kirsher 1528adfc5217SJeff Kirsher /* wait for completion */ 1529adfc5217SJeff Kirsher rc = -EBUSY; 1530adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1531adfc5217SJeff Kirsher udelay(5); 1532adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1533adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1534adfc5217SJeff Kirsher rc = 0; 1535adfc5217SJeff Kirsher break; 1536adfc5217SJeff Kirsher } 1537adfc5217SJeff Kirsher } 1538adfc5217SJeff Kirsher 153951c1a580SMerav Sicron if (rc == -EBUSY) 154051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 154151c1a580SMerav Sicron "nvram write timeout expired\n"); 1542adfc5217SJeff Kirsher return rc; 1543adfc5217SJeff Kirsher } 1544adfc5217SJeff Kirsher 1545adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1546adfc5217SJeff Kirsher 1547adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1548adfc5217SJeff Kirsher int buf_size) 1549adfc5217SJeff Kirsher { 1550adfc5217SJeff Kirsher int rc; 155130c20b67SDmitry Kravkov u32 cmd_flags, align_offset, val; 155230c20b67SDmitry Kravkov __be32 val_be; 1553adfc5217SJeff Kirsher 1554adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 155551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 155651c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1557adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1558adfc5217SJeff Kirsher return -EINVAL; 1559adfc5217SJeff Kirsher } 1560adfc5217SJeff Kirsher 1561adfc5217SJeff Kirsher /* request access to nvram interface */ 1562adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1563adfc5217SJeff Kirsher if (rc) 1564adfc5217SJeff Kirsher return rc; 1565adfc5217SJeff Kirsher 1566adfc5217SJeff Kirsher /* enable access to nvram interface */ 1567adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1568adfc5217SJeff Kirsher 1569adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1570adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 157130c20b67SDmitry Kravkov rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1572adfc5217SJeff Kirsher 1573adfc5217SJeff Kirsher if (rc == 0) { 1574adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 157507ba6af4SMiriam Shitrit * convert it back to cpu order 157607ba6af4SMiriam Shitrit */ 157730c20b67SDmitry Kravkov val = be32_to_cpu(val_be); 157830c20b67SDmitry Kravkov 1579c957d09fSYuval Mintz val &= ~le32_to_cpu((__force __le32) 1580c957d09fSYuval Mintz (0xff << BYTE_OFFSET(offset))); 1581c957d09fSYuval Mintz val |= le32_to_cpu((__force __le32) 1582c957d09fSYuval Mintz (*data_buf << BYTE_OFFSET(offset))); 1583adfc5217SJeff Kirsher 1584adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1585adfc5217SJeff Kirsher cmd_flags); 1586adfc5217SJeff Kirsher } 1587adfc5217SJeff Kirsher 1588adfc5217SJeff Kirsher /* disable access to nvram interface */ 1589adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1590adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1591adfc5217SJeff Kirsher 1592adfc5217SJeff Kirsher return rc; 1593adfc5217SJeff Kirsher } 1594adfc5217SJeff Kirsher 1595adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1596adfc5217SJeff Kirsher int buf_size) 1597adfc5217SJeff Kirsher { 1598adfc5217SJeff Kirsher int rc; 1599adfc5217SJeff Kirsher u32 cmd_flags; 1600adfc5217SJeff Kirsher u32 val; 1601adfc5217SJeff Kirsher u32 written_so_far; 1602adfc5217SJeff Kirsher 1603adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1604adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1605adfc5217SJeff Kirsher 1606adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 160751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1608adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1609adfc5217SJeff Kirsher offset, buf_size); 1610adfc5217SJeff Kirsher return -EINVAL; 1611adfc5217SJeff Kirsher } 1612adfc5217SJeff Kirsher 1613adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 161451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 161551c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1616adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1617adfc5217SJeff Kirsher return -EINVAL; 1618adfc5217SJeff Kirsher } 1619adfc5217SJeff Kirsher 1620adfc5217SJeff Kirsher /* request access to nvram interface */ 1621adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1622adfc5217SJeff Kirsher if (rc) 1623adfc5217SJeff Kirsher return rc; 1624adfc5217SJeff Kirsher 1625adfc5217SJeff Kirsher /* enable access to nvram interface */ 1626adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1627adfc5217SJeff Kirsher 1628adfc5217SJeff Kirsher written_so_far = 0; 1629adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1630adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1631adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1632adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1633adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1634adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1635adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1636adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1637adfc5217SJeff Kirsher 1638adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1639adfc5217SJeff Kirsher 164068bf5a10SYuval Mintz /* Notice unlike bnx2x_nvram_read_dword() this will not 164168bf5a10SYuval Mintz * change val using be32_to_cpu(), which causes data to flip 164268bf5a10SYuval Mintz * if the eeprom is read and then written back. This is due 164368bf5a10SYuval Mintz * to tools utilizing this functionality that would break 164468bf5a10SYuval Mintz * if this would be resolved. 164568bf5a10SYuval Mintz */ 1646adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1647adfc5217SJeff Kirsher 1648adfc5217SJeff Kirsher /* advance to the next dword */ 1649adfc5217SJeff Kirsher offset += sizeof(u32); 1650adfc5217SJeff Kirsher data_buf += sizeof(u32); 1651adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1652adfc5217SJeff Kirsher cmd_flags = 0; 1653adfc5217SJeff Kirsher } 1654adfc5217SJeff Kirsher 1655adfc5217SJeff Kirsher /* disable access to nvram interface */ 1656adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1657adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1658adfc5217SJeff Kirsher 1659adfc5217SJeff Kirsher return rc; 1660adfc5217SJeff Kirsher } 1661adfc5217SJeff Kirsher 1662adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1663adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1664adfc5217SJeff Kirsher { 1665adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1666adfc5217SJeff Kirsher int port = BP_PORT(bp); 1667adfc5217SJeff Kirsher int rc = 0; 1668adfc5217SJeff Kirsher u32 ext_phy_config; 16693fb43eb2SYuval Mintz 16703fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 167151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 167251c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1673adfc5217SJeff Kirsher return -EAGAIN; 167451c1a580SMerav Sicron } 1675adfc5217SJeff Kirsher 167651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1677f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1678adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1679adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1680adfc5217SJeff Kirsher 1681adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1682adfc5217SJeff Kirsher 1683adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1684adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 168551c1a580SMerav Sicron !bp->port.pmf) { 168651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 168751c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1688adfc5217SJeff Kirsher return -EINVAL; 168951c1a580SMerav Sicron } 1690adfc5217SJeff Kirsher 1691adfc5217SJeff Kirsher ext_phy_config = 1692adfc5217SJeff Kirsher SHMEM_RD(bp, 1693adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1694adfc5217SJeff Kirsher 1695adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1696adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1697adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1698adfc5217SJeff Kirsher 1699adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1700adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1701adfc5217SJeff Kirsher &bp->link_vars, 0); 1702adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1703adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1704adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1705adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1706adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1707adfc5217SJeff Kirsher bnx2x_link_report(bp); 1708adfc5217SJeff Kirsher 1709adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1710adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1711adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1712adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1713adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1714adfc5217SJeff Kirsher &bp->link_vars, 1); 1715adfc5217SJeff Kirsher 1716adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1717adfc5217SJeff Kirsher &bp->link_vars); 1718adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1719adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1720adfc5217SJeff Kirsher } 1721adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1722adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1723adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1724adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1725adfc5217SJeff Kirsher 1726adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1727adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1728adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1729adfc5217SJeff Kirsher 1730adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1731adfc5217SJeff Kirsher 1732adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1733adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1734adfc5217SJeff Kirsher 1735adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1736adfc5217SJeff Kirsher msleep(500); 1737adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1738adfc5217SJeff Kirsher msleep(500); 1739adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1740adfc5217SJeff Kirsher } 1741adfc5217SJeff Kirsher } else 1742adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1743adfc5217SJeff Kirsher 1744adfc5217SJeff Kirsher return rc; 1745adfc5217SJeff Kirsher } 1746adfc5217SJeff Kirsher 1747adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1748adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1749adfc5217SJeff Kirsher { 1750adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1751adfc5217SJeff Kirsher 1752adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1753adfc5217SJeff Kirsher 1754adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1755adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1756adfc5217SJeff Kirsher 1757adfc5217SJeff Kirsher return 0; 1758adfc5217SJeff Kirsher } 1759adfc5217SJeff Kirsher 1760adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1761adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1762adfc5217SJeff Kirsher { 1763adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1764adfc5217SJeff Kirsher 1765adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1766adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1767adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1768adfc5217SJeff Kirsher 1769adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1770adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1771adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1772adfc5217SJeff Kirsher 1773adfc5217SJeff Kirsher if (netif_running(dev)) 1774adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1775adfc5217SJeff Kirsher 1776adfc5217SJeff Kirsher return 0; 1777adfc5217SJeff Kirsher } 1778adfc5217SJeff Kirsher 1779adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1780adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1781adfc5217SJeff Kirsher { 1782adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1783adfc5217SJeff Kirsher 1784adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1785adfc5217SJeff Kirsher 1786adfc5217SJeff Kirsher if (bp->rx_ring_size) 1787adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1788adfc5217SJeff Kirsher else 1789adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1790adfc5217SJeff Kirsher 1791a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1792adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1793adfc5217SJeff Kirsher } 1794adfc5217SJeff Kirsher 1795adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1796adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1797adfc5217SJeff Kirsher { 1798adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1799adfc5217SJeff Kirsher 180004c46736SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 180104c46736SYuval Mintz "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 180204c46736SYuval Mintz ering->rx_pending, ering->tx_pending); 180304c46736SYuval Mintz 1804adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 180551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 180651c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1807adfc5217SJeff Kirsher return -EAGAIN; 1808adfc5217SJeff Kirsher } 1809adfc5217SJeff Kirsher 1810adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1811adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1812adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1813a3348722SBarak Witkowski (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 181451c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 181551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1816adfc5217SJeff Kirsher return -EINVAL; 181751c1a580SMerav Sicron } 1818adfc5217SJeff Kirsher 1819adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1820adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1821adfc5217SJeff Kirsher 1822adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1823adfc5217SJeff Kirsher } 1824adfc5217SJeff Kirsher 1825adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1826adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1827adfc5217SJeff Kirsher { 1828adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1829adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 18309e7e8399SMintz Yuval int cfg_reg; 18319e7e8399SMintz Yuval 1832adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1833adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1834adfc5217SJeff Kirsher 18359e7e8399SMintz Yuval if (!epause->autoneg) 1836241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 18379e7e8399SMintz Yuval else 18389e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 18399e7e8399SMintz Yuval 18409e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1841adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 18429e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1843adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1844adfc5217SJeff Kirsher 184551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1846f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1847adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1848adfc5217SJeff Kirsher } 1849adfc5217SJeff Kirsher 1850adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1851adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1852adfc5217SJeff Kirsher { 1853adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1854adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1855adfc5217SJeff Kirsher if (IS_MF(bp)) 1856adfc5217SJeff Kirsher return 0; 1857adfc5217SJeff Kirsher 185851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1859f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1860adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1861adfc5217SJeff Kirsher 1862adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1863adfc5217SJeff Kirsher 1864adfc5217SJeff Kirsher if (epause->rx_pause) 1865adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1866adfc5217SJeff Kirsher 1867adfc5217SJeff Kirsher if (epause->tx_pause) 1868adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1869adfc5217SJeff Kirsher 1870adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1871adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1872adfc5217SJeff Kirsher 1873adfc5217SJeff Kirsher if (epause->autoneg) { 1874adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 187551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1876adfc5217SJeff Kirsher return -EINVAL; 1877adfc5217SJeff Kirsher } 1878adfc5217SJeff Kirsher 1879adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1880adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1881adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1882adfc5217SJeff Kirsher } 1883ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv = 0; 18845cd75f0cSYaniv Rosner if (epause->rx_pause) 18855cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 18865cd75f0cSYaniv Rosner 18875cd75f0cSYaniv Rosner if (epause->tx_pause) 18885cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1889ba35a0fdSYaniv Rosner 1890ba35a0fdSYaniv Rosner if (!bp->link_params.req_fc_auto_adv) 1891ba35a0fdSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1892adfc5217SJeff Kirsher } 1893adfc5217SJeff Kirsher 189451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1895adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1896adfc5217SJeff Kirsher 1897adfc5217SJeff Kirsher if (netif_running(dev)) { 1898adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1899adfc5217SJeff Kirsher bnx2x_link_set(bp); 1900adfc5217SJeff Kirsher } 1901adfc5217SJeff Kirsher 1902adfc5217SJeff Kirsher return 0; 1903adfc5217SJeff Kirsher } 1904adfc5217SJeff Kirsher 19055889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1906cf2c1df6SMerav Sicron "register_test (offline) ", 1907cf2c1df6SMerav Sicron "memory_test (offline) ", 1908cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1909cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1910cf2c1df6SMerav Sicron "nvram_test (online) ", 1911cf2c1df6SMerav Sicron "interrupt_test (online) ", 1912cf2c1df6SMerav Sicron "link_test (online) " 1913adfc5217SJeff Kirsher }; 1914adfc5217SJeff Kirsher 19153521b419SYuval Mintz enum { 19163521b419SYuval Mintz BNX2X_PRI_FLAG_ISCSI, 19173521b419SYuval Mintz BNX2X_PRI_FLAG_FCOE, 19183521b419SYuval Mintz BNX2X_PRI_FLAG_STORAGE, 19193521b419SYuval Mintz BNX2X_PRI_FLAG_LEN, 19203521b419SYuval Mintz }; 19213521b419SYuval Mintz 19223521b419SYuval Mintz static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 19233521b419SYuval Mintz "iSCSI offload support", 19243521b419SYuval Mintz "FCoE offload support", 19253521b419SYuval Mintz "Storage only interface" 19263521b419SYuval Mintz }; 19273521b419SYuval Mintz 1928e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 1929e9939c80SYuval Mintz { 1930e9939c80SYuval Mintz u32 modes = 0; 1931e9939c80SYuval Mintz 1932e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 1933e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 1934e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 1935e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 1936e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 1937e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 1938e9939c80SYuval Mintz 1939e9939c80SYuval Mintz return modes; 1940e9939c80SYuval Mintz } 1941e9939c80SYuval Mintz 1942e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1943e9939c80SYuval Mintz { 1944e9939c80SYuval Mintz u32 eee_adv = 0; 1945e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 1946e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 1947e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 1948e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 1949e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 1950e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 1951e9939c80SYuval Mintz 1952e9939c80SYuval Mintz return eee_adv << shift; 1953e9939c80SYuval Mintz } 1954e9939c80SYuval Mintz 1955e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1956e9939c80SYuval Mintz { 1957e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1958e9939c80SYuval Mintz u32 eee_cfg; 1959e9939c80SYuval Mintz 1960e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1961e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1962e9939c80SYuval Mintz return -EOPNOTSUPP; 1963e9939c80SYuval Mintz } 1964e9939c80SYuval Mintz 196508e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1966e9939c80SYuval Mintz 1967e9939c80SYuval Mintz edata->supported = 1968e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 1969e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 1970e9939c80SYuval Mintz 1971e9939c80SYuval Mintz edata->advertised = 1972e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 1973e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1974e9939c80SYuval Mintz edata->lp_advertised = 1975e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 1976e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 1977e9939c80SYuval Mintz 1978e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 1979e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 1980e9939c80SYuval Mintz 1981e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 1982e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 1983e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 1984e9939c80SYuval Mintz 1985e9939c80SYuval Mintz return 0; 1986e9939c80SYuval Mintz } 1987e9939c80SYuval Mintz 1988e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 1989e9939c80SYuval Mintz { 1990e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1991e9939c80SYuval Mintz u32 eee_cfg; 1992e9939c80SYuval Mintz u32 advertised; 1993e9939c80SYuval Mintz 1994e9939c80SYuval Mintz if (IS_MF(bp)) 1995e9939c80SYuval Mintz return 0; 1996e9939c80SYuval Mintz 1997e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1998e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1999e9939c80SYuval Mintz return -EOPNOTSUPP; 2000e9939c80SYuval Mintz } 2001e9939c80SYuval Mintz 200208e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 2003e9939c80SYuval Mintz 2004e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2005e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2006e9939c80SYuval Mintz return -EOPNOTSUPP; 2007e9939c80SYuval Mintz } 2008e9939c80SYuval Mintz 2009e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 2010e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 2011e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2012e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2013efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 2014e9939c80SYuval Mintz return -EINVAL; 2015e9939c80SYuval Mintz } 2016e9939c80SYuval Mintz 2017e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2018e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2019e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 2020e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 2021e9939c80SYuval Mintz return -EINVAL; 2022e9939c80SYuval Mintz } 2023e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 2024e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2025e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 2026e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 2027e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2028e9939c80SYuval Mintz return -EINVAL; 2029e9939c80SYuval Mintz } 2030e9939c80SYuval Mintz 2031e9939c80SYuval Mintz /* All is well; Apply changes*/ 2032e9939c80SYuval Mintz if (edata->eee_enabled) 2033e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2034e9939c80SYuval Mintz else 2035e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2036e9939c80SYuval Mintz 2037e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 2038e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2039e9939c80SYuval Mintz else 2040e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2041e9939c80SYuval Mintz 2042e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2043e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2044e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 2045e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 2046e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 2047e9939c80SYuval Mintz 204816a5fd92SYuval Mintz /* Restart link to propagate changes */ 2049e9939c80SYuval Mintz if (netif_running(dev)) { 2050e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 20515d07d868SYuval Mintz bnx2x_force_link_reset(bp); 2052e9939c80SYuval Mintz bnx2x_link_set(bp); 2053e9939c80SYuval Mintz } 2054e9939c80SYuval Mintz 2055e9939c80SYuval Mintz return 0; 2056e9939c80SYuval Mintz } 2057e9939c80SYuval Mintz 2058adfc5217SJeff Kirsher enum { 2059adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 2060adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 2061adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 2062adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 2063adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 2064adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 2065adfc5217SJeff Kirsher }; 2066adfc5217SJeff Kirsher 2067adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2068adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2069adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2070adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2071adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2072adfc5217SJeff Kirsher 2073adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2074adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2075adfc5217SJeff Kirsher 2076adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 2077adfc5217SJeff Kirsher { 2078adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 2079adfc5217SJeff Kirsher u32 wr_val = 0, hw; 2080adfc5217SJeff Kirsher int port = BP_PORT(bp); 2081adfc5217SJeff Kirsher static const struct { 2082adfc5217SJeff Kirsher u32 hw; 2083adfc5217SJeff Kirsher u32 offset0; 2084adfc5217SJeff Kirsher u32 offset1; 2085adfc5217SJeff Kirsher u32 mask; 2086adfc5217SJeff Kirsher } reg_tbl[] = { 2087adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 2088adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2089adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2090adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2091adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 2092adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 2093adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2094adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2095adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2096adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2097adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 2098adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2099adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2100adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2101adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2102adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2103adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2104adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2105adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2106adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2107adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 2108adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2109adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2110adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2111adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2112adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 2113adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2114adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2115adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2116adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2117adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2118adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2119adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2120adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2121adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2122adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2123adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2124adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2125adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2126adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2127adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2128adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2129adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2130adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2131adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2132adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2133adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2134adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2135adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2136adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2137adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2138adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2139adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2140adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2141adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2142adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2143adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2144adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2145adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2146adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2147adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 2148adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2149adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2150adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2151adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2152adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2153adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2154adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2155adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2156adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2157adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2158adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2159adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2160adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2161adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2162adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2163adfc5217SJeff Kirsher 2164adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2165adfc5217SJeff Kirsher }; 2166adfc5217SJeff Kirsher 21673fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 216851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 216951c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2170adfc5217SJeff Kirsher return rc; 217151c1a580SMerav Sicron } 2172adfc5217SJeff Kirsher 2173adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2174adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 2175adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2176adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 2177adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2178adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 2179adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 2180adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 2181adfc5217SJeff Kirsher else /* e3 A0 */ 2182adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 2183adfc5217SJeff Kirsher 2184adfc5217SJeff Kirsher /* Repeat the test twice: 218507ba6af4SMiriam Shitrit * First by writing 0x00000000, second by writing 0xffffffff 218607ba6af4SMiriam Shitrit */ 2187adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 2188adfc5217SJeff Kirsher 2189adfc5217SJeff Kirsher switch (idx) { 2190adfc5217SJeff Kirsher case 0: 2191adfc5217SJeff Kirsher wr_val = 0; 2192adfc5217SJeff Kirsher break; 2193adfc5217SJeff Kirsher case 1: 2194adfc5217SJeff Kirsher wr_val = 0xffffffff; 2195adfc5217SJeff Kirsher break; 2196adfc5217SJeff Kirsher } 2197adfc5217SJeff Kirsher 2198adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2199adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 2200adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 2201adfc5217SJeff Kirsher continue; 2202adfc5217SJeff Kirsher 2203adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2204adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 2205adfc5217SJeff Kirsher 2206adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 2207adfc5217SJeff Kirsher 2208adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 2209adfc5217SJeff Kirsher 2210adfc5217SJeff Kirsher val = REG_RD(bp, offset); 2211adfc5217SJeff Kirsher 2212adfc5217SJeff Kirsher /* Restore the original register's value */ 2213adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 2214adfc5217SJeff Kirsher 2215adfc5217SJeff Kirsher /* verify value is as expected */ 2216adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 221751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2218adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2219adfc5217SJeff Kirsher offset, val, wr_val, mask); 2220adfc5217SJeff Kirsher goto test_reg_exit; 2221adfc5217SJeff Kirsher } 2222adfc5217SJeff Kirsher } 2223adfc5217SJeff Kirsher } 2224adfc5217SJeff Kirsher 2225adfc5217SJeff Kirsher rc = 0; 2226adfc5217SJeff Kirsher 2227adfc5217SJeff Kirsher test_reg_exit: 2228adfc5217SJeff Kirsher return rc; 2229adfc5217SJeff Kirsher } 2230adfc5217SJeff Kirsher 2231adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 2232adfc5217SJeff Kirsher { 2233adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 2234adfc5217SJeff Kirsher u32 val, index; 2235adfc5217SJeff Kirsher static const struct { 2236adfc5217SJeff Kirsher u32 offset; 2237adfc5217SJeff Kirsher int size; 2238adfc5217SJeff Kirsher } mem_tbl[] = { 2239adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2240adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2241adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2242adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2243adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2244adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2245adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2246adfc5217SJeff Kirsher 2247adfc5217SJeff Kirsher { 0xffffffff, 0 } 2248adfc5217SJeff Kirsher }; 2249adfc5217SJeff Kirsher 2250adfc5217SJeff Kirsher static const struct { 2251adfc5217SJeff Kirsher char *name; 2252adfc5217SJeff Kirsher u32 offset; 2253adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2254adfc5217SJeff Kirsher } prty_tbl[] = { 2255adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2256adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2257adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2258adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 2259adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2260adfc5217SJeff Kirsher {0, 0, 0, 0} }, 2261adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2262adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2263adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2264adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2265adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2266adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 2267adfc5217SJeff Kirsher 2268adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 2269adfc5217SJeff Kirsher }; 2270adfc5217SJeff Kirsher 22713fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 227251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 227351c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2274adfc5217SJeff Kirsher return rc; 227551c1a580SMerav Sicron } 2276adfc5217SJeff Kirsher 2277adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2278adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 2279adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2280adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 2281adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2282adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 2283adfc5217SJeff Kirsher else /* e3 */ 2284adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 2285adfc5217SJeff Kirsher 2286adfc5217SJeff Kirsher /* pre-Check the parity status */ 2287adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2288adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2289adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 229051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2291adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2292adfc5217SJeff Kirsher goto test_mem_exit; 2293adfc5217SJeff Kirsher } 2294adfc5217SJeff Kirsher } 2295adfc5217SJeff Kirsher 2296adfc5217SJeff Kirsher /* Go through all the memories */ 2297adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2298adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 2299adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 2300adfc5217SJeff Kirsher 2301adfc5217SJeff Kirsher /* Check the parity status */ 2302adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2303adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2304adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 230551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2306adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2307adfc5217SJeff Kirsher goto test_mem_exit; 2308adfc5217SJeff Kirsher } 2309adfc5217SJeff Kirsher } 2310adfc5217SJeff Kirsher 2311adfc5217SJeff Kirsher rc = 0; 2312adfc5217SJeff Kirsher 2313adfc5217SJeff Kirsher test_mem_exit: 2314adfc5217SJeff Kirsher return rc; 2315adfc5217SJeff Kirsher } 2316adfc5217SJeff Kirsher 2317adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2318adfc5217SJeff Kirsher { 2319adfc5217SJeff Kirsher int cnt = 1400; 2320adfc5217SJeff Kirsher 2321adfc5217SJeff Kirsher if (link_up) { 2322adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2323adfc5217SJeff Kirsher msleep(20); 2324adfc5217SJeff Kirsher 2325adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 232651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 23278970b2e4SMerav Sicron 23288970b2e4SMerav Sicron cnt = 1400; 23298970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 23308970b2e4SMerav Sicron msleep(20); 23318970b2e4SMerav Sicron 23328970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 23338970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 23348970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2335adfc5217SJeff Kirsher } 2336adfc5217SJeff Kirsher } 2337adfc5217SJeff Kirsher 2338adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2339adfc5217SJeff Kirsher { 2340adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2341adfc5217SJeff Kirsher struct sk_buff *skb; 2342adfc5217SJeff Kirsher unsigned char *packet; 2343adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2344adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 234565565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2346adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2347adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2348b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2349adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2350adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2351adfc5217SJeff Kirsher dma_addr_t mapping; 2352adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2353adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2354adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2355adfc5217SJeff Kirsher u16 len; 2356adfc5217SJeff Kirsher int rc = -ENODEV; 2357e52fcb24SEric Dumazet u8 *data; 23588970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 23598970b2e4SMerav Sicron txdata->txq_index); 2360adfc5217SJeff Kirsher 2361adfc5217SJeff Kirsher /* check the loopback mode */ 2362adfc5217SJeff Kirsher switch (loopback_mode) { 2363adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 23648970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 23658970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2366adfc5217SJeff Kirsher return -EINVAL; 23678970b2e4SMerav Sicron } 2368adfc5217SJeff Kirsher break; 2369adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 237032911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 237132911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 237232911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 237332911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 237432911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 237532911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 237632911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 237732911333SYaniv Rosner else 237832911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 237932911333SYaniv Rosner } else 238032911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 238132911333SYaniv Rosner 2382adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2383adfc5217SJeff Kirsher break; 23848970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 23858970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 23868970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 23878970b2e4SMerav Sicron "Can't configure external loopback\n"); 23888970b2e4SMerav Sicron return -EINVAL; 23898970b2e4SMerav Sicron } 23908970b2e4SMerav Sicron break; 2391adfc5217SJeff Kirsher default: 239251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2393adfc5217SJeff Kirsher return -EINVAL; 2394adfc5217SJeff Kirsher } 2395adfc5217SJeff Kirsher 2396adfc5217SJeff Kirsher /* prepare the loopback packet */ 2397adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2398adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2399adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2400adfc5217SJeff Kirsher if (!skb) { 240151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2402adfc5217SJeff Kirsher rc = -ENOMEM; 2403adfc5217SJeff Kirsher goto test_loopback_exit; 2404adfc5217SJeff Kirsher } 2405adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2406adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2407adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 2408adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2409adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2410adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2411adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2412adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2413adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2414adfc5217SJeff Kirsher rc = -ENOMEM; 2415adfc5217SJeff Kirsher dev_kfree_skb(skb); 241651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2417adfc5217SJeff Kirsher goto test_loopback_exit; 2418adfc5217SJeff Kirsher } 2419adfc5217SJeff Kirsher 2420adfc5217SJeff Kirsher /* send the loopback packet */ 2421adfc5217SJeff Kirsher num_pkts = 0; 2422adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2423adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2424adfc5217SJeff Kirsher 242573dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 242673dbb5e1SDmitry Kravkov 2427adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2428adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2429adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2430adfc5217SJeff Kirsher tx_buf->skb = skb; 2431adfc5217SJeff Kirsher tx_buf->flags = 0; 2432adfc5217SJeff Kirsher 2433adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2434adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2435adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2436adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2437adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2438adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2439adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2440adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2441adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2442adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2443adfc5217SJeff Kirsher 1); 244496bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 244596bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 244696bed4b9SYuval Mintz 0); 2447adfc5217SJeff Kirsher 2448adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2449adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2450adfc5217SJeff Kirsher 245196bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 245296bed4b9SYuval Mintz u16 global_data = 0; 245396bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 245496bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2455adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 245696bed4b9SYuval Mintz SET_FLAG(global_data, 245796bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 245896bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 245996bed4b9SYuval Mintz } else { 246096bed4b9SYuval Mintz u32 parsing_data = 0; 246196bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 246296bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 246396bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 246496bed4b9SYuval Mintz SET_FLAG(parsing_data, 246596bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 246696bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 246796bed4b9SYuval Mintz } 2468adfc5217SJeff Kirsher wmb(); 2469adfc5217SJeff Kirsher 2470adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2471adfc5217SJeff Kirsher barrier(); 2472adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2473adfc5217SJeff Kirsher 2474adfc5217SJeff Kirsher mmiowb(); 2475adfc5217SJeff Kirsher barrier(); 2476adfc5217SJeff Kirsher 2477adfc5217SJeff Kirsher num_pkts++; 2478adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2479adfc5217SJeff Kirsher 2480adfc5217SJeff Kirsher udelay(100); 2481adfc5217SJeff Kirsher 2482adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2483adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2484adfc5217SJeff Kirsher goto test_loopback_exit; 2485adfc5217SJeff Kirsher 2486adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2487adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2488adfc5217SJeff Kirsher * disabled. 2489adfc5217SJeff Kirsher */ 2490adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2491adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2492adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2493adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2494adfc5217SJeff Kirsher */ 2495adfc5217SJeff Kirsher local_bh_disable(); 2496adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2497adfc5217SJeff Kirsher local_bh_enable(); 2498adfc5217SJeff Kirsher } 2499adfc5217SJeff Kirsher 2500adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2501adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2502adfc5217SJeff Kirsher goto test_loopback_exit; 2503adfc5217SJeff Kirsher 2504b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2505adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2506adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2507adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2508adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2509adfc5217SJeff Kirsher 2510621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2511adfc5217SJeff Kirsher if (len != pkt_size) 2512adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2513adfc5217SJeff Kirsher 2514adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2515adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2516adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2517adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2518e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2519adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2520e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2521adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2522adfc5217SJeff Kirsher 2523adfc5217SJeff Kirsher rc = 0; 2524adfc5217SJeff Kirsher 2525adfc5217SJeff Kirsher test_loopback_rx_exit: 2526adfc5217SJeff Kirsher 2527adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2528adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2529adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2530adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2531adfc5217SJeff Kirsher 2532adfc5217SJeff Kirsher /* Update producers */ 2533adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2534adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2535adfc5217SJeff Kirsher 2536adfc5217SJeff Kirsher test_loopback_exit: 2537adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2538adfc5217SJeff Kirsher 2539adfc5217SJeff Kirsher return rc; 2540adfc5217SJeff Kirsher } 2541adfc5217SJeff Kirsher 2542adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2543adfc5217SJeff Kirsher { 2544adfc5217SJeff Kirsher int rc = 0, res; 2545adfc5217SJeff Kirsher 2546adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2547adfc5217SJeff Kirsher return rc; 2548adfc5217SJeff Kirsher 2549adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2550adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2551adfc5217SJeff Kirsher 2552adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2553adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2554adfc5217SJeff Kirsher 2555adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2556adfc5217SJeff Kirsher if (res) { 255751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2558adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2559adfc5217SJeff Kirsher } 2560adfc5217SJeff Kirsher 2561adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2562adfc5217SJeff Kirsher if (res) { 256351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2564adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2565adfc5217SJeff Kirsher } 2566adfc5217SJeff Kirsher 2567adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2568adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2569adfc5217SJeff Kirsher 2570adfc5217SJeff Kirsher return rc; 2571adfc5217SJeff Kirsher } 2572adfc5217SJeff Kirsher 25738970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 25748970b2e4SMerav Sicron { 25758970b2e4SMerav Sicron int rc; 25768970b2e4SMerav Sicron u8 is_serdes = 25778970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 25788970b2e4SMerav Sicron 25798970b2e4SMerav Sicron if (BP_NOMCP(bp)) 25808970b2e4SMerav Sicron return -ENODEV; 25818970b2e4SMerav Sicron 25828970b2e4SMerav Sicron if (!netif_running(bp->dev)) 25838970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 25848970b2e4SMerav Sicron 25855d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 25868970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 25878970b2e4SMerav Sicron if (rc) { 25888970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 25898970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 25908970b2e4SMerav Sicron return -ENODEV; 25918970b2e4SMerav Sicron } 25928970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 25938970b2e4SMerav Sicron 25948970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 25958970b2e4SMerav Sicron 25968970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 25978970b2e4SMerav Sicron if (rc) 25988970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 25998970b2e4SMerav Sicron 26008970b2e4SMerav Sicron bnx2x_netif_start(bp); 26018970b2e4SMerav Sicron 26028970b2e4SMerav Sicron return rc; 26038970b2e4SMerav Sicron } 26048970b2e4SMerav Sicron 2605edb944d2SDmitry Kravkov struct code_entry { 2606edb944d2SDmitry Kravkov u32 sram_start_addr; 2607edb944d2SDmitry Kravkov u32 code_attribute; 2608edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_MASK 0xf0800003 2609edb944d2SDmitry Kravkov #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2610edb944d2SDmitry Kravkov #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2611edb944d2SDmitry Kravkov #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2612edb944d2SDmitry Kravkov u32 nvm_start_addr; 2613edb944d2SDmitry Kravkov }; 2614edb944d2SDmitry Kravkov 2615edb944d2SDmitry Kravkov #define CODE_ENTRY_MAX 16 2616edb944d2SDmitry Kravkov #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2617edb944d2SDmitry Kravkov #define MAX_IMAGES_IN_EXTENDED_DIR 64 2618edb944d2SDmitry Kravkov #define NVRAM_DIR_OFFSET 0x14 2619edb944d2SDmitry Kravkov 2620edb944d2SDmitry Kravkov #define EXTENDED_DIR_EXISTS(code) \ 2621edb944d2SDmitry Kravkov ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2622edb944d2SDmitry Kravkov (code & CODE_IMAGE_LENGTH_MASK) != 0) 2623edb944d2SDmitry Kravkov 2624adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2625edb944d2SDmitry Kravkov #define CRC_BUFF_SIZE 256 2626edb944d2SDmitry Kravkov 2627edb944d2SDmitry Kravkov static int bnx2x_nvram_crc(struct bnx2x *bp, 2628edb944d2SDmitry Kravkov int offset, 2629edb944d2SDmitry Kravkov int size, 2630edb944d2SDmitry Kravkov u8 *buff) 2631edb944d2SDmitry Kravkov { 2632edb944d2SDmitry Kravkov u32 crc = ~0; 2633edb944d2SDmitry Kravkov int rc = 0, done = 0; 2634edb944d2SDmitry Kravkov 2635edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2636edb944d2SDmitry Kravkov "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2637edb944d2SDmitry Kravkov 2638edb944d2SDmitry Kravkov while (done < size) { 2639edb944d2SDmitry Kravkov int count = min_t(int, size - done, CRC_BUFF_SIZE); 2640edb944d2SDmitry Kravkov 2641edb944d2SDmitry Kravkov rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2642edb944d2SDmitry Kravkov 2643edb944d2SDmitry Kravkov if (rc) 2644edb944d2SDmitry Kravkov return rc; 2645edb944d2SDmitry Kravkov 2646edb944d2SDmitry Kravkov crc = crc32_le(crc, buff, count); 2647edb944d2SDmitry Kravkov done += count; 2648edb944d2SDmitry Kravkov } 2649edb944d2SDmitry Kravkov 2650edb944d2SDmitry Kravkov if (crc != CRC32_RESIDUAL) 2651edb944d2SDmitry Kravkov rc = -EINVAL; 2652edb944d2SDmitry Kravkov 2653edb944d2SDmitry Kravkov return rc; 2654edb944d2SDmitry Kravkov } 2655edb944d2SDmitry Kravkov 2656edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2657edb944d2SDmitry Kravkov struct code_entry *entry, 2658edb944d2SDmitry Kravkov u8 *buff) 2659edb944d2SDmitry Kravkov { 2660edb944d2SDmitry Kravkov size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2661edb944d2SDmitry Kravkov u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2662edb944d2SDmitry Kravkov int rc; 2663edb944d2SDmitry Kravkov 2664edb944d2SDmitry Kravkov /* Zero-length images and AFEX profiles do not have CRC */ 2665edb944d2SDmitry Kravkov if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2666edb944d2SDmitry Kravkov return 0; 2667edb944d2SDmitry Kravkov 2668edb944d2SDmitry Kravkov rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2669edb944d2SDmitry Kravkov if (rc) 2670edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2671edb944d2SDmitry Kravkov "image %x has failed crc test (rc %d)\n", type, rc); 2672edb944d2SDmitry Kravkov 2673edb944d2SDmitry Kravkov return rc; 2674edb944d2SDmitry Kravkov } 2675edb944d2SDmitry Kravkov 2676edb944d2SDmitry Kravkov static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2677edb944d2SDmitry Kravkov { 2678edb944d2SDmitry Kravkov int rc; 2679edb944d2SDmitry Kravkov struct code_entry entry; 2680edb944d2SDmitry Kravkov 2681edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2682edb944d2SDmitry Kravkov if (rc) 2683edb944d2SDmitry Kravkov return rc; 2684edb944d2SDmitry Kravkov 2685edb944d2SDmitry Kravkov return bnx2x_test_nvram_dir(bp, &entry, buff); 2686edb944d2SDmitry Kravkov } 2687edb944d2SDmitry Kravkov 2688edb944d2SDmitry Kravkov static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2689edb944d2SDmitry Kravkov { 2690edb944d2SDmitry Kravkov u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2691edb944d2SDmitry Kravkov struct code_entry entry; 2692edb944d2SDmitry Kravkov int i; 2693edb944d2SDmitry Kravkov 2694edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 2695edb944d2SDmitry Kravkov dir_offset + 2696edb944d2SDmitry Kravkov sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2697edb944d2SDmitry Kravkov (u32 *)&entry, sizeof(entry)); 2698edb944d2SDmitry Kravkov if (rc) 2699edb944d2SDmitry Kravkov return rc; 2700edb944d2SDmitry Kravkov 2701edb944d2SDmitry Kravkov if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2702edb944d2SDmitry Kravkov return 0; 2703edb944d2SDmitry Kravkov 2704edb944d2SDmitry Kravkov rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2705edb944d2SDmitry Kravkov &cnt, sizeof(u32)); 2706edb944d2SDmitry Kravkov if (rc) 2707edb944d2SDmitry Kravkov return rc; 2708edb944d2SDmitry Kravkov 2709edb944d2SDmitry Kravkov dir_offset = entry.nvm_start_addr + 8; 2710edb944d2SDmitry Kravkov 2711edb944d2SDmitry Kravkov for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2712edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2713edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2714edb944d2SDmitry Kravkov buff); 2715edb944d2SDmitry Kravkov if (rc) 2716edb944d2SDmitry Kravkov return rc; 2717edb944d2SDmitry Kravkov } 2718edb944d2SDmitry Kravkov 2719edb944d2SDmitry Kravkov return 0; 2720edb944d2SDmitry Kravkov } 2721edb944d2SDmitry Kravkov 2722edb944d2SDmitry Kravkov static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2723edb944d2SDmitry Kravkov { 2724edb944d2SDmitry Kravkov u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2725edb944d2SDmitry Kravkov int i; 2726edb944d2SDmitry Kravkov 2727edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2728edb944d2SDmitry Kravkov 2729edb944d2SDmitry Kravkov for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2730edb944d2SDmitry Kravkov rc = bnx2x_test_dir_entry(bp, dir_offset + 2731edb944d2SDmitry Kravkov sizeof(struct code_entry) * i, 2732edb944d2SDmitry Kravkov buff); 2733edb944d2SDmitry Kravkov if (rc) 2734edb944d2SDmitry Kravkov return rc; 2735edb944d2SDmitry Kravkov } 2736edb944d2SDmitry Kravkov 2737edb944d2SDmitry Kravkov return bnx2x_test_nvram_ext_dirs(bp, buff); 2738edb944d2SDmitry Kravkov } 2739edb944d2SDmitry Kravkov 2740edb944d2SDmitry Kravkov struct crc_pair { 2741edb944d2SDmitry Kravkov int offset; 2742edb944d2SDmitry Kravkov int size; 2743edb944d2SDmitry Kravkov }; 2744edb944d2SDmitry Kravkov 2745edb944d2SDmitry Kravkov static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2746edb944d2SDmitry Kravkov const struct crc_pair *nvram_tbl, u8 *buf) 2747edb944d2SDmitry Kravkov { 2748edb944d2SDmitry Kravkov int i; 2749edb944d2SDmitry Kravkov 2750edb944d2SDmitry Kravkov for (i = 0; nvram_tbl[i].size; i++) { 2751edb944d2SDmitry Kravkov int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2752edb944d2SDmitry Kravkov nvram_tbl[i].size, buf); 2753edb944d2SDmitry Kravkov if (rc) { 2754edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2755edb944d2SDmitry Kravkov "nvram_tbl[%d] has failed crc test (rc %d)\n", 2756edb944d2SDmitry Kravkov i, rc); 2757edb944d2SDmitry Kravkov return rc; 2758edb944d2SDmitry Kravkov } 2759edb944d2SDmitry Kravkov } 2760edb944d2SDmitry Kravkov 2761edb944d2SDmitry Kravkov return 0; 2762edb944d2SDmitry Kravkov } 2763adfc5217SJeff Kirsher 2764adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2765adfc5217SJeff Kirsher { 2766edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl[] = { 2767adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2768adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2769adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2770adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2771adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2772adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2773adfc5217SJeff Kirsher { 0, 0 } 2774adfc5217SJeff Kirsher }; 2775edb944d2SDmitry Kravkov const struct crc_pair nvram_tbl2[] = { 2776edb944d2SDmitry Kravkov { 0x7e8, 0x350 }, /* manuf_info2 */ 2777edb944d2SDmitry Kravkov { 0xb38, 0xf0 }, /* feature_info */ 2778edb944d2SDmitry Kravkov { 0, 0 } 2779edb944d2SDmitry Kravkov }; 2780edb944d2SDmitry Kravkov 278185640952SDmitry Kravkov u8 *buf; 2782edb944d2SDmitry Kravkov int rc; 2783edb944d2SDmitry Kravkov u32 magic; 2784adfc5217SJeff Kirsher 2785adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2786adfc5217SJeff Kirsher return 0; 2787adfc5217SJeff Kirsher 2788edb944d2SDmitry Kravkov buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2789afa13b4bSMintz Yuval if (!buf) { 279051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2791afa13b4bSMintz Yuval rc = -ENOMEM; 2792afa13b4bSMintz Yuval goto test_nvram_exit; 2793afa13b4bSMintz Yuval } 2794afa13b4bSMintz Yuval 279585640952SDmitry Kravkov rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2796adfc5217SJeff Kirsher if (rc) { 279751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 279851c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2799adfc5217SJeff Kirsher goto test_nvram_exit; 2800adfc5217SJeff Kirsher } 2801adfc5217SJeff Kirsher 2802adfc5217SJeff Kirsher if (magic != 0x669955aa) { 280351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 280451c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2805adfc5217SJeff Kirsher rc = -ENODEV; 2806adfc5217SJeff Kirsher goto test_nvram_exit; 2807adfc5217SJeff Kirsher } 2808adfc5217SJeff Kirsher 2809edb944d2SDmitry Kravkov DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2810edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2811edb944d2SDmitry Kravkov if (rc) 2812adfc5217SJeff Kirsher goto test_nvram_exit; 2813adfc5217SJeff Kirsher 2814edb944d2SDmitry Kravkov if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2815edb944d2SDmitry Kravkov u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2816edb944d2SDmitry Kravkov SHARED_HW_CFG_HIDE_PORT1; 2817edb944d2SDmitry Kravkov 2818edb944d2SDmitry Kravkov if (!hide) { 281951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2820edb944d2SDmitry Kravkov "Port 1 CRC test-set\n"); 2821edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2822edb944d2SDmitry Kravkov if (rc) 2823adfc5217SJeff Kirsher goto test_nvram_exit; 2824adfc5217SJeff Kirsher } 2825adfc5217SJeff Kirsher } 2826adfc5217SJeff Kirsher 2827edb944d2SDmitry Kravkov rc = bnx2x_test_nvram_dirs(bp, buf); 2828edb944d2SDmitry Kravkov 2829adfc5217SJeff Kirsher test_nvram_exit: 2830afa13b4bSMintz Yuval kfree(buf); 2831adfc5217SJeff Kirsher return rc; 2832adfc5217SJeff Kirsher } 2833adfc5217SJeff Kirsher 2834adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2835adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2836adfc5217SJeff Kirsher { 28373b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2838adfc5217SJeff Kirsher 283951c1a580SMerav Sicron if (!netif_running(bp->dev)) { 284051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 284151c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2842adfc5217SJeff Kirsher return -ENODEV; 284351c1a580SMerav Sicron } 2844adfc5217SJeff Kirsher 284515192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2846adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2847adfc5217SJeff Kirsher 2848adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2849adfc5217SJeff Kirsher 2850adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2851adfc5217SJeff Kirsher } 2852adfc5217SJeff Kirsher 2853adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2854adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2855adfc5217SJeff Kirsher { 2856adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2857a336ca7cSYaniv Rosner u8 is_serdes, link_up; 2858a336ca7cSYaniv Rosner int rc, cnt = 0; 2859cf2c1df6SMerav Sicron 2860adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 286151c1a580SMerav Sicron netdev_err(bp->dev, 286251c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2863adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2864adfc5217SJeff Kirsher return; 2865adfc5217SJeff Kirsher } 28662de67439SYuval Mintz 28678970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 28688970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 28698970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 28708970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2871adfc5217SJeff Kirsher 2872cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2873adfc5217SJeff Kirsher 2874bd8e012bSYuval Mintz if (bnx2x_test_nvram(bp) != 0) { 2875bd8e012bSYuval Mintz if (!IS_MF(bp)) 2876bd8e012bSYuval Mintz buf[4] = 1; 2877bd8e012bSYuval Mintz else 2878bd8e012bSYuval Mintz buf[0] = 1; 2879bd8e012bSYuval Mintz etest->flags |= ETH_TEST_FL_FAILED; 2880bd8e012bSYuval Mintz } 2881bd8e012bSYuval Mintz 2882cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2883bd8e012bSYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2884adfc5217SJeff Kirsher return; 2885cf2c1df6SMerav Sicron } 2886adfc5217SJeff Kirsher 2887adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2888a336ca7cSYaniv Rosner link_up = bp->link_vars.link_up; 2889cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2890cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2891adfc5217SJeff Kirsher int port = BP_PORT(bp); 2892adfc5217SJeff Kirsher u32 val; 2893adfc5217SJeff Kirsher 2894adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2895adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2896adfc5217SJeff Kirsher /* disable input for TX port IF */ 2897adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2898adfc5217SJeff Kirsher 28995d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2900cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2901cf2c1df6SMerav Sicron if (rc) { 2902cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2903cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2904cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2905cf2c1df6SMerav Sicron return; 2906cf2c1df6SMerav Sicron } 2907cf2c1df6SMerav Sicron 2908adfc5217SJeff Kirsher /* wait until link state is restored */ 2909adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2910adfc5217SJeff Kirsher 2911adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2912adfc5217SJeff Kirsher buf[0] = 1; 2913adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2914adfc5217SJeff Kirsher } 2915adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2916adfc5217SJeff Kirsher buf[1] = 1; 2917adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2918adfc5217SJeff Kirsher } 2919adfc5217SJeff Kirsher 29208970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2921adfc5217SJeff Kirsher if (buf[2] != 0) 2922adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2923adfc5217SJeff Kirsher 29248970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 29258970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 29268970b2e4SMerav Sicron if (buf[3] != 0) 29278970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 29288970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 29298970b2e4SMerav Sicron } 29308970b2e4SMerav Sicron 29315d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2932adfc5217SJeff Kirsher 2933adfc5217SJeff Kirsher /* restore input for TX port IF */ 2934adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2935cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2936cf2c1df6SMerav Sicron if (rc) { 2937cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2938cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2939cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 2940cf2c1df6SMerav Sicron return; 2941cf2c1df6SMerav Sicron } 2942adfc5217SJeff Kirsher /* wait until link state is restored */ 2943adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2944adfc5217SJeff Kirsher } 2945bd8e012bSYuval Mintz 2946adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2947cf2c1df6SMerav Sicron if (!IS_MF(bp)) 29488970b2e4SMerav Sicron buf[5] = 1; 2949cf2c1df6SMerav Sicron else 2950cf2c1df6SMerav Sicron buf[1] = 1; 2951adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2952adfc5217SJeff Kirsher } 2953adfc5217SJeff Kirsher 2954a336ca7cSYaniv Rosner if (link_up) { 2955a336ca7cSYaniv Rosner cnt = 100; 2956a336ca7cSYaniv Rosner while (bnx2x_link_test(bp, is_serdes) && --cnt) 2957a336ca7cSYaniv Rosner msleep(20); 2958a336ca7cSYaniv Rosner } 2959a336ca7cSYaniv Rosner 2960a336ca7cSYaniv Rosner if (!cnt) { 2961cf2c1df6SMerav Sicron if (!IS_MF(bp)) 29628970b2e4SMerav Sicron buf[6] = 1; 2963cf2c1df6SMerav Sicron else 2964cf2c1df6SMerav Sicron buf[2] = 1; 2965adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2966adfc5217SJeff Kirsher } 2967adfc5217SJeff Kirsher } 2968adfc5217SJeff Kirsher 2969adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 2970adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2971adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2972d8361051SYuval Mintz #define HIDE_PORT_STAT(bp) \ 2973d8361051SYuval Mintz ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \ 2974d8361051SYuval Mintz IS_VF(bp)) 2975adfc5217SJeff Kirsher 2976adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 2977adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 2978adfc5217SJeff Kirsher */ 29791191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 2980adfc5217SJeff Kirsher { 2981adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 2982adfc5217SJeff Kirsher } 2983adfc5217SJeff Kirsher 2984adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2985adfc5217SJeff Kirsher { 2986adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 29873521b419SYuval Mintz int i, num_strings = 0; 2988adfc5217SJeff Kirsher 2989adfc5217SJeff Kirsher switch (stringset) { 2990adfc5217SJeff Kirsher case ETH_SS_STATS: 2991adfc5217SJeff Kirsher if (is_multi(bp)) { 29923521b419SYuval Mintz num_strings = bnx2x_num_stat_queues(bp) * 2993adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 2994d5e83632SYuval Mintz } else 29953521b419SYuval Mintz num_strings = 0; 2996d8361051SYuval Mintz if (HIDE_PORT_STAT(bp)) { 2997adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 2998adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 29993521b419SYuval Mintz num_strings++; 3000adfc5217SJeff Kirsher } else 30013521b419SYuval Mintz num_strings += BNX2X_NUM_STATS; 3002d5e83632SYuval Mintz 30033521b419SYuval Mintz return num_strings; 3004adfc5217SJeff Kirsher 3005adfc5217SJeff Kirsher case ETH_SS_TEST: 3006cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 3007adfc5217SJeff Kirsher 30083521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 30093521b419SYuval Mintz return BNX2X_PRI_FLAG_LEN; 30103521b419SYuval Mintz 3011adfc5217SJeff Kirsher default: 3012adfc5217SJeff Kirsher return -EINVAL; 3013adfc5217SJeff Kirsher } 3014adfc5217SJeff Kirsher } 3015adfc5217SJeff Kirsher 30163521b419SYuval Mintz static u32 bnx2x_get_private_flags(struct net_device *dev) 30173521b419SYuval Mintz { 30183521b419SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 30193521b419SYuval Mintz u32 flags = 0; 30203521b419SYuval Mintz 30213521b419SYuval Mintz flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 30223521b419SYuval Mintz flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 30233521b419SYuval Mintz flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 30243521b419SYuval Mintz 30253521b419SYuval Mintz return flags; 30263521b419SYuval Mintz } 30273521b419SYuval Mintz 3028adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3029adfc5217SJeff Kirsher { 3030adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 30315889335cSMerav Sicron int i, j, k, start; 3032adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 3033adfc5217SJeff Kirsher 3034adfc5217SJeff Kirsher switch (stringset) { 3035adfc5217SJeff Kirsher case ETH_SS_STATS: 3036adfc5217SJeff Kirsher k = 0; 3037d5e83632SYuval Mintz if (is_multi(bp)) { 3038adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 3039adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 3040adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 3041adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3042adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3043adfc5217SJeff Kirsher ETH_GSTRING_LEN, 3044adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 3045adfc5217SJeff Kirsher queue_name); 3046adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3047adfc5217SJeff Kirsher } 3048d5e83632SYuval Mintz } 3049d5e83632SYuval Mintz 3050adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3051d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3052adfc5217SJeff Kirsher continue; 3053d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3054adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 3055adfc5217SJeff Kirsher j++; 3056adfc5217SJeff Kirsher } 3057d5e83632SYuval Mintz 3058adfc5217SJeff Kirsher break; 3059adfc5217SJeff Kirsher 3060adfc5217SJeff Kirsher case ETH_SS_TEST: 3061cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 3062cf2c1df6SMerav Sicron if (!IS_MF(bp)) 3063cf2c1df6SMerav Sicron start = 0; 3064cf2c1df6SMerav Sicron else 3065cf2c1df6SMerav Sicron start = 4; 30665889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 30675889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 30683521b419SYuval Mintz break; 30693521b419SYuval Mintz 30703521b419SYuval Mintz case ETH_SS_PRIV_FLAGS: 30713521b419SYuval Mintz memcpy(buf, bnx2x_private_arr, 30723521b419SYuval Mintz ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 30733521b419SYuval Mintz break; 3074adfc5217SJeff Kirsher } 3075adfc5217SJeff Kirsher } 3076adfc5217SJeff Kirsher 3077adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 3078adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 3079adfc5217SJeff Kirsher { 3080adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3081adfc5217SJeff Kirsher u32 *hw_stats, *offset; 3082d5e83632SYuval Mintz int i, j, k = 0; 3083adfc5217SJeff Kirsher 3084adfc5217SJeff Kirsher if (is_multi(bp)) { 3085adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 308615192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3087adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3088adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 3089adfc5217SJeff Kirsher /* skip this counter */ 3090adfc5217SJeff Kirsher buf[k + j] = 0; 3091adfc5217SJeff Kirsher continue; 3092adfc5217SJeff Kirsher } 3093adfc5217SJeff Kirsher offset = (hw_stats + 3094adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 3095adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 3096adfc5217SJeff Kirsher /* 4-byte counter */ 3097adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 3098adfc5217SJeff Kirsher continue; 3099adfc5217SJeff Kirsher } 3100adfc5217SJeff Kirsher /* 8-byte counter */ 3101adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3102adfc5217SJeff Kirsher } 3103adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 3104adfc5217SJeff Kirsher } 3105adfc5217SJeff Kirsher } 3106d5e83632SYuval Mintz 3107adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 3108adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3109d8361051SYuval Mintz if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3110adfc5217SJeff Kirsher continue; 3111adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 3112adfc5217SJeff Kirsher /* skip this counter */ 3113d5e83632SYuval Mintz buf[k + j] = 0; 3114adfc5217SJeff Kirsher j++; 3115adfc5217SJeff Kirsher continue; 3116adfc5217SJeff Kirsher } 3117adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 3118adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 3119adfc5217SJeff Kirsher /* 4-byte counter */ 3120d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 3121adfc5217SJeff Kirsher j++; 3122adfc5217SJeff Kirsher continue; 3123adfc5217SJeff Kirsher } 3124adfc5217SJeff Kirsher /* 8-byte counter */ 3125d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3126adfc5217SJeff Kirsher j++; 3127adfc5217SJeff Kirsher } 3128adfc5217SJeff Kirsher } 3129adfc5217SJeff Kirsher 3130adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 3131adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 3132adfc5217SJeff Kirsher { 3133adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3134adfc5217SJeff Kirsher 31353fb43eb2SYuval Mintz if (!bnx2x_is_nvm_accessible(bp)) { 313651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 313751c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 3138adfc5217SJeff Kirsher return -EAGAIN; 313951c1a580SMerav Sicron } 3140adfc5217SJeff Kirsher 3141adfc5217SJeff Kirsher switch (state) { 3142adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 3143adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 3144adfc5217SJeff Kirsher 3145adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 31468203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3147adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3148adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 31498203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3150adfc5217SJeff Kirsher break; 3151adfc5217SJeff Kirsher 3152adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 31538203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3154adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3155adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 31568203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3157adfc5217SJeff Kirsher break; 3158adfc5217SJeff Kirsher 3159adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 31608203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 3161adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 3162adfc5217SJeff Kirsher LED_MODE_OPER, 3163adfc5217SJeff Kirsher bp->link_vars.line_speed); 31648203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 3165adfc5217SJeff Kirsher } 3166adfc5217SJeff Kirsher 3167adfc5217SJeff Kirsher return 0; 3168adfc5217SJeff Kirsher } 3169adfc5217SJeff Kirsher 31705d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 31715d317c6aSMerav Sicron { 31725d317c6aSMerav Sicron switch (info->flow_type) { 31735d317c6aSMerav Sicron case TCP_V4_FLOW: 31745d317c6aSMerav Sicron case TCP_V6_FLOW: 31755d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 31765d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 31775d317c6aSMerav Sicron break; 31785d317c6aSMerav Sicron case UDP_V4_FLOW: 31795d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 31805d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 31815d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 31825d317c6aSMerav Sicron else 31835d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 31845d317c6aSMerav Sicron break; 31855d317c6aSMerav Sicron case UDP_V6_FLOW: 31865d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 31875d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 31885d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 31895d317c6aSMerav Sicron else 31905d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 31915d317c6aSMerav Sicron break; 31925d317c6aSMerav Sicron case IPV4_FLOW: 31935d317c6aSMerav Sicron case IPV6_FLOW: 31945d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 31955d317c6aSMerav Sicron break; 31965d317c6aSMerav Sicron default: 31975d317c6aSMerav Sicron info->data = 0; 31985d317c6aSMerav Sicron break; 31995d317c6aSMerav Sicron } 32005d317c6aSMerav Sicron 32015d317c6aSMerav Sicron return 0; 32025d317c6aSMerav Sicron } 32035d317c6aSMerav Sicron 3204adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3205815c7db5SBen Hutchings u32 *rules __always_unused) 3206adfc5217SJeff Kirsher { 3207adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3208adfc5217SJeff Kirsher 3209adfc5217SJeff Kirsher switch (info->cmd) { 3210adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 3211adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 3212adfc5217SJeff Kirsher return 0; 32135d317c6aSMerav Sicron case ETHTOOL_GRXFH: 32145d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 32155d317c6aSMerav Sicron default: 32165d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 32175d317c6aSMerav Sicron return -EOPNOTSUPP; 32185d317c6aSMerav Sicron } 32195d317c6aSMerav Sicron } 3220adfc5217SJeff Kirsher 32215d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 32225d317c6aSMerav Sicron { 32235d317c6aSMerav Sicron int udp_rss_requested; 32245d317c6aSMerav Sicron 32255d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32265d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 32275d317c6aSMerav Sicron info->flow_type, info->data); 32285d317c6aSMerav Sicron 32295d317c6aSMerav Sicron switch (info->flow_type) { 32305d317c6aSMerav Sicron case TCP_V4_FLOW: 32315d317c6aSMerav Sicron case TCP_V6_FLOW: 32325d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 32335d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 32345d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 32355d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32365d317c6aSMerav Sicron "Command parameters not supported\n"); 32375d317c6aSMerav Sicron return -EINVAL; 32385d317c6aSMerav Sicron } 32392de67439SYuval Mintz return 0; 32405d317c6aSMerav Sicron 32415d317c6aSMerav Sicron case UDP_V4_FLOW: 32425d317c6aSMerav Sicron case UDP_V6_FLOW: 32435d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 32445d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 32455d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 32465d317c6aSMerav Sicron udp_rss_requested = 1; 32475d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 32485d317c6aSMerav Sicron udp_rss_requested = 0; 32495d317c6aSMerav Sicron else 32505d317c6aSMerav Sicron return -EINVAL; 32515d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 32525d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 32535d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 32545d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32555d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 32565d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 325760cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 32585d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 32595d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 32605d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 32615d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32625d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 32635d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 326460cad4e6SAriel Elior return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 32655d317c6aSMerav Sicron } 3266924d75abSYuval Mintz return 0; 3267924d75abSYuval Mintz 32685d317c6aSMerav Sicron case IPV4_FLOW: 32695d317c6aSMerav Sicron case IPV6_FLOW: 32705d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 32715d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 32725d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32735d317c6aSMerav Sicron "Command parameters not supported\n"); 32745d317c6aSMerav Sicron return -EINVAL; 32755d317c6aSMerav Sicron } 3276924d75abSYuval Mintz return 0; 3277924d75abSYuval Mintz 32785d317c6aSMerav Sicron case SCTP_V4_FLOW: 32795d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 32805d317c6aSMerav Sicron case AH_V4_FLOW: 32815d317c6aSMerav Sicron case ESP_V4_FLOW: 32825d317c6aSMerav Sicron case SCTP_V6_FLOW: 32835d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 32845d317c6aSMerav Sicron case AH_V6_FLOW: 32855d317c6aSMerav Sicron case ESP_V6_FLOW: 32865d317c6aSMerav Sicron case IP_USER_FLOW: 32875d317c6aSMerav Sicron case ETHER_FLOW: 32885d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 32895d317c6aSMerav Sicron if (info->data) { 32905d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 32915d317c6aSMerav Sicron "Command parameters not supported\n"); 32925d317c6aSMerav Sicron return -EINVAL; 32935d317c6aSMerav Sicron } 3294924d75abSYuval Mintz return 0; 3295924d75abSYuval Mintz 32965d317c6aSMerav Sicron default: 32975d317c6aSMerav Sicron return -EINVAL; 32985d317c6aSMerav Sicron } 32995d317c6aSMerav Sicron } 33005d317c6aSMerav Sicron 33015d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 33025d317c6aSMerav Sicron { 33035d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 33045d317c6aSMerav Sicron 33055d317c6aSMerav Sicron switch (info->cmd) { 33065d317c6aSMerav Sicron case ETHTOOL_SRXFH: 33075d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 3308adfc5217SJeff Kirsher default: 330951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3310adfc5217SJeff Kirsher return -EOPNOTSUPP; 3311adfc5217SJeff Kirsher } 3312adfc5217SJeff Kirsher } 3313adfc5217SJeff Kirsher 33147850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3315adfc5217SJeff Kirsher { 331696305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 33177850f63fSBen Hutchings } 33187850f63fSBen Hutchings 33197850f63fSBen Hutchings static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 33207850f63fSBen Hutchings { 33217850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 3322adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3323adfc5217SJeff Kirsher size_t i; 3324adfc5217SJeff Kirsher 3325adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 3326adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3327adfc5217SJeff Kirsher 3328adfc5217SJeff Kirsher /* 3329adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 3330adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 3331adfc5217SJeff Kirsher * points to an array of u32. 3332adfc5217SJeff Kirsher * 3333adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3334adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 3335adfc5217SJeff Kirsher * queue. 3336adfc5217SJeff Kirsher */ 33377850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 33387850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 3339adfc5217SJeff Kirsher 3340adfc5217SJeff Kirsher return 0; 3341adfc5217SJeff Kirsher } 3342adfc5217SJeff Kirsher 33437850f63fSBen Hutchings static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 3344adfc5217SJeff Kirsher { 3345adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3346adfc5217SJeff Kirsher size_t i; 3347adfc5217SJeff Kirsher 3348adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3349adfc5217SJeff Kirsher /* 3350adfc5217SJeff Kirsher * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 3351adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 3352adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 3353adfc5217SJeff Kirsher * 3354adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3355adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 3356adfc5217SJeff Kirsher * queue 3357adfc5217SJeff Kirsher */ 33585d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3359adfc5217SJeff Kirsher } 3360adfc5217SJeff Kirsher 33615d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 3362adfc5217SJeff Kirsher } 3363adfc5217SJeff Kirsher 33640e8d2ec5SMerav Sicron /** 33650e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 33660e8d2ec5SMerav Sicron * 33670e8d2ec5SMerav Sicron * @dev: net device 33680e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 33690e8d2ec5SMerav Sicron */ 33700e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 33710e8d2ec5SMerav Sicron struct ethtool_channels *channels) 33720e8d2ec5SMerav Sicron { 33730e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 33740e8d2ec5SMerav Sicron 33750e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 33760e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 33770e8d2ec5SMerav Sicron } 33780e8d2ec5SMerav Sicron 33790e8d2ec5SMerav Sicron /** 33800e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 33810e8d2ec5SMerav Sicron * 33820e8d2ec5SMerav Sicron * @bp: bnx2x private structure 33830e8d2ec5SMerav Sicron * 33840e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 33850e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 33860e8d2ec5SMerav Sicron */ 33870e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 33880e8d2ec5SMerav Sicron { 33890e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 339055c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 339155c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 339255c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 33930e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 33940e8d2ec5SMerav Sicron } 33950e8d2ec5SMerav Sicron 33960e8d2ec5SMerav Sicron /** 33970e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 33980e8d2ec5SMerav Sicron * 33990e8d2ec5SMerav Sicron * @dev: net device 34000e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 34010e8d2ec5SMerav Sicron */ 34020e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 34030e8d2ec5SMerav Sicron struct ethtool_channels *channels) 34040e8d2ec5SMerav Sicron { 34050e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 34060e8d2ec5SMerav Sicron 34070e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34080e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 34090e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 34100e8d2ec5SMerav Sicron channels->combined_count); 34110e8d2ec5SMerav Sicron 34120e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 34130e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 34140e8d2ec5SMerav Sicron */ 34150e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 34160e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 34170e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 34180e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 34190e8d2ec5SMerav Sicron return -EINVAL; 34200e8d2ec5SMerav Sicron } 34210e8d2ec5SMerav Sicron 34220e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 34230e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 34240e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 34250e8d2ec5SMerav Sicron return 0; 34260e8d2ec5SMerav Sicron } 34270e8d2ec5SMerav Sicron 34280e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 34290e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 34300e8d2ec5SMerav Sicron * less than requested if memory is low. 34310e8d2ec5SMerav Sicron */ 34320e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 34330e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 34340e8d2ec5SMerav Sicron return 0; 34350e8d2ec5SMerav Sicron } 34365d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 34370e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 34380e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 34390e8d2ec5SMerav Sicron } 34400e8d2ec5SMerav Sicron 3441adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 3442adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 3443adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 3444adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 3445adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 3446adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 344707ba6af4SMiriam Shitrit .get_dump_flag = bnx2x_get_dump_flag, 344807ba6af4SMiriam Shitrit .get_dump_data = bnx2x_get_dump_data, 344907ba6af4SMiriam Shitrit .set_dump = bnx2x_set_dump, 3450adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 3451adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 3452adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 3453adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 3454adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 3455adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 3456adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 3457adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 3458adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 3459adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 3460adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 3461adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 3462adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 3463adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 3464adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 3465adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 3466adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 34673521b419SYuval Mintz .get_priv_flags = bnx2x_get_private_flags, 3468adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 3469adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 3470adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 3471adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 34725d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 34737850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3474adfc5217SJeff Kirsher .get_rxfh_indir = bnx2x_get_rxfh_indir, 3475adfc5217SJeff Kirsher .set_rxfh_indir = bnx2x_set_rxfh_indir, 34760e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 34770e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 347824ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 347924ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3480e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3481e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3482be53ce1eSRichard Cochran .get_ts_info = ethtool_op_get_ts_info, 3483adfc5217SJeff Kirsher }; 3484adfc5217SJeff Kirsher 3485005a07baSAriel Elior static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3486005a07baSAriel Elior .get_settings = bnx2x_get_settings, 3487005a07baSAriel Elior .set_settings = bnx2x_set_settings, 3488005a07baSAriel Elior .get_drvinfo = bnx2x_get_drvinfo, 3489005a07baSAriel Elior .get_msglevel = bnx2x_get_msglevel, 3490005a07baSAriel Elior .set_msglevel = bnx2x_set_msglevel, 3491005a07baSAriel Elior .get_link = bnx2x_get_link, 3492005a07baSAriel Elior .get_coalesce = bnx2x_get_coalesce, 3493005a07baSAriel Elior .get_ringparam = bnx2x_get_ringparam, 3494005a07baSAriel Elior .set_ringparam = bnx2x_set_ringparam, 3495005a07baSAriel Elior .get_sset_count = bnx2x_get_sset_count, 3496005a07baSAriel Elior .get_strings = bnx2x_get_strings, 3497005a07baSAriel Elior .get_ethtool_stats = bnx2x_get_ethtool_stats, 3498005a07baSAriel Elior .get_rxnfc = bnx2x_get_rxnfc, 3499005a07baSAriel Elior .set_rxnfc = bnx2x_set_rxnfc, 3500005a07baSAriel Elior .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3501005a07baSAriel Elior .get_rxfh_indir = bnx2x_get_rxfh_indir, 3502005a07baSAriel Elior .set_rxfh_indir = bnx2x_set_rxfh_indir, 3503005a07baSAriel Elior .get_channels = bnx2x_get_channels, 3504005a07baSAriel Elior .set_channels = bnx2x_set_channels, 3505005a07baSAriel Elior }; 3506005a07baSAriel Elior 3507005a07baSAriel Elior void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3508adfc5217SJeff Kirsher { 35097ad24ea4SWilfried Klaebe netdev->ethtool_ops = (IS_PF(bp)) ? 35107ad24ea4SWilfried Klaebe &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3511adfc5217SJeff Kirsher } 3512