1adfc5217SJeff Kirsher /* bnx2x_ethtool.c: Broadcom Everest network driver. 2adfc5217SJeff Kirsher * 3247fa82bSYuval Mintz * Copyright (c) 2007-2013 Broadcom Corporation 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * This program is free software; you can redistribute it and/or modify 6adfc5217SJeff Kirsher * it under the terms of the GNU General Public License as published by 7adfc5217SJeff Kirsher * the Free Software Foundation. 8adfc5217SJeff Kirsher * 9adfc5217SJeff Kirsher * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10adfc5217SJeff Kirsher * Written by: Eliezer Tamir 11adfc5217SJeff Kirsher * Based on code from Michael Chan's bnx2 driver 12adfc5217SJeff Kirsher * UDP CSUM errata workaround by Arik Gendelman 13adfc5217SJeff Kirsher * Slowpath and fastpath rework by Vladislav Zolotarov 14adfc5217SJeff Kirsher * Statistics and Link management by Yitchak Gertner 15adfc5217SJeff Kirsher * 16adfc5217SJeff Kirsher */ 17f1deab50SJoe Perches 18f1deab50SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19f1deab50SJoe Perches 20adfc5217SJeff Kirsher #include <linux/ethtool.h> 21adfc5217SJeff Kirsher #include <linux/netdevice.h> 22adfc5217SJeff Kirsher #include <linux/types.h> 23adfc5217SJeff Kirsher #include <linux/sched.h> 24adfc5217SJeff Kirsher #include <linux/crc32.h> 25adfc5217SJeff Kirsher #include "bnx2x.h" 26adfc5217SJeff Kirsher #include "bnx2x_cmn.h" 27adfc5217SJeff Kirsher #include "bnx2x_dump.h" 28adfc5217SJeff Kirsher #include "bnx2x_init.h" 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher /* Note: in the format strings below %s is replaced by the queue-name which is 31adfc5217SJeff Kirsher * either its index or 'fcoe' for the fcoe queue. Make sure the format string 32adfc5217SJeff Kirsher * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 33adfc5217SJeff Kirsher */ 34adfc5217SJeff Kirsher #define MAX_QUEUE_NAME_LEN 4 35adfc5217SJeff Kirsher static const struct { 36adfc5217SJeff Kirsher long offset; 37adfc5217SJeff Kirsher int size; 38adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 39adfc5217SJeff Kirsher } bnx2x_q_stats_arr[] = { 40adfc5217SJeff Kirsher /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 41adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 42adfc5217SJeff Kirsher 8, "[%s]: rx_ucast_packets" }, 43adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 44adfc5217SJeff Kirsher 8, "[%s]: rx_mcast_packets" }, 45adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 46adfc5217SJeff Kirsher 8, "[%s]: rx_bcast_packets" }, 47adfc5217SJeff Kirsher { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 48adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_err_discard_pkt), 49adfc5217SJeff Kirsher 4, "[%s]: rx_phy_ip_err_discards"}, 50adfc5217SJeff Kirsher { Q_STATS_OFFSET32(rx_skb_alloc_failed), 51adfc5217SJeff Kirsher 4, "[%s]: rx_skb_alloc_discard" }, 52adfc5217SJeff Kirsher { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 53adfc5217SJeff Kirsher 54adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 55adfc5217SJeff Kirsher /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 56adfc5217SJeff Kirsher 8, "[%s]: tx_ucast_packets" }, 57adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 58adfc5217SJeff Kirsher 8, "[%s]: tx_mcast_packets" }, 59adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 60adfc5217SJeff Kirsher 8, "[%s]: tx_bcast_packets" }, 61adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 62adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregations" }, 63adfc5217SJeff Kirsher { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 64adfc5217SJeff Kirsher 8, "[%s]: tpa_aggregated_frames"}, 65c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 66c96bdc0cSDmitry Kravkov { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 67c96bdc0cSDmitry Kravkov 4, "[%s]: driver_filtered_tx_pkt" } 68adfc5217SJeff Kirsher }; 69adfc5217SJeff Kirsher 70adfc5217SJeff Kirsher #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 71adfc5217SJeff Kirsher 72adfc5217SJeff Kirsher static const struct { 73adfc5217SJeff Kirsher long offset; 74adfc5217SJeff Kirsher int size; 75adfc5217SJeff Kirsher u32 flags; 76adfc5217SJeff Kirsher #define STATS_FLAGS_PORT 1 77adfc5217SJeff Kirsher #define STATS_FLAGS_FUNC 2 78adfc5217SJeff Kirsher #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 79adfc5217SJeff Kirsher char string[ETH_GSTRING_LEN]; 80adfc5217SJeff Kirsher } bnx2x_stats_arr[] = { 81adfc5217SJeff Kirsher /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 82adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bytes" }, 83adfc5217SJeff Kirsher { STATS_OFFSET32(error_bytes_received_hi), 84adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 85adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_received_hi), 86adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 87adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_received_hi), 88adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 89adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_received_hi), 90adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 91adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 92adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 93adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 94adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_align_errors" }, 95adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 96adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 97adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 98adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 99adfc5217SJeff Kirsher /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 100adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_fragments" }, 101adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 102adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_jabbers" }, 103adfc5217SJeff Kirsher { STATS_OFFSET32(no_buff_discard_hi), 104adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "rx_discards" }, 105adfc5217SJeff Kirsher { STATS_OFFSET32(mac_filter_discard), 106adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 107adfc5217SJeff Kirsher { STATS_OFFSET32(mf_tag_discard), 108adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 1090e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_received_hi), 1100e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 1110e898dd7SBarak Witkowski { STATS_OFFSET32(pfc_frames_sent_hi), 1120e898dd7SBarak Witkowski 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 113adfc5217SJeff Kirsher { STATS_OFFSET32(brb_drop_hi), 114adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 115adfc5217SJeff Kirsher { STATS_OFFSET32(brb_truncate_hi), 116adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 117adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_received_hi), 118adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 119adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 120adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 121adfc5217SJeff Kirsher { STATS_OFFSET32(nig_timer_max), 122adfc5217SJeff Kirsher 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 123adfc5217SJeff Kirsher /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 124adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 125adfc5217SJeff Kirsher { STATS_OFFSET32(rx_skb_alloc_failed), 126adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 127adfc5217SJeff Kirsher { STATS_OFFSET32(hw_csum_err), 128adfc5217SJeff Kirsher 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 129adfc5217SJeff Kirsher 130adfc5217SJeff Kirsher { STATS_OFFSET32(total_bytes_transmitted_hi), 131adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bytes" }, 132adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 133adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 134adfc5217SJeff Kirsher { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 135adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 136adfc5217SJeff Kirsher { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 137adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 138adfc5217SJeff Kirsher { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 139adfc5217SJeff Kirsher 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 140adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 141adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 142adfc5217SJeff Kirsher { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 143adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 144adfc5217SJeff Kirsher /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 145adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 146adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 147adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 148adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 149adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_deferred" }, 150adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 151adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 152adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 153adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 154adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 155adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 156adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 157adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 158adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 159adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 160adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 161adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 162adfc5217SJeff Kirsher { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 163adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 164adfc5217SJeff Kirsher /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 165adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 166adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 167adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 168adfc5217SJeff Kirsher { STATS_OFFSET32(etherstatspktsover1522octets_hi), 169adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 170adfc5217SJeff Kirsher { STATS_OFFSET32(pause_frames_sent_hi), 171adfc5217SJeff Kirsher 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 172adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregations_hi), 173adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 174adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 175adfc5217SJeff Kirsher 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 176adfc5217SJeff Kirsher { STATS_OFFSET32(total_tpa_bytes_hi), 1777a752993SAriel Elior 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 1787a752993SAriel Elior { STATS_OFFSET32(recoverable_error), 1797a752993SAriel Elior 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 1807a752993SAriel Elior { STATS_OFFSET32(unrecoverable_error), 1817a752993SAriel Elior 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 182c96bdc0cSDmitry Kravkov { STATS_OFFSET32(driver_filtered_tx_pkt), 183c96bdc0cSDmitry Kravkov 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 184e9939c80SYuval Mintz { STATS_OFFSET32(eee_tx_lpi), 185e9939c80SYuval Mintz 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 186adfc5217SJeff Kirsher }; 187adfc5217SJeff Kirsher 188adfc5217SJeff Kirsher #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 18907ba6af4SMiriam Shitrit 190adfc5217SJeff Kirsher static int bnx2x_get_port_type(struct bnx2x *bp) 191adfc5217SJeff Kirsher { 192adfc5217SJeff Kirsher int port_type; 193adfc5217SJeff Kirsher u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 194adfc5217SJeff Kirsher switch (bp->link_params.phy[phy_idx].media_type) { 195dbef807eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 196dbef807eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 197adfc5217SJeff Kirsher case ETH_PHY_XFP_FIBER: 198adfc5217SJeff Kirsher case ETH_PHY_KR: 199adfc5217SJeff Kirsher case ETH_PHY_CX4: 200adfc5217SJeff Kirsher port_type = PORT_FIBRE; 201adfc5217SJeff Kirsher break; 202adfc5217SJeff Kirsher case ETH_PHY_DA_TWINAX: 203adfc5217SJeff Kirsher port_type = PORT_DA; 204adfc5217SJeff Kirsher break; 205adfc5217SJeff Kirsher case ETH_PHY_BASE_T: 206adfc5217SJeff Kirsher port_type = PORT_TP; 207adfc5217SJeff Kirsher break; 208adfc5217SJeff Kirsher case ETH_PHY_NOT_PRESENT: 209adfc5217SJeff Kirsher port_type = PORT_NONE; 210adfc5217SJeff Kirsher break; 211adfc5217SJeff Kirsher case ETH_PHY_UNSPECIFIED: 212adfc5217SJeff Kirsher default: 213adfc5217SJeff Kirsher port_type = PORT_OTHER; 214adfc5217SJeff Kirsher break; 215adfc5217SJeff Kirsher } 216adfc5217SJeff Kirsher return port_type; 217adfc5217SJeff Kirsher } 218adfc5217SJeff Kirsher 219adfc5217SJeff Kirsher static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 220adfc5217SJeff Kirsher { 221adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 222adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 223adfc5217SJeff Kirsher 224adfc5217SJeff Kirsher /* Dual Media boards present all available port types */ 225adfc5217SJeff Kirsher cmd->supported = bp->port.supported[cfg_idx] | 226adfc5217SJeff Kirsher (bp->port.supported[cfg_idx ^ 1] & 227adfc5217SJeff Kirsher (SUPPORTED_TP | SUPPORTED_FIBRE)); 228adfc5217SJeff Kirsher cmd->advertising = bp->port.advertising[cfg_idx]; 229dbef807eSYuval Mintz if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type == 230dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER) { 231dbef807eSYuval Mintz cmd->supported &= ~(SUPPORTED_10000baseT_Full); 232dbef807eSYuval Mintz cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 233dbef807eSYuval Mintz } 234adfc5217SJeff Kirsher 23559694f00SYuval Mintz if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 23659694f00SYuval Mintz !(bp->flags & MF_FUNC_DIS)) { 237adfc5217SJeff Kirsher cmd->duplex = bp->link_vars.duplex; 238adfc5217SJeff Kirsher 23938298461SYuval Mintz if (IS_MF(bp) && !BP_NOMCP(bp)) 240adfc5217SJeff Kirsher ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 24159694f00SYuval Mintz else 24259694f00SYuval Mintz ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 24338298461SYuval Mintz } else { 24438298461SYuval Mintz cmd->duplex = DUPLEX_UNKNOWN; 24538298461SYuval Mintz ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 24638298461SYuval Mintz } 247adfc5217SJeff Kirsher 248adfc5217SJeff Kirsher cmd->port = bnx2x_get_port_type(bp); 249adfc5217SJeff Kirsher 250adfc5217SJeff Kirsher cmd->phy_address = bp->mdio.prtad; 251adfc5217SJeff Kirsher cmd->transceiver = XCVR_INTERNAL; 252adfc5217SJeff Kirsher 253adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 254adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_ENABLE; 255adfc5217SJeff Kirsher else 256adfc5217SJeff Kirsher cmd->autoneg = AUTONEG_DISABLE; 257adfc5217SJeff Kirsher 2589e7e8399SMintz Yuval /* Publish LP advertised speeds and FC */ 2599e7e8399SMintz Yuval if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 2609e7e8399SMintz Yuval u32 status = bp->link_vars.link_status; 2619e7e8399SMintz Yuval 2629e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Autoneg; 2639e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 2649e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Pause; 2659e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 2669e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_Asym_Pause; 2679e7e8399SMintz Yuval 2689e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 2699e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Half; 2709e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 2719e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10baseT_Full; 2729e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 2739e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Half; 2749e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 2759e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_100baseT_Full; 2769e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 2779e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 2789e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) 2799e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_1000baseT_Full; 2809e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 2819e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 2829e7e8399SMintz Yuval if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) 2839e7e8399SMintz Yuval cmd->lp_advertising |= ADVERTISED_10000baseT_Full; 2849e7e8399SMintz Yuval } 2859e7e8399SMintz Yuval 286adfc5217SJeff Kirsher cmd->maxtxpkt = 0; 287adfc5217SJeff Kirsher cmd->maxrxpkt = 0; 288adfc5217SJeff Kirsher 28951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 290f1deab50SJoe Perches " supported 0x%x advertising 0x%x speed %u\n" 291f1deab50SJoe Perches " duplex %d port %d phy_address %d transceiver %d\n" 292f1deab50SJoe Perches " autoneg %d maxtxpkt %d maxrxpkt %d\n", 293adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 294adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 295adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 296adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 297adfc5217SJeff Kirsher 298adfc5217SJeff Kirsher return 0; 299adfc5217SJeff Kirsher } 300adfc5217SJeff Kirsher 301adfc5217SJeff Kirsher static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 302adfc5217SJeff Kirsher { 303adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 304adfc5217SJeff Kirsher u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 305dbef807eSYuval Mintz u32 speed, phy_idx; 306adfc5217SJeff Kirsher 307adfc5217SJeff Kirsher if (IS_MF_SD(bp)) 308adfc5217SJeff Kirsher return 0; 309adfc5217SJeff Kirsher 31051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 311adfc5217SJeff Kirsher " supported 0x%x advertising 0x%x speed %u\n" 312adfc5217SJeff Kirsher " duplex %d port %d phy_address %d transceiver %d\n" 313adfc5217SJeff Kirsher " autoneg %d maxtxpkt %d maxrxpkt %d\n", 314adfc5217SJeff Kirsher cmd->cmd, cmd->supported, cmd->advertising, 315adfc5217SJeff Kirsher ethtool_cmd_speed(cmd), 316adfc5217SJeff Kirsher cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 317adfc5217SJeff Kirsher cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 318adfc5217SJeff Kirsher 319adfc5217SJeff Kirsher speed = ethtool_cmd_speed(cmd); 320adfc5217SJeff Kirsher 32138298461SYuval Mintz /* If recieved a request for an unknown duplex, assume full*/ 32238298461SYuval Mintz if (cmd->duplex == DUPLEX_UNKNOWN) 32338298461SYuval Mintz cmd->duplex = DUPLEX_FULL; 32438298461SYuval Mintz 325adfc5217SJeff Kirsher if (IS_MF_SI(bp)) { 326adfc5217SJeff Kirsher u32 part; 327adfc5217SJeff Kirsher u32 line_speed = bp->link_vars.line_speed; 328adfc5217SJeff Kirsher 329adfc5217SJeff Kirsher /* use 10G if no link detected */ 330adfc5217SJeff Kirsher if (!line_speed) 331adfc5217SJeff Kirsher line_speed = 10000; 332adfc5217SJeff Kirsher 333adfc5217SJeff Kirsher if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 33451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 33551c1a580SMerav Sicron "To set speed BC %X or higher is required, please upgrade BC\n", 336adfc5217SJeff Kirsher REQ_BC_VER_4_SET_MF_BW); 337adfc5217SJeff Kirsher return -EINVAL; 338adfc5217SJeff Kirsher } 339adfc5217SJeff Kirsher 340adfc5217SJeff Kirsher part = (speed * 100) / line_speed; 341adfc5217SJeff Kirsher 342adfc5217SJeff Kirsher if (line_speed < speed || !part) { 34351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 34451c1a580SMerav Sicron "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 345adfc5217SJeff Kirsher return -EINVAL; 346adfc5217SJeff Kirsher } 347adfc5217SJeff Kirsher 348adfc5217SJeff Kirsher if (bp->state != BNX2X_STATE_OPEN) 349adfc5217SJeff Kirsher /* store value for following "load" */ 350adfc5217SJeff Kirsher bp->pending_max = part; 351adfc5217SJeff Kirsher else 352adfc5217SJeff Kirsher bnx2x_update_max_mf_config(bp, part); 353adfc5217SJeff Kirsher 354adfc5217SJeff Kirsher return 0; 355adfc5217SJeff Kirsher } 356adfc5217SJeff Kirsher 357adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 358adfc5217SJeff Kirsher old_multi_phy_config = bp->link_params.multi_phy_config; 359adfc5217SJeff Kirsher switch (cmd->port) { 360adfc5217SJeff Kirsher case PORT_TP: 361adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_TP) 362adfc5217SJeff Kirsher break; /* no port change */ 363adfc5217SJeff Kirsher 364adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_TP || 365adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_TP)) { 36651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 367adfc5217SJeff Kirsher return -EINVAL; 368adfc5217SJeff Kirsher } 369adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 370adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 371adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 372adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 373adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 374adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 375adfc5217SJeff Kirsher else 376adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 377adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 378adfc5217SJeff Kirsher break; 379adfc5217SJeff Kirsher case PORT_FIBRE: 380bfdb5823SYaniv Rosner case PORT_DA: 381adfc5217SJeff Kirsher if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 382adfc5217SJeff Kirsher break; /* no port change */ 383adfc5217SJeff Kirsher 384adfc5217SJeff Kirsher if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 385adfc5217SJeff Kirsher bp->port.supported[1] & SUPPORTED_FIBRE)) { 38651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 387adfc5217SJeff Kirsher return -EINVAL; 388adfc5217SJeff Kirsher } 389adfc5217SJeff Kirsher bp->link_params.multi_phy_config &= 390adfc5217SJeff Kirsher ~PORT_HW_CFG_PHY_SELECTION_MASK; 391adfc5217SJeff Kirsher if (bp->link_params.multi_phy_config & 392adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SWAPPED_ENABLED) 393adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 394adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 395adfc5217SJeff Kirsher else 396adfc5217SJeff Kirsher bp->link_params.multi_phy_config |= 397adfc5217SJeff Kirsher PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 398adfc5217SJeff Kirsher break; 399adfc5217SJeff Kirsher default: 40051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 401adfc5217SJeff Kirsher return -EINVAL; 402adfc5217SJeff Kirsher } 4032de67439SYuval Mintz /* Save new config in case command complete successfully */ 404adfc5217SJeff Kirsher new_multi_phy_config = bp->link_params.multi_phy_config; 405adfc5217SJeff Kirsher /* Get the new cfg_idx */ 406adfc5217SJeff Kirsher cfg_idx = bnx2x_get_link_cfg_idx(bp); 407adfc5217SJeff Kirsher /* Restore old config in case command failed */ 408adfc5217SJeff Kirsher bp->link_params.multi_phy_config = old_multi_phy_config; 40951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 410adfc5217SJeff Kirsher 411adfc5217SJeff Kirsher if (cmd->autoneg == AUTONEG_ENABLE) { 41275318327SYaniv Rosner u32 an_supported_speed = bp->port.supported[cfg_idx]; 41375318327SYaniv Rosner if (bp->link_params.phy[EXT_PHY1].type == 41475318327SYaniv Rosner PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 41575318327SYaniv Rosner an_supported_speed |= (SUPPORTED_100baseT_Half | 41675318327SYaniv Rosner SUPPORTED_100baseT_Full); 417adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 41851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 419adfc5217SJeff Kirsher return -EINVAL; 420adfc5217SJeff Kirsher } 421adfc5217SJeff Kirsher 422adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 42375318327SYaniv Rosner if (cmd->advertising & ~an_supported_speed) { 42451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 42551c1a580SMerav Sicron "Advertisement parameters are not supported\n"); 4268decf868SDavid S. Miller return -EINVAL; 4278decf868SDavid S. Miller } 428adfc5217SJeff Kirsher 429adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 4308decf868SDavid S. Miller bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 4318decf868SDavid S. Miller bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 432adfc5217SJeff Kirsher cmd->advertising); 4338decf868SDavid S. Miller if (cmd->advertising) { 434adfc5217SJeff Kirsher 4358decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] = 0; 4368decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Half) { 4378decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4388decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 4398decf868SDavid S. Miller } 4408decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_10baseT_Full) 4418decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4428decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 4438decf868SDavid S. Miller 4448decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Full) 4458decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4468decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 4478decf868SDavid S. Miller 4488decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_100baseT_Half) { 4498decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4508decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 4518decf868SDavid S. Miller } 4528decf868SDavid S. Miller if (cmd->advertising & ADVERTISED_1000baseT_Half) { 4538decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4548decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4558decf868SDavid S. Miller } 4568decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_1000baseT_Full | 4578decf868SDavid S. Miller ADVERTISED_1000baseKX_Full)) 4588decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4598decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 4608decf868SDavid S. Miller 4618decf868SDavid S. Miller if (cmd->advertising & (ADVERTISED_10000baseT_Full | 4628decf868SDavid S. Miller ADVERTISED_10000baseKX4_Full | 4638decf868SDavid S. Miller ADVERTISED_10000baseKR_Full)) 4648decf868SDavid S. Miller bp->link_params.speed_cap_mask[cfg_idx] |= 4658decf868SDavid S. Miller PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 4668decf868SDavid S. Miller } 467adfc5217SJeff Kirsher } else { /* forced speed */ 468adfc5217SJeff Kirsher /* advertise the requested speed and duplex if supported */ 469adfc5217SJeff Kirsher switch (speed) { 470adfc5217SJeff Kirsher case SPEED_10: 471adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 472adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 473adfc5217SJeff Kirsher SUPPORTED_10baseT_Full)) { 47451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 475adfc5217SJeff Kirsher "10M full not supported\n"); 476adfc5217SJeff Kirsher return -EINVAL; 477adfc5217SJeff Kirsher } 478adfc5217SJeff Kirsher 479adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Full | 480adfc5217SJeff Kirsher ADVERTISED_TP); 481adfc5217SJeff Kirsher } else { 482adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 483adfc5217SJeff Kirsher SUPPORTED_10baseT_Half)) { 48451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 485adfc5217SJeff Kirsher "10M half not supported\n"); 486adfc5217SJeff Kirsher return -EINVAL; 487adfc5217SJeff Kirsher } 488adfc5217SJeff Kirsher 489adfc5217SJeff Kirsher advertising = (ADVERTISED_10baseT_Half | 490adfc5217SJeff Kirsher ADVERTISED_TP); 491adfc5217SJeff Kirsher } 492adfc5217SJeff Kirsher break; 493adfc5217SJeff Kirsher 494adfc5217SJeff Kirsher case SPEED_100: 495adfc5217SJeff Kirsher if (cmd->duplex == DUPLEX_FULL) { 496adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 497adfc5217SJeff Kirsher SUPPORTED_100baseT_Full)) { 49851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 499adfc5217SJeff Kirsher "100M full not supported\n"); 500adfc5217SJeff Kirsher return -EINVAL; 501adfc5217SJeff Kirsher } 502adfc5217SJeff Kirsher 503adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Full | 504adfc5217SJeff Kirsher ADVERTISED_TP); 505adfc5217SJeff Kirsher } else { 506adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 507adfc5217SJeff Kirsher SUPPORTED_100baseT_Half)) { 50851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 509adfc5217SJeff Kirsher "100M half not supported\n"); 510adfc5217SJeff Kirsher return -EINVAL; 511adfc5217SJeff Kirsher } 512adfc5217SJeff Kirsher 513adfc5217SJeff Kirsher advertising = (ADVERTISED_100baseT_Half | 514adfc5217SJeff Kirsher ADVERTISED_TP); 515adfc5217SJeff Kirsher } 516adfc5217SJeff Kirsher break; 517adfc5217SJeff Kirsher 518adfc5217SJeff Kirsher case SPEED_1000: 519adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 52051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52151c1a580SMerav Sicron "1G half not supported\n"); 522adfc5217SJeff Kirsher return -EINVAL; 523adfc5217SJeff Kirsher } 524adfc5217SJeff Kirsher 525adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & 526adfc5217SJeff Kirsher SUPPORTED_1000baseT_Full)) { 52751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 52851c1a580SMerav Sicron "1G full not supported\n"); 529adfc5217SJeff Kirsher return -EINVAL; 530adfc5217SJeff Kirsher } 531adfc5217SJeff Kirsher 532adfc5217SJeff Kirsher advertising = (ADVERTISED_1000baseT_Full | 533adfc5217SJeff Kirsher ADVERTISED_TP); 534adfc5217SJeff Kirsher break; 535adfc5217SJeff Kirsher 536adfc5217SJeff Kirsher case SPEED_2500: 537adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 53851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 539adfc5217SJeff Kirsher "2.5G half not supported\n"); 540adfc5217SJeff Kirsher return -EINVAL; 541adfc5217SJeff Kirsher } 542adfc5217SJeff Kirsher 543adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 544adfc5217SJeff Kirsher & SUPPORTED_2500baseX_Full)) { 54551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 546adfc5217SJeff Kirsher "2.5G full not supported\n"); 547adfc5217SJeff Kirsher return -EINVAL; 548adfc5217SJeff Kirsher } 549adfc5217SJeff Kirsher 550adfc5217SJeff Kirsher advertising = (ADVERTISED_2500baseX_Full | 551adfc5217SJeff Kirsher ADVERTISED_TP); 552adfc5217SJeff Kirsher break; 553adfc5217SJeff Kirsher 554adfc5217SJeff Kirsher case SPEED_10000: 555adfc5217SJeff Kirsher if (cmd->duplex != DUPLEX_FULL) { 55651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 55751c1a580SMerav Sicron "10G half not supported\n"); 558adfc5217SJeff Kirsher return -EINVAL; 559adfc5217SJeff Kirsher } 560dbef807eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 561adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] 562dbef807eSYuval Mintz & SUPPORTED_10000baseT_Full) || 563dbef807eSYuval Mintz (bp->link_params.phy[phy_idx].media_type == 564dbef807eSYuval Mintz ETH_PHY_SFP_1G_FIBER)) { 56551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 56651c1a580SMerav Sicron "10G full not supported\n"); 567adfc5217SJeff Kirsher return -EINVAL; 568adfc5217SJeff Kirsher } 569adfc5217SJeff Kirsher 570adfc5217SJeff Kirsher advertising = (ADVERTISED_10000baseT_Full | 571adfc5217SJeff Kirsher ADVERTISED_FIBRE); 572adfc5217SJeff Kirsher break; 573adfc5217SJeff Kirsher 574adfc5217SJeff Kirsher default: 57551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 576adfc5217SJeff Kirsher return -EINVAL; 577adfc5217SJeff Kirsher } 578adfc5217SJeff Kirsher 579adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx] = speed; 580adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 581adfc5217SJeff Kirsher bp->port.advertising[cfg_idx] = advertising; 582adfc5217SJeff Kirsher } 583adfc5217SJeff Kirsher 58451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 585f1deab50SJoe Perches " req_duplex %d advertising 0x%x\n", 586adfc5217SJeff Kirsher bp->link_params.req_line_speed[cfg_idx], 587adfc5217SJeff Kirsher bp->link_params.req_duplex[cfg_idx], 588adfc5217SJeff Kirsher bp->port.advertising[cfg_idx]); 589adfc5217SJeff Kirsher 590adfc5217SJeff Kirsher /* Set new config */ 591adfc5217SJeff Kirsher bp->link_params.multi_phy_config = new_multi_phy_config; 592adfc5217SJeff Kirsher if (netif_running(dev)) { 593adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 594adfc5217SJeff Kirsher bnx2x_link_set(bp); 595adfc5217SJeff Kirsher } 596adfc5217SJeff Kirsher 597adfc5217SJeff Kirsher return 0; 598adfc5217SJeff Kirsher } 599adfc5217SJeff Kirsher 60007ba6af4SMiriam Shitrit #define DUMP_ALL_PRESETS 0x1FFF 60107ba6af4SMiriam Shitrit #define DUMP_MAX_PRESETS 13 602adfc5217SJeff Kirsher 60307ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 604adfc5217SJeff Kirsher { 605adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 60607ba6af4SMiriam Shitrit return dump_num_registers[0][preset-1]; 607adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 60807ba6af4SMiriam Shitrit return dump_num_registers[1][preset-1]; 609adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 61007ba6af4SMiriam Shitrit return dump_num_registers[2][preset-1]; 611adfc5217SJeff Kirsher else if (CHIP_IS_E3A0(bp)) 61207ba6af4SMiriam Shitrit return dump_num_registers[3][preset-1]; 613adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 61407ba6af4SMiriam Shitrit return dump_num_registers[4][preset-1]; 615adfc5217SJeff Kirsher else 61607ba6af4SMiriam Shitrit return 0; 617adfc5217SJeff Kirsher } 618adfc5217SJeff Kirsher 61907ba6af4SMiriam Shitrit static int __bnx2x_get_regs_len(struct bnx2x *bp) 62007ba6af4SMiriam Shitrit { 62107ba6af4SMiriam Shitrit u32 preset_idx; 62207ba6af4SMiriam Shitrit int regdump_len = 0; 62307ba6af4SMiriam Shitrit 62407ba6af4SMiriam Shitrit /* Calculate the total preset regs length */ 62507ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 62607ba6af4SMiriam Shitrit regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 62707ba6af4SMiriam Shitrit 62807ba6af4SMiriam Shitrit return regdump_len; 62907ba6af4SMiriam Shitrit } 63007ba6af4SMiriam Shitrit 63107ba6af4SMiriam Shitrit static int bnx2x_get_regs_len(struct net_device *dev) 63207ba6af4SMiriam Shitrit { 63307ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 63407ba6af4SMiriam Shitrit int regdump_len = 0; 63507ba6af4SMiriam Shitrit 63607ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_regs_len(bp); 63707ba6af4SMiriam Shitrit regdump_len *= 4; 63807ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 63907ba6af4SMiriam Shitrit 64007ba6af4SMiriam Shitrit return regdump_len; 64107ba6af4SMiriam Shitrit } 64207ba6af4SMiriam Shitrit 64307ba6af4SMiriam Shitrit #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 64407ba6af4SMiriam Shitrit #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 64507ba6af4SMiriam Shitrit #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 64607ba6af4SMiriam Shitrit #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 64707ba6af4SMiriam Shitrit #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 64807ba6af4SMiriam Shitrit 64907ba6af4SMiriam Shitrit #define IS_REG_IN_PRESET(presets, idx) \ 65007ba6af4SMiriam Shitrit ((presets & (1 << (idx-1))) == (1 << (idx-1))) 65107ba6af4SMiriam Shitrit 652adfc5217SJeff Kirsher /******* Paged registers info selectors ********/ 6531191cb83SEric Dumazet static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 654adfc5217SJeff Kirsher { 655adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 656adfc5217SJeff Kirsher return page_vals_e2; 657adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 658adfc5217SJeff Kirsher return page_vals_e3; 659adfc5217SJeff Kirsher else 660adfc5217SJeff Kirsher return NULL; 661adfc5217SJeff Kirsher } 662adfc5217SJeff Kirsher 6631191cb83SEric Dumazet static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 664adfc5217SJeff Kirsher { 665adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 666adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E2; 667adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 668adfc5217SJeff Kirsher return PAGE_MODE_VALUES_E3; 669adfc5217SJeff Kirsher else 670adfc5217SJeff Kirsher return 0; 671adfc5217SJeff Kirsher } 672adfc5217SJeff Kirsher 6731191cb83SEric Dumazet static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 674adfc5217SJeff Kirsher { 675adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 676adfc5217SJeff Kirsher return page_write_regs_e2; 677adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 678adfc5217SJeff Kirsher return page_write_regs_e3; 679adfc5217SJeff Kirsher else 680adfc5217SJeff Kirsher return NULL; 681adfc5217SJeff Kirsher } 682adfc5217SJeff Kirsher 6831191cb83SEric Dumazet static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 684adfc5217SJeff Kirsher { 685adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 686adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E2; 687adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 688adfc5217SJeff Kirsher return PAGE_WRITE_REGS_E3; 689adfc5217SJeff Kirsher else 690adfc5217SJeff Kirsher return 0; 691adfc5217SJeff Kirsher } 692adfc5217SJeff Kirsher 6931191cb83SEric Dumazet static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 694adfc5217SJeff Kirsher { 695adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 696adfc5217SJeff Kirsher return page_read_regs_e2; 697adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 698adfc5217SJeff Kirsher return page_read_regs_e3; 699adfc5217SJeff Kirsher else 700adfc5217SJeff Kirsher return NULL; 701adfc5217SJeff Kirsher } 702adfc5217SJeff Kirsher 7031191cb83SEric Dumazet static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 704adfc5217SJeff Kirsher { 705adfc5217SJeff Kirsher if (CHIP_IS_E2(bp)) 706adfc5217SJeff Kirsher return PAGE_READ_REGS_E2; 707adfc5217SJeff Kirsher else if (CHIP_IS_E3(bp)) 708adfc5217SJeff Kirsher return PAGE_READ_REGS_E3; 709adfc5217SJeff Kirsher else 710adfc5217SJeff Kirsher return 0; 711adfc5217SJeff Kirsher } 712adfc5217SJeff Kirsher 71307ba6af4SMiriam Shitrit static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 71407ba6af4SMiriam Shitrit const struct reg_addr *reg_info) 715adfc5217SJeff Kirsher { 71607ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 71707ba6af4SMiriam Shitrit return IS_E1_REG(reg_info->chips); 71807ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 71907ba6af4SMiriam Shitrit return IS_E1H_REG(reg_info->chips); 72007ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 72107ba6af4SMiriam Shitrit return IS_E2_REG(reg_info->chips); 72207ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 72307ba6af4SMiriam Shitrit return IS_E3A0_REG(reg_info->chips); 72407ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 72507ba6af4SMiriam Shitrit return IS_E3B0_REG(reg_info->chips); 72607ba6af4SMiriam Shitrit else 72707ba6af4SMiriam Shitrit return false; 728adfc5217SJeff Kirsher } 729adfc5217SJeff Kirsher 73007ba6af4SMiriam Shitrit 73107ba6af4SMiriam Shitrit static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 73207ba6af4SMiriam Shitrit const struct wreg_addr *wreg_info) 733adfc5217SJeff Kirsher { 73407ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 73507ba6af4SMiriam Shitrit return IS_E1_REG(wreg_info->chips); 73607ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 73707ba6af4SMiriam Shitrit return IS_E1H_REG(wreg_info->chips); 73807ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 73907ba6af4SMiriam Shitrit return IS_E2_REG(wreg_info->chips); 74007ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 74107ba6af4SMiriam Shitrit return IS_E3A0_REG(wreg_info->chips); 74207ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 74307ba6af4SMiriam Shitrit return IS_E3B0_REG(wreg_info->chips); 74407ba6af4SMiriam Shitrit else 74507ba6af4SMiriam Shitrit return false; 746adfc5217SJeff Kirsher } 747adfc5217SJeff Kirsher 748adfc5217SJeff Kirsher /** 749adfc5217SJeff Kirsher * bnx2x_read_pages_regs - read "paged" registers 750adfc5217SJeff Kirsher * 751adfc5217SJeff Kirsher * @bp device handle 752adfc5217SJeff Kirsher * @p output buffer 753adfc5217SJeff Kirsher * 7542de67439SYuval Mintz * Reads "paged" memories: memories that may only be read by first writing to a 7552de67439SYuval Mintz * specific address ("write address") and then reading from a specific address 7562de67439SYuval Mintz * ("read address"). There may be more than one write address per "page" and 7572de67439SYuval Mintz * more than one read address per write address. 758adfc5217SJeff Kirsher */ 75907ba6af4SMiriam Shitrit static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 760adfc5217SJeff Kirsher { 761adfc5217SJeff Kirsher u32 i, j, k, n; 76207ba6af4SMiriam Shitrit 763adfc5217SJeff Kirsher /* addresses of the paged registers */ 764adfc5217SJeff Kirsher const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 765adfc5217SJeff Kirsher /* number of paged registers */ 766adfc5217SJeff Kirsher int num_pages = __bnx2x_get_page_reg_num(bp); 767adfc5217SJeff Kirsher /* write addresses */ 768adfc5217SJeff Kirsher const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 769adfc5217SJeff Kirsher /* number of write addresses */ 770adfc5217SJeff Kirsher int write_num = __bnx2x_get_page_write_num(bp); 771adfc5217SJeff Kirsher /* read addresses info */ 772adfc5217SJeff Kirsher const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 773adfc5217SJeff Kirsher /* number of read addresses */ 774adfc5217SJeff Kirsher int read_num = __bnx2x_get_page_read_num(bp); 77507ba6af4SMiriam Shitrit u32 addr, size; 776adfc5217SJeff Kirsher 777adfc5217SJeff Kirsher for (i = 0; i < num_pages; i++) { 778adfc5217SJeff Kirsher for (j = 0; j < write_num; j++) { 779adfc5217SJeff Kirsher REG_WR(bp, write_addr[j], page_addr[i]); 78007ba6af4SMiriam Shitrit 78107ba6af4SMiriam Shitrit for (k = 0; k < read_num; k++) { 78207ba6af4SMiriam Shitrit if (IS_REG_IN_PRESET(read_addr[k].presets, 78307ba6af4SMiriam Shitrit preset)) { 78407ba6af4SMiriam Shitrit size = read_addr[k].size; 78507ba6af4SMiriam Shitrit for (n = 0; n < size; n++) { 78607ba6af4SMiriam Shitrit addr = read_addr[k].addr + n*4; 78707ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr); 788adfc5217SJeff Kirsher } 789adfc5217SJeff Kirsher } 790adfc5217SJeff Kirsher } 79107ba6af4SMiriam Shitrit } 79207ba6af4SMiriam Shitrit } 79307ba6af4SMiriam Shitrit } 79407ba6af4SMiriam Shitrit 79507ba6af4SMiriam Shitrit static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 79607ba6af4SMiriam Shitrit { 79707ba6af4SMiriam Shitrit u32 i, j, addr; 79807ba6af4SMiriam Shitrit const struct wreg_addr *wreg_addr_p = NULL; 79907ba6af4SMiriam Shitrit 80007ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) 80107ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1; 80207ba6af4SMiriam Shitrit else if (CHIP_IS_E1H(bp)) 80307ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e1h; 80407ba6af4SMiriam Shitrit else if (CHIP_IS_E2(bp)) 80507ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e2; 80607ba6af4SMiriam Shitrit else if (CHIP_IS_E3A0(bp)) 80707ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3; 80807ba6af4SMiriam Shitrit else if (CHIP_IS_E3B0(bp)) 80907ba6af4SMiriam Shitrit wreg_addr_p = &wreg_addr_e3b0; 81007ba6af4SMiriam Shitrit 81107ba6af4SMiriam Shitrit /* Read the idle_chk registers */ 81207ba6af4SMiriam Shitrit for (i = 0; i < IDLE_REGS_COUNT; i++) { 81307ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 81407ba6af4SMiriam Shitrit IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 81507ba6af4SMiriam Shitrit for (j = 0; j < idle_reg_addrs[i].size; j++) 81607ba6af4SMiriam Shitrit *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 81707ba6af4SMiriam Shitrit } 81807ba6af4SMiriam Shitrit } 81907ba6af4SMiriam Shitrit 82007ba6af4SMiriam Shitrit /* Read the regular registers */ 82107ba6af4SMiriam Shitrit for (i = 0; i < REGS_COUNT; i++) { 82207ba6af4SMiriam Shitrit if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 82307ba6af4SMiriam Shitrit IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 82407ba6af4SMiriam Shitrit for (j = 0; j < reg_addrs[i].size; j++) 82507ba6af4SMiriam Shitrit *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 82607ba6af4SMiriam Shitrit } 82707ba6af4SMiriam Shitrit } 82807ba6af4SMiriam Shitrit 82907ba6af4SMiriam Shitrit /* Read the CAM registers */ 83007ba6af4SMiriam Shitrit if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 83107ba6af4SMiriam Shitrit IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 83207ba6af4SMiriam Shitrit for (i = 0; i < wreg_addr_p->size; i++) { 83307ba6af4SMiriam Shitrit *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 83407ba6af4SMiriam Shitrit 83507ba6af4SMiriam Shitrit /* In case of wreg_addr register, read additional 83607ba6af4SMiriam Shitrit registers from read_regs array 83707ba6af4SMiriam Shitrit */ 83807ba6af4SMiriam Shitrit for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 83907ba6af4SMiriam Shitrit addr = *(wreg_addr_p->read_regs); 84007ba6af4SMiriam Shitrit *p++ = REG_RD(bp, addr + j*4); 84107ba6af4SMiriam Shitrit } 84207ba6af4SMiriam Shitrit } 84307ba6af4SMiriam Shitrit } 84407ba6af4SMiriam Shitrit 84507ba6af4SMiriam Shitrit /* Paged registers are supported in E2 & E3 only */ 84607ba6af4SMiriam Shitrit if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 84707ba6af4SMiriam Shitrit /* Read "paged" registes */ 84807ba6af4SMiriam Shitrit bnx2x_read_pages_regs(bp, p, preset); 84907ba6af4SMiriam Shitrit } 85007ba6af4SMiriam Shitrit 85107ba6af4SMiriam Shitrit return 0; 85207ba6af4SMiriam Shitrit } 853adfc5217SJeff Kirsher 8541191cb83SEric Dumazet static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 855adfc5217SJeff Kirsher { 85607ba6af4SMiriam Shitrit u32 preset_idx; 857adfc5217SJeff Kirsher 85807ba6af4SMiriam Shitrit /* Read all registers, by reading all preset registers */ 85907ba6af4SMiriam Shitrit for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 86007ba6af4SMiriam Shitrit /* Skip presets with IOR */ 86107ba6af4SMiriam Shitrit if ((preset_idx == 2) || 86207ba6af4SMiriam Shitrit (preset_idx == 5) || 86307ba6af4SMiriam Shitrit (preset_idx == 8) || 86407ba6af4SMiriam Shitrit (preset_idx == 11)) 86507ba6af4SMiriam Shitrit continue; 86607ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, preset_idx); 86707ba6af4SMiriam Shitrit p += __bnx2x_get_preset_regs_len(bp, preset_idx); 86807ba6af4SMiriam Shitrit } 869adfc5217SJeff Kirsher } 870adfc5217SJeff Kirsher 871adfc5217SJeff Kirsher static void bnx2x_get_regs(struct net_device *dev, 872adfc5217SJeff Kirsher struct ethtool_regs *regs, void *_p) 873adfc5217SJeff Kirsher { 874adfc5217SJeff Kirsher u32 *p = _p; 875adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 87607ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 877adfc5217SJeff Kirsher 87807ba6af4SMiriam Shitrit regs->version = 2; 879adfc5217SJeff Kirsher memset(p, 0, regs->len); 880adfc5217SJeff Kirsher 881adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 882adfc5217SJeff Kirsher return; 883adfc5217SJeff Kirsher 884adfc5217SJeff Kirsher /* Disable parity attentions as long as following dump may 885adfc5217SJeff Kirsher * cause false alarms by reading never written registers. We 886adfc5217SJeff Kirsher * will re-enable parity attentions right after the dump. 887adfc5217SJeff Kirsher */ 88807ba6af4SMiriam Shitrit 88907ba6af4SMiriam Shitrit /* Disable parity on path 0 */ 89007ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 891adfc5217SJeff Kirsher bnx2x_disable_blocks_parity(bp); 892adfc5217SJeff Kirsher 89307ba6af4SMiriam Shitrit /* Disable parity on path 1 */ 89407ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 89507ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 896adfc5217SJeff Kirsher 89707ba6af4SMiriam Shitrit /* Return to current function */ 89807ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 899adfc5217SJeff Kirsher 90007ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 90107ba6af4SMiriam Shitrit dump_hdr.preset = DUMP_ALL_PRESETS; 90207ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 90307ba6af4SMiriam Shitrit 90407ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 90507ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 90607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 90707ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 90807ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 90907ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 91007ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 91107ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 91207ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 91307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 91407ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 91507ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 91607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 91707ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 91807ba6af4SMiriam Shitrit } 91907ba6af4SMiriam Shitrit 92007ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 92107ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 922adfc5217SJeff Kirsher 923adfc5217SJeff Kirsher /* Actually read the registers */ 924adfc5217SJeff Kirsher __bnx2x_get_regs(bp, p); 925adfc5217SJeff Kirsher 92607ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 0 */ 92707ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 928adfc5217SJeff Kirsher bnx2x_clear_blocks_parity(bp); 929adfc5217SJeff Kirsher bnx2x_enable_blocks_parity(bp); 93007ba6af4SMiriam Shitrit 93107ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 1 */ 93207ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 93307ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 93407ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 93507ba6af4SMiriam Shitrit 93607ba6af4SMiriam Shitrit /* Return to current function */ 93707ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 93807ba6af4SMiriam Shitrit } 93907ba6af4SMiriam Shitrit 94007ba6af4SMiriam Shitrit static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 94107ba6af4SMiriam Shitrit { 94207ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 94307ba6af4SMiriam Shitrit int regdump_len = 0; 94407ba6af4SMiriam Shitrit 94507ba6af4SMiriam Shitrit regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 94607ba6af4SMiriam Shitrit regdump_len *= 4; 94707ba6af4SMiriam Shitrit regdump_len += sizeof(struct dump_header); 94807ba6af4SMiriam Shitrit 94907ba6af4SMiriam Shitrit return regdump_len; 95007ba6af4SMiriam Shitrit } 95107ba6af4SMiriam Shitrit 95207ba6af4SMiriam Shitrit static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 95307ba6af4SMiriam Shitrit { 95407ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 95507ba6af4SMiriam Shitrit 95607ba6af4SMiriam Shitrit /* Use the ethtool_dump "flag" field as the dump preset index */ 95707ba6af4SMiriam Shitrit bp->dump_preset_idx = val->flag; 95807ba6af4SMiriam Shitrit return 0; 95907ba6af4SMiriam Shitrit } 96007ba6af4SMiriam Shitrit 96107ba6af4SMiriam Shitrit static int bnx2x_get_dump_flag(struct net_device *dev, 96207ba6af4SMiriam Shitrit struct ethtool_dump *dump) 96307ba6af4SMiriam Shitrit { 96407ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 96507ba6af4SMiriam Shitrit 96607ba6af4SMiriam Shitrit /* Calculate the requested preset idx length */ 96707ba6af4SMiriam Shitrit dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 96807ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 96907ba6af4SMiriam Shitrit bp->dump_preset_idx, dump->len); 97007ba6af4SMiriam Shitrit 97107ba6af4SMiriam Shitrit dump->flag = ETHTOOL_GET_DUMP_DATA; 97207ba6af4SMiriam Shitrit return 0; 97307ba6af4SMiriam Shitrit } 97407ba6af4SMiriam Shitrit 97507ba6af4SMiriam Shitrit static int bnx2x_get_dump_data(struct net_device *dev, 97607ba6af4SMiriam Shitrit struct ethtool_dump *dump, 97707ba6af4SMiriam Shitrit void *buffer) 97807ba6af4SMiriam Shitrit { 97907ba6af4SMiriam Shitrit u32 *p = buffer; 98007ba6af4SMiriam Shitrit struct bnx2x *bp = netdev_priv(dev); 98107ba6af4SMiriam Shitrit struct dump_header dump_hdr = {0}; 98207ba6af4SMiriam Shitrit 98307ba6af4SMiriam Shitrit memset(p, 0, dump->len); 98407ba6af4SMiriam Shitrit 98507ba6af4SMiriam Shitrit /* Disable parity attentions as long as following dump may 98607ba6af4SMiriam Shitrit * cause false alarms by reading never written registers. We 98707ba6af4SMiriam Shitrit * will re-enable parity attentions right after the dump. 98807ba6af4SMiriam Shitrit */ 98907ba6af4SMiriam Shitrit 99007ba6af4SMiriam Shitrit /* Disable parity on path 0 */ 99107ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 99207ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 99307ba6af4SMiriam Shitrit 99407ba6af4SMiriam Shitrit /* Disable parity on path 1 */ 99507ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 99607ba6af4SMiriam Shitrit bnx2x_disable_blocks_parity(bp); 99707ba6af4SMiriam Shitrit 99807ba6af4SMiriam Shitrit /* Return to current function */ 99907ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 100007ba6af4SMiriam Shitrit 100107ba6af4SMiriam Shitrit dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 100207ba6af4SMiriam Shitrit dump_hdr.preset = bp->dump_preset_idx; 100307ba6af4SMiriam Shitrit dump_hdr.version = BNX2X_DUMP_VERSION; 100407ba6af4SMiriam Shitrit 100507ba6af4SMiriam Shitrit DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 100607ba6af4SMiriam Shitrit 100707ba6af4SMiriam Shitrit /* dump_meta_data presents OR of CHIP and PATH. */ 100807ba6af4SMiriam Shitrit if (CHIP_IS_E1(bp)) { 100907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1; 101007ba6af4SMiriam Shitrit } else if (CHIP_IS_E1H(bp)) { 101107ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 101207ba6af4SMiriam Shitrit } else if (CHIP_IS_E2(bp)) { 101307ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 101407ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 101507ba6af4SMiriam Shitrit } else if (CHIP_IS_E3A0(bp)) { 101607ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 101707ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 101807ba6af4SMiriam Shitrit } else if (CHIP_IS_E3B0(bp)) { 101907ba6af4SMiriam Shitrit dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 102007ba6af4SMiriam Shitrit (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 102107ba6af4SMiriam Shitrit } 102207ba6af4SMiriam Shitrit 102307ba6af4SMiriam Shitrit memcpy(p, &dump_hdr, sizeof(struct dump_header)); 102407ba6af4SMiriam Shitrit p += dump_hdr.header_size + 1; 102507ba6af4SMiriam Shitrit 102607ba6af4SMiriam Shitrit /* Actually read the registers */ 102707ba6af4SMiriam Shitrit __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 102807ba6af4SMiriam Shitrit 102907ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 0 */ 103007ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 0); 103107ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 103207ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 103307ba6af4SMiriam Shitrit 103407ba6af4SMiriam Shitrit /* Re-enable parity attentions on path 1 */ 103507ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, 1); 103607ba6af4SMiriam Shitrit bnx2x_clear_blocks_parity(bp); 103707ba6af4SMiriam Shitrit bnx2x_enable_blocks_parity(bp); 103807ba6af4SMiriam Shitrit 103907ba6af4SMiriam Shitrit /* Return to current function */ 104007ba6af4SMiriam Shitrit bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 104107ba6af4SMiriam Shitrit 104207ba6af4SMiriam Shitrit return 0; 1043adfc5217SJeff Kirsher } 1044adfc5217SJeff Kirsher 1045adfc5217SJeff Kirsher static void bnx2x_get_drvinfo(struct net_device *dev, 1046adfc5217SJeff Kirsher struct ethtool_drvinfo *info) 1047adfc5217SJeff Kirsher { 1048adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1049adfc5217SJeff Kirsher 105068aad78cSRick Jones strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 105168aad78cSRick Jones strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1052adfc5217SJeff Kirsher 10538ca5e17eSAriel Elior bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 10548ca5e17eSAriel Elior 105568aad78cSRick Jones strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1056adfc5217SJeff Kirsher info->n_stats = BNX2X_NUM_STATS; 1057cf2c1df6SMerav Sicron info->testinfo_len = BNX2X_NUM_TESTS(bp); 1058adfc5217SJeff Kirsher info->eedump_len = bp->common.flash_size; 1059adfc5217SJeff Kirsher info->regdump_len = bnx2x_get_regs_len(dev); 1060adfc5217SJeff Kirsher } 1061adfc5217SJeff Kirsher 1062adfc5217SJeff Kirsher static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1063adfc5217SJeff Kirsher { 1064adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1065adfc5217SJeff Kirsher 1066adfc5217SJeff Kirsher if (bp->flags & NO_WOL_FLAG) { 1067adfc5217SJeff Kirsher wol->supported = 0; 1068adfc5217SJeff Kirsher wol->wolopts = 0; 1069adfc5217SJeff Kirsher } else { 1070adfc5217SJeff Kirsher wol->supported = WAKE_MAGIC; 1071adfc5217SJeff Kirsher if (bp->wol) 1072adfc5217SJeff Kirsher wol->wolopts = WAKE_MAGIC; 1073adfc5217SJeff Kirsher else 1074adfc5217SJeff Kirsher wol->wolopts = 0; 1075adfc5217SJeff Kirsher } 1076adfc5217SJeff Kirsher memset(&wol->sopass, 0, sizeof(wol->sopass)); 1077adfc5217SJeff Kirsher } 1078adfc5217SJeff Kirsher 1079adfc5217SJeff Kirsher static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1080adfc5217SJeff Kirsher { 1081adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1082adfc5217SJeff Kirsher 108351c1a580SMerav Sicron if (wol->wolopts & ~WAKE_MAGIC) { 10842de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1085adfc5217SJeff Kirsher return -EINVAL; 108651c1a580SMerav Sicron } 1087adfc5217SJeff Kirsher 1088adfc5217SJeff Kirsher if (wol->wolopts & WAKE_MAGIC) { 108951c1a580SMerav Sicron if (bp->flags & NO_WOL_FLAG) { 10902de67439SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1091adfc5217SJeff Kirsher return -EINVAL; 109251c1a580SMerav Sicron } 1093adfc5217SJeff Kirsher bp->wol = 1; 1094adfc5217SJeff Kirsher } else 1095adfc5217SJeff Kirsher bp->wol = 0; 1096adfc5217SJeff Kirsher 1097adfc5217SJeff Kirsher return 0; 1098adfc5217SJeff Kirsher } 1099adfc5217SJeff Kirsher 1100adfc5217SJeff Kirsher static u32 bnx2x_get_msglevel(struct net_device *dev) 1101adfc5217SJeff Kirsher { 1102adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1103adfc5217SJeff Kirsher 1104adfc5217SJeff Kirsher return bp->msg_enable; 1105adfc5217SJeff Kirsher } 1106adfc5217SJeff Kirsher 1107adfc5217SJeff Kirsher static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1108adfc5217SJeff Kirsher { 1109adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1110adfc5217SJeff Kirsher 1111adfc5217SJeff Kirsher if (capable(CAP_NET_ADMIN)) { 1112adfc5217SJeff Kirsher /* dump MCP trace */ 1113ad5afc89SAriel Elior if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1114adfc5217SJeff Kirsher bnx2x_fw_dump_lvl(bp, KERN_INFO); 1115adfc5217SJeff Kirsher bp->msg_enable = level; 1116adfc5217SJeff Kirsher } 1117adfc5217SJeff Kirsher } 1118adfc5217SJeff Kirsher 1119adfc5217SJeff Kirsher static int bnx2x_nway_reset(struct net_device *dev) 1120adfc5217SJeff Kirsher { 1121adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1122adfc5217SJeff Kirsher 1123adfc5217SJeff Kirsher if (!bp->port.pmf) 1124adfc5217SJeff Kirsher return 0; 1125adfc5217SJeff Kirsher 1126adfc5217SJeff Kirsher if (netif_running(dev)) { 1127adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 11285d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1129adfc5217SJeff Kirsher bnx2x_link_set(bp); 1130adfc5217SJeff Kirsher } 1131adfc5217SJeff Kirsher 1132adfc5217SJeff Kirsher return 0; 1133adfc5217SJeff Kirsher } 1134adfc5217SJeff Kirsher 1135adfc5217SJeff Kirsher static u32 bnx2x_get_link(struct net_device *dev) 1136adfc5217SJeff Kirsher { 1137adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1138adfc5217SJeff Kirsher 1139adfc5217SJeff Kirsher if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1140adfc5217SJeff Kirsher return 0; 1141adfc5217SJeff Kirsher 1142adfc5217SJeff Kirsher return bp->link_vars.link_up; 1143adfc5217SJeff Kirsher } 1144adfc5217SJeff Kirsher 1145adfc5217SJeff Kirsher static int bnx2x_get_eeprom_len(struct net_device *dev) 1146adfc5217SJeff Kirsher { 1147adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1148adfc5217SJeff Kirsher 1149adfc5217SJeff Kirsher return bp->common.flash_size; 1150adfc5217SJeff Kirsher } 1151adfc5217SJeff Kirsher 1152f16da43bSAriel Elior /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had 1153f16da43bSAriel Elior * we done things the other way around, if two pfs from the same port would 1154f16da43bSAriel Elior * attempt to access nvram at the same time, we could run into a scenario such 1155f16da43bSAriel Elior * as: 1156f16da43bSAriel Elior * pf A takes the port lock. 1157f16da43bSAriel Elior * pf B succeeds in taking the same lock since they are from the same port. 1158f16da43bSAriel Elior * pf A takes the per pf misc lock. Performs eeprom access. 1159f16da43bSAriel Elior * pf A finishes. Unlocks the per pf misc lock. 1160f16da43bSAriel Elior * Pf B takes the lock and proceeds to perform it's own access. 1161f16da43bSAriel Elior * pf A unlocks the per port lock, while pf B is still working (!). 1162f16da43bSAriel Elior * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 11632de67439SYuval Mintz * access corrupted by pf B) 1164f16da43bSAriel Elior */ 1165adfc5217SJeff Kirsher static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1166adfc5217SJeff Kirsher { 1167adfc5217SJeff Kirsher int port = BP_PORT(bp); 1168adfc5217SJeff Kirsher int count, i; 1169f16da43bSAriel Elior u32 val; 1170f16da43bSAriel Elior 1171f16da43bSAriel Elior /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1172f16da43bSAriel Elior bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1173adfc5217SJeff Kirsher 1174adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1175adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1176adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1177adfc5217SJeff Kirsher count *= 100; 1178adfc5217SJeff Kirsher 1179adfc5217SJeff Kirsher /* request access to nvram interface */ 1180adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1181adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1182adfc5217SJeff Kirsher 1183adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1184adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1185adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1186adfc5217SJeff Kirsher break; 1187adfc5217SJeff Kirsher 1188adfc5217SJeff Kirsher udelay(5); 1189adfc5217SJeff Kirsher } 1190adfc5217SJeff Kirsher 1191adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 119251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 119351c1a580SMerav Sicron "cannot get access to nvram interface\n"); 1194adfc5217SJeff Kirsher return -EBUSY; 1195adfc5217SJeff Kirsher } 1196adfc5217SJeff Kirsher 1197adfc5217SJeff Kirsher return 0; 1198adfc5217SJeff Kirsher } 1199adfc5217SJeff Kirsher 1200adfc5217SJeff Kirsher static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1201adfc5217SJeff Kirsher { 1202adfc5217SJeff Kirsher int port = BP_PORT(bp); 1203adfc5217SJeff Kirsher int count, i; 1204f16da43bSAriel Elior u32 val; 1205adfc5217SJeff Kirsher 1206adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1207adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1208adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1209adfc5217SJeff Kirsher count *= 100; 1210adfc5217SJeff Kirsher 1211adfc5217SJeff Kirsher /* relinquish nvram interface */ 1212adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1213adfc5217SJeff Kirsher (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1214adfc5217SJeff Kirsher 1215adfc5217SJeff Kirsher for (i = 0; i < count*10; i++) { 1216adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1217adfc5217SJeff Kirsher if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1218adfc5217SJeff Kirsher break; 1219adfc5217SJeff Kirsher 1220adfc5217SJeff Kirsher udelay(5); 1221adfc5217SJeff Kirsher } 1222adfc5217SJeff Kirsher 1223adfc5217SJeff Kirsher if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 122451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 122551c1a580SMerav Sicron "cannot free access to nvram interface\n"); 1226adfc5217SJeff Kirsher return -EBUSY; 1227adfc5217SJeff Kirsher } 1228adfc5217SJeff Kirsher 1229f16da43bSAriel Elior /* release HW lock: protect against other PFs in PF Direct Assignment */ 1230f16da43bSAriel Elior bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1231adfc5217SJeff Kirsher return 0; 1232adfc5217SJeff Kirsher } 1233adfc5217SJeff Kirsher 1234adfc5217SJeff Kirsher static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1235adfc5217SJeff Kirsher { 1236adfc5217SJeff Kirsher u32 val; 1237adfc5217SJeff Kirsher 1238adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1239adfc5217SJeff Kirsher 1240adfc5217SJeff Kirsher /* enable both bits, even on read */ 1241adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1242adfc5217SJeff Kirsher (val | MCPR_NVM_ACCESS_ENABLE_EN | 1243adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1244adfc5217SJeff Kirsher } 1245adfc5217SJeff Kirsher 1246adfc5217SJeff Kirsher static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1247adfc5217SJeff Kirsher { 1248adfc5217SJeff Kirsher u32 val; 1249adfc5217SJeff Kirsher 1250adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1251adfc5217SJeff Kirsher 1252adfc5217SJeff Kirsher /* disable both bits, even after read */ 1253adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1254adfc5217SJeff Kirsher (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1255adfc5217SJeff Kirsher MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1256adfc5217SJeff Kirsher } 1257adfc5217SJeff Kirsher 1258adfc5217SJeff Kirsher static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1259adfc5217SJeff Kirsher u32 cmd_flags) 1260adfc5217SJeff Kirsher { 1261adfc5217SJeff Kirsher int count, i, rc; 1262adfc5217SJeff Kirsher u32 val; 1263adfc5217SJeff Kirsher 1264adfc5217SJeff Kirsher /* build the command word */ 1265adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1266adfc5217SJeff Kirsher 1267adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1268adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1269adfc5217SJeff Kirsher 1270adfc5217SJeff Kirsher /* address of the NVRAM to read from */ 1271adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1272adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1273adfc5217SJeff Kirsher 1274adfc5217SJeff Kirsher /* issue a read command */ 1275adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1276adfc5217SJeff Kirsher 1277adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1278adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1279adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1280adfc5217SJeff Kirsher count *= 100; 1281adfc5217SJeff Kirsher 1282adfc5217SJeff Kirsher /* wait for completion */ 1283adfc5217SJeff Kirsher *ret_val = 0; 1284adfc5217SJeff Kirsher rc = -EBUSY; 1285adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1286adfc5217SJeff Kirsher udelay(5); 1287adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1288adfc5217SJeff Kirsher 1289adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1290adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1291adfc5217SJeff Kirsher /* we read nvram data in cpu order 1292adfc5217SJeff Kirsher * but ethtool sees it as an array of bytes 129307ba6af4SMiriam Shitrit * converting to big-endian will do the work 129407ba6af4SMiriam Shitrit */ 1295adfc5217SJeff Kirsher *ret_val = cpu_to_be32(val); 1296adfc5217SJeff Kirsher rc = 0; 1297adfc5217SJeff Kirsher break; 1298adfc5217SJeff Kirsher } 1299adfc5217SJeff Kirsher } 130051c1a580SMerav Sicron if (rc == -EBUSY) 130151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 130251c1a580SMerav Sicron "nvram read timeout expired\n"); 1303adfc5217SJeff Kirsher return rc; 1304adfc5217SJeff Kirsher } 1305adfc5217SJeff Kirsher 1306adfc5217SJeff Kirsher static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1307adfc5217SJeff Kirsher int buf_size) 1308adfc5217SJeff Kirsher { 1309adfc5217SJeff Kirsher int rc; 1310adfc5217SJeff Kirsher u32 cmd_flags; 1311adfc5217SJeff Kirsher __be32 val; 1312adfc5217SJeff Kirsher 1313adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 131451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1315adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1316adfc5217SJeff Kirsher offset, buf_size); 1317adfc5217SJeff Kirsher return -EINVAL; 1318adfc5217SJeff Kirsher } 1319adfc5217SJeff Kirsher 1320adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 132151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 132251c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1323adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1324adfc5217SJeff Kirsher return -EINVAL; 1325adfc5217SJeff Kirsher } 1326adfc5217SJeff Kirsher 1327adfc5217SJeff Kirsher /* request access to nvram interface */ 1328adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1329adfc5217SJeff Kirsher if (rc) 1330adfc5217SJeff Kirsher return rc; 1331adfc5217SJeff Kirsher 1332adfc5217SJeff Kirsher /* enable access to nvram interface */ 1333adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1334adfc5217SJeff Kirsher 1335adfc5217SJeff Kirsher /* read the first word(s) */ 1336adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1337adfc5217SJeff Kirsher while ((buf_size > sizeof(u32)) && (rc == 0)) { 1338adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1339adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1340adfc5217SJeff Kirsher 1341adfc5217SJeff Kirsher /* advance to the next dword */ 1342adfc5217SJeff Kirsher offset += sizeof(u32); 1343adfc5217SJeff Kirsher ret_buf += sizeof(u32); 1344adfc5217SJeff Kirsher buf_size -= sizeof(u32); 1345adfc5217SJeff Kirsher cmd_flags = 0; 1346adfc5217SJeff Kirsher } 1347adfc5217SJeff Kirsher 1348adfc5217SJeff Kirsher if (rc == 0) { 1349adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1350adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1351adfc5217SJeff Kirsher memcpy(ret_buf, &val, 4); 1352adfc5217SJeff Kirsher } 1353adfc5217SJeff Kirsher 1354adfc5217SJeff Kirsher /* disable access to nvram interface */ 1355adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1356adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1357adfc5217SJeff Kirsher 1358adfc5217SJeff Kirsher return rc; 1359adfc5217SJeff Kirsher } 1360adfc5217SJeff Kirsher 1361adfc5217SJeff Kirsher static int bnx2x_get_eeprom(struct net_device *dev, 1362adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1363adfc5217SJeff Kirsher { 1364adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1365adfc5217SJeff Kirsher int rc; 1366adfc5217SJeff Kirsher 136751c1a580SMerav Sicron if (!netif_running(dev)) { 136851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 136951c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1370adfc5217SJeff Kirsher return -EAGAIN; 137151c1a580SMerav Sicron } 1372adfc5217SJeff Kirsher 137351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1374f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1375adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1376adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1377adfc5217SJeff Kirsher 1378adfc5217SJeff Kirsher /* parameters already validated in ethtool_get_eeprom */ 1379adfc5217SJeff Kirsher 1380adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1381adfc5217SJeff Kirsher 1382adfc5217SJeff Kirsher return rc; 1383adfc5217SJeff Kirsher } 1384adfc5217SJeff Kirsher 138524ea818eSYuval Mintz static int bnx2x_get_module_eeprom(struct net_device *dev, 138624ea818eSYuval Mintz struct ethtool_eeprom *ee, 138724ea818eSYuval Mintz u8 *data) 138824ea818eSYuval Mintz { 138924ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 139024ea818eSYuval Mintz int rc = 0, phy_idx; 139124ea818eSYuval Mintz u8 *user_data = data; 139224ea818eSYuval Mintz int remaining_len = ee->len, xfer_size; 139324ea818eSYuval Mintz unsigned int page_off = ee->offset; 139424ea818eSYuval Mintz 139524ea818eSYuval Mintz if (!netif_running(dev)) { 139624ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 139724ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 139824ea818eSYuval Mintz return -EAGAIN; 139924ea818eSYuval Mintz } 140024ea818eSYuval Mintz 140124ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 140224ea818eSYuval Mintz bnx2x_acquire_phy_lock(bp); 140324ea818eSYuval Mintz while (!rc && remaining_len > 0) { 140424ea818eSYuval Mintz xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ? 140524ea818eSYuval Mintz SFP_EEPROM_PAGE_SIZE : remaining_len; 140624ea818eSYuval Mintz rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 140724ea818eSYuval Mintz &bp->link_params, 140824ea818eSYuval Mintz page_off, 140924ea818eSYuval Mintz xfer_size, 141024ea818eSYuval Mintz user_data); 141124ea818eSYuval Mintz remaining_len -= xfer_size; 141224ea818eSYuval Mintz user_data += xfer_size; 141324ea818eSYuval Mintz page_off += xfer_size; 141424ea818eSYuval Mintz } 141524ea818eSYuval Mintz 141624ea818eSYuval Mintz bnx2x_release_phy_lock(bp); 141724ea818eSYuval Mintz return rc; 141824ea818eSYuval Mintz } 141924ea818eSYuval Mintz 142024ea818eSYuval Mintz static int bnx2x_get_module_info(struct net_device *dev, 142124ea818eSYuval Mintz struct ethtool_modinfo *modinfo) 142224ea818eSYuval Mintz { 142324ea818eSYuval Mintz struct bnx2x *bp = netdev_priv(dev); 142424ea818eSYuval Mintz int phy_idx; 142524ea818eSYuval Mintz if (!netif_running(dev)) { 142624ea818eSYuval Mintz DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 142724ea818eSYuval Mintz "cannot access eeprom when the interface is down\n"); 142824ea818eSYuval Mintz return -EAGAIN; 142924ea818eSYuval Mintz } 143024ea818eSYuval Mintz 143124ea818eSYuval Mintz phy_idx = bnx2x_get_cur_phy_idx(bp); 143224ea818eSYuval Mintz switch (bp->link_params.phy[phy_idx].media_type) { 143324ea818eSYuval Mintz case ETH_PHY_SFPP_10G_FIBER: 143424ea818eSYuval Mintz case ETH_PHY_SFP_1G_FIBER: 143524ea818eSYuval Mintz case ETH_PHY_DA_TWINAX: 143624ea818eSYuval Mintz modinfo->type = ETH_MODULE_SFF_8079; 143724ea818eSYuval Mintz modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 143824ea818eSYuval Mintz return 0; 143924ea818eSYuval Mintz default: 144024ea818eSYuval Mintz return -EOPNOTSUPP; 144124ea818eSYuval Mintz } 144224ea818eSYuval Mintz } 144324ea818eSYuval Mintz 1444adfc5217SJeff Kirsher static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1445adfc5217SJeff Kirsher u32 cmd_flags) 1446adfc5217SJeff Kirsher { 1447adfc5217SJeff Kirsher int count, i, rc; 1448adfc5217SJeff Kirsher 1449adfc5217SJeff Kirsher /* build the command word */ 1450adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1451adfc5217SJeff Kirsher 1452adfc5217SJeff Kirsher /* need to clear DONE bit separately */ 1453adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1454adfc5217SJeff Kirsher 1455adfc5217SJeff Kirsher /* write the data */ 1456adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1457adfc5217SJeff Kirsher 1458adfc5217SJeff Kirsher /* address of the NVRAM to write to */ 1459adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1460adfc5217SJeff Kirsher (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1461adfc5217SJeff Kirsher 1462adfc5217SJeff Kirsher /* issue the write command */ 1463adfc5217SJeff Kirsher REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1464adfc5217SJeff Kirsher 1465adfc5217SJeff Kirsher /* adjust timeout for emulation/FPGA */ 1466adfc5217SJeff Kirsher count = BNX2X_NVRAM_TIMEOUT_COUNT; 1467adfc5217SJeff Kirsher if (CHIP_REV_IS_SLOW(bp)) 1468adfc5217SJeff Kirsher count *= 100; 1469adfc5217SJeff Kirsher 1470adfc5217SJeff Kirsher /* wait for completion */ 1471adfc5217SJeff Kirsher rc = -EBUSY; 1472adfc5217SJeff Kirsher for (i = 0; i < count; i++) { 1473adfc5217SJeff Kirsher udelay(5); 1474adfc5217SJeff Kirsher val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1475adfc5217SJeff Kirsher if (val & MCPR_NVM_COMMAND_DONE) { 1476adfc5217SJeff Kirsher rc = 0; 1477adfc5217SJeff Kirsher break; 1478adfc5217SJeff Kirsher } 1479adfc5217SJeff Kirsher } 1480adfc5217SJeff Kirsher 148151c1a580SMerav Sicron if (rc == -EBUSY) 148251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 148351c1a580SMerav Sicron "nvram write timeout expired\n"); 1484adfc5217SJeff Kirsher return rc; 1485adfc5217SJeff Kirsher } 1486adfc5217SJeff Kirsher 1487adfc5217SJeff Kirsher #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1488adfc5217SJeff Kirsher 1489adfc5217SJeff Kirsher static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1490adfc5217SJeff Kirsher int buf_size) 1491adfc5217SJeff Kirsher { 1492adfc5217SJeff Kirsher int rc; 1493adfc5217SJeff Kirsher u32 cmd_flags; 1494adfc5217SJeff Kirsher u32 align_offset; 1495adfc5217SJeff Kirsher __be32 val; 1496adfc5217SJeff Kirsher 1497adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 149851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 149951c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1500adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1501adfc5217SJeff Kirsher return -EINVAL; 1502adfc5217SJeff Kirsher } 1503adfc5217SJeff Kirsher 1504adfc5217SJeff Kirsher /* request access to nvram interface */ 1505adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1506adfc5217SJeff Kirsher if (rc) 1507adfc5217SJeff Kirsher return rc; 1508adfc5217SJeff Kirsher 1509adfc5217SJeff Kirsher /* enable access to nvram interface */ 1510adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1511adfc5217SJeff Kirsher 1512adfc5217SJeff Kirsher cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1513adfc5217SJeff Kirsher align_offset = (offset & ~0x03); 1514adfc5217SJeff Kirsher rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); 1515adfc5217SJeff Kirsher 1516adfc5217SJeff Kirsher if (rc == 0) { 1517adfc5217SJeff Kirsher val &= ~(0xff << BYTE_OFFSET(offset)); 1518adfc5217SJeff Kirsher val |= (*data_buf << BYTE_OFFSET(offset)); 1519adfc5217SJeff Kirsher 1520adfc5217SJeff Kirsher /* nvram data is returned as an array of bytes 152107ba6af4SMiriam Shitrit * convert it back to cpu order 152207ba6af4SMiriam Shitrit */ 1523adfc5217SJeff Kirsher val = be32_to_cpu(val); 1524adfc5217SJeff Kirsher 1525adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1526adfc5217SJeff Kirsher cmd_flags); 1527adfc5217SJeff Kirsher } 1528adfc5217SJeff Kirsher 1529adfc5217SJeff Kirsher /* disable access to nvram interface */ 1530adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1531adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1532adfc5217SJeff Kirsher 1533adfc5217SJeff Kirsher return rc; 1534adfc5217SJeff Kirsher } 1535adfc5217SJeff Kirsher 1536adfc5217SJeff Kirsher static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1537adfc5217SJeff Kirsher int buf_size) 1538adfc5217SJeff Kirsher { 1539adfc5217SJeff Kirsher int rc; 1540adfc5217SJeff Kirsher u32 cmd_flags; 1541adfc5217SJeff Kirsher u32 val; 1542adfc5217SJeff Kirsher u32 written_so_far; 1543adfc5217SJeff Kirsher 1544adfc5217SJeff Kirsher if (buf_size == 1) /* ethtool */ 1545adfc5217SJeff Kirsher return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1546adfc5217SJeff Kirsher 1547adfc5217SJeff Kirsher if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 154851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1549adfc5217SJeff Kirsher "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1550adfc5217SJeff Kirsher offset, buf_size); 1551adfc5217SJeff Kirsher return -EINVAL; 1552adfc5217SJeff Kirsher } 1553adfc5217SJeff Kirsher 1554adfc5217SJeff Kirsher if (offset + buf_size > bp->common.flash_size) { 155551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 155651c1a580SMerav Sicron "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1557adfc5217SJeff Kirsher offset, buf_size, bp->common.flash_size); 1558adfc5217SJeff Kirsher return -EINVAL; 1559adfc5217SJeff Kirsher } 1560adfc5217SJeff Kirsher 1561adfc5217SJeff Kirsher /* request access to nvram interface */ 1562adfc5217SJeff Kirsher rc = bnx2x_acquire_nvram_lock(bp); 1563adfc5217SJeff Kirsher if (rc) 1564adfc5217SJeff Kirsher return rc; 1565adfc5217SJeff Kirsher 1566adfc5217SJeff Kirsher /* enable access to nvram interface */ 1567adfc5217SJeff Kirsher bnx2x_enable_nvram_access(bp); 1568adfc5217SJeff Kirsher 1569adfc5217SJeff Kirsher written_so_far = 0; 1570adfc5217SJeff Kirsher cmd_flags = MCPR_NVM_COMMAND_FIRST; 1571adfc5217SJeff Kirsher while ((written_so_far < buf_size) && (rc == 0)) { 1572adfc5217SJeff Kirsher if (written_so_far == (buf_size - sizeof(u32))) 1573adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1574adfc5217SJeff Kirsher else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1575adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_LAST; 1576adfc5217SJeff Kirsher else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1577adfc5217SJeff Kirsher cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1578adfc5217SJeff Kirsher 1579adfc5217SJeff Kirsher memcpy(&val, data_buf, 4); 1580adfc5217SJeff Kirsher 1581adfc5217SJeff Kirsher rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1582adfc5217SJeff Kirsher 1583adfc5217SJeff Kirsher /* advance to the next dword */ 1584adfc5217SJeff Kirsher offset += sizeof(u32); 1585adfc5217SJeff Kirsher data_buf += sizeof(u32); 1586adfc5217SJeff Kirsher written_so_far += sizeof(u32); 1587adfc5217SJeff Kirsher cmd_flags = 0; 1588adfc5217SJeff Kirsher } 1589adfc5217SJeff Kirsher 1590adfc5217SJeff Kirsher /* disable access to nvram interface */ 1591adfc5217SJeff Kirsher bnx2x_disable_nvram_access(bp); 1592adfc5217SJeff Kirsher bnx2x_release_nvram_lock(bp); 1593adfc5217SJeff Kirsher 1594adfc5217SJeff Kirsher return rc; 1595adfc5217SJeff Kirsher } 1596adfc5217SJeff Kirsher 1597adfc5217SJeff Kirsher static int bnx2x_set_eeprom(struct net_device *dev, 1598adfc5217SJeff Kirsher struct ethtool_eeprom *eeprom, u8 *eebuf) 1599adfc5217SJeff Kirsher { 1600adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1601adfc5217SJeff Kirsher int port = BP_PORT(bp); 1602adfc5217SJeff Kirsher int rc = 0; 1603adfc5217SJeff Kirsher u32 ext_phy_config; 160451c1a580SMerav Sicron if (!netif_running(dev)) { 160551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 160651c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 1607adfc5217SJeff Kirsher return -EAGAIN; 160851c1a580SMerav Sicron } 1609adfc5217SJeff Kirsher 161051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1611f1deab50SJoe Perches " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1612adfc5217SJeff Kirsher eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1613adfc5217SJeff Kirsher eeprom->len, eeprom->len); 1614adfc5217SJeff Kirsher 1615adfc5217SJeff Kirsher /* parameters already validated in ethtool_set_eeprom */ 1616adfc5217SJeff Kirsher 1617adfc5217SJeff Kirsher /* PHY eeprom can be accessed only by the PMF */ 1618adfc5217SJeff Kirsher if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 161951c1a580SMerav Sicron !bp->port.pmf) { 162051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 162151c1a580SMerav Sicron "wrong magic or interface is not pmf\n"); 1622adfc5217SJeff Kirsher return -EINVAL; 162351c1a580SMerav Sicron } 1624adfc5217SJeff Kirsher 1625adfc5217SJeff Kirsher ext_phy_config = 1626adfc5217SJeff Kirsher SHMEM_RD(bp, 1627adfc5217SJeff Kirsher dev_info.port_hw_config[port].external_phy_config); 1628adfc5217SJeff Kirsher 1629adfc5217SJeff Kirsher if (eeprom->magic == 0x50485950) { 1630adfc5217SJeff Kirsher /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1631adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1632adfc5217SJeff Kirsher 1633adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1634adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1635adfc5217SJeff Kirsher &bp->link_vars, 0); 1636adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1637adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1638adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1639adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_HIGH, port); 1640adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1641adfc5217SJeff Kirsher bnx2x_link_report(bp); 1642adfc5217SJeff Kirsher 1643adfc5217SJeff Kirsher } else if (eeprom->magic == 0x50485952) { 1644adfc5217SJeff Kirsher /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1645adfc5217SJeff Kirsher if (bp->state == BNX2X_STATE_OPEN) { 1646adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1647adfc5217SJeff Kirsher rc |= bnx2x_link_reset(&bp->link_params, 1648adfc5217SJeff Kirsher &bp->link_vars, 1); 1649adfc5217SJeff Kirsher 1650adfc5217SJeff Kirsher rc |= bnx2x_phy_init(&bp->link_params, 1651adfc5217SJeff Kirsher &bp->link_vars); 1652adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1653adfc5217SJeff Kirsher bnx2x_calc_fc_adv(bp); 1654adfc5217SJeff Kirsher } 1655adfc5217SJeff Kirsher } else if (eeprom->magic == 0x53985943) { 1656adfc5217SJeff Kirsher /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1657adfc5217SJeff Kirsher if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1658adfc5217SJeff Kirsher PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1659adfc5217SJeff Kirsher 1660adfc5217SJeff Kirsher /* DSP Remove Download Mode */ 1661adfc5217SJeff Kirsher bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1662adfc5217SJeff Kirsher MISC_REGISTERS_GPIO_LOW, port); 1663adfc5217SJeff Kirsher 1664adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 1665adfc5217SJeff Kirsher 1666adfc5217SJeff Kirsher bnx2x_sfx7101_sp_sw_reset(bp, 1667adfc5217SJeff Kirsher &bp->link_params.phy[EXT_PHY1]); 1668adfc5217SJeff Kirsher 1669adfc5217SJeff Kirsher /* wait 0.5 sec to allow it to run */ 1670adfc5217SJeff Kirsher msleep(500); 1671adfc5217SJeff Kirsher bnx2x_ext_phy_hw_reset(bp, port); 1672adfc5217SJeff Kirsher msleep(500); 1673adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 1674adfc5217SJeff Kirsher } 1675adfc5217SJeff Kirsher } else 1676adfc5217SJeff Kirsher rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1677adfc5217SJeff Kirsher 1678adfc5217SJeff Kirsher return rc; 1679adfc5217SJeff Kirsher } 1680adfc5217SJeff Kirsher 1681adfc5217SJeff Kirsher static int bnx2x_get_coalesce(struct net_device *dev, 1682adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1683adfc5217SJeff Kirsher { 1684adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1685adfc5217SJeff Kirsher 1686adfc5217SJeff Kirsher memset(coal, 0, sizeof(struct ethtool_coalesce)); 1687adfc5217SJeff Kirsher 1688adfc5217SJeff Kirsher coal->rx_coalesce_usecs = bp->rx_ticks; 1689adfc5217SJeff Kirsher coal->tx_coalesce_usecs = bp->tx_ticks; 1690adfc5217SJeff Kirsher 1691adfc5217SJeff Kirsher return 0; 1692adfc5217SJeff Kirsher } 1693adfc5217SJeff Kirsher 1694adfc5217SJeff Kirsher static int bnx2x_set_coalesce(struct net_device *dev, 1695adfc5217SJeff Kirsher struct ethtool_coalesce *coal) 1696adfc5217SJeff Kirsher { 1697adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1698adfc5217SJeff Kirsher 1699adfc5217SJeff Kirsher bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1700adfc5217SJeff Kirsher if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1701adfc5217SJeff Kirsher bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1702adfc5217SJeff Kirsher 1703adfc5217SJeff Kirsher bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1704adfc5217SJeff Kirsher if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1705adfc5217SJeff Kirsher bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1706adfc5217SJeff Kirsher 1707adfc5217SJeff Kirsher if (netif_running(dev)) 1708adfc5217SJeff Kirsher bnx2x_update_coalesce(bp); 1709adfc5217SJeff Kirsher 1710adfc5217SJeff Kirsher return 0; 1711adfc5217SJeff Kirsher } 1712adfc5217SJeff Kirsher 1713adfc5217SJeff Kirsher static void bnx2x_get_ringparam(struct net_device *dev, 1714adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1715adfc5217SJeff Kirsher { 1716adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1717adfc5217SJeff Kirsher 1718adfc5217SJeff Kirsher ering->rx_max_pending = MAX_RX_AVAIL; 1719adfc5217SJeff Kirsher 1720adfc5217SJeff Kirsher if (bp->rx_ring_size) 1721adfc5217SJeff Kirsher ering->rx_pending = bp->rx_ring_size; 1722adfc5217SJeff Kirsher else 1723adfc5217SJeff Kirsher ering->rx_pending = MAX_RX_AVAIL; 1724adfc5217SJeff Kirsher 1725a3348722SBarak Witkowski ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1726adfc5217SJeff Kirsher ering->tx_pending = bp->tx_ring_size; 1727adfc5217SJeff Kirsher } 1728adfc5217SJeff Kirsher 1729adfc5217SJeff Kirsher static int bnx2x_set_ringparam(struct net_device *dev, 1730adfc5217SJeff Kirsher struct ethtool_ringparam *ering) 1731adfc5217SJeff Kirsher { 1732adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1733adfc5217SJeff Kirsher 173404c46736SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 173504c46736SYuval Mintz "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 173604c46736SYuval Mintz ering->rx_pending, ering->tx_pending); 173704c46736SYuval Mintz 1738adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 173951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 174051c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 1741adfc5217SJeff Kirsher return -EAGAIN; 1742adfc5217SJeff Kirsher } 1743adfc5217SJeff Kirsher 1744adfc5217SJeff Kirsher if ((ering->rx_pending > MAX_RX_AVAIL) || 1745adfc5217SJeff Kirsher (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1746adfc5217SJeff Kirsher MIN_RX_SIZE_TPA)) || 1747a3348722SBarak Witkowski (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) || 174851c1a580SMerav Sicron (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 174951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1750adfc5217SJeff Kirsher return -EINVAL; 175151c1a580SMerav Sicron } 1752adfc5217SJeff Kirsher 1753adfc5217SJeff Kirsher bp->rx_ring_size = ering->rx_pending; 1754adfc5217SJeff Kirsher bp->tx_ring_size = ering->tx_pending; 1755adfc5217SJeff Kirsher 1756adfc5217SJeff Kirsher return bnx2x_reload_if_running(dev); 1757adfc5217SJeff Kirsher } 1758adfc5217SJeff Kirsher 1759adfc5217SJeff Kirsher static void bnx2x_get_pauseparam(struct net_device *dev, 1760adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1761adfc5217SJeff Kirsher { 1762adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1763adfc5217SJeff Kirsher int cfg_idx = bnx2x_get_link_cfg_idx(bp); 17649e7e8399SMintz Yuval int cfg_reg; 17659e7e8399SMintz Yuval 1766adfc5217SJeff Kirsher epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1767adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO); 1768adfc5217SJeff Kirsher 17699e7e8399SMintz Yuval if (!epause->autoneg) 1770241fb5d2SYuval Mintz cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 17719e7e8399SMintz Yuval else 17729e7e8399SMintz Yuval cfg_reg = bp->link_params.req_fc_auto_adv; 17739e7e8399SMintz Yuval 17749e7e8399SMintz Yuval epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1775adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_RX); 17769e7e8399SMintz Yuval epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1777adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_TX); 1778adfc5217SJeff Kirsher 177951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1780f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1781adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1782adfc5217SJeff Kirsher } 1783adfc5217SJeff Kirsher 1784adfc5217SJeff Kirsher static int bnx2x_set_pauseparam(struct net_device *dev, 1785adfc5217SJeff Kirsher struct ethtool_pauseparam *epause) 1786adfc5217SJeff Kirsher { 1787adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 1788adfc5217SJeff Kirsher u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1789adfc5217SJeff Kirsher if (IS_MF(bp)) 1790adfc5217SJeff Kirsher return 0; 1791adfc5217SJeff Kirsher 179251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1793f1deab50SJoe Perches " autoneg %d rx_pause %d tx_pause %d\n", 1794adfc5217SJeff Kirsher epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1795adfc5217SJeff Kirsher 1796adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1797adfc5217SJeff Kirsher 1798adfc5217SJeff Kirsher if (epause->rx_pause) 1799adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1800adfc5217SJeff Kirsher 1801adfc5217SJeff Kirsher if (epause->tx_pause) 1802adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1803adfc5217SJeff Kirsher 1804adfc5217SJeff Kirsher if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1805adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1806adfc5217SJeff Kirsher 1807adfc5217SJeff Kirsher if (epause->autoneg) { 1808adfc5217SJeff Kirsher if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 180951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1810adfc5217SJeff Kirsher return -EINVAL; 1811adfc5217SJeff Kirsher } 1812adfc5217SJeff Kirsher 1813adfc5217SJeff Kirsher if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1814adfc5217SJeff Kirsher bp->link_params.req_flow_ctrl[cfg_idx] = 1815adfc5217SJeff Kirsher BNX2X_FLOW_CTRL_AUTO; 1816adfc5217SJeff Kirsher } 18175cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE; 18185cd75f0cSYaniv Rosner if (epause->rx_pause) 18195cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 18205cd75f0cSYaniv Rosner 18215cd75f0cSYaniv Rosner if (epause->tx_pause) 18225cd75f0cSYaniv Rosner bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1823adfc5217SJeff Kirsher } 1824adfc5217SJeff Kirsher 182551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 1826adfc5217SJeff Kirsher "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1827adfc5217SJeff Kirsher 1828adfc5217SJeff Kirsher if (netif_running(dev)) { 1829adfc5217SJeff Kirsher bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1830adfc5217SJeff Kirsher bnx2x_link_set(bp); 1831adfc5217SJeff Kirsher } 1832adfc5217SJeff Kirsher 1833adfc5217SJeff Kirsher return 0; 1834adfc5217SJeff Kirsher } 1835adfc5217SJeff Kirsher 18365889335cSMerav Sicron static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 1837cf2c1df6SMerav Sicron "register_test (offline) ", 1838cf2c1df6SMerav Sicron "memory_test (offline) ", 1839cf2c1df6SMerav Sicron "int_loopback_test (offline)", 1840cf2c1df6SMerav Sicron "ext_loopback_test (offline)", 1841cf2c1df6SMerav Sicron "nvram_test (online) ", 1842cf2c1df6SMerav Sicron "interrupt_test (online) ", 1843cf2c1df6SMerav Sicron "link_test (online) " 1844adfc5217SJeff Kirsher }; 1845adfc5217SJeff Kirsher 1846e9939c80SYuval Mintz static u32 bnx2x_eee_to_adv(u32 eee_adv) 1847e9939c80SYuval Mintz { 1848e9939c80SYuval Mintz u32 modes = 0; 1849e9939c80SYuval Mintz 1850e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_100M_ADV) 1851e9939c80SYuval Mintz modes |= ADVERTISED_100baseT_Full; 1852e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_1G_ADV) 1853e9939c80SYuval Mintz modes |= ADVERTISED_1000baseT_Full; 1854e9939c80SYuval Mintz if (eee_adv & SHMEM_EEE_10G_ADV) 1855e9939c80SYuval Mintz modes |= ADVERTISED_10000baseT_Full; 1856e9939c80SYuval Mintz 1857e9939c80SYuval Mintz return modes; 1858e9939c80SYuval Mintz } 1859e9939c80SYuval Mintz 1860e9939c80SYuval Mintz static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 1861e9939c80SYuval Mintz { 1862e9939c80SYuval Mintz u32 eee_adv = 0; 1863e9939c80SYuval Mintz if (modes & ADVERTISED_100baseT_Full) 1864e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_100M_ADV; 1865e9939c80SYuval Mintz if (modes & ADVERTISED_1000baseT_Full) 1866e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_1G_ADV; 1867e9939c80SYuval Mintz if (modes & ADVERTISED_10000baseT_Full) 1868e9939c80SYuval Mintz eee_adv |= SHMEM_EEE_10G_ADV; 1869e9939c80SYuval Mintz 1870e9939c80SYuval Mintz return eee_adv << shift; 1871e9939c80SYuval Mintz } 1872e9939c80SYuval Mintz 1873e9939c80SYuval Mintz static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 1874e9939c80SYuval Mintz { 1875e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1876e9939c80SYuval Mintz u32 eee_cfg; 1877e9939c80SYuval Mintz 1878e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1879e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1880e9939c80SYuval Mintz return -EOPNOTSUPP; 1881e9939c80SYuval Mintz } 1882e9939c80SYuval Mintz 188308e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1884e9939c80SYuval Mintz 1885e9939c80SYuval Mintz edata->supported = 1886e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 1887e9939c80SYuval Mintz SHMEM_EEE_SUPPORTED_SHIFT); 1888e9939c80SYuval Mintz 1889e9939c80SYuval Mintz edata->advertised = 1890e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 1891e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1892e9939c80SYuval Mintz edata->lp_advertised = 1893e9939c80SYuval Mintz bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 1894e9939c80SYuval Mintz SHMEM_EEE_LP_ADV_STATUS_SHIFT); 1895e9939c80SYuval Mintz 1896e9939c80SYuval Mintz /* SHMEM value is in 16u units --> Convert to 1u units. */ 1897e9939c80SYuval Mintz edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 1898e9939c80SYuval Mintz 1899e9939c80SYuval Mintz edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 1900e9939c80SYuval Mintz edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 1901e9939c80SYuval Mintz edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 1902e9939c80SYuval Mintz 1903e9939c80SYuval Mintz return 0; 1904e9939c80SYuval Mintz } 1905e9939c80SYuval Mintz 1906e9939c80SYuval Mintz static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 1907e9939c80SYuval Mintz { 1908e9939c80SYuval Mintz struct bnx2x *bp = netdev_priv(dev); 1909e9939c80SYuval Mintz u32 eee_cfg; 1910e9939c80SYuval Mintz u32 advertised; 1911e9939c80SYuval Mintz 1912e9939c80SYuval Mintz if (IS_MF(bp)) 1913e9939c80SYuval Mintz return 0; 1914e9939c80SYuval Mintz 1915e9939c80SYuval Mintz if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 1916e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 1917e9939c80SYuval Mintz return -EOPNOTSUPP; 1918e9939c80SYuval Mintz } 1919e9939c80SYuval Mintz 192008e9acc2SYuval Mintz eee_cfg = bp->link_vars.eee_status; 1921e9939c80SYuval Mintz 1922e9939c80SYuval Mintz if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 1923e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 1924e9939c80SYuval Mintz return -EOPNOTSUPP; 1925e9939c80SYuval Mintz } 1926e9939c80SYuval Mintz 1927e9939c80SYuval Mintz advertised = bnx2x_adv_to_eee(edata->advertised, 1928e9939c80SYuval Mintz SHMEM_EEE_ADV_STATUS_SHIFT); 1929e9939c80SYuval Mintz if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 1930e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1931efc7ce03SMasanari Iida "Direct manipulation of EEE advertisement is not supported\n"); 1932e9939c80SYuval Mintz return -EINVAL; 1933e9939c80SYuval Mintz } 1934e9939c80SYuval Mintz 1935e9939c80SYuval Mintz if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 1936e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1937e9939c80SYuval Mintz "Maximal Tx Lpi timer supported is %x(u)\n", 1938e9939c80SYuval Mintz EEE_MODE_TIMER_MASK); 1939e9939c80SYuval Mintz return -EINVAL; 1940e9939c80SYuval Mintz } 1941e9939c80SYuval Mintz if (edata->tx_lpi_enabled && 1942e9939c80SYuval Mintz (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 1943e9939c80SYuval Mintz DP(BNX2X_MSG_ETHTOOL, 1944e9939c80SYuval Mintz "Minimal Tx Lpi timer supported is %d(u)\n", 1945e9939c80SYuval Mintz EEE_MODE_NVRAM_AGGRESSIVE_TIME); 1946e9939c80SYuval Mintz return -EINVAL; 1947e9939c80SYuval Mintz } 1948e9939c80SYuval Mintz 1949e9939c80SYuval Mintz /* All is well; Apply changes*/ 1950e9939c80SYuval Mintz if (edata->eee_enabled) 1951e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 1952e9939c80SYuval Mintz else 1953e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 1954e9939c80SYuval Mintz 1955e9939c80SYuval Mintz if (edata->tx_lpi_enabled) 1956e9939c80SYuval Mintz bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 1957e9939c80SYuval Mintz else 1958e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 1959e9939c80SYuval Mintz 1960e9939c80SYuval Mintz bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 1961e9939c80SYuval Mintz bp->link_params.eee_mode |= (edata->tx_lpi_timer & 1962e9939c80SYuval Mintz EEE_MODE_TIMER_MASK) | 1963e9939c80SYuval Mintz EEE_MODE_OVERRIDE_NVRAM | 1964e9939c80SYuval Mintz EEE_MODE_OUTPUT_TIME; 1965e9939c80SYuval Mintz 1966e9939c80SYuval Mintz /* Restart link to propogate changes */ 1967e9939c80SYuval Mintz if (netif_running(dev)) { 1968e9939c80SYuval Mintz bnx2x_stats_handle(bp, STATS_EVENT_STOP); 19695d07d868SYuval Mintz bnx2x_force_link_reset(bp); 1970e9939c80SYuval Mintz bnx2x_link_set(bp); 1971e9939c80SYuval Mintz } 1972e9939c80SYuval Mintz 1973e9939c80SYuval Mintz return 0; 1974e9939c80SYuval Mintz } 1975e9939c80SYuval Mintz 1976adfc5217SJeff Kirsher enum { 1977adfc5217SJeff Kirsher BNX2X_CHIP_E1_OFST = 0, 1978adfc5217SJeff Kirsher BNX2X_CHIP_E1H_OFST, 1979adfc5217SJeff Kirsher BNX2X_CHIP_E2_OFST, 1980adfc5217SJeff Kirsher BNX2X_CHIP_E3_OFST, 1981adfc5217SJeff Kirsher BNX2X_CHIP_E3B0_OFST, 1982adfc5217SJeff Kirsher BNX2X_CHIP_MAX_OFST 1983adfc5217SJeff Kirsher }; 1984adfc5217SJeff Kirsher 1985adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 1986adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 1987adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 1988adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 1989adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 1990adfc5217SJeff Kirsher 1991adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 1992adfc5217SJeff Kirsher #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 1993adfc5217SJeff Kirsher 1994adfc5217SJeff Kirsher static int bnx2x_test_registers(struct bnx2x *bp) 1995adfc5217SJeff Kirsher { 1996adfc5217SJeff Kirsher int idx, i, rc = -ENODEV; 1997adfc5217SJeff Kirsher u32 wr_val = 0, hw; 1998adfc5217SJeff Kirsher int port = BP_PORT(bp); 1999adfc5217SJeff Kirsher static const struct { 2000adfc5217SJeff Kirsher u32 hw; 2001adfc5217SJeff Kirsher u32 offset0; 2002adfc5217SJeff Kirsher u32 offset1; 2003adfc5217SJeff Kirsher u32 mask; 2004adfc5217SJeff Kirsher } reg_tbl[] = { 2005adfc5217SJeff Kirsher /* 0 */ { BNX2X_CHIP_MASK_ALL, 2006adfc5217SJeff Kirsher BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2007adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2008adfc5217SJeff Kirsher DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2009adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X, 2010adfc5217SJeff Kirsher HC_REG_AGG_INT_0, 4, 0x000003ff }, 2011adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2012adfc5217SJeff Kirsher PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2013adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2014adfc5217SJeff Kirsher PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2015adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E3B0, 2016adfc5217SJeff Kirsher PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2017adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2018adfc5217SJeff Kirsher PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2019adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2020adfc5217SJeff Kirsher PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2021adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2022adfc5217SJeff Kirsher PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2023adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2024adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2025adfc5217SJeff Kirsher /* 10 */ { BNX2X_CHIP_MASK_ALL, 2026adfc5217SJeff Kirsher PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2027adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2028adfc5217SJeff Kirsher PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2029adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2030adfc5217SJeff Kirsher QM_REG_CONNNUM_0, 4, 0x000fffff }, 2031adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2032adfc5217SJeff Kirsher TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2033adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2034adfc5217SJeff Kirsher SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2035adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2036adfc5217SJeff Kirsher SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2037adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2038adfc5217SJeff Kirsher XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2039adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2040adfc5217SJeff Kirsher XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2041adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2042adfc5217SJeff Kirsher XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2043adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2044adfc5217SJeff Kirsher NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2045adfc5217SJeff Kirsher /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2046adfc5217SJeff Kirsher NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2047adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2048adfc5217SJeff Kirsher NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2049adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2050adfc5217SJeff Kirsher NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2051adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2052adfc5217SJeff Kirsher NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2053adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2054adfc5217SJeff Kirsher NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2055adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2056adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2057adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2058adfc5217SJeff Kirsher NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2059adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2060adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2061adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2062adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2063adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2064adfc5217SJeff Kirsher NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2065adfc5217SJeff Kirsher /* 30 */ { BNX2X_CHIP_MASK_ALL, 2066adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2067adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2068adfc5217SJeff Kirsher NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2069adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2070adfc5217SJeff Kirsher NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2071adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2072adfc5217SJeff Kirsher NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2073adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2074adfc5217SJeff Kirsher NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2075adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 2076adfc5217SJeff Kirsher NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2077adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2078adfc5217SJeff Kirsher NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2079adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2080adfc5217SJeff Kirsher NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2081adfc5217SJeff Kirsher 2082adfc5217SJeff Kirsher { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2083adfc5217SJeff Kirsher }; 2084adfc5217SJeff Kirsher 208551c1a580SMerav Sicron if (!netif_running(bp->dev)) { 208651c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 208751c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2088adfc5217SJeff Kirsher return rc; 208951c1a580SMerav Sicron } 2090adfc5217SJeff Kirsher 2091adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2092adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1; 2093adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2094adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E1H; 2095adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2096adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E2; 2097adfc5217SJeff Kirsher else if (CHIP_IS_E3B0(bp)) 2098adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3B0; 2099adfc5217SJeff Kirsher else /* e3 A0 */ 2100adfc5217SJeff Kirsher hw = BNX2X_CHIP_MASK_E3; 2101adfc5217SJeff Kirsher 2102adfc5217SJeff Kirsher /* Repeat the test twice: 210307ba6af4SMiriam Shitrit * First by writing 0x00000000, second by writing 0xffffffff 210407ba6af4SMiriam Shitrit */ 2105adfc5217SJeff Kirsher for (idx = 0; idx < 2; idx++) { 2106adfc5217SJeff Kirsher 2107adfc5217SJeff Kirsher switch (idx) { 2108adfc5217SJeff Kirsher case 0: 2109adfc5217SJeff Kirsher wr_val = 0; 2110adfc5217SJeff Kirsher break; 2111adfc5217SJeff Kirsher case 1: 2112adfc5217SJeff Kirsher wr_val = 0xffffffff; 2113adfc5217SJeff Kirsher break; 2114adfc5217SJeff Kirsher } 2115adfc5217SJeff Kirsher 2116adfc5217SJeff Kirsher for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2117adfc5217SJeff Kirsher u32 offset, mask, save_val, val; 2118adfc5217SJeff Kirsher if (!(hw & reg_tbl[i].hw)) 2119adfc5217SJeff Kirsher continue; 2120adfc5217SJeff Kirsher 2121adfc5217SJeff Kirsher offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2122adfc5217SJeff Kirsher mask = reg_tbl[i].mask; 2123adfc5217SJeff Kirsher 2124adfc5217SJeff Kirsher save_val = REG_RD(bp, offset); 2125adfc5217SJeff Kirsher 2126adfc5217SJeff Kirsher REG_WR(bp, offset, wr_val & mask); 2127adfc5217SJeff Kirsher 2128adfc5217SJeff Kirsher val = REG_RD(bp, offset); 2129adfc5217SJeff Kirsher 2130adfc5217SJeff Kirsher /* Restore the original register's value */ 2131adfc5217SJeff Kirsher REG_WR(bp, offset, save_val); 2132adfc5217SJeff Kirsher 2133adfc5217SJeff Kirsher /* verify value is as expected */ 2134adfc5217SJeff Kirsher if ((val & mask) != (wr_val & mask)) { 213551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2136adfc5217SJeff Kirsher "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2137adfc5217SJeff Kirsher offset, val, wr_val, mask); 2138adfc5217SJeff Kirsher goto test_reg_exit; 2139adfc5217SJeff Kirsher } 2140adfc5217SJeff Kirsher } 2141adfc5217SJeff Kirsher } 2142adfc5217SJeff Kirsher 2143adfc5217SJeff Kirsher rc = 0; 2144adfc5217SJeff Kirsher 2145adfc5217SJeff Kirsher test_reg_exit: 2146adfc5217SJeff Kirsher return rc; 2147adfc5217SJeff Kirsher } 2148adfc5217SJeff Kirsher 2149adfc5217SJeff Kirsher static int bnx2x_test_memory(struct bnx2x *bp) 2150adfc5217SJeff Kirsher { 2151adfc5217SJeff Kirsher int i, j, rc = -ENODEV; 2152adfc5217SJeff Kirsher u32 val, index; 2153adfc5217SJeff Kirsher static const struct { 2154adfc5217SJeff Kirsher u32 offset; 2155adfc5217SJeff Kirsher int size; 2156adfc5217SJeff Kirsher } mem_tbl[] = { 2157adfc5217SJeff Kirsher { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2158adfc5217SJeff Kirsher { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2159adfc5217SJeff Kirsher { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2160adfc5217SJeff Kirsher { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2161adfc5217SJeff Kirsher { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2162adfc5217SJeff Kirsher { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2163adfc5217SJeff Kirsher { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2164adfc5217SJeff Kirsher 2165adfc5217SJeff Kirsher { 0xffffffff, 0 } 2166adfc5217SJeff Kirsher }; 2167adfc5217SJeff Kirsher 2168adfc5217SJeff Kirsher static const struct { 2169adfc5217SJeff Kirsher char *name; 2170adfc5217SJeff Kirsher u32 offset; 2171adfc5217SJeff Kirsher u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2172adfc5217SJeff Kirsher } prty_tbl[] = { 2173adfc5217SJeff Kirsher { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2174adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2175adfc5217SJeff Kirsher { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2176adfc5217SJeff Kirsher {0x2, 0x2, 0, 0} }, 2177adfc5217SJeff Kirsher { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2178adfc5217SJeff Kirsher {0, 0, 0, 0} }, 2179adfc5217SJeff Kirsher { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2180adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2181adfc5217SJeff Kirsher { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2182adfc5217SJeff Kirsher {0x3ffc0, 0, 0, 0} }, 2183adfc5217SJeff Kirsher { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2184adfc5217SJeff Kirsher {0x3ffc1, 0, 0, 0} }, 2185adfc5217SJeff Kirsher 2186adfc5217SJeff Kirsher { NULL, 0xffffffff, {0, 0, 0, 0} } 2187adfc5217SJeff Kirsher }; 2188adfc5217SJeff Kirsher 218951c1a580SMerav Sicron if (!netif_running(bp->dev)) { 219051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 219151c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2192adfc5217SJeff Kirsher return rc; 219351c1a580SMerav Sicron } 2194adfc5217SJeff Kirsher 2195adfc5217SJeff Kirsher if (CHIP_IS_E1(bp)) 2196adfc5217SJeff Kirsher index = BNX2X_CHIP_E1_OFST; 2197adfc5217SJeff Kirsher else if (CHIP_IS_E1H(bp)) 2198adfc5217SJeff Kirsher index = BNX2X_CHIP_E1H_OFST; 2199adfc5217SJeff Kirsher else if (CHIP_IS_E2(bp)) 2200adfc5217SJeff Kirsher index = BNX2X_CHIP_E2_OFST; 2201adfc5217SJeff Kirsher else /* e3 */ 2202adfc5217SJeff Kirsher index = BNX2X_CHIP_E3_OFST; 2203adfc5217SJeff Kirsher 2204adfc5217SJeff Kirsher /* pre-Check the parity status */ 2205adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2206adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2207adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 220851c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2209adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2210adfc5217SJeff Kirsher goto test_mem_exit; 2211adfc5217SJeff Kirsher } 2212adfc5217SJeff Kirsher } 2213adfc5217SJeff Kirsher 2214adfc5217SJeff Kirsher /* Go through all the memories */ 2215adfc5217SJeff Kirsher for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2216adfc5217SJeff Kirsher for (j = 0; j < mem_tbl[i].size; j++) 2217adfc5217SJeff Kirsher REG_RD(bp, mem_tbl[i].offset + j*4); 2218adfc5217SJeff Kirsher 2219adfc5217SJeff Kirsher /* Check the parity status */ 2220adfc5217SJeff Kirsher for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2221adfc5217SJeff Kirsher val = REG_RD(bp, prty_tbl[i].offset); 2222adfc5217SJeff Kirsher if (val & ~(prty_tbl[i].hw_mask[index])) { 222351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2224adfc5217SJeff Kirsher "%s is 0x%x\n", prty_tbl[i].name, val); 2225adfc5217SJeff Kirsher goto test_mem_exit; 2226adfc5217SJeff Kirsher } 2227adfc5217SJeff Kirsher } 2228adfc5217SJeff Kirsher 2229adfc5217SJeff Kirsher rc = 0; 2230adfc5217SJeff Kirsher 2231adfc5217SJeff Kirsher test_mem_exit: 2232adfc5217SJeff Kirsher return rc; 2233adfc5217SJeff Kirsher } 2234adfc5217SJeff Kirsher 2235adfc5217SJeff Kirsher static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2236adfc5217SJeff Kirsher { 2237adfc5217SJeff Kirsher int cnt = 1400; 2238adfc5217SJeff Kirsher 2239adfc5217SJeff Kirsher if (link_up) { 2240adfc5217SJeff Kirsher while (bnx2x_link_test(bp, is_serdes) && cnt--) 2241adfc5217SJeff Kirsher msleep(20); 2242adfc5217SJeff Kirsher 2243adfc5217SJeff Kirsher if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 224451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 22458970b2e4SMerav Sicron 22468970b2e4SMerav Sicron cnt = 1400; 22478970b2e4SMerav Sicron while (!bp->link_vars.link_up && cnt--) 22488970b2e4SMerav Sicron msleep(20); 22498970b2e4SMerav Sicron 22508970b2e4SMerav Sicron if (cnt <= 0 && !bp->link_vars.link_up) 22518970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 22528970b2e4SMerav Sicron "Timeout waiting for link init\n"); 2253adfc5217SJeff Kirsher } 2254adfc5217SJeff Kirsher } 2255adfc5217SJeff Kirsher 2256adfc5217SJeff Kirsher static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2257adfc5217SJeff Kirsher { 2258adfc5217SJeff Kirsher unsigned int pkt_size, num_pkts, i; 2259adfc5217SJeff Kirsher struct sk_buff *skb; 2260adfc5217SJeff Kirsher unsigned char *packet; 2261adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2262adfc5217SJeff Kirsher struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 226365565884SMerav Sicron struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2264adfc5217SJeff Kirsher u16 tx_start_idx, tx_idx; 2265adfc5217SJeff Kirsher u16 rx_start_idx, rx_idx; 2266b0700b1eSDmitry Kravkov u16 pkt_prod, bd_prod; 2267adfc5217SJeff Kirsher struct sw_tx_bd *tx_buf; 2268adfc5217SJeff Kirsher struct eth_tx_start_bd *tx_start_bd; 2269adfc5217SJeff Kirsher dma_addr_t mapping; 2270adfc5217SJeff Kirsher union eth_rx_cqe *cqe; 2271adfc5217SJeff Kirsher u8 cqe_fp_flags, cqe_fp_type; 2272adfc5217SJeff Kirsher struct sw_rx_bd *rx_buf; 2273adfc5217SJeff Kirsher u16 len; 2274adfc5217SJeff Kirsher int rc = -ENODEV; 2275e52fcb24SEric Dumazet u8 *data; 22768970b2e4SMerav Sicron struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 22778970b2e4SMerav Sicron txdata->txq_index); 2278adfc5217SJeff Kirsher 2279adfc5217SJeff Kirsher /* check the loopback mode */ 2280adfc5217SJeff Kirsher switch (loopback_mode) { 2281adfc5217SJeff Kirsher case BNX2X_PHY_LOOPBACK: 22828970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 22838970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2284adfc5217SJeff Kirsher return -EINVAL; 22858970b2e4SMerav Sicron } 2286adfc5217SJeff Kirsher break; 2287adfc5217SJeff Kirsher case BNX2X_MAC_LOOPBACK: 228832911333SYaniv Rosner if (CHIP_IS_E3(bp)) { 228932911333SYaniv Rosner int cfg_idx = bnx2x_get_link_cfg_idx(bp); 229032911333SYaniv Rosner if (bp->port.supported[cfg_idx] & 229132911333SYaniv Rosner (SUPPORTED_10000baseT_Full | 229232911333SYaniv Rosner SUPPORTED_20000baseMLD2_Full | 229332911333SYaniv Rosner SUPPORTED_20000baseKR2_Full)) 229432911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_XMAC; 229532911333SYaniv Rosner else 229632911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_UMAC; 229732911333SYaniv Rosner } else 229832911333SYaniv Rosner bp->link_params.loopback_mode = LOOPBACK_BMAC; 229932911333SYaniv Rosner 2300adfc5217SJeff Kirsher bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2301adfc5217SJeff Kirsher break; 23028970b2e4SMerav Sicron case BNX2X_EXT_LOOPBACK: 23038970b2e4SMerav Sicron if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 23048970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 23058970b2e4SMerav Sicron "Can't configure external loopback\n"); 23068970b2e4SMerav Sicron return -EINVAL; 23078970b2e4SMerav Sicron } 23088970b2e4SMerav Sicron break; 2309adfc5217SJeff Kirsher default: 231051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2311adfc5217SJeff Kirsher return -EINVAL; 2312adfc5217SJeff Kirsher } 2313adfc5217SJeff Kirsher 2314adfc5217SJeff Kirsher /* prepare the loopback packet */ 2315adfc5217SJeff Kirsher pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2316adfc5217SJeff Kirsher bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2317adfc5217SJeff Kirsher skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2318adfc5217SJeff Kirsher if (!skb) { 231951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2320adfc5217SJeff Kirsher rc = -ENOMEM; 2321adfc5217SJeff Kirsher goto test_loopback_exit; 2322adfc5217SJeff Kirsher } 2323adfc5217SJeff Kirsher packet = skb_put(skb, pkt_size); 2324adfc5217SJeff Kirsher memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2325adfc5217SJeff Kirsher memset(packet + ETH_ALEN, 0, ETH_ALEN); 2326adfc5217SJeff Kirsher memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2327adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2328adfc5217SJeff Kirsher packet[i] = (unsigned char) (i & 0xff); 2329adfc5217SJeff Kirsher mapping = dma_map_single(&bp->pdev->dev, skb->data, 2330adfc5217SJeff Kirsher skb_headlen(skb), DMA_TO_DEVICE); 2331adfc5217SJeff Kirsher if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2332adfc5217SJeff Kirsher rc = -ENOMEM; 2333adfc5217SJeff Kirsher dev_kfree_skb(skb); 233451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2335adfc5217SJeff Kirsher goto test_loopback_exit; 2336adfc5217SJeff Kirsher } 2337adfc5217SJeff Kirsher 2338adfc5217SJeff Kirsher /* send the loopback packet */ 2339adfc5217SJeff Kirsher num_pkts = 0; 2340adfc5217SJeff Kirsher tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2341adfc5217SJeff Kirsher rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2342adfc5217SJeff Kirsher 234373dbb5e1SDmitry Kravkov netdev_tx_sent_queue(txq, skb->len); 234473dbb5e1SDmitry Kravkov 2345adfc5217SJeff Kirsher pkt_prod = txdata->tx_pkt_prod++; 2346adfc5217SJeff Kirsher tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2347adfc5217SJeff Kirsher tx_buf->first_bd = txdata->tx_bd_prod; 2348adfc5217SJeff Kirsher tx_buf->skb = skb; 2349adfc5217SJeff Kirsher tx_buf->flags = 0; 2350adfc5217SJeff Kirsher 2351adfc5217SJeff Kirsher bd_prod = TX_BD(txdata->tx_bd_prod); 2352adfc5217SJeff Kirsher tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2353adfc5217SJeff Kirsher tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2354adfc5217SJeff Kirsher tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2355adfc5217SJeff Kirsher tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2356adfc5217SJeff Kirsher tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2357adfc5217SJeff Kirsher tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2358adfc5217SJeff Kirsher tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2359adfc5217SJeff Kirsher SET_FLAG(tx_start_bd->general_data, 2360adfc5217SJeff Kirsher ETH_TX_START_BD_HDR_NBDS, 2361adfc5217SJeff Kirsher 1); 236296bed4b9SYuval Mintz SET_FLAG(tx_start_bd->general_data, 236396bed4b9SYuval Mintz ETH_TX_START_BD_PARSE_NBDS, 236496bed4b9SYuval Mintz 0); 2365adfc5217SJeff Kirsher 2366adfc5217SJeff Kirsher /* turn on parsing and get a BD */ 2367adfc5217SJeff Kirsher bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2368adfc5217SJeff Kirsher 236996bed4b9SYuval Mintz if (CHIP_IS_E1x(bp)) { 237096bed4b9SYuval Mintz u16 global_data = 0; 237196bed4b9SYuval Mintz struct eth_tx_parse_bd_e1x *pbd_e1x = 237296bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2373adfc5217SJeff Kirsher memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 237496bed4b9SYuval Mintz SET_FLAG(global_data, 237596bed4b9SYuval Mintz ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 237696bed4b9SYuval Mintz pbd_e1x->global_data = cpu_to_le16(global_data); 237796bed4b9SYuval Mintz } else { 237896bed4b9SYuval Mintz u32 parsing_data = 0; 237996bed4b9SYuval Mintz struct eth_tx_parse_bd_e2 *pbd_e2 = 238096bed4b9SYuval Mintz &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 238196bed4b9SYuval Mintz memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 238296bed4b9SYuval Mintz SET_FLAG(parsing_data, 238396bed4b9SYuval Mintz ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 238496bed4b9SYuval Mintz pbd_e2->parsing_data = cpu_to_le32(parsing_data); 238596bed4b9SYuval Mintz } 2386adfc5217SJeff Kirsher wmb(); 2387adfc5217SJeff Kirsher 2388adfc5217SJeff Kirsher txdata->tx_db.data.prod += 2; 2389adfc5217SJeff Kirsher barrier(); 2390adfc5217SJeff Kirsher DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2391adfc5217SJeff Kirsher 2392adfc5217SJeff Kirsher mmiowb(); 2393adfc5217SJeff Kirsher barrier(); 2394adfc5217SJeff Kirsher 2395adfc5217SJeff Kirsher num_pkts++; 2396adfc5217SJeff Kirsher txdata->tx_bd_prod += 2; /* start + pbd */ 2397adfc5217SJeff Kirsher 2398adfc5217SJeff Kirsher udelay(100); 2399adfc5217SJeff Kirsher 2400adfc5217SJeff Kirsher tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2401adfc5217SJeff Kirsher if (tx_idx != tx_start_idx + num_pkts) 2402adfc5217SJeff Kirsher goto test_loopback_exit; 2403adfc5217SJeff Kirsher 2404adfc5217SJeff Kirsher /* Unlike HC IGU won't generate an interrupt for status block 2405adfc5217SJeff Kirsher * updates that have been performed while interrupts were 2406adfc5217SJeff Kirsher * disabled. 2407adfc5217SJeff Kirsher */ 2408adfc5217SJeff Kirsher if (bp->common.int_block == INT_BLOCK_IGU) { 2409adfc5217SJeff Kirsher /* Disable local BHes to prevent a dead-lock situation between 2410adfc5217SJeff Kirsher * sch_direct_xmit() and bnx2x_run_loopback() (calling 2411adfc5217SJeff Kirsher * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2412adfc5217SJeff Kirsher */ 2413adfc5217SJeff Kirsher local_bh_disable(); 2414adfc5217SJeff Kirsher bnx2x_tx_int(bp, txdata); 2415adfc5217SJeff Kirsher local_bh_enable(); 2416adfc5217SJeff Kirsher } 2417adfc5217SJeff Kirsher 2418adfc5217SJeff Kirsher rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2419adfc5217SJeff Kirsher if (rx_idx != rx_start_idx + num_pkts) 2420adfc5217SJeff Kirsher goto test_loopback_exit; 2421adfc5217SJeff Kirsher 2422b0700b1eSDmitry Kravkov cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2423adfc5217SJeff Kirsher cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2424adfc5217SJeff Kirsher cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2425adfc5217SJeff Kirsher if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2426adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2427adfc5217SJeff Kirsher 2428621b4d66SDmitry Kravkov len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2429adfc5217SJeff Kirsher if (len != pkt_size) 2430adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2431adfc5217SJeff Kirsher 2432adfc5217SJeff Kirsher rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2433adfc5217SJeff Kirsher dma_sync_single_for_cpu(&bp->pdev->dev, 2434adfc5217SJeff Kirsher dma_unmap_addr(rx_buf, mapping), 2435adfc5217SJeff Kirsher fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2436e52fcb24SEric Dumazet data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2437adfc5217SJeff Kirsher for (i = ETH_HLEN; i < pkt_size; i++) 2438e52fcb24SEric Dumazet if (*(data + i) != (unsigned char) (i & 0xff)) 2439adfc5217SJeff Kirsher goto test_loopback_rx_exit; 2440adfc5217SJeff Kirsher 2441adfc5217SJeff Kirsher rc = 0; 2442adfc5217SJeff Kirsher 2443adfc5217SJeff Kirsher test_loopback_rx_exit: 2444adfc5217SJeff Kirsher 2445adfc5217SJeff Kirsher fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2446adfc5217SJeff Kirsher fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2447adfc5217SJeff Kirsher fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2448adfc5217SJeff Kirsher fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2449adfc5217SJeff Kirsher 2450adfc5217SJeff Kirsher /* Update producers */ 2451adfc5217SJeff Kirsher bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2452adfc5217SJeff Kirsher fp_rx->rx_sge_prod); 2453adfc5217SJeff Kirsher 2454adfc5217SJeff Kirsher test_loopback_exit: 2455adfc5217SJeff Kirsher bp->link_params.loopback_mode = LOOPBACK_NONE; 2456adfc5217SJeff Kirsher 2457adfc5217SJeff Kirsher return rc; 2458adfc5217SJeff Kirsher } 2459adfc5217SJeff Kirsher 2460adfc5217SJeff Kirsher static int bnx2x_test_loopback(struct bnx2x *bp) 2461adfc5217SJeff Kirsher { 2462adfc5217SJeff Kirsher int rc = 0, res; 2463adfc5217SJeff Kirsher 2464adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2465adfc5217SJeff Kirsher return rc; 2466adfc5217SJeff Kirsher 2467adfc5217SJeff Kirsher if (!netif_running(bp->dev)) 2468adfc5217SJeff Kirsher return BNX2X_LOOPBACK_FAILED; 2469adfc5217SJeff Kirsher 2470adfc5217SJeff Kirsher bnx2x_netif_stop(bp, 1); 2471adfc5217SJeff Kirsher bnx2x_acquire_phy_lock(bp); 2472adfc5217SJeff Kirsher 2473adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2474adfc5217SJeff Kirsher if (res) { 247551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2476adfc5217SJeff Kirsher rc |= BNX2X_PHY_LOOPBACK_FAILED; 2477adfc5217SJeff Kirsher } 2478adfc5217SJeff Kirsher 2479adfc5217SJeff Kirsher res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2480adfc5217SJeff Kirsher if (res) { 248151c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2482adfc5217SJeff Kirsher rc |= BNX2X_MAC_LOOPBACK_FAILED; 2483adfc5217SJeff Kirsher } 2484adfc5217SJeff Kirsher 2485adfc5217SJeff Kirsher bnx2x_release_phy_lock(bp); 2486adfc5217SJeff Kirsher bnx2x_netif_start(bp); 2487adfc5217SJeff Kirsher 2488adfc5217SJeff Kirsher return rc; 2489adfc5217SJeff Kirsher } 2490adfc5217SJeff Kirsher 24918970b2e4SMerav Sicron static int bnx2x_test_ext_loopback(struct bnx2x *bp) 24928970b2e4SMerav Sicron { 24938970b2e4SMerav Sicron int rc; 24948970b2e4SMerav Sicron u8 is_serdes = 24958970b2e4SMerav Sicron (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 24968970b2e4SMerav Sicron 24978970b2e4SMerav Sicron if (BP_NOMCP(bp)) 24988970b2e4SMerav Sicron return -ENODEV; 24998970b2e4SMerav Sicron 25008970b2e4SMerav Sicron if (!netif_running(bp->dev)) 25018970b2e4SMerav Sicron return BNX2X_EXT_LOOPBACK_FAILED; 25028970b2e4SMerav Sicron 25035d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 25048970b2e4SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 25058970b2e4SMerav Sicron if (rc) { 25068970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 25078970b2e4SMerav Sicron "Can't perform self-test, nic_load (for external lb) failed\n"); 25088970b2e4SMerav Sicron return -ENODEV; 25098970b2e4SMerav Sicron } 25108970b2e4SMerav Sicron bnx2x_wait_for_link(bp, 1, is_serdes); 25118970b2e4SMerav Sicron 25128970b2e4SMerav Sicron bnx2x_netif_stop(bp, 1); 25138970b2e4SMerav Sicron 25148970b2e4SMerav Sicron rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 25158970b2e4SMerav Sicron if (rc) 25168970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 25178970b2e4SMerav Sicron 25188970b2e4SMerav Sicron bnx2x_netif_start(bp); 25198970b2e4SMerav Sicron 25208970b2e4SMerav Sicron return rc; 25218970b2e4SMerav Sicron } 25228970b2e4SMerav Sicron 2523adfc5217SJeff Kirsher #define CRC32_RESIDUAL 0xdebb20e3 2524adfc5217SJeff Kirsher 2525adfc5217SJeff Kirsher static int bnx2x_test_nvram(struct bnx2x *bp) 2526adfc5217SJeff Kirsher { 2527adfc5217SJeff Kirsher static const struct { 2528adfc5217SJeff Kirsher int offset; 2529adfc5217SJeff Kirsher int size; 2530adfc5217SJeff Kirsher } nvram_tbl[] = { 2531adfc5217SJeff Kirsher { 0, 0x14 }, /* bootstrap */ 2532adfc5217SJeff Kirsher { 0x14, 0xec }, /* dir */ 2533adfc5217SJeff Kirsher { 0x100, 0x350 }, /* manuf_info */ 2534adfc5217SJeff Kirsher { 0x450, 0xf0 }, /* feature_info */ 2535adfc5217SJeff Kirsher { 0x640, 0x64 }, /* upgrade_key_info */ 2536adfc5217SJeff Kirsher { 0x708, 0x70 }, /* manuf_key_info */ 2537adfc5217SJeff Kirsher { 0, 0 } 2538adfc5217SJeff Kirsher }; 2539afa13b4bSMintz Yuval __be32 *buf; 2540afa13b4bSMintz Yuval u8 *data; 2541adfc5217SJeff Kirsher int i, rc; 2542adfc5217SJeff Kirsher u32 magic, crc; 2543adfc5217SJeff Kirsher 2544adfc5217SJeff Kirsher if (BP_NOMCP(bp)) 2545adfc5217SJeff Kirsher return 0; 2546adfc5217SJeff Kirsher 2547afa13b4bSMintz Yuval buf = kmalloc(0x350, GFP_KERNEL); 2548afa13b4bSMintz Yuval if (!buf) { 254951c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2550afa13b4bSMintz Yuval rc = -ENOMEM; 2551afa13b4bSMintz Yuval goto test_nvram_exit; 2552afa13b4bSMintz Yuval } 2553afa13b4bSMintz Yuval data = (u8 *)buf; 2554afa13b4bSMintz Yuval 2555adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, 0, data, 4); 2556adfc5217SJeff Kirsher if (rc) { 255751c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 255851c1a580SMerav Sicron "magic value read (rc %d)\n", rc); 2559adfc5217SJeff Kirsher goto test_nvram_exit; 2560adfc5217SJeff Kirsher } 2561adfc5217SJeff Kirsher 2562adfc5217SJeff Kirsher magic = be32_to_cpu(buf[0]); 2563adfc5217SJeff Kirsher if (magic != 0x669955aa) { 256451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 256551c1a580SMerav Sicron "wrong magic value (0x%08x)\n", magic); 2566adfc5217SJeff Kirsher rc = -ENODEV; 2567adfc5217SJeff Kirsher goto test_nvram_exit; 2568adfc5217SJeff Kirsher } 2569adfc5217SJeff Kirsher 2570adfc5217SJeff Kirsher for (i = 0; nvram_tbl[i].size; i++) { 2571adfc5217SJeff Kirsher 2572adfc5217SJeff Kirsher rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 2573adfc5217SJeff Kirsher nvram_tbl[i].size); 2574adfc5217SJeff Kirsher if (rc) { 257551c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2576adfc5217SJeff Kirsher "nvram_tbl[%d] read data (rc %d)\n", i, rc); 2577adfc5217SJeff Kirsher goto test_nvram_exit; 2578adfc5217SJeff Kirsher } 2579adfc5217SJeff Kirsher 2580adfc5217SJeff Kirsher crc = ether_crc_le(nvram_tbl[i].size, data); 2581adfc5217SJeff Kirsher if (crc != CRC32_RESIDUAL) { 258251c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 258351c1a580SMerav Sicron "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc); 2584adfc5217SJeff Kirsher rc = -ENODEV; 2585adfc5217SJeff Kirsher goto test_nvram_exit; 2586adfc5217SJeff Kirsher } 2587adfc5217SJeff Kirsher } 2588adfc5217SJeff Kirsher 2589adfc5217SJeff Kirsher test_nvram_exit: 2590afa13b4bSMintz Yuval kfree(buf); 2591adfc5217SJeff Kirsher return rc; 2592adfc5217SJeff Kirsher } 2593adfc5217SJeff Kirsher 2594adfc5217SJeff Kirsher /* Send an EMPTY ramrod on the first queue */ 2595adfc5217SJeff Kirsher static int bnx2x_test_intr(struct bnx2x *bp) 2596adfc5217SJeff Kirsher { 25973b603066SYuval Mintz struct bnx2x_queue_state_params params = {NULL}; 2598adfc5217SJeff Kirsher 259951c1a580SMerav Sicron if (!netif_running(bp->dev)) { 260051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 260151c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2602adfc5217SJeff Kirsher return -ENODEV; 260351c1a580SMerav Sicron } 2604adfc5217SJeff Kirsher 260515192a8cSBarak Witkowski params.q_obj = &bp->sp_objs->q_obj; 2606adfc5217SJeff Kirsher params.cmd = BNX2X_Q_CMD_EMPTY; 2607adfc5217SJeff Kirsher 2608adfc5217SJeff Kirsher __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2609adfc5217SJeff Kirsher 2610adfc5217SJeff Kirsher return bnx2x_queue_state_change(bp, ¶ms); 2611adfc5217SJeff Kirsher } 2612adfc5217SJeff Kirsher 2613adfc5217SJeff Kirsher static void bnx2x_self_test(struct net_device *dev, 2614adfc5217SJeff Kirsher struct ethtool_test *etest, u64 *buf) 2615adfc5217SJeff Kirsher { 2616adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2617a336ca7cSYaniv Rosner u8 is_serdes, link_up; 2618a336ca7cSYaniv Rosner int rc, cnt = 0; 2619cf2c1df6SMerav Sicron 2620adfc5217SJeff Kirsher if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 262151c1a580SMerav Sicron netdev_err(bp->dev, 262251c1a580SMerav Sicron "Handling parity error recovery. Try again later\n"); 2623adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2624adfc5217SJeff Kirsher return; 2625adfc5217SJeff Kirsher } 26262de67439SYuval Mintz 26278970b2e4SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 26288970b2e4SMerav Sicron "Self-test command parameters: offline = %d, external_lb = %d\n", 26298970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_OFFLINE), 26308970b2e4SMerav Sicron (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2631adfc5217SJeff Kirsher 2632cf2c1df6SMerav Sicron memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2633adfc5217SJeff Kirsher 2634cf2c1df6SMerav Sicron if (!netif_running(dev)) { 2635cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2636cf2c1df6SMerav Sicron "Can't perform self-test when interface is down\n"); 2637adfc5217SJeff Kirsher return; 2638cf2c1df6SMerav Sicron } 2639adfc5217SJeff Kirsher 2640adfc5217SJeff Kirsher is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2641a336ca7cSYaniv Rosner link_up = bp->link_vars.link_up; 2642cf2c1df6SMerav Sicron /* offline tests are not supported in MF mode */ 2643cf2c1df6SMerav Sicron if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2644adfc5217SJeff Kirsher int port = BP_PORT(bp); 2645adfc5217SJeff Kirsher u32 val; 2646adfc5217SJeff Kirsher 2647adfc5217SJeff Kirsher /* save current value of input enable for TX port IF */ 2648adfc5217SJeff Kirsher val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2649adfc5217SJeff Kirsher /* disable input for TX port IF */ 2650adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 2651adfc5217SJeff Kirsher 26525d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2653cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_DIAG); 2654cf2c1df6SMerav Sicron if (rc) { 2655cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2656cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2657cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for offline) failed\n"); 2658cf2c1df6SMerav Sicron return; 2659cf2c1df6SMerav Sicron } 2660cf2c1df6SMerav Sicron 2661adfc5217SJeff Kirsher /* wait until link state is restored */ 2662adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, 1, is_serdes); 2663adfc5217SJeff Kirsher 2664adfc5217SJeff Kirsher if (bnx2x_test_registers(bp) != 0) { 2665adfc5217SJeff Kirsher buf[0] = 1; 2666adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2667adfc5217SJeff Kirsher } 2668adfc5217SJeff Kirsher if (bnx2x_test_memory(bp) != 0) { 2669adfc5217SJeff Kirsher buf[1] = 1; 2670adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2671adfc5217SJeff Kirsher } 2672adfc5217SJeff Kirsher 26738970b2e4SMerav Sicron buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 2674adfc5217SJeff Kirsher if (buf[2] != 0) 2675adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2676adfc5217SJeff Kirsher 26778970b2e4SMerav Sicron if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 26788970b2e4SMerav Sicron buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 26798970b2e4SMerav Sicron if (buf[3] != 0) 26808970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 26818970b2e4SMerav Sicron etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 26828970b2e4SMerav Sicron } 26838970b2e4SMerav Sicron 26845d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2685adfc5217SJeff Kirsher 2686adfc5217SJeff Kirsher /* restore input for TX port IF */ 2687adfc5217SJeff Kirsher REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 2688cf2c1df6SMerav Sicron rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2689cf2c1df6SMerav Sicron if (rc) { 2690cf2c1df6SMerav Sicron etest->flags |= ETH_TEST_FL_FAILED; 2691cf2c1df6SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 2692cf2c1df6SMerav Sicron "Can't perform self-test, nic_load (for online) failed\n"); 2693cf2c1df6SMerav Sicron return; 2694cf2c1df6SMerav Sicron } 2695adfc5217SJeff Kirsher /* wait until link state is restored */ 2696adfc5217SJeff Kirsher bnx2x_wait_for_link(bp, link_up, is_serdes); 2697adfc5217SJeff Kirsher } 2698adfc5217SJeff Kirsher if (bnx2x_test_nvram(bp) != 0) { 2699cf2c1df6SMerav Sicron if (!IS_MF(bp)) 27008970b2e4SMerav Sicron buf[4] = 1; 2701cf2c1df6SMerav Sicron else 2702cf2c1df6SMerav Sicron buf[0] = 1; 2703adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2704adfc5217SJeff Kirsher } 2705adfc5217SJeff Kirsher if (bnx2x_test_intr(bp) != 0) { 2706cf2c1df6SMerav Sicron if (!IS_MF(bp)) 27078970b2e4SMerav Sicron buf[5] = 1; 2708cf2c1df6SMerav Sicron else 2709cf2c1df6SMerav Sicron buf[1] = 1; 2710adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2711adfc5217SJeff Kirsher } 2712adfc5217SJeff Kirsher 2713a336ca7cSYaniv Rosner if (link_up) { 2714a336ca7cSYaniv Rosner cnt = 100; 2715a336ca7cSYaniv Rosner while (bnx2x_link_test(bp, is_serdes) && --cnt) 2716a336ca7cSYaniv Rosner msleep(20); 2717a336ca7cSYaniv Rosner } 2718a336ca7cSYaniv Rosner 2719a336ca7cSYaniv Rosner if (!cnt) { 2720cf2c1df6SMerav Sicron if (!IS_MF(bp)) 27218970b2e4SMerav Sicron buf[6] = 1; 2722cf2c1df6SMerav Sicron else 2723cf2c1df6SMerav Sicron buf[2] = 1; 2724adfc5217SJeff Kirsher etest->flags |= ETH_TEST_FL_FAILED; 2725adfc5217SJeff Kirsher } 2726adfc5217SJeff Kirsher } 2727adfc5217SJeff Kirsher 2728adfc5217SJeff Kirsher #define IS_PORT_STAT(i) \ 2729adfc5217SJeff Kirsher ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 2730adfc5217SJeff Kirsher #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 2731adfc5217SJeff Kirsher #define IS_MF_MODE_STAT(bp) \ 2732adfc5217SJeff Kirsher (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) 2733adfc5217SJeff Kirsher 2734adfc5217SJeff Kirsher /* ethtool statistics are displayed for all regular ethernet queues and the 2735adfc5217SJeff Kirsher * fcoe L2 queue if not disabled 2736adfc5217SJeff Kirsher */ 27371191cb83SEric Dumazet static int bnx2x_num_stat_queues(struct bnx2x *bp) 2738adfc5217SJeff Kirsher { 2739adfc5217SJeff Kirsher return BNX2X_NUM_ETH_QUEUES(bp); 2740adfc5217SJeff Kirsher } 2741adfc5217SJeff Kirsher 2742adfc5217SJeff Kirsher static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 2743adfc5217SJeff Kirsher { 2744adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2745adfc5217SJeff Kirsher int i, num_stats; 2746adfc5217SJeff Kirsher 2747adfc5217SJeff Kirsher switch (stringset) { 2748adfc5217SJeff Kirsher case ETH_SS_STATS: 2749adfc5217SJeff Kirsher if (is_multi(bp)) { 2750adfc5217SJeff Kirsher num_stats = bnx2x_num_stat_queues(bp) * 2751adfc5217SJeff Kirsher BNX2X_NUM_Q_STATS; 2752d5e83632SYuval Mintz } else 2753adfc5217SJeff Kirsher num_stats = 0; 2754d5e83632SYuval Mintz if (IS_MF_MODE_STAT(bp)) { 2755adfc5217SJeff Kirsher for (i = 0; i < BNX2X_NUM_STATS; i++) 2756adfc5217SJeff Kirsher if (IS_FUNC_STAT(i)) 2757adfc5217SJeff Kirsher num_stats++; 2758adfc5217SJeff Kirsher } else 2759d5e83632SYuval Mintz num_stats += BNX2X_NUM_STATS; 2760d5e83632SYuval Mintz 2761adfc5217SJeff Kirsher return num_stats; 2762adfc5217SJeff Kirsher 2763adfc5217SJeff Kirsher case ETH_SS_TEST: 2764cf2c1df6SMerav Sicron return BNX2X_NUM_TESTS(bp); 2765adfc5217SJeff Kirsher 2766adfc5217SJeff Kirsher default: 2767adfc5217SJeff Kirsher return -EINVAL; 2768adfc5217SJeff Kirsher } 2769adfc5217SJeff Kirsher } 2770adfc5217SJeff Kirsher 2771adfc5217SJeff Kirsher static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 2772adfc5217SJeff Kirsher { 2773adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 27745889335cSMerav Sicron int i, j, k, start; 2775adfc5217SJeff Kirsher char queue_name[MAX_QUEUE_NAME_LEN+1]; 2776adfc5217SJeff Kirsher 2777adfc5217SJeff Kirsher switch (stringset) { 2778adfc5217SJeff Kirsher case ETH_SS_STATS: 2779adfc5217SJeff Kirsher k = 0; 2780d5e83632SYuval Mintz if (is_multi(bp)) { 2781adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 2782adfc5217SJeff Kirsher memset(queue_name, 0, sizeof(queue_name)); 2783adfc5217SJeff Kirsher sprintf(queue_name, "%d", i); 2784adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 2785adfc5217SJeff Kirsher snprintf(buf + (k + j)*ETH_GSTRING_LEN, 2786adfc5217SJeff Kirsher ETH_GSTRING_LEN, 2787adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].string, 2788adfc5217SJeff Kirsher queue_name); 2789adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2790adfc5217SJeff Kirsher } 2791d5e83632SYuval Mintz } 2792d5e83632SYuval Mintz 2793d5e83632SYuval Mintz 2794adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2795adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2796adfc5217SJeff Kirsher continue; 2797d5e83632SYuval Mintz strcpy(buf + (k + j)*ETH_GSTRING_LEN, 2798adfc5217SJeff Kirsher bnx2x_stats_arr[i].string); 2799adfc5217SJeff Kirsher j++; 2800adfc5217SJeff Kirsher } 2801d5e83632SYuval Mintz 2802adfc5217SJeff Kirsher break; 2803adfc5217SJeff Kirsher 2804adfc5217SJeff Kirsher case ETH_SS_TEST: 2805cf2c1df6SMerav Sicron /* First 4 tests cannot be done in MF mode */ 2806cf2c1df6SMerav Sicron if (!IS_MF(bp)) 2807cf2c1df6SMerav Sicron start = 0; 2808cf2c1df6SMerav Sicron else 2809cf2c1df6SMerav Sicron start = 4; 28105889335cSMerav Sicron memcpy(buf, bnx2x_tests_str_arr + start, 28115889335cSMerav Sicron ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 2812adfc5217SJeff Kirsher } 2813adfc5217SJeff Kirsher } 2814adfc5217SJeff Kirsher 2815adfc5217SJeff Kirsher static void bnx2x_get_ethtool_stats(struct net_device *dev, 2816adfc5217SJeff Kirsher struct ethtool_stats *stats, u64 *buf) 2817adfc5217SJeff Kirsher { 2818adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2819adfc5217SJeff Kirsher u32 *hw_stats, *offset; 2820d5e83632SYuval Mintz int i, j, k = 0; 2821adfc5217SJeff Kirsher 2822adfc5217SJeff Kirsher if (is_multi(bp)) { 2823adfc5217SJeff Kirsher for_each_eth_queue(bp, i) { 282415192a8cSBarak Witkowski hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 2825adfc5217SJeff Kirsher for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 2826adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 0) { 2827adfc5217SJeff Kirsher /* skip this counter */ 2828adfc5217SJeff Kirsher buf[k + j] = 0; 2829adfc5217SJeff Kirsher continue; 2830adfc5217SJeff Kirsher } 2831adfc5217SJeff Kirsher offset = (hw_stats + 2832adfc5217SJeff Kirsher bnx2x_q_stats_arr[j].offset); 2833adfc5217SJeff Kirsher if (bnx2x_q_stats_arr[j].size == 4) { 2834adfc5217SJeff Kirsher /* 4-byte counter */ 2835adfc5217SJeff Kirsher buf[k + j] = (u64) *offset; 2836adfc5217SJeff Kirsher continue; 2837adfc5217SJeff Kirsher } 2838adfc5217SJeff Kirsher /* 8-byte counter */ 2839adfc5217SJeff Kirsher buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2840adfc5217SJeff Kirsher } 2841adfc5217SJeff Kirsher k += BNX2X_NUM_Q_STATS; 2842adfc5217SJeff Kirsher } 2843adfc5217SJeff Kirsher } 2844d5e83632SYuval Mintz 2845adfc5217SJeff Kirsher hw_stats = (u32 *)&bp->eth_stats; 2846adfc5217SJeff Kirsher for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 2847adfc5217SJeff Kirsher if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) 2848adfc5217SJeff Kirsher continue; 2849adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 0) { 2850adfc5217SJeff Kirsher /* skip this counter */ 2851d5e83632SYuval Mintz buf[k + j] = 0; 2852adfc5217SJeff Kirsher j++; 2853adfc5217SJeff Kirsher continue; 2854adfc5217SJeff Kirsher } 2855adfc5217SJeff Kirsher offset = (hw_stats + bnx2x_stats_arr[i].offset); 2856adfc5217SJeff Kirsher if (bnx2x_stats_arr[i].size == 4) { 2857adfc5217SJeff Kirsher /* 4-byte counter */ 2858d5e83632SYuval Mintz buf[k + j] = (u64) *offset; 2859adfc5217SJeff Kirsher j++; 2860adfc5217SJeff Kirsher continue; 2861adfc5217SJeff Kirsher } 2862adfc5217SJeff Kirsher /* 8-byte counter */ 2863d5e83632SYuval Mintz buf[k + j] = HILO_U64(*offset, *(offset + 1)); 2864adfc5217SJeff Kirsher j++; 2865adfc5217SJeff Kirsher } 2866adfc5217SJeff Kirsher } 2867adfc5217SJeff Kirsher 2868adfc5217SJeff Kirsher static int bnx2x_set_phys_id(struct net_device *dev, 2869adfc5217SJeff Kirsher enum ethtool_phys_id_state state) 2870adfc5217SJeff Kirsher { 2871adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2872adfc5217SJeff Kirsher 287351c1a580SMerav Sicron if (!netif_running(dev)) { 287451c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 287551c1a580SMerav Sicron "cannot access eeprom when the interface is down\n"); 2876adfc5217SJeff Kirsher return -EAGAIN; 287751c1a580SMerav Sicron } 2878adfc5217SJeff Kirsher 287951c1a580SMerav Sicron if (!bp->port.pmf) { 288051c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n"); 2881adfc5217SJeff Kirsher return -EOPNOTSUPP; 288251c1a580SMerav Sicron } 2883adfc5217SJeff Kirsher 2884adfc5217SJeff Kirsher switch (state) { 2885adfc5217SJeff Kirsher case ETHTOOL_ID_ACTIVE: 2886adfc5217SJeff Kirsher return 1; /* cycle on/off once per second */ 2887adfc5217SJeff Kirsher 2888adfc5217SJeff Kirsher case ETHTOOL_ID_ON: 28898203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2890adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2891adfc5217SJeff Kirsher LED_MODE_ON, SPEED_1000); 28928203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2893adfc5217SJeff Kirsher break; 2894adfc5217SJeff Kirsher 2895adfc5217SJeff Kirsher case ETHTOOL_ID_OFF: 28968203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2897adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2898adfc5217SJeff Kirsher LED_MODE_FRONT_PANEL_OFF, 0); 28998203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2900adfc5217SJeff Kirsher break; 2901adfc5217SJeff Kirsher 2902adfc5217SJeff Kirsher case ETHTOOL_ID_INACTIVE: 29038203c4b6SYaniv Rosner bnx2x_acquire_phy_lock(bp); 2904adfc5217SJeff Kirsher bnx2x_set_led(&bp->link_params, &bp->link_vars, 2905adfc5217SJeff Kirsher LED_MODE_OPER, 2906adfc5217SJeff Kirsher bp->link_vars.line_speed); 29078203c4b6SYaniv Rosner bnx2x_release_phy_lock(bp); 2908adfc5217SJeff Kirsher } 2909adfc5217SJeff Kirsher 2910adfc5217SJeff Kirsher return 0; 2911adfc5217SJeff Kirsher } 2912adfc5217SJeff Kirsher 29135d317c6aSMerav Sicron static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 29145d317c6aSMerav Sicron { 29155d317c6aSMerav Sicron 29165d317c6aSMerav Sicron switch (info->flow_type) { 29175d317c6aSMerav Sicron case TCP_V4_FLOW: 29185d317c6aSMerav Sicron case TCP_V6_FLOW: 29195d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 29205d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 29215d317c6aSMerav Sicron break; 29225d317c6aSMerav Sicron case UDP_V4_FLOW: 29235d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v4) 29245d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 29255d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 29265d317c6aSMerav Sicron else 29275d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 29285d317c6aSMerav Sicron break; 29295d317c6aSMerav Sicron case UDP_V6_FLOW: 29305d317c6aSMerav Sicron if (bp->rss_conf_obj.udp_rss_v6) 29315d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST | 29325d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3; 29335d317c6aSMerav Sicron else 29345d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 29355d317c6aSMerav Sicron break; 29365d317c6aSMerav Sicron case IPV4_FLOW: 29375d317c6aSMerav Sicron case IPV6_FLOW: 29385d317c6aSMerav Sicron info->data = RXH_IP_SRC | RXH_IP_DST; 29395d317c6aSMerav Sicron break; 29405d317c6aSMerav Sicron default: 29415d317c6aSMerav Sicron info->data = 0; 29425d317c6aSMerav Sicron break; 29435d317c6aSMerav Sicron } 29445d317c6aSMerav Sicron 29455d317c6aSMerav Sicron return 0; 29465d317c6aSMerav Sicron } 29475d317c6aSMerav Sicron 2948adfc5217SJeff Kirsher static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2949815c7db5SBen Hutchings u32 *rules __always_unused) 2950adfc5217SJeff Kirsher { 2951adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 2952adfc5217SJeff Kirsher 2953adfc5217SJeff Kirsher switch (info->cmd) { 2954adfc5217SJeff Kirsher case ETHTOOL_GRXRINGS: 2955adfc5217SJeff Kirsher info->data = BNX2X_NUM_ETH_QUEUES(bp); 2956adfc5217SJeff Kirsher return 0; 29575d317c6aSMerav Sicron case ETHTOOL_GRXFH: 29585d317c6aSMerav Sicron return bnx2x_get_rss_flags(bp, info); 29595d317c6aSMerav Sicron default: 29605d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 29615d317c6aSMerav Sicron return -EOPNOTSUPP; 29625d317c6aSMerav Sicron } 29635d317c6aSMerav Sicron } 2964adfc5217SJeff Kirsher 29655d317c6aSMerav Sicron static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 29665d317c6aSMerav Sicron { 29675d317c6aSMerav Sicron int udp_rss_requested; 29685d317c6aSMerav Sicron 29695d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29705d317c6aSMerav Sicron "Set rss flags command parameters: flow type = %d, data = %llu\n", 29715d317c6aSMerav Sicron info->flow_type, info->data); 29725d317c6aSMerav Sicron 29735d317c6aSMerav Sicron switch (info->flow_type) { 29745d317c6aSMerav Sicron case TCP_V4_FLOW: 29755d317c6aSMerav Sicron case TCP_V6_FLOW: 29765d317c6aSMerav Sicron /* For TCP only 4-tupple hash is supported */ 29775d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 29785d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 29795d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29805d317c6aSMerav Sicron "Command parameters not supported\n"); 29815d317c6aSMerav Sicron return -EINVAL; 29825d317c6aSMerav Sicron } 29832de67439SYuval Mintz return 0; 29845d317c6aSMerav Sicron 29855d317c6aSMerav Sicron case UDP_V4_FLOW: 29865d317c6aSMerav Sicron case UDP_V6_FLOW: 29875d317c6aSMerav Sicron /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 29885d317c6aSMerav Sicron if (info->data == (RXH_IP_SRC | RXH_IP_DST | 29895d317c6aSMerav Sicron RXH_L4_B_0_1 | RXH_L4_B_2_3)) 29905d317c6aSMerav Sicron udp_rss_requested = 1; 29915d317c6aSMerav Sicron else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 29925d317c6aSMerav Sicron udp_rss_requested = 0; 29935d317c6aSMerav Sicron else 29945d317c6aSMerav Sicron return -EINVAL; 29955d317c6aSMerav Sicron if ((info->flow_type == UDP_V4_FLOW) && 29965d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 29975d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 29985d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 29995d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 30005d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 30015d317c6aSMerav Sicron return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 30025d317c6aSMerav Sicron } else if ((info->flow_type == UDP_V6_FLOW) && 30035d317c6aSMerav Sicron (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 30045d317c6aSMerav Sicron bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 30055d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 30065d317c6aSMerav Sicron "rss re-configured, UDP 4-tupple %s\n", 30075d317c6aSMerav Sicron udp_rss_requested ? "enabled" : "disabled"); 3008337da3e3SDan Carpenter return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0); 30095d317c6aSMerav Sicron } 3010924d75abSYuval Mintz return 0; 3011924d75abSYuval Mintz 30125d317c6aSMerav Sicron case IPV4_FLOW: 30135d317c6aSMerav Sicron case IPV6_FLOW: 30145d317c6aSMerav Sicron /* For IP only 2-tupple hash is supported */ 30155d317c6aSMerav Sicron if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 30165d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 30175d317c6aSMerav Sicron "Command parameters not supported\n"); 30185d317c6aSMerav Sicron return -EINVAL; 30195d317c6aSMerav Sicron } 3020924d75abSYuval Mintz return 0; 3021924d75abSYuval Mintz 30225d317c6aSMerav Sicron case SCTP_V4_FLOW: 30235d317c6aSMerav Sicron case AH_ESP_V4_FLOW: 30245d317c6aSMerav Sicron case AH_V4_FLOW: 30255d317c6aSMerav Sicron case ESP_V4_FLOW: 30265d317c6aSMerav Sicron case SCTP_V6_FLOW: 30275d317c6aSMerav Sicron case AH_ESP_V6_FLOW: 30285d317c6aSMerav Sicron case AH_V6_FLOW: 30295d317c6aSMerav Sicron case ESP_V6_FLOW: 30305d317c6aSMerav Sicron case IP_USER_FLOW: 30315d317c6aSMerav Sicron case ETHER_FLOW: 30325d317c6aSMerav Sicron /* RSS is not supported for these protocols */ 30335d317c6aSMerav Sicron if (info->data) { 30345d317c6aSMerav Sicron DP(BNX2X_MSG_ETHTOOL, 30355d317c6aSMerav Sicron "Command parameters not supported\n"); 30365d317c6aSMerav Sicron return -EINVAL; 30375d317c6aSMerav Sicron } 3038924d75abSYuval Mintz return 0; 3039924d75abSYuval Mintz 30405d317c6aSMerav Sicron default: 30415d317c6aSMerav Sicron return -EINVAL; 30425d317c6aSMerav Sicron } 30435d317c6aSMerav Sicron } 30445d317c6aSMerav Sicron 30455d317c6aSMerav Sicron static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 30465d317c6aSMerav Sicron { 30475d317c6aSMerav Sicron struct bnx2x *bp = netdev_priv(dev); 30485d317c6aSMerav Sicron 30495d317c6aSMerav Sicron switch (info->cmd) { 30505d317c6aSMerav Sicron case ETHTOOL_SRXFH: 30515d317c6aSMerav Sicron return bnx2x_set_rss_flags(bp, info); 3052adfc5217SJeff Kirsher default: 305351c1a580SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3054adfc5217SJeff Kirsher return -EOPNOTSUPP; 3055adfc5217SJeff Kirsher } 3056adfc5217SJeff Kirsher } 3057adfc5217SJeff Kirsher 30587850f63fSBen Hutchings static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3059adfc5217SJeff Kirsher { 306096305234SDmitry Kravkov return T_ETH_INDIRECTION_TABLE_SIZE; 30617850f63fSBen Hutchings } 30627850f63fSBen Hutchings 30637850f63fSBen Hutchings static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) 30647850f63fSBen Hutchings { 30657850f63fSBen Hutchings struct bnx2x *bp = netdev_priv(dev); 3066adfc5217SJeff Kirsher u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3067adfc5217SJeff Kirsher size_t i; 3068adfc5217SJeff Kirsher 3069adfc5217SJeff Kirsher /* Get the current configuration of the RSS indirection table */ 3070adfc5217SJeff Kirsher bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3071adfc5217SJeff Kirsher 3072adfc5217SJeff Kirsher /* 3073adfc5217SJeff Kirsher * We can't use a memcpy() as an internal storage of an 3074adfc5217SJeff Kirsher * indirection table is a u8 array while indir->ring_index 3075adfc5217SJeff Kirsher * points to an array of u32. 3076adfc5217SJeff Kirsher * 3077adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3078adfc5217SJeff Kirsher * align the returned table to the Client ID of the leading RSS 3079adfc5217SJeff Kirsher * queue. 3080adfc5217SJeff Kirsher */ 30817850f63fSBen Hutchings for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 30827850f63fSBen Hutchings indir[i] = ind_table[i] - bp->fp->cl_id; 3083adfc5217SJeff Kirsher 3084adfc5217SJeff Kirsher return 0; 3085adfc5217SJeff Kirsher } 3086adfc5217SJeff Kirsher 30877850f63fSBen Hutchings static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) 3088adfc5217SJeff Kirsher { 3089adfc5217SJeff Kirsher struct bnx2x *bp = netdev_priv(dev); 3090adfc5217SJeff Kirsher size_t i; 3091adfc5217SJeff Kirsher 3092adfc5217SJeff Kirsher for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3093adfc5217SJeff Kirsher /* 3094adfc5217SJeff Kirsher * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() 3095adfc5217SJeff Kirsher * as an internal storage of an indirection table is a u8 array 3096adfc5217SJeff Kirsher * while indir->ring_index points to an array of u32. 3097adfc5217SJeff Kirsher * 3098adfc5217SJeff Kirsher * Indirection table contains the FW Client IDs, so we need to 3099adfc5217SJeff Kirsher * align the received table to the Client ID of the leading RSS 3100adfc5217SJeff Kirsher * queue 3101adfc5217SJeff Kirsher */ 31025d317c6aSMerav Sicron bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3103adfc5217SJeff Kirsher } 3104adfc5217SJeff Kirsher 31055d317c6aSMerav Sicron return bnx2x_config_rss_eth(bp, false); 3106adfc5217SJeff Kirsher } 3107adfc5217SJeff Kirsher 31080e8d2ec5SMerav Sicron /** 31090e8d2ec5SMerav Sicron * bnx2x_get_channels - gets the number of RSS queues. 31100e8d2ec5SMerav Sicron * 31110e8d2ec5SMerav Sicron * @dev: net device 31120e8d2ec5SMerav Sicron * @channels: returns the number of max / current queues 31130e8d2ec5SMerav Sicron */ 31140e8d2ec5SMerav Sicron static void bnx2x_get_channels(struct net_device *dev, 31150e8d2ec5SMerav Sicron struct ethtool_channels *channels) 31160e8d2ec5SMerav Sicron { 31170e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 31180e8d2ec5SMerav Sicron 31190e8d2ec5SMerav Sicron channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 31200e8d2ec5SMerav Sicron channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 31210e8d2ec5SMerav Sicron } 31220e8d2ec5SMerav Sicron 31230e8d2ec5SMerav Sicron /** 31240e8d2ec5SMerav Sicron * bnx2x_change_num_queues - change the number of RSS queues. 31250e8d2ec5SMerav Sicron * 31260e8d2ec5SMerav Sicron * @bp: bnx2x private structure 31270e8d2ec5SMerav Sicron * 31280e8d2ec5SMerav Sicron * Re-configure interrupt mode to get the new number of MSI-X 31290e8d2ec5SMerav Sicron * vectors and re-add NAPI objects. 31300e8d2ec5SMerav Sicron */ 31310e8d2ec5SMerav Sicron static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 31320e8d2ec5SMerav Sicron { 31330e8d2ec5SMerav Sicron bnx2x_disable_msi(bp); 313455c11941SMerav Sicron bp->num_ethernet_queues = num_rss; 313555c11941SMerav Sicron bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 313655c11941SMerav Sicron BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 31370e8d2ec5SMerav Sicron bnx2x_set_int_mode(bp); 31380e8d2ec5SMerav Sicron } 31390e8d2ec5SMerav Sicron 31400e8d2ec5SMerav Sicron /** 31410e8d2ec5SMerav Sicron * bnx2x_set_channels - sets the number of RSS queues. 31420e8d2ec5SMerav Sicron * 31430e8d2ec5SMerav Sicron * @dev: net device 31440e8d2ec5SMerav Sicron * @channels: includes the number of queues requested 31450e8d2ec5SMerav Sicron */ 31460e8d2ec5SMerav Sicron static int bnx2x_set_channels(struct net_device *dev, 31470e8d2ec5SMerav Sicron struct ethtool_channels *channels) 31480e8d2ec5SMerav Sicron { 31490e8d2ec5SMerav Sicron struct bnx2x *bp = netdev_priv(dev); 31500e8d2ec5SMerav Sicron 31510e8d2ec5SMerav Sicron 31520e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, 31530e8d2ec5SMerav Sicron "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 31540e8d2ec5SMerav Sicron channels->rx_count, channels->tx_count, channels->other_count, 31550e8d2ec5SMerav Sicron channels->combined_count); 31560e8d2ec5SMerav Sicron 31570e8d2ec5SMerav Sicron /* We don't support separate rx / tx channels. 31580e8d2ec5SMerav Sicron * We don't allow setting 'other' channels. 31590e8d2ec5SMerav Sicron */ 31600e8d2ec5SMerav Sicron if (channels->rx_count || channels->tx_count || channels->other_count 31610e8d2ec5SMerav Sicron || (channels->combined_count == 0) || 31620e8d2ec5SMerav Sicron (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 31630e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 31640e8d2ec5SMerav Sicron return -EINVAL; 31650e8d2ec5SMerav Sicron } 31660e8d2ec5SMerav Sicron 31670e8d2ec5SMerav Sicron /* Check if there was a change in the active parameters */ 31680e8d2ec5SMerav Sicron if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 31690e8d2ec5SMerav Sicron DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 31700e8d2ec5SMerav Sicron return 0; 31710e8d2ec5SMerav Sicron } 31720e8d2ec5SMerav Sicron 31730e8d2ec5SMerav Sicron /* Set the requested number of queues in bp context. 31740e8d2ec5SMerav Sicron * Note that the actual number of queues created during load may be 31750e8d2ec5SMerav Sicron * less than requested if memory is low. 31760e8d2ec5SMerav Sicron */ 31770e8d2ec5SMerav Sicron if (unlikely(!netif_running(dev))) { 31780e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 31790e8d2ec5SMerav Sicron return 0; 31800e8d2ec5SMerav Sicron } 31815d07d868SYuval Mintz bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 31820e8d2ec5SMerav Sicron bnx2x_change_num_queues(bp, channels->combined_count); 31830e8d2ec5SMerav Sicron return bnx2x_nic_load(bp, LOAD_NORMAL); 31840e8d2ec5SMerav Sicron } 31850e8d2ec5SMerav Sicron 3186adfc5217SJeff Kirsher static const struct ethtool_ops bnx2x_ethtool_ops = { 3187adfc5217SJeff Kirsher .get_settings = bnx2x_get_settings, 3188adfc5217SJeff Kirsher .set_settings = bnx2x_set_settings, 3189adfc5217SJeff Kirsher .get_drvinfo = bnx2x_get_drvinfo, 3190adfc5217SJeff Kirsher .get_regs_len = bnx2x_get_regs_len, 3191adfc5217SJeff Kirsher .get_regs = bnx2x_get_regs, 319207ba6af4SMiriam Shitrit .get_dump_flag = bnx2x_get_dump_flag, 319307ba6af4SMiriam Shitrit .get_dump_data = bnx2x_get_dump_data, 319407ba6af4SMiriam Shitrit .set_dump = bnx2x_set_dump, 3195adfc5217SJeff Kirsher .get_wol = bnx2x_get_wol, 3196adfc5217SJeff Kirsher .set_wol = bnx2x_set_wol, 3197adfc5217SJeff Kirsher .get_msglevel = bnx2x_get_msglevel, 3198adfc5217SJeff Kirsher .set_msglevel = bnx2x_set_msglevel, 3199adfc5217SJeff Kirsher .nway_reset = bnx2x_nway_reset, 3200adfc5217SJeff Kirsher .get_link = bnx2x_get_link, 3201adfc5217SJeff Kirsher .get_eeprom_len = bnx2x_get_eeprom_len, 3202adfc5217SJeff Kirsher .get_eeprom = bnx2x_get_eeprom, 3203adfc5217SJeff Kirsher .set_eeprom = bnx2x_set_eeprom, 3204adfc5217SJeff Kirsher .get_coalesce = bnx2x_get_coalesce, 3205adfc5217SJeff Kirsher .set_coalesce = bnx2x_set_coalesce, 3206adfc5217SJeff Kirsher .get_ringparam = bnx2x_get_ringparam, 3207adfc5217SJeff Kirsher .set_ringparam = bnx2x_set_ringparam, 3208adfc5217SJeff Kirsher .get_pauseparam = bnx2x_get_pauseparam, 3209adfc5217SJeff Kirsher .set_pauseparam = bnx2x_set_pauseparam, 3210adfc5217SJeff Kirsher .self_test = bnx2x_self_test, 3211adfc5217SJeff Kirsher .get_sset_count = bnx2x_get_sset_count, 3212adfc5217SJeff Kirsher .get_strings = bnx2x_get_strings, 3213adfc5217SJeff Kirsher .set_phys_id = bnx2x_set_phys_id, 3214adfc5217SJeff Kirsher .get_ethtool_stats = bnx2x_get_ethtool_stats, 3215adfc5217SJeff Kirsher .get_rxnfc = bnx2x_get_rxnfc, 32165d317c6aSMerav Sicron .set_rxnfc = bnx2x_set_rxnfc, 32177850f63fSBen Hutchings .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3218adfc5217SJeff Kirsher .get_rxfh_indir = bnx2x_get_rxfh_indir, 3219adfc5217SJeff Kirsher .set_rxfh_indir = bnx2x_set_rxfh_indir, 32200e8d2ec5SMerav Sicron .get_channels = bnx2x_get_channels, 32210e8d2ec5SMerav Sicron .set_channels = bnx2x_set_channels, 322224ea818eSYuval Mintz .get_module_info = bnx2x_get_module_info, 322324ea818eSYuval Mintz .get_module_eeprom = bnx2x_get_module_eeprom, 3224e9939c80SYuval Mintz .get_eee = bnx2x_get_eee, 3225e9939c80SYuval Mintz .set_eee = bnx2x_set_eee, 3226be53ce1eSRichard Cochran .get_ts_info = ethtool_op_get_ts_info, 3227adfc5217SJeff Kirsher }; 3228adfc5217SJeff Kirsher 3229adfc5217SJeff Kirsher void bnx2x_set_ethtool_ops(struct net_device *netdev) 3230adfc5217SJeff Kirsher { 3231adfc5217SJeff Kirsher SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); 3232adfc5217SJeff Kirsher } 3233