1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for 8 * Atlantic hardware abstraction layer. 9 */ 10 11 #include "../aq_hw.h" 12 #include "../aq_hw_utils.h" 13 #include "../aq_pci_func.h" 14 #include "../aq_ring.h" 15 #include "../aq_vec.h" 16 #include "../aq_nic.h" 17 #include "hw_atl_utils.h" 18 #include "hw_atl_llh.h" 19 20 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334 21 22 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360 23 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364 24 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368 25 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C 26 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370 27 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374 28 29 #define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE) 30 #define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE) 31 #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY) 32 #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL) 33 34 #define HW_ATL_FW2X_CTRL_SLEEP_PROXY BIT(CTRL_SLEEP_PROXY) 35 #define HW_ATL_FW2X_CTRL_WOL BIT(CTRL_WOL) 36 #define HW_ATL_FW2X_CTRL_LINK_DROP BIT(CTRL_LINK_DROP) 37 #define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE) 38 #define HW_ATL_FW2X_CTRL_TEMPERATURE BIT(CTRL_TEMPERATURE) 39 #define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE) 40 #define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT) 41 42 #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE) 43 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE) 44 #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE) 45 #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE) 46 47 #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8 48 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E 49 50 struct __packed fw2x_msg_wol_pattern { 51 u8 mask[16]; 52 u32 crc; 53 }; 54 55 struct __packed fw2x_msg_wol { 56 u32 msg_id; 57 u8 hw_addr[ETH_ALEN]; 58 u8 magic_packet_enabled; 59 u8 filter_count; 60 struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT]; 61 u8 link_up_enabled; 62 u8 link_down_enabled; 63 u16 reserved; 64 u32 link_up_timeout; 65 u32 link_down_timeout; 66 }; 67 68 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed); 69 static int aq_fw2x_set_state(struct aq_hw_s *self, 70 enum hal_atl_utils_fw_state_e state); 71 72 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self); 73 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self); 74 static u32 aq_fw2x_state2_get(struct aq_hw_s *self); 75 76 static int aq_fw2x_init(struct aq_hw_s *self) 77 { 78 int err = 0; 79 80 /* check 10 times by 1ms */ 81 err = readx_poll_timeout_atomic(aq_fw2x_mbox_get, 82 self, self->mbox_addr, 83 self->mbox_addr != 0U, 84 1000U, 10000U); 85 86 err = readx_poll_timeout_atomic(aq_fw2x_rpc_get, 87 self, self->rpc_addr, 88 self->rpc_addr != 0U, 89 1000U, 100000U); 90 91 return err; 92 } 93 94 static int aq_fw2x_deinit(struct aq_hw_s *self) 95 { 96 int err = aq_fw2x_set_link_speed(self, 0); 97 98 if (!err) 99 err = aq_fw2x_set_state(self, MPI_DEINIT); 100 101 return err; 102 } 103 104 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed) 105 { 106 enum hw_atl_fw2x_rate rate = 0; 107 108 if (speed & AQ_NIC_RATE_10G) 109 rate |= FW2X_RATE_10G; 110 111 if (speed & AQ_NIC_RATE_5G) 112 rate |= FW2X_RATE_5G; 113 114 if (speed & AQ_NIC_RATE_5GSR) 115 rate |= FW2X_RATE_5G; 116 117 if (speed & AQ_NIC_RATE_2GS) 118 rate |= FW2X_RATE_2G5; 119 120 if (speed & AQ_NIC_RATE_1G) 121 rate |= FW2X_RATE_1G; 122 123 if (speed & AQ_NIC_RATE_100M) 124 rate |= FW2X_RATE_100M; 125 126 return rate; 127 } 128 129 static u32 fw2x_to_eee_mask(u32 speed) 130 { 131 u32 rate = 0; 132 133 if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK) 134 rate |= AQ_NIC_RATE_EEE_10G; 135 if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK) 136 rate |= AQ_NIC_RATE_EEE_5G; 137 if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK) 138 rate |= AQ_NIC_RATE_EEE_2GS; 139 if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK) 140 rate |= AQ_NIC_RATE_EEE_1G; 141 142 return rate; 143 } 144 145 static u32 eee_mask_to_fw2x(u32 speed) 146 { 147 u32 rate = 0; 148 149 if (speed & AQ_NIC_RATE_EEE_10G) 150 rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK; 151 if (speed & AQ_NIC_RATE_EEE_5G) 152 rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK; 153 if (speed & AQ_NIC_RATE_EEE_2GS) 154 rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK; 155 if (speed & AQ_NIC_RATE_EEE_1G) 156 rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK; 157 158 return rate; 159 } 160 161 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed) 162 { 163 u32 val = link_speed_mask_2fw2x_ratemask(speed); 164 165 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val); 166 167 return 0; 168 } 169 170 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state) 171 { 172 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX) 173 *mpi_state |= BIT(CAPS_HI_PAUSE); 174 else 175 *mpi_state &= ~BIT(CAPS_HI_PAUSE); 176 177 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX) 178 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE); 179 else 180 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE); 181 } 182 183 static void aq_fw2x_upd_eee_rate_bits(struct aq_hw_s *self, u32 *mpi_opts, 184 u32 eee_speeds) 185 { 186 *mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK | 187 HW_ATL_FW2X_CAP_EEE_2G5_MASK | 188 HW_ATL_FW2X_CAP_EEE_5G_MASK | 189 HW_ATL_FW2X_CAP_EEE_10G_MASK); 190 191 *mpi_opts |= eee_mask_to_fw2x(eee_speeds); 192 } 193 194 static int aq_fw2x_set_state(struct aq_hw_s *self, 195 enum hal_atl_utils_fw_state_e state) 196 { 197 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 198 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; 199 200 switch (state) { 201 case MPI_INIT: 202 mpi_state &= ~BIT(CAPS_HI_LINK_DROP); 203 aq_fw2x_upd_eee_rate_bits(self, &mpi_state, cfg->eee_speeds); 204 aq_fw2x_set_mpi_flow_control(self, &mpi_state); 205 break; 206 case MPI_DEINIT: 207 mpi_state |= BIT(CAPS_HI_LINK_DROP); 208 break; 209 case MPI_RESET: 210 case MPI_POWER: 211 /* No actions */ 212 break; 213 } 214 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state); 215 return 0; 216 } 217 218 static int aq_fw2x_update_link_status(struct aq_hw_s *self) 219 { 220 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR); 221 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G | 222 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G); 223 struct aq_hw_link_status_s *link_status = &self->aq_link_status; 224 225 if (speed) { 226 if (speed & FW2X_RATE_10G) 227 link_status->mbps = 10000; 228 else if (speed & FW2X_RATE_5G) 229 link_status->mbps = 5000; 230 else if (speed & FW2X_RATE_2G5) 231 link_status->mbps = 2500; 232 else if (speed & FW2X_RATE_1G) 233 link_status->mbps = 1000; 234 else if (speed & FW2X_RATE_100M) 235 link_status->mbps = 100; 236 else 237 link_status->mbps = 10000; 238 } else { 239 link_status->mbps = 0; 240 } 241 242 return 0; 243 } 244 245 static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac) 246 { 247 int err = 0; 248 u32 h = 0U; 249 u32 l = 0U; 250 u32 mac_addr[2] = { 0 }; 251 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR); 252 253 if (efuse_addr != 0) { 254 err = hw_atl_utils_fw_downld_dwords(self, 255 efuse_addr + (40U * 4U), 256 mac_addr, 257 ARRAY_SIZE(mac_addr)); 258 if (err) 259 return err; 260 mac_addr[0] = __swab32(mac_addr[0]); 261 mac_addr[1] = __swab32(mac_addr[1]); 262 } 263 264 ether_addr_copy(mac, (u8 *)mac_addr); 265 266 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) { 267 unsigned int rnd = 0; 268 269 get_random_bytes(&rnd, sizeof(unsigned int)); 270 271 l = 0xE3000000U | (0xFFFFU & rnd) | (0x00 << 16); 272 h = 0x8001300EU; 273 274 mac[5] = (u8)(0xFFU & l); 275 l >>= 8; 276 mac[4] = (u8)(0xFFU & l); 277 l >>= 8; 278 mac[3] = (u8)(0xFFU & l); 279 l >>= 8; 280 mac[2] = (u8)(0xFFU & l); 281 mac[1] = (u8)(0xFFU & h); 282 h >>= 8; 283 mac[0] = (u8)(0xFFU & h); 284 } 285 return err; 286 } 287 288 static int aq_fw2x_update_stats(struct aq_hw_s *self) 289 { 290 int err = 0; 291 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 292 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS); 293 u32 stats_val; 294 295 /* Toggle statistics bit for FW to update */ 296 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS); 297 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 298 299 /* Wait FW to report back */ 300 err = readx_poll_timeout_atomic(aq_fw2x_state2_get, 301 self, stats_val, 302 orig_stats_val != (stats_val & 303 BIT(CAPS_HI_STATISTICS)), 304 1U, 10000U); 305 if (err) 306 return err; 307 308 return hw_atl_utils_update_stats(self); 309 } 310 311 static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp) 312 { 313 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 314 u32 temp_val = mpi_opts & HW_ATL_FW2X_CTRL_TEMPERATURE; 315 u32 phy_temp_offset; 316 u32 temp_res; 317 int err = 0; 318 u32 val; 319 320 phy_temp_offset = self->mbox_addr + 321 offsetof(struct hw_atl_utils_mbox, info) + 322 offsetof(struct hw_aq_info, phy_temperature); 323 /* Toggle statistics bit for FW to 0x36C.18 (CTRL_TEMPERATURE) */ 324 mpi_opts = mpi_opts ^ HW_ATL_FW2X_CTRL_TEMPERATURE; 325 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 326 /* Wait FW to report back */ 327 err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val, 328 temp_val != 329 (val & HW_ATL_FW2X_CTRL_TEMPERATURE), 330 1U, 10000U); 331 err = hw_atl_utils_fw_downld_dwords(self, phy_temp_offset, 332 &temp_res, 1); 333 334 if (err) 335 return err; 336 337 /* Convert PHY temperature from 1/256 degree Celsius 338 * to 1/1000 degree Celsius. 339 */ 340 *temp = temp_res * 1000 / 256; 341 342 return 0; 343 } 344 345 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac) 346 { 347 struct hw_atl_utils_fw_rpc *rpc = NULL; 348 struct offload_info *cfg = NULL; 349 unsigned int rpc_size = 0U; 350 u32 mpi_opts; 351 int err = 0; 352 u32 val; 353 354 rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg); 355 356 err = hw_atl_utils_fw_rpc_wait(self, &rpc); 357 if (err < 0) 358 goto err_exit; 359 360 memset(rpc, 0, rpc_size); 361 cfg = (struct offload_info *)(&rpc->msg_id + 1); 362 363 memcpy(cfg->mac_addr, mac, ETH_ALEN); 364 cfg->len = sizeof(*cfg); 365 366 /* Clear bit 0x36C.23 and 0x36C.22 */ 367 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 368 mpi_opts &= ~HW_ATL_FW2X_CTRL_SLEEP_PROXY; 369 mpi_opts &= ~HW_ATL_FW2X_CTRL_LINK_DROP; 370 371 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 372 373 err = hw_atl_utils_fw_rpc_call(self, rpc_size); 374 if (err < 0) 375 goto err_exit; 376 377 /* Set bit 0x36C.23 */ 378 mpi_opts |= HW_ATL_FW2X_CTRL_SLEEP_PROXY; 379 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 380 381 err = readx_poll_timeout_atomic(aq_fw2x_state2_get, 382 self, val, 383 val & HW_ATL_FW2X_CTRL_SLEEP_PROXY, 384 1U, 10000U); 385 386 err_exit: 387 return err; 388 } 389 390 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac) 391 { 392 struct hw_atl_utils_fw_rpc *rpc = NULL; 393 struct fw2x_msg_wol *msg = NULL; 394 u32 mpi_opts; 395 int err = 0; 396 u32 val; 397 398 err = hw_atl_utils_fw_rpc_wait(self, &rpc); 399 if (err < 0) 400 goto err_exit; 401 402 msg = (struct fw2x_msg_wol *)rpc; 403 404 msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL; 405 msg->magic_packet_enabled = true; 406 memcpy(msg->hw_addr, mac, ETH_ALEN); 407 408 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 409 mpi_opts &= ~(HW_ATL_FW2X_CTRL_SLEEP_PROXY | HW_ATL_FW2X_CTRL_WOL); 410 411 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 412 413 err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg)); 414 if (err < 0) 415 goto err_exit; 416 417 /* Set bit 0x36C.24 */ 418 mpi_opts |= HW_ATL_FW2X_CTRL_WOL; 419 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 420 421 err = readx_poll_timeout_atomic(aq_fw2x_state2_get, 422 self, val, val & HW_ATL_FW2X_CTRL_WOL, 423 1U, 10000U); 424 425 err_exit: 426 return err; 427 } 428 429 static int aq_fw2x_set_power(struct aq_hw_s *self, unsigned int power_state, 430 u8 *mac) 431 { 432 int err = 0; 433 434 if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) { 435 err = aq_fw2x_set_sleep_proxy(self, mac); 436 if (err < 0) 437 goto err_exit; 438 err = aq_fw2x_set_wol_params(self, mac); 439 } 440 441 err_exit: 442 return err; 443 } 444 445 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed) 446 { 447 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 448 449 aq_fw2x_upd_eee_rate_bits(self, &mpi_opts, speed); 450 451 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 452 453 return 0; 454 } 455 456 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate, 457 u32 *supported_rates) 458 { 459 u32 mpi_state; 460 u32 caps_hi; 461 int err = 0; 462 u32 addr = self->mbox_addr + offsetof(struct hw_atl_utils_mbox, info) + 463 offsetof(struct hw_aq_info, caps_hi); 464 465 err = hw_atl_utils_fw_downld_dwords(self, addr, &caps_hi, 466 sizeof(caps_hi) / sizeof(u32)); 467 468 if (err) 469 return err; 470 471 *supported_rates = fw2x_to_eee_mask(caps_hi); 472 473 mpi_state = aq_fw2x_state2_get(self); 474 *rate = fw2x_to_eee_mask(mpi_state); 475 476 return err; 477 } 478 479 static int aq_fw2x_renegotiate(struct aq_hw_s *self) 480 { 481 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 482 483 mpi_opts |= BIT(CTRL_FORCE_RECONNECT); 484 485 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); 486 487 return 0; 488 } 489 490 static int aq_fw2x_set_flow_control(struct aq_hw_s *self) 491 { 492 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); 493 494 aq_fw2x_set_mpi_flow_control(self, &mpi_state); 495 496 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state); 497 498 return 0; 499 } 500 501 static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode) 502 { 503 u32 mpi_state = aq_fw2x_state2_get(self); 504 505 if (mpi_state & HW_ATL_FW2X_CAP_PAUSE) 506 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE) 507 *fcmode = AQ_NIC_FC_RX; 508 else 509 *fcmode = AQ_NIC_FC_RX | AQ_NIC_FC_TX; 510 else 511 if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE) 512 *fcmode = AQ_NIC_FC_TX; 513 else 514 *fcmode = 0; 515 516 return 0; 517 } 518 519 static u32 aq_fw2x_mbox_get(struct aq_hw_s *self) 520 { 521 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR); 522 } 523 524 static u32 aq_fw2x_rpc_get(struct aq_hw_s *self) 525 { 526 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR); 527 } 528 529 static u32 aq_fw2x_state2_get(struct aq_hw_s *self) 530 { 531 return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR); 532 } 533 534 const struct aq_fw_ops aq_fw_2x_ops = { 535 .init = aq_fw2x_init, 536 .deinit = aq_fw2x_deinit, 537 .reset = NULL, 538 .renegotiate = aq_fw2x_renegotiate, 539 .get_mac_permanent = aq_fw2x_get_mac_permanent, 540 .set_link_speed = aq_fw2x_set_link_speed, 541 .set_state = aq_fw2x_set_state, 542 .update_link_status = aq_fw2x_update_link_status, 543 .update_stats = aq_fw2x_update_stats, 544 .get_phy_temp = aq_fw2x_get_phy_temp, 545 .set_power = aq_fw2x_set_power, 546 .set_eee_rate = aq_fw2x_set_eee_rate, 547 .get_eee_rate = aq_fw2x_get_eee_rate, 548 .set_flow_control = aq_fw2x_set_flow_control, 549 .get_flow_control = aq_fw2x_get_flow_control 550 }; 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