175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2843e1396SMark Starovoytov /* Atlantic Network Driver
3843e1396SMark Starovoytov *
4843e1396SMark Starovoytov * Copyright (C) 2014-2019 aQuantia Corporation
5843e1396SMark Starovoytov * Copyright (C) 2019-2020 Marvell International Ltd.
6a57d3929SIgor Russkikh */
7a57d3929SIgor Russkikh
8a57d3929SIgor Russkikh /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
9a57d3929SIgor Russkikh * Atlantic hardware abstraction layer.
10a57d3929SIgor Russkikh */
11a57d3929SIgor Russkikh
12a57d3929SIgor Russkikh #include "../aq_hw.h"
13a57d3929SIgor Russkikh #include "../aq_hw_utils.h"
14a57d3929SIgor Russkikh #include "../aq_pci_func.h"
15a57d3929SIgor Russkikh #include "../aq_ring.h"
16a57d3929SIgor Russkikh #include "../aq_vec.h"
170e1a0ddeSYana Esina #include "../aq_nic.h"
18a57d3929SIgor Russkikh #include "hw_atl_utils.h"
19a57d3929SIgor Russkikh #include "hw_atl_llh.h"
20a57d3929SIgor Russkikh
21d1287ce4SNikita Danilov #define HW_ATL_FW2X_MPI_LED_ADDR 0x31c
223ee5c887SYana Esina #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
23a57d3929SIgor Russkikh
246a7f2277SNikita Danilov #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
256a7f2277SNikita Danilov #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
26a57d3929SIgor Russkikh #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
27a57d3929SIgor Russkikh #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
28a57d3929SIgor Russkikh #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
29a57d3929SIgor Russkikh #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
30a57d3929SIgor Russkikh
31910479a9SEgor Pomozov #define HW_ATL_FW3X_EXT_CONTROL_ADDR 0x378
32910479a9SEgor Pomozov #define HW_ATL_FW3X_EXT_STATE_ADDR 0x37c
33910479a9SEgor Pomozov
34f08a464cSEgor Pomozov #define HW_ATL_FW3X_PTP_ADJ_LSW_ADDR 0x50a0
35f08a464cSEgor Pomozov #define HW_ATL_FW3X_PTP_ADJ_MSW_ADDR 0x50a4
36f08a464cSEgor Pomozov
3735e8e8b4SIgor Russkikh #define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE)
3835e8e8b4SIgor Russkikh #define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE)
390e1a0ddeSYana Esina #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
400e1a0ddeSYana Esina #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
410e1a0ddeSYana Esina
42837c6378SNikita Danilov #define HW_ATL_FW2X_CTRL_WAKE_ON_LINK BIT(CTRL_WAKE_ON_LINK)
430e1a0ddeSYana Esina #define HW_ATL_FW2X_CTRL_SLEEP_PROXY BIT(CTRL_SLEEP_PROXY)
440e1a0ddeSYana Esina #define HW_ATL_FW2X_CTRL_WOL BIT(CTRL_WOL)
450e1a0ddeSYana Esina #define HW_ATL_FW2X_CTRL_LINK_DROP BIT(CTRL_LINK_DROP)
460e1a0ddeSYana Esina #define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE)
478f894011SYana Esina #define HW_ATL_FW2X_CTRL_TEMPERATURE BIT(CTRL_TEMPERATURE)
480e1a0ddeSYana Esina #define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)
49ea4b4d7fSIgor Russkikh #define HW_ATL_FW2X_CTRL_INT_LOOPBACK BIT(CTRL_INT_LOOPBACK)
50ea4b4d7fSIgor Russkikh #define HW_ATL_FW2X_CTRL_EXT_LOOPBACK BIT(CTRL_EXT_LOOPBACK)
51ea4b4d7fSIgor Russkikh #define HW_ATL_FW2X_CTRL_DOWNSHIFT BIT(CTRL_DOWNSHIFT)
520e1a0ddeSYana Esina #define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT)
530e1a0ddeSYana Esina
5492ab6407SYana Esina #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
5592ab6407SYana Esina #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
5692ab6407SYana Esina #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
5792ab6407SYana Esina #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
5892ab6407SYana Esina
5962c1c2e6SDmitry Bogdanov #define HW_ATL_FW2X_CAP_MACSEC BIT(CAPS_LO_MACSEC)
6062c1c2e6SDmitry Bogdanov
610e1a0ddeSYana Esina #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
620e1a0ddeSYana Esina #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
630e1a0ddeSYana Esina
64d1287ce4SNikita Danilov #define HW_ATL_FW_VER_LED 0x03010026U
65ea4b4d7fSIgor Russkikh #define HW_ATL_FW_VER_MEDIA_CONTROL 0x0301005aU
66d1287ce4SNikita Danilov
670e1a0ddeSYana Esina struct __packed fw2x_msg_wol_pattern {
680e1a0ddeSYana Esina u8 mask[16];
690e1a0ddeSYana Esina u32 crc;
700e1a0ddeSYana Esina };
710e1a0ddeSYana Esina
720e1a0ddeSYana Esina struct __packed fw2x_msg_wol {
730e1a0ddeSYana Esina u32 msg_id;
740e1a0ddeSYana Esina u8 hw_addr[ETH_ALEN];
750e1a0ddeSYana Esina u8 magic_packet_enabled;
760e1a0ddeSYana Esina u8 filter_count;
770e1a0ddeSYana Esina struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
780e1a0ddeSYana Esina u8 link_up_enabled;
790e1a0ddeSYana Esina u8 link_down_enabled;
800e1a0ddeSYana Esina u16 reserved;
810e1a0ddeSYana Esina u32 link_up_timeout;
820e1a0ddeSYana Esina u32 link_down_timeout;
830e1a0ddeSYana Esina };
840e1a0ddeSYana Esina
8544e00dd8SIgor Russkikh static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
8644e00dd8SIgor Russkikh static int aq_fw2x_set_state(struct aq_hw_s *self,
8744e00dd8SIgor Russkikh enum hal_atl_utils_fw_state_e state);
8844e00dd8SIgor Russkikh
896a7f2277SNikita Danilov static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);
906a7f2277SNikita Danilov static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);
91dc12f75aSNikita Danilov static int aq_fw2x_settings_get(struct aq_hw_s *self, u32 *addr);
9262c1c2e6SDmitry Bogdanov static u32 aq_fw2x_state_get(struct aq_hw_s *self);
936a7f2277SNikita Danilov static u32 aq_fw2x_state2_get(struct aq_hw_s *self);
946a7f2277SNikita Danilov
aq_fw2x_init(struct aq_hw_s * self)95a57d3929SIgor Russkikh static int aq_fw2x_init(struct aq_hw_s *self)
96a57d3929SIgor Russkikh {
97a57d3929SIgor Russkikh int err = 0;
98a57d3929SIgor Russkikh
99a57d3929SIgor Russkikh /* check 10 times by 1ms */
1006a7f2277SNikita Danilov err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,
1016a7f2277SNikita Danilov self, self->mbox_addr,
1026a7f2277SNikita Danilov self->mbox_addr != 0U,
1036a7f2277SNikita Danilov 1000U, 10000U);
1046a7f2277SNikita Danilov
1056a7f2277SNikita Danilov err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,
1066a7f2277SNikita Danilov self, self->rpc_addr,
1076a7f2277SNikita Danilov self->rpc_addr != 0U,
1086a7f2277SNikita Danilov 1000U, 100000U);
1093ee5c887SYana Esina
110dc12f75aSNikita Danilov err = aq_fw2x_settings_get(self, &self->settings_addr);
111dc12f75aSNikita Danilov
112a57d3929SIgor Russkikh return err;
113a57d3929SIgor Russkikh }
114a57d3929SIgor Russkikh
aq_fw2x_deinit(struct aq_hw_s * self)11544e00dd8SIgor Russkikh static int aq_fw2x_deinit(struct aq_hw_s *self)
11644e00dd8SIgor Russkikh {
11744e00dd8SIgor Russkikh int err = aq_fw2x_set_link_speed(self, 0);
11844e00dd8SIgor Russkikh
11944e00dd8SIgor Russkikh if (!err)
12044e00dd8SIgor Russkikh err = aq_fw2x_set_state(self, MPI_DEINIT);
12144e00dd8SIgor Russkikh
12244e00dd8SIgor Russkikh return err;
12344e00dd8SIgor Russkikh }
12444e00dd8SIgor Russkikh
link_speed_mask_2fw2x_ratemask(u32 speed)125a57d3929SIgor Russkikh static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
126a57d3929SIgor Russkikh {
127a57d3929SIgor Russkikh enum hw_atl_fw2x_rate rate = 0;
128a57d3929SIgor Russkikh
129a57d3929SIgor Russkikh if (speed & AQ_NIC_RATE_10G)
130a57d3929SIgor Russkikh rate |= FW2X_RATE_10G;
131a57d3929SIgor Russkikh
132a57d3929SIgor Russkikh if (speed & AQ_NIC_RATE_5G)
133a57d3929SIgor Russkikh rate |= FW2X_RATE_5G;
134a57d3929SIgor Russkikh
135843e1396SMark Starovoytov if (speed & AQ_NIC_RATE_2G5)
136a57d3929SIgor Russkikh rate |= FW2X_RATE_2G5;
137a57d3929SIgor Russkikh
138a57d3929SIgor Russkikh if (speed & AQ_NIC_RATE_1G)
139a57d3929SIgor Russkikh rate |= FW2X_RATE_1G;
140a57d3929SIgor Russkikh
141a57d3929SIgor Russkikh if (speed & AQ_NIC_RATE_100M)
142a57d3929SIgor Russkikh rate |= FW2X_RATE_100M;
143a57d3929SIgor Russkikh
144a57d3929SIgor Russkikh return rate;
145a57d3929SIgor Russkikh }
146a57d3929SIgor Russkikh
fw2x_to_eee_mask(u32 speed)14792ab6407SYana Esina static u32 fw2x_to_eee_mask(u32 speed)
14892ab6407SYana Esina {
14992ab6407SYana Esina u32 rate = 0;
15092ab6407SYana Esina
15192ab6407SYana Esina if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
15292ab6407SYana Esina rate |= AQ_NIC_RATE_EEE_10G;
15392ab6407SYana Esina if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
15492ab6407SYana Esina rate |= AQ_NIC_RATE_EEE_5G;
15592ab6407SYana Esina if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
156843e1396SMark Starovoytov rate |= AQ_NIC_RATE_EEE_2G5;
15792ab6407SYana Esina if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
15892ab6407SYana Esina rate |= AQ_NIC_RATE_EEE_1G;
15992ab6407SYana Esina
16092ab6407SYana Esina return rate;
16192ab6407SYana Esina }
16292ab6407SYana Esina
eee_mask_to_fw2x(u32 speed)16392ab6407SYana Esina static u32 eee_mask_to_fw2x(u32 speed)
16492ab6407SYana Esina {
16592ab6407SYana Esina u32 rate = 0;
16692ab6407SYana Esina
16792ab6407SYana Esina if (speed & AQ_NIC_RATE_EEE_10G)
16892ab6407SYana Esina rate |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
16992ab6407SYana Esina if (speed & AQ_NIC_RATE_EEE_5G)
17092ab6407SYana Esina rate |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
171843e1396SMark Starovoytov if (speed & AQ_NIC_RATE_EEE_2G5)
17292ab6407SYana Esina rate |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
17392ab6407SYana Esina if (speed & AQ_NIC_RATE_EEE_1G)
17492ab6407SYana Esina rate |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
17592ab6407SYana Esina
17692ab6407SYana Esina return rate;
17792ab6407SYana Esina }
17892ab6407SYana Esina
aq_fw2x_set_link_speed(struct aq_hw_s * self,u32 speed)179a57d3929SIgor Russkikh static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
180a57d3929SIgor Russkikh {
181a57d3929SIgor Russkikh u32 val = link_speed_mask_2fw2x_ratemask(speed);
182a57d3929SIgor Russkikh
183a57d3929SIgor Russkikh aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
184a57d3929SIgor Russkikh
185a57d3929SIgor Russkikh return 0;
186a57d3929SIgor Russkikh }
187a57d3929SIgor Russkikh
aq_fw2x_upd_flow_control_bits(struct aq_hw_s * self,u32 * mpi_state,u32 fc)1888009bb19SNikita Danilov static void aq_fw2x_upd_flow_control_bits(struct aq_hw_s *self,
1898009bb19SNikita Danilov u32 *mpi_state, u32 fc)
190288551deSIgor Russkikh {
1918009bb19SNikita Danilov *mpi_state &= ~(HW_ATL_FW2X_CTRL_PAUSE |
1928009bb19SNikita Danilov HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE);
193288551deSIgor Russkikh
1948009bb19SNikita Danilov switch (fc) {
1958009bb19SNikita Danilov /* There is not explicit mode of RX only pause frames,
1968009bb19SNikita Danilov * thus, we join this mode with FC full.
1978009bb19SNikita Danilov * FC full is either Rx, either Tx, or both.
1988009bb19SNikita Danilov */
1998009bb19SNikita Danilov case AQ_NIC_FC_FULL:
2008009bb19SNikita Danilov case AQ_NIC_FC_RX:
2018009bb19SNikita Danilov *mpi_state |= HW_ATL_FW2X_CTRL_PAUSE |
2028009bb19SNikita Danilov HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE;
2038009bb19SNikita Danilov break;
2048009bb19SNikita Danilov case AQ_NIC_FC_TX:
2058009bb19SNikita Danilov *mpi_state |= HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE;
2068009bb19SNikita Danilov break;
2078009bb19SNikita Danilov }
208288551deSIgor Russkikh }
209288551deSIgor Russkikh
aq_fw2x_upd_eee_rate_bits(struct aq_hw_s * self,u32 * mpi_opts,u32 eee_speeds)21092ab6407SYana Esina static void aq_fw2x_upd_eee_rate_bits(struct aq_hw_s *self, u32 *mpi_opts,
21192ab6407SYana Esina u32 eee_speeds)
21292ab6407SYana Esina {
21392ab6407SYana Esina *mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
21492ab6407SYana Esina HW_ATL_FW2X_CAP_EEE_2G5_MASK |
21592ab6407SYana Esina HW_ATL_FW2X_CAP_EEE_5G_MASK |
21692ab6407SYana Esina HW_ATL_FW2X_CAP_EEE_10G_MASK);
21792ab6407SYana Esina
21892ab6407SYana Esina *mpi_opts |= eee_mask_to_fw2x(eee_speeds);
21992ab6407SYana Esina }
22092ab6407SYana Esina
aq_fw2x_set_state(struct aq_hw_s * self,enum hal_atl_utils_fw_state_e state)221a57d3929SIgor Russkikh static int aq_fw2x_set_state(struct aq_hw_s *self,
222a57d3929SIgor Russkikh enum hal_atl_utils_fw_state_e state)
223a57d3929SIgor Russkikh {
22444e00dd8SIgor Russkikh u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
22592ab6407SYana Esina struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
22644e00dd8SIgor Russkikh
22744e00dd8SIgor Russkikh switch (state) {
22844e00dd8SIgor Russkikh case MPI_INIT:
22944e00dd8SIgor Russkikh mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
23092ab6407SYana Esina aq_fw2x_upd_eee_rate_bits(self, &mpi_state, cfg->eee_speeds);
2318009bb19SNikita Danilov aq_fw2x_upd_flow_control_bits(self, &mpi_state,
2328009bb19SNikita Danilov self->aq_nic_cfg->fc.req);
23344e00dd8SIgor Russkikh break;
23444e00dd8SIgor Russkikh case MPI_DEINIT:
23544e00dd8SIgor Russkikh mpi_state |= BIT(CAPS_HI_LINK_DROP);
23644e00dd8SIgor Russkikh break;
23744e00dd8SIgor Russkikh case MPI_RESET:
23844e00dd8SIgor Russkikh case MPI_POWER:
23944e00dd8SIgor Russkikh /* No actions */
24044e00dd8SIgor Russkikh break;
24144e00dd8SIgor Russkikh }
24244e00dd8SIgor Russkikh aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
2437b0c342fSNikita Danilov
244a57d3929SIgor Russkikh return 0;
245a57d3929SIgor Russkikh }
246a57d3929SIgor Russkikh
aq_fw2x_update_link_status(struct aq_hw_s * self)247a57d3929SIgor Russkikh static int aq_fw2x_update_link_status(struct aq_hw_s *self)
248a57d3929SIgor Russkikh {
249a57d3929SIgor Russkikh struct aq_hw_link_status_s *link_status = &self->aq_link_status;
2507b0c342fSNikita Danilov u32 mpi_state;
2517b0c342fSNikita Danilov u32 speed;
2527b0c342fSNikita Danilov
2537b0c342fSNikita Danilov mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
2547b0c342fSNikita Danilov speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
2557b0c342fSNikita Danilov FW2X_RATE_2G5 | FW2X_RATE_5G |
2567b0c342fSNikita Danilov FW2X_RATE_10G);
257a57d3929SIgor Russkikh
258a57d3929SIgor Russkikh if (speed) {
259a57d3929SIgor Russkikh if (speed & FW2X_RATE_10G)
260a57d3929SIgor Russkikh link_status->mbps = 10000;
261a57d3929SIgor Russkikh else if (speed & FW2X_RATE_5G)
262a57d3929SIgor Russkikh link_status->mbps = 5000;
263a57d3929SIgor Russkikh else if (speed & FW2X_RATE_2G5)
264a57d3929SIgor Russkikh link_status->mbps = 2500;
265a57d3929SIgor Russkikh else if (speed & FW2X_RATE_1G)
266a57d3929SIgor Russkikh link_status->mbps = 1000;
267a57d3929SIgor Russkikh else if (speed & FW2X_RATE_100M)
268a57d3929SIgor Russkikh link_status->mbps = 100;
269a57d3929SIgor Russkikh else
270a57d3929SIgor Russkikh link_status->mbps = 10000;
271a57d3929SIgor Russkikh } else {
272a57d3929SIgor Russkikh link_status->mbps = 0;
273a57d3929SIgor Russkikh }
274071a0204SIgor Russkikh link_status->full_duplex = true;
275a57d3929SIgor Russkikh
276a57d3929SIgor Russkikh return 0;
277a57d3929SIgor Russkikh }
278a57d3929SIgor Russkikh
aq_fw2x_get_mac_permanent(struct aq_hw_s * self,u8 * mac)27976a45194SColin Ian King static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
280a57d3929SIgor Russkikh {
2817b0c342fSNikita Danilov u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
2827b0c342fSNikita Danilov u32 mac_addr[2] = { 0 };
283a57d3929SIgor Russkikh int err = 0;
284a57d3929SIgor Russkikh
285a57d3929SIgor Russkikh if (efuse_addr != 0) {
286a57d3929SIgor Russkikh err = hw_atl_utils_fw_downld_dwords(self,
287a57d3929SIgor Russkikh efuse_addr + (40U * 4U),
288a57d3929SIgor Russkikh mac_addr,
289a57d3929SIgor Russkikh ARRAY_SIZE(mac_addr));
290a57d3929SIgor Russkikh if (err)
291a57d3929SIgor Russkikh return err;
292a57d3929SIgor Russkikh mac_addr[0] = __swab32(mac_addr[0]);
293a57d3929SIgor Russkikh mac_addr[1] = __swab32(mac_addr[1]);
294a57d3929SIgor Russkikh }
295a57d3929SIgor Russkikh
296a57d3929SIgor Russkikh ether_addr_copy(mac, (u8 *)mac_addr);
297a57d3929SIgor Russkikh
298a57d3929SIgor Russkikh return err;
299a57d3929SIgor Russkikh }
300a57d3929SIgor Russkikh
aq_fw2x_update_stats(struct aq_hw_s * self)3010ba4ad32SYueHaibing static int aq_fw2x_update_stats(struct aq_hw_s *self)
302a57d3929SIgor Russkikh {
303a57d3929SIgor Russkikh u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
304a57d3929SIgor Russkikh u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
3056a7f2277SNikita Danilov u32 stats_val;
3067b0c342fSNikita Danilov int err = 0;
307a57d3929SIgor Russkikh
308a57d3929SIgor Russkikh /* Toggle statistics bit for FW to update */
309a57d3929SIgor Russkikh mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
310a57d3929SIgor Russkikh aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
311a57d3929SIgor Russkikh
312a57d3929SIgor Russkikh /* Wait FW to report back */
3136a7f2277SNikita Danilov err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
3146a7f2277SNikita Danilov self, stats_val,
3156a7f2277SNikita Danilov orig_stats_val != (stats_val &
316a57d3929SIgor Russkikh BIT(CAPS_HI_STATISTICS)),
317a57d3929SIgor Russkikh 1U, 10000U);
318a57d3929SIgor Russkikh if (err)
319a57d3929SIgor Russkikh return err;
320a57d3929SIgor Russkikh
321a57d3929SIgor Russkikh return hw_atl_utils_update_stats(self);
322a57d3929SIgor Russkikh }
323a57d3929SIgor Russkikh
aq_fw2x_get_phy_temp(struct aq_hw_s * self,int * temp)3248f894011SYana Esina static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)
3258f894011SYana Esina {
3268f894011SYana Esina u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
3278f894011SYana Esina u32 temp_val = mpi_opts & HW_ATL_FW2X_CTRL_TEMPERATURE;
3288f894011SYana Esina u32 phy_temp_offset;
3298f894011SYana Esina u32 temp_res;
3308f894011SYana Esina int err = 0;
3318f894011SYana Esina u32 val;
3328f894011SYana Esina
3337b0c342fSNikita Danilov phy_temp_offset = self->mbox_addr + offsetof(struct hw_atl_utils_mbox,
3347b0c342fSNikita Danilov info.phy_temperature);
3357b0c342fSNikita Danilov
3368f894011SYana Esina /* Toggle statistics bit for FW to 0x36C.18 (CTRL_TEMPERATURE) */
3378f894011SYana Esina mpi_opts = mpi_opts ^ HW_ATL_FW2X_CTRL_TEMPERATURE;
3388f894011SYana Esina aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
3398f894011SYana Esina /* Wait FW to report back */
3408f894011SYana Esina err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
3418f894011SYana Esina temp_val !=
3428f894011SYana Esina (val & HW_ATL_FW2X_CTRL_TEMPERATURE),
3438f894011SYana Esina 1U, 10000U);
3448f894011SYana Esina err = hw_atl_utils_fw_downld_dwords(self, phy_temp_offset,
3458f894011SYana Esina &temp_res, 1);
3468f894011SYana Esina
3478f894011SYana Esina if (err)
3488f894011SYana Esina return err;
3498f894011SYana Esina
3508f894011SYana Esina /* Convert PHY temperature from 1/256 degree Celsius
3518f894011SYana Esina * to 1/1000 degree Celsius.
3528f894011SYana Esina */
3538dcf2ad3SMark Starovoytov *temp = (int16_t)(temp_res & 0xFFFF) * 1000 / 256;
3548f894011SYana Esina
3558f894011SYana Esina return 0;
3568f894011SYana Esina }
3578f894011SYana Esina
aq_fw2x_set_wol(struct aq_hw_s * self,const u8 * mac)358*76660757SJakub Kicinski static int aq_fw2x_set_wol(struct aq_hw_s *self, const u8 *mac)
359a0da96c0SYana Esina {
3608f60f762SNikita Danilov struct hw_atl_utils_fw_rpc *rpc = NULL;
361837c6378SNikita Danilov struct offload_info *info = NULL;
362837c6378SNikita Danilov u32 wol_bits = 0;
363837c6378SNikita Danilov u32 rpc_size;
364a0da96c0SYana Esina int err = 0;
3656a7f2277SNikita Danilov u32 val;
366a0da96c0SYana Esina
367837c6378SNikita Danilov if (self->aq_nic_cfg->wol & WAKE_PHY) {
368837c6378SNikita Danilov aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR,
369837c6378SNikita Danilov HW_ATL_FW2X_CTRL_LINK_DROP);
370837c6378SNikita Danilov readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
371837c6378SNikita Danilov (val &
372837c6378SNikita Danilov HW_ATL_FW2X_CTRL_LINK_DROP) != 0,
373837c6378SNikita Danilov 1000, 100000);
374837c6378SNikita Danilov wol_bits |= HW_ATL_FW2X_CTRL_WAKE_ON_LINK;
375837c6378SNikita Danilov }
376837c6378SNikita Danilov
377837c6378SNikita Danilov if (self->aq_nic_cfg->wol & WAKE_MAGIC) {
378837c6378SNikita Danilov wol_bits |= HW_ATL_FW2X_CTRL_SLEEP_PROXY |
379837c6378SNikita Danilov HW_ATL_FW2X_CTRL_WOL;
380a0da96c0SYana Esina
381a0da96c0SYana Esina err = hw_atl_utils_fw_rpc_wait(self, &rpc);
382a0da96c0SYana Esina if (err < 0)
383a0da96c0SYana Esina goto err_exit;
384a0da96c0SYana Esina
385837c6378SNikita Danilov rpc_size = sizeof(*info) +
386837c6378SNikita Danilov offsetof(struct hw_atl_utils_fw_rpc, fw2x_offloads);
387a0da96c0SYana Esina memset(rpc, 0, rpc_size);
388837c6378SNikita Danilov info = &rpc->fw2x_offloads;
389837c6378SNikita Danilov memcpy(info->mac_addr, mac, ETH_ALEN);
390837c6378SNikita Danilov info->len = sizeof(*info);
391a0da96c0SYana Esina
392a0da96c0SYana Esina err = hw_atl_utils_fw_rpc_call(self, rpc_size);
393a0da96c0SYana Esina if (err < 0)
394a0da96c0SYana Esina goto err_exit;
395a0da96c0SYana Esina }
396a0da96c0SYana Esina
397837c6378SNikita Danilov aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, wol_bits);
398a0da96c0SYana Esina
399a0da96c0SYana Esina err_exit:
400a0da96c0SYana Esina return err;
401a0da96c0SYana Esina }
402a0da96c0SYana Esina
aq_fw2x_set_power(struct aq_hw_s * self,unsigned int power_state,const u8 * mac)403a0da96c0SYana Esina static int aq_fw2x_set_power(struct aq_hw_s *self, unsigned int power_state,
404*76660757SJakub Kicinski const u8 *mac)
405a0da96c0SYana Esina {
406a0da96c0SYana Esina int err = 0;
407a0da96c0SYana Esina
408837c6378SNikita Danilov if (self->aq_nic_cfg->wol)
409837c6378SNikita Danilov err = aq_fw2x_set_wol(self, mac);
410a0da96c0SYana Esina
411a0da96c0SYana Esina return err;
412a0da96c0SYana Esina }
413a0da96c0SYana Esina
aq_fw2x_send_fw_request(struct aq_hw_s * self,const struct hw_fw_request_iface * fw_req,size_t size)414910479a9SEgor Pomozov static int aq_fw2x_send_fw_request(struct aq_hw_s *self,
415910479a9SEgor Pomozov const struct hw_fw_request_iface *fw_req,
416910479a9SEgor Pomozov size_t size)
417910479a9SEgor Pomozov {
418910479a9SEgor Pomozov u32 ctrl2, orig_ctrl2;
419910479a9SEgor Pomozov u32 dword_cnt;
420910479a9SEgor Pomozov int err = 0;
421910479a9SEgor Pomozov u32 val;
422910479a9SEgor Pomozov
423910479a9SEgor Pomozov /* Write data to drvIface Mailbox */
424910479a9SEgor Pomozov dword_cnt = size / sizeof(u32);
425910479a9SEgor Pomozov if (size % sizeof(u32))
426910479a9SEgor Pomozov dword_cnt++;
427dc12f75aSNikita Danilov err = hw_atl_write_fwcfg_dwords(self, (void *)fw_req, dword_cnt);
428910479a9SEgor Pomozov if (err < 0)
429910479a9SEgor Pomozov goto err_exit;
430910479a9SEgor Pomozov
431910479a9SEgor Pomozov /* Toggle statistics bit for FW to update */
432910479a9SEgor Pomozov ctrl2 = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
433910479a9SEgor Pomozov orig_ctrl2 = ctrl2 & BIT(CAPS_HI_FW_REQUEST);
434910479a9SEgor Pomozov ctrl2 = ctrl2 ^ BIT(CAPS_HI_FW_REQUEST);
435910479a9SEgor Pomozov aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, ctrl2);
436910479a9SEgor Pomozov
437910479a9SEgor Pomozov /* Wait FW to report back */
438910479a9SEgor Pomozov err = readx_poll_timeout_atomic(aq_fw2x_state2_get, self, val,
439910479a9SEgor Pomozov orig_ctrl2 != (val &
440910479a9SEgor Pomozov BIT(CAPS_HI_FW_REQUEST)),
441910479a9SEgor Pomozov 1U, 10000U);
442910479a9SEgor Pomozov
443910479a9SEgor Pomozov err_exit:
444910479a9SEgor Pomozov return err;
445910479a9SEgor Pomozov }
446910479a9SEgor Pomozov
aq_fw3x_enable_ptp(struct aq_hw_s * self,int enable)447910479a9SEgor Pomozov static void aq_fw3x_enable_ptp(struct aq_hw_s *self, int enable)
448910479a9SEgor Pomozov {
449910479a9SEgor Pomozov u32 ptp_opts = aq_hw_read_reg(self, HW_ATL_FW3X_EXT_STATE_ADDR);
450910479a9SEgor Pomozov u32 all_ptp_features = BIT(CAPS_EX_PHY_PTP_EN) |
451910479a9SEgor Pomozov BIT(CAPS_EX_PTP_GPIO_EN);
452910479a9SEgor Pomozov
453910479a9SEgor Pomozov if (enable)
454910479a9SEgor Pomozov ptp_opts |= all_ptp_features;
455910479a9SEgor Pomozov else
456910479a9SEgor Pomozov ptp_opts &= ~all_ptp_features;
457910479a9SEgor Pomozov
458910479a9SEgor Pomozov aq_hw_write_reg(self, HW_ATL_FW3X_EXT_CONTROL_ADDR, ptp_opts);
459910479a9SEgor Pomozov }
460910479a9SEgor Pomozov
aq_fw3x_adjust_ptp(struct aq_hw_s * self,uint64_t adj)461f08a464cSEgor Pomozov static void aq_fw3x_adjust_ptp(struct aq_hw_s *self, uint64_t adj)
462f08a464cSEgor Pomozov {
463f08a464cSEgor Pomozov aq_hw_write_reg(self, HW_ATL_FW3X_PTP_ADJ_LSW_ADDR,
464f08a464cSEgor Pomozov (adj >> 0) & 0xffffffff);
465f08a464cSEgor Pomozov aq_hw_write_reg(self, HW_ATL_FW3X_PTP_ADJ_MSW_ADDR,
466f08a464cSEgor Pomozov (adj >> 32) & 0xffffffff);
467f08a464cSEgor Pomozov }
468f08a464cSEgor Pomozov
aq_fw2x_led_control(struct aq_hw_s * self,u32 mode)469d1287ce4SNikita Danilov static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
470d1287ce4SNikita Danilov {
471d1287ce4SNikita Danilov if (self->fw_ver_actual < HW_ATL_FW_VER_LED)
472d1287ce4SNikita Danilov return -EOPNOTSUPP;
473d1287ce4SNikita Danilov
474d1287ce4SNikita Danilov aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
475d1287ce4SNikita Danilov
476d1287ce4SNikita Danilov return 0;
477d1287ce4SNikita Danilov }
478d1287ce4SNikita Danilov
aq_fw2x_set_eee_rate(struct aq_hw_s * self,u32 speed)47992ab6407SYana Esina static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
48092ab6407SYana Esina {
48192ab6407SYana Esina u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
48292ab6407SYana Esina
48392ab6407SYana Esina aq_fw2x_upd_eee_rate_bits(self, &mpi_opts, speed);
48492ab6407SYana Esina
48592ab6407SYana Esina aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
48692ab6407SYana Esina
48792ab6407SYana Esina return 0;
48892ab6407SYana Esina }
48992ab6407SYana Esina
aq_fw2x_get_eee_rate(struct aq_hw_s * self,u32 * rate,u32 * supported_rates)49092ab6407SYana Esina static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
49192ab6407SYana Esina u32 *supported_rates)
49292ab6407SYana Esina {
49392ab6407SYana Esina u32 mpi_state;
49492ab6407SYana Esina u32 caps_hi;
49592ab6407SYana Esina int err = 0;
4967b0c342fSNikita Danilov u32 offset;
49792ab6407SYana Esina
4987b0c342fSNikita Danilov offset = self->mbox_addr + offsetof(struct hw_atl_utils_mbox,
4997b0c342fSNikita Danilov info.caps_hi);
5007b0c342fSNikita Danilov
5017b0c342fSNikita Danilov err = hw_atl_utils_fw_downld_dwords(self, offset, &caps_hi, 1);
50292ab6407SYana Esina
50392ab6407SYana Esina if (err)
50492ab6407SYana Esina return err;
50592ab6407SYana Esina
50692ab6407SYana Esina *supported_rates = fw2x_to_eee_mask(caps_hi);
50792ab6407SYana Esina
5080b926d46SNikita Danilov mpi_state = aq_fw2x_state2_get(self);
50992ab6407SYana Esina *rate = fw2x_to_eee_mask(mpi_state);
51092ab6407SYana Esina
51192ab6407SYana Esina return err;
51292ab6407SYana Esina }
51392ab6407SYana Esina
aq_fw2x_renegotiate(struct aq_hw_s * self)514b8d68b62SAnton Mikaev static int aq_fw2x_renegotiate(struct aq_hw_s *self)
515b8d68b62SAnton Mikaev {
516b8d68b62SAnton Mikaev u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
517b8d68b62SAnton Mikaev
518b8d68b62SAnton Mikaev mpi_opts |= BIT(CTRL_FORCE_RECONNECT);
519b8d68b62SAnton Mikaev
520b8d68b62SAnton Mikaev aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
521b8d68b62SAnton Mikaev
522b8d68b62SAnton Mikaev return 0;
523b8d68b62SAnton Mikaev }
524b8d68b62SAnton Mikaev
aq_fw2x_set_flow_control(struct aq_hw_s * self)525288551deSIgor Russkikh static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
526288551deSIgor Russkikh {
527288551deSIgor Russkikh u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
528288551deSIgor Russkikh
5298009bb19SNikita Danilov aq_fw2x_upd_flow_control_bits(self, &mpi_state,
5308009bb19SNikita Danilov self->aq_nic_cfg->fc.req);
531288551deSIgor Russkikh
532288551deSIgor Russkikh aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
533288551deSIgor Russkikh
534288551deSIgor Russkikh return 0;
535288551deSIgor Russkikh }
536288551deSIgor Russkikh
aq_fw2x_get_flow_control(struct aq_hw_s * self,u32 * fcmode)53735e8e8b4SIgor Russkikh static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
53835e8e8b4SIgor Russkikh {
5390b926d46SNikita Danilov u32 mpi_state = aq_fw2x_state2_get(self);
5408009bb19SNikita Danilov *fcmode = 0;
54135e8e8b4SIgor Russkikh
54235e8e8b4SIgor Russkikh if (mpi_state & HW_ATL_FW2X_CAP_PAUSE)
5438009bb19SNikita Danilov *fcmode |= AQ_NIC_FC_RX;
5448009bb19SNikita Danilov
54535e8e8b4SIgor Russkikh if (mpi_state & HW_ATL_FW2X_CAP_ASYM_PAUSE)
5468009bb19SNikita Danilov *fcmode |= AQ_NIC_FC_TX;
54735e8e8b4SIgor Russkikh
54835e8e8b4SIgor Russkikh return 0;
54935e8e8b4SIgor Russkikh }
55035e8e8b4SIgor Russkikh
aq_fw2x_set_phyloopback(struct aq_hw_s * self,u32 mode,bool enable)551ea4b4d7fSIgor Russkikh static int aq_fw2x_set_phyloopback(struct aq_hw_s *self, u32 mode, bool enable)
552ea4b4d7fSIgor Russkikh {
553ea4b4d7fSIgor Russkikh u32 mpi_opts;
554ea4b4d7fSIgor Russkikh
555ea4b4d7fSIgor Russkikh switch (mode) {
556ea4b4d7fSIgor Russkikh case AQ_HW_LOOPBACK_PHYINT_SYS:
557ea4b4d7fSIgor Russkikh mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
558ea4b4d7fSIgor Russkikh if (enable)
559ea4b4d7fSIgor Russkikh mpi_opts |= HW_ATL_FW2X_CTRL_INT_LOOPBACK;
560ea4b4d7fSIgor Russkikh else
561ea4b4d7fSIgor Russkikh mpi_opts &= ~HW_ATL_FW2X_CTRL_INT_LOOPBACK;
562ea4b4d7fSIgor Russkikh aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
563ea4b4d7fSIgor Russkikh break;
564ea4b4d7fSIgor Russkikh case AQ_HW_LOOPBACK_PHYEXT_SYS:
565ea4b4d7fSIgor Russkikh mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
566ea4b4d7fSIgor Russkikh if (enable)
567ea4b4d7fSIgor Russkikh mpi_opts |= HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
568ea4b4d7fSIgor Russkikh else
569ea4b4d7fSIgor Russkikh mpi_opts &= ~HW_ATL_FW2X_CTRL_EXT_LOOPBACK;
570ea4b4d7fSIgor Russkikh aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
571ea4b4d7fSIgor Russkikh break;
572ea4b4d7fSIgor Russkikh default:
573ea4b4d7fSIgor Russkikh return -EINVAL;
574ea4b4d7fSIgor Russkikh }
5757b0c342fSNikita Danilov
576ea4b4d7fSIgor Russkikh return 0;
577ea4b4d7fSIgor Russkikh }
578ea4b4d7fSIgor Russkikh
aq_fw2x_mbox_get(struct aq_hw_s * self)5796a7f2277SNikita Danilov static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
5806a7f2277SNikita Danilov {
5816a7f2277SNikita Danilov return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
5826a7f2277SNikita Danilov }
5836a7f2277SNikita Danilov
aq_fw2x_rpc_get(struct aq_hw_s * self)5846a7f2277SNikita Danilov static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)
5856a7f2277SNikita Danilov {
5866a7f2277SNikita Danilov return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
5876a7f2277SNikita Danilov }
5886a7f2277SNikita Danilov
aq_fw2x_settings_get(struct aq_hw_s * self,u32 * addr)589dc12f75aSNikita Danilov static int aq_fw2x_settings_get(struct aq_hw_s *self, u32 *addr)
590dc12f75aSNikita Danilov {
591dc12f75aSNikita Danilov int err = 0;
592dc12f75aSNikita Danilov u32 offset;
593dc12f75aSNikita Danilov
594dc12f75aSNikita Danilov offset = self->mbox_addr + offsetof(struct hw_atl_utils_mbox,
595dc12f75aSNikita Danilov info.setting_address);
596dc12f75aSNikita Danilov
597dc12f75aSNikita Danilov err = hw_atl_utils_fw_downld_dwords(self, offset, addr, 1);
598dc12f75aSNikita Danilov
599dc12f75aSNikita Danilov return err;
600dc12f75aSNikita Danilov }
601dc12f75aSNikita Danilov
aq_fw2x_state_get(struct aq_hw_s * self)60262c1c2e6SDmitry Bogdanov static u32 aq_fw2x_state_get(struct aq_hw_s *self)
60362c1c2e6SDmitry Bogdanov {
60462c1c2e6SDmitry Bogdanov return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
60562c1c2e6SDmitry Bogdanov }
60662c1c2e6SDmitry Bogdanov
aq_fw2x_state2_get(struct aq_hw_s * self)6076a7f2277SNikita Danilov static u32 aq_fw2x_state2_get(struct aq_hw_s *self)
6086a7f2277SNikita Danilov {
6096a7f2277SNikita Danilov return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
6106a7f2277SNikita Danilov }
6116a7f2277SNikita Danilov
aq_fw2x_set_downshift(struct aq_hw_s * self,u32 counter)612e193c3abSIgor Russkikh static int aq_fw2x_set_downshift(struct aq_hw_s *self, u32 counter)
613e193c3abSIgor Russkikh {
614e193c3abSIgor Russkikh int err = 0;
615e193c3abSIgor Russkikh u32 mpi_opts;
616e193c3abSIgor Russkikh u32 offset;
617e193c3abSIgor Russkikh
618e193c3abSIgor Russkikh offset = offsetof(struct hw_atl_utils_settings, downshift_retry_count);
619e193c3abSIgor Russkikh err = hw_atl_write_fwsettings_dwords(self, offset, &counter, 1);
620e193c3abSIgor Russkikh if (err)
621e193c3abSIgor Russkikh return err;
622e193c3abSIgor Russkikh
623e193c3abSIgor Russkikh mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
624e193c3abSIgor Russkikh if (counter)
625e193c3abSIgor Russkikh mpi_opts |= HW_ATL_FW2X_CTRL_DOWNSHIFT;
626e193c3abSIgor Russkikh else
627e193c3abSIgor Russkikh mpi_opts &= ~HW_ATL_FW2X_CTRL_DOWNSHIFT;
628e193c3abSIgor Russkikh aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
629e193c3abSIgor Russkikh
630e193c3abSIgor Russkikh return err;
631e193c3abSIgor Russkikh }
632e193c3abSIgor Russkikh
aq_fw2x_set_media_detect(struct aq_hw_s * self,bool on)63360db5e40SIgor Russkikh static int aq_fw2x_set_media_detect(struct aq_hw_s *self, bool on)
63460db5e40SIgor Russkikh {
63560db5e40SIgor Russkikh u32 enable;
63660db5e40SIgor Russkikh u32 offset;
63760db5e40SIgor Russkikh
63860db5e40SIgor Russkikh if (self->fw_ver_actual < HW_ATL_FW_VER_MEDIA_CONTROL)
63960db5e40SIgor Russkikh return -EOPNOTSUPP;
64060db5e40SIgor Russkikh
64160db5e40SIgor Russkikh offset = offsetof(struct hw_atl_utils_settings, media_detect);
64260db5e40SIgor Russkikh enable = on;
64360db5e40SIgor Russkikh
64460db5e40SIgor Russkikh return hw_atl_write_fwsettings_dwords(self, offset, &enable, 1);
64560db5e40SIgor Russkikh }
64660db5e40SIgor Russkikh
aq_fw2x_get_link_capabilities(struct aq_hw_s * self)64762c1c2e6SDmitry Bogdanov static u32 aq_fw2x_get_link_capabilities(struct aq_hw_s *self)
64862c1c2e6SDmitry Bogdanov {
64962c1c2e6SDmitry Bogdanov int err = 0;
65062c1c2e6SDmitry Bogdanov u32 offset;
65162c1c2e6SDmitry Bogdanov u32 val;
65262c1c2e6SDmitry Bogdanov
65362c1c2e6SDmitry Bogdanov offset = self->mbox_addr +
65462c1c2e6SDmitry Bogdanov offsetof(struct hw_atl_utils_mbox, info.caps_lo);
65562c1c2e6SDmitry Bogdanov
65662c1c2e6SDmitry Bogdanov err = hw_atl_utils_fw_downld_dwords(self, offset, &val, 1);
65762c1c2e6SDmitry Bogdanov
65862c1c2e6SDmitry Bogdanov if (err)
65962c1c2e6SDmitry Bogdanov return 0;
66062c1c2e6SDmitry Bogdanov
66162c1c2e6SDmitry Bogdanov return val;
66262c1c2e6SDmitry Bogdanov }
66362c1c2e6SDmitry Bogdanov
aq_fw2x_send_macsec_req(struct aq_hw_s * hw,struct macsec_msg_fw_request * req,struct macsec_msg_fw_response * response)66462c1c2e6SDmitry Bogdanov static int aq_fw2x_send_macsec_req(struct aq_hw_s *hw,
66562c1c2e6SDmitry Bogdanov struct macsec_msg_fw_request *req,
66662c1c2e6SDmitry Bogdanov struct macsec_msg_fw_response *response)
66762c1c2e6SDmitry Bogdanov {
66862c1c2e6SDmitry Bogdanov u32 low_status, low_req = 0;
66962c1c2e6SDmitry Bogdanov u32 dword_cnt;
67062c1c2e6SDmitry Bogdanov u32 caps_lo;
67162c1c2e6SDmitry Bogdanov u32 offset;
67262c1c2e6SDmitry Bogdanov int err;
67362c1c2e6SDmitry Bogdanov
67462c1c2e6SDmitry Bogdanov if (!req || !response)
67562c1c2e6SDmitry Bogdanov return -EINVAL;
67662c1c2e6SDmitry Bogdanov
67762c1c2e6SDmitry Bogdanov caps_lo = aq_fw2x_get_link_capabilities(hw);
67862c1c2e6SDmitry Bogdanov if (!(caps_lo & BIT(CAPS_LO_MACSEC)))
67962c1c2e6SDmitry Bogdanov return -EOPNOTSUPP;
68062c1c2e6SDmitry Bogdanov
68162c1c2e6SDmitry Bogdanov /* Write macsec request to cfg memory */
68262c1c2e6SDmitry Bogdanov dword_cnt = (sizeof(*req) + sizeof(u32) - 1) / sizeof(u32);
68362c1c2e6SDmitry Bogdanov err = hw_atl_write_fwcfg_dwords(hw, (void *)req, dword_cnt);
68462c1c2e6SDmitry Bogdanov if (err < 0)
68562c1c2e6SDmitry Bogdanov return err;
68662c1c2e6SDmitry Bogdanov
68762c1c2e6SDmitry Bogdanov /* Toggle 0x368.CAPS_LO_MACSEC bit */
68862c1c2e6SDmitry Bogdanov low_req = aq_hw_read_reg(hw, HW_ATL_FW2X_MPI_CONTROL_ADDR);
68962c1c2e6SDmitry Bogdanov low_req ^= HW_ATL_FW2X_CAP_MACSEC;
69062c1c2e6SDmitry Bogdanov aq_hw_write_reg(hw, HW_ATL_FW2X_MPI_CONTROL_ADDR, low_req);
69162c1c2e6SDmitry Bogdanov
69262c1c2e6SDmitry Bogdanov /* Wait FW to report back */
69362c1c2e6SDmitry Bogdanov err = readx_poll_timeout_atomic(aq_fw2x_state_get, hw, low_status,
69462c1c2e6SDmitry Bogdanov low_req != (low_status & BIT(CAPS_LO_MACSEC)), 1U, 10000U);
69562c1c2e6SDmitry Bogdanov if (err)
69662c1c2e6SDmitry Bogdanov return -EIO;
69762c1c2e6SDmitry Bogdanov
69862c1c2e6SDmitry Bogdanov /* Read status of write operation */
69962c1c2e6SDmitry Bogdanov offset = hw->rpc_addr + sizeof(u32);
70062c1c2e6SDmitry Bogdanov err = hw_atl_utils_fw_downld_dwords(hw, offset, (u32 *)(void *)response,
70162c1c2e6SDmitry Bogdanov sizeof(*response) / sizeof(u32));
70262c1c2e6SDmitry Bogdanov
70362c1c2e6SDmitry Bogdanov return err;
70462c1c2e6SDmitry Bogdanov }
70562c1c2e6SDmitry Bogdanov
706a57d3929SIgor Russkikh const struct aq_fw_ops aq_fw_2x_ops = {
707a57d3929SIgor Russkikh .init = aq_fw2x_init,
70844e00dd8SIgor Russkikh .deinit = aq_fw2x_deinit,
709a57d3929SIgor Russkikh .reset = NULL,
710b8d68b62SAnton Mikaev .renegotiate = aq_fw2x_renegotiate,
711a57d3929SIgor Russkikh .get_mac_permanent = aq_fw2x_get_mac_permanent,
712a57d3929SIgor Russkikh .set_link_speed = aq_fw2x_set_link_speed,
713a57d3929SIgor Russkikh .set_state = aq_fw2x_set_state,
714a57d3929SIgor Russkikh .update_link_status = aq_fw2x_update_link_status,
715a57d3929SIgor Russkikh .update_stats = aq_fw2x_update_stats,
7168dcf2ad3SMark Starovoytov .get_mac_temp = NULL,
7178f894011SYana Esina .get_phy_temp = aq_fw2x_get_phy_temp,
718a0da96c0SYana Esina .set_power = aq_fw2x_set_power,
71992ab6407SYana Esina .set_eee_rate = aq_fw2x_set_eee_rate,
72092ab6407SYana Esina .get_eee_rate = aq_fw2x_get_eee_rate,
721288551deSIgor Russkikh .set_flow_control = aq_fw2x_set_flow_control,
722910479a9SEgor Pomozov .get_flow_control = aq_fw2x_get_flow_control,
723910479a9SEgor Pomozov .send_fw_request = aq_fw2x_send_fw_request,
724910479a9SEgor Pomozov .enable_ptp = aq_fw3x_enable_ptp,
725d1287ce4SNikita Danilov .led_control = aq_fw2x_led_control,
726ea4b4d7fSIgor Russkikh .set_phyloopback = aq_fw2x_set_phyloopback,
727e193c3abSIgor Russkikh .set_downshift = aq_fw2x_set_downshift,
72860db5e40SIgor Russkikh .set_media_detect = aq_fw2x_set_media_detect,
729f08a464cSEgor Pomozov .adjust_ptp = aq_fw3x_adjust_ptp,
73062c1c2e6SDmitry Bogdanov .get_link_capabilities = aq_fw2x_get_link_capabilities,
73162c1c2e6SDmitry Bogdanov .send_macsec_req = aq_fw2x_send_macsec_req,
732a57d3929SIgor Russkikh };
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