1 /* Applied Micro X-Gene SoC Ethernet Driver
2  *
3  * Copyright (c) 2014, Applied Micro Circuits Corporation
4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
5  *	    Ravi Patel <rapatel@apm.com>
6  *	    Keyur Chudgar <kchudgar@apm.com>
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #ifndef __XGENE_ENET_MAIN_H__
23 #define __XGENE_ENET_MAIN_H__
24 
25 #include <linux/acpi.h>
26 #include <linux/clk.h>
27 #include <linux/efi.h>
28 #include <linux/io.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_net.h>
31 #include <linux/of_mdio.h>
32 #include <linux/module.h>
33 #include <net/ip.h>
34 #include <linux/prefetch.h>
35 #include <linux/if_vlan.h>
36 #include <linux/phy.h>
37 #include "xgene_enet_hw.h"
38 #include "xgene_enet_ring2.h"
39 
40 #define XGENE_DRV_VERSION	"v1.0"
41 #define XGENE_ENET_MAX_MTU	1536
42 #define SKB_BUFFER_SIZE		(XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
43 #define BUFLEN_16K	(16 * 1024)
44 #define NUM_PKT_BUF	64
45 #define NUM_BUFPOOL	32
46 #define MAX_EXP_BUFFS	256
47 #define XGENE_ENET_MSS	1448
48 #define XGENE_MIN_ENET_FRAME_SIZE	60
49 
50 #define START_CPU_BUFNUM_0	0
51 #define START_ETH_BUFNUM_0	2
52 #define START_BP_BUFNUM_0	0x22
53 #define START_RING_NUM_0	8
54 #define START_CPU_BUFNUM_1	12
55 #define START_ETH_BUFNUM_1	10
56 #define START_BP_BUFNUM_1	0x2A
57 #define START_RING_NUM_1	264
58 
59 #define X2_START_CPU_BUFNUM_0	0
60 #define X2_START_ETH_BUFNUM_0	0
61 #define X2_START_BP_BUFNUM_0	0x20
62 #define X2_START_RING_NUM_0	0
63 #define X2_START_CPU_BUFNUM_1	0xc
64 #define X2_START_ETH_BUFNUM_1	0
65 #define X2_START_BP_BUFNUM_1	0x20
66 #define X2_START_RING_NUM_1	256
67 
68 #define IRQ_ID_SIZE		16
69 #define XGENE_MAX_TXC_RINGS	1
70 
71 #define PHY_POLL_LINK_ON	(10 * HZ)
72 #define PHY_POLL_LINK_OFF	(PHY_POLL_LINK_ON / 5)
73 
74 enum xgene_enet_id {
75 	XGENE_ENET1 = 1,
76 	XGENE_ENET2
77 };
78 
79 /* software context of a descriptor ring */
80 struct xgene_enet_desc_ring {
81 	struct net_device *ndev;
82 	u16 id;
83 	u16 num;
84 	u16 head;
85 	u16 tail;
86 	u16 exp_buf_tail;
87 	u16 slots;
88 	u16 irq;
89 	char irq_name[IRQ_ID_SIZE];
90 	u32 size;
91 	u32 state[X2_NUM_RING_CONFIG];
92 	void __iomem *cmd_base;
93 	void __iomem *cmd;
94 	dma_addr_t dma;
95 	dma_addr_t irq_mbox_dma;
96 	void *irq_mbox_addr;
97 	u16 dst_ring_num;
98 	u8 nbufpool;
99 	struct sk_buff *(*rx_skb);
100 	struct sk_buff *(*cp_skb);
101 	dma_addr_t *frag_dma_addr;
102 	enum xgene_enet_ring_cfgsize cfgsize;
103 	struct xgene_enet_desc_ring *cp_ring;
104 	struct xgene_enet_desc_ring *buf_pool;
105 	struct napi_struct napi;
106 	union {
107 		void *desc_addr;
108 		struct xgene_enet_raw_desc *raw_desc;
109 		struct xgene_enet_raw_desc16 *raw_desc16;
110 	};
111 	__le64 *exp_bufs;
112 };
113 
114 struct xgene_mac_ops {
115 	void (*init)(struct xgene_enet_pdata *pdata);
116 	void (*reset)(struct xgene_enet_pdata *pdata);
117 	void (*tx_enable)(struct xgene_enet_pdata *pdata);
118 	void (*rx_enable)(struct xgene_enet_pdata *pdata);
119 	void (*tx_disable)(struct xgene_enet_pdata *pdata);
120 	void (*rx_disable)(struct xgene_enet_pdata *pdata);
121 	void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
122 	void (*set_mss)(struct xgene_enet_pdata *pdata);
123 	void (*link_state)(struct work_struct *work);
124 };
125 
126 struct xgene_port_ops {
127 	int (*reset)(struct xgene_enet_pdata *pdata);
128 	void (*cle_bypass)(struct xgene_enet_pdata *pdata,
129 			   u32 dst_ring_num, u16 bufpool_id);
130 	void (*shutdown)(struct xgene_enet_pdata *pdata);
131 };
132 
133 struct xgene_ring_ops {
134 	u8 num_ring_config;
135 	u8 num_ring_id_shift;
136 	struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
137 	void (*clear)(struct xgene_enet_desc_ring *);
138 	void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
139 	u32 (*len)(struct xgene_enet_desc_ring *);
140 };
141 
142 /* ethernet private data */
143 struct xgene_enet_pdata {
144 	struct net_device *ndev;
145 	struct mii_bus *mdio_bus;
146 	struct phy_device *phy_dev;
147 	int phy_speed;
148 	struct clk *clk;
149 	struct platform_device *pdev;
150 	enum xgene_enet_id enet_id;
151 	struct xgene_enet_desc_ring *tx_ring;
152 	struct xgene_enet_desc_ring *rx_ring;
153 	char *dev_name;
154 	u32 rx_buff_cnt;
155 	u32 tx_qcnt_hi;
156 	u32 cp_qcnt_hi;
157 	u32 cp_qcnt_low;
158 	u32 rx_irq;
159 	u32 txc_irq;
160 	u8 cq_cnt;
161 	void __iomem *eth_csr_addr;
162 	void __iomem *eth_ring_if_addr;
163 	void __iomem *eth_diag_csr_addr;
164 	void __iomem *mcx_mac_addr;
165 	void __iomem *mcx_mac_csr_addr;
166 	void __iomem *base_addr;
167 	void __iomem *ring_csr_addr;
168 	void __iomem *ring_cmd_addr;
169 	int phy_mode;
170 	enum xgene_enet_rm rm;
171 	struct rtnl_link_stats64 stats;
172 	struct xgene_mac_ops *mac_ops;
173 	struct xgene_port_ops *port_ops;
174 	struct xgene_ring_ops *ring_ops;
175 	struct delayed_work link_work;
176 	u32 port_id;
177 	u8 cpu_bufnum;
178 	u8 eth_bufnum;
179 	u8 bp_bufnum;
180 	u16 ring_num;
181 	u32 mss;
182 };
183 
184 struct xgene_indirect_ctl {
185 	void __iomem *addr;
186 	void __iomem *ctl;
187 	void __iomem *cmd;
188 	void __iomem *cmd_done;
189 };
190 
191 /* Set the specified value into a bit-field defined by its starting position
192  * and length within a single u64.
193  */
194 static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
195 {
196 	return (val & ((1ULL << len) - 1)) << pos;
197 }
198 
199 #define SET_VAL(field, val) \
200 		xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
201 
202 #define SET_BIT(field) \
203 		xgene_enet_set_field_value(field ## _POS, 1, 1)
204 
205 /* Get the value from a bit-field defined by its starting position
206  * and length within the specified u64.
207  */
208 static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
209 {
210 	return (src >> pos) & ((1ULL << len) - 1);
211 }
212 
213 #define GET_VAL(field, src) \
214 		xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
215 
216 #define GET_BIT(field, src) \
217 		xgene_enet_get_field_value(field ## _POS, 1, src)
218 
219 static inline struct device *ndev_to_dev(struct net_device *ndev)
220 {
221 	return ndev->dev.parent;
222 }
223 
224 void xgene_enet_set_ethtool_ops(struct net_device *netdev);
225 
226 #endif /* __XGENE_ENET_MAIN_H__ */
227