1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Applied Micro X-Gene SoC Ethernet Driver
3  *
4  * Copyright (c) 2014, Applied Micro Circuits Corporation
5  * Authors: Iyappan Subramanian <isubramanian@apm.com>
6  *	    Ravi Patel <rapatel@apm.com>
7  *	    Keyur Chudgar <kchudgar@apm.com>
8  */
9 
10 #ifndef __XGENE_ENET_MAIN_H__
11 #define __XGENE_ENET_MAIN_H__
12 
13 #include <linux/acpi.h>
14 #include <linux/clk.h>
15 #include <linux/efi.h>
16 #include <linux/irq.h>
17 #include <linux/io.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_net.h>
20 #include <linux/of_mdio.h>
21 #include <linux/mdio/mdio-xgene.h>
22 #include <linux/module.h>
23 #include <net/ip.h>
24 #include <linux/prefetch.h>
25 #include <linux/if_vlan.h>
26 #include <linux/phy.h>
27 #include "xgene_enet_hw.h"
28 #include "xgene_enet_cle.h"
29 #include "xgene_enet_ring2.h"
30 
31 #define ETHER_MIN_PACKET	64
32 #define ETHER_STD_PACKET	1518
33 #define XGENE_ENET_STD_MTU	1536
34 #define XGENE_ENET_MAX_MTU	9600
35 #define SKB_BUFFER_SIZE		(XGENE_ENET_STD_MTU - NET_IP_ALIGN)
36 
37 #define BUFLEN_16K	(16 * 1024)
38 #define NUM_PKT_BUF	1024
39 #define NUM_BUFPOOL	32
40 #define NUM_NXTBUFPOOL	8
41 #define MAX_EXP_BUFFS	256
42 #define NUM_MSS_REG	4
43 #define XGENE_MIN_ENET_FRAME_SIZE	60
44 
45 #define XGENE_MAX_ENET_IRQ	16
46 #define XGENE_NUM_RX_RING	8
47 #define XGENE_NUM_TX_RING	8
48 #define XGENE_NUM_TXC_RING	8
49 
50 #define START_CPU_BUFNUM_0	0
51 #define START_ETH_BUFNUM_0	2
52 #define START_BP_BUFNUM_0	0x22
53 #define START_RING_NUM_0	8
54 #define START_CPU_BUFNUM_1	12
55 #define START_ETH_BUFNUM_1	10
56 #define START_BP_BUFNUM_1	0x2A
57 #define START_RING_NUM_1	264
58 
59 #define XG_START_CPU_BUFNUM_1	12
60 #define XG_START_ETH_BUFNUM_1	2
61 #define XG_START_BP_BUFNUM_1	0x22
62 #define XG_START_RING_NUM_1	264
63 
64 #define X2_START_CPU_BUFNUM_0	0
65 #define X2_START_ETH_BUFNUM_0	0
66 #define X2_START_BP_BUFNUM_0	0x20
67 #define X2_START_RING_NUM_0	0
68 #define X2_START_CPU_BUFNUM_1	0xc
69 #define X2_START_ETH_BUFNUM_1	0
70 #define X2_START_BP_BUFNUM_1	0x20
71 #define X2_START_RING_NUM_1	256
72 
73 #define IRQ_ID_SIZE		16
74 
75 #define PHY_POLL_LINK_ON	(10 * HZ)
76 #define PHY_POLL_LINK_OFF	(PHY_POLL_LINK_ON / 5)
77 
78 enum xgene_enet_id {
79 	XGENE_ENET1 = 1,
80 	XGENE_ENET2
81 };
82 
83 enum xgene_enet_buf_len {
84 	SIZE_2K = 2048,
85 	SIZE_4K = 4096,
86 	SIZE_16K = 16384
87 };
88 
89 /* software context of a descriptor ring */
90 struct xgene_enet_desc_ring {
91 	struct net_device *ndev;
92 	u16 id;
93 	u16 num;
94 	u16 head;
95 	u16 tail;
96 	u16 exp_buf_tail;
97 	u16 slots;
98 	u16 irq;
99 	char irq_name[IRQ_ID_SIZE];
100 	u32 size;
101 	u32 state[X2_NUM_RING_CONFIG];
102 	void __iomem *cmd_base;
103 	void __iomem *cmd;
104 	dma_addr_t dma;
105 	dma_addr_t irq_mbox_dma;
106 	void *irq_mbox_addr;
107 	u16 dst_ring_num;
108 	u16 nbufpool;
109 	int npagepool;
110 	u8 index;
111 	u32 flags;
112 	struct sk_buff *(*rx_skb);
113 	struct sk_buff *(*cp_skb);
114 	dma_addr_t *frag_dma_addr;
115 	struct page *(*frag_page);
116 	enum xgene_enet_ring_cfgsize cfgsize;
117 	struct xgene_enet_desc_ring *cp_ring;
118 	struct xgene_enet_desc_ring *buf_pool;
119 	struct xgene_enet_desc_ring *page_pool;
120 	struct napi_struct napi;
121 	union {
122 		void *desc_addr;
123 		struct xgene_enet_raw_desc *raw_desc;
124 		struct xgene_enet_raw_desc16 *raw_desc16;
125 	};
126 	__le64 *exp_bufs;
127 	u64 tx_packets;
128 	u64 tx_bytes;
129 	u64 tx_dropped;
130 	u64 tx_errors;
131 	u64 rx_packets;
132 	u64 rx_bytes;
133 	u64 rx_dropped;
134 	u64 rx_errors;
135 	u64 rx_length_errors;
136 	u64 rx_crc_errors;
137 	u64 rx_frame_errors;
138 	u64 rx_fifo_errors;
139 };
140 
141 struct xgene_mac_ops {
142 	void (*init)(struct xgene_enet_pdata *pdata);
143 	void (*reset)(struct xgene_enet_pdata *pdata);
144 	void (*tx_enable)(struct xgene_enet_pdata *pdata);
145 	void (*rx_enable)(struct xgene_enet_pdata *pdata);
146 	void (*tx_disable)(struct xgene_enet_pdata *pdata);
147 	void (*rx_disable)(struct xgene_enet_pdata *pdata);
148 	void (*get_drop_cnt)(struct xgene_enet_pdata *pdata, u32 *rx, u32 *tx);
149 	void (*set_speed)(struct xgene_enet_pdata *pdata);
150 	void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
151 	void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
152 	void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
153 	void (*link_state)(struct work_struct *work);
154 	void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable);
155 	void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable);
156 	void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable);
157 };
158 
159 struct xgene_port_ops {
160 	int (*reset)(struct xgene_enet_pdata *pdata);
161 	void (*clear)(struct xgene_enet_pdata *pdata,
162 		      struct xgene_enet_desc_ring *ring);
163 	void (*cle_bypass)(struct xgene_enet_pdata *pdata,
164 			   u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
165 	void (*shutdown)(struct xgene_enet_pdata *pdata);
166 };
167 
168 struct xgene_ring_ops {
169 	u8 num_ring_config;
170 	u8 num_ring_id_shift;
171 	struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
172 	void (*clear)(struct xgene_enet_desc_ring *);
173 	void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
174 	u32 (*len)(struct xgene_enet_desc_ring *);
175 	void (*coalesce)(struct xgene_enet_desc_ring *);
176 };
177 
178 struct xgene_cle_ops {
179 	int (*cle_init)(struct xgene_enet_pdata *pdata);
180 };
181 
182 /* ethernet private data */
183 struct xgene_enet_pdata {
184 	struct net_device *ndev;
185 	struct mii_bus *mdio_bus;
186 	int phy_speed;
187 	struct clk *clk;
188 	struct platform_device *pdev;
189 	enum xgene_enet_id enet_id;
190 	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
191 	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
192 	u16 tx_level[XGENE_NUM_TX_RING];
193 	u16 txc_level[XGENE_NUM_TX_RING];
194 	char *dev_name;
195 	u32 rx_buff_cnt;
196 	u32 tx_qcnt_hi;
197 	u32 irqs[XGENE_MAX_ENET_IRQ];
198 	u8 rxq_cnt;
199 	u8 txq_cnt;
200 	u8 cq_cnt;
201 	void __iomem *eth_csr_addr;
202 	void __iomem *eth_ring_if_addr;
203 	void __iomem *eth_diag_csr_addr;
204 	void __iomem *mcx_mac_addr;
205 	void __iomem *mcx_mac_csr_addr;
206 	void __iomem *mcx_stats_addr;
207 	void __iomem *base_addr;
208 	void __iomem *pcs_addr;
209 	void __iomem *ring_csr_addr;
210 	void __iomem *ring_cmd_addr;
211 	int phy_mode;
212 	enum xgene_enet_rm rm;
213 	struct xgene_enet_cle cle;
214 	u64 *extd_stats;
215 	u64 false_rflr;
216 	u64 vlan_rjbr;
217 	spinlock_t stats_lock; /* statistics lock */
218 	const struct xgene_mac_ops *mac_ops;
219 	spinlock_t mac_lock; /* mac lock */
220 	const struct xgene_port_ops *port_ops;
221 	struct xgene_ring_ops *ring_ops;
222 	const struct xgene_cle_ops *cle_ops;
223 	struct delayed_work link_work;
224 	u32 port_id;
225 	u8 cpu_bufnum;
226 	u8 eth_bufnum;
227 	u8 bp_bufnum;
228 	u16 ring_num;
229 	u32 mss[NUM_MSS_REG];
230 	u32 mss_refcnt[NUM_MSS_REG];
231 	spinlock_t mss_lock;  /* mss lock */
232 	u8 tx_delay;
233 	u8 rx_delay;
234 	bool mdio_driver;
235 	struct gpio_desc *sfp_rdy;
236 	bool sfp_gpio_en;
237 	u32 pause_autoneg;
238 	bool tx_pause;
239 	bool rx_pause;
240 };
241 
242 struct xgene_indirect_ctl {
243 	void __iomem *addr;
244 	void __iomem *ctl;
245 	void __iomem *cmd;
246 	void __iomem *cmd_done;
247 };
248 
ndev_to_dev(struct net_device * ndev)249 static inline struct device *ndev_to_dev(struct net_device *ndev)
250 {
251 	return ndev->dev.parent;
252 }
253 
xgene_enet_dst_ring_num(struct xgene_enet_desc_ring * ring)254 static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
255 {
256 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
257 
258 	return ((u16)pdata->rm << 10) | ring->num;
259 }
260 
261 void xgene_enet_set_ethtool_ops(struct net_device *netdev);
262 int xgene_extd_stats_init(struct xgene_enet_pdata *pdata);
263 
264 #endif /* __XGENE_ENET_MAIN_H__ */
265