1 /* Applied Micro X-Gene SoC Ethernet Driver
2  *
3  * Copyright (c) 2014, Applied Micro Circuits Corporation
4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
5  *	    Ravi Patel <rapatel@apm.com>
6  *	    Keyur Chudgar <kchudgar@apm.com>
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #ifndef __XGENE_ENET_MAIN_H__
23 #define __XGENE_ENET_MAIN_H__
24 
25 #include <linux/acpi.h>
26 #include <linux/clk.h>
27 #include <linux/efi.h>
28 #include <linux/irq.h>
29 #include <linux/io.h>
30 #include <linux/of_platform.h>
31 #include <linux/of_net.h>
32 #include <linux/of_mdio.h>
33 #include <linux/module.h>
34 #include <net/ip.h>
35 #include <linux/prefetch.h>
36 #include <linux/if_vlan.h>
37 #include <linux/phy.h>
38 #include "xgene_enet_hw.h"
39 #include "xgene_enet_cle.h"
40 #include "xgene_enet_ring2.h"
41 #include "../../../phy/mdio-xgene.h"
42 
43 #define XGENE_DRV_VERSION	"v1.0"
44 #define ETHER_MIN_PACKET	64
45 #define ETHER_STD_PACKET	1518
46 #define XGENE_ENET_STD_MTU	1536
47 #define XGENE_ENET_MAX_MTU	9600
48 #define SKB_BUFFER_SIZE		(XGENE_ENET_STD_MTU - NET_IP_ALIGN)
49 
50 #define BUFLEN_16K	(16 * 1024)
51 #define NUM_PKT_BUF	1024
52 #define NUM_BUFPOOL	32
53 #define NUM_NXTBUFPOOL	8
54 #define MAX_EXP_BUFFS	256
55 #define NUM_MSS_REG	4
56 #define XGENE_MIN_ENET_FRAME_SIZE	60
57 
58 #define XGENE_MAX_ENET_IRQ	16
59 #define XGENE_NUM_RX_RING	8
60 #define XGENE_NUM_TX_RING	8
61 #define XGENE_NUM_TXC_RING	8
62 
63 #define START_CPU_BUFNUM_0	0
64 #define START_ETH_BUFNUM_0	2
65 #define START_BP_BUFNUM_0	0x22
66 #define START_RING_NUM_0	8
67 #define START_CPU_BUFNUM_1	12
68 #define START_ETH_BUFNUM_1	10
69 #define START_BP_BUFNUM_1	0x2A
70 #define START_RING_NUM_1	264
71 
72 #define XG_START_CPU_BUFNUM_1	12
73 #define XG_START_ETH_BUFNUM_1	2
74 #define XG_START_BP_BUFNUM_1	0x22
75 #define XG_START_RING_NUM_1	264
76 
77 #define X2_START_CPU_BUFNUM_0	0
78 #define X2_START_ETH_BUFNUM_0	0
79 #define X2_START_BP_BUFNUM_0	0x20
80 #define X2_START_RING_NUM_0	0
81 #define X2_START_CPU_BUFNUM_1	0xc
82 #define X2_START_ETH_BUFNUM_1	0
83 #define X2_START_BP_BUFNUM_1	0x20
84 #define X2_START_RING_NUM_1	256
85 
86 #define IRQ_ID_SIZE		16
87 
88 #define PHY_POLL_LINK_ON	(10 * HZ)
89 #define PHY_POLL_LINK_OFF	(PHY_POLL_LINK_ON / 5)
90 
91 enum xgene_enet_id {
92 	XGENE_ENET1 = 1,
93 	XGENE_ENET2
94 };
95 
96 enum xgene_enet_buf_len {
97 	SIZE_2K = 2048,
98 	SIZE_4K = 4096,
99 	SIZE_16K = 16384
100 };
101 
102 /* software context of a descriptor ring */
103 struct xgene_enet_desc_ring {
104 	struct net_device *ndev;
105 	u16 id;
106 	u16 num;
107 	u16 head;
108 	u16 tail;
109 	u16 exp_buf_tail;
110 	u16 slots;
111 	u16 irq;
112 	char irq_name[IRQ_ID_SIZE];
113 	u32 size;
114 	u32 state[X2_NUM_RING_CONFIG];
115 	void __iomem *cmd_base;
116 	void __iomem *cmd;
117 	dma_addr_t dma;
118 	dma_addr_t irq_mbox_dma;
119 	void *irq_mbox_addr;
120 	u16 dst_ring_num;
121 	u16 nbufpool;
122 	int npagepool;
123 	u8 index;
124 	u32 flags;
125 	struct sk_buff *(*rx_skb);
126 	struct sk_buff *(*cp_skb);
127 	dma_addr_t *frag_dma_addr;
128 	struct page *(*frag_page);
129 	enum xgene_enet_ring_cfgsize cfgsize;
130 	struct xgene_enet_desc_ring *cp_ring;
131 	struct xgene_enet_desc_ring *buf_pool;
132 	struct xgene_enet_desc_ring *page_pool;
133 	struct napi_struct napi;
134 	union {
135 		void *desc_addr;
136 		struct xgene_enet_raw_desc *raw_desc;
137 		struct xgene_enet_raw_desc16 *raw_desc16;
138 	};
139 	__le64 *exp_bufs;
140 	u64 tx_packets;
141 	u64 tx_bytes;
142 	u64 tx_dropped;
143 	u64 tx_errors;
144 	u64 rx_packets;
145 	u64 rx_bytes;
146 	u64 rx_dropped;
147 	u64 rx_errors;
148 	u64 rx_length_errors;
149 	u64 rx_crc_errors;
150 	u64 rx_frame_errors;
151 	u64 rx_fifo_errors;
152 };
153 
154 struct xgene_mac_ops {
155 	void (*init)(struct xgene_enet_pdata *pdata);
156 	void (*reset)(struct xgene_enet_pdata *pdata);
157 	void (*tx_enable)(struct xgene_enet_pdata *pdata);
158 	void (*rx_enable)(struct xgene_enet_pdata *pdata);
159 	void (*tx_disable)(struct xgene_enet_pdata *pdata);
160 	void (*rx_disable)(struct xgene_enet_pdata *pdata);
161 	void (*get_drop_cnt)(struct xgene_enet_pdata *pdata, u32 *rx, u32 *tx);
162 	void (*set_speed)(struct xgene_enet_pdata *pdata);
163 	void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
164 	void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
165 	void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
166 	void (*link_state)(struct work_struct *work);
167 	void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable);
168 	void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable);
169 	void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable);
170 };
171 
172 struct xgene_port_ops {
173 	int (*reset)(struct xgene_enet_pdata *pdata);
174 	void (*clear)(struct xgene_enet_pdata *pdata,
175 		      struct xgene_enet_desc_ring *ring);
176 	void (*cle_bypass)(struct xgene_enet_pdata *pdata,
177 			   u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
178 	void (*shutdown)(struct xgene_enet_pdata *pdata);
179 };
180 
181 struct xgene_ring_ops {
182 	u8 num_ring_config;
183 	u8 num_ring_id_shift;
184 	struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
185 	void (*clear)(struct xgene_enet_desc_ring *);
186 	void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
187 	u32 (*len)(struct xgene_enet_desc_ring *);
188 	void (*coalesce)(struct xgene_enet_desc_ring *);
189 };
190 
191 struct xgene_cle_ops {
192 	int (*cle_init)(struct xgene_enet_pdata *pdata);
193 };
194 
195 /* ethernet private data */
196 struct xgene_enet_pdata {
197 	struct net_device *ndev;
198 	struct mii_bus *mdio_bus;
199 	int phy_speed;
200 	struct clk *clk;
201 	struct platform_device *pdev;
202 	enum xgene_enet_id enet_id;
203 	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
204 	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
205 	u16 tx_level[XGENE_NUM_TX_RING];
206 	u16 txc_level[XGENE_NUM_TX_RING];
207 	char *dev_name;
208 	u32 rx_buff_cnt;
209 	u32 tx_qcnt_hi;
210 	u32 irqs[XGENE_MAX_ENET_IRQ];
211 	u8 rxq_cnt;
212 	u8 txq_cnt;
213 	u8 cq_cnt;
214 	void __iomem *eth_csr_addr;
215 	void __iomem *eth_ring_if_addr;
216 	void __iomem *eth_diag_csr_addr;
217 	void __iomem *mcx_mac_addr;
218 	void __iomem *mcx_mac_csr_addr;
219 	void __iomem *mcx_stats_addr;
220 	void __iomem *base_addr;
221 	void __iomem *pcs_addr;
222 	void __iomem *ring_csr_addr;
223 	void __iomem *ring_cmd_addr;
224 	int phy_mode;
225 	enum xgene_enet_rm rm;
226 	struct xgene_enet_cle cle;
227 	u64 *extd_stats;
228 	u64 false_rflr;
229 	u64 vlan_rjbr;
230 	spinlock_t stats_lock; /* statistics lock */
231 	const struct xgene_mac_ops *mac_ops;
232 	spinlock_t mac_lock; /* mac lock */
233 	const struct xgene_port_ops *port_ops;
234 	struct xgene_ring_ops *ring_ops;
235 	const struct xgene_cle_ops *cle_ops;
236 	struct delayed_work link_work;
237 	u32 port_id;
238 	u8 cpu_bufnum;
239 	u8 eth_bufnum;
240 	u8 bp_bufnum;
241 	u16 ring_num;
242 	u32 mss[NUM_MSS_REG];
243 	u32 mss_refcnt[NUM_MSS_REG];
244 	spinlock_t mss_lock;  /* mss lock */
245 	u8 tx_delay;
246 	u8 rx_delay;
247 	bool mdio_driver;
248 	struct gpio_desc *sfp_rdy;
249 	bool sfp_gpio_en;
250 	u32 pause_autoneg;
251 	bool tx_pause;
252 	bool rx_pause;
253 };
254 
255 struct xgene_indirect_ctl {
256 	void __iomem *addr;
257 	void __iomem *ctl;
258 	void __iomem *cmd;
259 	void __iomem *cmd_done;
260 };
261 
262 static inline struct device *ndev_to_dev(struct net_device *ndev)
263 {
264 	return ndev->dev.parent;
265 }
266 
267 static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
268 {
269 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
270 
271 	return ((u16)pdata->rm << 10) | ring->num;
272 }
273 
274 void xgene_enet_set_ethtool_ops(struct net_device *netdev);
275 int xgene_extd_stats_init(struct xgene_enet_pdata *pdata);
276 
277 #endif /* __XGENE_ENET_MAIN_H__ */
278