1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Ravi Patel <rapatel@apm.com> 6 * Keyur Chudgar <kchudgar@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __XGENE_ENET_MAIN_H__ 23 #define __XGENE_ENET_MAIN_H__ 24 25 #include <linux/acpi.h> 26 #include <linux/clk.h> 27 #include <linux/efi.h> 28 #include <linux/irq.h> 29 #include <linux/io.h> 30 #include <linux/of_platform.h> 31 #include <linux/of_net.h> 32 #include <linux/of_mdio.h> 33 #include <linux/module.h> 34 #include <net/ip.h> 35 #include <linux/prefetch.h> 36 #include <linux/if_vlan.h> 37 #include <linux/phy.h> 38 #include "xgene_enet_hw.h" 39 #include "xgene_enet_cle.h" 40 #include "xgene_enet_ring2.h" 41 #include "../../../phy/mdio-xgene.h" 42 43 #define XGENE_DRV_VERSION "v1.0" 44 #define ETHER_MIN_PACKET 64 45 #define XGENE_ENET_STD_MTU 1536 46 #define XGENE_ENET_MAX_MTU 9600 47 #define SKB_BUFFER_SIZE (XGENE_ENET_STD_MTU - NET_IP_ALIGN) 48 49 #define BUFLEN_16K (16 * 1024) 50 #define NUM_PKT_BUF 1024 51 #define NUM_BUFPOOL 32 52 #define NUM_NXTBUFPOOL 8 53 #define MAX_EXP_BUFFS 256 54 #define NUM_MSS_REG 4 55 #define XGENE_MIN_ENET_FRAME_SIZE 60 56 57 #define XGENE_MAX_ENET_IRQ 16 58 #define XGENE_NUM_RX_RING 8 59 #define XGENE_NUM_TX_RING 8 60 #define XGENE_NUM_TXC_RING 8 61 62 #define START_CPU_BUFNUM_0 0 63 #define START_ETH_BUFNUM_0 2 64 #define START_BP_BUFNUM_0 0x22 65 #define START_RING_NUM_0 8 66 #define START_CPU_BUFNUM_1 12 67 #define START_ETH_BUFNUM_1 10 68 #define START_BP_BUFNUM_1 0x2A 69 #define START_RING_NUM_1 264 70 71 #define XG_START_CPU_BUFNUM_1 12 72 #define XG_START_ETH_BUFNUM_1 2 73 #define XG_START_BP_BUFNUM_1 0x22 74 #define XG_START_RING_NUM_1 264 75 76 #define X2_START_CPU_BUFNUM_0 0 77 #define X2_START_ETH_BUFNUM_0 0 78 #define X2_START_BP_BUFNUM_0 0x20 79 #define X2_START_RING_NUM_0 0 80 #define X2_START_CPU_BUFNUM_1 0xc 81 #define X2_START_ETH_BUFNUM_1 0 82 #define X2_START_BP_BUFNUM_1 0x20 83 #define X2_START_RING_NUM_1 256 84 85 #define IRQ_ID_SIZE 16 86 87 #define PHY_POLL_LINK_ON (10 * HZ) 88 #define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5) 89 90 enum xgene_enet_id { 91 XGENE_ENET1 = 1, 92 XGENE_ENET2 93 }; 94 95 enum xgene_enet_buf_len { 96 SIZE_2K = 2048, 97 SIZE_4K = 4096, 98 SIZE_16K = 16384 99 }; 100 101 /* software context of a descriptor ring */ 102 struct xgene_enet_desc_ring { 103 struct net_device *ndev; 104 u16 id; 105 u16 num; 106 u16 head; 107 u16 tail; 108 u16 exp_buf_tail; 109 u16 slots; 110 u16 irq; 111 char irq_name[IRQ_ID_SIZE]; 112 u32 size; 113 u32 state[X2_NUM_RING_CONFIG]; 114 void __iomem *cmd_base; 115 void __iomem *cmd; 116 dma_addr_t dma; 117 dma_addr_t irq_mbox_dma; 118 void *irq_mbox_addr; 119 u16 dst_ring_num; 120 u16 nbufpool; 121 int npagepool; 122 u8 index; 123 u32 flags; 124 struct sk_buff *(*rx_skb); 125 struct sk_buff *(*cp_skb); 126 dma_addr_t *frag_dma_addr; 127 struct page *(*frag_page); 128 enum xgene_enet_ring_cfgsize cfgsize; 129 struct xgene_enet_desc_ring *cp_ring; 130 struct xgene_enet_desc_ring *buf_pool; 131 struct xgene_enet_desc_ring *page_pool; 132 struct napi_struct napi; 133 union { 134 void *desc_addr; 135 struct xgene_enet_raw_desc *raw_desc; 136 struct xgene_enet_raw_desc16 *raw_desc16; 137 }; 138 __le64 *exp_bufs; 139 u64 tx_packets; 140 u64 tx_bytes; 141 u64 rx_packets; 142 u64 rx_bytes; 143 u64 rx_dropped; 144 u64 rx_errors; 145 u64 rx_length_errors; 146 u64 rx_crc_errors; 147 u64 rx_frame_errors; 148 u64 rx_fifo_errors; 149 }; 150 151 struct xgene_mac_ops { 152 void (*init)(struct xgene_enet_pdata *pdata); 153 void (*reset)(struct xgene_enet_pdata *pdata); 154 void (*tx_enable)(struct xgene_enet_pdata *pdata); 155 void (*rx_enable)(struct xgene_enet_pdata *pdata); 156 void (*tx_disable)(struct xgene_enet_pdata *pdata); 157 void (*rx_disable)(struct xgene_enet_pdata *pdata); 158 void (*set_speed)(struct xgene_enet_pdata *pdata); 159 void (*set_mac_addr)(struct xgene_enet_pdata *pdata); 160 void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize); 161 void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index); 162 void (*link_state)(struct work_struct *work); 163 void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable); 164 void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable); 165 void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable); 166 }; 167 168 struct xgene_port_ops { 169 int (*reset)(struct xgene_enet_pdata *pdata); 170 void (*clear)(struct xgene_enet_pdata *pdata, 171 struct xgene_enet_desc_ring *ring); 172 void (*cle_bypass)(struct xgene_enet_pdata *pdata, 173 u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id); 174 void (*shutdown)(struct xgene_enet_pdata *pdata); 175 }; 176 177 struct xgene_ring_ops { 178 u8 num_ring_config; 179 u8 num_ring_id_shift; 180 struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *); 181 void (*clear)(struct xgene_enet_desc_ring *); 182 void (*wr_cmd)(struct xgene_enet_desc_ring *, int); 183 u32 (*len)(struct xgene_enet_desc_ring *); 184 void (*coalesce)(struct xgene_enet_desc_ring *); 185 }; 186 187 struct xgene_cle_ops { 188 int (*cle_init)(struct xgene_enet_pdata *pdata); 189 }; 190 191 /* ethernet private data */ 192 struct xgene_enet_pdata { 193 struct net_device *ndev; 194 struct mii_bus *mdio_bus; 195 int phy_speed; 196 struct clk *clk; 197 struct platform_device *pdev; 198 enum xgene_enet_id enet_id; 199 struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING]; 200 struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING]; 201 u16 tx_level[XGENE_NUM_TX_RING]; 202 u16 txc_level[XGENE_NUM_TX_RING]; 203 char *dev_name; 204 u32 rx_buff_cnt; 205 u32 tx_qcnt_hi; 206 u32 irqs[XGENE_MAX_ENET_IRQ]; 207 u8 rxq_cnt; 208 u8 txq_cnt; 209 u8 cq_cnt; 210 void __iomem *eth_csr_addr; 211 void __iomem *eth_ring_if_addr; 212 void __iomem *eth_diag_csr_addr; 213 void __iomem *mcx_mac_addr; 214 void __iomem *mcx_mac_csr_addr; 215 void __iomem *base_addr; 216 void __iomem *pcs_addr; 217 void __iomem *ring_csr_addr; 218 void __iomem *ring_cmd_addr; 219 int phy_mode; 220 enum xgene_enet_rm rm; 221 struct xgene_enet_cle cle; 222 const struct xgene_mac_ops *mac_ops; 223 spinlock_t mac_lock; /* mac lock */ 224 const struct xgene_port_ops *port_ops; 225 struct xgene_ring_ops *ring_ops; 226 const struct xgene_cle_ops *cle_ops; 227 struct delayed_work link_work; 228 u32 port_id; 229 u8 cpu_bufnum; 230 u8 eth_bufnum; 231 u8 bp_bufnum; 232 u16 ring_num; 233 u32 mss[NUM_MSS_REG]; 234 u32 mss_refcnt[NUM_MSS_REG]; 235 spinlock_t mss_lock; /* mss lock */ 236 u8 tx_delay; 237 u8 rx_delay; 238 bool mdio_driver; 239 struct gpio_desc *sfp_rdy; 240 bool sfp_gpio_en; 241 u32 pause_autoneg; 242 bool tx_pause; 243 bool rx_pause; 244 }; 245 246 struct xgene_indirect_ctl { 247 void __iomem *addr; 248 void __iomem *ctl; 249 void __iomem *cmd; 250 void __iomem *cmd_done; 251 }; 252 253 static inline struct device *ndev_to_dev(struct net_device *ndev) 254 { 255 return ndev->dev.parent; 256 } 257 258 static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring) 259 { 260 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); 261 262 return ((u16)pdata->rm << 10) | ring->num; 263 } 264 265 void xgene_enet_set_ethtool_ops(struct net_device *netdev); 266 267 #endif /* __XGENE_ENET_MAIN_H__ */ 268