1 /* Altera Triple-Speed Ethernet MAC driver 2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 3 * 4 * Contributors: 5 * Dalon Westergreen 6 * Thomas Chou 7 * Ian Abbott 8 * Yuriy Kozlov 9 * Tobias Klauser 10 * Andriy Smolskyy 11 * Roman Bulgakov 12 * Dmytro Mytarchuk 13 * Matthew Gerlach 14 * 15 * Original driver contributed by SLS. 16 * Major updates contributed by GlobalLogic 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #include <linux/atomic.h> 32 #include <linux/delay.h> 33 #include <linux/etherdevice.h> 34 #include <linux/if_vlan.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/kernel.h> 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/of_device.h> 42 #include <linux/of_mdio.h> 43 #include <linux/of_net.h> 44 #include <linux/of_platform.h> 45 #include <linux/phy.h> 46 #include <linux/platform_device.h> 47 #include <linux/skbuff.h> 48 #include <asm/cacheflush.h> 49 50 #include "altera_utils.h" 51 #include "altera_tse.h" 52 #include "altera_sgdma.h" 53 #include "altera_msgdma.h" 54 55 static atomic_t instance_count = ATOMIC_INIT(~0); 56 /* Module parameters */ 57 static int debug = -1; 58 module_param(debug, int, S_IRUGO | S_IWUSR); 59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 60 61 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 62 NETIF_MSG_LINK | NETIF_MSG_IFUP | 63 NETIF_MSG_IFDOWN); 64 65 #define RX_DESCRIPTORS 64 66 static int dma_rx_num = RX_DESCRIPTORS; 67 module_param(dma_rx_num, int, S_IRUGO | S_IWUSR); 68 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list"); 69 70 #define TX_DESCRIPTORS 64 71 static int dma_tx_num = TX_DESCRIPTORS; 72 module_param(dma_tx_num, int, S_IRUGO | S_IWUSR); 73 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list"); 74 75 76 #define POLL_PHY (-1) 77 78 /* Make sure DMA buffer size is larger than the max frame size 79 * plus some alignment offset and a VLAN header. If the max frame size is 80 * 1518, a VLAN header would be additional 4 bytes and additional 81 * headroom for alignment is 2 bytes, 2048 is just fine. 82 */ 83 #define ALTERA_RXDMABUFFER_SIZE 2048 84 85 /* Allow network stack to resume queueing packets after we've 86 * finished transmitting at least 1/4 of the packets in the queue. 87 */ 88 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4) 89 90 #define TXQUEUESTOP_THRESHHOLD 2 91 92 static const struct of_device_id altera_tse_ids[]; 93 94 static inline u32 tse_tx_avail(struct altera_tse_private *priv) 95 { 96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1; 97 } 98 99 /* MDIO specific functions 100 */ 101 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 102 { 103 struct net_device *ndev = bus->priv; 104 struct altera_tse_private *priv = netdev_priv(ndev); 105 106 /* set MDIO address */ 107 csrwr32((mii_id & 0x1f), priv->mac_dev, 108 tse_csroffs(mdio_phy1_addr)); 109 110 /* get the data */ 111 return csrrd32(priv->mac_dev, 112 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff; 113 } 114 115 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 116 u16 value) 117 { 118 struct net_device *ndev = bus->priv; 119 struct altera_tse_private *priv = netdev_priv(ndev); 120 121 /* set MDIO address */ 122 csrwr32((mii_id & 0x1f), priv->mac_dev, 123 tse_csroffs(mdio_phy1_addr)); 124 125 /* write the data */ 126 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4); 127 return 0; 128 } 129 130 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id) 131 { 132 struct altera_tse_private *priv = netdev_priv(dev); 133 int ret; 134 struct device_node *mdio_node = NULL; 135 struct mii_bus *mdio = NULL; 136 struct device_node *child_node = NULL; 137 138 for_each_child_of_node(priv->device->of_node, child_node) { 139 if (of_device_is_compatible(child_node, "altr,tse-mdio")) { 140 mdio_node = child_node; 141 break; 142 } 143 } 144 145 if (mdio_node) { 146 netdev_dbg(dev, "FOUND MDIO subnode\n"); 147 } else { 148 netdev_dbg(dev, "NO MDIO subnode\n"); 149 return 0; 150 } 151 152 mdio = mdiobus_alloc(); 153 if (mdio == NULL) { 154 netdev_err(dev, "Error allocating MDIO bus\n"); 155 return -ENOMEM; 156 } 157 158 mdio->name = ALTERA_TSE_RESOURCE_NAME; 159 mdio->read = &altera_tse_mdio_read; 160 mdio->write = &altera_tse_mdio_write; 161 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id); 162 163 mdio->priv = dev; 164 mdio->parent = priv->device; 165 166 ret = of_mdiobus_register(mdio, mdio_node); 167 if (ret != 0) { 168 netdev_err(dev, "Cannot register MDIO bus %s\n", 169 mdio->id); 170 goto out_free_mdio; 171 } 172 173 if (netif_msg_drv(priv)) 174 netdev_info(dev, "MDIO bus %s: created\n", mdio->id); 175 176 priv->mdio = mdio; 177 return 0; 178 out_free_mdio: 179 mdiobus_free(mdio); 180 mdio = NULL; 181 return ret; 182 } 183 184 static void altera_tse_mdio_destroy(struct net_device *dev) 185 { 186 struct altera_tse_private *priv = netdev_priv(dev); 187 188 if (priv->mdio == NULL) 189 return; 190 191 if (netif_msg_drv(priv)) 192 netdev_info(dev, "MDIO bus %s: removed\n", 193 priv->mdio->id); 194 195 mdiobus_unregister(priv->mdio); 196 mdiobus_free(priv->mdio); 197 priv->mdio = NULL; 198 } 199 200 static int tse_init_rx_buffer(struct altera_tse_private *priv, 201 struct tse_buffer *rxbuffer, int len) 202 { 203 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len); 204 if (!rxbuffer->skb) 205 return -ENOMEM; 206 207 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data, 208 len, 209 DMA_FROM_DEVICE); 210 211 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) { 212 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 213 dev_kfree_skb_any(rxbuffer->skb); 214 return -EINVAL; 215 } 216 rxbuffer->dma_addr &= (dma_addr_t)~3; 217 rxbuffer->len = len; 218 return 0; 219 } 220 221 static void tse_free_rx_buffer(struct altera_tse_private *priv, 222 struct tse_buffer *rxbuffer) 223 { 224 struct sk_buff *skb = rxbuffer->skb; 225 dma_addr_t dma_addr = rxbuffer->dma_addr; 226 227 if (skb != NULL) { 228 if (dma_addr) 229 dma_unmap_single(priv->device, dma_addr, 230 rxbuffer->len, 231 DMA_FROM_DEVICE); 232 dev_kfree_skb_any(skb); 233 rxbuffer->skb = NULL; 234 rxbuffer->dma_addr = 0; 235 } 236 } 237 238 /* Unmap and free Tx buffer resources 239 */ 240 static void tse_free_tx_buffer(struct altera_tse_private *priv, 241 struct tse_buffer *buffer) 242 { 243 if (buffer->dma_addr) { 244 if (buffer->mapped_as_page) 245 dma_unmap_page(priv->device, buffer->dma_addr, 246 buffer->len, DMA_TO_DEVICE); 247 else 248 dma_unmap_single(priv->device, buffer->dma_addr, 249 buffer->len, DMA_TO_DEVICE); 250 buffer->dma_addr = 0; 251 } 252 if (buffer->skb) { 253 dev_kfree_skb_any(buffer->skb); 254 buffer->skb = NULL; 255 } 256 } 257 258 static int alloc_init_skbufs(struct altera_tse_private *priv) 259 { 260 unsigned int rx_descs = priv->rx_ring_size; 261 unsigned int tx_descs = priv->tx_ring_size; 262 int ret = -ENOMEM; 263 int i; 264 265 /* Create Rx ring buffer */ 266 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer), 267 GFP_KERNEL); 268 if (!priv->rx_ring) 269 goto err_rx_ring; 270 271 /* Create Tx ring buffer */ 272 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer), 273 GFP_KERNEL); 274 if (!priv->tx_ring) 275 goto err_tx_ring; 276 277 priv->tx_cons = 0; 278 priv->tx_prod = 0; 279 280 /* Init Rx ring */ 281 for (i = 0; i < rx_descs; i++) { 282 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i], 283 priv->rx_dma_buf_sz); 284 if (ret) 285 goto err_init_rx_buffers; 286 } 287 288 priv->rx_cons = 0; 289 priv->rx_prod = 0; 290 291 return 0; 292 err_init_rx_buffers: 293 while (--i >= 0) 294 tse_free_rx_buffer(priv, &priv->rx_ring[i]); 295 kfree(priv->tx_ring); 296 err_tx_ring: 297 kfree(priv->rx_ring); 298 err_rx_ring: 299 return ret; 300 } 301 302 static void free_skbufs(struct net_device *dev) 303 { 304 struct altera_tse_private *priv = netdev_priv(dev); 305 unsigned int rx_descs = priv->rx_ring_size; 306 unsigned int tx_descs = priv->tx_ring_size; 307 int i; 308 309 /* Release the DMA TX/RX socket buffers */ 310 for (i = 0; i < rx_descs; i++) 311 tse_free_rx_buffer(priv, &priv->rx_ring[i]); 312 for (i = 0; i < tx_descs; i++) 313 tse_free_tx_buffer(priv, &priv->tx_ring[i]); 314 315 316 kfree(priv->tx_ring); 317 } 318 319 /* Reallocate the skb for the reception process 320 */ 321 static inline void tse_rx_refill(struct altera_tse_private *priv) 322 { 323 unsigned int rxsize = priv->rx_ring_size; 324 unsigned int entry; 325 int ret; 326 327 for (; priv->rx_cons - priv->rx_prod > 0; 328 priv->rx_prod++) { 329 entry = priv->rx_prod % rxsize; 330 if (likely(priv->rx_ring[entry].skb == NULL)) { 331 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry], 332 priv->rx_dma_buf_sz); 333 if (unlikely(ret != 0)) 334 break; 335 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]); 336 } 337 } 338 } 339 340 /* Pull out the VLAN tag and fix up the packet 341 */ 342 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb) 343 { 344 struct ethhdr *eth_hdr; 345 u16 vid; 346 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 347 !__vlan_get_tag(skb, &vid)) { 348 eth_hdr = (struct ethhdr *)skb->data; 349 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2); 350 skb_pull(skb, VLAN_HLEN); 351 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 352 } 353 } 354 355 /* Receive a packet: retrieve and pass over to upper levels 356 */ 357 static int tse_rx(struct altera_tse_private *priv, int limit) 358 { 359 unsigned int count = 0; 360 unsigned int next_entry; 361 struct sk_buff *skb; 362 unsigned int entry = priv->rx_cons % priv->rx_ring_size; 363 u32 rxstatus; 364 u16 pktlength; 365 u16 pktstatus; 366 367 /* Check for count < limit first as get_rx_status is changing 368 * the response-fifo so we must process the next packet 369 * after calling get_rx_status if a response is pending. 370 * (reading the last byte of the response pops the value from the fifo.) 371 */ 372 while ((count < limit) && 373 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) { 374 pktstatus = rxstatus >> 16; 375 pktlength = rxstatus & 0xffff; 376 377 if ((pktstatus & 0xFF) || (pktlength == 0)) 378 netdev_err(priv->dev, 379 "RCV pktstatus %08X pktlength %08X\n", 380 pktstatus, pktlength); 381 382 /* DMA trasfer from TSE starts with 2 aditional bytes for 383 * IP payload alignment. Status returned by get_rx_status() 384 * contains DMA transfer length. Packet is 2 bytes shorter. 385 */ 386 pktlength -= 2; 387 388 count++; 389 next_entry = (++priv->rx_cons) % priv->rx_ring_size; 390 391 skb = priv->rx_ring[entry].skb; 392 if (unlikely(!skb)) { 393 netdev_err(priv->dev, 394 "%s: Inconsistent Rx descriptor chain\n", 395 __func__); 396 priv->dev->stats.rx_dropped++; 397 break; 398 } 399 priv->rx_ring[entry].skb = NULL; 400 401 skb_put(skb, pktlength); 402 403 /* make cache consistent with receive packet buffer */ 404 dma_sync_single_for_cpu(priv->device, 405 priv->rx_ring[entry].dma_addr, 406 priv->rx_ring[entry].len, 407 DMA_FROM_DEVICE); 408 409 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr, 410 priv->rx_ring[entry].len, DMA_FROM_DEVICE); 411 412 if (netif_msg_pktdata(priv)) { 413 netdev_info(priv->dev, "frame received %d bytes\n", 414 pktlength); 415 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET, 416 16, 1, skb->data, pktlength, true); 417 } 418 419 tse_rx_vlan(priv->dev, skb); 420 421 skb->protocol = eth_type_trans(skb, priv->dev); 422 skb_checksum_none_assert(skb); 423 424 napi_gro_receive(&priv->napi, skb); 425 426 priv->dev->stats.rx_packets++; 427 priv->dev->stats.rx_bytes += pktlength; 428 429 entry = next_entry; 430 431 tse_rx_refill(priv); 432 } 433 434 return count; 435 } 436 437 /* Reclaim resources after transmission completes 438 */ 439 static int tse_tx_complete(struct altera_tse_private *priv) 440 { 441 unsigned int txsize = priv->tx_ring_size; 442 u32 ready; 443 unsigned int entry; 444 struct tse_buffer *tx_buff; 445 int txcomplete = 0; 446 447 spin_lock(&priv->tx_lock); 448 449 ready = priv->dmaops->tx_completions(priv); 450 451 /* Free sent buffers */ 452 while (ready && (priv->tx_cons != priv->tx_prod)) { 453 entry = priv->tx_cons % txsize; 454 tx_buff = &priv->tx_ring[entry]; 455 456 if (netif_msg_tx_done(priv)) 457 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n", 458 __func__, priv->tx_prod, priv->tx_cons); 459 460 if (likely(tx_buff->skb)) 461 priv->dev->stats.tx_packets++; 462 463 tse_free_tx_buffer(priv, tx_buff); 464 priv->tx_cons++; 465 466 txcomplete++; 467 ready--; 468 } 469 470 if (unlikely(netif_queue_stopped(priv->dev) && 471 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) { 472 netif_tx_lock(priv->dev); 473 if (netif_queue_stopped(priv->dev) && 474 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) { 475 if (netif_msg_tx_done(priv)) 476 netdev_dbg(priv->dev, "%s: restart transmit\n", 477 __func__); 478 netif_wake_queue(priv->dev); 479 } 480 netif_tx_unlock(priv->dev); 481 } 482 483 spin_unlock(&priv->tx_lock); 484 return txcomplete; 485 } 486 487 /* NAPI polling function 488 */ 489 static int tse_poll(struct napi_struct *napi, int budget) 490 { 491 struct altera_tse_private *priv = 492 container_of(napi, struct altera_tse_private, napi); 493 int rxcomplete = 0; 494 unsigned long int flags; 495 496 tse_tx_complete(priv); 497 498 rxcomplete = tse_rx(priv, budget); 499 500 if (rxcomplete < budget) { 501 502 napi_complete(napi); 503 504 netdev_dbg(priv->dev, 505 "NAPI Complete, did %d packets with budget %d\n", 506 rxcomplete, budget); 507 508 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 509 priv->dmaops->enable_rxirq(priv); 510 priv->dmaops->enable_txirq(priv); 511 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 512 } 513 return rxcomplete; 514 } 515 516 /* DMA TX & RX FIFO interrupt routing 517 */ 518 static irqreturn_t altera_isr(int irq, void *dev_id) 519 { 520 struct net_device *dev = dev_id; 521 struct altera_tse_private *priv; 522 523 if (unlikely(!dev)) { 524 pr_err("%s: invalid dev pointer\n", __func__); 525 return IRQ_NONE; 526 } 527 priv = netdev_priv(dev); 528 529 spin_lock(&priv->rxdma_irq_lock); 530 /* reset IRQs */ 531 priv->dmaops->clear_rxirq(priv); 532 priv->dmaops->clear_txirq(priv); 533 spin_unlock(&priv->rxdma_irq_lock); 534 535 if (likely(napi_schedule_prep(&priv->napi))) { 536 spin_lock(&priv->rxdma_irq_lock); 537 priv->dmaops->disable_rxirq(priv); 538 priv->dmaops->disable_txirq(priv); 539 spin_unlock(&priv->rxdma_irq_lock); 540 __napi_schedule(&priv->napi); 541 } 542 543 544 return IRQ_HANDLED; 545 } 546 547 /* Transmit a packet (called by the kernel). Dispatches 548 * either the SGDMA method for transmitting or the 549 * MSGDMA method, assumes no scatter/gather support, 550 * implying an assumption that there's only one 551 * physically contiguous fragment starting at 552 * skb->data, for length of skb_headlen(skb). 553 */ 554 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev) 555 { 556 struct altera_tse_private *priv = netdev_priv(dev); 557 unsigned int txsize = priv->tx_ring_size; 558 unsigned int entry; 559 struct tse_buffer *buffer = NULL; 560 int nfrags = skb_shinfo(skb)->nr_frags; 561 unsigned int nopaged_len = skb_headlen(skb); 562 enum netdev_tx ret = NETDEV_TX_OK; 563 dma_addr_t dma_addr; 564 565 spin_lock_bh(&priv->tx_lock); 566 567 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) { 568 if (!netif_queue_stopped(dev)) { 569 netif_stop_queue(dev); 570 /* This is a hard error, log it. */ 571 netdev_err(priv->dev, 572 "%s: Tx list full when queue awake\n", 573 __func__); 574 } 575 ret = NETDEV_TX_BUSY; 576 goto out; 577 } 578 579 /* Map the first skb fragment */ 580 entry = priv->tx_prod % txsize; 581 buffer = &priv->tx_ring[entry]; 582 583 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len, 584 DMA_TO_DEVICE); 585 if (dma_mapping_error(priv->device, dma_addr)) { 586 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 587 ret = NETDEV_TX_OK; 588 goto out; 589 } 590 591 buffer->skb = skb; 592 buffer->dma_addr = dma_addr; 593 buffer->len = nopaged_len; 594 595 /* Push data out of the cache hierarchy into main memory */ 596 dma_sync_single_for_device(priv->device, buffer->dma_addr, 597 buffer->len, DMA_TO_DEVICE); 598 599 priv->dmaops->tx_buffer(priv, buffer); 600 601 skb_tx_timestamp(skb); 602 603 priv->tx_prod++; 604 dev->stats.tx_bytes += skb->len; 605 606 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) { 607 if (netif_msg_hw(priv)) 608 netdev_dbg(priv->dev, "%s: stop transmitted packets\n", 609 __func__); 610 netif_stop_queue(dev); 611 } 612 613 out: 614 spin_unlock_bh(&priv->tx_lock); 615 616 return ret; 617 } 618 619 /* Called every time the controller might need to be made 620 * aware of new link state. The PHY code conveys this 621 * information through variables in the phydev structure, and this 622 * function converts those variables into the appropriate 623 * register values, and can bring down the device if needed. 624 */ 625 static void altera_tse_adjust_link(struct net_device *dev) 626 { 627 struct altera_tse_private *priv = netdev_priv(dev); 628 struct phy_device *phydev = dev->phydev; 629 int new_state = 0; 630 631 /* only change config if there is a link */ 632 spin_lock(&priv->mac_cfg_lock); 633 if (phydev->link) { 634 /* Read old config */ 635 u32 cfg_reg = ioread32(&priv->mac_dev->command_config); 636 637 /* Check duplex */ 638 if (phydev->duplex != priv->oldduplex) { 639 new_state = 1; 640 if (!(phydev->duplex)) 641 cfg_reg |= MAC_CMDCFG_HD_ENA; 642 else 643 cfg_reg &= ~MAC_CMDCFG_HD_ENA; 644 645 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n", 646 dev->name, phydev->duplex); 647 648 priv->oldduplex = phydev->duplex; 649 } 650 651 /* Check speed */ 652 if (phydev->speed != priv->oldspeed) { 653 new_state = 1; 654 switch (phydev->speed) { 655 case 1000: 656 cfg_reg |= MAC_CMDCFG_ETH_SPEED; 657 cfg_reg &= ~MAC_CMDCFG_ENA_10; 658 break; 659 case 100: 660 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; 661 cfg_reg &= ~MAC_CMDCFG_ENA_10; 662 break; 663 case 10: 664 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; 665 cfg_reg |= MAC_CMDCFG_ENA_10; 666 break; 667 default: 668 if (netif_msg_link(priv)) 669 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n", 670 phydev->speed); 671 break; 672 } 673 priv->oldspeed = phydev->speed; 674 } 675 iowrite32(cfg_reg, &priv->mac_dev->command_config); 676 677 if (!priv->oldlink) { 678 new_state = 1; 679 priv->oldlink = 1; 680 } 681 } else if (priv->oldlink) { 682 new_state = 1; 683 priv->oldlink = 0; 684 priv->oldspeed = 0; 685 priv->oldduplex = -1; 686 } 687 688 if (new_state && netif_msg_link(priv)) 689 phy_print_status(phydev); 690 691 spin_unlock(&priv->mac_cfg_lock); 692 } 693 static struct phy_device *connect_local_phy(struct net_device *dev) 694 { 695 struct altera_tse_private *priv = netdev_priv(dev); 696 struct phy_device *phydev = NULL; 697 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 698 699 if (priv->phy_addr != POLL_PHY) { 700 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, 701 priv->mdio->id, priv->phy_addr); 702 703 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt); 704 705 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link, 706 priv->phy_iface); 707 if (IS_ERR(phydev)) 708 netdev_err(dev, "Could not attach to PHY\n"); 709 710 } else { 711 int ret; 712 phydev = phy_find_first(priv->mdio); 713 if (phydev == NULL) { 714 netdev_err(dev, "No PHY found\n"); 715 return phydev; 716 } 717 718 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link, 719 priv->phy_iface); 720 if (ret != 0) { 721 netdev_err(dev, "Could not attach to PHY\n"); 722 phydev = NULL; 723 } 724 } 725 return phydev; 726 } 727 728 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev) 729 { 730 struct altera_tse_private *priv = netdev_priv(dev); 731 struct device_node *np = priv->device->of_node; 732 int ret = 0; 733 734 priv->phy_iface = of_get_phy_mode(np); 735 736 /* Avoid get phy addr and create mdio if no phy is present */ 737 if (!priv->phy_iface) 738 return 0; 739 740 /* try to get PHY address from device tree, use PHY autodetection if 741 * no valid address is given 742 */ 743 744 if (of_property_read_u32(priv->device->of_node, "phy-addr", 745 &priv->phy_addr)) { 746 priv->phy_addr = POLL_PHY; 747 } 748 749 if (!((priv->phy_addr == POLL_PHY) || 750 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) { 751 netdev_err(dev, "invalid phy-addr specified %d\n", 752 priv->phy_addr); 753 return -ENODEV; 754 } 755 756 /* Create/attach to MDIO bus */ 757 ret = altera_tse_mdio_create(dev, 758 atomic_add_return(1, &instance_count)); 759 760 if (ret) 761 return -ENODEV; 762 763 return 0; 764 } 765 766 /* Initialize driver's PHY state, and attach to the PHY 767 */ 768 static int init_phy(struct net_device *dev) 769 { 770 struct altera_tse_private *priv = netdev_priv(dev); 771 struct phy_device *phydev; 772 struct device_node *phynode; 773 bool fixed_link = false; 774 int rc = 0; 775 776 /* Avoid init phy in case of no phy present */ 777 if (!priv->phy_iface) 778 return 0; 779 780 priv->oldlink = 0; 781 priv->oldspeed = 0; 782 priv->oldduplex = -1; 783 784 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0); 785 786 if (!phynode) { 787 /* check if a fixed-link is defined in device-tree */ 788 if (of_phy_is_fixed_link(priv->device->of_node)) { 789 rc = of_phy_register_fixed_link(priv->device->of_node); 790 if (rc < 0) { 791 netdev_err(dev, "cannot register fixed PHY\n"); 792 return rc; 793 } 794 795 /* In the case of a fixed PHY, the DT node associated 796 * to the PHY is the Ethernet MAC DT node. 797 */ 798 phynode = of_node_get(priv->device->of_node); 799 fixed_link = true; 800 801 netdev_dbg(dev, "fixed-link detected\n"); 802 phydev = of_phy_connect(dev, phynode, 803 &altera_tse_adjust_link, 804 0, priv->phy_iface); 805 } else { 806 netdev_dbg(dev, "no phy-handle found\n"); 807 if (!priv->mdio) { 808 netdev_err(dev, "No phy-handle nor local mdio specified\n"); 809 return -ENODEV; 810 } 811 phydev = connect_local_phy(dev); 812 } 813 } else { 814 netdev_dbg(dev, "phy-handle found\n"); 815 phydev = of_phy_connect(dev, phynode, 816 &altera_tse_adjust_link, 0, priv->phy_iface); 817 } 818 819 if (!phydev) { 820 netdev_err(dev, "Could not find the PHY\n"); 821 return -ENODEV; 822 } 823 824 /* Stop Advertising 1000BASE Capability if interface is not GMII 825 * Note: Checkpatch throws CHECKs for the camel case defines below, 826 * it's ok to ignore. 827 */ 828 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) || 829 (priv->phy_iface == PHY_INTERFACE_MODE_RMII)) 830 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 831 SUPPORTED_1000baseT_Full); 832 833 /* Broken HW is sometimes missing the pull-up resistor on the 834 * MDIO line, which results in reads to non-existent devices returning 835 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 836 * device as well. If a fixed-link is used the phy_id is always 0. 837 * Note: phydev->phy_id is the result of reading the UID PHY registers. 838 */ 839 if ((phydev->phy_id == 0) && !fixed_link) { 840 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id); 841 phy_disconnect(phydev); 842 return -ENODEV; 843 } 844 845 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n", 846 phydev->mdio.addr, phydev->phy_id, phydev->link); 847 848 return 0; 849 } 850 851 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr) 852 { 853 u32 msb; 854 u32 lsb; 855 856 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 857 lsb = ((addr[5] << 8) | addr[4]) & 0xffff; 858 859 /* Set primary MAC address */ 860 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0)); 861 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1)); 862 } 863 864 /* MAC software reset. 865 * When reset is triggered, the MAC function completes the current 866 * transmission or reception, and subsequently disables the transmit and 867 * receive logic, flushes the receive FIFO buffer, and resets the statistics 868 * counters. 869 */ 870 static int reset_mac(struct altera_tse_private *priv) 871 { 872 int counter; 873 u32 dat; 874 875 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 876 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); 877 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET; 878 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config)); 879 880 counter = 0; 881 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { 882 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config), 883 MAC_CMDCFG_SW_RESET)) 884 break; 885 udelay(1); 886 } 887 888 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { 889 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 890 dat &= ~MAC_CMDCFG_SW_RESET; 891 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config)); 892 return -1; 893 } 894 return 0; 895 } 896 897 /* Initialize MAC core registers 898 */ 899 static int init_mac(struct altera_tse_private *priv) 900 { 901 unsigned int cmd = 0; 902 u32 frm_length; 903 904 /* Setup Rx FIFO */ 905 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY, 906 priv->mac_dev, tse_csroffs(rx_section_empty)); 907 908 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev, 909 tse_csroffs(rx_section_full)); 910 911 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev, 912 tse_csroffs(rx_almost_empty)); 913 914 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev, 915 tse_csroffs(rx_almost_full)); 916 917 /* Setup Tx FIFO */ 918 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY, 919 priv->mac_dev, tse_csroffs(tx_section_empty)); 920 921 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev, 922 tse_csroffs(tx_section_full)); 923 924 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev, 925 tse_csroffs(tx_almost_empty)); 926 927 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev, 928 tse_csroffs(tx_almost_full)); 929 930 /* MAC Address Configuration */ 931 tse_update_mac_addr(priv, priv->dev->dev_addr); 932 933 /* MAC Function Configuration */ 934 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN; 935 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length)); 936 937 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev, 938 tse_csroffs(tx_ipg_length)); 939 940 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit 941 * start address 942 */ 943 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat), 944 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16); 945 946 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat), 947 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 | 948 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC); 949 950 /* Set the MAC options */ 951 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 952 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */ 953 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */ 954 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames 955 * with CRC errors 956 */ 957 cmd |= MAC_CMDCFG_CNTL_FRM_ENA; 958 cmd &= ~MAC_CMDCFG_TX_ENA; 959 cmd &= ~MAC_CMDCFG_RX_ENA; 960 961 /* Default speed and duplex setting, full/100 */ 962 cmd &= ~MAC_CMDCFG_HD_ENA; 963 cmd &= ~MAC_CMDCFG_ETH_SPEED; 964 cmd &= ~MAC_CMDCFG_ENA_10; 965 966 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config)); 967 968 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev, 969 tse_csroffs(pause_quanta)); 970 971 if (netif_msg_hw(priv)) 972 dev_dbg(priv->device, 973 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd); 974 975 return 0; 976 } 977 978 /* Start/stop MAC transmission logic 979 */ 980 static void tse_set_mac(struct altera_tse_private *priv, bool enable) 981 { 982 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 983 984 if (enable) 985 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA; 986 else 987 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); 988 989 csrwr32(value, priv->mac_dev, tse_csroffs(command_config)); 990 } 991 992 /* Change the MTU 993 */ 994 static int tse_change_mtu(struct net_device *dev, int new_mtu) 995 { 996 struct altera_tse_private *priv = netdev_priv(dev); 997 unsigned int max_mtu = priv->max_mtu; 998 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN; 999 1000 if (netif_running(dev)) { 1001 netdev_err(dev, "must be stopped to change its MTU\n"); 1002 return -EBUSY; 1003 } 1004 1005 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) { 1006 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu); 1007 return -EINVAL; 1008 } 1009 1010 dev->mtu = new_mtu; 1011 netdev_update_features(dev); 1012 1013 return 0; 1014 } 1015 1016 static void altera_tse_set_mcfilter(struct net_device *dev) 1017 { 1018 struct altera_tse_private *priv = netdev_priv(dev); 1019 int i; 1020 struct netdev_hw_addr *ha; 1021 1022 /* clear the hash filter */ 1023 for (i = 0; i < 64; i++) 1024 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4); 1025 1026 netdev_for_each_mc_addr(ha, dev) { 1027 unsigned int hash = 0; 1028 int mac_octet; 1029 1030 for (mac_octet = 5; mac_octet >= 0; mac_octet--) { 1031 unsigned char xor_bit = 0; 1032 unsigned char octet = ha->addr[mac_octet]; 1033 unsigned int bitshift; 1034 1035 for (bitshift = 0; bitshift < 8; bitshift++) 1036 xor_bit ^= ((octet >> bitshift) & 0x01); 1037 1038 hash = (hash << 1) | xor_bit; 1039 } 1040 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4); 1041 } 1042 } 1043 1044 1045 static void altera_tse_set_mcfilterall(struct net_device *dev) 1046 { 1047 struct altera_tse_private *priv = netdev_priv(dev); 1048 int i; 1049 1050 /* set the hash filter */ 1051 for (i = 0; i < 64; i++) 1052 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4); 1053 } 1054 1055 /* Set or clear the multicast filter for this adaptor 1056 */ 1057 static void tse_set_rx_mode_hashfilter(struct net_device *dev) 1058 { 1059 struct altera_tse_private *priv = netdev_priv(dev); 1060 1061 spin_lock(&priv->mac_cfg_lock); 1062 1063 if (dev->flags & IFF_PROMISC) 1064 tse_set_bit(priv->mac_dev, tse_csroffs(command_config), 1065 MAC_CMDCFG_PROMIS_EN); 1066 1067 if (dev->flags & IFF_ALLMULTI) 1068 altera_tse_set_mcfilterall(dev); 1069 else 1070 altera_tse_set_mcfilter(dev); 1071 1072 spin_unlock(&priv->mac_cfg_lock); 1073 } 1074 1075 /* Set or clear the multicast filter for this adaptor 1076 */ 1077 static void tse_set_rx_mode(struct net_device *dev) 1078 { 1079 struct altera_tse_private *priv = netdev_priv(dev); 1080 1081 spin_lock(&priv->mac_cfg_lock); 1082 1083 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) || 1084 !netdev_mc_empty(dev) || !netdev_uc_empty(dev)) 1085 tse_set_bit(priv->mac_dev, tse_csroffs(command_config), 1086 MAC_CMDCFG_PROMIS_EN); 1087 else 1088 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config), 1089 MAC_CMDCFG_PROMIS_EN); 1090 1091 spin_unlock(&priv->mac_cfg_lock); 1092 } 1093 1094 /* Open and initialize the interface 1095 */ 1096 static int tse_open(struct net_device *dev) 1097 { 1098 struct altera_tse_private *priv = netdev_priv(dev); 1099 int ret = 0; 1100 int i; 1101 unsigned long int flags; 1102 1103 /* Reset and configure TSE MAC and probe associated PHY */ 1104 ret = priv->dmaops->init_dma(priv); 1105 if (ret != 0) { 1106 netdev_err(dev, "Cannot initialize DMA\n"); 1107 goto phy_error; 1108 } 1109 1110 if (netif_msg_ifup(priv)) 1111 netdev_warn(dev, "device MAC address %pM\n", 1112 dev->dev_addr); 1113 1114 if ((priv->revision < 0xd00) || (priv->revision > 0xe00)) 1115 netdev_warn(dev, "TSE revision %x\n", priv->revision); 1116 1117 spin_lock(&priv->mac_cfg_lock); 1118 ret = reset_mac(priv); 1119 /* Note that reset_mac will fail if the clocks are gated by the PHY 1120 * due to the PHY being put into isolation or power down mode. 1121 * This is not an error if reset fails due to no clock. 1122 */ 1123 if (ret) 1124 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret); 1125 1126 ret = init_mac(priv); 1127 spin_unlock(&priv->mac_cfg_lock); 1128 if (ret) { 1129 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret); 1130 goto alloc_skbuf_error; 1131 } 1132 1133 priv->dmaops->reset_dma(priv); 1134 1135 /* Create and initialize the TX/RX descriptors chains. */ 1136 priv->rx_ring_size = dma_rx_num; 1137 priv->tx_ring_size = dma_tx_num; 1138 ret = alloc_init_skbufs(priv); 1139 if (ret) { 1140 netdev_err(dev, "DMA descriptors initialization failed\n"); 1141 goto alloc_skbuf_error; 1142 } 1143 1144 1145 /* Register RX interrupt */ 1146 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED, 1147 dev->name, dev); 1148 if (ret) { 1149 netdev_err(dev, "Unable to register RX interrupt %d\n", 1150 priv->rx_irq); 1151 goto init_error; 1152 } 1153 1154 /* Register TX interrupt */ 1155 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED, 1156 dev->name, dev); 1157 if (ret) { 1158 netdev_err(dev, "Unable to register TX interrupt %d\n", 1159 priv->tx_irq); 1160 goto tx_request_irq_error; 1161 } 1162 1163 /* Enable DMA interrupts */ 1164 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 1165 priv->dmaops->enable_rxirq(priv); 1166 priv->dmaops->enable_txirq(priv); 1167 1168 /* Setup RX descriptor chain */ 1169 for (i = 0; i < priv->rx_ring_size; i++) 1170 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]); 1171 1172 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 1173 1174 if (dev->phydev) 1175 phy_start(dev->phydev); 1176 1177 napi_enable(&priv->napi); 1178 netif_start_queue(dev); 1179 1180 priv->dmaops->start_rxdma(priv); 1181 1182 /* Start MAC Rx/Tx */ 1183 spin_lock(&priv->mac_cfg_lock); 1184 tse_set_mac(priv, true); 1185 spin_unlock(&priv->mac_cfg_lock); 1186 1187 return 0; 1188 1189 tx_request_irq_error: 1190 free_irq(priv->rx_irq, dev); 1191 init_error: 1192 free_skbufs(dev); 1193 alloc_skbuf_error: 1194 phy_error: 1195 return ret; 1196 } 1197 1198 /* Stop TSE MAC interface and put the device in an inactive state 1199 */ 1200 static int tse_shutdown(struct net_device *dev) 1201 { 1202 struct altera_tse_private *priv = netdev_priv(dev); 1203 int ret; 1204 unsigned long int flags; 1205 1206 /* Stop the PHY */ 1207 if (dev->phydev) 1208 phy_stop(dev->phydev); 1209 1210 netif_stop_queue(dev); 1211 napi_disable(&priv->napi); 1212 1213 /* Disable DMA interrupts */ 1214 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 1215 priv->dmaops->disable_rxirq(priv); 1216 priv->dmaops->disable_txirq(priv); 1217 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 1218 1219 /* Free the IRQ lines */ 1220 free_irq(priv->rx_irq, dev); 1221 free_irq(priv->tx_irq, dev); 1222 1223 /* disable and reset the MAC, empties fifo */ 1224 spin_lock(&priv->mac_cfg_lock); 1225 spin_lock(&priv->tx_lock); 1226 1227 ret = reset_mac(priv); 1228 /* Note that reset_mac will fail if the clocks are gated by the PHY 1229 * due to the PHY being put into isolation or power down mode. 1230 * This is not an error if reset fails due to no clock. 1231 */ 1232 if (ret) 1233 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret); 1234 priv->dmaops->reset_dma(priv); 1235 free_skbufs(dev); 1236 1237 spin_unlock(&priv->tx_lock); 1238 spin_unlock(&priv->mac_cfg_lock); 1239 1240 priv->dmaops->uninit_dma(priv); 1241 1242 return 0; 1243 } 1244 1245 static struct net_device_ops altera_tse_netdev_ops = { 1246 .ndo_open = tse_open, 1247 .ndo_stop = tse_shutdown, 1248 .ndo_start_xmit = tse_start_xmit, 1249 .ndo_set_mac_address = eth_mac_addr, 1250 .ndo_set_rx_mode = tse_set_rx_mode, 1251 .ndo_change_mtu = tse_change_mtu, 1252 .ndo_validate_addr = eth_validate_addr, 1253 }; 1254 1255 static int request_and_map(struct platform_device *pdev, const char *name, 1256 struct resource **res, void __iomem **ptr) 1257 { 1258 struct resource *region; 1259 struct device *device = &pdev->dev; 1260 1261 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 1262 if (*res == NULL) { 1263 dev_err(device, "resource %s not defined\n", name); 1264 return -ENODEV; 1265 } 1266 1267 region = devm_request_mem_region(device, (*res)->start, 1268 resource_size(*res), dev_name(device)); 1269 if (region == NULL) { 1270 dev_err(device, "unable to request %s\n", name); 1271 return -EBUSY; 1272 } 1273 1274 *ptr = devm_ioremap_nocache(device, region->start, 1275 resource_size(region)); 1276 if (*ptr == NULL) { 1277 dev_err(device, "ioremap_nocache of %s failed!", name); 1278 return -ENOMEM; 1279 } 1280 1281 return 0; 1282 } 1283 1284 /* Probe Altera TSE MAC device 1285 */ 1286 static int altera_tse_probe(struct platform_device *pdev) 1287 { 1288 struct net_device *ndev; 1289 int ret = -ENODEV; 1290 struct resource *control_port; 1291 struct resource *dma_res; 1292 struct altera_tse_private *priv; 1293 const unsigned char *macaddr; 1294 void __iomem *descmap; 1295 const struct of_device_id *of_id = NULL; 1296 1297 ndev = alloc_etherdev(sizeof(struct altera_tse_private)); 1298 if (!ndev) { 1299 dev_err(&pdev->dev, "Could not allocate network device\n"); 1300 return -ENODEV; 1301 } 1302 1303 SET_NETDEV_DEV(ndev, &pdev->dev); 1304 1305 priv = netdev_priv(ndev); 1306 priv->device = &pdev->dev; 1307 priv->dev = ndev; 1308 priv->msg_enable = netif_msg_init(debug, default_msg_level); 1309 1310 of_id = of_match_device(altera_tse_ids, &pdev->dev); 1311 1312 if (of_id) 1313 priv->dmaops = (struct altera_dmaops *)of_id->data; 1314 1315 1316 if (priv->dmaops && 1317 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) { 1318 /* Get the mapped address to the SGDMA descriptor memory */ 1319 ret = request_and_map(pdev, "s1", &dma_res, &descmap); 1320 if (ret) 1321 goto err_free_netdev; 1322 1323 /* Start of that memory is for transmit descriptors */ 1324 priv->tx_dma_desc = descmap; 1325 1326 /* First half is for tx descriptors, other half for tx */ 1327 priv->txdescmem = resource_size(dma_res)/2; 1328 1329 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start; 1330 1331 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap + 1332 priv->txdescmem)); 1333 priv->rxdescmem = resource_size(dma_res)/2; 1334 priv->rxdescmem_busaddr = dma_res->start; 1335 priv->rxdescmem_busaddr += priv->txdescmem; 1336 1337 if (upper_32_bits(priv->rxdescmem_busaddr)) { 1338 dev_dbg(priv->device, 1339 "SGDMA bus addresses greater than 32-bits\n"); 1340 goto err_free_netdev; 1341 } 1342 if (upper_32_bits(priv->txdescmem_busaddr)) { 1343 dev_dbg(priv->device, 1344 "SGDMA bus addresses greater than 32-bits\n"); 1345 goto err_free_netdev; 1346 } 1347 } else if (priv->dmaops && 1348 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) { 1349 ret = request_and_map(pdev, "rx_resp", &dma_res, 1350 &priv->rx_dma_resp); 1351 if (ret) 1352 goto err_free_netdev; 1353 1354 ret = request_and_map(pdev, "tx_desc", &dma_res, 1355 &priv->tx_dma_desc); 1356 if (ret) 1357 goto err_free_netdev; 1358 1359 priv->txdescmem = resource_size(dma_res); 1360 priv->txdescmem_busaddr = dma_res->start; 1361 1362 ret = request_and_map(pdev, "rx_desc", &dma_res, 1363 &priv->rx_dma_desc); 1364 if (ret) 1365 goto err_free_netdev; 1366 1367 priv->rxdescmem = resource_size(dma_res); 1368 priv->rxdescmem_busaddr = dma_res->start; 1369 1370 } else { 1371 goto err_free_netdev; 1372 } 1373 1374 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) 1375 dma_set_coherent_mask(priv->device, 1376 DMA_BIT_MASK(priv->dmaops->dmamask)); 1377 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) 1378 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32)); 1379 else 1380 goto err_free_netdev; 1381 1382 /* MAC address space */ 1383 ret = request_and_map(pdev, "control_port", &control_port, 1384 (void __iomem **)&priv->mac_dev); 1385 if (ret) 1386 goto err_free_netdev; 1387 1388 /* xSGDMA Rx Dispatcher address space */ 1389 ret = request_and_map(pdev, "rx_csr", &dma_res, 1390 &priv->rx_dma_csr); 1391 if (ret) 1392 goto err_free_netdev; 1393 1394 1395 /* xSGDMA Tx Dispatcher address space */ 1396 ret = request_and_map(pdev, "tx_csr", &dma_res, 1397 &priv->tx_dma_csr); 1398 if (ret) 1399 goto err_free_netdev; 1400 1401 1402 /* Rx IRQ */ 1403 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq"); 1404 if (priv->rx_irq == -ENXIO) { 1405 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n"); 1406 ret = -ENXIO; 1407 goto err_free_netdev; 1408 } 1409 1410 /* Tx IRQ */ 1411 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq"); 1412 if (priv->tx_irq == -ENXIO) { 1413 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n"); 1414 ret = -ENXIO; 1415 goto err_free_netdev; 1416 } 1417 1418 /* get FIFO depths from device tree */ 1419 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", 1420 &priv->rx_fifo_depth)) { 1421 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n"); 1422 ret = -ENXIO; 1423 goto err_free_netdev; 1424 } 1425 1426 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", 1427 &priv->tx_fifo_depth)) { 1428 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n"); 1429 ret = -ENXIO; 1430 goto err_free_netdev; 1431 } 1432 1433 /* get hash filter settings for this instance */ 1434 priv->hash_filter = 1435 of_property_read_bool(pdev->dev.of_node, 1436 "altr,has-hash-multicast-filter"); 1437 1438 /* Set hash filter to not set for now until the 1439 * multicast filter receive issue is debugged 1440 */ 1441 priv->hash_filter = 0; 1442 1443 /* get supplemental address settings for this instance */ 1444 priv->added_unicast = 1445 of_property_read_bool(pdev->dev.of_node, 1446 "altr,has-supplementary-unicast"); 1447 1448 /* Max MTU is 1500, ETH_DATA_LEN */ 1449 priv->max_mtu = ETH_DATA_LEN; 1450 1451 /* Get the max mtu from the device tree. Note that the 1452 * "max-frame-size" parameter is actually max mtu. Definition 1453 * in the ePAPR v1.1 spec and usage differ, so go with usage. 1454 */ 1455 of_property_read_u32(pdev->dev.of_node, "max-frame-size", 1456 &priv->max_mtu); 1457 1458 /* The DMA buffer size already accounts for an alignment bias 1459 * to avoid unaligned access exceptions for the NIOS processor, 1460 */ 1461 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE; 1462 1463 /* get default MAC address from device tree */ 1464 macaddr = of_get_mac_address(pdev->dev.of_node); 1465 if (macaddr) 1466 ether_addr_copy(ndev->dev_addr, macaddr); 1467 else 1468 eth_hw_addr_random(ndev); 1469 1470 /* get phy addr and create mdio */ 1471 ret = altera_tse_phy_get_addr_mdio_create(ndev); 1472 1473 if (ret) 1474 goto err_free_netdev; 1475 1476 /* initialize netdev */ 1477 ndev->mem_start = control_port->start; 1478 ndev->mem_end = control_port->end; 1479 ndev->netdev_ops = &altera_tse_netdev_ops; 1480 altera_tse_set_ethtool_ops(ndev); 1481 1482 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode; 1483 1484 if (priv->hash_filter) 1485 altera_tse_netdev_ops.ndo_set_rx_mode = 1486 tse_set_rx_mode_hashfilter; 1487 1488 /* Scatter/gather IO is not supported, 1489 * so it is turned off 1490 */ 1491 ndev->hw_features &= ~NETIF_F_SG; 1492 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 1493 1494 /* VLAN offloading of tagging, stripping and filtering is not 1495 * supported by hardware, but driver will accommodate the 1496 * extra 4-byte VLAN tag for processing by upper layers 1497 */ 1498 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1499 1500 /* setup NAPI interface */ 1501 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT); 1502 1503 spin_lock_init(&priv->mac_cfg_lock); 1504 spin_lock_init(&priv->tx_lock); 1505 spin_lock_init(&priv->rxdma_irq_lock); 1506 1507 netif_carrier_off(ndev); 1508 ret = register_netdev(ndev); 1509 if (ret) { 1510 dev_err(&pdev->dev, "failed to register TSE net device\n"); 1511 goto err_register_netdev; 1512 } 1513 1514 platform_set_drvdata(pdev, ndev); 1515 1516 priv->revision = ioread32(&priv->mac_dev->megacore_revision); 1517 1518 if (netif_msg_probe(priv)) 1519 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n", 1520 (priv->revision >> 8) & 0xff, 1521 priv->revision & 0xff, 1522 (unsigned long) control_port->start, priv->rx_irq, 1523 priv->tx_irq); 1524 1525 ret = init_phy(ndev); 1526 if (ret != 0) { 1527 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret); 1528 goto err_init_phy; 1529 } 1530 return 0; 1531 1532 err_init_phy: 1533 unregister_netdev(ndev); 1534 err_register_netdev: 1535 netif_napi_del(&priv->napi); 1536 altera_tse_mdio_destroy(ndev); 1537 err_free_netdev: 1538 free_netdev(ndev); 1539 return ret; 1540 } 1541 1542 /* Remove Altera TSE MAC device 1543 */ 1544 static int altera_tse_remove(struct platform_device *pdev) 1545 { 1546 struct net_device *ndev = platform_get_drvdata(pdev); 1547 1548 if (ndev->phydev) 1549 phy_disconnect(ndev->phydev); 1550 1551 platform_set_drvdata(pdev, NULL); 1552 altera_tse_mdio_destroy(ndev); 1553 unregister_netdev(ndev); 1554 free_netdev(ndev); 1555 1556 return 0; 1557 } 1558 1559 static const struct altera_dmaops altera_dtype_sgdma = { 1560 .altera_dtype = ALTERA_DTYPE_SGDMA, 1561 .dmamask = 32, 1562 .reset_dma = sgdma_reset, 1563 .enable_txirq = sgdma_enable_txirq, 1564 .enable_rxirq = sgdma_enable_rxirq, 1565 .disable_txirq = sgdma_disable_txirq, 1566 .disable_rxirq = sgdma_disable_rxirq, 1567 .clear_txirq = sgdma_clear_txirq, 1568 .clear_rxirq = sgdma_clear_rxirq, 1569 .tx_buffer = sgdma_tx_buffer, 1570 .tx_completions = sgdma_tx_completions, 1571 .add_rx_desc = sgdma_add_rx_desc, 1572 .get_rx_status = sgdma_rx_status, 1573 .init_dma = sgdma_initialize, 1574 .uninit_dma = sgdma_uninitialize, 1575 .start_rxdma = sgdma_start_rxdma, 1576 }; 1577 1578 static const struct altera_dmaops altera_dtype_msgdma = { 1579 .altera_dtype = ALTERA_DTYPE_MSGDMA, 1580 .dmamask = 64, 1581 .reset_dma = msgdma_reset, 1582 .enable_txirq = msgdma_enable_txirq, 1583 .enable_rxirq = msgdma_enable_rxirq, 1584 .disable_txirq = msgdma_disable_txirq, 1585 .disable_rxirq = msgdma_disable_rxirq, 1586 .clear_txirq = msgdma_clear_txirq, 1587 .clear_rxirq = msgdma_clear_rxirq, 1588 .tx_buffer = msgdma_tx_buffer, 1589 .tx_completions = msgdma_tx_completions, 1590 .add_rx_desc = msgdma_add_rx_desc, 1591 .get_rx_status = msgdma_rx_status, 1592 .init_dma = msgdma_initialize, 1593 .uninit_dma = msgdma_uninitialize, 1594 .start_rxdma = msgdma_start_rxdma, 1595 }; 1596 1597 static const struct of_device_id altera_tse_ids[] = { 1598 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, }, 1599 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, }, 1600 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, }, 1601 {}, 1602 }; 1603 MODULE_DEVICE_TABLE(of, altera_tse_ids); 1604 1605 static struct platform_driver altera_tse_driver = { 1606 .probe = altera_tse_probe, 1607 .remove = altera_tse_remove, 1608 .suspend = NULL, 1609 .resume = NULL, 1610 .driver = { 1611 .name = ALTERA_TSE_RESOURCE_NAME, 1612 .of_match_table = altera_tse_ids, 1613 }, 1614 }; 1615 1616 module_platform_driver(altera_tse_driver); 1617 1618 MODULE_AUTHOR("Altera Corporation"); 1619 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver"); 1620 MODULE_LICENSE("GPL v2"); 1621