1 /* Altera Triple-Speed Ethernet MAC driver 2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 3 * 4 * Contributors: 5 * Dalon Westergreen 6 * Thomas Chou 7 * Ian Abbott 8 * Yuriy Kozlov 9 * Tobias Klauser 10 * Andriy Smolskyy 11 * Roman Bulgakov 12 * Dmytro Mytarchuk 13 * Matthew Gerlach 14 * 15 * Original driver contributed by SLS. 16 * Major updates contributed by GlobalLogic 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #include <linux/atomic.h> 32 #include <linux/delay.h> 33 #include <linux/etherdevice.h> 34 #include <linux/if_vlan.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/kernel.h> 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/of_device.h> 42 #include <linux/of_mdio.h> 43 #include <linux/of_net.h> 44 #include <linux/of_platform.h> 45 #include <linux/phy.h> 46 #include <linux/platform_device.h> 47 #include <linux/skbuff.h> 48 #include <asm/cacheflush.h> 49 50 #include "altera_utils.h" 51 #include "altera_tse.h" 52 #include "altera_sgdma.h" 53 #include "altera_msgdma.h" 54 55 static atomic_t instance_count = ATOMIC_INIT(~0); 56 /* Module parameters */ 57 static int debug = -1; 58 module_param(debug, int, S_IRUGO | S_IWUSR); 59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 60 61 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 62 NETIF_MSG_LINK | NETIF_MSG_IFUP | 63 NETIF_MSG_IFDOWN); 64 65 #define RX_DESCRIPTORS 64 66 static int dma_rx_num = RX_DESCRIPTORS; 67 module_param(dma_rx_num, int, S_IRUGO | S_IWUSR); 68 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list"); 69 70 #define TX_DESCRIPTORS 64 71 static int dma_tx_num = TX_DESCRIPTORS; 72 module_param(dma_tx_num, int, S_IRUGO | S_IWUSR); 73 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list"); 74 75 76 #define POLL_PHY (-1) 77 78 /* Make sure DMA buffer size is larger than the max frame size 79 * plus some alignment offset and a VLAN header. If the max frame size is 80 * 1518, a VLAN header would be additional 4 bytes and additional 81 * headroom for alignment is 2 bytes, 2048 is just fine. 82 */ 83 #define ALTERA_RXDMABUFFER_SIZE 2048 84 85 /* Allow network stack to resume queueing packets after we've 86 * finished transmitting at least 1/4 of the packets in the queue. 87 */ 88 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4) 89 90 #define TXQUEUESTOP_THRESHHOLD 2 91 92 static const struct of_device_id altera_tse_ids[]; 93 94 static inline u32 tse_tx_avail(struct altera_tse_private *priv) 95 { 96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1; 97 } 98 99 /* MDIO specific functions 100 */ 101 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 102 { 103 struct net_device *ndev = bus->priv; 104 struct altera_tse_private *priv = netdev_priv(ndev); 105 106 /* set MDIO address */ 107 csrwr32((mii_id & 0x1f), priv->mac_dev, 108 tse_csroffs(mdio_phy1_addr)); 109 110 /* get the data */ 111 return csrrd32(priv->mac_dev, 112 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff; 113 } 114 115 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 116 u16 value) 117 { 118 struct net_device *ndev = bus->priv; 119 struct altera_tse_private *priv = netdev_priv(ndev); 120 121 /* set MDIO address */ 122 csrwr32((mii_id & 0x1f), priv->mac_dev, 123 tse_csroffs(mdio_phy1_addr)); 124 125 /* write the data */ 126 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4); 127 return 0; 128 } 129 130 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id) 131 { 132 struct altera_tse_private *priv = netdev_priv(dev); 133 int ret; 134 int i; 135 struct device_node *mdio_node = NULL; 136 struct mii_bus *mdio = NULL; 137 struct device_node *child_node = NULL; 138 139 for_each_child_of_node(priv->device->of_node, child_node) { 140 if (of_device_is_compatible(child_node, "altr,tse-mdio")) { 141 mdio_node = child_node; 142 break; 143 } 144 } 145 146 if (mdio_node) { 147 netdev_dbg(dev, "FOUND MDIO subnode\n"); 148 } else { 149 netdev_dbg(dev, "NO MDIO subnode\n"); 150 return 0; 151 } 152 153 mdio = mdiobus_alloc(); 154 if (mdio == NULL) { 155 netdev_err(dev, "Error allocating MDIO bus\n"); 156 return -ENOMEM; 157 } 158 159 mdio->name = ALTERA_TSE_RESOURCE_NAME; 160 mdio->read = &altera_tse_mdio_read; 161 mdio->write = &altera_tse_mdio_write; 162 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id); 163 164 mdio->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 165 if (mdio->irq == NULL) { 166 ret = -ENOMEM; 167 goto out_free_mdio; 168 } 169 for (i = 0; i < PHY_MAX_ADDR; i++) 170 mdio->irq[i] = PHY_POLL; 171 172 mdio->priv = dev; 173 mdio->parent = priv->device; 174 175 ret = of_mdiobus_register(mdio, mdio_node); 176 if (ret != 0) { 177 netdev_err(dev, "Cannot register MDIO bus %s\n", 178 mdio->id); 179 goto out_free_mdio_irq; 180 } 181 182 if (netif_msg_drv(priv)) 183 netdev_info(dev, "MDIO bus %s: created\n", mdio->id); 184 185 priv->mdio = mdio; 186 return 0; 187 out_free_mdio_irq: 188 kfree(mdio->irq); 189 out_free_mdio: 190 mdiobus_free(mdio); 191 mdio = NULL; 192 return ret; 193 } 194 195 static void altera_tse_mdio_destroy(struct net_device *dev) 196 { 197 struct altera_tse_private *priv = netdev_priv(dev); 198 199 if (priv->mdio == NULL) 200 return; 201 202 if (netif_msg_drv(priv)) 203 netdev_info(dev, "MDIO bus %s: removed\n", 204 priv->mdio->id); 205 206 mdiobus_unregister(priv->mdio); 207 kfree(priv->mdio->irq); 208 mdiobus_free(priv->mdio); 209 priv->mdio = NULL; 210 } 211 212 static int tse_init_rx_buffer(struct altera_tse_private *priv, 213 struct tse_buffer *rxbuffer, int len) 214 { 215 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len); 216 if (!rxbuffer->skb) 217 return -ENOMEM; 218 219 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data, 220 len, 221 DMA_FROM_DEVICE); 222 223 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) { 224 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 225 dev_kfree_skb_any(rxbuffer->skb); 226 return -EINVAL; 227 } 228 rxbuffer->dma_addr &= (dma_addr_t)~3; 229 rxbuffer->len = len; 230 return 0; 231 } 232 233 static void tse_free_rx_buffer(struct altera_tse_private *priv, 234 struct tse_buffer *rxbuffer) 235 { 236 struct sk_buff *skb = rxbuffer->skb; 237 dma_addr_t dma_addr = rxbuffer->dma_addr; 238 239 if (skb != NULL) { 240 if (dma_addr) 241 dma_unmap_single(priv->device, dma_addr, 242 rxbuffer->len, 243 DMA_FROM_DEVICE); 244 dev_kfree_skb_any(skb); 245 rxbuffer->skb = NULL; 246 rxbuffer->dma_addr = 0; 247 } 248 } 249 250 /* Unmap and free Tx buffer resources 251 */ 252 static void tse_free_tx_buffer(struct altera_tse_private *priv, 253 struct tse_buffer *buffer) 254 { 255 if (buffer->dma_addr) { 256 if (buffer->mapped_as_page) 257 dma_unmap_page(priv->device, buffer->dma_addr, 258 buffer->len, DMA_TO_DEVICE); 259 else 260 dma_unmap_single(priv->device, buffer->dma_addr, 261 buffer->len, DMA_TO_DEVICE); 262 buffer->dma_addr = 0; 263 } 264 if (buffer->skb) { 265 dev_kfree_skb_any(buffer->skb); 266 buffer->skb = NULL; 267 } 268 } 269 270 static int alloc_init_skbufs(struct altera_tse_private *priv) 271 { 272 unsigned int rx_descs = priv->rx_ring_size; 273 unsigned int tx_descs = priv->tx_ring_size; 274 int ret = -ENOMEM; 275 int i; 276 277 /* Create Rx ring buffer */ 278 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer), 279 GFP_KERNEL); 280 if (!priv->rx_ring) 281 goto err_rx_ring; 282 283 /* Create Tx ring buffer */ 284 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer), 285 GFP_KERNEL); 286 if (!priv->tx_ring) 287 goto err_tx_ring; 288 289 priv->tx_cons = 0; 290 priv->tx_prod = 0; 291 292 /* Init Rx ring */ 293 for (i = 0; i < rx_descs; i++) { 294 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i], 295 priv->rx_dma_buf_sz); 296 if (ret) 297 goto err_init_rx_buffers; 298 } 299 300 priv->rx_cons = 0; 301 priv->rx_prod = 0; 302 303 return 0; 304 err_init_rx_buffers: 305 while (--i >= 0) 306 tse_free_rx_buffer(priv, &priv->rx_ring[i]); 307 kfree(priv->tx_ring); 308 err_tx_ring: 309 kfree(priv->rx_ring); 310 err_rx_ring: 311 return ret; 312 } 313 314 static void free_skbufs(struct net_device *dev) 315 { 316 struct altera_tse_private *priv = netdev_priv(dev); 317 unsigned int rx_descs = priv->rx_ring_size; 318 unsigned int tx_descs = priv->tx_ring_size; 319 int i; 320 321 /* Release the DMA TX/RX socket buffers */ 322 for (i = 0; i < rx_descs; i++) 323 tse_free_rx_buffer(priv, &priv->rx_ring[i]); 324 for (i = 0; i < tx_descs; i++) 325 tse_free_tx_buffer(priv, &priv->tx_ring[i]); 326 327 328 kfree(priv->tx_ring); 329 } 330 331 /* Reallocate the skb for the reception process 332 */ 333 static inline void tse_rx_refill(struct altera_tse_private *priv) 334 { 335 unsigned int rxsize = priv->rx_ring_size; 336 unsigned int entry; 337 int ret; 338 339 for (; priv->rx_cons - priv->rx_prod > 0; 340 priv->rx_prod++) { 341 entry = priv->rx_prod % rxsize; 342 if (likely(priv->rx_ring[entry].skb == NULL)) { 343 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry], 344 priv->rx_dma_buf_sz); 345 if (unlikely(ret != 0)) 346 break; 347 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]); 348 } 349 } 350 } 351 352 /* Pull out the VLAN tag and fix up the packet 353 */ 354 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb) 355 { 356 struct ethhdr *eth_hdr; 357 u16 vid; 358 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 359 !__vlan_get_tag(skb, &vid)) { 360 eth_hdr = (struct ethhdr *)skb->data; 361 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2); 362 skb_pull(skb, VLAN_HLEN); 363 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 364 } 365 } 366 367 /* Receive a packet: retrieve and pass over to upper levels 368 */ 369 static int tse_rx(struct altera_tse_private *priv, int limit) 370 { 371 unsigned int count = 0; 372 unsigned int next_entry; 373 struct sk_buff *skb; 374 unsigned int entry = priv->rx_cons % priv->rx_ring_size; 375 u32 rxstatus; 376 u16 pktlength; 377 u16 pktstatus; 378 379 /* Check for count < limit first as get_rx_status is changing 380 * the response-fifo so we must process the next packet 381 * after calling get_rx_status if a response is pending. 382 * (reading the last byte of the response pops the value from the fifo.) 383 */ 384 while ((count < limit) && 385 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) { 386 pktstatus = rxstatus >> 16; 387 pktlength = rxstatus & 0xffff; 388 389 if ((pktstatus & 0xFF) || (pktlength == 0)) 390 netdev_err(priv->dev, 391 "RCV pktstatus %08X pktlength %08X\n", 392 pktstatus, pktlength); 393 394 count++; 395 next_entry = (++priv->rx_cons) % priv->rx_ring_size; 396 397 skb = priv->rx_ring[entry].skb; 398 if (unlikely(!skb)) { 399 netdev_err(priv->dev, 400 "%s: Inconsistent Rx descriptor chain\n", 401 __func__); 402 priv->dev->stats.rx_dropped++; 403 break; 404 } 405 priv->rx_ring[entry].skb = NULL; 406 407 skb_put(skb, pktlength); 408 409 /* make cache consistent with receive packet buffer */ 410 dma_sync_single_for_cpu(priv->device, 411 priv->rx_ring[entry].dma_addr, 412 priv->rx_ring[entry].len, 413 DMA_FROM_DEVICE); 414 415 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr, 416 priv->rx_ring[entry].len, DMA_FROM_DEVICE); 417 418 if (netif_msg_pktdata(priv)) { 419 netdev_info(priv->dev, "frame received %d bytes\n", 420 pktlength); 421 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET, 422 16, 1, skb->data, pktlength, true); 423 } 424 425 tse_rx_vlan(priv->dev, skb); 426 427 skb->protocol = eth_type_trans(skb, priv->dev); 428 skb_checksum_none_assert(skb); 429 430 napi_gro_receive(&priv->napi, skb); 431 432 priv->dev->stats.rx_packets++; 433 priv->dev->stats.rx_bytes += pktlength; 434 435 entry = next_entry; 436 437 tse_rx_refill(priv); 438 } 439 440 return count; 441 } 442 443 /* Reclaim resources after transmission completes 444 */ 445 static int tse_tx_complete(struct altera_tse_private *priv) 446 { 447 unsigned int txsize = priv->tx_ring_size; 448 u32 ready; 449 unsigned int entry; 450 struct tse_buffer *tx_buff; 451 int txcomplete = 0; 452 453 spin_lock(&priv->tx_lock); 454 455 ready = priv->dmaops->tx_completions(priv); 456 457 /* Free sent buffers */ 458 while (ready && (priv->tx_cons != priv->tx_prod)) { 459 entry = priv->tx_cons % txsize; 460 tx_buff = &priv->tx_ring[entry]; 461 462 if (netif_msg_tx_done(priv)) 463 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n", 464 __func__, priv->tx_prod, priv->tx_cons); 465 466 if (likely(tx_buff->skb)) 467 priv->dev->stats.tx_packets++; 468 469 tse_free_tx_buffer(priv, tx_buff); 470 priv->tx_cons++; 471 472 txcomplete++; 473 ready--; 474 } 475 476 if (unlikely(netif_queue_stopped(priv->dev) && 477 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) { 478 netif_tx_lock(priv->dev); 479 if (netif_queue_stopped(priv->dev) && 480 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) { 481 if (netif_msg_tx_done(priv)) 482 netdev_dbg(priv->dev, "%s: restart transmit\n", 483 __func__); 484 netif_wake_queue(priv->dev); 485 } 486 netif_tx_unlock(priv->dev); 487 } 488 489 spin_unlock(&priv->tx_lock); 490 return txcomplete; 491 } 492 493 /* NAPI polling function 494 */ 495 static int tse_poll(struct napi_struct *napi, int budget) 496 { 497 struct altera_tse_private *priv = 498 container_of(napi, struct altera_tse_private, napi); 499 int rxcomplete = 0; 500 unsigned long int flags; 501 502 tse_tx_complete(priv); 503 504 rxcomplete = tse_rx(priv, budget); 505 506 if (rxcomplete < budget) { 507 508 napi_gro_flush(napi, false); 509 __napi_complete(napi); 510 511 netdev_dbg(priv->dev, 512 "NAPI Complete, did %d packets with budget %d\n", 513 rxcomplete, budget); 514 515 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 516 priv->dmaops->enable_rxirq(priv); 517 priv->dmaops->enable_txirq(priv); 518 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 519 } 520 return rxcomplete; 521 } 522 523 /* DMA TX & RX FIFO interrupt routing 524 */ 525 static irqreturn_t altera_isr(int irq, void *dev_id) 526 { 527 struct net_device *dev = dev_id; 528 struct altera_tse_private *priv; 529 530 if (unlikely(!dev)) { 531 pr_err("%s: invalid dev pointer\n", __func__); 532 return IRQ_NONE; 533 } 534 priv = netdev_priv(dev); 535 536 spin_lock(&priv->rxdma_irq_lock); 537 /* reset IRQs */ 538 priv->dmaops->clear_rxirq(priv); 539 priv->dmaops->clear_txirq(priv); 540 spin_unlock(&priv->rxdma_irq_lock); 541 542 if (likely(napi_schedule_prep(&priv->napi))) { 543 spin_lock(&priv->rxdma_irq_lock); 544 priv->dmaops->disable_rxirq(priv); 545 priv->dmaops->disable_txirq(priv); 546 spin_unlock(&priv->rxdma_irq_lock); 547 __napi_schedule(&priv->napi); 548 } 549 550 551 return IRQ_HANDLED; 552 } 553 554 /* Transmit a packet (called by the kernel). Dispatches 555 * either the SGDMA method for transmitting or the 556 * MSGDMA method, assumes no scatter/gather support, 557 * implying an assumption that there's only one 558 * physically contiguous fragment starting at 559 * skb->data, for length of skb_headlen(skb). 560 */ 561 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev) 562 { 563 struct altera_tse_private *priv = netdev_priv(dev); 564 unsigned int txsize = priv->tx_ring_size; 565 unsigned int entry; 566 struct tse_buffer *buffer = NULL; 567 int nfrags = skb_shinfo(skb)->nr_frags; 568 unsigned int nopaged_len = skb_headlen(skb); 569 enum netdev_tx ret = NETDEV_TX_OK; 570 dma_addr_t dma_addr; 571 572 spin_lock_bh(&priv->tx_lock); 573 574 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) { 575 if (!netif_queue_stopped(dev)) { 576 netif_stop_queue(dev); 577 /* This is a hard error, log it. */ 578 netdev_err(priv->dev, 579 "%s: Tx list full when queue awake\n", 580 __func__); 581 } 582 ret = NETDEV_TX_BUSY; 583 goto out; 584 } 585 586 /* Map the first skb fragment */ 587 entry = priv->tx_prod % txsize; 588 buffer = &priv->tx_ring[entry]; 589 590 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len, 591 DMA_TO_DEVICE); 592 if (dma_mapping_error(priv->device, dma_addr)) { 593 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 594 ret = NETDEV_TX_OK; 595 goto out; 596 } 597 598 buffer->skb = skb; 599 buffer->dma_addr = dma_addr; 600 buffer->len = nopaged_len; 601 602 /* Push data out of the cache hierarchy into main memory */ 603 dma_sync_single_for_device(priv->device, buffer->dma_addr, 604 buffer->len, DMA_TO_DEVICE); 605 606 priv->dmaops->tx_buffer(priv, buffer); 607 608 skb_tx_timestamp(skb); 609 610 priv->tx_prod++; 611 dev->stats.tx_bytes += skb->len; 612 613 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) { 614 if (netif_msg_hw(priv)) 615 netdev_dbg(priv->dev, "%s: stop transmitted packets\n", 616 __func__); 617 netif_stop_queue(dev); 618 } 619 620 out: 621 spin_unlock_bh(&priv->tx_lock); 622 623 return ret; 624 } 625 626 /* Called every time the controller might need to be made 627 * aware of new link state. The PHY code conveys this 628 * information through variables in the phydev structure, and this 629 * function converts those variables into the appropriate 630 * register values, and can bring down the device if needed. 631 */ 632 static void altera_tse_adjust_link(struct net_device *dev) 633 { 634 struct altera_tse_private *priv = netdev_priv(dev); 635 struct phy_device *phydev = priv->phydev; 636 int new_state = 0; 637 638 /* only change config if there is a link */ 639 spin_lock(&priv->mac_cfg_lock); 640 if (phydev->link) { 641 /* Read old config */ 642 u32 cfg_reg = ioread32(&priv->mac_dev->command_config); 643 644 /* Check duplex */ 645 if (phydev->duplex != priv->oldduplex) { 646 new_state = 1; 647 if (!(phydev->duplex)) 648 cfg_reg |= MAC_CMDCFG_HD_ENA; 649 else 650 cfg_reg &= ~MAC_CMDCFG_HD_ENA; 651 652 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n", 653 dev->name, phydev->duplex); 654 655 priv->oldduplex = phydev->duplex; 656 } 657 658 /* Check speed */ 659 if (phydev->speed != priv->oldspeed) { 660 new_state = 1; 661 switch (phydev->speed) { 662 case 1000: 663 cfg_reg |= MAC_CMDCFG_ETH_SPEED; 664 cfg_reg &= ~MAC_CMDCFG_ENA_10; 665 break; 666 case 100: 667 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; 668 cfg_reg &= ~MAC_CMDCFG_ENA_10; 669 break; 670 case 10: 671 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; 672 cfg_reg |= MAC_CMDCFG_ENA_10; 673 break; 674 default: 675 if (netif_msg_link(priv)) 676 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n", 677 phydev->speed); 678 break; 679 } 680 priv->oldspeed = phydev->speed; 681 } 682 iowrite32(cfg_reg, &priv->mac_dev->command_config); 683 684 if (!priv->oldlink) { 685 new_state = 1; 686 priv->oldlink = 1; 687 } 688 } else if (priv->oldlink) { 689 new_state = 1; 690 priv->oldlink = 0; 691 priv->oldspeed = 0; 692 priv->oldduplex = -1; 693 } 694 695 if (new_state && netif_msg_link(priv)) 696 phy_print_status(phydev); 697 698 spin_unlock(&priv->mac_cfg_lock); 699 } 700 static struct phy_device *connect_local_phy(struct net_device *dev) 701 { 702 struct altera_tse_private *priv = netdev_priv(dev); 703 struct phy_device *phydev = NULL; 704 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 705 706 if (priv->phy_addr != POLL_PHY) { 707 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, 708 priv->mdio->id, priv->phy_addr); 709 710 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt); 711 712 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link, 713 priv->phy_iface); 714 if (IS_ERR(phydev)) 715 netdev_err(dev, "Could not attach to PHY\n"); 716 717 } else { 718 int ret; 719 phydev = phy_find_first(priv->mdio); 720 if (phydev == NULL) { 721 netdev_err(dev, "No PHY found\n"); 722 return phydev; 723 } 724 725 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link, 726 priv->phy_iface); 727 if (ret != 0) { 728 netdev_err(dev, "Could not attach to PHY\n"); 729 phydev = NULL; 730 } 731 } 732 return phydev; 733 } 734 735 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev) 736 { 737 struct altera_tse_private *priv = netdev_priv(dev); 738 struct device_node *np = priv->device->of_node; 739 int ret = 0; 740 741 priv->phy_iface = of_get_phy_mode(np); 742 743 /* Avoid get phy addr and create mdio if no phy is present */ 744 if (!priv->phy_iface) 745 return 0; 746 747 /* try to get PHY address from device tree, use PHY autodetection if 748 * no valid address is given 749 */ 750 751 if (of_property_read_u32(priv->device->of_node, "phy-addr", 752 &priv->phy_addr)) { 753 priv->phy_addr = POLL_PHY; 754 } 755 756 if (!((priv->phy_addr == POLL_PHY) || 757 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) { 758 netdev_err(dev, "invalid phy-addr specified %d\n", 759 priv->phy_addr); 760 return -ENODEV; 761 } 762 763 /* Create/attach to MDIO bus */ 764 ret = altera_tse_mdio_create(dev, 765 atomic_add_return(1, &instance_count)); 766 767 if (ret) 768 return -ENODEV; 769 770 return 0; 771 } 772 773 /* Initialize driver's PHY state, and attach to the PHY 774 */ 775 static int init_phy(struct net_device *dev) 776 { 777 struct altera_tse_private *priv = netdev_priv(dev); 778 struct phy_device *phydev; 779 struct device_node *phynode; 780 781 /* Avoid init phy in case of no phy present */ 782 if (!priv->phy_iface) 783 return 0; 784 785 priv->oldlink = 0; 786 priv->oldspeed = 0; 787 priv->oldduplex = -1; 788 789 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0); 790 791 if (!phynode) { 792 netdev_dbg(dev, "no phy-handle found\n"); 793 if (!priv->mdio) { 794 netdev_err(dev, 795 "No phy-handle nor local mdio specified\n"); 796 return -ENODEV; 797 } 798 phydev = connect_local_phy(dev); 799 } else { 800 netdev_dbg(dev, "phy-handle found\n"); 801 phydev = of_phy_connect(dev, phynode, 802 &altera_tse_adjust_link, 0, priv->phy_iface); 803 } 804 805 if (!phydev) { 806 netdev_err(dev, "Could not find the PHY\n"); 807 return -ENODEV; 808 } 809 810 /* Stop Advertising 1000BASE Capability if interface is not GMII 811 * Note: Checkpatch throws CHECKs for the camel case defines below, 812 * it's ok to ignore. 813 */ 814 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) || 815 (priv->phy_iface == PHY_INTERFACE_MODE_RMII)) 816 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 817 SUPPORTED_1000baseT_Full); 818 819 /* Broken HW is sometimes missing the pull-up resistor on the 820 * MDIO line, which results in reads to non-existent devices returning 821 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 822 * device as well. 823 * Note: phydev->phy_id is the result of reading the UID PHY registers. 824 */ 825 if (phydev->phy_id == 0) { 826 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id); 827 phy_disconnect(phydev); 828 return -ENODEV; 829 } 830 831 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n", 832 phydev->addr, phydev->phy_id, phydev->link); 833 834 priv->phydev = phydev; 835 return 0; 836 } 837 838 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr) 839 { 840 u32 msb; 841 u32 lsb; 842 843 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 844 lsb = ((addr[5] << 8) | addr[4]) & 0xffff; 845 846 /* Set primary MAC address */ 847 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0)); 848 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1)); 849 } 850 851 /* MAC software reset. 852 * When reset is triggered, the MAC function completes the current 853 * transmission or reception, and subsequently disables the transmit and 854 * receive logic, flushes the receive FIFO buffer, and resets the statistics 855 * counters. 856 */ 857 static int reset_mac(struct altera_tse_private *priv) 858 { 859 int counter; 860 u32 dat; 861 862 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 863 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); 864 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET; 865 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config)); 866 867 counter = 0; 868 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { 869 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config), 870 MAC_CMDCFG_SW_RESET)) 871 break; 872 udelay(1); 873 } 874 875 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { 876 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 877 dat &= ~MAC_CMDCFG_SW_RESET; 878 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config)); 879 return -1; 880 } 881 return 0; 882 } 883 884 /* Initialize MAC core registers 885 */ 886 static int init_mac(struct altera_tse_private *priv) 887 { 888 unsigned int cmd = 0; 889 u32 frm_length; 890 891 /* Setup Rx FIFO */ 892 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY, 893 priv->mac_dev, tse_csroffs(rx_section_empty)); 894 895 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev, 896 tse_csroffs(rx_section_full)); 897 898 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev, 899 tse_csroffs(rx_almost_empty)); 900 901 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev, 902 tse_csroffs(rx_almost_full)); 903 904 /* Setup Tx FIFO */ 905 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY, 906 priv->mac_dev, tse_csroffs(tx_section_empty)); 907 908 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev, 909 tse_csroffs(tx_section_full)); 910 911 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev, 912 tse_csroffs(tx_almost_empty)); 913 914 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev, 915 tse_csroffs(tx_almost_full)); 916 917 /* MAC Address Configuration */ 918 tse_update_mac_addr(priv, priv->dev->dev_addr); 919 920 /* MAC Function Configuration */ 921 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN; 922 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length)); 923 924 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev, 925 tse_csroffs(tx_ipg_length)); 926 927 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit 928 * start address 929 */ 930 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat), 931 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16); 932 933 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat), 934 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 | 935 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC); 936 937 /* Set the MAC options */ 938 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 939 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */ 940 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */ 941 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames 942 * with CRC errors 943 */ 944 cmd |= MAC_CMDCFG_CNTL_FRM_ENA; 945 cmd &= ~MAC_CMDCFG_TX_ENA; 946 cmd &= ~MAC_CMDCFG_RX_ENA; 947 948 /* Default speed and duplex setting, full/100 */ 949 cmd &= ~MAC_CMDCFG_HD_ENA; 950 cmd &= ~MAC_CMDCFG_ETH_SPEED; 951 cmd &= ~MAC_CMDCFG_ENA_10; 952 953 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config)); 954 955 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev, 956 tse_csroffs(pause_quanta)); 957 958 if (netif_msg_hw(priv)) 959 dev_dbg(priv->device, 960 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd); 961 962 return 0; 963 } 964 965 /* Start/stop MAC transmission logic 966 */ 967 static void tse_set_mac(struct altera_tse_private *priv, bool enable) 968 { 969 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 970 971 if (enable) 972 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA; 973 else 974 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); 975 976 csrwr32(value, priv->mac_dev, tse_csroffs(command_config)); 977 } 978 979 /* Change the MTU 980 */ 981 static int tse_change_mtu(struct net_device *dev, int new_mtu) 982 { 983 struct altera_tse_private *priv = netdev_priv(dev); 984 unsigned int max_mtu = priv->max_mtu; 985 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN; 986 987 if (netif_running(dev)) { 988 netdev_err(dev, "must be stopped to change its MTU\n"); 989 return -EBUSY; 990 } 991 992 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) { 993 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu); 994 return -EINVAL; 995 } 996 997 dev->mtu = new_mtu; 998 netdev_update_features(dev); 999 1000 return 0; 1001 } 1002 1003 static void altera_tse_set_mcfilter(struct net_device *dev) 1004 { 1005 struct altera_tse_private *priv = netdev_priv(dev); 1006 int i; 1007 struct netdev_hw_addr *ha; 1008 1009 /* clear the hash filter */ 1010 for (i = 0; i < 64; i++) 1011 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4); 1012 1013 netdev_for_each_mc_addr(ha, dev) { 1014 unsigned int hash = 0; 1015 int mac_octet; 1016 1017 for (mac_octet = 5; mac_octet >= 0; mac_octet--) { 1018 unsigned char xor_bit = 0; 1019 unsigned char octet = ha->addr[mac_octet]; 1020 unsigned int bitshift; 1021 1022 for (bitshift = 0; bitshift < 8; bitshift++) 1023 xor_bit ^= ((octet >> bitshift) & 0x01); 1024 1025 hash = (hash << 1) | xor_bit; 1026 } 1027 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4); 1028 } 1029 } 1030 1031 1032 static void altera_tse_set_mcfilterall(struct net_device *dev) 1033 { 1034 struct altera_tse_private *priv = netdev_priv(dev); 1035 int i; 1036 1037 /* set the hash filter */ 1038 for (i = 0; i < 64; i++) 1039 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4); 1040 } 1041 1042 /* Set or clear the multicast filter for this adaptor 1043 */ 1044 static void tse_set_rx_mode_hashfilter(struct net_device *dev) 1045 { 1046 struct altera_tse_private *priv = netdev_priv(dev); 1047 1048 spin_lock(&priv->mac_cfg_lock); 1049 1050 if (dev->flags & IFF_PROMISC) 1051 tse_set_bit(priv->mac_dev, tse_csroffs(command_config), 1052 MAC_CMDCFG_PROMIS_EN); 1053 1054 if (dev->flags & IFF_ALLMULTI) 1055 altera_tse_set_mcfilterall(dev); 1056 else 1057 altera_tse_set_mcfilter(dev); 1058 1059 spin_unlock(&priv->mac_cfg_lock); 1060 } 1061 1062 /* Set or clear the multicast filter for this adaptor 1063 */ 1064 static void tse_set_rx_mode(struct net_device *dev) 1065 { 1066 struct altera_tse_private *priv = netdev_priv(dev); 1067 1068 spin_lock(&priv->mac_cfg_lock); 1069 1070 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) || 1071 !netdev_mc_empty(dev) || !netdev_uc_empty(dev)) 1072 tse_set_bit(priv->mac_dev, tse_csroffs(command_config), 1073 MAC_CMDCFG_PROMIS_EN); 1074 else 1075 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config), 1076 MAC_CMDCFG_PROMIS_EN); 1077 1078 spin_unlock(&priv->mac_cfg_lock); 1079 } 1080 1081 /* Open and initialize the interface 1082 */ 1083 static int tse_open(struct net_device *dev) 1084 { 1085 struct altera_tse_private *priv = netdev_priv(dev); 1086 int ret = 0; 1087 int i; 1088 unsigned long int flags; 1089 1090 /* Reset and configure TSE MAC and probe associated PHY */ 1091 ret = priv->dmaops->init_dma(priv); 1092 if (ret != 0) { 1093 netdev_err(dev, "Cannot initialize DMA\n"); 1094 goto phy_error; 1095 } 1096 1097 if (netif_msg_ifup(priv)) 1098 netdev_warn(dev, "device MAC address %pM\n", 1099 dev->dev_addr); 1100 1101 if ((priv->revision < 0xd00) || (priv->revision > 0xe00)) 1102 netdev_warn(dev, "TSE revision %x\n", priv->revision); 1103 1104 spin_lock(&priv->mac_cfg_lock); 1105 ret = reset_mac(priv); 1106 /* Note that reset_mac will fail if the clocks are gated by the PHY 1107 * due to the PHY being put into isolation or power down mode. 1108 * This is not an error if reset fails due to no clock. 1109 */ 1110 if (ret) 1111 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret); 1112 1113 ret = init_mac(priv); 1114 spin_unlock(&priv->mac_cfg_lock); 1115 if (ret) { 1116 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret); 1117 goto alloc_skbuf_error; 1118 } 1119 1120 priv->dmaops->reset_dma(priv); 1121 1122 /* Create and initialize the TX/RX descriptors chains. */ 1123 priv->rx_ring_size = dma_rx_num; 1124 priv->tx_ring_size = dma_tx_num; 1125 ret = alloc_init_skbufs(priv); 1126 if (ret) { 1127 netdev_err(dev, "DMA descriptors initialization failed\n"); 1128 goto alloc_skbuf_error; 1129 } 1130 1131 1132 /* Register RX interrupt */ 1133 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED, 1134 dev->name, dev); 1135 if (ret) { 1136 netdev_err(dev, "Unable to register RX interrupt %d\n", 1137 priv->rx_irq); 1138 goto init_error; 1139 } 1140 1141 /* Register TX interrupt */ 1142 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED, 1143 dev->name, dev); 1144 if (ret) { 1145 netdev_err(dev, "Unable to register TX interrupt %d\n", 1146 priv->tx_irq); 1147 goto tx_request_irq_error; 1148 } 1149 1150 /* Enable DMA interrupts */ 1151 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 1152 priv->dmaops->enable_rxirq(priv); 1153 priv->dmaops->enable_txirq(priv); 1154 1155 /* Setup RX descriptor chain */ 1156 for (i = 0; i < priv->rx_ring_size; i++) 1157 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]); 1158 1159 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 1160 1161 if (priv->phydev) 1162 phy_start(priv->phydev); 1163 1164 napi_enable(&priv->napi); 1165 netif_start_queue(dev); 1166 1167 priv->dmaops->start_rxdma(priv); 1168 1169 /* Start MAC Rx/Tx */ 1170 spin_lock(&priv->mac_cfg_lock); 1171 tse_set_mac(priv, true); 1172 spin_unlock(&priv->mac_cfg_lock); 1173 1174 return 0; 1175 1176 tx_request_irq_error: 1177 free_irq(priv->rx_irq, dev); 1178 init_error: 1179 free_skbufs(dev); 1180 alloc_skbuf_error: 1181 phy_error: 1182 return ret; 1183 } 1184 1185 /* Stop TSE MAC interface and put the device in an inactive state 1186 */ 1187 static int tse_shutdown(struct net_device *dev) 1188 { 1189 struct altera_tse_private *priv = netdev_priv(dev); 1190 int ret; 1191 unsigned long int flags; 1192 1193 /* Stop the PHY */ 1194 if (priv->phydev) 1195 phy_stop(priv->phydev); 1196 1197 netif_stop_queue(dev); 1198 napi_disable(&priv->napi); 1199 1200 /* Disable DMA interrupts */ 1201 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 1202 priv->dmaops->disable_rxirq(priv); 1203 priv->dmaops->disable_txirq(priv); 1204 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 1205 1206 /* Free the IRQ lines */ 1207 free_irq(priv->rx_irq, dev); 1208 free_irq(priv->tx_irq, dev); 1209 1210 /* disable and reset the MAC, empties fifo */ 1211 spin_lock(&priv->mac_cfg_lock); 1212 spin_lock(&priv->tx_lock); 1213 1214 ret = reset_mac(priv); 1215 /* Note that reset_mac will fail if the clocks are gated by the PHY 1216 * due to the PHY being put into isolation or power down mode. 1217 * This is not an error if reset fails due to no clock. 1218 */ 1219 if (ret) 1220 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret); 1221 priv->dmaops->reset_dma(priv); 1222 free_skbufs(dev); 1223 1224 spin_unlock(&priv->tx_lock); 1225 spin_unlock(&priv->mac_cfg_lock); 1226 1227 priv->dmaops->uninit_dma(priv); 1228 1229 return 0; 1230 } 1231 1232 static struct net_device_ops altera_tse_netdev_ops = { 1233 .ndo_open = tse_open, 1234 .ndo_stop = tse_shutdown, 1235 .ndo_start_xmit = tse_start_xmit, 1236 .ndo_set_mac_address = eth_mac_addr, 1237 .ndo_set_rx_mode = tse_set_rx_mode, 1238 .ndo_change_mtu = tse_change_mtu, 1239 .ndo_validate_addr = eth_validate_addr, 1240 }; 1241 1242 static int request_and_map(struct platform_device *pdev, const char *name, 1243 struct resource **res, void __iomem **ptr) 1244 { 1245 struct resource *region; 1246 struct device *device = &pdev->dev; 1247 1248 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 1249 if (*res == NULL) { 1250 dev_err(device, "resource %s not defined\n", name); 1251 return -ENODEV; 1252 } 1253 1254 region = devm_request_mem_region(device, (*res)->start, 1255 resource_size(*res), dev_name(device)); 1256 if (region == NULL) { 1257 dev_err(device, "unable to request %s\n", name); 1258 return -EBUSY; 1259 } 1260 1261 *ptr = devm_ioremap_nocache(device, region->start, 1262 resource_size(region)); 1263 if (*ptr == NULL) { 1264 dev_err(device, "ioremap_nocache of %s failed!", name); 1265 return -ENOMEM; 1266 } 1267 1268 return 0; 1269 } 1270 1271 /* Probe Altera TSE MAC device 1272 */ 1273 static int altera_tse_probe(struct platform_device *pdev) 1274 { 1275 struct net_device *ndev; 1276 int ret = -ENODEV; 1277 struct resource *control_port; 1278 struct resource *dma_res; 1279 struct altera_tse_private *priv; 1280 const unsigned char *macaddr; 1281 void __iomem *descmap; 1282 const struct of_device_id *of_id = NULL; 1283 1284 ndev = alloc_etherdev(sizeof(struct altera_tse_private)); 1285 if (!ndev) { 1286 dev_err(&pdev->dev, "Could not allocate network device\n"); 1287 return -ENODEV; 1288 } 1289 1290 SET_NETDEV_DEV(ndev, &pdev->dev); 1291 1292 priv = netdev_priv(ndev); 1293 priv->device = &pdev->dev; 1294 priv->dev = ndev; 1295 priv->msg_enable = netif_msg_init(debug, default_msg_level); 1296 1297 of_id = of_match_device(altera_tse_ids, &pdev->dev); 1298 1299 if (of_id) 1300 priv->dmaops = (struct altera_dmaops *)of_id->data; 1301 1302 1303 if (priv->dmaops && 1304 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) { 1305 /* Get the mapped address to the SGDMA descriptor memory */ 1306 ret = request_and_map(pdev, "s1", &dma_res, &descmap); 1307 if (ret) 1308 goto err_free_netdev; 1309 1310 /* Start of that memory is for transmit descriptors */ 1311 priv->tx_dma_desc = descmap; 1312 1313 /* First half is for tx descriptors, other half for tx */ 1314 priv->txdescmem = resource_size(dma_res)/2; 1315 1316 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start; 1317 1318 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap + 1319 priv->txdescmem)); 1320 priv->rxdescmem = resource_size(dma_res)/2; 1321 priv->rxdescmem_busaddr = dma_res->start; 1322 priv->rxdescmem_busaddr += priv->txdescmem; 1323 1324 if (upper_32_bits(priv->rxdescmem_busaddr)) { 1325 dev_dbg(priv->device, 1326 "SGDMA bus addresses greater than 32-bits\n"); 1327 goto err_free_netdev; 1328 } 1329 if (upper_32_bits(priv->txdescmem_busaddr)) { 1330 dev_dbg(priv->device, 1331 "SGDMA bus addresses greater than 32-bits\n"); 1332 goto err_free_netdev; 1333 } 1334 } else if (priv->dmaops && 1335 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) { 1336 ret = request_and_map(pdev, "rx_resp", &dma_res, 1337 &priv->rx_dma_resp); 1338 if (ret) 1339 goto err_free_netdev; 1340 1341 ret = request_and_map(pdev, "tx_desc", &dma_res, 1342 &priv->tx_dma_desc); 1343 if (ret) 1344 goto err_free_netdev; 1345 1346 priv->txdescmem = resource_size(dma_res); 1347 priv->txdescmem_busaddr = dma_res->start; 1348 1349 ret = request_and_map(pdev, "rx_desc", &dma_res, 1350 &priv->rx_dma_desc); 1351 if (ret) 1352 goto err_free_netdev; 1353 1354 priv->rxdescmem = resource_size(dma_res); 1355 priv->rxdescmem_busaddr = dma_res->start; 1356 1357 } else { 1358 goto err_free_netdev; 1359 } 1360 1361 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) 1362 dma_set_coherent_mask(priv->device, 1363 DMA_BIT_MASK(priv->dmaops->dmamask)); 1364 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) 1365 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32)); 1366 else 1367 goto err_free_netdev; 1368 1369 /* MAC address space */ 1370 ret = request_and_map(pdev, "control_port", &control_port, 1371 (void __iomem **)&priv->mac_dev); 1372 if (ret) 1373 goto err_free_netdev; 1374 1375 /* xSGDMA Rx Dispatcher address space */ 1376 ret = request_and_map(pdev, "rx_csr", &dma_res, 1377 &priv->rx_dma_csr); 1378 if (ret) 1379 goto err_free_netdev; 1380 1381 1382 /* xSGDMA Tx Dispatcher address space */ 1383 ret = request_and_map(pdev, "tx_csr", &dma_res, 1384 &priv->tx_dma_csr); 1385 if (ret) 1386 goto err_free_netdev; 1387 1388 1389 /* Rx IRQ */ 1390 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq"); 1391 if (priv->rx_irq == -ENXIO) { 1392 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n"); 1393 ret = -ENXIO; 1394 goto err_free_netdev; 1395 } 1396 1397 /* Tx IRQ */ 1398 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq"); 1399 if (priv->tx_irq == -ENXIO) { 1400 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n"); 1401 ret = -ENXIO; 1402 goto err_free_netdev; 1403 } 1404 1405 /* get FIFO depths from device tree */ 1406 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", 1407 &priv->rx_fifo_depth)) { 1408 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n"); 1409 ret = -ENXIO; 1410 goto err_free_netdev; 1411 } 1412 1413 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", 1414 &priv->tx_fifo_depth)) { 1415 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n"); 1416 ret = -ENXIO; 1417 goto err_free_netdev; 1418 } 1419 1420 /* get hash filter settings for this instance */ 1421 priv->hash_filter = 1422 of_property_read_bool(pdev->dev.of_node, 1423 "altr,has-hash-multicast-filter"); 1424 1425 /* Set hash filter to not set for now until the 1426 * multicast filter receive issue is debugged 1427 */ 1428 priv->hash_filter = 0; 1429 1430 /* get supplemental address settings for this instance */ 1431 priv->added_unicast = 1432 of_property_read_bool(pdev->dev.of_node, 1433 "altr,has-supplementary-unicast"); 1434 1435 /* Max MTU is 1500, ETH_DATA_LEN */ 1436 priv->max_mtu = ETH_DATA_LEN; 1437 1438 /* Get the max mtu from the device tree. Note that the 1439 * "max-frame-size" parameter is actually max mtu. Definition 1440 * in the ePAPR v1.1 spec and usage differ, so go with usage. 1441 */ 1442 of_property_read_u32(pdev->dev.of_node, "max-frame-size", 1443 &priv->max_mtu); 1444 1445 /* The DMA buffer size already accounts for an alignment bias 1446 * to avoid unaligned access exceptions for the NIOS processor, 1447 */ 1448 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE; 1449 1450 /* get default MAC address from device tree */ 1451 macaddr = of_get_mac_address(pdev->dev.of_node); 1452 if (macaddr) 1453 ether_addr_copy(ndev->dev_addr, macaddr); 1454 else 1455 eth_hw_addr_random(ndev); 1456 1457 /* get phy addr and create mdio */ 1458 ret = altera_tse_phy_get_addr_mdio_create(ndev); 1459 1460 if (ret) 1461 goto err_free_netdev; 1462 1463 /* initialize netdev */ 1464 ndev->mem_start = control_port->start; 1465 ndev->mem_end = control_port->end; 1466 ndev->netdev_ops = &altera_tse_netdev_ops; 1467 altera_tse_set_ethtool_ops(ndev); 1468 1469 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode; 1470 1471 if (priv->hash_filter) 1472 altera_tse_netdev_ops.ndo_set_rx_mode = 1473 tse_set_rx_mode_hashfilter; 1474 1475 /* Scatter/gather IO is not supported, 1476 * so it is turned off 1477 */ 1478 ndev->hw_features &= ~NETIF_F_SG; 1479 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 1480 1481 /* VLAN offloading of tagging, stripping and filtering is not 1482 * supported by hardware, but driver will accommodate the 1483 * extra 4-byte VLAN tag for processing by upper layers 1484 */ 1485 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1486 1487 /* setup NAPI interface */ 1488 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT); 1489 1490 spin_lock_init(&priv->mac_cfg_lock); 1491 spin_lock_init(&priv->tx_lock); 1492 spin_lock_init(&priv->rxdma_irq_lock); 1493 1494 ret = register_netdev(ndev); 1495 if (ret) { 1496 dev_err(&pdev->dev, "failed to register TSE net device\n"); 1497 goto err_register_netdev; 1498 } 1499 1500 platform_set_drvdata(pdev, ndev); 1501 1502 priv->revision = ioread32(&priv->mac_dev->megacore_revision); 1503 1504 if (netif_msg_probe(priv)) 1505 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n", 1506 (priv->revision >> 8) & 0xff, 1507 priv->revision & 0xff, 1508 (unsigned long) control_port->start, priv->rx_irq, 1509 priv->tx_irq); 1510 1511 ret = init_phy(ndev); 1512 if (ret != 0) { 1513 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret); 1514 goto err_init_phy; 1515 } 1516 return 0; 1517 1518 err_init_phy: 1519 unregister_netdev(ndev); 1520 err_register_netdev: 1521 netif_napi_del(&priv->napi); 1522 altera_tse_mdio_destroy(ndev); 1523 err_free_netdev: 1524 free_netdev(ndev); 1525 return ret; 1526 } 1527 1528 /* Remove Altera TSE MAC device 1529 */ 1530 static int altera_tse_remove(struct platform_device *pdev) 1531 { 1532 struct net_device *ndev = platform_get_drvdata(pdev); 1533 struct altera_tse_private *priv = netdev_priv(ndev); 1534 1535 if (priv->phydev) 1536 phy_disconnect(priv->phydev); 1537 1538 platform_set_drvdata(pdev, NULL); 1539 altera_tse_mdio_destroy(ndev); 1540 unregister_netdev(ndev); 1541 free_netdev(ndev); 1542 1543 return 0; 1544 } 1545 1546 static const struct altera_dmaops altera_dtype_sgdma = { 1547 .altera_dtype = ALTERA_DTYPE_SGDMA, 1548 .dmamask = 32, 1549 .reset_dma = sgdma_reset, 1550 .enable_txirq = sgdma_enable_txirq, 1551 .enable_rxirq = sgdma_enable_rxirq, 1552 .disable_txirq = sgdma_disable_txirq, 1553 .disable_rxirq = sgdma_disable_rxirq, 1554 .clear_txirq = sgdma_clear_txirq, 1555 .clear_rxirq = sgdma_clear_rxirq, 1556 .tx_buffer = sgdma_tx_buffer, 1557 .tx_completions = sgdma_tx_completions, 1558 .add_rx_desc = sgdma_add_rx_desc, 1559 .get_rx_status = sgdma_rx_status, 1560 .init_dma = sgdma_initialize, 1561 .uninit_dma = sgdma_uninitialize, 1562 .start_rxdma = sgdma_start_rxdma, 1563 }; 1564 1565 static const struct altera_dmaops altera_dtype_msgdma = { 1566 .altera_dtype = ALTERA_DTYPE_MSGDMA, 1567 .dmamask = 64, 1568 .reset_dma = msgdma_reset, 1569 .enable_txirq = msgdma_enable_txirq, 1570 .enable_rxirq = msgdma_enable_rxirq, 1571 .disable_txirq = msgdma_disable_txirq, 1572 .disable_rxirq = msgdma_disable_rxirq, 1573 .clear_txirq = msgdma_clear_txirq, 1574 .clear_rxirq = msgdma_clear_rxirq, 1575 .tx_buffer = msgdma_tx_buffer, 1576 .tx_completions = msgdma_tx_completions, 1577 .add_rx_desc = msgdma_add_rx_desc, 1578 .get_rx_status = msgdma_rx_status, 1579 .init_dma = msgdma_initialize, 1580 .uninit_dma = msgdma_uninitialize, 1581 .start_rxdma = msgdma_start_rxdma, 1582 }; 1583 1584 static const struct of_device_id altera_tse_ids[] = { 1585 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, }, 1586 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, }, 1587 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, }, 1588 {}, 1589 }; 1590 MODULE_DEVICE_TABLE(of, altera_tse_ids); 1591 1592 static struct platform_driver altera_tse_driver = { 1593 .probe = altera_tse_probe, 1594 .remove = altera_tse_remove, 1595 .suspend = NULL, 1596 .resume = NULL, 1597 .driver = { 1598 .name = ALTERA_TSE_RESOURCE_NAME, 1599 .of_match_table = altera_tse_ids, 1600 }, 1601 }; 1602 1603 module_platform_driver(altera_tse_driver); 1604 1605 MODULE_AUTHOR("Altera Corporation"); 1606 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver"); 1607 MODULE_LICENSE("GPL v2"); 1608