1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. 3 * 4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk> 5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk> 6 * 7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4 8 * integrated PHYs for the user facing ports, and an extension interface which 9 * can be connected to the CPU - or another PHY - via either MII, RMII, or 10 * RGMII. The switch is configured via the Realtek Simple Management Interface 11 * (SMI), which uses the MDIO/MDC lines. 12 * 13 * Below is a simplified block diagram of the chip and its relevant interfaces. 14 * 15 * .-----------------------------------. 16 * | | 17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC | 18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC | 19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC | 20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC | 21 * | | 22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension | 23 * | interface 1 GMAC 1 | 24 * | | 25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ | 26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ | 27 * | ~RTL8365MB ~~~ | 28 * | ~GXXXC TAIWAN~ | 29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ | 30 * | | 31 * Interrupt <----------> Link UP/DOWN events | 32 * controller | | 33 * '-----------------------------------' 34 * 35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the 36 * kernel. Netdevices are created for the user ports, as are PHY devices for 37 * their integrated PHYs. The device tree firmware should also specify the link 38 * partner of the extension port - either via a fixed-link or other phy-handle. 39 * See the device tree bindings for more detailed information. Note that the 40 * driver has only been tested with a fixed-link, but in principle it should not 41 * matter. 42 * 43 * NOTE: Currently, only the RGMII interface is implemented in this driver. 44 * 45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a 46 * custom irqchip to handle this interrupt and demultiplex the events by reading 47 * the status registers via SMI. Interrupts are then propagated to the relevant 48 * PHY device. 49 * 50 * The EEPROM contains initial register values which the chip will read over I2C 51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases, 52 * the driver will manually reprogram some registers using jam tables to reach 53 * an initial state defined by the vendor driver. 54 * 55 * This Linux driver is written based on an OS-agnostic vendor driver from 56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt 57 * source tree under the name rtl8367c. The vendor driver claims to support a 58 * number of similar switch controllers from Realtek, but the only hardware we 59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under 60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of 61 * common hardware revision, there exist examples of chips with the suffix -VC 62 * which are explicitly not supported by the rtl8367c driver and which instead 63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has 64 * been modestly named rtl8365mb. Future implementors may wish to rename things 65 * accordingly. 66 * 67 * In the same family of chips, some carry up to 8 user ports and up to 2 68 * extension ports. Where possible this driver tries to make things generic, but 69 * more work must be done to support these configurations. According to 70 * documentation from Realtek, the family should include the following chips: 71 * 72 * - RTL8363NB 73 * - RTL8363NB-VB 74 * - RTL8363SC 75 * - RTL8363SC-VB 76 * - RTL8364NB 77 * - RTL8364NB-VB 78 * - RTL8365MB-VC 79 * - RTL8366SC 80 * - RTL8367RB-VB 81 * - RTL8367SB 82 * - RTL8367S 83 * - RTL8370MB 84 * - RTL8310SR 85 * 86 * Some of the register logic for these additional chips has been skipped over 87 * while implementing this driver. It is therefore not possible to assume that 88 * things will work out-of-the-box for other chips, and a careful review of the 89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be 90 * one of the simpler chips. 91 */ 92 93 #include <linux/bitfield.h> 94 #include <linux/bitops.h> 95 #include <linux/interrupt.h> 96 #include <linux/irqdomain.h> 97 #include <linux/mutex.h> 98 #include <linux/of_irq.h> 99 #include <linux/regmap.h> 100 #include <linux/if_bridge.h> 101 102 #include "realtek.h" 103 104 /* Chip-specific data and limits */ 105 #define RTL8365MB_CHIP_ID_8365MB_VC 0x6367 106 #define RTL8365MB_CHIP_VER_8365MB_VC 0x0040 107 108 #define RTL8365MB_CHIP_ID_8367S 0x6367 109 #define RTL8365MB_CHIP_VER_8367S 0x00A0 110 111 #define RTL8365MB_CHIP_ID_8367RB 0x6367 112 #define RTL8365MB_CHIP_VER_8367RB 0x0020 113 114 /* Family-specific data and limits */ 115 #define RTL8365MB_PHYADDRMAX 7 116 #define RTL8365MB_NUM_PHYREGS 32 117 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) 118 /* RTL8370MB and RTL8310SR, possibly suportable by this driver, have 10 ports */ 119 #define RTL8365MB_MAX_NUM_PORTS 10 120 #define RTL8365MB_LEARN_LIMIT_MAX 2112 121 122 /* valid for all 6-port or less variants */ 123 static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, -1, -1}; 124 125 /* Chip identification registers */ 126 #define RTL8365MB_CHIP_ID_REG 0x1300 127 128 #define RTL8365MB_CHIP_VER_REG 0x1301 129 130 #define RTL8365MB_MAGIC_REG 0x13C2 131 #define RTL8365MB_MAGIC_VALUE 0x0249 132 133 /* Chip reset register */ 134 #define RTL8365MB_CHIP_RESET_REG 0x1322 135 #define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 136 #define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 137 138 /* Interrupt polarity register */ 139 #define RTL8365MB_INTR_POLARITY_REG 0x1100 140 #define RTL8365MB_INTR_POLARITY_MASK 0x0001 141 #define RTL8365MB_INTR_POLARITY_HIGH 0 142 #define RTL8365MB_INTR_POLARITY_LOW 1 143 144 /* Interrupt control/status register - enable/check specific interrupt types */ 145 #define RTL8365MB_INTR_CTRL_REG 0x1101 146 #define RTL8365MB_INTR_STATUS_REG 0x1102 147 #define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 148 #define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 149 #define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 150 #define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 151 #define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 152 #define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 153 #define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 154 #define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 155 #define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 156 #define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 157 #define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 158 #define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 159 #define RTL8365MB_INTR_ALL_MASK \ 160 (RTL8365MB_INTR_SLIENT_START_2_MASK | \ 161 RTL8365MB_INTR_SLIENT_START_MASK | \ 162 RTL8365MB_INTR_ACL_ACTION_MASK | \ 163 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ 164 RTL8365MB_INTR_INTERRUPT_8051_MASK | \ 165 RTL8365MB_INTR_LOOP_DETECTION_MASK | \ 166 RTL8365MB_INTR_GREEN_TIMER_MASK | \ 167 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ 168 RTL8365MB_INTR_SPEED_CHANGE_MASK | \ 169 RTL8365MB_INTR_LEARN_OVER_MASK | \ 170 RTL8365MB_INTR_METER_EXCEEDED_MASK | \ 171 RTL8365MB_INTR_LINK_CHANGE_MASK) 172 173 /* Per-port interrupt type status registers */ 174 #define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 175 #define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF 176 177 #define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 178 #define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF 179 180 /* PHY indirect access registers */ 181 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 182 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 183 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 184 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 185 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 186 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 187 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 188 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 189 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) 190 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) 191 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) 192 #define RTL8365MB_PHY_BASE 0x2000 193 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 194 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 195 196 /* PHY OCP address prefix register */ 197 #define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 198 #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 199 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 200 201 /* The PHY OCP addresses of PHY registers 0~31 start here */ 202 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 203 204 /* EXT interface port mode values - used in DIGITAL_INTERFACE_SELECT */ 205 #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 206 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 207 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 208 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 209 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 210 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 211 #define RTL8365MB_EXT_PORT_MODE_GMII 6 212 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 213 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 214 #define RTL8365MB_EXT_PORT_MODE_SGMII 9 215 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10 216 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 217 #define RTL8365MB_EXT_PORT_MODE_1000X 12 218 #define RTL8365MB_EXT_PORT_MODE_100FX 13 219 220 /* Realtek docs and driver uses logic number as EXT_PORT0=16, EXT_PORT1=17, 221 * EXT_PORT2=18, to interact with switch ports. That logic number is internally 222 * converted to either a physical port number (0..9) or an external interface id (0..2), 223 * depending on which function was called. The external interface id is calculated as 224 * (ext_id=logic_port-15), while the logical to physical map depends on the chip id/version. 225 * 226 * EXT_PORT0 mentioned in datasheets and rtl8367c driver is used in this driver 227 * as extid==1, EXT_PORT2, mentioned in Realtek rtl8367c driver for 10-port switches, 228 * would have an ext_id of 3 (out of range for most extint macros) and ext_id 0 does 229 * not seem to be used as well for this family. 230 */ 231 232 /* EXT interface mode configuration registers 0~1 */ 233 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT1 */ 234 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */ 235 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \ 236 ((_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \ 237 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \ 238 0x0) 239 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \ 240 (0xF << (((_extint) % 2))) 241 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ 242 (((_extint) % 2) * 4) 243 244 /* EXT interface RGMII TX/RX delay configuration registers 0~2 */ 245 #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */ 246 #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */ 247 #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */ 248 #define RTL8365MB_EXT_RGMXF_REG(_extint) \ 249 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \ 250 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \ 251 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \ 252 0x0) 253 #define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 254 #define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 255 256 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */ 257 #define RTL8365MB_PORT_SPEED_10M 0 258 #define RTL8365MB_PORT_SPEED_100M 1 259 #define RTL8365MB_PORT_SPEED_1000M 2 260 261 /* EXT interface force configuration registers 0~2 */ 262 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ 263 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */ 264 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */ 265 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \ 266 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \ 267 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \ 268 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \ 269 0x0) 270 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 271 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 272 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 273 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 274 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 275 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 276 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 277 278 /* CPU port mask register - controls which ports are treated as CPU ports */ 279 #define RTL8365MB_CPU_PORT_MASK_REG 0x1219 280 #define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF 281 282 /* CPU control register */ 283 #define RTL8365MB_CPU_CTRL_REG 0x121A 284 #define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 285 #define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 286 #define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 287 #define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 288 #define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 289 #define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 290 #define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 291 292 /* Maximum packet length register */ 293 #define RTL8365MB_CFG0_MAX_LEN_REG 0x088C 294 #define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF 295 296 /* Port learning limit registers */ 297 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 298 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ 299 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) 300 301 /* Port isolation (forwarding mask) registers */ 302 #define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 303 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \ 304 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) 305 #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF 306 307 /* MSTP port state registers - indexed by tree instance */ 308 #define RTL8365MB_MSTI_CTRL_BASE 0x0A00 309 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ 310 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) 311 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) 312 #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ 313 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) 314 315 /* MIB counter value registers */ 316 #define RTL8365MB_MIB_COUNTER_BASE 0x1000 317 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) 318 319 /* MIB counter address register */ 320 #define RTL8365MB_MIB_ADDRESS_REG 0x1004 321 #define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C 322 #define RTL8365MB_MIB_ADDRESS(_p, _x) \ 323 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) 324 325 #define RTL8365MB_MIB_CTRL0_REG 0x1005 326 #define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 327 #define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 328 329 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed 330 * to block. On the other hand, accessing MIB counters absolutely requires us to 331 * block. The solution is thus to schedule work which polls the MIB counters 332 * asynchronously and updates some private data, which the callback can then 333 * fetch atomically. Three seconds should be a good enough polling interval. 334 */ 335 #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) 336 337 enum rtl8365mb_mib_counter_index { 338 RTL8365MB_MIB_ifInOctets, 339 RTL8365MB_MIB_dot3StatsFCSErrors, 340 RTL8365MB_MIB_dot3StatsSymbolErrors, 341 RTL8365MB_MIB_dot3InPauseFrames, 342 RTL8365MB_MIB_dot3ControlInUnknownOpcodes, 343 RTL8365MB_MIB_etherStatsFragments, 344 RTL8365MB_MIB_etherStatsJabbers, 345 RTL8365MB_MIB_ifInUcastPkts, 346 RTL8365MB_MIB_etherStatsDropEvents, 347 RTL8365MB_MIB_ifInMulticastPkts, 348 RTL8365MB_MIB_ifInBroadcastPkts, 349 RTL8365MB_MIB_inMldChecksumError, 350 RTL8365MB_MIB_inIgmpChecksumError, 351 RTL8365MB_MIB_inMldSpecificQuery, 352 RTL8365MB_MIB_inMldGeneralQuery, 353 RTL8365MB_MIB_inIgmpSpecificQuery, 354 RTL8365MB_MIB_inIgmpGeneralQuery, 355 RTL8365MB_MIB_inMldLeaves, 356 RTL8365MB_MIB_inIgmpLeaves, 357 RTL8365MB_MIB_etherStatsOctets, 358 RTL8365MB_MIB_etherStatsUnderSizePkts, 359 RTL8365MB_MIB_etherOversizeStats, 360 RTL8365MB_MIB_etherStatsPkts64Octets, 361 RTL8365MB_MIB_etherStatsPkts65to127Octets, 362 RTL8365MB_MIB_etherStatsPkts128to255Octets, 363 RTL8365MB_MIB_etherStatsPkts256to511Octets, 364 RTL8365MB_MIB_etherStatsPkts512to1023Octets, 365 RTL8365MB_MIB_etherStatsPkts1024to1518Octets, 366 RTL8365MB_MIB_ifOutOctets, 367 RTL8365MB_MIB_dot3StatsSingleCollisionFrames, 368 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, 369 RTL8365MB_MIB_dot3StatsDeferredTransmissions, 370 RTL8365MB_MIB_dot3StatsLateCollisions, 371 RTL8365MB_MIB_etherStatsCollisions, 372 RTL8365MB_MIB_dot3StatsExcessiveCollisions, 373 RTL8365MB_MIB_dot3OutPauseFrames, 374 RTL8365MB_MIB_ifOutDiscards, 375 RTL8365MB_MIB_dot1dTpPortInDiscards, 376 RTL8365MB_MIB_ifOutUcastPkts, 377 RTL8365MB_MIB_ifOutMulticastPkts, 378 RTL8365MB_MIB_ifOutBroadcastPkts, 379 RTL8365MB_MIB_outOampduPkts, 380 RTL8365MB_MIB_inOampduPkts, 381 RTL8365MB_MIB_inIgmpJoinsSuccess, 382 RTL8365MB_MIB_inIgmpJoinsFail, 383 RTL8365MB_MIB_inMldJoinsSuccess, 384 RTL8365MB_MIB_inMldJoinsFail, 385 RTL8365MB_MIB_inReportSuppressionDrop, 386 RTL8365MB_MIB_inLeaveSuppressionDrop, 387 RTL8365MB_MIB_outIgmpReports, 388 RTL8365MB_MIB_outIgmpLeaves, 389 RTL8365MB_MIB_outIgmpGeneralQuery, 390 RTL8365MB_MIB_outIgmpSpecificQuery, 391 RTL8365MB_MIB_outMldReports, 392 RTL8365MB_MIB_outMldLeaves, 393 RTL8365MB_MIB_outMldGeneralQuery, 394 RTL8365MB_MIB_outMldSpecificQuery, 395 RTL8365MB_MIB_inKnownMulticastPkts, 396 RTL8365MB_MIB_END, 397 }; 398 399 struct rtl8365mb_mib_counter { 400 u32 offset; 401 u32 length; 402 const char *name; 403 }; 404 405 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ 406 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } 407 408 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { 409 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), 410 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), 411 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), 412 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), 413 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), 414 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), 415 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), 416 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), 417 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), 418 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), 419 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), 420 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), 421 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), 422 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), 423 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), 424 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), 425 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), 426 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), 427 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), 428 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), 429 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), 430 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), 431 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), 432 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), 433 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), 434 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), 435 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), 436 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), 437 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), 438 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), 439 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), 440 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), 441 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), 442 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), 443 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), 444 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), 445 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), 446 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), 447 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), 448 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), 449 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), 450 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), 451 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), 452 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), 453 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), 454 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), 455 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), 456 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), 457 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), 458 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), 459 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), 460 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), 461 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), 462 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), 463 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), 464 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), 465 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), 466 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), 467 }; 468 469 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); 470 471 struct rtl8365mb_jam_tbl_entry { 472 u16 reg; 473 u16 val; 474 }; 475 476 /* Lifted from the vendor driver sources */ 477 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { 478 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, 479 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, 480 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, 481 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F }, 482 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 }, 483 { 0x13F0, 0x0000 }, 484 }; 485 486 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { 487 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, 488 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, 489 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, 490 { 0x1D32, 0x0002 }, 491 }; 492 493 enum rtl8365mb_stp_state { 494 RTL8365MB_STP_STATE_DISABLED = 0, 495 RTL8365MB_STP_STATE_BLOCKING = 1, 496 RTL8365MB_STP_STATE_LEARNING = 2, 497 RTL8365MB_STP_STATE_FORWARDING = 3, 498 }; 499 500 enum rtl8365mb_cpu_insert { 501 RTL8365MB_CPU_INSERT_TO_ALL = 0, 502 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, 503 RTL8365MB_CPU_INSERT_TO_NONE = 2, 504 }; 505 506 enum rtl8365mb_cpu_position { 507 RTL8365MB_CPU_POS_AFTER_SA = 0, 508 RTL8365MB_CPU_POS_BEFORE_CRC = 1, 509 }; 510 511 enum rtl8365mb_cpu_format { 512 RTL8365MB_CPU_FORMAT_8BYTES = 0, 513 RTL8365MB_CPU_FORMAT_4BYTES = 1, 514 }; 515 516 enum rtl8365mb_cpu_rxlen { 517 RTL8365MB_CPU_RXLEN_72BYTES = 0, 518 RTL8365MB_CPU_RXLEN_64BYTES = 1, 519 }; 520 521 /** 522 * struct rtl8365mb_cpu - CPU port configuration 523 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames 524 * @mask: port mask of ports that parse should parse CPU tags 525 * @trap_port: forward trapped frames to this port 526 * @insert: CPU tag insertion mode in switch->CPU frames 527 * @position: position of CPU tag in frame 528 * @rx_length: minimum CPU RX length 529 * @format: CPU tag format 530 * 531 * Represents the CPU tagging and CPU port configuration of the switch. These 532 * settings are configurable at runtime. 533 */ 534 struct rtl8365mb_cpu { 535 bool enable; 536 u32 mask; 537 u32 trap_port; 538 enum rtl8365mb_cpu_insert insert; 539 enum rtl8365mb_cpu_position position; 540 enum rtl8365mb_cpu_rxlen rx_length; 541 enum rtl8365mb_cpu_format format; 542 }; 543 544 /** 545 * struct rtl8365mb_port - private per-port data 546 * @priv: pointer to parent realtek_priv data 547 * @index: DSA port index, same as dsa_port::index 548 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic 549 * access via rtl8365mb_get_stats64 550 * @stats_lock: protect the stats structure during read/update 551 * @mib_work: delayed work for polling MIB counters 552 */ 553 struct rtl8365mb_port { 554 struct realtek_priv *priv; 555 unsigned int index; 556 struct rtnl_link_stats64 stats; 557 spinlock_t stats_lock; 558 struct delayed_work mib_work; 559 }; 560 561 /** 562 * struct rtl8365mb - private chip-specific driver data 563 * @priv: pointer to parent realtek_priv data 564 * @irq: registered IRQ or zero 565 * @chip_id: chip identifier 566 * @chip_ver: chip silicon revision 567 * @port_mask: mask of all ports 568 * @learn_limit_max: maximum number of L2 addresses the chip can learn 569 * @cpu: CPU tagging and CPU port configuration for this chip 570 * @mib_lock: prevent concurrent reads of MIB counters 571 * @ports: per-port data 572 * @jam_table: chip-specific initialization jam table 573 * @jam_size: size of the chip's jam table 574 * 575 * Private data for this driver. 576 */ 577 struct rtl8365mb { 578 struct realtek_priv *priv; 579 int irq; 580 u32 chip_id; 581 u32 chip_ver; 582 u32 port_mask; 583 u32 learn_limit_max; 584 struct rtl8365mb_cpu cpu; 585 struct mutex mib_lock; 586 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; 587 const struct rtl8365mb_jam_tbl_entry *jam_table; 588 size_t jam_size; 589 }; 590 591 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) 592 { 593 u32 val; 594 595 return regmap_read_poll_timeout(priv->map_nolock, 596 RTL8365MB_INDIRECT_ACCESS_STATUS_REG, 597 val, !val, 10, 100); 598 } 599 600 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, 601 u32 ocp_addr) 602 { 603 u32 val; 604 int ret; 605 606 /* Set OCP prefix */ 607 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); 608 ret = regmap_update_bits( 609 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG, 610 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, 611 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); 612 if (ret) 613 return ret; 614 615 /* Set PHY register address */ 616 val = RTL8365MB_PHY_BASE; 617 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); 618 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, 619 ocp_addr >> 1); 620 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, 621 ocp_addr >> 6); 622 ret = regmap_write(priv->map_nolock, 623 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val); 624 if (ret) 625 return ret; 626 627 return 0; 628 } 629 630 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, 631 u32 ocp_addr, u16 *data) 632 { 633 u32 val; 634 int ret; 635 636 mutex_lock(&priv->map_lock); 637 638 ret = rtl8365mb_phy_poll_busy(priv); 639 if (ret) 640 goto out; 641 642 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 643 if (ret) 644 goto out; 645 646 /* Execute read operation */ 647 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 648 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 649 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 650 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); 651 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 652 val); 653 if (ret) 654 goto out; 655 656 ret = rtl8365mb_phy_poll_busy(priv); 657 if (ret) 658 goto out; 659 660 /* Get PHY register data */ 661 ret = regmap_read(priv->map_nolock, 662 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val); 663 if (ret) 664 goto out; 665 666 *data = val & 0xFFFF; 667 668 out: 669 mutex_unlock(&priv->map_lock); 670 671 return ret; 672 } 673 674 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, 675 u32 ocp_addr, u16 data) 676 { 677 u32 val; 678 int ret; 679 680 mutex_lock(&priv->map_lock); 681 682 ret = rtl8365mb_phy_poll_busy(priv); 683 if (ret) 684 goto out; 685 686 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 687 if (ret) 688 goto out; 689 690 /* Set PHY register data */ 691 ret = regmap_write(priv->map_nolock, 692 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data); 693 if (ret) 694 goto out; 695 696 /* Execute write operation */ 697 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 698 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 699 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 700 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); 701 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 702 val); 703 if (ret) 704 goto out; 705 706 ret = rtl8365mb_phy_poll_busy(priv); 707 if (ret) 708 goto out; 709 710 out: 711 mutex_unlock(&priv->map_lock); 712 713 return 0; 714 } 715 716 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) 717 { 718 u32 ocp_addr; 719 u16 val; 720 int ret; 721 722 if (phy > RTL8365MB_PHYADDRMAX) 723 return -EINVAL; 724 725 if (regnum > RTL8365MB_PHYREGMAX) 726 return -EINVAL; 727 728 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 729 730 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); 731 if (ret) { 732 dev_err(priv->dev, 733 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, 734 regnum, ocp_addr, ret); 735 return ret; 736 } 737 738 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", 739 phy, regnum, ocp_addr, val); 740 741 return val; 742 } 743 744 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, 745 u16 val) 746 { 747 u32 ocp_addr; 748 int ret; 749 750 if (phy > RTL8365MB_PHYADDRMAX) 751 return -EINVAL; 752 753 if (regnum > RTL8365MB_PHYREGMAX) 754 return -EINVAL; 755 756 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 757 758 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); 759 if (ret) { 760 dev_err(priv->dev, 761 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, 762 regnum, ocp_addr, ret); 763 return ret; 764 } 765 766 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", 767 phy, regnum, ocp_addr, val); 768 769 return 0; 770 } 771 772 static int rtl8365mb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum) 773 { 774 return rtl8365mb_phy_read(ds->priv, phy, regnum); 775 } 776 777 static int rtl8365mb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum, 778 u16 val) 779 { 780 return rtl8365mb_phy_write(ds->priv, phy, regnum, val); 781 } 782 783 static enum dsa_tag_protocol 784 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, 785 enum dsa_tag_protocol mp) 786 { 787 struct realtek_priv *priv = ds->priv; 788 struct rtl8365mb_cpu *cpu; 789 struct rtl8365mb *mb; 790 791 mb = priv->chip_data; 792 cpu = &mb->cpu; 793 794 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC) 795 return DSA_TAG_PROTO_RTL8_4T; 796 797 return DSA_TAG_PROTO_RTL8_4; 798 } 799 800 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, 801 phy_interface_t interface) 802 { 803 struct device_node *dn; 804 struct dsa_port *dp; 805 int tx_delay = 0; 806 int rx_delay = 0; 807 int ext_int; 808 u32 val; 809 int ret; 810 811 ext_int = rtl8365mb_extint_port_map[port]; 812 813 if (ext_int <= 0) { 814 dev_err(priv->dev, "Port %d is not an external interface port\n", port); 815 return -EINVAL; 816 } 817 818 dp = dsa_to_port(priv->ds, port); 819 dn = dp->dn; 820 821 /* Set the RGMII TX/RX delay 822 * 823 * The Realtek vendor driver indicates the following possible 824 * configuration settings: 825 * 826 * TX delay: 827 * 0 = no delay, 1 = 2 ns delay 828 * RX delay: 829 * 0 = no delay, 7 = maximum delay 830 * Each step is approximately 0.3 ns, so the maximum delay is about 831 * 2.1 ns. 832 * 833 * The vendor driver also states that this must be configured *before* 834 * forcing the external interface into a particular mode, which is done 835 * in the rtl8365mb_phylink_mac_link_{up,down} functions. 836 * 837 * Only configure an RGMII TX (resp. RX) delay if the 838 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is 839 * specified. We ignore the detail of the RGMII interface mode 840 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only 841 * property. 842 */ 843 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) { 844 val = val / 1000; /* convert to ns */ 845 846 if (val == 0 || val == 2) 847 tx_delay = val / 2; 848 else 849 dev_warn(priv->dev, 850 "EXT interface TX delay must be 0 or 2 ns\n"); 851 } 852 853 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { 854 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */ 855 856 if (val <= 7) 857 rx_delay = val; 858 else 859 dev_warn(priv->dev, 860 "EXT interface RX delay must be 0 to 2.1 ns\n"); 861 } 862 863 ret = regmap_update_bits( 864 priv->map, RTL8365MB_EXT_RGMXF_REG(ext_int), 865 RTL8365MB_EXT_RGMXF_TXDELAY_MASK | 866 RTL8365MB_EXT_RGMXF_RXDELAY_MASK, 867 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | 868 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); 869 if (ret) 870 return ret; 871 872 ret = regmap_update_bits( 873 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_int), 874 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_int), 875 RTL8365MB_EXT_PORT_MODE_RGMII 876 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( 877 ext_int)); 878 if (ret) 879 return ret; 880 881 return 0; 882 } 883 884 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, 885 bool link, int speed, int duplex, 886 bool tx_pause, bool rx_pause) 887 { 888 u32 r_tx_pause; 889 u32 r_rx_pause; 890 u32 r_duplex; 891 u32 r_speed; 892 u32 r_link; 893 int ext_int; 894 int val; 895 int ret; 896 897 ext_int = rtl8365mb_extint_port_map[port]; 898 899 if (ext_int <= 0) { 900 dev_err(priv->dev, "Port %d is not an external interface port\n", port); 901 return -EINVAL; 902 } 903 904 if (link) { 905 /* Force the link up with the desired configuration */ 906 r_link = 1; 907 r_rx_pause = rx_pause ? 1 : 0; 908 r_tx_pause = tx_pause ? 1 : 0; 909 910 if (speed == SPEED_1000) { 911 r_speed = RTL8365MB_PORT_SPEED_1000M; 912 } else if (speed == SPEED_100) { 913 r_speed = RTL8365MB_PORT_SPEED_100M; 914 } else if (speed == SPEED_10) { 915 r_speed = RTL8365MB_PORT_SPEED_10M; 916 } else { 917 dev_err(priv->dev, "unsupported port speed %s\n", 918 phy_speed_to_str(speed)); 919 return -EINVAL; 920 } 921 922 if (duplex == DUPLEX_FULL) { 923 r_duplex = 1; 924 } else if (duplex == DUPLEX_HALF) { 925 r_duplex = 0; 926 } else { 927 dev_err(priv->dev, "unsupported duplex %s\n", 928 phy_duplex_to_str(duplex)); 929 return -EINVAL; 930 } 931 } else { 932 /* Force the link down and reset any programmed configuration */ 933 r_link = 0; 934 r_tx_pause = 0; 935 r_rx_pause = 0; 936 r_speed = 0; 937 r_duplex = 0; 938 } 939 940 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | 941 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, 942 r_tx_pause) | 943 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, 944 r_rx_pause) | 945 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | 946 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, 947 r_duplex) | 948 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); 949 ret = regmap_write(priv->map, 950 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_int), 951 val); 952 if (ret) 953 return ret; 954 955 return 0; 956 } 957 958 static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port, 959 struct phylink_config *config) 960 { 961 if (dsa_is_user_port(ds, port)) { 962 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 963 config->supported_interfaces); 964 965 /* GMII is the default interface mode for phylib, so 966 * we have to support it for ports with integrated PHY. 967 */ 968 __set_bit(PHY_INTERFACE_MODE_GMII, 969 config->supported_interfaces); 970 } else if (dsa_is_cpu_port(ds, port)) { 971 phy_interface_set_rgmii(config->supported_interfaces); 972 } 973 974 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 975 MAC_10 | MAC_100 | MAC_1000FD; 976 } 977 978 static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, 979 unsigned int mode, 980 const struct phylink_link_state *state) 981 { 982 struct realtek_priv *priv = ds->priv; 983 int ret; 984 985 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) { 986 dev_err(priv->dev, 987 "port %d supports only conventional PHY or fixed-link\n", 988 port); 989 return; 990 } 991 992 if (phy_interface_mode_is_rgmii(state->interface)) { 993 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); 994 if (ret) 995 dev_err(priv->dev, 996 "failed to configure RGMII mode on port %d: %d\n", 997 port, ret); 998 return; 999 } 1000 1001 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also 1002 * supports 1003 */ 1004 } 1005 1006 static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, 1007 unsigned int mode, 1008 phy_interface_t interface) 1009 { 1010 struct realtek_priv *priv = ds->priv; 1011 struct rtl8365mb_port *p; 1012 struct rtl8365mb *mb; 1013 int ret; 1014 1015 mb = priv->chip_data; 1016 p = &mb->ports[port]; 1017 cancel_delayed_work_sync(&p->mib_work); 1018 1019 if (phy_interface_mode_is_rgmii(interface)) { 1020 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, 1021 false, false); 1022 if (ret) 1023 dev_err(priv->dev, 1024 "failed to reset forced mode on port %d: %d\n", 1025 port, ret); 1026 1027 return; 1028 } 1029 } 1030 1031 static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, 1032 unsigned int mode, 1033 phy_interface_t interface, 1034 struct phy_device *phydev, int speed, 1035 int duplex, bool tx_pause, 1036 bool rx_pause) 1037 { 1038 struct realtek_priv *priv = ds->priv; 1039 struct rtl8365mb_port *p; 1040 struct rtl8365mb *mb; 1041 int ret; 1042 1043 mb = priv->chip_data; 1044 p = &mb->ports[port]; 1045 schedule_delayed_work(&p->mib_work, 0); 1046 1047 if (phy_interface_mode_is_rgmii(interface)) { 1048 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, 1049 duplex, tx_pause, 1050 rx_pause); 1051 if (ret) 1052 dev_err(priv->dev, 1053 "failed to force mode on port %d: %d\n", port, 1054 ret); 1055 1056 return; 1057 } 1058 } 1059 1060 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, 1061 u8 state) 1062 { 1063 struct realtek_priv *priv = ds->priv; 1064 enum rtl8365mb_stp_state val; 1065 int msti = 0; 1066 1067 switch (state) { 1068 case BR_STATE_DISABLED: 1069 val = RTL8365MB_STP_STATE_DISABLED; 1070 break; 1071 case BR_STATE_BLOCKING: 1072 case BR_STATE_LISTENING: 1073 val = RTL8365MB_STP_STATE_BLOCKING; 1074 break; 1075 case BR_STATE_LEARNING: 1076 val = RTL8365MB_STP_STATE_LEARNING; 1077 break; 1078 case BR_STATE_FORWARDING: 1079 val = RTL8365MB_STP_STATE_FORWARDING; 1080 break; 1081 default: 1082 dev_err(priv->dev, "invalid STP state: %u\n", state); 1083 return; 1084 } 1085 1086 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), 1087 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), 1088 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); 1089 } 1090 1091 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, 1092 bool enable) 1093 { 1094 struct rtl8365mb *mb = priv->chip_data; 1095 1096 /* Enable/disable learning by limiting the number of L2 addresses the 1097 * port can learn. Realtek documentation states that a limit of zero 1098 * disables learning. When enabling learning, set it to the chip's 1099 * maximum. 1100 */ 1101 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), 1102 enable ? mb->learn_limit_max : 0); 1103 } 1104 1105 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, 1106 u32 mask) 1107 { 1108 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); 1109 } 1110 1111 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, 1112 u32 offset, u32 length, u64 *mibvalue) 1113 { 1114 u64 tmpvalue = 0; 1115 u32 val; 1116 int ret; 1117 int i; 1118 1119 /* The MIB address is an SRAM address. We request a particular address 1120 * and then poll the control register before reading the value from some 1121 * counter registers. 1122 */ 1123 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, 1124 RTL8365MB_MIB_ADDRESS(port, offset)); 1125 if (ret) 1126 return ret; 1127 1128 /* Poll for completion */ 1129 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, 1130 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), 1131 10, 100); 1132 if (ret) 1133 return ret; 1134 1135 /* Presumably this indicates a MIB counter read failure */ 1136 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) 1137 return -EIO; 1138 1139 /* There are four MIB counter registers each holding a 16 bit word of a 1140 * MIB counter. Depending on the offset, we should read from the upper 1141 * two or lower two registers. In case the MIB counter is 4 words, we 1142 * read from all four registers. 1143 */ 1144 if (length == 4) 1145 offset = 3; 1146 else 1147 offset = (offset + 1) % 4; 1148 1149 /* Read the MIB counter 16 bits at a time */ 1150 for (i = 0; i < length; i++) { 1151 ret = regmap_read(priv->map, 1152 RTL8365MB_MIB_COUNTER_REG(offset - i), &val); 1153 if (ret) 1154 return ret; 1155 1156 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF); 1157 } 1158 1159 /* Only commit the result if no error occurred */ 1160 *mibvalue = tmpvalue; 1161 1162 return 0; 1163 } 1164 1165 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1166 { 1167 struct realtek_priv *priv = ds->priv; 1168 struct rtl8365mb *mb; 1169 int ret; 1170 int i; 1171 1172 mb = priv->chip_data; 1173 1174 mutex_lock(&mb->mib_lock); 1175 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1176 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1177 1178 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1179 mib->length, &data[i]); 1180 if (ret) { 1181 dev_err(priv->dev, 1182 "failed to read port %d counters: %d\n", port, 1183 ret); 1184 break; 1185 } 1186 } 1187 mutex_unlock(&mb->mib_lock); 1188 } 1189 1190 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) 1191 { 1192 int i; 1193 1194 if (stringset != ETH_SS_STATS) 1195 return; 1196 1197 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1198 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1199 1200 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN); 1201 } 1202 } 1203 1204 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) 1205 { 1206 if (sset != ETH_SS_STATS) 1207 return -EOPNOTSUPP; 1208 1209 return RTL8365MB_MIB_END; 1210 } 1211 1212 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, 1213 struct ethtool_eth_phy_stats *phy_stats) 1214 { 1215 struct realtek_priv *priv = ds->priv; 1216 struct rtl8365mb_mib_counter *mib; 1217 struct rtl8365mb *mb; 1218 1219 mb = priv->chip_data; 1220 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; 1221 1222 mutex_lock(&mb->mib_lock); 1223 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1224 &phy_stats->SymbolErrorDuringCarrier); 1225 mutex_unlock(&mb->mib_lock); 1226 } 1227 1228 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, 1229 struct ethtool_eth_mac_stats *mac_stats) 1230 { 1231 u64 cnt[RTL8365MB_MIB_END] = { 1232 [RTL8365MB_MIB_ifOutOctets] = 1, 1233 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1234 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1235 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1236 [RTL8365MB_MIB_dot3OutPauseFrames] = 1, 1237 [RTL8365MB_MIB_ifOutDiscards] = 1, 1238 [RTL8365MB_MIB_ifInOctets] = 1, 1239 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1240 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1241 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1242 [RTL8365MB_MIB_dot3InPauseFrames] = 1, 1243 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, 1244 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, 1245 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1246 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, 1247 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1248 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, 1249 1250 }; 1251 struct realtek_priv *priv = ds->priv; 1252 struct rtl8365mb *mb; 1253 int ret; 1254 int i; 1255 1256 mb = priv->chip_data; 1257 1258 mutex_lock(&mb->mib_lock); 1259 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1260 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1261 1262 /* Only fetch required MIB counters (marked = 1 above) */ 1263 if (!cnt[i]) 1264 continue; 1265 1266 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1267 mib->length, &cnt[i]); 1268 if (ret) 1269 break; 1270 } 1271 mutex_unlock(&mb->mib_lock); 1272 1273 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into 1274 * IEEE 802.3 Managed Objects. This is not always completely faithful, 1275 * but we try out best. See RFC 3635 for a detailed treatment of the 1276 * subject. 1277 */ 1278 1279 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1280 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1281 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + 1282 cnt[RTL8365MB_MIB_dot3OutPauseFrames] - 1283 cnt[RTL8365MB_MIB_ifOutDiscards]; 1284 mac_stats->SingleCollisionFrames = 1285 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; 1286 mac_stats->MultipleCollisionFrames = 1287 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; 1288 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1289 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1290 cnt[RTL8365MB_MIB_ifInBroadcastPkts] + 1291 cnt[RTL8365MB_MIB_dot3InPauseFrames]; 1292 mac_stats->FrameCheckSequenceErrors = 1293 cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1294 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - 1295 18 * mac_stats->FramesTransmittedOK; 1296 mac_stats->FramesWithDeferredXmissions = 1297 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; 1298 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1299 mac_stats->FramesAbortedDueToXSColls = 1300 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; 1301 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - 1302 18 * mac_stats->FramesReceivedOK; 1303 mac_stats->MulticastFramesXmittedOK = 1304 cnt[RTL8365MB_MIB_ifOutMulticastPkts]; 1305 mac_stats->BroadcastFramesXmittedOK = 1306 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1307 mac_stats->MulticastFramesReceivedOK = 1308 cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1309 mac_stats->BroadcastFramesReceivedOK = 1310 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 1311 } 1312 1313 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, 1314 struct ethtool_eth_ctrl_stats *ctrl_stats) 1315 { 1316 struct realtek_priv *priv = ds->priv; 1317 struct rtl8365mb_mib_counter *mib; 1318 struct rtl8365mb *mb; 1319 1320 mb = priv->chip_data; 1321 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; 1322 1323 mutex_lock(&mb->mib_lock); 1324 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1325 &ctrl_stats->UnsupportedOpcodesReceived); 1326 mutex_unlock(&mb->mib_lock); 1327 } 1328 1329 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) 1330 { 1331 u64 cnt[RTL8365MB_MIB_END] = { 1332 [RTL8365MB_MIB_ifOutOctets] = 1, 1333 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1334 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1335 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1336 [RTL8365MB_MIB_ifOutDiscards] = 1, 1337 [RTL8365MB_MIB_ifInOctets] = 1, 1338 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1339 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1340 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1341 [RTL8365MB_MIB_etherStatsDropEvents] = 1, 1342 [RTL8365MB_MIB_etherStatsCollisions] = 1, 1343 [RTL8365MB_MIB_etherStatsFragments] = 1, 1344 [RTL8365MB_MIB_etherStatsJabbers] = 1, 1345 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1346 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1347 }; 1348 struct rtl8365mb *mb = priv->chip_data; 1349 struct rtnl_link_stats64 *stats; 1350 int ret; 1351 int i; 1352 1353 stats = &mb->ports[port].stats; 1354 1355 mutex_lock(&mb->mib_lock); 1356 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1357 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; 1358 1359 /* Only fetch required MIB counters (marked = 1 above) */ 1360 if (!cnt[i]) 1361 continue; 1362 1363 ret = rtl8365mb_mib_counter_read(priv, port, c->offset, 1364 c->length, &cnt[i]); 1365 if (ret) 1366 break; 1367 } 1368 mutex_unlock(&mb->mib_lock); 1369 1370 /* Don't update statistics if there was an error reading the counters */ 1371 if (ret) 1372 return; 1373 1374 spin_lock(&mb->ports[port].stats_lock); 1375 1376 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1377 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1378 cnt[RTL8365MB_MIB_ifInBroadcastPkts] - 1379 cnt[RTL8365MB_MIB_ifOutDiscards]; 1380 1381 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1382 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1383 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1384 1385 /* if{In,Out}Octets includes FCS - remove it */ 1386 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; 1387 stats->tx_bytes = 1388 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; 1389 1390 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; 1391 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; 1392 1393 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1394 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; 1395 1396 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + 1397 cnt[RTL8365MB_MIB_etherStatsJabbers]; 1398 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1399 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; 1400 1401 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; 1402 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1403 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; 1404 1405 spin_unlock(&mb->ports[port].stats_lock); 1406 } 1407 1408 static void rtl8365mb_stats_poll(struct work_struct *work) 1409 { 1410 struct rtl8365mb_port *p = container_of(to_delayed_work(work), 1411 struct rtl8365mb_port, 1412 mib_work); 1413 struct realtek_priv *priv = p->priv; 1414 1415 rtl8365mb_stats_update(priv, p->index); 1416 1417 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); 1418 } 1419 1420 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, 1421 struct rtnl_link_stats64 *s) 1422 { 1423 struct realtek_priv *priv = ds->priv; 1424 struct rtl8365mb_port *p; 1425 struct rtl8365mb *mb; 1426 1427 mb = priv->chip_data; 1428 p = &mb->ports[port]; 1429 1430 spin_lock(&p->stats_lock); 1431 memcpy(s, &p->stats, sizeof(*s)); 1432 spin_unlock(&p->stats_lock); 1433 } 1434 1435 static void rtl8365mb_stats_setup(struct realtek_priv *priv) 1436 { 1437 struct rtl8365mb *mb = priv->chip_data; 1438 int i; 1439 1440 /* Per-chip global mutex to protect MIB counter access, since doing 1441 * so requires accessing a series of registers in a particular order. 1442 */ 1443 mutex_init(&mb->mib_lock); 1444 1445 for (i = 0; i < priv->num_ports; i++) { 1446 struct rtl8365mb_port *p = &mb->ports[i]; 1447 1448 if (dsa_is_unused_port(priv->ds, i)) 1449 continue; 1450 1451 /* Per-port spinlock to protect the stats64 data */ 1452 spin_lock_init(&p->stats_lock); 1453 1454 /* This work polls the MIB counters and keeps the stats64 data 1455 * up-to-date. 1456 */ 1457 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); 1458 } 1459 } 1460 1461 static void rtl8365mb_stats_teardown(struct realtek_priv *priv) 1462 { 1463 struct rtl8365mb *mb = priv->chip_data; 1464 int i; 1465 1466 for (i = 0; i < priv->num_ports; i++) { 1467 struct rtl8365mb_port *p = &mb->ports[i]; 1468 1469 if (dsa_is_unused_port(priv->ds, i)) 1470 continue; 1471 1472 cancel_delayed_work_sync(&p->mib_work); 1473 } 1474 } 1475 1476 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, 1477 u32 *val) 1478 { 1479 int ret; 1480 1481 ret = regmap_read(priv->map, reg, val); 1482 if (ret) 1483 return ret; 1484 1485 return regmap_write(priv->map, reg, *val); 1486 } 1487 1488 static irqreturn_t rtl8365mb_irq(int irq, void *data) 1489 { 1490 struct realtek_priv *priv = data; 1491 unsigned long line_changes = 0; 1492 struct rtl8365mb *mb; 1493 u32 stat; 1494 int line; 1495 int ret; 1496 1497 mb = priv->chip_data; 1498 1499 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, 1500 &stat); 1501 if (ret) 1502 goto out_error; 1503 1504 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { 1505 u32 linkdown_ind; 1506 u32 linkup_ind; 1507 u32 val; 1508 1509 ret = rtl8365mb_get_and_clear_status_reg( 1510 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); 1511 if (ret) 1512 goto out_error; 1513 1514 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); 1515 1516 ret = rtl8365mb_get_and_clear_status_reg( 1517 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); 1518 if (ret) 1519 goto out_error; 1520 1521 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); 1522 1523 line_changes = (linkup_ind | linkdown_ind) & mb->port_mask; 1524 } 1525 1526 if (!line_changes) 1527 goto out_none; 1528 1529 for_each_set_bit(line, &line_changes, priv->num_ports) { 1530 int child_irq = irq_find_mapping(priv->irqdomain, line); 1531 1532 handle_nested_irq(child_irq); 1533 } 1534 1535 return IRQ_HANDLED; 1536 1537 out_error: 1538 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret); 1539 1540 out_none: 1541 return IRQ_NONE; 1542 } 1543 1544 static struct irq_chip rtl8365mb_irq_chip = { 1545 .name = "rtl8365mb", 1546 /* The hardware doesn't support masking IRQs on a per-port basis */ 1547 }; 1548 1549 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, 1550 irq_hw_number_t hwirq) 1551 { 1552 irq_set_chip_data(irq, domain->host_data); 1553 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); 1554 irq_set_nested_thread(irq, 1); 1555 irq_set_noprobe(irq); 1556 1557 return 0; 1558 } 1559 1560 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) 1561 { 1562 irq_set_nested_thread(irq, 0); 1563 irq_set_chip_and_handler(irq, NULL, NULL); 1564 irq_set_chip_data(irq, NULL); 1565 } 1566 1567 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { 1568 .map = rtl8365mb_irq_map, 1569 .unmap = rtl8365mb_irq_unmap, 1570 .xlate = irq_domain_xlate_onecell, 1571 }; 1572 1573 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) 1574 { 1575 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, 1576 RTL8365MB_INTR_LINK_CHANGE_MASK, 1577 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, 1578 enable ? 1 : 0)); 1579 } 1580 1581 static int rtl8365mb_irq_enable(struct realtek_priv *priv) 1582 { 1583 return rtl8365mb_set_irq_enable(priv, true); 1584 } 1585 1586 static int rtl8365mb_irq_disable(struct realtek_priv *priv) 1587 { 1588 return rtl8365mb_set_irq_enable(priv, false); 1589 } 1590 1591 static int rtl8365mb_irq_setup(struct realtek_priv *priv) 1592 { 1593 struct rtl8365mb *mb = priv->chip_data; 1594 struct device_node *intc; 1595 u32 irq_trig; 1596 int virq; 1597 int irq; 1598 u32 val; 1599 int ret; 1600 int i; 1601 1602 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 1603 if (!intc) { 1604 dev_err(priv->dev, "missing child interrupt-controller node\n"); 1605 return -EINVAL; 1606 } 1607 1608 /* rtl8365mb IRQs cascade off this one */ 1609 irq = of_irq_get(intc, 0); 1610 if (irq <= 0) { 1611 if (irq != -EPROBE_DEFER) 1612 dev_err(priv->dev, "failed to get parent irq: %d\n", 1613 irq); 1614 ret = irq ? irq : -EINVAL; 1615 goto out_put_node; 1616 } 1617 1618 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, 1619 &rtl8365mb_irqdomain_ops, priv); 1620 if (!priv->irqdomain) { 1621 dev_err(priv->dev, "failed to add irq domain\n"); 1622 ret = -ENOMEM; 1623 goto out_put_node; 1624 } 1625 1626 for (i = 0; i < priv->num_ports; i++) { 1627 virq = irq_create_mapping(priv->irqdomain, i); 1628 if (!virq) { 1629 dev_err(priv->dev, 1630 "failed to create irq domain mapping\n"); 1631 ret = -EINVAL; 1632 goto out_remove_irqdomain; 1633 } 1634 1635 irq_set_parent(virq, irq); 1636 } 1637 1638 /* Configure chip interrupt signal polarity */ 1639 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1640 switch (irq_trig) { 1641 case IRQF_TRIGGER_RISING: 1642 case IRQF_TRIGGER_HIGH: 1643 val = RTL8365MB_INTR_POLARITY_HIGH; 1644 break; 1645 case IRQF_TRIGGER_FALLING: 1646 case IRQF_TRIGGER_LOW: 1647 val = RTL8365MB_INTR_POLARITY_LOW; 1648 break; 1649 default: 1650 dev_err(priv->dev, "unsupported irq trigger type %u\n", 1651 irq_trig); 1652 ret = -EINVAL; 1653 goto out_remove_irqdomain; 1654 } 1655 1656 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, 1657 RTL8365MB_INTR_POLARITY_MASK, 1658 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); 1659 if (ret) 1660 goto out_remove_irqdomain; 1661 1662 /* Disable the interrupt in case the chip has it enabled on reset */ 1663 ret = rtl8365mb_irq_disable(priv); 1664 if (ret) 1665 goto out_remove_irqdomain; 1666 1667 /* Clear the interrupt status register */ 1668 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, 1669 RTL8365MB_INTR_ALL_MASK); 1670 if (ret) 1671 goto out_remove_irqdomain; 1672 1673 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, 1674 "rtl8365mb", priv); 1675 if (ret) { 1676 dev_err(priv->dev, "failed to request irq: %d\n", ret); 1677 goto out_remove_irqdomain; 1678 } 1679 1680 /* Store the irq so that we know to free it during teardown */ 1681 mb->irq = irq; 1682 1683 ret = rtl8365mb_irq_enable(priv); 1684 if (ret) 1685 goto out_free_irq; 1686 1687 of_node_put(intc); 1688 1689 return 0; 1690 1691 out_free_irq: 1692 free_irq(mb->irq, priv); 1693 mb->irq = 0; 1694 1695 out_remove_irqdomain: 1696 for (i = 0; i < priv->num_ports; i++) { 1697 virq = irq_find_mapping(priv->irqdomain, i); 1698 irq_dispose_mapping(virq); 1699 } 1700 1701 irq_domain_remove(priv->irqdomain); 1702 priv->irqdomain = NULL; 1703 1704 out_put_node: 1705 of_node_put(intc); 1706 1707 return ret; 1708 } 1709 1710 static void rtl8365mb_irq_teardown(struct realtek_priv *priv) 1711 { 1712 struct rtl8365mb *mb = priv->chip_data; 1713 int virq; 1714 int i; 1715 1716 if (mb->irq) { 1717 free_irq(mb->irq, priv); 1718 mb->irq = 0; 1719 } 1720 1721 if (priv->irqdomain) { 1722 for (i = 0; i < priv->num_ports; i++) { 1723 virq = irq_find_mapping(priv->irqdomain, i); 1724 irq_dispose_mapping(virq); 1725 } 1726 1727 irq_domain_remove(priv->irqdomain); 1728 priv->irqdomain = NULL; 1729 } 1730 } 1731 1732 static int rtl8365mb_cpu_config(struct realtek_priv *priv) 1733 { 1734 struct rtl8365mb *mb = priv->chip_data; 1735 struct rtl8365mb_cpu *cpu = &mb->cpu; 1736 u32 val; 1737 int ret; 1738 1739 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, 1740 RTL8365MB_CPU_PORT_MASK_MASK, 1741 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, 1742 cpu->mask)); 1743 if (ret) 1744 return ret; 1745 1746 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | 1747 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | 1748 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | 1749 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | 1750 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | 1751 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) | 1752 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, 1753 cpu->trap_port >> 3 & 0x1); 1754 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); 1755 if (ret) 1756 return ret; 1757 1758 return 0; 1759 } 1760 1761 static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds, 1762 enum dsa_tag_protocol proto) 1763 { 1764 struct realtek_priv *priv = ds->priv; 1765 struct rtl8365mb_cpu *cpu; 1766 struct rtl8365mb *mb; 1767 1768 mb = priv->chip_data; 1769 cpu = &mb->cpu; 1770 1771 switch (proto) { 1772 case DSA_TAG_PROTO_RTL8_4: 1773 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 1774 cpu->position = RTL8365MB_CPU_POS_AFTER_SA; 1775 break; 1776 case DSA_TAG_PROTO_RTL8_4T: 1777 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 1778 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC; 1779 break; 1780 /* The switch also supports a 4-byte format, similar to rtl4a but with 1781 * the same 0x04 8-bit version and probably 8-bit port source/dest. 1782 * There is no public doc about it. Not supported yet and it will probably 1783 * never be. 1784 */ 1785 default: 1786 return -EPROTONOSUPPORT; 1787 } 1788 1789 return rtl8365mb_cpu_config(priv); 1790 } 1791 1792 static int rtl8365mb_switch_init(struct realtek_priv *priv) 1793 { 1794 struct rtl8365mb *mb = priv->chip_data; 1795 int ret; 1796 int i; 1797 1798 /* Do any chip-specific init jam before getting to the common stuff */ 1799 if (mb->jam_table) { 1800 for (i = 0; i < mb->jam_size; i++) { 1801 ret = regmap_write(priv->map, mb->jam_table[i].reg, 1802 mb->jam_table[i].val); 1803 if (ret) 1804 return ret; 1805 } 1806 } 1807 1808 /* Common init jam */ 1809 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { 1810 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, 1811 rtl8365mb_init_jam_common[i].val); 1812 if (ret) 1813 return ret; 1814 } 1815 1816 return 0; 1817 } 1818 1819 static int rtl8365mb_reset_chip(struct realtek_priv *priv) 1820 { 1821 u32 val; 1822 1823 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, 1824 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1)); 1825 1826 /* Realtek documentation says the chip needs 1 second to reset. Sleep 1827 * for 100 ms before accessing any registers to prevent ACK timeouts. 1828 */ 1829 msleep(100); 1830 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, 1831 !(val & RTL8365MB_CHIP_RESET_HW_MASK), 1832 20000, 1e6); 1833 } 1834 1835 static int rtl8365mb_setup(struct dsa_switch *ds) 1836 { 1837 struct realtek_priv *priv = ds->priv; 1838 struct rtl8365mb_cpu *cpu; 1839 struct dsa_port *cpu_dp; 1840 struct rtl8365mb *mb; 1841 int ret; 1842 int i; 1843 1844 mb = priv->chip_data; 1845 cpu = &mb->cpu; 1846 1847 ret = rtl8365mb_reset_chip(priv); 1848 if (ret) { 1849 dev_err(priv->dev, "failed to reset chip: %d\n", ret); 1850 goto out_error; 1851 } 1852 1853 /* Configure switch to vendor-defined initial state */ 1854 ret = rtl8365mb_switch_init(priv); 1855 if (ret) { 1856 dev_err(priv->dev, "failed to initialize switch: %d\n", ret); 1857 goto out_error; 1858 } 1859 1860 /* Set up cascading IRQs */ 1861 ret = rtl8365mb_irq_setup(priv); 1862 if (ret == -EPROBE_DEFER) 1863 return ret; 1864 else if (ret) 1865 dev_info(priv->dev, "no interrupt support\n"); 1866 1867 /* Configure CPU tagging */ 1868 dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) { 1869 cpu->mask |= BIT(cpu_dp->index); 1870 1871 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS) 1872 cpu->trap_port = cpu_dp->index; 1873 } 1874 cpu->enable = cpu->mask > 0; 1875 ret = rtl8365mb_cpu_config(priv); 1876 if (ret) 1877 goto out_teardown_irq; 1878 1879 /* Configure ports */ 1880 for (i = 0; i < priv->num_ports; i++) { 1881 struct rtl8365mb_port *p = &mb->ports[i]; 1882 1883 if (dsa_is_unused_port(priv->ds, i)) 1884 continue; 1885 1886 /* Forward only to the CPU */ 1887 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask); 1888 if (ret) 1889 goto out_teardown_irq; 1890 1891 /* Disable learning */ 1892 ret = rtl8365mb_port_set_learning(priv, i, false); 1893 if (ret) 1894 goto out_teardown_irq; 1895 1896 /* Set the initial STP state of all ports to DISABLED, otherwise 1897 * ports will still forward frames to the CPU despite being 1898 * administratively down by default. 1899 */ 1900 rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); 1901 1902 /* Set up per-port private data */ 1903 p->priv = priv; 1904 p->index = i; 1905 } 1906 1907 /* Set maximum packet length to 1536 bytes */ 1908 ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, 1909 RTL8365MB_CFG0_MAX_LEN_MASK, 1910 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536)); 1911 if (ret) 1912 goto out_teardown_irq; 1913 1914 if (priv->setup_interface) { 1915 ret = priv->setup_interface(ds); 1916 if (ret) { 1917 dev_err(priv->dev, "could not set up MDIO bus\n"); 1918 goto out_teardown_irq; 1919 } 1920 } 1921 1922 /* Start statistics counter polling */ 1923 rtl8365mb_stats_setup(priv); 1924 1925 return 0; 1926 1927 out_teardown_irq: 1928 rtl8365mb_irq_teardown(priv); 1929 1930 out_error: 1931 return ret; 1932 } 1933 1934 static void rtl8365mb_teardown(struct dsa_switch *ds) 1935 { 1936 struct realtek_priv *priv = ds->priv; 1937 1938 rtl8365mb_stats_teardown(priv); 1939 rtl8365mb_irq_teardown(priv); 1940 } 1941 1942 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) 1943 { 1944 int ret; 1945 1946 /* For some reason we have to write a magic value to an arbitrary 1947 * register whenever accessing the chip ID/version registers. 1948 */ 1949 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); 1950 if (ret) 1951 return ret; 1952 1953 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); 1954 if (ret) 1955 return ret; 1956 1957 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); 1958 if (ret) 1959 return ret; 1960 1961 /* Reset magic register */ 1962 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); 1963 if (ret) 1964 return ret; 1965 1966 return 0; 1967 } 1968 1969 static int rtl8365mb_detect(struct realtek_priv *priv) 1970 { 1971 struct rtl8365mb *mb = priv->chip_data; 1972 u32 chip_id; 1973 u32 chip_ver; 1974 int ret; 1975 1976 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); 1977 if (ret) { 1978 dev_err(priv->dev, "failed to read chip id and version: %d\n", 1979 ret); 1980 return ret; 1981 } 1982 1983 switch (chip_id) { 1984 case RTL8365MB_CHIP_ID_8365MB_VC: 1985 switch (chip_ver) { 1986 case RTL8365MB_CHIP_VER_8365MB_VC: 1987 dev_info(priv->dev, 1988 "found an RTL8365MB-VC switch (ver=0x%04x)\n", 1989 chip_ver); 1990 break; 1991 case RTL8365MB_CHIP_VER_8367RB: 1992 dev_info(priv->dev, 1993 "found an RTL8367RB-VB switch (ver=0x%04x)\n", 1994 chip_ver); 1995 break; 1996 case RTL8365MB_CHIP_VER_8367S: 1997 dev_info(priv->dev, 1998 "found an RTL8367S switch (ver=0x%04x)\n", 1999 chip_ver); 2000 break; 2001 default: 2002 dev_err(priv->dev, "unrecognized switch version (ver=0x%04x)", 2003 chip_ver); 2004 return -ENODEV; 2005 } 2006 2007 priv->num_ports = RTL8365MB_MAX_NUM_PORTS; 2008 2009 mb->priv = priv; 2010 mb->chip_id = chip_id; 2011 mb->chip_ver = chip_ver; 2012 mb->port_mask = GENMASK(priv->num_ports - 1, 0); 2013 mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX; 2014 mb->jam_table = rtl8365mb_init_jam_8365mb_vc; 2015 mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); 2016 2017 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; 2018 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; 2019 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; 2020 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; 2021 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; 2022 2023 break; 2024 default: 2025 dev_err(priv->dev, 2026 "found an unknown Realtek switch (id=0x%04x, ver=0x%04x)\n", 2027 chip_id, chip_ver); 2028 return -ENODEV; 2029 } 2030 2031 return 0; 2032 } 2033 2034 static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = { 2035 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2036 .change_tag_protocol = rtl8365mb_change_tag_protocol, 2037 .setup = rtl8365mb_setup, 2038 .teardown = rtl8365mb_teardown, 2039 .phylink_get_caps = rtl8365mb_phylink_get_caps, 2040 .phylink_mac_config = rtl8365mb_phylink_mac_config, 2041 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, 2042 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, 2043 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2044 .get_strings = rtl8365mb_get_strings, 2045 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2046 .get_sset_count = rtl8365mb_get_sset_count, 2047 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2048 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2049 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2050 .get_stats64 = rtl8365mb_get_stats64, 2051 }; 2052 2053 static const struct dsa_switch_ops rtl8365mb_switch_ops_mdio = { 2054 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2055 .change_tag_protocol = rtl8365mb_change_tag_protocol, 2056 .setup = rtl8365mb_setup, 2057 .teardown = rtl8365mb_teardown, 2058 .phylink_get_caps = rtl8365mb_phylink_get_caps, 2059 .phylink_mac_config = rtl8365mb_phylink_mac_config, 2060 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, 2061 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, 2062 .phy_read = rtl8365mb_dsa_phy_read, 2063 .phy_write = rtl8365mb_dsa_phy_write, 2064 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2065 .get_strings = rtl8365mb_get_strings, 2066 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2067 .get_sset_count = rtl8365mb_get_sset_count, 2068 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2069 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2070 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2071 .get_stats64 = rtl8365mb_get_stats64, 2072 }; 2073 2074 static const struct realtek_ops rtl8365mb_ops = { 2075 .detect = rtl8365mb_detect, 2076 .phy_read = rtl8365mb_phy_read, 2077 .phy_write = rtl8365mb_phy_write, 2078 }; 2079 2080 const struct realtek_variant rtl8365mb_variant = { 2081 .ds_ops_smi = &rtl8365mb_switch_ops_smi, 2082 .ds_ops_mdio = &rtl8365mb_switch_ops_mdio, 2083 .ops = &rtl8365mb_ops, 2084 .clk_delay = 10, 2085 .cmd_read = 0xb9, 2086 .cmd_write = 0xb8, 2087 .chip_data_sz = sizeof(struct rtl8365mb), 2088 }; 2089 EXPORT_SYMBOL_GPL(rtl8365mb_variant); 2090 2091 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>"); 2092 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch"); 2093 MODULE_LICENSE("GPL"); 2094